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DMA receive transaction timed out #72
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Given that the AXI DMA test driver is also failing, I would guess that the issue lies in your custom HLS IP. It could also be an issue with the block diagram connections or the device tree configuration, but those both look good to me. Also, I'm guessing the reason that it works fine in the baremetal application is that you're polling the AXI DMA IP, rather than relying on the interrupt, so the behavior being tested is different. Without knowing any specifics about your custom IP, it's hard to say exactly what the issue is. However, the most likely culprit is that you're not correctly asserting the |
Hi Brandon, First off, thank you for taking the time to answer. I have now checked all of your suggestions and unfortunately none of them applies. Specifically, the baremetal application transfers packets in interrupt mode with the AXI DMA core configured in SG Mode. To the best of my understanding, I am simply asserting the TLAST signal to 1 at the last 64-bit packet of the IP output stream (see attached HLS simulation screenshot) unless I am missing something here and there is more to it. Please let me know if Ι can provide more design resources to help you identify the problem. |
Yeah all of your signals look fine, and the reset of your configuration is correct. The only other guess I have would be the Linux version you're using, but since you're using PetaLinux, this shouldn't be a problem. |
Hi ,DrFuzzy! |
I have the same problem but my SG is not enabled , the IRQ is mapped but never triggers. I changed a bit the device tree based on the automatic device tree created by petalinux : |
Hi @DrFuzzy I had the same issues wiith the axidmatest.ko driver and after lot's of effort I found these settings worked for me inside vivado with a simple loopback. Summary of axidma settings (axi_dma_0) Enable scatter Gather Engine |
Hi @DrFuzzy
I had the same issues AXI DMA core configured in SG Mode. root@xdmatest:/usr/bin# ./axidma-benchmark Using transmit channel 0 and receive channel 1. |
I had the same issues AXI DMA core configured in non SG Mode, and the tlast is just the same with the picture. Have you solved this problem? |
你发给我的邮件已收到! ——王振华
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Hi, this issue is a about mapping between devicetree node (dma) property and zynq interrupt number (IRQ_F2P[15:0]) for example when you connect mm2s_introut -> IRQ_F2P[0] and s2mm_introut -> IRQ_F2P[1] your devcietree node property should be like this: IRQ_F2P[0] = 61 --> 61-32 = 29 = 0x1d so:
}; |
When running axidma_transfer (or the benchmark example) on PetaLinux 2017.2, I am getting "axidma: axidma_dma.c: axidma_start_transfer: 305: DMA receive transaction timed out".
My Vivado 2017.2 design (SG enabled) uses a custom HLS IP and has been verified with a baremetal application already.
Below is the Vivado block diagram:
with the following AXI DMA settings:
the system-user.dtsi:
and the output dmesg after running axidma_transfer:
and again same story with AXI DMA Test driver:
Do you have any idea what might be wrong with this setup or any suggestions to try?
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