From c1565eeb7ec28b79a4a8b43e6c42c7a61a1eda79 Mon Sep 17 00:00:00 2001 From: simon1hofmann <119581649+simon1hofmann@users.noreply.github.com> Date: Fri, 17 May 2024 14:49:00 +0200 Subject: [PATCH] Update README.md --- README.md | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/README.md b/README.md index 6dccfeafe..c7a4ecd66 100644 --- a/README.md +++ b/README.md @@ -16,7 +16,7 @@

- +

@@ -76,7 +76,7 @@ cli/fiction > Here is an example of running *fiction* to perform a full physical design flow on a QCA circuit layout that can > afterward be simulated in QCADesigner: -![CLI example](docs/_static/fiction_cli_example.gif) +![CLI example](https://raw.githubusercontent.com/cda-tum/fiction/main/docs/_static/fiction_cli_example.gif) ### The Header-only Library @@ -124,7 +124,7 @@ Additionally, output formats for external physical simulator engines are also su ### Quantum-dot Cellular Automata (QCA) -QCA cells +QCA cells Gate libraries: @@ -142,7 +142,7 @@ QCA-STACK format, and to Sophia Kuhn for implementing the SVG writer! ### in-plane Nanomagnet Logic (iNML) -iNML cells +iNML cells Gate libraries: @@ -157,7 +157,7 @@ Many thanks to Umberto Garlando, Fabrizio Riente, and Giuliana Beretta for their ### Silicon Dangling Bonds (SiDBs) -SiDB cells +SiDB cells Gate libraries: @@ -188,7 +188,7 @@ For automatic FCN layout obtainment, *fiction* provides algorithms that receive [mockturtle logic networks](https://mockturtle.readthedocs.io/en/latest/implementations.html) as input specification and output placed, routed, and clocked generic FCN circuits. -QCA Layout +QCA Layout Among these algorithms are @@ -219,7 +219,7 @@ using ### Physical Simulation -SiDB simulation result +SiDB simulation result When a layout is compiled to the cell level via the application of a technology-dependent gate library, it can be simulated using a physical model. Currently, the following simulation algorithms are implemented in *fiction*: @@ -244,21 +244,21 @@ Built-in schemes are | [Columnar](https://ieeexplore.ieee.org/document/573740) | [Row](https://ieeexplore.ieee.org/document/573740) | [2DDWave](https://ieeexplore.ieee.org/document/1717097) | |:------------------------------------------------------------------:|:--------------------------------------------------------:|:----------------------------------------------------------------:| -| Columnar | Row | 2DDWave | +| Columnar | Row | 2DDWave | | [USE](https://ieeexplore.ieee.org/document/7219390) | [RES](https://www.tandfonline.com/doi/abs/10.1080/21681724.2019.1570551) | [ESR](https://link.springer.com/content/pdf/10.1007/s10470-020-01760-4.pdf) | |:--------------------------------------------------------:|:------------------------------------------------------------------------:|:---------------------------------------------------------------------------:| -| USE | RES | ESR | +| USE | RES | ESR | | [CFE](https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-cds.2019.0096) | [Ripple](https://scholarworks.rit.edu/cgi/viewcontent.cgi?referer=&httpsredir=1&article=8266&context=theses) | [BANCS](https://ieeexplore.ieee.org/document/8533251) | |:--------------------------------------------------------------------------------:|:------------------------------------------------------------------------------------------------------------:|:------------------------------------------------------------:| -| CFE | Ripple | BANCS | +| CFE | Ripple | BANCS | plus the mentioned irregular open clocking that works via a clock map instead of a regular extrapolated cutout. ## Wire Crossings -Second layer crossing +Second layer crossing With many FCN technologies considered planar, wire crossings should be minimized if possible. However, there are some options in QCA where, using a second layer, crossings over short distances and co-planar rotated cells become possible. @@ -271,7 +271,7 @@ Wires are only allowed to cross other wires! Wires crossing gates is considered ## Gate Pins vs. Designated I/Os -Input pin and cell output +Input pin and cell output In the literature, both are seen: having input cells (pins) directly located in the gate structure or using designated I/O elements that are located outside of gates. This distinction only makes sense on the gate level and *fiction* @@ -279,7 +279,7 @@ supports both approaches and offers usage in the implemented physical design alg ## Multi Wires -Multi wires +Multi wires Gate-level abstraction has its limits. Often, chip area is wasted when only using a single wire per tile. In *fiction*, cell-level layouts allow for precise control over cell placement and can, thus, also create multiple wire segments per @@ -288,7 +288,7 @@ functionality. ## Synchronization Elements -Synchronization element +Synchronization element A technology extension proposes to utilize the external clock signal generator in an unconventional way: by creating further asymmetric clock signals with extended *Hold* phases that are assigned to specific wire