diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv index 5bedde743..8b8d0bb3e 100755 --- a/src/integration/rtl/caliptra_top.sv +++ b/src/integration/rtl/caliptra_top.sv @@ -44,18 +44,9 @@ module caliptra_top output logic jtag_tdo, // JTAG TDO output logic jtag_tdoEn, // JTAG TDO enable - //APB Interface - input logic [`CALIPTRA_APB_ADDR_WIDTH-1:0] PADDR, - input logic [2:0] PPROT, - input logic PSEL, - input logic PENABLE, - input logic PWRITE, - input logic [`CALIPTRA_APB_DATA_WIDTH-1:0] PWDATA, - input logic [`CALIPTRA_APB_USER_WIDTH-1:0] PAUSER, - - output logic PREADY, - output logic PSLVERR, - output logic [`CALIPTRA_APB_DATA_WIDTH-1:0] PRDATA, + //SoC AXI Interface + axi_if.w_sub s_axi_w_if, + axi_if.r_sub s_axi_r_if, //QSPI Interface output logic qspi_clk_o, @@ -1171,9 +1162,10 @@ uart #( soc_ifc_top #( .AHB_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)), .AHB_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE), - .APB_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)), - .APB_DATA_WIDTH(`CALIPTRA_APB_DATA_WIDTH), - .APB_USER_WIDTH(`CALIPTRA_APB_USER_WIDTH) + .AXI_ADDR_WIDTH(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)), + .AXI_DATA_WIDTH(`CALIPTRA_AXI_DATA_WIDTH), + .AXI_ID_WIDTH (`CALIPTRA_AXI_ID_WIDTH ), + .AXI_USER_WIDTH(`CALIPTRA_AXI_USER_WIDTH) ) soc_ifc_top1 ( @@ -1203,16 +1195,10 @@ soc_ifc_top1 // RV ECC Status Interface .rv_ecc_sts(rv_ecc_sts), - //APB Interface with SoC - .paddr_i(PADDR[`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)-1:0]), - .psel_i(PSEL), - .penable_i(PENABLE), - .pwrite_i(PWRITE), - .pwdata_i(PWDATA), - .pauser_i(PAUSER), - .pready_o(PREADY), - .prdata_o(PRDATA), - .pslverr_o(PSLVERR), + //SoC AXI Interface + .s_axi_w_if(s_axi_w_if), + .s_axi_r_if(s_axi_r_if), + //AHB Interface with uC .haddr_i (responder_inst[`CALIPTRA_SLAVE_SEL_SOC_IFC].haddr[`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)-1:0]), .hwdata_i (responder_inst[`CALIPTRA_SLAVE_SEL_SOC_IFC].hwdata), @@ -1321,17 +1307,4 @@ endgenerate `CALIPTRA_ASSERT_KNOWN(AHB_MASTER_HRDATA_X, initiator_inst.hready ? initiator_inst.hrdata : '0, clk, !cptra_noncore_rst_b) `CALIPTRA_ASSERT_NEVER(AHB_MASTER_HTRANS_BUSY, initiator_inst.htrans == 2'b01, clk, !cptra_noncore_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PADDR_X, PADDR, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PWDATA_X, PWDATA, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PWRITE_X, PWRITE, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PREADY_X, PREADY, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PENABLE_X, PENABLE, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PSEL_X, PSEL, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PPROT_X, PPROT, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PAUSER_X, PAUSER, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PSLVERR_X, PSLVERR, clk, !cptra_rst_b) -`CALIPTRA_ASSERT_KNOWN(APB_MASTER_PRDATA_X, PREADY ? PRDATA : '0, clk, !cptra_rst_b) - -`CALIPTRA_ASSERT_NEVER(APB_MASTER_PPROT_ACTIVE, PPROT !== 3'b000, clk, !cptra_rst_b) - endmodule diff --git a/src/integration/rtl/config_defines.svh b/src/integration/rtl/config_defines.svh index 1a52b4002..21a904129 100755 --- a/src/integration/rtl/config_defines.svh +++ b/src/integration/rtl/config_defines.svh @@ -22,9 +22,10 @@ `define CALIPTRA_AHB_MASTERS_NUM 4'd1 // Number of masters AHB `define CALIPTRA_AHB_HADDR_SIZE 32 // bit-width AHB address haddr `define CALIPTRA_AHB_HDATA_SIZE 64 // bit-width AHB data - `define CALIPTRA_APB_ADDR_WIDTH 32 // bit-width APB address - `define CALIPTRA_APB_DATA_WIDTH 32 // bit-width APB data - `define CALIPTRA_APB_USER_WIDTH 32 // bit-width APB PAUSER field + `define CALIPTRA_AXI_ADDR_WIDTH 32 // bit-width AXI address + `define CALIPTRA_AXI_DATA_WIDTH 32 // bit-width AXI data + `define CALIPTRA_AXI_USER_WIDTH 32 // bit-width AXI USER field + `define CALIPTRA_AXI_ID_WIDTH 5 // bit-width AXI ID field `define CALIPTRA_QSPI_CS_WIDTH 2 `define CALIPTRA_QSPI_IO_WIDTH 4 `define CALIPTRA_SOC_SEC_STATE_WIDTH 3 diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv index a2d4adbed..11b6c125e 100644 --- a/src/soc_ifc/rtl/mbox.sv +++ b/src/soc_ifc/rtl/mbox.sv @@ -53,7 +53,7 @@ module mbox output logic soc_mbox_data_avail, output logic soc_req_mbox_lock, output mbox_protocol_error_t mbox_protocol_error, - output logic mbox_inv_pauser_axs, + output logic mbox_inv_axi_id_axs, //DMI reg access input logic dmi_inc_rdptr, @@ -146,10 +146,10 @@ assign mbox_error = read_error | write_error; //Determine if this is a valid request from the requester side //1) uC requests are valid if uc has lock -//2) SoC requests are valid if soc has lock and it's the user that locked it +//2) SoC requests are valid if soc has lock and it's the AXI ID that locked it always_comb valid_requester = hwif_out.mbox_lock.lock.value & ((~req_data.soc_req & (~soc_has_lock || (mbox_fsm_ps == MBOX_EXECUTE_UC))) | - ( req_data.soc_req & soc_has_lock & (req_data.user == hwif_out.mbox_user.user.value))); + ( req_data.soc_req & soc_has_lock & (req_data.id == hwif_out.mbox_id.id.value))); //Determine if this is a valid request from the receiver side always_comb valid_receiver = hwif_out.mbox_lock.lock.value & @@ -162,7 +162,7 @@ always_comb valid_receiver = hwif_out.mbox_lock.lock.value & (~soc_has_lock & (mbox_fsm_ps == MBOX_EXECUTE_UC))))); //We want to mask read data when -//Invalid user is trying to access the mailbox data +//Invalid ID is trying to access the mailbox data always_comb mask_rdata = hwif_out.mbox_dataout.dataout.swacc & ~valid_receiver; //move from idle to rdy for command when lock is acquired @@ -191,7 +191,7 @@ always_comb arc_FORCE_MBOX_UNLOCK = hwif_out.mbox_unlock.unlock.value; // Any register write or read by an INVALID agent results in the access // being silently dropped. // Assumption: uC (ROM, FMC, RT) will never make an invalid request. -// NOTE: Any APB agent can trigger the error at any point during a uC->SOC flow +// NOTE: Any AXI agent can trigger the error at any point during a uC->SOC flow // by writing to mbox_status (since it's a valid_receiver). // FIXED! valid_receiver is restricted by FSM state now. always_comb arc_MBOX_RDY_FOR_CMD_MBOX_ERROR = (mbox_fsm_ps == MBOX_RDY_FOR_CMD) && @@ -340,7 +340,7 @@ always_comb begin : mbox_fsm_combo end end //uC set execute, data is for the SoC - //If we're here, restrict reading to the user that requested the data + //If we're here, restrict reading to the AXI ID that requested the data //Only SoC can read from mbox //Only SoC can write to datain here to respond to uC MBOX_EXECUTE_SOC: begin @@ -379,10 +379,10 @@ always_comb begin : mbox_fsm_combo endcase end -// Any ol' PAUSER is fine for reg-reads (except dataout) -// NOTE: This only captures accesses by APB agents that are valid, but do not +// Any ol' AXI_ID is fine for reg-reads (except dataout) +// NOTE: This only captures accesses by AXI agents that are valid, but do not // have lock. Invalid agent accesses are blocked by arbiter. -assign mbox_inv_pauser_axs = req_dv && req_data.soc_req && !req_hold && +assign mbox_inv_axi_id_axs = req_dv && req_data.soc_req && !req_hold && !valid_requester && !valid_receiver && (req_data.write || hwif_out.mbox_dataout.dataout.swacc); @@ -519,18 +519,18 @@ always_comb mbox_rd_full_nxt = rst_mbox_rdptr ? '0 : inc_rdptr & (mbox_rdptr == always_comb soc_req_mbox_lock = hwif_out.mbox_lock.lock.value & ~soc_has_lock & hwif_out.mbox_lock.lock.swmod & req_data.soc_req; always_comb hwif_in.cptra_rst_b = rst_b; -always_comb hwif_in.mbox_user.user.next = req_data.user; +always_comb hwif_in.mbox_id.id.next = req_data.id; always_comb hwif_in.mbox_status.mbox_fsm_ps.next = mbox_fsm_ps; always_comb hwif_in.soc_req = req_data.soc_req; -//check the requesting user: +//check the requesting ID: //don't update mailbox data if lock hasn't been acquired //if uc has the lock, check that this request is from uc -//if soc has the lock, check that this request is from soc and user attributes match +//if soc has the lock, check that this request is from soc and ID attributes match always_comb hwif_in.valid_requester = valid_requester; always_comb hwif_in.valid_receiver = valid_receiver; -//indicate that requesting user is setting the lock +//indicate that requesting ID is setting the lock always_comb hwif_in.lock_set = arc_MBOX_IDLE_MBOX_RDY_FOR_CMD; //update dataout diff --git a/src/soc_ifc/rtl/mbox_csr.rdl b/src/soc_ifc/rtl/mbox_csr.rdl index 8a67121be..b6a710714 100644 --- a/src/soc_ifc/rtl/mbox_csr.rdl +++ b/src/soc_ifc/rtl/mbox_csr.rdl @@ -39,15 +39,15 @@ addrmap mbox_csr { field {rset; sw=r; hw=r; hwclr=true; precedence=hw; swmod=true;} lock=0; } mbox_lock; - // user register - // store user from interface when setting lock + // ID register + // store AXI ID from interface when setting lock reg { - name="Mailbox User"; - desc="Stores the user that locked the mailbox + name="Mailbox ID"; + desc="Stores the AXI ID that locked the mailbox [br]Caliptra Access: RO [br]SOC Access: RO"; - field {sw=r; hw=rw; we=lock_set;} user[32]=0; - } mbox_user; + field {sw=r; hw=rw; we=lock_set;} id[32]=0; + } mbox_id; reg { name="Mailbox Command"; diff --git a/src/soc_ifc/rtl/mbox_csr.sv b/src/soc_ifc/rtl/mbox_csr.sv index c58f79ea2..d99ba04d7 100644 --- a/src/soc_ifc/rtl/mbox_csr.sv +++ b/src/soc_ifc/rtl/mbox_csr.sv @@ -67,7 +67,7 @@ module mbox_csr ( //-------------------------------------------------------------------------- typedef struct packed{ logic mbox_lock; - logic mbox_user; + logic mbox_id; logic mbox_cmd; logic mbox_dlen; logic mbox_datain; @@ -84,7 +84,7 @@ module mbox_csr ( always_comb begin decoded_reg_strb.mbox_lock = cpuif_req_masked & (cpuif_addr == 6'h0); - decoded_reg_strb.mbox_user = cpuif_req_masked & (cpuif_addr == 6'h4); + decoded_reg_strb.mbox_id = cpuif_req_masked & (cpuif_addr == 6'h4); decoded_reg_strb.mbox_cmd = cpuif_req_masked & (cpuif_addr == 6'h8); decoded_reg_strb.mbox_dlen = cpuif_req_masked & (cpuif_addr == 6'hc); decoded_reg_strb.mbox_datain = cpuif_req_masked & (cpuif_addr == 6'h10); @@ -114,8 +114,8 @@ module mbox_csr ( struct packed{ logic [31:0] next; logic load_next; - } user; - } mbox_user; + } id; + } mbox_id; struct packed{ struct packed{ logic [31:0] next; @@ -190,8 +190,8 @@ module mbox_csr ( struct packed{ struct packed{ logic [31:0] value; - } user; - } mbox_user; + } id; + } mbox_id; struct packed{ struct packed{ logic [31:0] value; @@ -270,27 +270,27 @@ module mbox_csr ( end assign hwif_out.mbox_lock.lock.value = field_storage.mbox_lock.lock.value; assign hwif_out.mbox_lock.lock.swmod = decoded_reg_strb.mbox_lock && !decoded_req_is_wr; - // Field: mbox_csr.mbox_user.user + // Field: mbox_csr.mbox_id.id always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.mbox_user.user.value; + next_c = field_storage.mbox_id.id.value; load_next_c = '0; if(hwif_in.lock_set) begin // HW Write - we - next_c = hwif_in.mbox_user.user.next; + next_c = hwif_in.mbox_id.id.next; load_next_c = '1; end - field_combo.mbox_user.user.next = next_c; - field_combo.mbox_user.user.load_next = load_next_c; + field_combo.mbox_id.id.next = next_c; + field_combo.mbox_id.id.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_user.user.value <= 32'h0; - end else if(field_combo.mbox_user.user.load_next) begin - field_storage.mbox_user.user.value <= field_combo.mbox_user.user.next; + field_storage.mbox_id.id.value <= 32'h0; + end else if(field_combo.mbox_id.id.load_next) begin + field_storage.mbox_id.id.value <= field_combo.mbox_id.id.next; end end - assign hwif_out.mbox_user.user.value = field_storage.mbox_user.user.value; + assign hwif_out.mbox_id.id.value = field_storage.mbox_id.id.value; // Field: mbox_csr.mbox_cmd.command always_comb begin automatic logic [31:0] next_c; @@ -585,7 +585,7 @@ module mbox_csr ( logic [9-1:0][31:0] readback_array; assign readback_array[0][0:0] = (decoded_reg_strb.mbox_lock && !decoded_req_is_wr) ? field_storage.mbox_lock.lock.value : '0; assign readback_array[0][31:1] = '0; - assign readback_array[1][31:0] = (decoded_reg_strb.mbox_user && !decoded_req_is_wr) ? field_storage.mbox_user.user.value : '0; + assign readback_array[1][31:0] = (decoded_reg_strb.mbox_id && !decoded_req_is_wr) ? field_storage.mbox_id.id.value : '0; assign readback_array[2][31:0] = (decoded_reg_strb.mbox_cmd && !decoded_req_is_wr) ? field_storage.mbox_cmd.command.value : '0; assign readback_array[3][31:0] = (decoded_reg_strb.mbox_dlen && !decoded_req_is_wr) ? field_storage.mbox_dlen.length.value : '0; assign readback_array[4][31:0] = (decoded_reg_strb.mbox_datain && !decoded_req_is_wr) ? field_storage.mbox_datain.datain.value : '0; diff --git a/src/soc_ifc/rtl/mbox_csr_covergroups.svh b/src/soc_ifc/rtl/mbox_csr_covergroups.svh index 3664e1fc3..7efb5ce3c 100644 --- a/src/soc_ifc/rtl/mbox_csr_covergroups.svh +++ b/src/soc_ifc/rtl/mbox_csr_covergroups.svh @@ -41,8 +41,8 @@ endgroup - /*----------------------- MBOX_CSR__MBOX_USER COVERGROUPS -----------------------*/ - covergroup mbox_csr__mbox_user_bit_cg with function sample(input bit reg_bit); + /*----------------------- MBOX_CSR__MBOX_ID COVERGROUPS -----------------------*/ + covergroup mbox_csr__mbox_id_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -53,11 +53,11 @@ } endgroup - covergroup mbox_csr__mbox_user_fld_cg with function sample( - input bit [32-1:0] user + covergroup mbox_csr__mbox_id_fld_cg with function sample( + input bit [32-1:0] id ); option.per_instance = 1; - user_cp : coverpoint user { + id_cp : coverpoint id { bins zero_val = {32'h0}; bins rand_val[64] = {[1:32'hFFFF_FFFE]}; bins ones_val = {{32{1'b1}}}; @@ -221,7 +221,8 @@ input bit [1-1:0] ecc_single_error, input bit [1-1:0] ecc_double_error, input bit [3-1:0] mbox_fsm_ps, - input bit [1-1:0] soc_has_lock + input bit [1-1:0] soc_has_lock, + input bit [15-1:0] mbox_rdptr ); option.per_instance = 1; status_cp : coverpoint status; @@ -278,6 +279,7 @@ // illegal_bins TRANSITION_ERROR_EXECUTE_SOC = (mbox_fsm_state_e'(MBOX_ERROR) => mbox_fsm_state_e'(MBOX_EXECUTE_SOC)); } soc_has_lock_cp : coverpoint soc_has_lock; + mbox_rdptr_cp : coverpoint mbox_rdptr; status_edge_cp : coverpoint status { bins rise = (0 => 1); bins fall = (1 => 0); diff --git a/src/soc_ifc/rtl/mbox_csr_pkg.sv b/src/soc_ifc/rtl/mbox_csr_pkg.sv index 39f775c03..13341ef52 100644 --- a/src/soc_ifc/rtl/mbox_csr_pkg.sv +++ b/src/soc_ifc/rtl/mbox_csr_pkg.sv @@ -16,11 +16,11 @@ package mbox_csr_pkg; typedef struct packed{ logic [31:0] next; - } mbox_csr__mbox_user__user__in_t; + } mbox_csr__mbox_id__id__in_t; typedef struct packed{ - mbox_csr__mbox_user__user__in_t user; - } mbox_csr__mbox_user__in_t; + mbox_csr__mbox_id__id__in_t id; + } mbox_csr__mbox_id__in_t; typedef struct packed{ logic [31:0] next; @@ -80,7 +80,7 @@ package mbox_csr_pkg; logic valid_requester; logic valid_receiver; mbox_csr__mbox_lock__in_t mbox_lock; - mbox_csr__mbox_user__in_t mbox_user; + mbox_csr__mbox_id__in_t mbox_id; mbox_csr__mbox_dataout__in_t mbox_dataout; mbox_csr__mbox_execute__in_t mbox_execute; mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__in_t mbox_status; @@ -97,11 +97,11 @@ package mbox_csr_pkg; typedef struct packed{ logic [31:0] value; - } mbox_csr__mbox_user__user__out_t; + } mbox_csr__mbox_id__id__out_t; typedef struct packed{ - mbox_csr__mbox_user__user__out_t user; - } mbox_csr__mbox_user__out_t; + mbox_csr__mbox_id__id__out_t id; + } mbox_csr__mbox_id__out_t; typedef struct packed{ logic swmod; @@ -190,7 +190,7 @@ package mbox_csr_pkg; typedef struct packed{ mbox_csr__mbox_lock__out_t mbox_lock; - mbox_csr__mbox_user__out_t mbox_user; + mbox_csr__mbox_id__out_t mbox_id; mbox_csr__mbox_cmd__out_t mbox_cmd; mbox_csr__mbox_dlen__out_t mbox_dlen; mbox_csr__mbox_datain__out_t mbox_datain; diff --git a/src/soc_ifc/rtl/mbox_csr_sample.svh b/src/soc_ifc/rtl/mbox_csr_sample.svh index 29ef7be05..b061ddb12 100644 --- a/src/soc_ifc/rtl/mbox_csr_sample.svh +++ b/src/soc_ifc/rtl/mbox_csr_sample.svh @@ -40,8 +40,8 @@ end endfunction - /*----------------------- MBOX_CSR__MBOX_USER SAMPLE FUNCTIONS -----------------------*/ - function void mbox_csr__mbox_user::sample(uvm_reg_data_t data, + /*----------------------- MBOX_CSR__MBOX_ID SAMPLE FUNCTIONS -----------------------*/ + function void mbox_csr__mbox_id::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -49,19 +49,19 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(user_bit_cg[bt]) this.user_bit_cg[bt].sample(data[0 + bt]); + foreach(id_bit_cg[bt]) this.id_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*user*/ ); + this.fld_cg.sample( data[31:0]/*id*/ ); end endfunction - function void mbox_csr__mbox_user::sample_values(); + function void mbox_csr__mbox_id::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(user_bit_cg[bt]) this.user_bit_cg[bt].sample(user.get_mirrored_value() >> bt); + foreach(id_bit_cg[bt]) this.id_bit_cg[bt].sample(id.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( user.get_mirrored_value() ); + this.fld_cg.sample( id.get_mirrored_value() ); end endfunction @@ -204,9 +204,10 @@ foreach(ecc_double_error_bit_cg[bt]) this.ecc_double_error_bit_cg[bt].sample(data[5 + bt]); foreach(mbox_fsm_ps_bit_cg[bt]) this.mbox_fsm_ps_bit_cg[bt].sample(data[6 + bt]); foreach(soc_has_lock_bit_cg[bt]) this.soc_has_lock_bit_cg[bt].sample(data[9 + bt]); + foreach(mbox_rdptr_bit_cg[bt]) this.mbox_rdptr_bit_cg[bt].sample(data[10 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[3:0]/*status*/ , data[4:4]/*ecc_single_error*/ , data[5:5]/*ecc_double_error*/ , data[8:6]/*mbox_fsm_ps*/ , data[9:9]/*soc_has_lock*/ ); + this.fld_cg.sample( data[3:0]/*status*/ , data[4:4]/*ecc_single_error*/ , data[5:5]/*ecc_double_error*/ , data[8:6]/*mbox_fsm_ps*/ , data[9:9]/*soc_has_lock*/ , data[24:10]/*mbox_rdptr*/ ); end endfunction @@ -217,9 +218,10 @@ foreach(ecc_double_error_bit_cg[bt]) this.ecc_double_error_bit_cg[bt].sample(ecc_double_error.get_mirrored_value() >> bt); foreach(mbox_fsm_ps_bit_cg[bt]) this.mbox_fsm_ps_bit_cg[bt].sample(mbox_fsm_ps.get_mirrored_value() >> bt); foreach(soc_has_lock_bit_cg[bt]) this.soc_has_lock_bit_cg[bt].sample(soc_has_lock.get_mirrored_value() >> bt); + foreach(mbox_rdptr_bit_cg[bt]) this.mbox_rdptr_bit_cg[bt].sample(mbox_rdptr.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( status.get_mirrored_value() , ecc_single_error.get_mirrored_value() , ecc_double_error.get_mirrored_value() , mbox_fsm_ps.get_mirrored_value() , soc_has_lock.get_mirrored_value() ); + this.fld_cg.sample( status.get_mirrored_value() , ecc_single_error.get_mirrored_value() , ecc_double_error.get_mirrored_value() , mbox_fsm_ps.get_mirrored_value() , soc_has_lock.get_mirrored_value() , mbox_rdptr.get_mirrored_value() ); end endfunction diff --git a/src/soc_ifc/rtl/mbox_csr_uvm.sv b/src/soc_ifc/rtl/mbox_csr_uvm.sv index 760853a1a..ee50564b5 100644 --- a/src/soc_ifc/rtl/mbox_csr_uvm.sv +++ b/src/soc_ifc/rtl/mbox_csr_uvm.sv @@ -34,17 +34,17 @@ package mbox_csr_uvm; endfunction : build endclass : mbox_csr__mbox_lock - // Reg - mbox_csr::mbox_user - class mbox_csr__mbox_user extends uvm_reg; + // Reg - mbox_csr::mbox_id + class mbox_csr__mbox_id extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - mbox_csr__mbox_user_bit_cg user_bit_cg[32]; - mbox_csr__mbox_user_fld_cg fld_cg; - rand uvm_reg_field user; + mbox_csr__mbox_id_bit_cg id_bit_cg[32]; + mbox_csr__mbox_id_fld_cg fld_cg; + rand uvm_reg_field id; - function new(string name = "mbox_csr__mbox_user"); + function new(string name = "mbox_csr__mbox_id"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -54,15 +54,15 @@ package mbox_csr_uvm; uvm_reg_map map); virtual function void build(); - this.user = new("user"); - this.user.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0); + this.id = new("id"); + this.id.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(user_bit_cg[bt]) user_bit_cg[bt] = new(); + foreach(id_bit_cg[bt]) id_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : mbox_csr__mbox_user + endclass : mbox_csr__mbox_id // Reg - mbox_csr::mbox_cmd class mbox_csr__mbox_cmd extends uvm_reg; @@ -302,7 +302,7 @@ package mbox_csr_uvm; // Addrmap - mbox_csr class mbox_csr extends uvm_reg_block; rand mbox_csr__mbox_lock mbox_lock; - rand mbox_csr__mbox_user mbox_user; + rand mbox_csr__mbox_id mbox_id; rand mbox_csr__mbox_cmd mbox_cmd; rand mbox_csr__mbox_dlen mbox_dlen; rand mbox_csr__mbox_datain mbox_datain; @@ -322,11 +322,11 @@ package mbox_csr_uvm; this.mbox_lock.build(); this.default_map.add_reg(this.mbox_lock, 'h0); - this.mbox_user = new("mbox_user"); - this.mbox_user.configure(this); + this.mbox_id = new("mbox_id"); + this.mbox_id.configure(this); - this.mbox_user.build(); - this.default_map.add_reg(this.mbox_user, 'h4); + this.mbox_id.build(); + this.default_map.add_reg(this.mbox_id, 'h4); this.mbox_cmd = new("mbox_cmd"); this.mbox_cmd.configure(this); diff --git a/src/soc_ifc/rtl/sha512_acc_csr.sv b/src/soc_ifc/rtl/sha512_acc_csr.sv index ba52bf8ec..78bfe43fa 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr.sv +++ b/src/soc_ifc/rtl/sha512_acc_csr.sv @@ -67,7 +67,7 @@ module sha512_acc_csr ( //-------------------------------------------------------------------------- typedef struct packed{ logic LOCK; - logic USER; + logic ID; logic MODE; logic START_ADDRESS; logic DLEN; @@ -106,7 +106,7 @@ module sha512_acc_csr ( always_comb begin decoded_reg_strb.LOCK = cpuif_req_masked & (cpuif_addr == 12'h0); - decoded_reg_strb.USER = cpuif_req_masked & (cpuif_addr == 12'h4); + decoded_reg_strb.ID = cpuif_req_masked & (cpuif_addr == 12'h4); decoded_reg_strb.MODE = cpuif_req_masked & (cpuif_addr == 12'h8); decoded_reg_strb.START_ADDRESS = cpuif_req_masked & (cpuif_addr == 12'hc); decoded_reg_strb.DLEN = cpuif_req_masked & (cpuif_addr == 12'h10); @@ -158,8 +158,8 @@ module sha512_acc_csr ( struct packed{ logic [31:0] next; logic load_next; - } USER; - } USER; + } ID; + } ID; struct packed{ struct packed{ logic [1:0] next; @@ -404,8 +404,8 @@ module sha512_acc_csr ( struct packed{ struct packed{ logic [31:0] value; - } USER; - } USER; + } ID; + } ID; struct packed{ struct packed{ logic [1:0] value; @@ -591,7 +591,7 @@ module sha512_acc_csr ( if(decoded_reg_strb.LOCK && !decoded_req_is_wr) begin // SW set on read next_c = '1; load_next_c = '1; - end else if(decoded_reg_strb.LOCK && decoded_req_is_wr && hwif_in.valid_user) begin // SW write 1 clear + end else if(decoded_reg_strb.LOCK && decoded_req_is_wr && hwif_in.valid_id) begin // SW write 1 clear next_c = field_storage.LOCK.LOCK.value & ~(decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end @@ -607,34 +607,34 @@ module sha512_acc_csr ( end assign hwif_out.LOCK.LOCK.value = field_storage.LOCK.LOCK.value; assign hwif_out.LOCK.LOCK.swmod = decoded_reg_strb.LOCK; - // Field: sha512_acc_csr.USER.USER + // Field: sha512_acc_csr.ID.ID always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.USER.USER.value; + next_c = field_storage.ID.ID.value; load_next_c = '0; if(hwif_in.lock_set) begin // HW Write - we - next_c = hwif_in.USER.USER.next; + next_c = hwif_in.ID.ID.next; load_next_c = '1; end - field_combo.USER.USER.next = next_c; - field_combo.USER.USER.load_next = load_next_c; + field_combo.ID.ID.next = next_c; + field_combo.ID.ID.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.USER.USER.value <= 32'h0; - end else if(field_combo.USER.USER.load_next) begin - field_storage.USER.USER.value <= field_combo.USER.USER.next; + field_storage.ID.ID.value <= 32'h0; + end else if(field_combo.ID.ID.load_next) begin + field_storage.ID.ID.value <= field_combo.ID.ID.next; end end - assign hwif_out.USER.USER.value = field_storage.USER.USER.value; + assign hwif_out.ID.ID.value = field_storage.ID.ID.value; // Field: sha512_acc_csr.MODE.MODE always_comb begin automatic logic [1:0] next_c; automatic logic load_next_c; next_c = field_storage.MODE.MODE.value; load_next_c = '0; - if(decoded_reg_strb.MODE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write + if(decoded_reg_strb.MODE && decoded_req_is_wr && hwif_in.valid_id) begin // SW write next_c = (field_storage.MODE.MODE.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); load_next_c = '1; end @@ -656,7 +656,7 @@ module sha512_acc_csr ( automatic logic load_next_c; next_c = field_storage.MODE.ENDIAN_TOGGLE.value; load_next_c = '0; - if(decoded_reg_strb.MODE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write + if(decoded_reg_strb.MODE && decoded_req_is_wr && hwif_in.valid_id) begin // SW write next_c = (field_storage.MODE.ENDIAN_TOGGLE.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; end @@ -677,7 +677,7 @@ module sha512_acc_csr ( automatic logic load_next_c; next_c = field_storage.START_ADDRESS.ADDR.value; load_next_c = '0; - if(decoded_reg_strb.START_ADDRESS && decoded_req_is_wr && hwif_in.valid_user) begin // SW write + if(decoded_reg_strb.START_ADDRESS && decoded_req_is_wr && hwif_in.valid_id) begin // SW write next_c = (field_storage.START_ADDRESS.ADDR.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end @@ -698,7 +698,7 @@ module sha512_acc_csr ( automatic logic load_next_c; next_c = field_storage.DLEN.LENGTH.value; load_next_c = '0; - if(decoded_reg_strb.DLEN && decoded_req_is_wr && hwif_in.valid_user) begin // SW write + if(decoded_reg_strb.DLEN && decoded_req_is_wr && hwif_in.valid_id) begin // SW write next_c = (field_storage.DLEN.LENGTH.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end @@ -719,7 +719,7 @@ module sha512_acc_csr ( automatic logic load_next_c; next_c = field_storage.DATAIN.DATAIN.value; load_next_c = '0; - if(decoded_reg_strb.DATAIN && decoded_req_is_wr && hwif_in.valid_user) begin // SW write + if(decoded_reg_strb.DATAIN && decoded_req_is_wr && hwif_in.valid_id) begin // SW write next_c = (field_storage.DATAIN.DATAIN.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end @@ -740,7 +740,7 @@ module sha512_acc_csr ( automatic logic load_next_c; next_c = field_storage.EXECUTE.EXECUTE.value; load_next_c = '0; - if(decoded_reg_strb.EXECUTE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write + if(decoded_reg_strb.EXECUTE && decoded_req_is_wr && hwif_in.valid_id) begin // SW write next_c = (field_storage.EXECUTE.EXECUTE.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end else if(hwif_in.EXECUTE.EXECUTE.hwclr) begin // HW Clear @@ -1630,7 +1630,7 @@ module sha512_acc_csr ( logic [44-1:0][31:0] readback_array; assign readback_array[0][0:0] = (decoded_reg_strb.LOCK && !decoded_req_is_wr) ? field_storage.LOCK.LOCK.value : '0; assign readback_array[0][31:1] = '0; - assign readback_array[1][31:0] = (decoded_reg_strb.USER && !decoded_req_is_wr) ? field_storage.USER.USER.value : '0; + assign readback_array[1][31:0] = (decoded_reg_strb.ID && !decoded_req_is_wr) ? field_storage.ID.ID.value : '0; assign readback_array[2][1:0] = (decoded_reg_strb.MODE && !decoded_req_is_wr) ? field_storage.MODE.MODE.value : '0; assign readback_array[2][2:2] = (decoded_reg_strb.MODE && !decoded_req_is_wr) ? field_storage.MODE.ENDIAN_TOGGLE.value : '0; assign readback_array[2][31:3] = '0; diff --git a/src/soc_ifc/rtl/sha512_acc_csr_covergroups.svh b/src/soc_ifc/rtl/sha512_acc_csr_covergroups.svh index 68cab6060..acc164a78 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr_covergroups.svh +++ b/src/soc_ifc/rtl/sha512_acc_csr_covergroups.svh @@ -35,8 +35,8 @@ endgroup - /*----------------------- SHA512_ACC_CSR__USER COVERGROUPS -----------------------*/ - covergroup sha512_acc_csr__USER_bit_cg with function sample(input bit reg_bit); + /*----------------------- SHA512_ACC_CSR__ID COVERGROUPS -----------------------*/ + covergroup sha512_acc_csr__ID_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -47,11 +47,11 @@ } endgroup - covergroup sha512_acc_csr__USER_fld_cg with function sample( - input bit [32-1:0] USER + covergroup sha512_acc_csr__ID_fld_cg with function sample( + input bit [32-1:0] ID ); option.per_instance = 1; - USER_cp : coverpoint USER; + ID_cp : coverpoint ID; endgroup diff --git a/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv b/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv index 71e0470dd..ae96e1e4e 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv +++ b/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv @@ -8,11 +8,11 @@ package sha512_acc_csr_pkg; typedef struct packed{ logic [31:0] next; - } sha512_acc_csr__USER__USER__in_t; + } sha512_acc_csr__ID__ID__in_t; typedef struct packed{ - sha512_acc_csr__USER__USER__in_t USER; - } sha512_acc_csr__USER__in_t; + sha512_acc_csr__ID__ID__in_t ID; + } sha512_acc_csr__ID__in_t; typedef struct packed{ logic hwclr; @@ -82,11 +82,11 @@ package sha512_acc_csr_pkg; typedef struct packed{ logic lock_set; - logic valid_user; + logic valid_id; logic soc_req; logic cptra_rst_b; logic cptra_pwrgood; - sha512_acc_csr__USER__in_t USER; + sha512_acc_csr__ID__in_t ID; sha512_acc_csr__EXECUTE__in_t EXECUTE; sha512_acc_csr__STATUS__in_t STATUS; sha512_acc_csr__DIGEST__in_t [16-1:0]DIGEST; @@ -104,11 +104,11 @@ package sha512_acc_csr_pkg; typedef struct packed{ logic [31:0] value; - } sha512_acc_csr__USER__USER__out_t; + } sha512_acc_csr__ID__ID__out_t; typedef struct packed{ - sha512_acc_csr__USER__USER__out_t USER; - } sha512_acc_csr__USER__out_t; + sha512_acc_csr__ID__ID__out_t ID; + } sha512_acc_csr__ID__out_t; typedef struct packed{ logic [1:0] value; @@ -202,7 +202,7 @@ package sha512_acc_csr_pkg; typedef struct packed{ sha512_acc_csr__LOCK__out_t LOCK; - sha512_acc_csr__USER__out_t USER; + sha512_acc_csr__ID__out_t ID; sha512_acc_csr__MODE__out_t MODE; sha512_acc_csr__START_ADDRESS__out_t START_ADDRESS; sha512_acc_csr__DLEN__out_t DLEN; diff --git a/src/soc_ifc/rtl/sha512_acc_csr_properties.rdl b/src/soc_ifc/rtl/sha512_acc_csr_properties.rdl index 7ae68c502..c538e477f 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr_properties.rdl +++ b/src/soc_ifc/rtl/sha512_acc_csr_properties.rdl @@ -23,7 +23,7 @@ default regwidth = 32; // reg property default accesswidth = 32; // reg property signal {} lock_set; -signal {} valid_user; +signal {} valid_id; //signal to indicate request is coming from soc side signal {} soc_req; diff --git a/src/soc_ifc/rtl/sha512_acc_csr_sample.svh b/src/soc_ifc/rtl/sha512_acc_csr_sample.svh index cb752d1e8..09e30dbc6 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr_sample.svh +++ b/src/soc_ifc/rtl/sha512_acc_csr_sample.svh @@ -40,8 +40,8 @@ end endfunction - /*----------------------- SHA512_ACC_CSR__USER SAMPLE FUNCTIONS -----------------------*/ - function void sha512_acc_csr__USER::sample(uvm_reg_data_t data, + /*----------------------- SHA512_ACC_CSR__ID SAMPLE FUNCTIONS -----------------------*/ + function void sha512_acc_csr__ID::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -49,19 +49,19 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(USER_bit_cg[bt]) this.USER_bit_cg[bt].sample(data[0 + bt]); + foreach(ID_bit_cg[bt]) this.ID_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*USER*/ ); + this.fld_cg.sample( data[31:0]/*ID*/ ); end endfunction - function void sha512_acc_csr__USER::sample_values(); + function void sha512_acc_csr__ID::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(USER_bit_cg[bt]) this.USER_bit_cg[bt].sample(USER.get_mirrored_value() >> bt); + foreach(ID_bit_cg[bt]) this.ID_bit_cg[bt].sample(ID.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( USER.get_mirrored_value() ); + this.fld_cg.sample( ID.get_mirrored_value() ); end endfunction diff --git a/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv b/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv index d5f30e46e..49a28ec13 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv +++ b/src/soc_ifc/rtl/sha512_acc_csr_uvm.sv @@ -34,17 +34,17 @@ package sha512_acc_csr_uvm; endfunction : build endclass : sha512_acc_csr__LOCK - // Reg - sha512_acc_csr::USER - class sha512_acc_csr__USER extends uvm_reg; + // Reg - sha512_acc_csr::ID + class sha512_acc_csr__ID extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - sha512_acc_csr__USER_bit_cg USER_bit_cg[32]; - sha512_acc_csr__USER_fld_cg fld_cg; - rand uvm_reg_field USER; + sha512_acc_csr__ID_bit_cg ID_bit_cg[32]; + sha512_acc_csr__ID_fld_cg fld_cg; + rand uvm_reg_field ID; - function new(string name = "sha512_acc_csr__USER"); + function new(string name = "sha512_acc_csr__ID"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -54,15 +54,15 @@ package sha512_acc_csr_uvm; uvm_reg_map map); virtual function void build(); - this.USER = new("USER"); - this.USER.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0); + this.ID = new("ID"); + this.ID.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(USER_bit_cg[bt]) USER_bit_cg[bt] = new(); + foreach(ID_bit_cg[bt]) ID_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : sha512_acc_csr__USER + endclass : sha512_acc_csr__ID // Reg - sha512_acc_csr::MODE class sha512_acc_csr__MODE extends uvm_reg; @@ -1063,7 +1063,7 @@ package sha512_acc_csr_uvm; // Addrmap - sha512_acc_csr class sha512_acc_csr extends uvm_reg_block; rand sha512_acc_csr__LOCK LOCK; - rand sha512_acc_csr__USER USER; + rand sha512_acc_csr__ID ID; rand sha512_acc_csr__MODE MODE; rand sha512_acc_csr__START_ADDRESS START_ADDRESS; rand sha512_acc_csr__DLEN DLEN; @@ -1085,11 +1085,11 @@ package sha512_acc_csr_uvm; this.LOCK.build(); this.default_map.add_reg(this.LOCK, 'h0); - this.USER = new("USER"); - this.USER.configure(this); + this.ID = new("ID"); + this.ID.configure(this); - this.USER.build(); - this.default_map.add_reg(this.USER, 'h4); + this.ID.build(); + this.default_map.add_reg(this.ID, 'h4); this.MODE = new("MODE"); this.MODE.configure(this); diff --git a/src/soc_ifc/rtl/sha512_acc_external_csr.rdl b/src/soc_ifc/rtl/sha512_acc_external_csr.rdl index 4f273224a..f0896f8e6 100644 --- a/src/soc_ifc/rtl/sha512_acc_external_csr.rdl +++ b/src/soc_ifc/rtl/sha512_acc_external_csr.rdl @@ -19,16 +19,16 @@ reg { desc="SHA lock register for SHA access, reading 0 will set the lock, Write 1 to clear the lock [br]Caliptra Access: RW [br]SOC Access: RW"; - field {rset; woclr; sw=rw; hw=r; swwe=valid_user; swmod=true;} LOCK=1; + field {rset; woclr; sw=rw; hw=r; swwe=valid_id; swmod=true;} LOCK=1; } LOCK; reg { - name="SHA Accelerator User"; - desc="Stores the user that locked the SHA + name="SHA Accelerator ID"; + desc="Stores the AXI ID that locked the SHA [br]Caliptra Access: RO [br]SOC Access: RO"; - field {sw=r; hw=rw; we=lock_set;} USER[32]=0; -} USER; + field {sw=r; hw=rw; we=lock_set;} ID[32]=0; +} ID; reg { name="SHA Accelerator Mode"; @@ -53,7 +53,7 @@ reg { desc = "SHA is in SHA512, mailbox mode"; }; }; - sw=rw; hw=r; swwe=valid_user; swmod=true; encode = sha_cmd_e;} MODE[2]=0; + sw=rw; hw=r; swwe=valid_id; swmod=true; encode = sha_cmd_e;} MODE[2]=0; field { name="Endianness Toggle for SHA in mailbox mode"; desc="Default behavior assumes that data in mailbox is little endian, @@ -61,7 +61,7 @@ reg { When set to 1, data from the mailbox will be loaded into SHA as-is. [br]Caliptra Access: RW [br]SOC Access: RW"; - sw=rw; hw=r; swwe=valid_user;} ENDIAN_TOGGLE=0; + sw=rw; hw=r; swwe=valid_id;} ENDIAN_TOGGLE=0; } MODE; reg { @@ -70,7 +70,7 @@ reg { Start Address must be dword aligned. [br]Caliptra Access: RW [br]SOC Access: RW"; - field {sw=rw; hw=r; swwe=valid_user;} ADDR[32]=0; + field {sw=rw; hw=r; swwe=valid_id;} ADDR[32]=0; } START_ADDRESS; reg { @@ -78,7 +78,7 @@ reg { desc="The length of data to be processed in bytes. [br]Caliptra Access: RW [br]SOC Access: RW"; - field {sw=rw; hw=r; swwe=valid_user;} LENGTH[32]=0; + field {sw=rw; hw=r; swwe=valid_id;} LENGTH[32]=0; } DLEN; reg { @@ -86,7 +86,7 @@ reg { desc="Data in register for SHA Streaming function [br]Caliptra Access: RW [br]SOC Access: RW"; - field {sw=rw; hw=na; swwe=valid_user; swmod=true;} DATAIN[32]=0; + field {sw=rw; hw=na; swwe=valid_id; swmod=true;} DATAIN[32]=0; } DATAIN; reg { @@ -95,7 +95,7 @@ reg { For the Mailbox SHA Function, indicates that the SHA can begin execution. [br]Caliptra Access: RW [br]SOC Access: RW"; - field {sw=rw; hw=r; hwclr; swwe=valid_user;} EXECUTE=0; + field {sw=rw; hw=r; hwclr; swwe=valid_id;} EXECUTE=0; } EXECUTE; reg { diff --git a/src/soc_ifc/rtl/sha512_acc_top.sv b/src/soc_ifc/rtl/sha512_acc_top.sv index 6445b4f7b..c22816b90 100644 --- a/src/soc_ifc/rtl/sha512_acc_top.sv +++ b/src/soc_ifc/rtl/sha512_acc_top.sv @@ -24,7 +24,7 @@ module sha512_acc_top input logic rst_b, input logic cptra_pwrgood, - // Incoming request from ahb or apb + // Incoming request from ahb or axi input logic req_dv, output logic req_hold, input soc_ifc_req_t req_data, @@ -164,19 +164,19 @@ always_comb core_digest_valid_q = core_digest_valid & ~(init_reg | next_reg); end // reg_update //SHA API - //Acquire the lock and store the user - always_comb hwif_in.USER.USER.next = req_data.user; + //Acquire the lock and store the id + always_comb hwif_in.ID.ID.next = req_data.id; //Detect the lock getting set when swmod is asserted and lock is 0 and it's not a write //Since this lock is cleared by writing, the swmod asserts on write attempts too, but we only want to set lock on read when value is 0 always_comb lock_set = ~hwif_out.LOCK.LOCK.value & hwif_out.LOCK.LOCK.swmod & ~req_data.write; always_comb hwif_in.lock_set = lock_set; - //check the requesting user: + //check the requesting id: //don't update SHA registers if lock hasn't been acquired //if uc has the lock, check that this request is from uc - //if soc has the lock, check that this request is from soc and user attributes match - always_comb hwif_in.valid_user = hwif_out.LOCK.LOCK.value & ((~soc_has_lock & ~req_data.soc_req) | - (soc_has_lock & req_data.soc_req & (req_data.user == hwif_out.USER.USER.value))); + //if soc has the lock, check that this request is from soc and id attributes match + always_comb hwif_in.valid_id = hwif_out.LOCK.LOCK.value & ((~soc_has_lock & ~req_data.soc_req) | + (soc_has_lock & req_data.soc_req & (req_data.id == hwif_out.ID.ID.value))); always_comb hwif_in.soc_req = req_data.soc_req; always_comb hwif_in.STATUS.SOC_HAS_LOCK.next = soc_has_lock; @@ -187,7 +187,7 @@ always_comb core_digest_valid_q = core_digest_valid & ~(init_reg | next_reg); always_comb streaming_mode = ~mode[1] | soc_has_lock; always_comb mailbox_mode = mode[1] & ~soc_has_lock; //Detect writes to datain register - always_comb datain_write = hwif_in.valid_user & hwif_out.DATAIN.DATAIN.swmod; + always_comb datain_write = hwif_in.valid_id & hwif_out.DATAIN.DATAIN.swmod; always_comb execute_set = hwif_out.EXECUTE.EXECUTE.value; //When we reach the end of a block we indicate block full diff --git a/src/soc_ifc/rtl/soc_ifc_arb.sv b/src/soc_ifc/rtl/soc_ifc_arb.sv index 8660009a9..e9ca24f98 100644 --- a/src/soc_ifc/rtl/soc_ifc_arb.sv +++ b/src/soc_ifc/rtl/soc_ifc_arb.sv @@ -15,13 +15,13 @@ module soc_ifc_arb import soc_ifc_pkg::*; #( - parameter APB_USER_WIDTH = 32 + parameter AXI_ID_WIDTH = 32 )( input logic clk, input logic rst_b, - input logic [4:0][APB_USER_WIDTH-1:0] valid_mbox_users, - input logic valid_fuse_user, + input logic [4:0][AXI_ID_WIDTH-1:0] valid_mbox_ids, + input logic valid_fuse_id, //UC inf input logic uc_req_dv, output logic uc_req_hold, @@ -91,7 +91,7 @@ logic uc_mbox_req_ip; logic uc_reg_req_ip; logic uc_sha_req_ip; -//filter mailbox requests by pauser +//filter mailbox requests by id logic valid_mbox_req; @@ -137,24 +137,24 @@ always_comb uc_mbox_dir_req = (uc_req_dv & (uc_req_data.addr inside {[MBOX_DIR_S //SoC requests to mailbox always_comb soc_mbox_req = (valid_mbox_req & (soc_req_data.addr inside {[MBOX_REG_START_ADDR:MBOX_REG_END_ADDR]})); //Requests to arch/fuse register block -//Ensure that requests to fuse block match the appropriate user value +//Ensure that requests to fuse block match the appropriate id value always_comb uc_reg_req = (uc_req_dv & (uc_req_data.addr inside {[SOC_IFC_REG_START_ADDR:SOC_IFC_REG_END_ADDR]})); always_comb soc_reg_req = (soc_req_dv & (soc_req_data.addr inside {[SOC_IFC_REG_START_ADDR:SOC_IFC_REG_END_ADDR]}) & - (~(soc_req_data.addr inside {[SOC_IFC_FUSE_START_ADDR:SOC_IFC_FUSE_END_ADDR]}) | valid_fuse_user)); + (~(soc_req_data.addr inside {[SOC_IFC_FUSE_START_ADDR:SOC_IFC_FUSE_END_ADDR]}) | valid_fuse_id)); //Requests to SHA always_comb uc_sha_req = (uc_req_dv & (uc_req_data.addr inside {[SHA_REG_START_ADDR:SHA_REG_END_ADDR]})); always_comb soc_sha_req = (soc_req_dv & (soc_req_data.addr inside {[SHA_REG_START_ADDR:SHA_REG_END_ADDR]})); -//Check if SoC request is coming from a valid user -//There are 5 valid pauser registers, check if user attribute matches any of them -//Check if user matches Default Valid User parameter - this user value is always valid +//Check if SoC request is coming from a valid id +//There are 5 valid id registers, check if id attribute matches any of them +//Check if id matches Default Valid id parameter - this id value is always valid always_comb begin valid_mbox_req = '0; for (int i=0; i < 5; i++) begin - valid_mbox_req |= soc_req_dv & (soc_req_data.user == valid_mbox_users[i]); + valid_mbox_req |= soc_req_dv & (soc_req_data.id == valid_mbox_ids[i]); end - valid_mbox_req |= soc_req_dv & (soc_req_data.user == CPTRA_DEF_MBOX_VALID_PAUSER); + valid_mbox_req |= soc_req_dv & (soc_req_data.id == CPTRA_DEF_MBOX_VALID_AXI_ID); end //check for collisions diff --git a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl index 048bcb6c4..7bcbb7dad 100644 --- a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl +++ b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl @@ -165,46 +165,46 @@ reg { } CPTRA_SECURITY_STATE; reg { - name = "Valid User Registers"; - desc = "Valid PAUSER attributes for requests from SoC APB Interface. Only valid once LOCK is set. + name = "Valid ID Registers"; + desc = "Valid AXI ID attributes for requests from SoC AXI Interface. Only valid once LOCK is set. [br]Caliptra Access: RW [br]SOC Access: RW - Read-Only once locked by PAUSER_LOCK."; - field {sw=rw; hw=r; swwel;resetsignal = cptra_rst_b;} PAUSER[32]=0xFFFF_FFFF; - } CPTRA_MBOX_VALID_PAUSER[5]; + Read-Only once locked by AXI_ID_LOCK."; + field {sw=rw; hw=r; swwel;resetsignal = cptra_rst_b;} AXI_ID[32]=0xFFFF_FFFF; + } CPTRA_MBOX_VALID_AXI_ID[5]; //FIXME: Should LOCK be W1 here? reg { - name = "Valid User Register Lock"; - desc = "Valid PAUSER attributes for requests from SoC APB Interface. - [br]Each bit corresponds to locking the associated MBOX_VALID_PAUSER register. - [br]Associated MBOX_VALID_PAUSER register is only valid once locked by this bit. + name = "Valid ID Register Lock"; + desc = "Valid AXI_ID attributes for requests from SoC AXI Interface. + [br]Each bit corresponds to locking the associated MBOX_VALID_AXI_ID register. + [br]Associated MBOX_VALID_AXI_ID register is only valid once locked by this bit. [br]Caliptra Access: RW [br]SOC Access: RW [br]Read-Only once locked."; field {sw=rw; hw=r; swwel; resetsignal = cptra_rst_b;} LOCK=0; - } CPTRA_MBOX_PAUSER_LOCK[5]; + } CPTRA_MBOX_AXI_ID_LOCK[5]; reg { - name = "Valid User for TRNG"; - desc = "Valid PAUSER attributes for TRNG on SoC APB Interface. Only valid once LOCK is set. + name = "Valid ID for TRNG"; + desc = "Valid AXI ID attributes for TRNG on SoC AXI Interface. Only valid once LOCK is set. [br]Caliptra Access: RW [br]SOC Access: RW - [br]Read-Only once locked by TRNG_PAUSER_LOCK."; - field {sw=rw; hw=r; swwel; resetsignal = cptra_rst_b;} PAUSER[32]=0xFFFF_FFFF; - } CPTRA_TRNG_VALID_PAUSER; + [br]Read-Only once locked by TRNG_AXI_ID_LOCK."; + field {sw=rw; hw=r; swwel; resetsignal = cptra_rst_b;} AXI_ID[32]=0xFFFF_FFFF; + } CPTRA_TRNG_VALID_AXI_ID; reg { - name = "Valid User for TRNG PAUSER Lock"; - desc = "Valid PAUSER attributes for requests from SoC APB Interface. - [br]Each bit corresponds to locking the associated TRNG_VALID_PAUSER register. - [br]Associated TRNG_VALID_PAUSER register is only valid once locked by this bit. + name = "Valid ID for TRNG AXI_ID Lock"; + desc = "Valid AXI ID attributes for requests from SoC AXI Interface. + [br]Each bit corresponds to locking the associated TRNG_VALID_AXI_ID register. + [br]Associated TRNG_VALID_AXI_ID register is only valid once locked by this bit. [br]Caliptra FW RW access for survivability but cannot unlock once locked [br]Caliptra Access: RW [br]SOC Access: RW [br]Read-Only once locked."; field {sw=rw; hw=r; swwel; resetsignal=cptra_rst_b;} LOCK=0; - } CPTRA_TRNG_PAUSER_LOCK; + } CPTRA_TRNG_AXI_ID_LOCK; reg { name = "TRNG Data"; @@ -397,25 +397,25 @@ reg { } CPTRA_WDT_STATUS; reg { - name = "Valid User for FUSE"; - desc = "Valid PAUSER attributes for FUSE on SoC APB Interface. Only valid once LOCK is set. + name = "Valid ID for FUSE"; + desc = "Valid AXI ID attributes for FUSE on SoC AXI Interface. Only valid once LOCK is set. [br]Caliptra Access: RW [br]SOC Access: RW - [br]Read-Only once locked by FUSE_PAUSER_LOCK."; - field {sw=rw; hw=r; swwel; resetsignal = cptra_pwrgood;} PAUSER[32]=0xFFFF_FFFF; - } CPTRA_FUSE_VALID_PAUSER; + [br]Read-Only once locked by FUSE_AXI_ID_LOCK."; + field {sw=rw; hw=r; swwel; resetsignal = cptra_pwrgood;} AXI_ID[32]=0xFFFF_FFFF; + } CPTRA_FUSE_VALID_AXI_ID; reg { - name = "Valid User for FUSE PAUSER Lock"; - desc = "Valid PAUSER attributes for requests from SoC APB Interface. - [br]Each bit corresponds to locking the associated FUSE_VALID_PAUSER register. - [br]Associated FUSE_VALID_PAUSER register is only valid once locked by this bit. + name = "Valid ID for FUSE AXI_ID Lock"; + desc = "Valid AXI_ID attributes for requests from SoC AXI Interface. + [br]Each bit corresponds to locking the associated FUSE_VALID_AXI_ID register. + [br]Associated FUSE_VALID_AXI_ID register is only valid once locked by this bit. [br]Caliptra FW RW access for survivability but cannot unlock once locked [br]Caliptra Access: RW [br]SOC Access: RW [br]Read-Only once locked."; field {sw=rw; hw=r; swwel; resetsignal=cptra_pwrgood;} LOCK=0; - } CPTRA_FUSE_PAUSER_LOCK; + } CPTRA_FUSE_AXI_ID_LOCK; reg { name = "Caliptra WDT1 Config"; diff --git a/src/soc_ifc/rtl/soc_ifc_pkg.sv b/src/soc_ifc/rtl/soc_ifc_pkg.sv index 8934bdb55..1d8a16312 100644 --- a/src/soc_ifc/rtl/soc_ifc_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_pkg.sv @@ -22,6 +22,7 @@ package soc_ifc_pkg; parameter SOC_IFC_ADDR_W = 18; parameter SOC_IFC_DATA_W = 32; parameter SOC_IFC_USER_W = 32; + parameter SOC_IFC_ID_W = 5; parameter MBOX_SIZE_KB = 128; parameter MBOX_SIZE_BYTES = MBOX_SIZE_KB * 1024; @@ -49,14 +50,14 @@ package soc_ifc_pkg; parameter SOC_IFC_FUSE_START_ADDR = SOC_IFC_REG_START_ADDR + 32'h0000_0200; parameter SOC_IFC_FUSE_END_ADDR = SOC_IFC_REG_START_ADDR + 32'h0000_05FF; - //Valid PAUSER - //Lock the PAUSER values from integration time - parameter [4:0] CPTRA_SET_MBOX_PAUSER_INTEG = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}; - parameter [4:0][31:0] CPTRA_MBOX_VALID_PAUSER = {32'h4444_4444, 32'h3333_3333, 32'h2222_2222, 32'h1111_1111, 32'h0000_0000}; - parameter [31:0] CPTRA_DEF_MBOX_VALID_PAUSER = 32'hFFFF_FFFF; + //Valid AXI_ID + //Lock the AXI_ID values from integration time + parameter [4:0] CPTRA_SET_MBOX_AXI_ID_INTEG = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}; + parameter [4:0][31:0] CPTRA_MBOX_VALID_AXI_ID = {32'h4444_4444, 32'h3333_3333, 32'h2222_2222, 32'h1111_1111, 32'h0000_0000}; + parameter [31:0] CPTRA_DEF_MBOX_VALID_AXI_ID = 32'hFFFF_FFFF; - parameter CPTRA_SET_FUSE_PAUSER_INTEG = 1'b0; - parameter [31:0] CPTRA_FUSE_VALID_PAUSER = 32'h0000_0000; + parameter CPTRA_SET_FUSE_AXI_ID_INTEG = 1'b0; + parameter [31:0] CPTRA_FUSE_VALID_AXI_ID = 32'h0000_0000; //DMI Register encodings //Read only registers @@ -120,7 +121,8 @@ package soc_ifc_pkg; typedef struct packed { logic [SOC_IFC_ADDR_W-1:0] addr; logic [SOC_IFC_DATA_W-1:0] wdata; - logic [SOC_IFC_USER_W-1:0] user; +// logic [SOC_IFC_USER_W-1:0] user; + logic [SOC_IFC_ID_W -1:0] id; logic write; logic soc_req; } soc_ifc_req_t; diff --git a/src/soc_ifc/rtl/soc_ifc_reg.sv b/src/soc_ifc/rtl/soc_ifc_reg.sv index 60e85ee1f..353d469a6 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg.sv @@ -77,10 +77,10 @@ module soc_ifc_reg ( logic CPTRA_FLOW_STATUS; logic CPTRA_RESET_REASON; logic CPTRA_SECURITY_STATE; - logic [5-1:0]CPTRA_MBOX_VALID_PAUSER; - logic [5-1:0]CPTRA_MBOX_PAUSER_LOCK; - logic CPTRA_TRNG_VALID_PAUSER; - logic CPTRA_TRNG_PAUSER_LOCK; + logic [5-1:0]CPTRA_MBOX_VALID_AXI_ID; + logic [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; + logic CPTRA_TRNG_VALID_AXI_ID; + logic CPTRA_TRNG_AXI_ID_LOCK; logic [12-1:0]CPTRA_TRNG_DATA; logic CPTRA_TRNG_CTRL; logic CPTRA_TRNG_STATUS; @@ -101,8 +101,8 @@ module soc_ifc_reg ( logic CPTRA_WDT_TIMER2_CTRL; logic [2-1:0]CPTRA_WDT_TIMER2_TIMEOUT_PERIOD; logic CPTRA_WDT_STATUS; - logic CPTRA_FUSE_VALID_PAUSER; - logic CPTRA_FUSE_PAUSER_LOCK; + logic CPTRA_FUSE_VALID_AXI_ID; + logic CPTRA_FUSE_AXI_ID_LOCK; logic [2-1:0]CPTRA_WDT_CFG; logic CPTRA_iTRNG_ENTROPY_CONFIG_0; logic CPTRA_iTRNG_ENTROPY_CONFIG_1; @@ -195,13 +195,13 @@ module soc_ifc_reg ( decoded_reg_strb.CPTRA_RESET_REASON = cpuif_req_masked & (cpuif_addr == 12'h40); decoded_reg_strb.CPTRA_SECURITY_STATE = cpuif_req_masked & (cpuif_addr == 12'h44); for(int i0=0; i0<5; i0++) begin - decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] = cpuif_req_masked & (cpuif_addr == 12'h48 + i0*12'h4); + decoded_reg_strb.CPTRA_MBOX_VALID_AXI_ID[i0] = cpuif_req_masked & (cpuif_addr == 12'h48 + i0*12'h4); end for(int i0=0; i0<5; i0++) begin - decoded_reg_strb.CPTRA_MBOX_PAUSER_LOCK[i0] = cpuif_req_masked & (cpuif_addr == 12'h5c + i0*12'h4); + decoded_reg_strb.CPTRA_MBOX_AXI_ID_LOCK[i0] = cpuif_req_masked & (cpuif_addr == 12'h5c + i0*12'h4); end - decoded_reg_strb.CPTRA_TRNG_VALID_PAUSER = cpuif_req_masked & (cpuif_addr == 12'h70); - decoded_reg_strb.CPTRA_TRNG_PAUSER_LOCK = cpuif_req_masked & (cpuif_addr == 12'h74); + decoded_reg_strb.CPTRA_TRNG_VALID_AXI_ID = cpuif_req_masked & (cpuif_addr == 12'h70); + decoded_reg_strb.CPTRA_TRNG_AXI_ID_LOCK = cpuif_req_masked & (cpuif_addr == 12'h74); for(int i0=0; i0<12; i0++) begin decoded_reg_strb.CPTRA_TRNG_DATA[i0] = cpuif_req_masked & (cpuif_addr == 12'h78 + i0*12'h4); end @@ -234,8 +234,8 @@ module soc_ifc_reg ( decoded_reg_strb.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 12'hfc + i0*12'h4); end decoded_reg_strb.CPTRA_WDT_STATUS = cpuif_req_masked & (cpuif_addr == 12'h104); - decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER = cpuif_req_masked & (cpuif_addr == 12'h108); - decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK = cpuif_req_masked & (cpuif_addr == 12'h10c); + decoded_reg_strb.CPTRA_FUSE_VALID_AXI_ID = cpuif_req_masked & (cpuif_addr == 12'h108); + decoded_reg_strb.CPTRA_FUSE_AXI_ID_LOCK = cpuif_req_masked & (cpuif_addr == 12'h10c); for(int i0=0; i0<2; i0++) begin decoded_reg_strb.CPTRA_WDT_CFG[i0] = cpuif_req_masked & (cpuif_addr == 12'h110 + i0*12'h4); end @@ -440,26 +440,26 @@ module soc_ifc_reg ( struct packed{ logic [31:0] next; logic load_next; - } PAUSER; - } [5-1:0]CPTRA_MBOX_VALID_PAUSER; + } AXI_ID; + } [5-1:0]CPTRA_MBOX_VALID_AXI_ID; struct packed{ struct packed{ logic next; logic load_next; } LOCK; - } [5-1:0]CPTRA_MBOX_PAUSER_LOCK; + } [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; struct packed{ struct packed{ logic [31:0] next; logic load_next; - } PAUSER; - } CPTRA_TRNG_VALID_PAUSER; + } AXI_ID; + } CPTRA_TRNG_VALID_AXI_ID; struct packed{ struct packed{ logic next; logic load_next; } LOCK; - } CPTRA_TRNG_PAUSER_LOCK; + } CPTRA_TRNG_AXI_ID_LOCK; struct packed{ struct packed{ logic [31:0] next; @@ -580,14 +580,14 @@ module soc_ifc_reg ( struct packed{ logic [31:0] next; logic load_next; - } PAUSER; - } CPTRA_FUSE_VALID_PAUSER; + } AXI_ID; + } CPTRA_FUSE_VALID_AXI_ID; struct packed{ struct packed{ logic next; logic load_next; } LOCK; - } CPTRA_FUSE_PAUSER_LOCK; + } CPTRA_FUSE_AXI_ID_LOCK; struct packed{ struct packed{ logic [31:0] next; @@ -1317,23 +1317,23 @@ module soc_ifc_reg ( struct packed{ struct packed{ logic [31:0] value; - } PAUSER; - } [5-1:0]CPTRA_MBOX_VALID_PAUSER; + } AXI_ID; + } [5-1:0]CPTRA_MBOX_VALID_AXI_ID; struct packed{ struct packed{ logic value; } LOCK; - } [5-1:0]CPTRA_MBOX_PAUSER_LOCK; + } [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; struct packed{ struct packed{ logic [31:0] value; - } PAUSER; - } CPTRA_TRNG_VALID_PAUSER; + } AXI_ID; + } CPTRA_TRNG_VALID_AXI_ID; struct packed{ struct packed{ logic value; } LOCK; - } CPTRA_TRNG_PAUSER_LOCK; + } CPTRA_TRNG_AXI_ID_LOCK; struct packed{ struct packed{ logic [31:0] value; @@ -1433,13 +1433,13 @@ module soc_ifc_reg ( struct packed{ struct packed{ logic [31:0] value; - } PAUSER; - } CPTRA_FUSE_VALID_PAUSER; + } AXI_ID; + } CPTRA_FUSE_VALID_AXI_ID; struct packed{ struct packed{ logic value; } LOCK; - } CPTRA_FUSE_PAUSER_LOCK; + } CPTRA_FUSE_AXI_ID_LOCK; struct packed{ struct packed{ logic [31:0] value; @@ -2365,93 +2365,93 @@ module soc_ifc_reg ( end assign hwif_out.CPTRA_RESET_REASON.WARM_RESET.value = field_storage.CPTRA_RESET_REASON.WARM_RESET.value; for(genvar i0=0; i0<5; i0++) begin - // Field: soc_ifc_reg.CPTRA_MBOX_VALID_PAUSER[].PAUSER + // Field: soc_ifc_reg.CPTRA_MBOX_VALID_AXI_ID[].AXI_ID always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value; + next_c = field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.swwel)) begin // SW write - next_c = (field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + if(decoded_reg_strb.CPTRA_MBOX_VALID_AXI_ID[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.swwel)) begin // SW write + next_c = (field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end - field_combo.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.next = next_c; - field_combo.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.load_next = load_next_c; + field_combo.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.next = next_c; + field_combo.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value <= 32'hffffffff; - end else if(field_combo.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.load_next) begin - field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value <= field_combo.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.next; + field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value <= 32'hffffffff; + end else if(field_combo.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.load_next) begin + field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value <= field_combo.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.next; end end - assign hwif_out.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value = field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value; + assign hwif_out.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value = field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value; end for(genvar i0=0; i0<5; i0++) begin - // Field: soc_ifc_reg.CPTRA_MBOX_PAUSER_LOCK[].LOCK + // Field: soc_ifc_reg.CPTRA_MBOX_AXI_ID_LOCK[].LOCK always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value; + next_c = field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_MBOX_PAUSER_LOCK[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.swwel)) begin // SW write - next_c = (field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + if(decoded_reg_strb.CPTRA_MBOX_AXI_ID_LOCK[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.swwel)) begin // SW write + next_c = (field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end - field_combo.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.next = next_c; - field_combo.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.load_next = load_next_c; + field_combo.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.next = next_c; + field_combo.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value <= 1'h0; - end else if(field_combo.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.load_next) begin - field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value <= field_combo.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.next; + field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value <= 1'h0; + end else if(field_combo.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.load_next) begin + field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value <= field_combo.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.next; end end - assign hwif_out.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value = field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value; + assign hwif_out.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value = field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value; end - // Field: soc_ifc_reg.CPTRA_TRNG_VALID_PAUSER.PAUSER + // Field: soc_ifc_reg.CPTRA_TRNG_VALID_AXI_ID.AXI_ID always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value; + next_c = field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_TRNG_VALID_PAUSER && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_VALID_PAUSER.PAUSER.swwel)) begin // SW write - next_c = (field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + if(decoded_reg_strb.CPTRA_TRNG_VALID_AXI_ID && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.swwel)) begin // SW write + next_c = (field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end - field_combo.CPTRA_TRNG_VALID_PAUSER.PAUSER.next = next_c; - field_combo.CPTRA_TRNG_VALID_PAUSER.PAUSER.load_next = load_next_c; + field_combo.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.next = next_c; + field_combo.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value <= 32'hffffffff; - end else if(field_combo.CPTRA_TRNG_VALID_PAUSER.PAUSER.load_next) begin - field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value <= field_combo.CPTRA_TRNG_VALID_PAUSER.PAUSER.next; + field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value <= 32'hffffffff; + end else if(field_combo.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.load_next) begin + field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value <= field_combo.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.next; end end - assign hwif_out.CPTRA_TRNG_VALID_PAUSER.PAUSER.value = field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value; - // Field: soc_ifc_reg.CPTRA_TRNG_PAUSER_LOCK.LOCK + assign hwif_out.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value = field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value; + // Field: soc_ifc_reg.CPTRA_TRNG_AXI_ID_LOCK.LOCK always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value; + next_c = field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_TRNG_PAUSER_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_PAUSER_LOCK.LOCK.swwel)) begin // SW write - next_c = (field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + if(decoded_reg_strb.CPTRA_TRNG_AXI_ID_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_AXI_ID_LOCK.LOCK.swwel)) begin // SW write + next_c = (field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end - field_combo.CPTRA_TRNG_PAUSER_LOCK.LOCK.next = next_c; - field_combo.CPTRA_TRNG_PAUSER_LOCK.LOCK.load_next = load_next_c; + field_combo.CPTRA_TRNG_AXI_ID_LOCK.LOCK.next = next_c; + field_combo.CPTRA_TRNG_AXI_ID_LOCK.LOCK.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value <= 1'h0; - end else if(field_combo.CPTRA_TRNG_PAUSER_LOCK.LOCK.load_next) begin - field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value <= field_combo.CPTRA_TRNG_PAUSER_LOCK.LOCK.next; + field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value <= 1'h0; + end else if(field_combo.CPTRA_TRNG_AXI_ID_LOCK.LOCK.load_next) begin + field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value <= field_combo.CPTRA_TRNG_AXI_ID_LOCK.LOCK.next; end end - assign hwif_out.CPTRA_TRNG_PAUSER_LOCK.LOCK.value = field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value; + assign hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value = field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value; for(genvar i0=0; i0<12; i0++) begin // Field: soc_ifc_reg.CPTRA_TRNG_DATA[].DATA always_comb begin @@ -2910,48 +2910,48 @@ module soc_ifc_reg ( end end assign hwif_out.CPTRA_WDT_STATUS.t2_timeout.value = field_storage.CPTRA_WDT_STATUS.t2_timeout.value; - // Field: soc_ifc_reg.CPTRA_FUSE_VALID_PAUSER.PAUSER + // Field: soc_ifc_reg.CPTRA_FUSE_VALID_AXI_ID.AXI_ID always_comb begin automatic logic [31:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value; + next_c = field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_VALID_PAUSER.PAUSER.swwel)) begin // SW write - next_c = (field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + if(decoded_reg_strb.CPTRA_FUSE_VALID_AXI_ID && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.swwel)) begin // SW write + next_c = (field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end - field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.next = next_c; - field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.load_next = load_next_c; + field_combo.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.next = next_c; + field_combo.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value <= 32'hffffffff; - end else if(field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.load_next) begin - field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value <= field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.next; + field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value <= 32'hffffffff; + end else if(field_combo.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.load_next) begin + field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value <= field_combo.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.next; end end - assign hwif_out.CPTRA_FUSE_VALID_PAUSER.PAUSER.value = field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value; - // Field: soc_ifc_reg.CPTRA_FUSE_PAUSER_LOCK.LOCK + assign hwif_out.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value = field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value; + // Field: soc_ifc_reg.CPTRA_FUSE_AXI_ID_LOCK.LOCK always_comb begin automatic logic [0:0] next_c; automatic logic load_next_c; - next_c = field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value; + next_c = field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value; load_next_c = '0; - if(decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_PAUSER_LOCK.LOCK.swwel)) begin // SW write - next_c = (field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + if(decoded_reg_strb.CPTRA_FUSE_AXI_ID_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_AXI_ID_LOCK.LOCK.swwel)) begin // SW write + next_c = (field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; end - field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.next = next_c; - field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.load_next = load_next_c; + field_combo.CPTRA_FUSE_AXI_ID_LOCK.LOCK.next = next_c; + field_combo.CPTRA_FUSE_AXI_ID_LOCK.LOCK.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value <= 1'h0; - end else if(field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.load_next) begin - field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value <= field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.next; + field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value <= 1'h0; + end else if(field_combo.CPTRA_FUSE_AXI_ID_LOCK.LOCK.load_next) begin + field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value <= field_combo.CPTRA_FUSE_AXI_ID_LOCK.LOCK.next; end end - assign hwif_out.CPTRA_FUSE_PAUSER_LOCK.LOCK.value = field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value; + assign hwif_out.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value = field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value; for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_WDT_CFG[].TIMEOUT always_comb begin @@ -5805,14 +5805,14 @@ module soc_ifc_reg ( assign readback_array[17][3:3] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? hwif_in.CPTRA_SECURITY_STATE.scan_mode.next : '0; assign readback_array[17][31:4] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? 28'h0 : '0; for(genvar i0=0; i0<5; i0++) begin - assign readback_array[i0*1 + 18][31:0] = (decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value : '0; + assign readback_array[i0*1 + 18][31:0] = (decoded_reg_strb.CPTRA_MBOX_VALID_AXI_ID[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_VALID_AXI_ID[i0].AXI_ID.value : '0; end for(genvar i0=0; i0<5; i0++) begin - assign readback_array[i0*1 + 23][0:0] = (decoded_reg_strb.CPTRA_MBOX_PAUSER_LOCK[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value : '0; + assign readback_array[i0*1 + 23][0:0] = (decoded_reg_strb.CPTRA_MBOX_AXI_ID_LOCK[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_AXI_ID_LOCK[i0].LOCK.value : '0; assign readback_array[i0*1 + 23][31:1] = '0; end - assign readback_array[28][31:0] = (decoded_reg_strb.CPTRA_TRNG_VALID_PAUSER && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value : '0; - assign readback_array[29][0:0] = (decoded_reg_strb.CPTRA_TRNG_PAUSER_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value : '0; + assign readback_array[28][31:0] = (decoded_reg_strb.CPTRA_TRNG_VALID_AXI_ID && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value : '0; + assign readback_array[29][0:0] = (decoded_reg_strb.CPTRA_TRNG_AXI_ID_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value : '0; assign readback_array[29][31:1] = '0; for(genvar i0=0; i0<12; i0++) begin assign readback_array[i0*1 + 30][31:0] = (decoded_reg_strb.CPTRA_TRNG_DATA[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_TRNG_DATA[i0].DATA.value : '0; @@ -5864,8 +5864,8 @@ module soc_ifc_reg ( assign readback_array[65][0:0] = (decoded_reg_strb.CPTRA_WDT_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_STATUS.t1_timeout.value : '0; assign readback_array[65][1:1] = (decoded_reg_strb.CPTRA_WDT_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_STATUS.t2_timeout.value : '0; assign readback_array[65][31:2] = '0; - assign readback_array[66][31:0] = (decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value : '0; - assign readback_array[67][0:0] = (decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value : '0; + assign readback_array[66][31:0] = (decoded_reg_strb.CPTRA_FUSE_VALID_AXI_ID && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value : '0; + assign readback_array[67][0:0] = (decoded_reg_strb.CPTRA_FUSE_AXI_ID_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value : '0; assign readback_array[67][31:1] = '0; for(genvar i0=0; i0<2; i0++) begin assign readback_array[i0*1 + 68][31:0] = (decoded_reg_strb.CPTRA_WDT_CFG[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value : '0; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh index c74221ba9..ebd06c48a 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh @@ -265,8 +265,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_PAUSER COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_AXI_ID COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -277,16 +277,16 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER_fld_cg with function sample( - input bit [32-1:0] PAUSER + covergroup soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID_fld_cg with function sample( + input bit [32-1:0] AXI_ID ); option.per_instance = 1; - PAUSER_cp : coverpoint PAUSER; + AXI_ID_cp : coverpoint AXI_ID; endgroup - /*----------------------- SOC_IFC_REG__CPTRA_MBOX_PAUSER_LOCK COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_MBOX_AXI_ID_LOCK COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -297,7 +297,7 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK_fld_cg with function sample( + covergroup soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK_fld_cg with function sample( input bit [1-1:0] LOCK ); option.per_instance = 1; @@ -305,8 +305,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_PAUSER COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_AXI_ID COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -317,11 +317,11 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER_fld_cg with function sample( - input bit [32-1:0] PAUSER + covergroup soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID_fld_cg with function sample( + input bit [32-1:0] AXI_ID ); option.per_instance = 1; - PAUSER_cp : coverpoint PAUSER { + AXI_ID_cp : coverpoint AXI_ID { bins zero_val = {32'h0}; bins rand_val[64] = {[1:32'hFFFF_FFFE]}; bins ones_val = {{32{1'b1}}}; @@ -331,8 +331,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_TRNG_PAUSER_LOCK COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_TRNG_AXI_ID_LOCK COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -343,7 +343,7 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK_fld_cg with function sample( + covergroup soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK_fld_cg with function sample( input bit [1-1:0] LOCK ); option.per_instance = 1; @@ -789,8 +789,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_PAUSER COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_AXI_ID COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -801,11 +801,11 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER_fld_cg with function sample( - input bit [32-1:0] PAUSER + covergroup soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID_fld_cg with function sample( + input bit [32-1:0] AXI_ID ); option.per_instance = 1; - PAUSER_cp : coverpoint PAUSER { + AXI_ID_cp : coverpoint AXI_ID { bins zero_val = {32'h0}; bins rand_val[64] = {[1:32'hFFFF_FFFE]}; bins ones_val = {{32{1'b1}}}; @@ -815,8 +815,8 @@ endgroup - /*----------------------- SOC_IFC_REG__CPTRA_FUSE_PAUSER_LOCK COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__CPTRA_FUSE_AXI_ID_LOCK COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -827,7 +827,7 @@ } endgroup - covergroup soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK_fld_cg with function sample( + covergroup soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK_fld_cg with function sample( input bit [1-1:0] LOCK ); option.per_instance = 1; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv index 15d1f534f..2172b382c 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv @@ -84,35 +84,35 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__PAUSER__in_t; + } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__AXI_ID__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__PAUSER__in_t PAUSER; - } soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__in_t; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__AXI_ID__in_t AXI_ID; + } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__in_t; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__LOCK__in_t; + } soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__LOCK__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__LOCK__in_t LOCK; - } soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__in_t; + soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__LOCK__in_t LOCK; + } soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__in_t; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__PAUSER__in_t; + } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__AXI_ID__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__PAUSER__in_t PAUSER; - } soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__in_t; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__AXI_ID__in_t AXI_ID; + } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__in_t; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__LOCK__in_t; + } soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__LOCK__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__LOCK__in_t LOCK; - } soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__in_t; + soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__LOCK__in_t LOCK; + } soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__in_t; typedef struct packed{ logic swwe; @@ -217,19 +217,19 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__PAUSER__in_t; + } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__AXI_ID__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__PAUSER__in_t PAUSER; - } soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__in_t; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__AXI_ID__in_t AXI_ID; + } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__in_t; typedef struct packed{ logic swwel; - } soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__LOCK__in_t; + } soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__LOCK__in_t; typedef struct packed{ - soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__LOCK__in_t LOCK; - } soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__in_t; + soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__LOCK__in_t LOCK; + } soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__in_t; typedef struct packed{ logic swwel; @@ -439,10 +439,10 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_FLOW_STATUS__in_t CPTRA_FLOW_STATUS; soc_ifc_reg__CPTRA_RESET_REASON__in_t CPTRA_RESET_REASON; soc_ifc_reg__CPTRA_SECURITY_STATE__in_t CPTRA_SECURITY_STATE; - soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__in_t [5-1:0]CPTRA_MBOX_VALID_PAUSER; - soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__in_t [5-1:0]CPTRA_MBOX_PAUSER_LOCK; - soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__in_t CPTRA_TRNG_VALID_PAUSER; - soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__in_t CPTRA_TRNG_PAUSER_LOCK; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__in_t [5-1:0]CPTRA_MBOX_VALID_AXI_ID; + soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__in_t [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__in_t CPTRA_TRNG_VALID_AXI_ID; + soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__in_t CPTRA_TRNG_AXI_ID_LOCK; soc_ifc_reg__CPTRA_TRNG_DATA__in_t [12-1:0]CPTRA_TRNG_DATA; soc_ifc_reg__CPTRA_TRNG_STATUS__in_t CPTRA_TRNG_STATUS; soc_ifc_reg__CPTRA_FUSE_WR_DONE__in_t CPTRA_FUSE_WR_DONE; @@ -452,8 +452,8 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_HW_REV_ID__in_t CPTRA_HW_REV_ID; soc_ifc_reg__CPTRA_HW_CONFIG__in_t CPTRA_HW_CONFIG; soc_ifc_reg__CPTRA_WDT_STATUS__in_t CPTRA_WDT_STATUS; - soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__in_t CPTRA_FUSE_VALID_PAUSER; - soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__in_t CPTRA_FUSE_PAUSER_LOCK; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__in_t CPTRA_FUSE_VALID_AXI_ID; + soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__in_t CPTRA_FUSE_AXI_ID_LOCK; soc_ifc_reg__fuse_uds_seed__in_t [12-1:0]fuse_uds_seed; soc_ifc_reg__fuse_field_entropy__in_t [8-1:0]fuse_field_entropy; soc_ifc_reg__fuse_key_manifest_pk_hash__in_t [12-1:0]fuse_key_manifest_pk_hash; @@ -575,35 +575,35 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic [31:0] value; - } soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__PAUSER__out_t; + } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__AXI_ID__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__PAUSER__out_t PAUSER; - } soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__out_t; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__AXI_ID__out_t AXI_ID; + } soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__out_t; typedef struct packed{ logic value; - } soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__LOCK__out_t; + } soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__LOCK__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__LOCK__out_t LOCK; - } soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__out_t; + soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__LOCK__out_t LOCK; + } soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__out_t; typedef struct packed{ logic [31:0] value; - } soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__PAUSER__out_t; + } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__AXI_ID__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__PAUSER__out_t PAUSER; - } soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__out_t; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__AXI_ID__out_t AXI_ID; + } soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__out_t; typedef struct packed{ logic value; - } soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__LOCK__out_t; + } soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__LOCK__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__LOCK__out_t LOCK; - } soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__out_t; + soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__LOCK__out_t LOCK; + } soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__out_t; typedef struct packed{ logic swacc; @@ -749,19 +749,19 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic [31:0] value; - } soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__PAUSER__out_t; + } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__AXI_ID__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__PAUSER__out_t PAUSER; - } soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__out_t; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__AXI_ID__out_t AXI_ID; + } soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__out_t; typedef struct packed{ logic value; - } soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__LOCK__out_t; + } soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__LOCK__out_t; typedef struct packed{ - soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__LOCK__out_t LOCK; - } soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__out_t; + soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__LOCK__out_t LOCK; + } soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__out_t; typedef struct packed{ logic [31:0] value; @@ -980,10 +980,10 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_BOOT_STATUS__out_t CPTRA_BOOT_STATUS; soc_ifc_reg__CPTRA_FLOW_STATUS__out_t CPTRA_FLOW_STATUS; soc_ifc_reg__CPTRA_RESET_REASON__out_t CPTRA_RESET_REASON; - soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER__out_t [5-1:0]CPTRA_MBOX_VALID_PAUSER; - soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK__out_t [5-1:0]CPTRA_MBOX_PAUSER_LOCK; - soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER__out_t CPTRA_TRNG_VALID_PAUSER; - soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK__out_t CPTRA_TRNG_PAUSER_LOCK; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID__out_t [5-1:0]CPTRA_MBOX_VALID_AXI_ID; + soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK__out_t [5-1:0]CPTRA_MBOX_AXI_ID_LOCK; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID__out_t CPTRA_TRNG_VALID_AXI_ID; + soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK__out_t CPTRA_TRNG_AXI_ID_LOCK; soc_ifc_reg__CPTRA_TRNG_DATA__out_t [12-1:0]CPTRA_TRNG_DATA; soc_ifc_reg__CPTRA_TRNG_CTRL__out_t CPTRA_TRNG_CTRL; soc_ifc_reg__CPTRA_TRNG_STATUS__out_t CPTRA_TRNG_STATUS; @@ -1001,8 +1001,8 @@ package soc_ifc_reg_pkg; soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL__out_t CPTRA_WDT_TIMER2_CTRL; soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD__out_t [2-1:0]CPTRA_WDT_TIMER2_TIMEOUT_PERIOD; soc_ifc_reg__CPTRA_WDT_STATUS__out_t CPTRA_WDT_STATUS; - soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER__out_t CPTRA_FUSE_VALID_PAUSER; - soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK__out_t CPTRA_FUSE_PAUSER_LOCK; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID__out_t CPTRA_FUSE_VALID_AXI_ID; + soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK__out_t CPTRA_FUSE_AXI_ID_LOCK; soc_ifc_reg__fuse_uds_seed__out_t [12-1:0]fuse_uds_seed; soc_ifc_reg__fuse_field_entropy__out_t [8-1:0]fuse_field_entropy; soc_ifc_reg__fuse_key_manifest_pk_hash__out_t [12-1:0]fuse_key_manifest_pk_hash; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh index 4274380d0..ff26ec47f 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh @@ -320,8 +320,8 @@ end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_PAUSER SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_MBOX_VALID_AXI_ID SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -329,24 +329,24 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(data[0 + bt]); + foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*PAUSER*/ ); + this.fld_cg.sample( data[31:0]/*AXI_ID*/ ); end endfunction - function void soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER::sample_values(); + function void soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(PAUSER.get_mirrored_value() >> bt); + foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(AXI_ID.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( PAUSER.get_mirrored_value() ); + this.fld_cg.sample( AXI_ID.get_mirrored_value() ); end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_MBOX_PAUSER_LOCK SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_MBOX_AXI_ID_LOCK SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -361,7 +361,7 @@ end endfunction - function void soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK::sample_values(); + function void soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(LOCK.get_mirrored_value() >> bt); end @@ -370,8 +370,8 @@ end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_PAUSER SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_TRNG_VALID_AXI_ID SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -379,24 +379,24 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(data[0 + bt]); + foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*PAUSER*/ ); + this.fld_cg.sample( data[31:0]/*AXI_ID*/ ); end endfunction - function void soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER::sample_values(); + function void soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(PAUSER.get_mirrored_value() >> bt); + foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(AXI_ID.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( PAUSER.get_mirrored_value() ); + this.fld_cg.sample( AXI_ID.get_mirrored_value() ); end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_TRNG_PAUSER_LOCK SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_TRNG_AXI_ID_LOCK SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -411,7 +411,7 @@ end endfunction - function void soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK::sample_values(); + function void soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(LOCK.get_mirrored_value() >> bt); end @@ -934,8 +934,8 @@ end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_PAUSER SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_FUSE_VALID_AXI_ID SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -943,24 +943,24 @@ m_data = data; m_is_read = is_read; if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(data[0 + bt]); + foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(data[0 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*PAUSER*/ ); + this.fld_cg.sample( data[31:0]/*AXI_ID*/ ); end endfunction - function void soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER::sample_values(); + function void soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) this.PAUSER_bit_cg[bt].sample(PAUSER.get_mirrored_value() >> bt); + foreach(AXI_ID_bit_cg[bt]) this.AXI_ID_bit_cg[bt].sample(AXI_ID.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( PAUSER.get_mirrored_value() ); + this.fld_cg.sample( AXI_ID.get_mirrored_value() ); end endfunction - /*----------------------- SOC_IFC_REG__CPTRA_FUSE_PAUSER_LOCK SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__CPTRA_FUSE_AXI_ID_LOCK SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -975,7 +975,7 @@ end endfunction - function void soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK::sample_values(); + function void soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin foreach(LOCK_bit_cg[bt]) this.LOCK_bit_cg[bt].sample(LOCK.get_mirrored_value() >> bt); end diff --git a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv index b111caa8c..da67c9fe0 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv @@ -409,17 +409,17 @@ package soc_ifc_reg_uvm; endfunction : build endclass : soc_ifc_reg__CPTRA_SECURITY_STATE - // Reg - soc_ifc_reg::CPTRA_MBOX_VALID_PAUSER - class soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_MBOX_VALID_AXI_ID + class soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER_bit_cg PAUSER_bit_cg[32]; - soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER_fld_cg fld_cg; - rand uvm_reg_field PAUSER; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID_bit_cg AXI_ID_bit_cg[32]; + soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID_fld_cg fld_cg; + rand uvm_reg_field AXI_ID; - function new(string name = "soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER"); + function new(string name = "soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -429,27 +429,27 @@ package soc_ifc_reg_uvm; uvm_reg_map map); virtual function void build(); - this.PAUSER = new("PAUSER"); - this.PAUSER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); + this.AXI_ID = new("AXI_ID"); + this.AXI_ID.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) PAUSER_bit_cg[bt] = new(); + foreach(AXI_ID_bit_cg[bt]) AXI_ID_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER + endclass : soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID - // Reg - soc_ifc_reg::CPTRA_MBOX_PAUSER_LOCK - class soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_MBOX_AXI_ID_LOCK + class soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK_bit_cg LOCK_bit_cg[1]; - soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK_fld_cg fld_cg; + soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK_bit_cg LOCK_bit_cg[1]; + soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK_fld_cg fld_cg; rand uvm_reg_field LOCK; - function new(string name = "soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK"); + function new(string name = "soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -467,19 +467,19 @@ package soc_ifc_reg_uvm; if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK + endclass : soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK - // Reg - soc_ifc_reg::CPTRA_TRNG_VALID_PAUSER - class soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_TRNG_VALID_AXI_ID + class soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER_bit_cg PAUSER_bit_cg[32]; - soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER_fld_cg fld_cg; - rand uvm_reg_field PAUSER; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID_bit_cg AXI_ID_bit_cg[32]; + soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID_fld_cg fld_cg; + rand uvm_reg_field AXI_ID; - function new(string name = "soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER"); + function new(string name = "soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -489,27 +489,27 @@ package soc_ifc_reg_uvm; uvm_reg_map map); virtual function void build(); - this.PAUSER = new("PAUSER"); - this.PAUSER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); + this.AXI_ID = new("AXI_ID"); + this.AXI_ID.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) PAUSER_bit_cg[bt] = new(); + foreach(AXI_ID_bit_cg[bt]) AXI_ID_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER + endclass : soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID - // Reg - soc_ifc_reg::CPTRA_TRNG_PAUSER_LOCK - class soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_TRNG_AXI_ID_LOCK + class soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK_bit_cg LOCK_bit_cg[1]; - soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK_fld_cg fld_cg; + soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK_bit_cg LOCK_bit_cg[1]; + soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK_fld_cg fld_cg; rand uvm_reg_field LOCK; - function new(string name = "soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK"); + function new(string name = "soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -527,7 +527,7 @@ package soc_ifc_reg_uvm; if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK + endclass : soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK // Reg - soc_ifc_reg::CPTRA_TRNG_DATA class soc_ifc_reg__CPTRA_TRNG_DATA extends uvm_reg; @@ -1164,17 +1164,17 @@ package soc_ifc_reg_uvm; endfunction : build endclass : soc_ifc_reg__CPTRA_WDT_STATUS - // Reg - soc_ifc_reg::CPTRA_FUSE_VALID_PAUSER - class soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_FUSE_VALID_AXI_ID + class soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER_bit_cg PAUSER_bit_cg[32]; - soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER_fld_cg fld_cg; - rand uvm_reg_field PAUSER; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID_bit_cg AXI_ID_bit_cg[32]; + soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID_fld_cg fld_cg; + rand uvm_reg_field AXI_ID; - function new(string name = "soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER"); + function new(string name = "soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -1184,27 +1184,27 @@ package soc_ifc_reg_uvm; uvm_reg_map map); virtual function void build(); - this.PAUSER = new("PAUSER"); - this.PAUSER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); + this.AXI_ID = new("AXI_ID"); + this.AXI_ID.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin - foreach(PAUSER_bit_cg[bt]) PAUSER_bit_cg[bt] = new(); + foreach(AXI_ID_bit_cg[bt]) AXI_ID_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER + endclass : soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID - // Reg - soc_ifc_reg::CPTRA_FUSE_PAUSER_LOCK - class soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK extends uvm_reg; + // Reg - soc_ifc_reg::CPTRA_FUSE_AXI_ID_LOCK + class soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK extends uvm_reg; protected uvm_reg_data_t m_current; protected uvm_reg_data_t m_data; protected bit m_is_read; - soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK_bit_cg LOCK_bit_cg[1]; - soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK_fld_cg fld_cg; + soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK_bit_cg LOCK_bit_cg[1]; + soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK_fld_cg fld_cg; rand uvm_reg_field LOCK; - function new(string name = "soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK"); + function new(string name = "soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); endfunction : new extern virtual function void sample_values(); @@ -1222,7 +1222,7 @@ package soc_ifc_reg_uvm; if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); endfunction : build - endclass : soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK + endclass : soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK // Reg - soc_ifc_reg::CPTRA_WDT_CFG class soc_ifc_reg__CPTRA_WDT_CFG extends uvm_reg; @@ -3731,10 +3731,10 @@ package soc_ifc_reg_uvm; rand soc_ifc_reg__CPTRA_FLOW_STATUS CPTRA_FLOW_STATUS; rand soc_ifc_reg__CPTRA_RESET_REASON CPTRA_RESET_REASON; rand soc_ifc_reg__CPTRA_SECURITY_STATE CPTRA_SECURITY_STATE; - rand soc_ifc_reg__CPTRA_MBOX_VALID_PAUSER CPTRA_MBOX_VALID_PAUSER[5]; - rand soc_ifc_reg__CPTRA_MBOX_PAUSER_LOCK CPTRA_MBOX_PAUSER_LOCK[5]; - rand soc_ifc_reg__CPTRA_TRNG_VALID_PAUSER CPTRA_TRNG_VALID_PAUSER; - rand soc_ifc_reg__CPTRA_TRNG_PAUSER_LOCK CPTRA_TRNG_PAUSER_LOCK; + rand soc_ifc_reg__CPTRA_MBOX_VALID_AXI_ID CPTRA_MBOX_VALID_AXI_ID[5]; + rand soc_ifc_reg__CPTRA_MBOX_AXI_ID_LOCK CPTRA_MBOX_AXI_ID_LOCK[5]; + rand soc_ifc_reg__CPTRA_TRNG_VALID_AXI_ID CPTRA_TRNG_VALID_AXI_ID; + rand soc_ifc_reg__CPTRA_TRNG_AXI_ID_LOCK CPTRA_TRNG_AXI_ID_LOCK; rand soc_ifc_reg__CPTRA_TRNG_DATA CPTRA_TRNG_DATA[12]; rand soc_ifc_reg__CPTRA_TRNG_CTRL CPTRA_TRNG_CTRL; rand soc_ifc_reg__CPTRA_TRNG_STATUS CPTRA_TRNG_STATUS; @@ -3755,8 +3755,8 @@ package soc_ifc_reg_uvm; rand soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL CPTRA_WDT_TIMER2_CTRL; rand soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[2]; rand soc_ifc_reg__CPTRA_WDT_STATUS CPTRA_WDT_STATUS; - rand soc_ifc_reg__CPTRA_FUSE_VALID_PAUSER CPTRA_FUSE_VALID_PAUSER; - rand soc_ifc_reg__CPTRA_FUSE_PAUSER_LOCK CPTRA_FUSE_PAUSER_LOCK; + rand soc_ifc_reg__CPTRA_FUSE_VALID_AXI_ID CPTRA_FUSE_VALID_AXI_ID; + rand soc_ifc_reg__CPTRA_FUSE_AXI_ID_LOCK CPTRA_FUSE_AXI_ID_LOCK; rand soc_ifc_reg__CPTRA_WDT_CFG CPTRA_WDT_CFG[2]; rand soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0 CPTRA_iTRNG_ENTROPY_CONFIG_0; rand soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1 CPTRA_iTRNG_ENTROPY_CONFIG_1; @@ -3853,30 +3853,30 @@ package soc_ifc_reg_uvm; this.CPTRA_SECURITY_STATE.build(); this.default_map.add_reg(this.CPTRA_SECURITY_STATE, 'h44); - foreach(this.CPTRA_MBOX_VALID_PAUSER[i0]) begin - this.CPTRA_MBOX_VALID_PAUSER[i0] = new($sformatf("CPTRA_MBOX_VALID_PAUSER[%0d]", i0)); - this.CPTRA_MBOX_VALID_PAUSER[i0].configure(this); + foreach(this.CPTRA_MBOX_VALID_AXI_ID[i0]) begin + this.CPTRA_MBOX_VALID_AXI_ID[i0] = new($sformatf("CPTRA_MBOX_VALID_AXI_ID[%0d]", i0)); + this.CPTRA_MBOX_VALID_AXI_ID[i0].configure(this); - this.CPTRA_MBOX_VALID_PAUSER[i0].build(); - this.default_map.add_reg(this.CPTRA_MBOX_VALID_PAUSER[i0], 'h48 + i0*'h4); + this.CPTRA_MBOX_VALID_AXI_ID[i0].build(); + this.default_map.add_reg(this.CPTRA_MBOX_VALID_AXI_ID[i0], 'h48 + i0*'h4); end - foreach(this.CPTRA_MBOX_PAUSER_LOCK[i0]) begin - this.CPTRA_MBOX_PAUSER_LOCK[i0] = new($sformatf("CPTRA_MBOX_PAUSER_LOCK[%0d]", i0)); - this.CPTRA_MBOX_PAUSER_LOCK[i0].configure(this); + foreach(this.CPTRA_MBOX_AXI_ID_LOCK[i0]) begin + this.CPTRA_MBOX_AXI_ID_LOCK[i0] = new($sformatf("CPTRA_MBOX_AXI_ID_LOCK[%0d]", i0)); + this.CPTRA_MBOX_AXI_ID_LOCK[i0].configure(this); - this.CPTRA_MBOX_PAUSER_LOCK[i0].build(); - this.default_map.add_reg(this.CPTRA_MBOX_PAUSER_LOCK[i0], 'h5c + i0*'h4); + this.CPTRA_MBOX_AXI_ID_LOCK[i0].build(); + this.default_map.add_reg(this.CPTRA_MBOX_AXI_ID_LOCK[i0], 'h5c + i0*'h4); end - this.CPTRA_TRNG_VALID_PAUSER = new("CPTRA_TRNG_VALID_PAUSER"); - this.CPTRA_TRNG_VALID_PAUSER.configure(this); + this.CPTRA_TRNG_VALID_AXI_ID = new("CPTRA_TRNG_VALID_AXI_ID"); + this.CPTRA_TRNG_VALID_AXI_ID.configure(this); - this.CPTRA_TRNG_VALID_PAUSER.build(); - this.default_map.add_reg(this.CPTRA_TRNG_VALID_PAUSER, 'h70); - this.CPTRA_TRNG_PAUSER_LOCK = new("CPTRA_TRNG_PAUSER_LOCK"); - this.CPTRA_TRNG_PAUSER_LOCK.configure(this); + this.CPTRA_TRNG_VALID_AXI_ID.build(); + this.default_map.add_reg(this.CPTRA_TRNG_VALID_AXI_ID, 'h70); + this.CPTRA_TRNG_AXI_ID_LOCK = new("CPTRA_TRNG_AXI_ID_LOCK"); + this.CPTRA_TRNG_AXI_ID_LOCK.configure(this); - this.CPTRA_TRNG_PAUSER_LOCK.build(); - this.default_map.add_reg(this.CPTRA_TRNG_PAUSER_LOCK, 'h74); + this.CPTRA_TRNG_AXI_ID_LOCK.build(); + this.default_map.add_reg(this.CPTRA_TRNG_AXI_ID_LOCK, 'h74); foreach(this.CPTRA_TRNG_DATA[i0]) begin this.CPTRA_TRNG_DATA[i0] = new($sformatf("CPTRA_TRNG_DATA[%0d]", i0)); this.CPTRA_TRNG_DATA[i0].configure(this); @@ -3989,16 +3989,16 @@ package soc_ifc_reg_uvm; this.CPTRA_WDT_STATUS.build(); this.default_map.add_reg(this.CPTRA_WDT_STATUS, 'h104); - this.CPTRA_FUSE_VALID_PAUSER = new("CPTRA_FUSE_VALID_PAUSER"); - this.CPTRA_FUSE_VALID_PAUSER.configure(this); + this.CPTRA_FUSE_VALID_AXI_ID = new("CPTRA_FUSE_VALID_AXI_ID"); + this.CPTRA_FUSE_VALID_AXI_ID.configure(this); - this.CPTRA_FUSE_VALID_PAUSER.build(); - this.default_map.add_reg(this.CPTRA_FUSE_VALID_PAUSER, 'h108); - this.CPTRA_FUSE_PAUSER_LOCK = new("CPTRA_FUSE_PAUSER_LOCK"); - this.CPTRA_FUSE_PAUSER_LOCK.configure(this); + this.CPTRA_FUSE_VALID_AXI_ID.build(); + this.default_map.add_reg(this.CPTRA_FUSE_VALID_AXI_ID, 'h108); + this.CPTRA_FUSE_AXI_ID_LOCK = new("CPTRA_FUSE_AXI_ID_LOCK"); + this.CPTRA_FUSE_AXI_ID_LOCK.configure(this); - this.CPTRA_FUSE_PAUSER_LOCK.build(); - this.default_map.add_reg(this.CPTRA_FUSE_PAUSER_LOCK, 'h10c); + this.CPTRA_FUSE_AXI_ID_LOCK.build(); + this.default_map.add_reg(this.CPTRA_FUSE_AXI_ID_LOCK, 'h10c); foreach(this.CPTRA_WDT_CFG[i0]) begin this.CPTRA_WDT_CFG[i0] = new($sformatf("CPTRA_WDT_CFG[%0d]", i0)); this.CPTRA_WDT_CFG[i0].configure(this); diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv index 119ebacc5..288fc346c 100644 --- a/src/soc_ifc/rtl/soc_ifc_top.sv +++ b/src/soc_ifc/rtl/soc_ifc_top.sv @@ -20,9 +20,10 @@ module soc_ifc_top import soc_ifc_pkg::*; import soc_ifc_reg_pkg::*; #( - parameter APB_ADDR_WIDTH = 18 - ,parameter APB_DATA_WIDTH = 32 - ,parameter APB_USER_WIDTH = 32 + parameter AXI_ADDR_WIDTH = 18 + ,parameter AXI_DATA_WIDTH = 32 + ,parameter AXI_ID_WIDTH = 32 + ,parameter AXI_USER_WIDTH = 32 ,parameter AHB_ADDR_WIDTH = 18 ,parameter AHB_DATA_WIDTH = 32 ) @@ -49,16 +50,20 @@ module soc_ifc_top input logic BootFSM_BrkPoint, output logic [1:0][31:0] generic_output_wires, - //SoC APB Interface - input logic [APB_ADDR_WIDTH-1:0] paddr_i, - input logic psel_i, - input logic penable_i, - input logic pwrite_i, - input logic [APB_DATA_WIDTH-1:0] pwdata_i, - input logic [APB_USER_WIDTH-1:0] pauser_i, - output logic pready_o, - output logic [APB_DATA_WIDTH-1:0] prdata_o, - output logic pslverr_o, + //SoC AXI Interface + axi_if.w_sub s_axi_w_if, + axi_if.r_sub s_axi_r_if, + +// //SoC APB Interface +// input logic [APB_ADDR_WIDTH-1:0] paddr_i, +// input logic psel_i, +// input logic penable_i, +// input logic pwrite_i, +// input logic [APB_DATA_WIDTH-1:0] pwdata_i, +// input logic [APB_USER_WIDTH-1:0] pauser_i, +// output logic pready_o, +// output logic [APB_DATA_WIDTH-1:0] prdata_o, +// output logic pslverr_o, //uC AHB Lite Interface input logic [AHB_ADDR_WIDTH-1:0] haddr_i, @@ -130,7 +135,7 @@ module soc_ifc_top //gasket to assemble mailbox request logic soc_req_dv, soc_req_hold; logic soc_req_error; -logic [APB_DATA_WIDTH-1:0] soc_req_rdata; +logic [AXI_DATA_WIDTH-1:0] soc_req_rdata; soc_ifc_req_t soc_req; //gasket to assemble mailbox request @@ -168,7 +173,7 @@ logic [MBOX_ADDR_W-1:0] sha_sram_req_addr; mbox_sram_resp_t sha_sram_resp; logic sha_sram_hold; -logic [4:0][APB_USER_WIDTH-1:0] valid_mbox_users; +logic [4:0][AXI_ID_WIDTH-1:0] valid_mbox_ids; // Pulse signals to trigger interrupts logic uc_mbox_data_avail; @@ -183,7 +188,7 @@ logic sram_double_ecc_error; logic soc_req_mbox_lock; logic [1:0] generic_input_toggle; mbox_protocol_error_t mbox_protocol_error; -logic mbox_inv_user_p; +logic mbox_inv_id_p; logic iccm_unlock; logic fw_upd_rst_executed; @@ -224,8 +229,8 @@ logic t2_timeout_p; logic wdt_error_t1_intr_serviced; logic wdt_error_t2_intr_serviced; -logic valid_trng_user; -logic valid_fuse_user; +logic valid_trng_id; +logic valid_fuse_id; boot_fsm_state_e boot_fsm_ps; @@ -260,42 +265,41 @@ soc_ifc_boot_fsm i_soc_ifc_boot_fsm ( always_comb soc_ifc_reg_hwif_in.CPTRA_RESET_REASON.FW_UPD_RESET.we = fw_upd_rst_executed; always_comb soc_ifc_reg_hwif_in.CPTRA_RESET_REASON.FW_UPD_RESET.next = 1; -//APB Interface -//This module contains the logic for interfacing with the SoC over the APB Interface -//The SoC sends read and write requests using APB Protocol -//This wrapper decodes that protocol and issues requests to the arbitration block -apb_slv_sif #( - .ADDR_WIDTH(APB_ADDR_WIDTH), - .DATA_WIDTH(APB_DATA_WIDTH), - .USER_WIDTH(APB_USER_WIDTH) -) -i_apb_slv_sif_soc_ifc ( - //AMBA APB INF - .PCLK(soc_ifc_clk_cg), - .PRESETn(cptra_noncore_rst_b), - .PADDR(paddr_i), - .PPROT('0), - .PSEL(psel_i), - .PENABLE(penable_i), - .PWRITE(pwrite_i), - .PWDATA(pwdata_i), - .PAUSER(pauser_i), - - .PREADY(pready_o), - .PSLVERR(pslverr_o), - .PRDATA(prdata_o), +//AXI Interface +//This module contains the logic for interfacing with the SoC over the AXI Interface +//The SoC sends read and write requests using AXI Protocol +//This wrapper decodes that protocol, collapses the full-duplex protocol to +// simplex, and issues requests to the soc_ifc arbitration block +axi_sub #( + .AW (AXI_ADDR_WIDTH), + .DW (AXI_DATA_WIDTH), + .UW (AXI_USER_WIDTH), + .IW (AXI_ID_WIDTH ), + .EX_EN(0 ), + .C_LAT(0 ) +) i_axi_sub_sif_soc_ifc ( + .clk (soc_ifc_clk_cg ), + .rst_n(cptra_noncore_rst_b), + + // AXI INF + .s_axi_w_if(s_axi_w_if), + .s_axi_r_if(s_axi_r_if), //COMPONENT INF - .dv(soc_req_dv), - .req_hold(soc_req_hold), + .dv (soc_req_dv ), + .addr (soc_req.addr ), // Byte address .write(soc_req.write), - .user(soc_req.user), - .wdata(soc_req.wdata), - .addr(soc_req.addr), - .slverr(soc_req_error), - .rdata(soc_req_rdata) + .user (/*soc_req.user*/), + .id (soc_req.id ), + .wdata(soc_req.wdata), // Requires: Component dwidth == AXI dwidth + .wstrb(soc_req.wstrb), // Requires: Component dwidth == AXI dwidth + .rdata(soc_req_rdata), // Requires: Component dwidth == AXI dwidth + .last ( ), // Asserted with final 'dv' of a burst + .hld (soc_req_hold ), + .err (soc_req_error) ); -//req from apb is for soc always + +//req from axi is for soc always always_comb soc_req.soc_req = 1'b1; //AHB-Lite Interface @@ -335,7 +339,8 @@ i_ahb_slv_sif_soc_ifc ( .rdata(uc_req_rdata) ); -always_comb uc_req.user = '1; +//always_comb uc_req.user = '1; +always_comb uc_req.id = '1; always_comb uc_req.soc_req = 1'b0; //mailbox_arb @@ -343,13 +348,13 @@ always_comb uc_req.soc_req = 1'b0; //Requests are serviced using round robin arbitration soc_ifc_arb #( - .APB_USER_WIDTH(APB_USER_WIDTH) + .AXI_ID_WIDTH(AXI_ID_WIDTH) ) i_soc_ifc_arb ( .clk(soc_ifc_clk_cg), .rst_b(cptra_noncore_rst_b), - .valid_mbox_users(valid_mbox_users), - .valid_fuse_user(valid_fuse_user), + .valid_mbox_ids(valid_mbox_ids), + .valid_fuse_id(valid_fuse_id), //UC inf .uc_req_dv(uc_req_dv), .uc_req_hold(uc_req_hold), @@ -546,27 +551,27 @@ end always_comb scan_mode_p = scan_mode & ~scan_mode_f; -//Filtering by PAUSER +//Filtering by ID always_comb begin for (int i=0; i<5; i++) begin //once locked, can't be cleared until reset - soc_ifc_reg_hwif_in.CPTRA_MBOX_PAUSER_LOCK[i].LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_PAUSER_LOCK[i].LOCK.value; - //lock the writes to valid user field once lock is set - soc_ifc_reg_hwif_in.CPTRA_MBOX_VALID_PAUSER[i].PAUSER.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_PAUSER_LOCK[i].LOCK.value; - //If integrator set PAUSER values at integration time, pick it up from the define - valid_mbox_users[i] = CPTRA_SET_MBOX_PAUSER_INTEG[i] ? CPTRA_MBOX_VALID_PAUSER[i][APB_USER_WIDTH-1:0] : - soc_ifc_reg_hwif_out.CPTRA_MBOX_PAUSER_LOCK[i].LOCK.value ? - soc_ifc_reg_hwif_out.CPTRA_MBOX_VALID_PAUSER[i].PAUSER.value[APB_USER_WIDTH-1:0] : CPTRA_DEF_MBOX_VALID_PAUSER; + soc_ifc_reg_hwif_in.CPTRA_MBOX_AXI_ID_LOCK[i].LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_ID_LOCK[i].LOCK.value; + //lock the writes to valid id field once lock is set + soc_ifc_reg_hwif_in.CPTRA_MBOX_VALID_AXI_ID[i].AXI_ID.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_ID_LOCK[i].LOCK.value; + //If integrator set AXI_ID values at integration time, pick it up from the define + valid_mbox_ids[i] = CPTRA_SET_MBOX_AXI_ID_INTEG[i] ? CPTRA_MBOX_VALID_AXI_ID[i][AXI_ID_WIDTH-1:0] : + soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_ID_LOCK[i].LOCK.value ? + soc_ifc_reg_hwif_out.CPTRA_MBOX_VALID_AXI_ID[i].AXI_ID.value[AXI_ID_WIDTH-1:0] : CPTRA_DEF_MBOX_VALID_AXI_ID; end end -//can't write to trng valid user after it is locked -always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_VALID_PAUSER.PAUSER.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_PAUSER_LOCK.LOCK.value; -always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_PAUSER_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_PAUSER_LOCK.LOCK.value; +//can't write to trng valid id after it is locked +always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value; +always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_AXI_ID_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value; -//fuse register pauser fields -always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_VALID_PAUSER.PAUSER.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_PAUSER_LOCK.LOCK.value; -always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_PAUSER_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_PAUSER_LOCK.LOCK.value; +//fuse register AXI ID fields +always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value; +always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_AXI_ID_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value; ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Can't write to RW-able fuses once fuse_done is set (implies the register is being locked using the fuse_wr_done) @@ -622,16 +627,16 @@ always_comb soc_ifc_reg_hwif_in.fuse_soc_stepping_id.soc_stepping_id.swwel = soc always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_WR_DONE.done.swwe = soc_ifc_reg_req_data.soc_req & ~soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value; ///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//When TRNG_PAUSER_LOCK is one only allow valid users to write to TRNG -//If TRNG_PAUSER_LOCK is zero allow any user to write to TRNG -always_comb valid_trng_user = soc_ifc_reg_req_data.soc_req & (~soc_ifc_reg_hwif_out.CPTRA_TRNG_PAUSER_LOCK.LOCK.value | - (soc_ifc_reg_req_data.user == soc_ifc_reg_hwif_out.CPTRA_TRNG_VALID_PAUSER.PAUSER.value[APB_USER_WIDTH-1:0])); +//When TRNG_AXI_ID_LOCK is one only allow valid ids to write to TRNG +//If TRNG_AXI_ID_LOCK is zero allow any id to write to TRNG +always_comb valid_trng_id = soc_ifc_reg_req_data.soc_req & (~soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value | + (soc_ifc_reg_req_data.id == soc_ifc_reg_hwif_out.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value[AXI_ID_WIDTH-1:0])); -always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_STATUS.DATA_WR_DONE.swwe = valid_trng_user; +always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_STATUS.DATA_WR_DONE.swwe = valid_trng_id; always_comb begin for (int i = 0; i < 12; i++) begin - soc_ifc_reg_hwif_in.CPTRA_TRNG_DATA[i].DATA.swwe = valid_trng_user; + soc_ifc_reg_hwif_in.CPTRA_TRNG_DATA[i].DATA.swwe = valid_trng_id; soc_ifc_reg_hwif_in.CPTRA_TRNG_DATA[i].DATA.hwclr = soc_ifc_reg_hwif_out.CPTRA_TRNG_CTRL.clear.value; end end @@ -640,11 +645,11 @@ end always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_STATUS.DATA_WR_DONE.hwclr = ~soc_ifc_reg_hwif_out.CPTRA_TRNG_STATUS.DATA_REQ.value; generate - if (CPTRA_SET_FUSE_PAUSER_INTEG) begin - always_comb valid_fuse_user = soc_req_dv & (soc_req.user == CPTRA_FUSE_VALID_PAUSER); + if (CPTRA_SET_FUSE_AXI_ID_INTEG) begin + always_comb valid_fuse_id = soc_req_dv & (soc_req.id == CPTRA_FUSE_VALID_AXI_ID); end else begin - always_comb valid_fuse_user = soc_req_dv & (~soc_ifc_reg_hwif_out.CPTRA_FUSE_PAUSER_LOCK.LOCK.value | - (soc_req.user == soc_ifc_reg_hwif_out.CPTRA_FUSE_VALID_PAUSER.PAUSER.value[APB_USER_WIDTH-1:0])); + always_comb valid_fuse_id = soc_req_dv & (~soc_ifc_reg_hwif_out.CPTRA_FUSE_AXI_ID_LOCK.LOCK.value | + (soc_req.id == soc_ifc_reg_hwif_out.CPTRA_FUSE_VALID_AXI_ID.AXI_ID.value[AXI_ID_WIDTH-1:0])); end endgenerate // Generate a pulse to set the interrupt bit @@ -660,7 +665,7 @@ end always_comb uc_cmd_avail_p = uc_mbox_data_avail & !uc_mbox_data_avail_d; // Pulse input to soc_ifc_reg to set the interrupt status bit and generate interrupt output (if enabled) always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset = 1'b0; // TODO -always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.hwset = mbox_inv_user_p; // All invalid users, or only 'valid user but != mbox_user.user'? +always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.hwset = mbox_inv_id_p; // All invalid ids, or only 'valid id but != mbox_id.id'? always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.hwset = |mbox_protocol_error; // Set by any protocol error violation (mirrors the bits in CPTRA_HW_ERROR_NON_FATAL) always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.hwset = 1'b0; // TODO always_comb soc_ifc_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.hwset = iccm_axs_blocked; @@ -705,13 +710,13 @@ soc_ifc_reg i_soc_ifc_reg ( .hwif_out(soc_ifc_reg_hwif_out) ); -//Mask read data to TRNG DATA when TRNG PAUSER is locked and the requester isn't the correct PAUSER +//Mask read data to TRNG DATA when TRNG AXI_ID is locked and the requester isn't the correct AXI_ID always_comb begin soc_ifc_reg_rdata_mask = 0; for (int i = 0; i < 12; i++) begin soc_ifc_reg_rdata_mask |= soc_ifc_reg_req_data.soc_req & soc_ifc_reg_hwif_out.CPTRA_TRNG_DATA[i].DATA.swacc & - soc_ifc_reg_hwif_out.CPTRA_TRNG_PAUSER_LOCK.LOCK.value & - (soc_ifc_reg_req_data.user != soc_ifc_reg_hwif_out.CPTRA_TRNG_VALID_PAUSER.PAUSER.value[APB_USER_WIDTH-1:0]); + soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_ID_LOCK.LOCK.value & + (soc_ifc_reg_req_data.id != soc_ifc_reg_hwif_out.CPTRA_TRNG_VALID_AXI_ID.AXI_ID.value[AXI_ID_WIDTH-1:0]); end end @@ -786,7 +791,7 @@ assign timer_intr = {soc_ifc_reg_hwif_out.internal_rv_mtime_h.count_h.value //SHA Accelerator sha512_acc_top #( - .DATA_WIDTH(APB_DATA_WIDTH) + .DATA_WIDTH(AXI_DATA_WIDTH) ) i_sha512_acc_top ( .clk(soc_ifc_clk_cg), @@ -839,7 +844,7 @@ i_mbox ( .uc_mbox_data_avail(uc_mbox_data_avail), .soc_req_mbox_lock(soc_req_mbox_lock), .mbox_protocol_error(mbox_protocol_error), - .mbox_inv_pauser_axs(mbox_inv_user_p), + .mbox_inv_axi_id_axs(mbox_inv_id_p), .dmi_inc_rdptr(dmi_inc_rdptr), .dmi_reg(mbox_dmi_reg) ); @@ -990,6 +995,11 @@ always_ff @(posedge rdc_clk_cg or negedge cptra_pwrgood) begin end end +`CALIPTRA_ASSERT (AXI_SUB_DATA_WIDTH, SOC_IFC_ADDR_W == AXI_ADDR_WIDTH, clk, !cptra_noncore_rst_b) +`CALIPTRA_ASSERT (AXI_SUB_DATA_WIDTH, SOC_IFC_DATA_W == AXI_DATA_WIDTH, clk, !cptra_noncore_rst_b) +`CALIPTRA_ASSERT (AXI_SUB_DATA_WIDTH, SOC_IFC_USER_W == AXI_USER_WIDTH, clk, !cptra_noncore_rst_b) +`CALIPTRA_ASSERT (AXI_SUB_DATA_WIDTH, SOC_IFC_ID_W == AXI_ID_WIDTH, clk, !cptra_noncore_rst_b) + `CALIPTRA_ASSERT_KNOWN(ERR_AHB_INF_X, {hreadyout_o,hresp_o}, clk, !cptra_noncore_rst_b) //this generates an NMI in the core, but we don't have a handler so it just hangs `CALIPTRA_ASSERT_NEVER(ERR_SOC_IFC_AHB_ERR, hresp_o, clk, !cptra_noncore_rst_b)