From c8aa4673b2564d952e51549ef93b6539d9c0a65f Mon Sep 17 00:00:00 2001 From: Michael Norris <108370498+Nitsirks@users.noreply.github.com> Date: Fri, 26 Apr 2024 14:13:30 -0700 Subject: [PATCH] Additional round of lint cleanup (#483) * Issue 445 LINT fixes * initial round of lint fixes * removing lint blackboxes removed packed struct post processing from generated reg files. cast width of dynamic shifts to make lint happy casting some arithmetic widths, math parameter widths etc * removing change from other lint pr branch, not sure where it came from. * fixing lint errors from LMS changes * rolling back packed struct removal enabling lint on integrated TRNG files fixes for integrated TRNG lint violations * updating reg files with latest version of reg gen * fixing script so it detects endpackage correctly * scrubbing enums in generated reg pkg files * NVDA Lint Fixes on top of main_lint_regress branch * matching number of bits on RHS of AND mask equation * Rename uses of keywords 'NULL', 'WAIT', 'Wait' * Cast address offset (constant) to addr_width for lint * Explicit types for localparams in VeeR * Change localparam types from 2-state to 4-state logic in csrng * Add 'unsigned' qualifier * Convert more localparam int to localparam logic [31:0] * Change module params from 2-state to 4-state logic in csrng * Cast a 33-bit expression as 32-bit (drop the carry bit) * Cast literal constant as unsigned for lint * rolling back change to modport to adhere to SV spec * fix to dmi reg data width lint violation * Regenerated reg macro files without ending newline * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/lint_fix' with updated timestamp and hash after successful run --------- Co-authored-by: Matthew Border Co-authored-by: Michael Norris Co-authored-by: Avirup Mullick Co-authored-by: Michael Norris Co-authored-by: Caleb Whitehead --- .github/workflow_metadata/pr_hash | 2 +- .github/workflow_metadata/pr_timestamp | 2 +- src/aes/config/compile.yml | 4 + src/aes/rtl/aes_pkg.sv | 2 +- src/aes/rtl/aes_reg_pkg.sv | 2 +- .../rtl/caliptra_prim_packer_fifo.sv | 2 +- src/caliptra_prim/rtl/caliptra_prim_pkg.sv | 2 +- .../rtl/caliptra_prim_util_pkg.sv | 24 +- src/csrng/config/compile.yml | 5 + src/csrng/rtl/csrng.sv | 2 +- src/csrng/rtl/csrng_block_encrypt.sv | 14 +- src/csrng/rtl/csrng_cmd_stage.sv | 20 +- src/csrng/rtl/csrng_core.sv | 42 +- src/csrng/rtl/csrng_ctr_drbg_cmd.sv | 26 +- src/csrng/rtl/csrng_ctr_drbg_gen.sv | 36 +- src/csrng/rtl/csrng_ctr_drbg_upd.sv | 40 +- src/csrng/rtl/csrng_pkg.sv | 10 +- src/csrng/rtl/csrng_reg_pkg.sv | 6 +- src/csrng/rtl/csrng_reg_top.sv | 6 +- src/csrng/rtl/csrng_state_db.sv | 20 +- src/datavault/config/compile.yml | 2 - src/datavault/rtl/dv_reg.sv | 111 +- src/datavault/rtl/dv_reg_pkg.sv | 4 + src/doe/config/compile.yml | 2 - src/doe/rtl/doe_fsm.sv | 2 +- src/doe/rtl/doe_reg.sv | 483 +++-- src/doe/rtl/doe_reg_pkg.sv | 31 +- src/ecc/config/compile.yml | 2 - src/ecc/rtl/ecc_add_sub_mod_alter.sv | 2 +- src/ecc/rtl/ecc_dsa_ctrl.sv | 16 +- src/ecc/rtl/ecc_dsa_sequencer.sv | 2 +- src/ecc/rtl/ecc_dsa_uop_pkg.sv | 6 +- src/ecc/rtl/ecc_hmac_drbg_interface.sv | 8 +- src/ecc/rtl/ecc_pm_ctrl.sv | 14 +- src/ecc/rtl/ecc_pm_sequencer.sv | 2 +- src/ecc/rtl/ecc_reg.sv | 533 +++-- src/ecc/rtl/ecc_reg_pkg.sv | 46 +- src/entropy_src/config/compile.yml | 5 + src/entropy_src/rtl/entropy_src_ack_sm.sv | 4 +- src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv | 6 +- src/entropy_src/rtl/entropy_src_reg_pkg.sv | 2 +- .../rtl/entropy_src_watermark_reg.sv | 33 +- src/hmac/config/compile.yml | 2 - src/hmac/rtl/hmac_core.v | 4 +- src/hmac/rtl/hmac_ctrl.sv | 10 +- src/hmac/rtl/hmac_reg.sv | 679 +++--- src/hmac/rtl/hmac_reg_pkg.sv | 58 +- src/hmac_drbg/rtl/hmac_drbg.sv | 14 +- src/integration/asserts/caliptra_top_sva.sv | 44 +- src/integration/config/compile.yml | 4 +- src/integration/rtl/caliptra_top.sv | 1 + src/keyvault/config/compile.yml | 2 - src/keyvault/rtl/kv.sv | 4 +- src/keyvault/rtl/kv_fsm.sv | 27 +- src/keyvault/rtl/kv_reg.sv | 111 +- src/keyvault/rtl/kv_reg_pkg.sv | 4 + src/kmac/config/compile.yml | 4 + src/kmac/rtl/keccak_2share.sv | 12 +- src/pcrvault/config/compile.yml | 2 - src/pcrvault/rtl/pv_gen_hash.sv | 1 + src/pcrvault/rtl/pv_reg.sv | 67 +- src/pcrvault/rtl/pv_reg_pkg.sv | 4 + src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv | 2 +- .../veer_el2/rtl/dec/el2_dec_decode_ctl.sv | 2 +- .../veer_el2/rtl/dec/el2_dec_tlu_ctl.sv | 3 +- src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv | 13 +- src/riscv_core/veer_el2/rtl/el2_mem.sv | 2 + src/riscv_core/veer_el2/rtl/el2_pdef.vh | 344 +-- .../veer_el2/rtl/el2_veer_wrapper.sv | 59 + .../veer_el2/rtl/exu/el2_exu_alu_ctl.sv | 2 +- .../veer_el2/rtl/exu/el2_exu_mul_ctl.sv | 32 +- .../veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv | 8 +- .../veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv | 2 +- .../veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv | 55 +- .../veer_el2/rtl/include/el2_def.sv | 2 +- .../veer_el2/rtl/lib/axi4_to_ahb.sv | 2 +- src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv | 2 +- .../veer_el2/rtl/lsu/el2_lsu_addrcheck.sv | 68 +- .../veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv | 24 +- .../veer_el2/rtl/lsu/el2_lsu_bus_intf.sv | 2 +- .../veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv | 4 +- .../veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv | 6 +- .../veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv | 2 +- src/sha256/config/compile.yml | 2 - src/sha256/rtl/sha256.sv | 10 +- src/sha256/rtl/sha256_ctrl.sv | 12 +- src/sha256/rtl/sha256_reg.sv | 232 +- src/sha512/config/compile.yml | 2 - src/sha512/rtl/sha512.sv | 2 +- src/sha512/rtl/sha512_core.v | 2 +- src/sha512/rtl/sha512_ctrl.sv | 12 +- src/sha512/rtl/sha512_h_constants.v | 2 +- src/sha512/rtl/sha512_k_constants.v | 2 +- src/sha512/rtl/sha512_reg.sv | 681 +++--- src/sha512/rtl/sha512_reg_pkg.sv | 52 +- src/sha512_masked/config/compile.yml | 2 - src/sha512_masked/rtl/sha512_masked_core.sv | 2 +- src/soc_ifc/config/compile.yml | 9 - src/soc_ifc/rtl/caliptra_top_reg.h | 2 +- src/soc_ifc/rtl/caliptra_top_reg_defines.svh | 2 +- src/soc_ifc/rtl/mbox.sv | 25 +- src/soc_ifc/rtl/mbox_csr.sv | 177 +- src/soc_ifc/rtl/mbox_csr_pkg.sv | 69 +- src/soc_ifc/rtl/sha512_acc_csr.sv | 571 ++--- src/soc_ifc/rtl/sha512_acc_csr_pkg.sv | 31 +- src/soc_ifc/rtl/sha512_acc_top.sv | 4 +- src/soc_ifc/rtl/soc_ifc_reg.sv | 1878 ++++++++++------- src/soc_ifc/rtl/soc_ifc_reg_pkg.sv | 66 +- src/soc_ifc/rtl/soc_ifc_top.sv | 12 +- src/spi_host/rtl/spi_host_reg_pkg.sv | 2 +- src/uart/rtl/uart_reg_pkg.sv | 2 +- tools/scripts/rdl_post_process.py | 5 + tools/scripts/reg_gen.py | 3 +- 113 files changed, 4191 insertions(+), 2955 deletions(-) diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash index 7c6d65bf3..20f0e5170 100644 --- a/.github/workflow_metadata/pr_hash +++ b/.github/workflow_metadata/pr_hash @@ -1 +1 @@ -6cd6271af5cc73b4c69623c0fb3354d0d211b459c36b1c0820075afadd8ce3eda9f3f4c0e50ae2f8b96f2e74b837f94b \ No newline at end of file +2feeef5876321043dcbc1134f4143038d5c6b0588afbc56a44f3886ee264908e10650c88c85aa2e9e0ba9b6e8969be99 \ No newline at end of file diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp index 35f9d0732..74eb568cd 100644 --- a/.github/workflow_metadata/pr_timestamp +++ b/.github/workflow_metadata/pr_timestamp @@ -1 +1 @@ -1714005956 \ No newline at end of file +1714158756 \ No newline at end of file diff --git a/src/aes/config/compile.yml b/src/aes/config/compile.yml index fc4379b07..445d407e6 100644 --- a/src/aes/config/compile.yml +++ b/src/aes/config/compile.yml @@ -39,3 +39,7 @@ targets: - $COMPILE_ROOT/rtl/aes_prng_masking.sv - $COMPILE_ROOT/rtl/aes_key_expand.sv tops: [aes_cipher_core] + rtl_lint: + directories: [] + waiver_files: [] + tops: [aes_cipher_core] diff --git a/src/aes/rtl/aes_pkg.sv b/src/aes/rtl/aes_pkg.sv index 170be20f2..1ec439032 100644 --- a/src/aes/rtl/aes_pkg.sv +++ b/src/aes/rtl/aes_pkg.sv @@ -68,7 +68,7 @@ parameter masking_lfsr_perm_t RndCnstMaskingLfsrPermDefault = { 256'h808d419d63982a16995e0e3b57826a36718a9329452492533d83115a75316e15 }; -typedef enum integer { +typedef enum logic [31:0] { SBoxImplLut, // Unmasked LUT-based S-Box SBoxImplCanright, // Unmasked Canright S-Box, see aes_sbox_canright.sv SBoxImplCanrightMasked, // First-order masked Canright S-Box diff --git a/src/aes/rtl/aes_reg_pkg.sv b/src/aes/rtl/aes_reg_pkg.sv index 657bc046a..d3b3d4b7d 100644 --- a/src/aes/rtl/aes_reg_pkg.sv +++ b/src/aes/rtl/aes_reg_pkg.sv @@ -336,7 +336,7 @@ package aes_reg_pkg; parameter logic [0:0] AES_CTRL_SHADOWED_MANUAL_OPERATION_RESVAL = 1'h 0; // Register index - typedef enum int { + typedef enum logic [31:0] { AES_ALERT_TEST, AES_KEY_SHARE0_0, AES_KEY_SHARE0_1, diff --git a/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv b/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv index 24fdd1429..7f0b2d364 100644 --- a/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv +++ b/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv @@ -132,7 +132,7 @@ module caliptra_prim_packer_fifo #( assign lsb_is_one = {{DepthW{1'b0}},1'b1}; assign max_value = FullDepth; - assign rdata_shifted = data_q >> ptr_q*OutW; + assign rdata_shifted = MaxW'(data_q >> ptr_q*OutW); assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q; assign clear_data = (ClearOnRead && clear_status) || clr_q; assign load_data = wvalid_i && wready_o; diff --git a/src/caliptra_prim/rtl/caliptra_prim_pkg.sv b/src/caliptra_prim/rtl/caliptra_prim_pkg.sv index 97242c359..2d69a31dc 100755 --- a/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +++ b/src/caliptra_prim/rtl/caliptra_prim_pkg.sv @@ -9,7 +9,7 @@ package caliptra_prim_pkg; // Implementation target specialization - typedef enum integer { + typedef enum logic [31:0] { ImplGeneric, ImplXilinx, ImplBadbit diff --git a/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv b/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv index 4a6f7c7a9..df441ca70 100644 --- a/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv +++ b/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv @@ -25,17 +25,19 @@ package caliptra_prim_util_pkg; * vector value. The argument shall be treated as an unsigned * value, and an argument value of 0 shall produce a result of 0. */ - function automatic integer _clog2(integer value); - integer result; - // Use an intermediate value to avoid assigning to an input port, which produces a warning in - // Synopsys DC. - integer v = value; - v = v - 1; - for (result = 0; v > 0; result++) begin - v = v >> 1; - end - return result; - endfunction + + //Function causing LINT errors. Not used in current codebase + //deprecated and replaced by $clog2() //function automatic integer _clog2(integer value); + //deprecated and replaced by $clog2() // integer result; + //deprecated and replaced by $clog2() // Use an intermediate value to avoid assigning to an input port, which produces a warning in + //deprecated and replaced by $clog2() // Synopsys DC. + //deprecated and replaced by $clog2() // integer v = value; + //deprecated and replaced by $clog2() // v = v - 1; + //deprecated and replaced by $clog2() // for (result = 0; v > 0; result++) begin + //deprecated and replaced by $clog2() // v = v >> 1; + //deprecated and replaced by $clog2() // end + //deprecated and replaced by $clog2() // return result; + //deprecated and replaced by $clog2() //endfunction /** diff --git a/src/csrng/config/compile.yml b/src/csrng/config/compile.yml index 146c5653c..ebd6e931d 100644 --- a/src/csrng/config/compile.yml +++ b/src/csrng/config/compile.yml @@ -41,6 +41,11 @@ targets: - $COMPILE_ROOT/rtl/csrng_cmd_stage.sv - $COMPILE_ROOT/rtl/csrng.sv tops: [csrng] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/csrng/config/design_lint/sglint_waivers + tops: [csrng] --- provides: [csrng_tb] schema_version: 2.4.0 diff --git a/src/csrng/rtl/csrng.sv b/src/csrng/rtl/csrng.sv index f19303187..c2b4cc191 100644 --- a/src/csrng/rtl/csrng.sv +++ b/src/csrng/rtl/csrng.sv @@ -15,7 +15,7 @@ module csrng #( parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplCanright, parameter logic [csrng_reg_pkg::NumAlerts-1:0] AlertAsyncOn = {csrng_reg_pkg::NumAlerts{1'b1}}, - parameter int NHwApps = 2, + parameter logic [31:0] NHwApps = 2, parameter cs_keymgr_div_t RndCnstCsKeymgrDivNonProduction = CsKeymgrDivWidth'(0), parameter cs_keymgr_div_t RndCnstCsKeymgrDivProduction = CsKeymgrDivWidth'(0), parameter AHBDataWidth = 64, diff --git a/src/csrng/rtl/csrng_block_encrypt.sv b/src/csrng/rtl/csrng_block_encrypt.sv index a05152b65..73c890149 100644 --- a/src/csrng/rtl/csrng_block_encrypt.sv +++ b/src/csrng/rtl/csrng_block_encrypt.sv @@ -7,10 +7,10 @@ module csrng_block_encrypt import csrng_pkg::*; #( parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplLut, - parameter int Cmd = 3, - parameter int StateId = 4, - parameter int BlkLen = 128, - parameter int KeyLen = 256 + parameter logic [31:0] Cmd = 3, + parameter logic [31:0] StateId = 4, + parameter logic [31:0] BlkLen = 128, + parameter logic [31:0] KeyLen = 256 ) ( input logic clk_i, input logic rst_ni, @@ -33,9 +33,9 @@ module csrng_block_encrypt import csrng_pkg::*; #( output logic [2:0] block_encrypt_sfifo_blkenc_err_o ); - localparam int BlkEncFifoDepth = 1; - localparam int BlkEncFifoWidth = StateId+Cmd; - localparam int NumShares = 1; + localparam logic[31:0] BlkEncFifoDepth = 1; + localparam logic[31:0] BlkEncFifoWidth = StateId+Cmd; + localparam logic[31:0] NumShares = 1; // signals // blk_encrypt_in fifo diff --git a/src/csrng/rtl/csrng_cmd_stage.sv b/src/csrng/rtl/csrng_cmd_stage.sv index f62311e79..580ae2081 100644 --- a/src/csrng/rtl/csrng_cmd_stage.sv +++ b/src/csrng/rtl/csrng_cmd_stage.sv @@ -6,9 +6,9 @@ // module csrng_cmd_stage import csrng_pkg::*; #( - parameter int CmdFifoWidth = 32, - parameter int CmdFifoDepth = 16, - parameter int StateId = 4 + parameter logic [31:0] CmdFifoWidth = 32, + parameter logic [31:0] CmdFifoDepth = 16, + parameter logic [31:0] StateId = 4 ) ( input logic clk_i, input logic rst_ni, @@ -48,9 +48,9 @@ module csrng_cmd_stage import csrng_pkg::*; #( ); // Genbits parameters. - localparam int GenBitsFifoWidth = 1+128; - localparam int GenBitsFifoDepth = 1; - localparam int GenBitsCntrWidth = 13; + localparam logic[31:0] GenBitsFifoWidth = 1+128; + localparam logic[31:0] GenBitsFifoDepth = 1; + localparam logic[31:0] GenBitsCntrWidth = 13; // Command FIFO. logic [CmdFifoWidth-1:0] sfifo_cmd_rdata; @@ -191,7 +191,7 @@ module csrng_cmd_stage import csrng_pkg::*; #( .set_cnt_i(sfifo_cmd_rdata[24:12]), .incr_en_i(1'b0), .decr_en_i(cmd_gen_cnt_dec), // Count down. - .step_i(GenBitsCntrWidth'(1)), + .step_i(GenBitsCntrWidth'(unsigned'(1))), .cnt_o(cmd_gen_cnt), .cnt_next_o(), .err_o(cmd_gen_cnt_err_o) @@ -224,7 +224,7 @@ module csrng_cmd_stage import csrng_pkg::*; #( // Minimum Hamming weight: 1 // Maximum Hamming weight: 7 // - localparam int StateWidth = 8; + localparam logic[31:0] StateWidth = 8; typedef enum logic [StateWidth-1:0] { Idle = 8'b00011011, // idle ArbGnt = 8'b11110101, // general arbiter request @@ -285,7 +285,7 @@ module csrng_cmd_stage import csrng_pkg::*; #( cmd_gen_1st_req = 1'b1; cmd_arb_sop_o = 1'b1; cmd_fifo_pop = 1'b1; - if (sfifo_cmd_rdata[24:12] == GenBitsCntrWidth'(1)) begin + if (sfifo_cmd_rdata[24:12] == GenBitsCntrWidth'(unsigned'(1))) begin cmd_gen_cnt_last = 1'b1; end if (cmd_len == '0) begin @@ -350,7 +350,7 @@ module csrng_cmd_stage import csrng_pkg::*; #( cmd_gen_inc_req = 1'b1; state_d = GenCmdChk; // Check for final genbits beat. - if (cmd_gen_cnt == GenBitsCntrWidth'(1)) begin + if (cmd_gen_cnt == GenBitsCntrWidth'(unsigned'(1))) begin cmd_gen_cnt_last = 1'b1; end end diff --git a/src/csrng/rtl/csrng_core.sv b/src/csrng/rtl/csrng_core.sv index e28c30048..c703a6ffb 100644 --- a/src/csrng/rtl/csrng_core.sv +++ b/src/csrng/rtl/csrng_core.sv @@ -13,7 +13,7 @@ module csrng_core import lc_ctrl_pkg::*; #( parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplLut, - parameter int NHwApps = 2, + parameter logic [31:0] NHwApps = 2, parameter cs_keymgr_div_t RndCnstCsKeymgrDivNonProduction = CsKeymgrDivWidth'(0), parameter cs_keymgr_div_t RndCnstCsKeymgrDivProduction = CsKeymgrDivWidth'(0) ) ( @@ -60,26 +60,26 @@ module csrng_core import caliptra_prim_mubi_pkg::mubi4_test_true_strict; import caliptra_prim_mubi_pkg::mubi4_test_invalid; - localparam int NApps = NHwApps + 1; - localparam int AppCmdWidth = 32; - localparam int AppCmdFifoDepth = 2; - localparam int GenBitsWidth = 128; - localparam int Cmd = 3; - localparam int StateId = 4; - localparam int KeyLen = 256; - localparam int BlkLen = 128; - localparam int SeedLen = 384; - localparam int CtrLen = 32; - localparam int NBlkEncArbReqs = 2; - localparam int BlkEncArbWidth = KeyLen+BlkLen+StateId+Cmd; - localparam int NUpdateArbReqs = 2; - localparam int UpdateArbWidth = KeyLen+BlkLen+SeedLen+StateId+Cmd; - localparam int MaxClen = 12; - localparam int ADataDepthWidth = SeedLen/AppCmdWidth; - localparam unsigned ADataDepthClog = $clog2(ADataDepthWidth)+1; - localparam int CsEnableCopies = 53; - localparam int LcHwDebugCopies = 1; - localparam int Flag0Copies = 3; + localparam logic [31:0] NApps = NHwApps + 1; + localparam logic [31:0] AppCmdWidth = 32; + localparam logic [31:0] AppCmdFifoDepth = 2; + localparam logic [31:0] GenBitsWidth = 128; + localparam logic [31:0] Cmd = 3; + localparam logic [31:0] StateId = 4; + localparam logic [31:0] KeyLen = 256; + localparam logic [31:0] BlkLen = 128; + localparam logic [31:0] SeedLen = 384; + localparam logic [31:0] CtrLen = 32; + localparam logic [31:0] NBlkEncArbReqs = 2; + localparam logic [31:0] BlkEncArbWidth = KeyLen+BlkLen+StateId+Cmd; + localparam logic [31:0] NUpdateArbReqs = 2; + localparam logic [31:0] UpdateArbWidth = KeyLen+BlkLen+SeedLen+StateId+Cmd; + localparam logic [31:0] MaxClen = 12; + localparam logic [31:0] ADataDepthWidth = SeedLen/AppCmdWidth; + localparam logic [31:0] ADataDepthClog = $clog2(ADataDepthWidth)+1; + localparam logic [31:0] CsEnableCopies = 53; + localparam logic [31:0] LcHwDebugCopies = 1; + localparam logic [31:0] Flag0Copies = 3; // signals // interrupt signals diff --git a/src/csrng/rtl/csrng_ctr_drbg_cmd.sv b/src/csrng/rtl/csrng_ctr_drbg_cmd.sv index 567cbbf24..33228fe23 100644 --- a/src/csrng/rtl/csrng_ctr_drbg_cmd.sv +++ b/src/csrng/rtl/csrng_ctr_drbg_cmd.sv @@ -7,12 +7,12 @@ // Accepts all csrng commands module csrng_ctr_drbg_cmd import csrng_pkg::*; #( - parameter int Cmd = 3, - parameter int StateId = 4, - parameter int BlkLen = 128, - parameter int KeyLen = 256, - parameter int SeedLen = 384, - parameter int CtrLen = 32 + parameter logic [31:0] Cmd = 3, + parameter logic [31:0] StateId = 4, + parameter logic [31:0] BlkLen = 128, + parameter logic [31:0] KeyLen = 256, + parameter logic [31:0] SeedLen = 384, + parameter logic [31:0] CtrLen = 32 ) ( input logic clk_i, input logic rst_ni, @@ -65,12 +65,12 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; #( output logic [2:0] ctr_drbg_cmd_sfifo_keyvrc_err_o ); - localparam int CmdreqFifoDepth = 1; - localparam int CmdreqFifoWidth = KeyLen+BlkLen+CtrLen+1+2*SeedLen+1+StateId+Cmd; - localparam int RCStageFifoDepth = 1; - localparam int RCStageFifoWidth = KeyLen+BlkLen+StateId+CtrLen+1+SeedLen+1+Cmd; - localparam int KeyVRCFifoDepth = 1; - localparam int KeyVRCFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+1+StateId+Cmd; + localparam logic[31:0] CmdreqFifoDepth = 1; + localparam logic[31:0] CmdreqFifoWidth = KeyLen+BlkLen+CtrLen+1+2*SeedLen+1+StateId+Cmd; + localparam logic[31:0] RCStageFifoDepth = 1; + localparam logic[31:0] RCStageFifoWidth = KeyLen+BlkLen+StateId+CtrLen+1+SeedLen+1+Cmd; + localparam logic[31:0] KeyVRCFifoDepth = 1; + localparam logic[31:0] KeyVRCFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+1+StateId+Cmd; // signals @@ -319,7 +319,7 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; #( assign ctr_drbg_cmd_ack_o = sfifo_keyvrc_pop; assign ctr_drbg_cmd_sts_o = sfifo_keyvrc_pop && (ctr_drbg_cmd_ccmd_o == UNI) && - ((KeyLen == '0) && (BlkLen == '0) && (CtrLen == '0)); + ((KeyLen == unsigned'(0)) && (BlkLen == unsigned'(0)) && (CtrLen == unsigned'(0))); endmodule diff --git a/src/csrng/rtl/csrng_ctr_drbg_gen.sv b/src/csrng/rtl/csrng_ctr_drbg_gen.sv index 66aed6132..70ddf1c79 100644 --- a/src/csrng/rtl/csrng_ctr_drbg_gen.sv +++ b/src/csrng/rtl/csrng_ctr_drbg_gen.sv @@ -9,13 +9,13 @@ // ctr_drbg cmd module. module csrng_ctr_drbg_gen import csrng_pkg::*; #( - parameter int NApps = 4, - parameter int Cmd = 3, - parameter int StateId = 4, - parameter int BlkLen = 128, - parameter int KeyLen = 256, - parameter int SeedLen = 384, - parameter int CtrLen = 32 + parameter logic [31:0] NApps = 4, + parameter logic [31:0] Cmd = 3, + parameter logic [31:0] StateId = 4, + parameter logic [31:0] BlkLen = 128, + parameter logic [31:0] KeyLen = 256, + parameter logic [31:0] SeedLen = 384, + parameter logic [31:0] CtrLen = 32 ) ( input logic clk_i, input logic rst_ni, @@ -85,16 +85,16 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #( output logic ctr_drbg_gen_sm_err_o ); - localparam int GenreqFifoDepth = 1; - localparam int GenreqFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+1+StateId+Cmd; - localparam int BlkEncAckFifoDepth = 1; - localparam int BlkEncAckFifoWidth = BlkLen+StateId+Cmd; - localparam int AdstageFifoDepth = 1; - localparam int AdstageFifoWidth = KeyLen+BlkLen+CtrLen+1+1; - localparam int RCStageFifoDepth = 1; - localparam int RCStageFifoWidth = KeyLen+BlkLen+BlkLen+CtrLen+1+1+StateId+Cmd; - localparam int GenbitsFifoDepth = 1; - localparam int GenbitsFifoWidth = 1+BlkLen+KeyLen+BlkLen+CtrLen+StateId+Cmd; + localparam logic[31:0] GenreqFifoDepth = 1; + localparam logic[31:0] GenreqFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+1+StateId+Cmd; + localparam logic[31:0] BlkEncAckFifoDepth = 1; + localparam logic[31:0] BlkEncAckFifoWidth = BlkLen+StateId+Cmd; + localparam logic[31:0] AdstageFifoDepth = 1; + localparam logic[31:0] AdstageFifoWidth = KeyLen+BlkLen+CtrLen+1+1; + localparam logic[31:0] RCStageFifoDepth = 1; + localparam logic[31:0] RCStageFifoWidth = KeyLen+BlkLen+BlkLen+CtrLen+1+1+StateId+Cmd; + localparam logic[31:0] GenbitsFifoDepth = 1; + localparam logic[31:0] GenbitsFifoWidth = 1+BlkLen+KeyLen+BlkLen+CtrLen+StateId+Cmd; // signals logic [Cmd-1:0] genreq_ccmd; @@ -205,7 +205,7 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #( // Maximum Hamming weight: 3 // - localparam int StateWidth = 5; + localparam logic[31:0] StateWidth = 5; typedef enum logic [StateWidth-1:0] { ReqIdle = 5'b01101, ReqSend = 5'b00011, diff --git a/src/csrng/rtl/csrng_ctr_drbg_upd.sv b/src/csrng/rtl/csrng_ctr_drbg_upd.sv index 8e5320b4a..9317df51b 100644 --- a/src/csrng/rtl/csrng_ctr_drbg_upd.sv +++ b/src/csrng/rtl/csrng_ctr_drbg_upd.sv @@ -7,12 +7,12 @@ // implementation using security_strength = 256 module csrng_ctr_drbg_upd #( - parameter int Cmd = 3, - parameter int StateId = 4, - parameter int BlkLen = 128, - parameter int KeyLen = 256, - parameter int SeedLen = 384, - parameter int CtrLen = 32 + parameter logic [31:0] Cmd = 3, + parameter logic [31:0] StateId = 4, + parameter logic [31:0] BlkLen = 128, + parameter logic [31:0] KeyLen = 256, + parameter logic [31:0] SeedLen = 384, + parameter logic [31:0] CtrLen = 32 ) ( input logic clk_i, input logic rst_ni, @@ -59,16 +59,16 @@ module csrng_ctr_drbg_upd #( output logic ctr_drbg_updob_sm_err_o ); - localparam int UpdReqFifoDepth = 1; - localparam int UpdReqFifoWidth = KeyLen+BlkLen+SeedLen+StateId+Cmd; - localparam int BlkEncReqFifoDepth = 1; - localparam int BlkEncReqFifoWidth = KeyLen+BlkLen+StateId+Cmd; - localparam int BlkEncAckFifoDepth = 1; - localparam int BlkEncAckFifoWidth = BlkLen+StateId+Cmd; - localparam int PDataFifoDepth = 1; - localparam int PDataFifoWidth = SeedLen; - localparam int FinalFifoDepth = 1; - localparam int FinalFifoWidth = KeyLen+BlkLen+StateId+Cmd; + localparam logic[31:0] UpdReqFifoDepth = 1; + localparam logic[31:0] UpdReqFifoWidth = KeyLen+BlkLen+SeedLen+StateId+Cmd; + localparam logic[31:0] BlkEncReqFifoDepth = 1; + localparam logic[31:0] BlkEncReqFifoWidth = KeyLen+BlkLen+StateId+Cmd; + localparam logic[31:0] BlkEncAckFifoDepth = 1; + localparam logic[31:0] BlkEncAckFifoWidth = BlkLen+StateId+Cmd; + localparam logic[31:0] PDataFifoDepth = 1; + localparam logic[31:0] PDataFifoWidth = SeedLen; + localparam logic[31:0] FinalFifoDepth = 1; + localparam logic[31:0] FinalFifoWidth = KeyLen+BlkLen+StateId+Cmd; // signals logic [SeedLen-1:0] updated_key_and_v; @@ -173,7 +173,7 @@ module csrng_ctr_drbg_upd #( // Maximum Hamming weight: 3 // - localparam int BlkEncStateWidth = 5; + localparam logic[31:0] BlkEncStateWidth = 5; typedef enum logic [BlkEncStateWidth-1:0] { ReqIdle = 5'b11000, ReqSend = 5'b10011, @@ -207,7 +207,7 @@ module csrng_ctr_drbg_upd #( // Maximum Hamming weight: 4 // - localparam int OutBlkStateWidth = 6; + localparam logic[31:0] OutBlkStateWidth = 6; typedef enum logic [OutBlkStateWidth-1:0] { AckIdle = 6'b110110, Load = 6'b110001, @@ -312,7 +312,7 @@ module csrng_ctr_drbg_upd #( interate_ctr_inc ? (interate_ctr_q + 1) : interate_ctr_q; - assign interate_ctr_done = (int'(interate_ctr_q) >= SeedLen/BlkLen); + assign interate_ctr_done = (32'(interate_ctr_q) >= SeedLen/BlkLen); //-------------------------------------------- // state machine to send values to block_encrypt @@ -507,7 +507,7 @@ module csrng_ctr_drbg_upd #( concat_ctr_inc ? (concat_ctr_q + 1) : concat_ctr_q; - assign concat_ctr_done = (int'(concat_ctr_q) >= (SeedLen/BlkLen)); + assign concat_ctr_done = (32'(concat_ctr_q) >= (SeedLen/BlkLen)); assign concat_inst_id_d = (!ctr_drbg_upd_enable_i) ? '0 : diff --git a/src/csrng/rtl/csrng_pkg.sv b/src/csrng/rtl/csrng_pkg.sv index 43636c060..7792c1300 100644 --- a/src/csrng/rtl/csrng_pkg.sv +++ b/src/csrng/rtl/csrng_pkg.sv @@ -9,11 +9,11 @@ package csrng_pkg; // Application Interfaces //------------------------- - parameter int unsigned GENBITS_BUS_WIDTH = 128; - parameter int unsigned CSRNG_CMD_WIDTH = 32; - parameter int unsigned FIPS_GENBITS_BUS_WIDTH = entropy_src_pkg::FIPS_BUS_WIDTH + + parameter logic [31:0] GENBITS_BUS_WIDTH = 128; + parameter logic [31:0] CSRNG_CMD_WIDTH = 32; + parameter logic [31:0] FIPS_GENBITS_BUS_WIDTH = entropy_src_pkg::FIPS_BUS_WIDTH + GENBITS_BUS_WIDTH; - parameter int unsigned MainSmStateWidth = 8; + parameter logic [31:0] MainSmStateWidth = 8; // instantiation interface typedef struct packed { @@ -85,7 +85,7 @@ package csrng_pkg; MainSmError = 8'b01111000 // error state, results in fatal alert } main_sm_state_e; - parameter int CsKeymgrDivWidth = 384; + parameter logic [31:0] CsKeymgrDivWidth = 384; typedef logic [CsKeymgrDivWidth-1:0] cs_keymgr_div_t; endpackage : csrng_pkg diff --git a/src/csrng/rtl/csrng_reg_pkg.sv b/src/csrng/rtl/csrng_reg_pkg.sv index aedce98b7..c9037ad1f 100644 --- a/src/csrng/rtl/csrng_reg_pkg.sv +++ b/src/csrng/rtl/csrng_reg_pkg.sv @@ -7,10 +7,10 @@ package csrng_reg_pkg; // Param list - parameter int NumAlerts = 2; + parameter logic [31:0] NumAlerts = 2; // Address widths within the block - parameter int BlockAw = 7; + parameter logic [31:0] BlockAw = 7; //////////////////////////// // Typedefs for registers // @@ -364,7 +364,7 @@ package csrng_reg_pkg; parameter logic [31:0] CSRNG_INT_STATE_VAL_RESVAL = 32'h 0; // Register index - typedef enum int { + typedef enum logic [31:0] { CSRNG_INTR_STATE, CSRNG_INTR_ENABLE, CSRNG_INTR_TEST, diff --git a/src/csrng/rtl/csrng_reg_top.sv b/src/csrng/rtl/csrng_reg_top.sv index 45086aee3..1648975c3 100644 --- a/src/csrng/rtl/csrng_reg_top.sv +++ b/src/csrng/rtl/csrng_reg_top.sv @@ -38,9 +38,9 @@ module csrng_reg_top #( import csrng_reg_pkg::*; - localparam int AW = 7; - localparam int DW = 32; - localparam int DBW = DW/8; // Byte Width + localparam logic[31:0] AW = 7; + localparam logic[31:0] DW = 32; + localparam logic[31:0] DBW = DW/8; // Byte Width // ahb interface register signals logic ahb_reg_dv; diff --git a/src/csrng/rtl/csrng_state_db.sv b/src/csrng/rtl/csrng_state_db.sv index 034304bba..2bac7b79b 100644 --- a/src/csrng/rtl/csrng_state_db.sv +++ b/src/csrng/rtl/csrng_state_db.sv @@ -10,12 +10,12 @@ `include "caliptra_prim_assert.sv" module csrng_state_db import csrng_pkg::*; #( - parameter int NApps = 4, - parameter int StateId = 4, - parameter int BlkLen = 128, - parameter int KeyLen = 256, - parameter int CtrLen = 32, - parameter int Cmd = 3 + parameter logic [31:0] NApps = 4, + parameter logic [31:0] StateId = 4, + parameter logic [31:0] BlkLen = 128, + parameter logic [31:0] KeyLen = 256, + parameter logic [31:0] CtrLen = 32, + parameter logic [31:0] Cmd = 3 ) ( input logic clk_i, input logic rst_ni, @@ -49,10 +49,10 @@ module csrng_state_db import csrng_pkg::*; #( output logic [StateId-1:0] state_db_sts_id_o ); - localparam int InternalStateWidth = 2+KeyLen+BlkLen+CtrLen; - localparam int RegInternalStateWidth = 30+InternalStateWidth; - localparam int RegW = 32; - localparam int StateWidth = 1+1+KeyLen+BlkLen+CtrLen+StateId+1; + localparam logic[31:0] InternalStateWidth = 2+KeyLen+BlkLen+CtrLen; + localparam logic[31:0] RegInternalStateWidth = 30+InternalStateWidth; + localparam logic[31:0] RegW = 32; + localparam logic[31:0] StateWidth = 1+1+KeyLen+BlkLen+CtrLen+StateId+1; logic [StateId-1:0] state_db_id; logic [KeyLen-1:0] state_db_key; diff --git a/src/datavault/config/compile.yml b/src/datavault/config/compile.yml index d15f1319f..f22338e93 100644 --- a/src/datavault/config/compile.yml +++ b/src/datavault/config/compile.yml @@ -37,8 +37,6 @@ targets: directories: [] waiver_files: - $MSFT_REPO_ROOT/src/datavault/config/design_lint/datavault/sglint_waivers - black_box: - - dv_reg global: tool: vcs: diff --git a/src/datavault/rtl/dv_reg.sv b/src/datavault/rtl/dv_reg.sv index be6393cd6..3cf9a61b9 100644 --- a/src/datavault/rtl/dv_reg.sv +++ b/src/datavault/rtl/dv_reg.sv @@ -58,7 +58,9 @@ module dv_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -82,35 +84,35 @@ module dv_reg ( always_comb begin for(int i0=0; i0<10; i0++) begin - decoded_reg_strb.StickyDataVaultCtrl[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); + decoded_reg_strb.StickyDataVaultCtrl[i0] = cpuif_req_masked & (cpuif_addr == 11'h0 + i0*11'h4); end for(int i0=0; i0<10; i0++) begin for(int i1=0; i1<12; i1++) begin - decoded_reg_strb.STICKY_DATA_VAULT_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 'h28 + i0*'h30 + i1*'h4); + decoded_reg_strb.STICKY_DATA_VAULT_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 11'h28 + i0*11'h30 + i1*11'h4); end end for(int i0=0; i0<10; i0++) begin - decoded_reg_strb.DataVaultCtrl[i0] = cpuif_req_masked & (cpuif_addr == 'h208 + i0*'h4); + decoded_reg_strb.DataVaultCtrl[i0] = cpuif_req_masked & (cpuif_addr == 11'h208 + i0*11'h4); end for(int i0=0; i0<10; i0++) begin for(int i1=0; i1<12; i1++) begin - decoded_reg_strb.DATA_VAULT_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 'h230 + i0*'h30 + i1*'h4); + decoded_reg_strb.DATA_VAULT_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 11'h230 + i0*11'h30 + i1*11'h4); end end for(int i0=0; i0<10; i0++) begin - decoded_reg_strb.LockableScratchRegCtrl[i0] = cpuif_req_masked & (cpuif_addr == 'h410 + i0*'h4); + decoded_reg_strb.LockableScratchRegCtrl[i0] = cpuif_req_masked & (cpuif_addr == 11'h410 + i0*11'h4); end for(int i0=0; i0<10; i0++) begin - decoded_reg_strb.LockableScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 'h438 + i0*'h4); + decoded_reg_strb.LockableScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 11'h438 + i0*11'h4); end for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.NonStickyGenericScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 'h460 + i0*'h4); + decoded_reg_strb.NonStickyGenericScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 11'h460 + i0*11'h4); end for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.StickyLockableScratchRegCtrl[i0] = cpuif_req_masked & (cpuif_addr == 'h480 + i0*'h4); + decoded_reg_strb.StickyLockableScratchRegCtrl[i0] = cpuif_req_masked & (cpuif_addr == 11'h480 + i0*11'h4); end for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.StickyLockableScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 'h4a0 + i0*'h4); + decoded_reg_strb.StickyLockableScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 11'h4a0 + i0*11'h4); end end @@ -120,10 +122,6 @@ module dv_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -237,8 +235,10 @@ module dv_reg ( for(genvar i0=0; i0<10; i0++) begin // Field: dv_reg.StickyDataVaultCtrl[].lock_entry always_comb begin - automatic logic [0:0] next_c = field_storage.StickyDataVaultCtrl[i0].lock_entry.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.StickyDataVaultCtrl[i0].lock_entry.value; + load_next_c = '0; if(decoded_reg_strb.StickyDataVaultCtrl[i0] && decoded_req_is_wr && !(hwif_in.StickyDataVaultCtrl[i0].lock_entry.swwel)) begin // SW write next_c = (field_storage.StickyDataVaultCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -248,7 +248,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.StickyDataVaultCtrl[i0].lock_entry.value <= 'h0; + field_storage.StickyDataVaultCtrl[i0].lock_entry.value <= 1'h0; end else if(field_combo.StickyDataVaultCtrl[i0].lock_entry.load_next) begin field_storage.StickyDataVaultCtrl[i0].lock_entry.value <= field_combo.StickyDataVaultCtrl[i0].lock_entry.next; end @@ -259,8 +259,10 @@ module dv_reg ( for(genvar i1=0; i1<12; i1++) begin // Field: dv_reg.STICKY_DATA_VAULT_ENTRY[][].data always_comb begin - automatic logic [31:0] next_c = field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value; + load_next_c = '0; if(decoded_reg_strb.STICKY_DATA_VAULT_ENTRY[i0][i1] && decoded_req_is_wr && !(hwif_in.STICKY_DATA_VAULT_ENTRY[i0][i1].data.swwel)) begin // SW write next_c = (field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -270,7 +272,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value <= 'h0; + field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value <= 32'h0; end else if(field_combo.STICKY_DATA_VAULT_ENTRY[i0][i1].data.load_next) begin field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value <= field_combo.STICKY_DATA_VAULT_ENTRY[i0][i1].data.next; end @@ -280,8 +282,10 @@ module dv_reg ( for(genvar i0=0; i0<10; i0++) begin // Field: dv_reg.DataVaultCtrl[].lock_entry always_comb begin - automatic logic [0:0] next_c = field_storage.DataVaultCtrl[i0].lock_entry.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DataVaultCtrl[i0].lock_entry.value; + load_next_c = '0; if(decoded_reg_strb.DataVaultCtrl[i0] && decoded_req_is_wr && !(hwif_in.DataVaultCtrl[i0].lock_entry.swwel)) begin // SW write next_c = (field_storage.DataVaultCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -291,7 +295,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin if(~hwif_in.core_only_rst_b) begin - field_storage.DataVaultCtrl[i0].lock_entry.value <= 'h0; + field_storage.DataVaultCtrl[i0].lock_entry.value <= 1'h0; end else if(field_combo.DataVaultCtrl[i0].lock_entry.load_next) begin field_storage.DataVaultCtrl[i0].lock_entry.value <= field_combo.DataVaultCtrl[i0].lock_entry.next; end @@ -302,8 +306,10 @@ module dv_reg ( for(genvar i1=0; i1<12; i1++) begin // Field: dv_reg.DATA_VAULT_ENTRY[][].data always_comb begin - automatic logic [31:0] next_c = field_storage.DATA_VAULT_ENTRY[i0][i1].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DATA_VAULT_ENTRY[i0][i1].data.value; + load_next_c = '0; if(decoded_reg_strb.DATA_VAULT_ENTRY[i0][i1] && decoded_req_is_wr && !(hwif_in.DATA_VAULT_ENTRY[i0][i1].data.swwel)) begin // SW write next_c = (field_storage.DATA_VAULT_ENTRY[i0][i1].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -313,7 +319,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.DATA_VAULT_ENTRY[i0][i1].data.value <= 'h0; + field_storage.DATA_VAULT_ENTRY[i0][i1].data.value <= 32'h0; end else if(field_combo.DATA_VAULT_ENTRY[i0][i1].data.load_next) begin field_storage.DATA_VAULT_ENTRY[i0][i1].data.value <= field_combo.DATA_VAULT_ENTRY[i0][i1].data.next; end @@ -323,8 +329,10 @@ module dv_reg ( for(genvar i0=0; i0<10; i0++) begin // Field: dv_reg.LockableScratchRegCtrl[].lock_entry always_comb begin - automatic logic [0:0] next_c = field_storage.LockableScratchRegCtrl[i0].lock_entry.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.LockableScratchRegCtrl[i0].lock_entry.value; + load_next_c = '0; if(decoded_reg_strb.LockableScratchRegCtrl[i0] && decoded_req_is_wr && !(hwif_in.LockableScratchRegCtrl[i0].lock_entry.swwel)) begin // SW write next_c = (field_storage.LockableScratchRegCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -334,7 +342,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin if(~hwif_in.core_only_rst_b) begin - field_storage.LockableScratchRegCtrl[i0].lock_entry.value <= 'h0; + field_storage.LockableScratchRegCtrl[i0].lock_entry.value <= 1'h0; end else if(field_combo.LockableScratchRegCtrl[i0].lock_entry.load_next) begin field_storage.LockableScratchRegCtrl[i0].lock_entry.value <= field_combo.LockableScratchRegCtrl[i0].lock_entry.next; end @@ -344,8 +352,10 @@ module dv_reg ( for(genvar i0=0; i0<10; i0++) begin // Field: dv_reg.LockableScratchReg[].data always_comb begin - automatic logic [31:0] next_c = field_storage.LockableScratchReg[i0].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.LockableScratchReg[i0].data.value; + load_next_c = '0; if(decoded_reg_strb.LockableScratchReg[i0] && decoded_req_is_wr && !(hwif_in.LockableScratchReg[i0].data.swwel)) begin // SW write next_c = (field_storage.LockableScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -355,7 +365,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.LockableScratchReg[i0].data.value <= 'h0; + field_storage.LockableScratchReg[i0].data.value <= 32'h0; end else if(field_combo.LockableScratchReg[i0].data.load_next) begin field_storage.LockableScratchReg[i0].data.value <= field_combo.LockableScratchReg[i0].data.next; end @@ -364,8 +374,10 @@ module dv_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: dv_reg.NonStickyGenericScratchReg[].data always_comb begin - automatic logic [31:0] next_c = field_storage.NonStickyGenericScratchReg[i0].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.NonStickyGenericScratchReg[i0].data.value; + load_next_c = '0; if(decoded_reg_strb.NonStickyGenericScratchReg[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.NonStickyGenericScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -375,7 +387,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.NonStickyGenericScratchReg[i0].data.value <= 'h0; + field_storage.NonStickyGenericScratchReg[i0].data.value <= 32'h0; end else if(field_combo.NonStickyGenericScratchReg[i0].data.load_next) begin field_storage.NonStickyGenericScratchReg[i0].data.value <= field_combo.NonStickyGenericScratchReg[i0].data.next; end @@ -384,8 +396,10 @@ module dv_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: dv_reg.StickyLockableScratchRegCtrl[].lock_entry always_comb begin - automatic logic [0:0] next_c = field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value; + load_next_c = '0; if(decoded_reg_strb.StickyLockableScratchRegCtrl[i0] && decoded_req_is_wr && !(hwif_in.StickyLockableScratchRegCtrl[i0].lock_entry.swwel)) begin // SW write next_c = (field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -395,7 +409,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value <= 'h0; + field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value <= 1'h0; end else if(field_combo.StickyLockableScratchRegCtrl[i0].lock_entry.load_next) begin field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value <= field_combo.StickyLockableScratchRegCtrl[i0].lock_entry.next; end @@ -405,8 +419,10 @@ module dv_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: dv_reg.StickyLockableScratchReg[].data always_comb begin - automatic logic [31:0] next_c = field_storage.StickyLockableScratchReg[i0].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.StickyLockableScratchReg[i0].data.value; + load_next_c = '0; if(decoded_reg_strb.StickyLockableScratchReg[i0] && decoded_req_is_wr && !(hwif_in.StickyLockableScratchReg[i0].data.swwel)) begin // SW write next_c = (field_storage.StickyLockableScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -416,19 +432,28 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.StickyLockableScratchReg[i0].data.value <= 'h0; + field_storage.StickyLockableScratchReg[i0].data.value <= 32'h0; end else if(field_combo.StickyLockableScratchReg[i0].data.load_next) begin field_storage.StickyLockableScratchReg[i0].data.value <= field_combo.StickyLockableScratchReg[i0].data.next; end end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [304-1:0][31:0] readback_array; for(genvar i0=0; i0<10; i0++) begin @@ -483,4 +508,4 @@ module dv_reg ( `CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.hard_reset_b) -endmodule \ No newline at end of file +endmodule diff --git a/src/datavault/rtl/dv_reg_pkg.sv b/src/datavault/rtl/dv_reg_pkg.sv index ee3801467..10a491e9f 100644 --- a/src/datavault/rtl/dv_reg_pkg.sv +++ b/src/datavault/rtl/dv_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package dv_reg_pkg; + + localparam DV_REG_DATA_WIDTH = 32; + localparam DV_REG_MIN_ADDR_WIDTH = 11; + typedef struct packed{ logic swwel; } dv_reg__StickyDataVaultCtrl__lock_entry__in_t; diff --git a/src/doe/config/compile.yml b/src/doe/config/compile.yml index c2556d00d..8bf6ee765 100755 --- a/src/doe/config/compile.yml +++ b/src/doe/config/compile.yml @@ -39,8 +39,6 @@ targets: directories: [] waiver_files: - $MSFT_REPO_ROOT/src/doe/config/design_lint/doe_ctrl/sglint_waivers - black_box: - - doe_reg --- provides: [doe_cbc_tb] schema_version: 2.4.0 diff --git a/src/doe/rtl/doe_fsm.sv b/src/doe/rtl/doe_fsm.sv index f6f1a934f..c3e8a0d9e 100644 --- a/src/doe/rtl/doe_fsm.sv +++ b/src/doe/rtl/doe_fsm.sv @@ -147,7 +147,7 @@ always_comb begin : kv_doe_fsm dest_write_offset_nxt = dest_write_offset; flow_done = '0; - unique casez (kv_doe_fsm_ps) + unique case (kv_doe_fsm_ps) DOE_IDLE: begin if (arc_DOE_IDLE_DOE_INIT) kv_doe_fsm_ns = DOE_INIT; //assert flow done if a locked flow is attempted diff --git a/src/doe/rtl/doe_reg.sv b/src/doe/rtl/doe_reg.sv index 22c9ff0a8..377e1784e 100644 --- a/src/doe/rtl/doe_reg.sv +++ b/src/doe/rtl/doe_reg.sv @@ -58,7 +58,9 @@ module doe_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -97,29 +99,29 @@ module doe_reg ( always_comb begin for(int i0=0; i0<4; i0++) begin - decoded_reg_strb.DOE_IV[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); - end - decoded_reg_strb.DOE_CTRL = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.DOE_STATUS = cpuif_req_masked & (cpuif_addr == 'h14); - decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800); - decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804); - decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808); - decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h80c); - decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h810); - decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h814); - decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h818); - decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h81c); - decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h820); - decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h900); - decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h904); - decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h908); - decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h90c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980); - decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00); - decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04); - decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha08); - decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha0c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha10); + decoded_reg_strb.DOE_IV[i0] = cpuif_req_masked & (cpuif_addr == 12'h0 + i0*12'h4); + end + decoded_reg_strb.DOE_CTRL = cpuif_req_masked & (cpuif_addr == 12'h10); + decoded_reg_strb.DOE_STATUS = cpuif_req_masked & (cpuif_addr == 12'h14); + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h80c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h810); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h814); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h818); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h81c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h820); + decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h900); + decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h904); + decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h908); + decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h90c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h980); + decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha00); + decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha04); + decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha08); + decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha0c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha10); end // Pass down signals to next stage @@ -128,10 +130,6 @@ module doe_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -503,8 +501,10 @@ module doe_reg ( for(genvar i0=0; i0<4; i0++) begin // Field: doe_reg.DOE_IV[].IV always_comb begin - automatic logic [31:0] next_c = field_storage.DOE_IV[i0].IV.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DOE_IV[i0].IV.value; + load_next_c = '0; if(decoded_reg_strb.DOE_IV[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.DOE_IV[i0].IV.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -517,7 +517,7 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.DOE_IV[i0].IV.value <= 'h0; + field_storage.DOE_IV[i0].IV.value <= 32'h0; end else if(field_combo.DOE_IV[i0].IV.load_next) begin field_storage.DOE_IV[i0].IV.value <= field_combo.DOE_IV[i0].IV.next; end @@ -527,8 +527,10 @@ module doe_reg ( end // Field: doe_reg.DOE_CTRL.CMD always_comb begin - automatic logic [1:0] next_c = field_storage.DOE_CTRL.CMD.value; - automatic logic load_next_c = '0; + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DOE_CTRL.CMD.value; + load_next_c = '0; if(decoded_reg_strb.DOE_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.DOE_CTRL.CMD.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); load_next_c = '1; @@ -541,7 +543,7 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.DOE_CTRL.CMD.value <= 'h0; + field_storage.DOE_CTRL.CMD.value <= 2'h0; end else if(field_combo.DOE_CTRL.CMD.load_next) begin field_storage.DOE_CTRL.CMD.value <= field_combo.DOE_CTRL.CMD.next; end @@ -550,8 +552,10 @@ module doe_reg ( assign hwif_out.DOE_CTRL.CMD.swmod = decoded_reg_strb.DOE_CTRL && decoded_req_is_wr; // Field: doe_reg.DOE_CTRL.DEST always_comb begin - automatic logic [4:0] next_c = field_storage.DOE_CTRL.DEST.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DOE_CTRL.DEST.value; + load_next_c = '0; if(decoded_reg_strb.DOE_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.DOE_CTRL.DEST.value & ~decoded_wr_biten[6:2]) | (decoded_wr_data[6:2] & decoded_wr_biten[6:2]); load_next_c = '1; @@ -561,7 +565,7 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.DOE_CTRL.DEST.value <= 'h0; + field_storage.DOE_CTRL.DEST.value <= 5'h0; end else if(field_combo.DOE_CTRL.DEST.load_next) begin field_storage.DOE_CTRL.DEST.value <= field_combo.DOE_CTRL.DEST.next; end @@ -569,8 +573,10 @@ module doe_reg ( assign hwif_out.DOE_CTRL.DEST.value = field_storage.DOE_CTRL.DEST.value; // Field: doe_reg.DOE_STATUS.READY always_comb begin - automatic logic [0:0] next_c = field_storage.DOE_STATUS.READY.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DOE_STATUS.READY.value; + load_next_c = '0; if(hwif_in.DOE_STATUS.READY.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -583,15 +589,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.DOE_STATUS.READY.value <= 'h0; + field_storage.DOE_STATUS.READY.value <= 1'h0; end else if(field_combo.DOE_STATUS.READY.load_next) begin field_storage.DOE_STATUS.READY.value <= field_combo.DOE_STATUS.READY.next; end end // Field: doe_reg.DOE_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.DOE_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DOE_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.DOE_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -604,15 +612,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.DOE_STATUS.VALID.value <= 'h0; + field_storage.DOE_STATUS.VALID.value <= 1'h0; end else if(field_combo.DOE_STATUS.VALID.load_next) begin field_storage.DOE_STATUS.VALID.value <= field_combo.DOE_STATUS.VALID.next; end end // Field: doe_reg.DOE_STATUS.DEOBF_SECRETS_CLEARED always_comb begin - automatic logic [0:0] next_c = field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value; + load_next_c = '0; if(hwif_in.DOE_STATUS.DEOBF_SECRETS_CLEARED.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -622,15 +632,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value <= 'h0; + field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value <= 1'h0; end else if(field_combo.DOE_STATUS.DEOBF_SECRETS_CLEARED.load_next) begin field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value <= field_combo.DOE_STATUS.DEOBF_SECRETS_CLEARED.next; end end // Field: doe_reg.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -640,15 +652,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; end end // Field: doe_reg.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -658,15 +672,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; end end // Field: doe_reg.intr_block_rf.error_intr_en_r.error0_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error0_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -676,15 +692,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error0_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= field_combo.intr_block_rf.error_intr_en_r.error0_en.next; end end // Field: doe_reg.intr_block_rf.error_intr_en_r.error1_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error1_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -694,15 +712,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error1_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= field_combo.intr_block_rf.error_intr_en_r.error1_en.next; end end // Field: doe_reg.intr_block_rf.error_intr_en_r.error2_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error2_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -712,15 +732,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error2_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= field_combo.intr_block_rf.error_intr_en_r.error2_en.next; end end // Field: doe_reg.intr_block_rf.error_intr_en_r.error3_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error3_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -730,15 +752,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error3_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= field_combo.intr_block_rf.error_intr_en_r.error3_en.next; end end // Field: doe_reg.intr_block_rf.notif_intr_en_r.notif_cmd_done_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -748,25 +772,27 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.next; end end // Field: doe_reg.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; end @@ -775,18 +801,20 @@ module doe_reg ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: doe_reg.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; end @@ -795,9 +823,11 @@ module doe_reg ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: doe_reg.intr_block_rf.error_internal_intr_r.error0_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error0_sts.hwset) begin // HW Set @@ -812,16 +842,18 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error0_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error0_sts.next; end end // Field: doe_reg.intr_block_rf.error_internal_intr_r.error1_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error1_sts.hwset) begin // HW Set @@ -836,16 +868,18 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error1_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error1_sts.next; end end // Field: doe_reg.intr_block_rf.error_internal_intr_r.error2_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error2_sts.hwset) begin // HW Set @@ -860,16 +894,18 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error2_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error2_sts.next; end end // Field: doe_reg.intr_block_rf.error_internal_intr_r.error3_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error3_sts.hwset) begin // HW Set @@ -884,7 +920,7 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error3_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error3_sts.next; end @@ -896,9 +932,11 @@ module doe_reg ( || |(field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value & field_storage.intr_block_rf.error_intr_en_r.error3_en.value); // Field: doe_reg.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset) begin // HW Set @@ -913,7 +951,7 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.next; end @@ -922,12 +960,14 @@ module doe_reg ( |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value); // Field: doe_reg.intr_block_rf.error_intr_trig_r.error0_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -936,19 +976,21 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error0_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error0_trig.next; end end // Field: doe_reg.intr_block_rf.error_intr_trig_r.error1_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -957,19 +999,21 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error1_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error1_trig.next; end end // Field: doe_reg.intr_block_rf.error_intr_trig_r.error2_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -978,19 +1022,21 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error2_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error2_trig.next; end end // Field: doe_reg.intr_block_rf.error_intr_trig_r.error3_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -999,19 +1045,21 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error3_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error3_trig.next; end end // Field: doe_reg.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1020,31 +1068,33 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.next; end end // Field: doe_reg.intr_block_rf.error0_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error0_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error0_intr_count_r.cnt.next = next_c; @@ -1052,31 +1102,33 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error0_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= field_combo.intr_block_rf.error0_intr_count_r.cnt.next; end end // Field: doe_reg.intr_block_rf.error1_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error1_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error1_intr_count_r.cnt.next = next_c; @@ -1084,31 +1136,33 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error1_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= field_combo.intr_block_rf.error1_intr_count_r.cnt.next; end end // Field: doe_reg.intr_block_rf.error2_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error2_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error2_intr_count_r.cnt.next = next_c; @@ -1116,31 +1170,33 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error2_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= field_combo.intr_block_rf.error2_intr_count_r.cnt.next; end end // Field: doe_reg.intr_block_rf.error3_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error3_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error3_intr_count_r.cnt.next = next_c; @@ -1148,31 +1204,33 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error3_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= field_combo.intr_block_rf.error3_intr_count_r.cnt.next; end end // Field: doe_reg.intr_block_rf.notif_cmd_done_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next = next_c; @@ -1180,15 +1238,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next; end end // Field: doe_reg.intr_block_rf.error0_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; @@ -1197,27 +1257,29 @@ module doe_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next; end end // Field: doe_reg.intr_block_rf.error1_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; @@ -1226,27 +1288,29 @@ module doe_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next; end end // Field: doe_reg.intr_block_rf.error2_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; @@ -1255,27 +1319,29 @@ module doe_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next; end end // Field: doe_reg.intr_block_rf.error3_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; @@ -1284,27 +1350,29 @@ module doe_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next; end end // Field: doe_reg.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; @@ -1313,30 +1381,39 @@ module doe_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [25-1:0][31:0] readback_array; for(genvar i0=0; i0<4; i0++) begin @@ -1411,4 +1488,4 @@ module doe_reg ( `CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.cptra_pwrgood) -endmodule \ No newline at end of file +endmodule diff --git a/src/doe/rtl/doe_reg_pkg.sv b/src/doe/rtl/doe_reg_pkg.sv index e8d318c07..7da3e948b 100644 --- a/src/doe/rtl/doe_reg_pkg.sv +++ b/src/doe/rtl/doe_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package doe_reg_pkg; + + localparam DOE_REG_DATA_WIDTH = 32; + localparam DOE_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic hwclr; } doe_reg__DOE_IV__IV__in_t; @@ -50,33 +54,33 @@ package doe_reg_pkg; typedef struct packed{ logic hwset; - } doe_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t; + } doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } doe_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t; + } doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } doe_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t; + } doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } doe_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t; + } doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t; typedef struct packed{ - doe_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t error0_sts; - doe_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t error1_sts; - doe_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t error2_sts; - doe_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t error3_sts; + doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t error0_sts; + doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t error1_sts; + doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t error2_sts; + doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t error3_sts; } doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__in_t; typedef struct packed{ logic hwset; - } doe_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; + } doe_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; typedef struct packed{ - doe_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; + doe_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; } doe_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__in_t; typedef struct packed{ @@ -145,6 +149,13 @@ package doe_reg_pkg; doe_reg__intr_block_t__out_t intr_block_rf; } doe_reg__out_t; + typedef enum logic [31:0] { + doe_reg__DOE_CTRL__CMD__doe_cmd_e__DOE_IDLE = 'h0, + doe_reg__DOE_CTRL__CMD__doe_cmd_e__DOE_UDS = 'h1, + doe_reg__DOE_CTRL__CMD__doe_cmd_e__DOE_FE = 'h2, + doe_reg__DOE_CTRL__CMD__doe_cmd_e__DOE_CLEAR_OBF_SECRETS = 'h3 + } doe_reg__DOE_CTRL__CMD__doe_cmd_e_e; + localparam DOE_REG_ADDR_WIDTH = 32'd12; endpackage \ No newline at end of file diff --git a/src/ecc/config/compile.yml b/src/ecc/config/compile.yml index 92b109284..cdaeba6d6 100755 --- a/src/ecc/config/compile.yml +++ b/src/ecc/config/compile.yml @@ -41,8 +41,6 @@ targets: directories: [] waiver_files: - $MSFT_REPO_ROOT/src/ecc/config/design_lint/ecc_top/sglint_waivers - black_box: - - ecc_reg --- provides: [ecc_top_tb] schema_version: 2.4.0 diff --git a/src/ecc/rtl/ecc_add_sub_mod_alter.sv b/src/ecc/rtl/ecc_add_sub_mod_alter.sv index 2bf3eb332..ae11bcbe6 100644 --- a/src/ecc/rtl/ecc_add_sub_mod_alter.sv +++ b/src/ecc/rtl/ecc_add_sub_mod_alter.sv @@ -105,7 +105,7 @@ module ecc_add_sub_mod_alter #( else if (add_en_i) push_result_reg <= 2'b10; else // one shift to right - push_result_reg <= (push_result_reg >> 1); + push_result_reg <= 2'(push_result_reg >> 1); end assign ready_o = push_result_reg[0]; diff --git a/src/ecc/rtl/ecc_dsa_ctrl.sv b/src/ecc/rtl/ecc_dsa_ctrl.sv index 46a186e33..bb82bb795 100644 --- a/src/ecc/rtl/ecc_dsa_ctrl.sv +++ b/src/ecc/rtl/ecc_dsa_ctrl.sv @@ -297,7 +297,7 @@ module ecc_dsa_ctrl always_comb begin : SCA_config - scalar_out_reg = (sca_scalar_rnd_en)? scalar_out : (scalar_in_reg << RND_SIZE); + scalar_out_reg = (sca_scalar_rnd_en)? scalar_out : (REG_SIZE+RND_SIZE)'(scalar_in_reg << RND_SIZE); lambda_reg = (sca_point_rnd_en)? lambda : ONE_CONST; masking_rnd_reg = (sca_mask_sign_en)? masking_rnd : ZERO_CONST; end // SCA_config @@ -536,7 +536,7 @@ module ecc_dsa_ctrl hw_verify_r_we = 0; hw_pk_chk_we = 0; if ((prog_instr.opcode == DSA_UOP_RD_CORE) & (cycle_cnt == 0)) begin - unique casez (prog_instr.reg_id) + unique case (prog_instr.reg_id) PRIVKEY_ID : hw_privkey_we = 1; PUBKEYX_ID : hw_pubkeyx_we = 1; PUBKEYY_ID : hw_pubkeyy_we = 1; @@ -569,7 +569,7 @@ module ecc_dsa_ctrl begin : write_to_pm_core write_reg = '0; if (prog_instr.opcode == DSA_UOP_WR_CORE) begin - unique casez (prog_instr.reg_id) + unique case (prog_instr.reg_id) CONST_ZERO_ID : write_reg = {zero_pad, ZERO_CONST}; CONST_ONE_ID : write_reg = {zero_pad, ONE_CONST}; CONST_E_a_MONT_ID : write_reg = {zero_pad, E_a_MONT}; @@ -594,9 +594,9 @@ module ecc_dsa_ctrl endcase end else if (prog_instr.opcode == DSA_UOP_WR_SCALAR) begin - unique casez (prog_instr.reg_id) - SCALAR_PK_ID : write_reg = (scalar_PK_reg << RND_SIZE); - SCALAR_G_ID : write_reg = (scalar_G_reg << RND_SIZE); + unique case (prog_instr.reg_id) + SCALAR_PK_ID : write_reg = (REG_SIZE+RND_SIZE)'(scalar_PK_reg << RND_SIZE); + SCALAR_G_ID : write_reg = (REG_SIZE+RND_SIZE)'(scalar_G_reg << RND_SIZE); SCALAR_ID : write_reg = scalar_out_reg; // SCA default : write_reg = '0; endcase @@ -727,13 +727,13 @@ module ecc_dsa_ctrl end else begin cycle_cnt <= '0; - unique casez (prog_cntr) + unique case (prog_cntr) DSA_NOP : begin keygen_process <= 0; signing_process <= 0; verifying_process <= 0; // Waiting for new valid command - unique casez (cmd_reg) + unique case (cmd_reg) KEYGEN : begin // keygen prog_cntr <= DSA_KG_S; dsa_valid_reg <= 0; diff --git a/src/ecc/rtl/ecc_dsa_sequencer.sv b/src/ecc/rtl/ecc_dsa_sequencer.sv index a41c080cb..7fa42fa49 100644 --- a/src/ecc/rtl/ecc_dsa_sequencer.sv +++ b/src/ecc/rtl/ecc_dsa_sequencer.sv @@ -64,7 +64,7 @@ module ecc_dsa_sequencer end else begin if (ena) begin - unique casez(addra) + unique case(addra) //PM CORE INIT 0 : douta <= {DSA_UOP_NOP, NOP_ID, UOP_OPR_DONTCARE}; 1 : douta <= {DSA_UOP_WR_CORE, CONST_ZERO_ID, UOP_OPR_CONST_ZERO}; diff --git a/src/ecc/rtl/ecc_dsa_uop_pkg.sv b/src/ecc/rtl/ecc_dsa_uop_pkg.sv index 02439063c..b807d35a5 100644 --- a/src/ecc/rtl/ecc_dsa_uop_pkg.sv +++ b/src/ecc/rtl/ecc_dsa_uop_pkg.sv @@ -105,8 +105,8 @@ localparam [DSA_OPR_ADDR_WIDTH-1 : 0] MASKING_ID = 6'd28; localparam [DSA_OPR_ADDR_WIDTH-1 : 0] PK_VALID_ID = 6'd29; // DSA Subroutine listing -localparam [DSA_PROG_ADDR_W-1 : 0] DSA_RESET = 6'd0; -localparam [DSA_PROG_ADDR_W-1 : 0] DSA_NOP = 6'd12; +localparam [DSA_PROG_ADDR_W-1 : 0] DSA_RESET = 7'd0; +localparam [DSA_PROG_ADDR_W-1 : 0] DSA_NOP = 7'd12; localparam [DSA_PROG_ADDR_W-1 : 0] DSA_KG_S = DSA_NOP + 2; localparam [DSA_PROG_ADDR_W-1 : 0] DSA_KG_E = DSA_KG_S + 12; localparam [DSA_PROG_ADDR_W-1 : 0] DSA_SGN_S = DSA_KG_E + 2; @@ -117,4 +117,4 @@ localparam [DSA_PROG_ADDR_W-1 : 0] DSA_VER_E = DSA_VER_S + 23 endpackage -`endif \ No newline at end of file +`endif diff --git a/src/ecc/rtl/ecc_hmac_drbg_interface.sv b/src/ecc/rtl/ecc_hmac_drbg_interface.sv index 071debff9..50676c035 100644 --- a/src/ecc/rtl/ecc_hmac_drbg_interface.sv +++ b/src/ecc/rtl/ecc_hmac_drbg_interface.sv @@ -140,7 +140,7 @@ module ecc_hmac_drbg_interface#( always_comb begin : hmac_drbg_entropy_input - unique casez (state_reg) + unique case (state_reg) LFSR_ST: hmac_drbg_entropy = IV; LAMBDA_ST: hmac_drbg_entropy = IV; SCALAR_RND_ST: hmac_drbg_entropy = IV; @@ -153,7 +153,7 @@ module ecc_hmac_drbg_interface#( always_comb begin : hmac_drbg_nonce_input - unique casez (state_reg) + unique case (state_reg) LFSR_ST: hmac_drbg_nonce = counter_nonce_reg; LAMBDA_ST: hmac_drbg_nonce = counter_nonce_reg; SCALAR_RND_ST: hmac_drbg_nonce = counter_nonce_reg; @@ -171,7 +171,7 @@ module ecc_hmac_drbg_interface#( hmac_drbg_init = 0; hmac_drbg_next = 0; if (first_round) begin - unique casez (state_reg) + unique case (state_reg) LFSR_ST: hmac_drbg_init = 1; LAMBDA_ST: hmac_drbg_next = 1; SCALAR_RND_ST: hmac_drbg_next = 1; @@ -290,7 +290,7 @@ module ecc_hmac_drbg_interface#( always_comb begin : interface_fsm state_next = IDLE_ST; - unique casez(state_reg) + unique case(state_reg) IDLE_ST: state_next = (en & hmac_drbg_ready)? LFSR_ST : IDLE_ST; LFSR_ST: state_next = (hmac_done_edge)? LAMBDA_ST : LFSR_ST; LAMBDA_ST: state_next = (hmac_done_edge)? SCALAR_RND_ST : LAMBDA_ST; diff --git a/src/ecc/rtl/ecc_pm_ctrl.sv b/src/ecc/rtl/ecc_pm_ctrl.sv index 3be02ec79..7abb4dd87 100644 --- a/src/ecc/rtl/ecc_pm_ctrl.sv +++ b/src/ecc/rtl/ecc_pm_ctrl.sv @@ -150,7 +150,7 @@ module ecc_pm_ctrl stall_cntr <= stall_cntr - 1; end else if (stall_flag & (!stalled) & (!stalled_pipe1)) begin - unique casez (prog_instr.opcode) + unique case (prog_instr.opcode) UOP_DO_ADD_p : begin stalled <= 1'b1; stall_cntr <= ADD_DELAY; end // ADD UOP_DO_SUB_p : begin stalled <= 1'b1; stall_cntr <= ADD_DELAY; end // SUB UOP_DO_MUL_p : begin stalled <= 1'b1; stall_cntr <= MULT_DELAY; end // MULT @@ -162,10 +162,10 @@ module ecc_pm_ctrl end else if ((!stalled) | (stalled & (stall_cntr == 0))) begin stalled <= 0; - unique casez (prog_cntr) + unique case (prog_cntr) NOP : begin // Waiting for new valid command ecc_cmd_reg <= ecc_cmd_i; - unique casez (ecc_cmd_i) + unique case (ecc_cmd_i) KEYGEN_CMD : begin // keygen mont_cntr <= (sca_en_i)? Secp384_SCA_MONT_COUNT : Secp384_MONT_COUNT; prog_cntr <= PM_INIT_G_S; @@ -231,7 +231,7 @@ module ecc_pm_ctrl PD_E : begin //End of point doubling if (mont_cntr == 0) begin // Montgomery ladder is done - unique casez (ecc_cmd_reg) + unique case (ecc_cmd_reg) VER_PART1_CMD : prog_cntr <= NOP; VER_PART2_CMD : prog_cntr <= VER2_PA_S; default : prog_cntr <= INV_S; @@ -251,7 +251,7 @@ module ecc_pm_ctrl end CONV_E : begin // End of conversion from projective Mont (X,Y,Z) to affine normanl (x,y) - unique casez (ecc_cmd_reg) + unique case (ecc_cmd_reg) SIGN_CMD : prog_cntr <= SIGN0_S; default : prog_cntr <= NOP; endcase @@ -262,7 +262,7 @@ module ecc_pm_ctrl end INVq_E : begin // End of inversion mod q - unique casez (ecc_cmd_reg) + unique case (ecc_cmd_reg) SIGN_CMD : prog_cntr <= SIGN1_S; VER_PART0_CMD : prog_cntr <= VER0_P1_S; default : prog_cntr <= NOP; @@ -344,7 +344,7 @@ module ecc_pm_ctrl /* always_comb begin : delay_flag - unique casez (prog_instr.opcode) + unique case (prog_instr.opcode) UOP_DO_ADD_p : stall_flag = 1; UOP_DO_SUB_p : stall_flag = 1; UOP_DO_MUL_p : stall_flag = 1; diff --git a/src/ecc/rtl/ecc_pm_sequencer.sv b/src/ecc/rtl/ecc_pm_sequencer.sv index d4d758d9e..f0249c53f 100644 --- a/src/ecc/rtl/ecc_pm_sequencer.sv +++ b/src/ecc/rtl/ecc_pm_sequencer.sv @@ -60,7 +60,7 @@ module ecc_pm_sequencer end else begin if (ena) begin - unique casez(addra) + unique case(addra) NOP : douta <= '0; 1 : douta <= '0; diff --git a/src/ecc/rtl/ecc_reg.sv b/src/ecc/rtl/ecc_reg.sv index c10afc816..76f71c3dd 100644 --- a/src/ecc/rtl/ecc_reg.sv +++ b/src/ecc/rtl/ecc_reg.sv @@ -58,7 +58,9 @@ module ecc_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -109,65 +111,65 @@ module ecc_reg ( always_comb begin for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.ECC_NAME[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); + decoded_reg_strb.ECC_NAME[i0] = cpuif_req_masked & (cpuif_addr == 12'h0 + i0*12'h4); end for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.ECC_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 'h8 + i0*'h4); + decoded_reg_strb.ECC_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 12'h8 + i0*12'h4); end - decoded_reg_strb.ECC_CTRL = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.ECC_STATUS = cpuif_req_masked & (cpuif_addr == 'h18); + decoded_reg_strb.ECC_CTRL = cpuif_req_masked & (cpuif_addr == 12'h10); + decoded_reg_strb.ECC_STATUS = cpuif_req_masked & (cpuif_addr == 12'h18); for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_SEED[i0] = cpuif_req_masked & (cpuif_addr == 'h80 + i0*'h4); + decoded_reg_strb.ECC_SEED[i0] = cpuif_req_masked & (cpuif_addr == 12'h80 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_MSG[i0] = cpuif_req_masked & (cpuif_addr == 'h100 + i0*'h4); + decoded_reg_strb.ECC_MSG[i0] = cpuif_req_masked & (cpuif_addr == 12'h100 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_PRIVKEY_OUT[i0] = cpuif_req_masked & (cpuif_addr == 'h180 + i0*'h4); + decoded_reg_strb.ECC_PRIVKEY_OUT[i0] = cpuif_req_masked & (cpuif_addr == 12'h180 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_PUBKEY_X[i0] = cpuif_req_masked & (cpuif_addr == 'h200 + i0*'h4); + decoded_reg_strb.ECC_PUBKEY_X[i0] = cpuif_req_masked & (cpuif_addr == 12'h200 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_PUBKEY_Y[i0] = cpuif_req_masked & (cpuif_addr == 'h280 + i0*'h4); + decoded_reg_strb.ECC_PUBKEY_Y[i0] = cpuif_req_masked & (cpuif_addr == 12'h280 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_SIGN_R[i0] = cpuif_req_masked & (cpuif_addr == 'h300 + i0*'h4); + decoded_reg_strb.ECC_SIGN_R[i0] = cpuif_req_masked & (cpuif_addr == 12'h300 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_SIGN_S[i0] = cpuif_req_masked & (cpuif_addr == 'h380 + i0*'h4); + decoded_reg_strb.ECC_SIGN_S[i0] = cpuif_req_masked & (cpuif_addr == 12'h380 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_VERIFY_R[i0] = cpuif_req_masked & (cpuif_addr == 'h400 + i0*'h4); + decoded_reg_strb.ECC_VERIFY_R[i0] = cpuif_req_masked & (cpuif_addr == 12'h400 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_IV[i0] = cpuif_req_masked & (cpuif_addr == 'h480 + i0*'h4); + decoded_reg_strb.ECC_IV[i0] = cpuif_req_masked & (cpuif_addr == 12'h480 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_NONCE[i0] = cpuif_req_masked & (cpuif_addr == 'h500 + i0*'h4); + decoded_reg_strb.ECC_NONCE[i0] = cpuif_req_masked & (cpuif_addr == 12'h500 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_PRIVKEY_IN[i0] = cpuif_req_masked & (cpuif_addr == 'h580 + i0*'h4); - end - decoded_reg_strb.ecc_kv_rd_pkey_ctrl = cpuif_req_masked & (cpuif_addr == 'h600); - decoded_reg_strb.ecc_kv_rd_pkey_status = cpuif_req_masked & (cpuif_addr == 'h604); - decoded_reg_strb.ecc_kv_rd_seed_ctrl = cpuif_req_masked & (cpuif_addr == 'h608); - decoded_reg_strb.ecc_kv_rd_seed_status = cpuif_req_masked & (cpuif_addr == 'h60c); - decoded_reg_strb.ecc_kv_wr_pkey_ctrl = cpuif_req_masked & (cpuif_addr == 'h610); - decoded_reg_strb.ecc_kv_wr_pkey_status = cpuif_req_masked & (cpuif_addr == 'h614); - decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800); - decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804); - decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808); - decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h80c); - decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h810); - decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h814); - decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h818); - decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h81c); - decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h820); - decoded_reg_strb.intr_block_rf.error_internal_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h900); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980); - decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04); + decoded_reg_strb.ECC_PRIVKEY_IN[i0] = cpuif_req_masked & (cpuif_addr == 12'h580 + i0*12'h4); + end + decoded_reg_strb.ecc_kv_rd_pkey_ctrl = cpuif_req_masked & (cpuif_addr == 12'h600); + decoded_reg_strb.ecc_kv_rd_pkey_status = cpuif_req_masked & (cpuif_addr == 12'h604); + decoded_reg_strb.ecc_kv_rd_seed_ctrl = cpuif_req_masked & (cpuif_addr == 12'h608); + decoded_reg_strb.ecc_kv_rd_seed_status = cpuif_req_masked & (cpuif_addr == 12'h60c); + decoded_reg_strb.ecc_kv_wr_pkey_ctrl = cpuif_req_masked & (cpuif_addr == 12'h610); + decoded_reg_strb.ecc_kv_wr_pkey_status = cpuif_req_masked & (cpuif_addr == 12'h614); + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h80c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h810); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h814); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h818); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h81c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h820); + decoded_reg_strb.intr_block_rf.error_internal_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h900); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h980); + decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha00); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha04); end // Pass down signals to next stage @@ -176,10 +178,6 @@ module ecc_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -658,8 +656,10 @@ module ecc_reg ( // Field: ecc_reg.ECC_CTRL.CTRL always_comb begin - automatic logic [1:0] next_c = field_storage.ECC_CTRL.CTRL.value; - automatic logic load_next_c = '0; + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_CTRL.CTRL.value; + load_next_c = '0; if(decoded_reg_strb.ECC_CTRL && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_CTRL.CTRL.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); load_next_c = '1; @@ -672,7 +672,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_CTRL.CTRL.value <= 'h0; + field_storage.ECC_CTRL.CTRL.value <= 2'h0; end else if(field_combo.ECC_CTRL.CTRL.load_next) begin field_storage.ECC_CTRL.CTRL.value <= field_combo.ECC_CTRL.CTRL.next; end @@ -680,12 +680,14 @@ module ecc_reg ( assign hwif_out.ECC_CTRL.CTRL.value = field_storage.ECC_CTRL.CTRL.value; // Field: ecc_reg.ECC_CTRL.ZEROIZE always_comb begin - automatic logic [0:0] next_c = field_storage.ECC_CTRL.ZEROIZE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_CTRL.ZEROIZE.value; + load_next_c = '0; if(decoded_reg_strb.ECC_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.ECC_CTRL.ZEROIZE.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -694,7 +696,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_CTRL.ZEROIZE.value <= 'h0; + field_storage.ECC_CTRL.ZEROIZE.value <= 1'h0; end else if(field_combo.ECC_CTRL.ZEROIZE.load_next) begin field_storage.ECC_CTRL.ZEROIZE.value <= field_combo.ECC_CTRL.ZEROIZE.next; end @@ -702,8 +704,10 @@ module ecc_reg ( assign hwif_out.ECC_CTRL.ZEROIZE.value = field_storage.ECC_CTRL.ZEROIZE.value; // Field: ecc_reg.ECC_CTRL.PCR_SIGN always_comb begin - automatic logic [0:0] next_c = field_storage.ECC_CTRL.PCR_SIGN.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_CTRL.PCR_SIGN.value; + load_next_c = '0; if(decoded_reg_strb.ECC_CTRL && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_CTRL.PCR_SIGN.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -716,7 +720,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_CTRL.PCR_SIGN.value <= 'h0; + field_storage.ECC_CTRL.PCR_SIGN.value <= 1'h0; end else if(field_combo.ECC_CTRL.PCR_SIGN.load_next) begin field_storage.ECC_CTRL.PCR_SIGN.value <= field_combo.ECC_CTRL.PCR_SIGN.next; end @@ -725,8 +729,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_SEED[].SEED always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_SEED[i0].SEED.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_SEED[i0].SEED.value; + load_next_c = '0; if(decoded_reg_strb.ECC_SEED[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_SEED[i0].SEED.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -742,7 +748,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_SEED[i0].SEED.value <= 'h0; + field_storage.ECC_SEED[i0].SEED.value <= 32'h0; end else if(field_combo.ECC_SEED[i0].SEED.load_next) begin field_storage.ECC_SEED[i0].SEED.value <= field_combo.ECC_SEED[i0].SEED.next; end @@ -752,8 +758,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_MSG[].MSG always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_MSG[i0].MSG.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_MSG[i0].MSG.value; + load_next_c = '0; if(decoded_reg_strb.ECC_MSG[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_MSG[i0].MSG.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -769,7 +777,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_MSG[i0].MSG.value <= 'h0; + field_storage.ECC_MSG[i0].MSG.value <= 32'h0; end else if(field_combo.ECC_MSG[i0].MSG.load_next) begin field_storage.ECC_MSG[i0].MSG.value <= field_combo.ECC_MSG[i0].MSG.next; end @@ -779,8 +787,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_PRIVKEY_OUT[].PRIVKEY_OUT always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.value; + load_next_c = '0; if(hwif_in.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.we) begin // HW Write - we next_c = hwif_in.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.next; load_next_c = '1; @@ -793,7 +803,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.value <= 'h0; + field_storage.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.value <= 32'h0; end else if(field_combo.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.load_next) begin field_storage.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.value <= field_combo.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.next; end @@ -802,8 +812,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_PUBKEY_X[].PUBKEY_X always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_PUBKEY_X[i0].PUBKEY_X.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_PUBKEY_X[i0].PUBKEY_X.value; + load_next_c = '0; if(decoded_reg_strb.ECC_PUBKEY_X[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_PUBKEY_X[i0].PUBKEY_X.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -819,7 +831,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_PUBKEY_X[i0].PUBKEY_X.value <= 'h0; + field_storage.ECC_PUBKEY_X[i0].PUBKEY_X.value <= 32'h0; end else if(field_combo.ECC_PUBKEY_X[i0].PUBKEY_X.load_next) begin field_storage.ECC_PUBKEY_X[i0].PUBKEY_X.value <= field_combo.ECC_PUBKEY_X[i0].PUBKEY_X.next; end @@ -829,8 +841,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_PUBKEY_Y[].PUBKEY_Y always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_PUBKEY_Y[i0].PUBKEY_Y.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_PUBKEY_Y[i0].PUBKEY_Y.value; + load_next_c = '0; if(decoded_reg_strb.ECC_PUBKEY_Y[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_PUBKEY_Y[i0].PUBKEY_Y.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -846,7 +860,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_PUBKEY_Y[i0].PUBKEY_Y.value <= 'h0; + field_storage.ECC_PUBKEY_Y[i0].PUBKEY_Y.value <= 32'h0; end else if(field_combo.ECC_PUBKEY_Y[i0].PUBKEY_Y.load_next) begin field_storage.ECC_PUBKEY_Y[i0].PUBKEY_Y.value <= field_combo.ECC_PUBKEY_Y[i0].PUBKEY_Y.next; end @@ -856,8 +870,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_SIGN_R[].SIGN_R always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_SIGN_R[i0].SIGN_R.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_SIGN_R[i0].SIGN_R.value; + load_next_c = '0; if(decoded_reg_strb.ECC_SIGN_R[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_SIGN_R[i0].SIGN_R.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -873,7 +889,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_SIGN_R[i0].SIGN_R.value <= 'h0; + field_storage.ECC_SIGN_R[i0].SIGN_R.value <= 32'h0; end else if(field_combo.ECC_SIGN_R[i0].SIGN_R.load_next) begin field_storage.ECC_SIGN_R[i0].SIGN_R.value <= field_combo.ECC_SIGN_R[i0].SIGN_R.next; end @@ -883,8 +899,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_SIGN_S[].SIGN_S always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_SIGN_S[i0].SIGN_S.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_SIGN_S[i0].SIGN_S.value; + load_next_c = '0; if(decoded_reg_strb.ECC_SIGN_S[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_SIGN_S[i0].SIGN_S.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -900,7 +918,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_SIGN_S[i0].SIGN_S.value <= 'h0; + field_storage.ECC_SIGN_S[i0].SIGN_S.value <= 32'h0; end else if(field_combo.ECC_SIGN_S[i0].SIGN_S.load_next) begin field_storage.ECC_SIGN_S[i0].SIGN_S.value <= field_combo.ECC_SIGN_S[i0].SIGN_S.next; end @@ -910,8 +928,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_VERIFY_R[].VERIFY_R always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_VERIFY_R[i0].VERIFY_R.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_VERIFY_R[i0].VERIFY_R.value; + load_next_c = '0; if(hwif_in.ECC_VERIFY_R[i0].VERIFY_R.we) begin // HW Write - we next_c = hwif_in.ECC_VERIFY_R[i0].VERIFY_R.next; load_next_c = '1; @@ -924,7 +944,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_VERIFY_R[i0].VERIFY_R.value <= 'h0; + field_storage.ECC_VERIFY_R[i0].VERIFY_R.value <= 32'h0; end else if(field_combo.ECC_VERIFY_R[i0].VERIFY_R.load_next) begin field_storage.ECC_VERIFY_R[i0].VERIFY_R.value <= field_combo.ECC_VERIFY_R[i0].VERIFY_R.next; end @@ -934,8 +954,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_IV[].IV always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_IV[i0].IV.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_IV[i0].IV.value; + load_next_c = '0; if(decoded_reg_strb.ECC_IV[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_IV[i0].IV.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -948,7 +970,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_IV[i0].IV.value <= 'h0; + field_storage.ECC_IV[i0].IV.value <= 32'h0; end else if(field_combo.ECC_IV[i0].IV.load_next) begin field_storage.ECC_IV[i0].IV.value <= field_combo.ECC_IV[i0].IV.next; end @@ -958,8 +980,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_NONCE[].NONCE always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_NONCE[i0].NONCE.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_NONCE[i0].NONCE.value; + load_next_c = '0; if(decoded_reg_strb.ECC_NONCE[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_NONCE[i0].NONCE.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -972,7 +996,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_NONCE[i0].NONCE.value <= 'h0; + field_storage.ECC_NONCE[i0].NONCE.value <= 32'h0; end else if(field_combo.ECC_NONCE[i0].NONCE.load_next) begin field_storage.ECC_NONCE[i0].NONCE.value <= field_combo.ECC_NONCE[i0].NONCE.next; end @@ -982,8 +1006,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_PRIVKEY_IN[].PRIVKEY_IN always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.value; + load_next_c = '0; if(decoded_reg_strb.ECC_PRIVKEY_IN[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -999,7 +1025,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.value <= 'h0; + field_storage.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.value <= 32'h0; end else if(field_combo.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.load_next) begin field_storage.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.value <= field_combo.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.next; end @@ -1008,8 +1034,10 @@ module ecc_reg ( end // Field: ecc_reg.ecc_kv_rd_pkey_ctrl.read_en always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_rd_pkey_ctrl.read_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_pkey_ctrl.read_en.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_pkey_ctrl.read_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1022,7 +1050,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_pkey_ctrl.read_en.value <= 'h0; + field_storage.ecc_kv_rd_pkey_ctrl.read_en.value <= 1'h0; end else if(field_combo.ecc_kv_rd_pkey_ctrl.read_en.load_next) begin field_storage.ecc_kv_rd_pkey_ctrl.read_en.value <= field_combo.ecc_kv_rd_pkey_ctrl.read_en.next; end @@ -1030,8 +1058,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_pkey_ctrl.read_en.value = field_storage.ecc_kv_rd_pkey_ctrl.read_en.value; // Field: ecc_reg.ecc_kv_rd_pkey_ctrl.read_entry always_comb begin - automatic logic [4:0] next_c = field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -1041,7 +1071,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value <= 'h0; + field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value <= 5'h0; end else if(field_combo.ecc_kv_rd_pkey_ctrl.read_entry.load_next) begin field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value <= field_combo.ecc_kv_rd_pkey_ctrl.read_entry.next; end @@ -1049,8 +1079,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_pkey_ctrl.read_entry.value = field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value; // Field: ecc_reg.ecc_kv_rd_pkey_ctrl.pcr_hash_extend always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -1060,7 +1092,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value <= 'h0; + field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value <= 1'h0; end else if(field_combo.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.load_next) begin field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value <= field_combo.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.next; end @@ -1068,8 +1100,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value = field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value; // Field: ecc_reg.ecc_kv_rd_pkey_ctrl.rsvd always_comb begin - automatic logic [24:0] next_c = field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [24:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value & ~decoded_wr_biten[31:7]) | (decoded_wr_data[31:7] & decoded_wr_biten[31:7]); load_next_c = '1; @@ -1079,7 +1113,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value <= 'h0; + field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value <= 25'h0; end else if(field_combo.ecc_kv_rd_pkey_ctrl.rsvd.load_next) begin field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value <= field_combo.ecc_kv_rd_pkey_ctrl.rsvd.next; end @@ -1087,8 +1121,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_pkey_ctrl.rsvd.value = field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value; // Field: ecc_reg.ecc_kv_rd_pkey_status.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_rd_pkey_status.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_pkey_status.VALID.value; + load_next_c = '0; if(hwif_in.ecc_kv_rd_pkey_status.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1101,15 +1137,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_pkey_status.VALID.value <= 'h0; + field_storage.ecc_kv_rd_pkey_status.VALID.value <= 1'h0; end else if(field_combo.ecc_kv_rd_pkey_status.VALID.load_next) begin field_storage.ecc_kv_rd_pkey_status.VALID.value <= field_combo.ecc_kv_rd_pkey_status.VALID.next; end end // Field: ecc_reg.ecc_kv_rd_seed_ctrl.read_en always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_rd_seed_ctrl.read_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_seed_ctrl.read_en.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_seed_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_seed_ctrl.read_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1122,7 +1160,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_seed_ctrl.read_en.value <= 'h0; + field_storage.ecc_kv_rd_seed_ctrl.read_en.value <= 1'h0; end else if(field_combo.ecc_kv_rd_seed_ctrl.read_en.load_next) begin field_storage.ecc_kv_rd_seed_ctrl.read_en.value <= field_combo.ecc_kv_rd_seed_ctrl.read_en.next; end @@ -1130,8 +1168,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_seed_ctrl.read_en.value = field_storage.ecc_kv_rd_seed_ctrl.read_en.value; // Field: ecc_reg.ecc_kv_rd_seed_ctrl.read_entry always_comb begin - automatic logic [4:0] next_c = field_storage.ecc_kv_rd_seed_ctrl.read_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_seed_ctrl.read_entry.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_seed_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_seed_ctrl.read_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -1141,7 +1181,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_seed_ctrl.read_entry.value <= 'h0; + field_storage.ecc_kv_rd_seed_ctrl.read_entry.value <= 5'h0; end else if(field_combo.ecc_kv_rd_seed_ctrl.read_entry.load_next) begin field_storage.ecc_kv_rd_seed_ctrl.read_entry.value <= field_combo.ecc_kv_rd_seed_ctrl.read_entry.next; end @@ -1149,8 +1189,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_seed_ctrl.read_entry.value = field_storage.ecc_kv_rd_seed_ctrl.read_entry.value; // Field: ecc_reg.ecc_kv_rd_seed_ctrl.pcr_hash_extend always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_seed_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -1160,7 +1202,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value <= 'h0; + field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value <= 1'h0; end else if(field_combo.ecc_kv_rd_seed_ctrl.pcr_hash_extend.load_next) begin field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value <= field_combo.ecc_kv_rd_seed_ctrl.pcr_hash_extend.next; end @@ -1168,8 +1210,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value = field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value; // Field: ecc_reg.ecc_kv_rd_seed_ctrl.rsvd always_comb begin - automatic logic [24:0] next_c = field_storage.ecc_kv_rd_seed_ctrl.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [24:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_seed_ctrl.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_seed_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_seed_ctrl.rsvd.value & ~decoded_wr_biten[31:7]) | (decoded_wr_data[31:7] & decoded_wr_biten[31:7]); load_next_c = '1; @@ -1179,7 +1223,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_seed_ctrl.rsvd.value <= 'h0; + field_storage.ecc_kv_rd_seed_ctrl.rsvd.value <= 25'h0; end else if(field_combo.ecc_kv_rd_seed_ctrl.rsvd.load_next) begin field_storage.ecc_kv_rd_seed_ctrl.rsvd.value <= field_combo.ecc_kv_rd_seed_ctrl.rsvd.next; end @@ -1187,8 +1231,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_seed_ctrl.rsvd.value = field_storage.ecc_kv_rd_seed_ctrl.rsvd.value; // Field: ecc_reg.ecc_kv_rd_seed_status.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_rd_seed_status.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_seed_status.VALID.value; + load_next_c = '0; if(hwif_in.ecc_kv_rd_seed_status.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1201,15 +1247,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_seed_status.VALID.value <= 'h0; + field_storage.ecc_kv_rd_seed_status.VALID.value <= 1'h0; end else if(field_combo.ecc_kv_rd_seed_status.VALID.load_next) begin field_storage.ecc_kv_rd_seed_status.VALID.value <= field_combo.ecc_kv_rd_seed_status.VALID.next; end end // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.write_en always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.write_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.write_en.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.write_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1222,7 +1270,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.write_en.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.write_en.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.write_en.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.write_en.value <= field_combo.ecc_kv_wr_pkey_ctrl.write_en.next; end @@ -1230,8 +1278,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.write_en.value = field_storage.ecc_kv_wr_pkey_ctrl.write_en.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.write_entry always_comb begin - automatic logic [4:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -1241,7 +1291,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value <= 5'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.write_entry.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value <= field_combo.ecc_kv_wr_pkey_ctrl.write_entry.next; end @@ -1249,8 +1299,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.write_entry.value = field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -1260,7 +1312,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value <= field_combo.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.next; end @@ -1268,8 +1320,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value = field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value & ~decoded_wr_biten[7:7]) | (decoded_wr_data[7:7] & decoded_wr_biten[7:7]); load_next_c = '1; @@ -1279,7 +1333,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value <= field_combo.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.next; end @@ -1287,8 +1341,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value = field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]); load_next_c = '1; @@ -1298,7 +1354,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value <= field_combo.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.next; end @@ -1306,8 +1362,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value = field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value & ~decoded_wr_biten[9:9]) | (decoded_wr_data[9:9] & decoded_wr_biten[9:9]); load_next_c = '1; @@ -1317,7 +1375,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value <= field_combo.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.next; end @@ -1325,8 +1383,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value = field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value & ~decoded_wr_biten[10:10]) | (decoded_wr_data[10:10] & decoded_wr_biten[10:10]); load_next_c = '1; @@ -1336,7 +1396,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value <= field_combo.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.next; end @@ -1344,8 +1404,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value = field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.rsvd always_comb begin - automatic logic [20:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [20:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value & ~decoded_wr_biten[31:11]) | (decoded_wr_data[31:11] & decoded_wr_biten[31:11]); load_next_c = '1; @@ -1355,7 +1417,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value <= 21'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.rsvd.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value <= field_combo.ecc_kv_wr_pkey_ctrl.rsvd.next; end @@ -1363,8 +1425,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.rsvd.value = field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value; // Field: ecc_reg.ecc_kv_wr_pkey_status.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_status.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_status.VALID.value; + load_next_c = '0; if(hwif_in.ecc_kv_wr_pkey_status.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1377,15 +1441,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_status.VALID.value <= 'h0; + field_storage.ecc_kv_wr_pkey_status.VALID.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_status.VALID.load_next) begin field_storage.ecc_kv_wr_pkey_status.VALID.value <= field_combo.ecc_kv_wr_pkey_status.VALID.next; end end // Field: ecc_reg.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1395,15 +1461,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; end end // Field: ecc_reg.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -1413,15 +1481,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; end end // Field: ecc_reg.intr_block_rf.error_intr_en_r.error_internal_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1431,15 +1501,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_internal_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_internal_en.next; end end // Field: ecc_reg.intr_block_rf.notif_intr_en_r.notif_cmd_done_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1449,25 +1521,27 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.next; end end // Field: ecc_reg.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; end @@ -1476,18 +1550,20 @@ module ecc_reg ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: ecc_reg.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; end @@ -1496,9 +1572,11 @@ module ecc_reg ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: ecc_reg.intr_block_rf.error_internal_intr_r.error_internal_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset) begin // HW Set @@ -1513,7 +1591,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_internal_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_internal_sts.next; end @@ -1522,9 +1600,11 @@ module ecc_reg ( |(field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value & field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value); // Field: ecc_reg.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset) begin // HW Set @@ -1539,7 +1619,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.next; end @@ -1548,12 +1628,14 @@ module ecc_reg ( |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value); // Field: ecc_reg.intr_block_rf.error_intr_trig_r.error_internal_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1562,19 +1644,21 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_internal_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_internal_trig.next; end end // Field: ecc_reg.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1583,31 +1667,33 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.next; end end // Field: ecc_reg.intr_block_rf.error_internal_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_internal_intr_count_r.cnt.next = next_c; @@ -1615,31 +1701,33 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_internal_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_internal_intr_count_r.cnt.next; end end // Field: ecc_reg.intr_block_rf.notif_cmd_done_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next = next_c; @@ -1647,15 +1735,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next; end end // Field: ecc_reg.intr_block_rf.error_internal_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; load_next_c = '1; @@ -1664,27 +1754,29 @@ module ecc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.next; end end // Field: ecc_reg.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; @@ -1693,30 +1785,39 @@ module ecc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [96-1:0][31:0] readback_array; for(genvar i0=0; i0<2; i0++) begin @@ -1816,4 +1917,4 @@ module ecc_reg ( `CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.hard_reset_b) -endmodule \ No newline at end of file +endmodule diff --git a/src/ecc/rtl/ecc_reg_pkg.sv b/src/ecc/rtl/ecc_reg_pkg.sv index da1893d0e..d729b5a14 100644 --- a/src/ecc/rtl/ecc_reg_pkg.sv +++ b/src/ecc/rtl/ecc_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package ecc_reg_pkg; + + localparam ECC_REG_DATA_WIDTH = 32; + localparam ECC_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic [31:0] next; } ecc_reg__ECC_NAME__NAME__in_t; @@ -156,7 +160,7 @@ package ecc_reg_pkg; typedef struct packed{ kv_read_ctrl_reg__read_en__in_t read_en; - } __kv_read_ctrl_reg__in_t; + } kv_read_ctrl_reg__in_t; typedef struct packed{ logic next; @@ -175,7 +179,7 @@ package ecc_reg_pkg; kv_status_reg__READY__in_t READY; kv_status_reg__VALID__in_t VALID; kv_status_reg__ERROR__in_t ERROR; - } __kv_status_reg__in_t; + } kv_status_reg__in_t; typedef struct packed{ logic hwclr; @@ -183,22 +187,22 @@ package ecc_reg_pkg; typedef struct packed{ kv_write_ctrl_reg__write_en__in_t write_en; - } __kv_write_ctrl_reg__in_t; + } kv_write_ctrl_reg__in_t; typedef struct packed{ logic hwset; - } ecc_reg__intr_block_t__error_intr_t__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_0d7eaa27__in_t; + } ecc_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_0d7eaa27__in_t; typedef struct packed{ - ecc_reg__intr_block_t__error_intr_t__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_0d7eaa27__in_t error_internal_sts; + ecc_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_0d7eaa27__in_t error_internal_sts; } ecc_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02__in_t; typedef struct packed{ logic hwset; - } ecc_reg__intr_block_t__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; + } ecc_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; typedef struct packed{ - ecc_reg__intr_block_t__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; + ecc_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; } ecc_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e__in_t; typedef struct packed{ @@ -225,12 +229,12 @@ package ecc_reg_pkg; ecc_reg__ECC_IV__in_t [12-1:0]ECC_IV; ecc_reg__ECC_NONCE__in_t [12-1:0]ECC_NONCE; ecc_reg__ECC_PRIVKEY_IN__in_t [12-1:0]ECC_PRIVKEY_IN; - __kv_read_ctrl_reg__in_t ecc_kv_rd_pkey_ctrl; - __kv_status_reg__in_t ecc_kv_rd_pkey_status; - __kv_read_ctrl_reg__in_t ecc_kv_rd_seed_ctrl; - __kv_status_reg__in_t ecc_kv_rd_seed_status; - __kv_write_ctrl_reg__in_t ecc_kv_wr_pkey_ctrl; - __kv_status_reg__in_t ecc_kv_wr_pkey_status; + kv_read_ctrl_reg__in_t ecc_kv_rd_pkey_ctrl; + kv_status_reg__in_t ecc_kv_rd_pkey_status; + kv_read_ctrl_reg__in_t ecc_kv_rd_seed_ctrl; + kv_status_reg__in_t ecc_kv_rd_seed_status; + kv_write_ctrl_reg__in_t ecc_kv_wr_pkey_ctrl; + kv_status_reg__in_t ecc_kv_wr_pkey_status; ecc_reg__intr_block_t__in_t intr_block_rf; } ecc_reg__in_t; @@ -353,7 +357,7 @@ package ecc_reg_pkg; kv_read_ctrl_reg__read_entry__out_t read_entry; kv_read_ctrl_reg__pcr_hash_extend__out_t pcr_hash_extend; kv_read_ctrl_reg__rsvd__out_t rsvd; - } __kv_read_ctrl_reg__out_t; + } kv_read_ctrl_reg__out_t; typedef struct packed{ logic value; @@ -396,7 +400,7 @@ package ecc_reg_pkg; kv_write_ctrl_reg__ecc_pkey_dest_valid__out_t ecc_pkey_dest_valid; kv_write_ctrl_reg__ecc_seed_dest_valid__out_t ecc_seed_dest_valid; kv_write_ctrl_reg__rsvd__out_t rsvd; - } __kv_write_ctrl_reg__out_t; + } kv_write_ctrl_reg__out_t; typedef struct packed{ logic intr; @@ -433,12 +437,18 @@ package ecc_reg_pkg; ecc_reg__ECC_IV__out_t [12-1:0]ECC_IV; ecc_reg__ECC_NONCE__out_t [12-1:0]ECC_NONCE; ecc_reg__ECC_PRIVKEY_IN__out_t [12-1:0]ECC_PRIVKEY_IN; - __kv_read_ctrl_reg__out_t ecc_kv_rd_pkey_ctrl; - __kv_read_ctrl_reg__out_t ecc_kv_rd_seed_ctrl; - __kv_write_ctrl_reg__out_t ecc_kv_wr_pkey_ctrl; + kv_read_ctrl_reg__out_t ecc_kv_rd_pkey_ctrl; + kv_read_ctrl_reg__out_t ecc_kv_rd_seed_ctrl; + kv_write_ctrl_reg__out_t ecc_kv_wr_pkey_ctrl; ecc_reg__intr_block_t__out_t intr_block_rf; } ecc_reg__out_t; + typedef enum logic [31:0] { + kv_status_reg__ERROR__kv_error_e__SUCCESS = 'h0, + kv_status_reg__ERROR__kv_error_e__KV_READ_FAIL = 'h1, + kv_status_reg__ERROR__kv_error_e__KV_WRITE_FAIL = 'h2 + } kv_status_reg__ERROR__kv_error_e_e; + localparam ECC_REG_ADDR_WIDTH = 32'd12; endpackage \ No newline at end of file diff --git a/src/entropy_src/config/compile.yml b/src/entropy_src/config/compile.yml index 9cdb9c50a..d74440352 100644 --- a/src/entropy_src/config/compile.yml +++ b/src/entropy_src/config/compile.yml @@ -43,6 +43,11 @@ targets: - $COMPILE_ROOT/rtl/entropy_src_ack_sm.sv - $COMPILE_ROOT/rtl/entropy_src.sv tops: [entropy_src] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/entropy_src/config/design_lint/sglint_waivers + tops: [entropy_src] tb: directories: [$COMPILE_ROOT/tb] files: diff --git a/src/entropy_src/rtl/entropy_src_ack_sm.sv b/src/entropy_src/rtl/entropy_src_ack_sm.sv index 6fda7f6ce..4528da428 100644 --- a/src/entropy_src/rtl/entropy_src_ack_sm.sv +++ b/src/entropy_src/rtl/entropy_src_ack_sm.sv @@ -33,11 +33,11 @@ module entropy_src_ack_sm ( Idle: begin if (enable_i) begin if (req_i) begin - state_d = Wait; + state_d = Wait_Data; end end end - Wait: begin + Wait_Data: begin if (!enable_i) begin state_d = Idle; end else begin diff --git a/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv b/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv index 116a419f4..f0bc489ac 100644 --- a/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv +++ b/src/entropy_src/rtl/entropy_src_ack_sm_pkg.sv @@ -27,9 +27,9 @@ package entropy_src_ack_sm_pkg; // localparam int StateWidth = 6; typedef enum logic [StateWidth-1:0] { - Idle = 6'b011101, // idle - Wait = 6'b101100, // wait until the fifo has an entry - Error = 6'b000010 // illegal state reached and hang + Idle = 6'b011101, // idle + Wait_Data = 6'b101100, // wait until the fifo has an entry + Error = 6'b000010 // illegal state reached and hang } state_e; endpackage diff --git a/src/entropy_src/rtl/entropy_src_reg_pkg.sv b/src/entropy_src/rtl/entropy_src_reg_pkg.sv index b95a710cf..d85cc0949 100644 --- a/src/entropy_src/rtl/entropy_src_reg_pkg.sv +++ b/src/entropy_src/rtl/entropy_src_reg_pkg.sv @@ -893,7 +893,7 @@ package entropy_src_reg_pkg; parameter logic [0:0] ENTROPY_SRC_DEBUG_STATUS_MAIN_SM_IDLE_RESVAL = 1'h 1; // Register index - typedef enum int { + typedef enum logic [31:0] { ENTROPY_SRC_INTR_STATE, ENTROPY_SRC_INTR_ENABLE, ENTROPY_SRC_INTR_TEST, diff --git a/src/entropy_src/rtl/entropy_src_watermark_reg.sv b/src/entropy_src/rtl/entropy_src_watermark_reg.sv index ae9cd1022..1b9e094c9 100644 --- a/src/entropy_src/rtl/entropy_src_watermark_reg.sv +++ b/src/entropy_src/rtl/entropy_src_watermark_reg.sv @@ -26,29 +26,40 @@ module entropy_src_watermark_reg #( // flops logic [RegWidth-1:0] event_cntr_q, event_cntr_d; - always_ff @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - event_cntr_q <= reg_reset; - end else begin - event_cntr_q <= event_cntr_d; - end - - assign event_cntr_d = clear_i ? reg_reset : - event_i ? event_cntr_change : - event_cntr_q; - // Set mode of this counter to be either a high or low watermark if (HighWatermark) begin : gen_hi_wm assign reg_reset = {RegWidth{1'b0}}; assign event_cntr_change = (value_i > event_cntr_q) ? (value_i) : event_cntr_q; + + assign event_cntr_d = clear_i ? reg_reset : + event_i ? event_cntr_change : + event_cntr_q; + + always_ff @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + event_cntr_q <= {RegWidth{1'b0}}; + end else begin + event_cntr_q <= event_cntr_d; + end end else begin : gen_lo_wm assign reg_reset = {RegWidth{1'b1}}; assign event_cntr_change = (value_i < event_cntr_q) ? (value_i) : event_cntr_q; + + assign event_cntr_d = clear_i ? reg_reset : + event_i ? event_cntr_change : + event_cntr_q; + + always_ff @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + event_cntr_q <= {RegWidth{1'b1}}; + end else begin + event_cntr_q <= event_cntr_d; + end end diff --git a/src/hmac/config/compile.yml b/src/hmac/config/compile.yml index 8313b86ae..5d058830e 100755 --- a/src/hmac/config/compile.yml +++ b/src/hmac/config/compile.yml @@ -21,8 +21,6 @@ targets: directories: [] waiver_files: - $MSFT_REPO_ROOT/src/hmac/config/design_lint/hmac_ctrl/sglint_waivers - black_box: - - hmac_reg --- provides: [hmac_ctrl_tb] schema_version: 2.4.0 diff --git a/src/hmac/rtl/hmac_core.v b/src/hmac/rtl/hmac_core.v index 703f71dc0..97e07d135 100644 --- a/src/hmac/rtl/hmac_core.v +++ b/src/hmac/rtl/hmac_core.v @@ -228,7 +228,7 @@ module hmac_core first_round = (hmac_ctrl_reg == hmac_ctrl_last)? 1'b0 : 1'b1; - unique casez (hmac_ctrl_reg) + unique case (hmac_ctrl_reg) CTRL_IPAD: begin if (first_round) @@ -288,7 +288,7 @@ module hmac_core hmac_ctrl_new = CTRL_IDLE; hmac_ctrl_we = 0; - unique casez (hmac_ctrl_reg) + unique case (hmac_ctrl_reg) CTRL_IDLE: begin ready_flag = 1; diff --git a/src/hmac/rtl/hmac_ctrl.sv b/src/hmac/rtl/hmac_ctrl.sv index b9c5482f6..04ee61a4c 100644 --- a/src/hmac/rtl/hmac_ctrl.sv +++ b/src/hmac/rtl/hmac_ctrl.sv @@ -65,11 +65,11 @@ module hmac_ctrl //---------------------------------------------------------------- // hmac //---------------------------------------------------------------- - reg hmac_cs; - reg hmac_we; - reg [AHB_ADDR_WIDTH-1 : 0] hmac_address; - reg [31 : 0] hmac_write_data; - reg [31 : 0] hmac_read_data; + logic hmac_cs; + logic hmac_we; + logic [AHB_ADDR_WIDTH-1 : 0] hmac_address; + logic [31 : 0] hmac_write_data; + logic [31 : 0] hmac_read_data; hmac #( .ADDR_WIDTH (AHB_ADDR_WIDTH), diff --git a/src/hmac/rtl/hmac_reg.sv b/src/hmac/rtl/hmac_reg.sv index 6f69ac4be..69a67bdbf 100644 --- a/src/hmac/rtl/hmac_reg.sv +++ b/src/hmac/rtl/hmac_reg.sv @@ -58,7 +58,9 @@ module hmac_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -108,50 +110,50 @@ module hmac_reg ( always_comb begin for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.HMAC384_NAME[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); + decoded_reg_strb.HMAC384_NAME[i0] = cpuif_req_masked & (cpuif_addr == 12'h0 + i0*12'h4); end for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.HMAC384_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 'h8 + i0*'h4); + decoded_reg_strb.HMAC384_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 12'h8 + i0*12'h4); end - decoded_reg_strb.HMAC384_CTRL = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.HMAC384_STATUS = cpuif_req_masked & (cpuif_addr == 'h18); + decoded_reg_strb.HMAC384_CTRL = cpuif_req_masked & (cpuif_addr == 12'h10); + decoded_reg_strb.HMAC384_STATUS = cpuif_req_masked & (cpuif_addr == 12'h18); for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.HMAC384_KEY[i0] = cpuif_req_masked & (cpuif_addr == 'h40 + i0*'h4); + decoded_reg_strb.HMAC384_KEY[i0] = cpuif_req_masked & (cpuif_addr == 12'h40 + i0*12'h4); end for(int i0=0; i0<32; i0++) begin - decoded_reg_strb.HMAC384_BLOCK[i0] = cpuif_req_masked & (cpuif_addr == 'h80 + i0*'h4); + decoded_reg_strb.HMAC384_BLOCK[i0] = cpuif_req_masked & (cpuif_addr == 12'h80 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.HMAC384_TAG[i0] = cpuif_req_masked & (cpuif_addr == 'h100 + i0*'h4); + decoded_reg_strb.HMAC384_TAG[i0] = cpuif_req_masked & (cpuif_addr == 12'h100 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.HMAC384_LFSR_SEED[i0] = cpuif_req_masked & (cpuif_addr == 'h130 + i0*'h4); - end - decoded_reg_strb.HMAC384_KV_RD_KEY_CTRL = cpuif_req_masked & (cpuif_addr == 'h600); - decoded_reg_strb.HMAC384_KV_RD_KEY_STATUS = cpuif_req_masked & (cpuif_addr == 'h604); - decoded_reg_strb.HMAC384_KV_RD_BLOCK_CTRL = cpuif_req_masked & (cpuif_addr == 'h608); - decoded_reg_strb.HMAC384_KV_RD_BLOCK_STATUS = cpuif_req_masked & (cpuif_addr == 'h60c); - decoded_reg_strb.HMAC384_KV_WR_CTRL = cpuif_req_masked & (cpuif_addr == 'h610); - decoded_reg_strb.HMAC384_KV_WR_STATUS = cpuif_req_masked & (cpuif_addr == 'h614); - decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800); - decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804); - decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808); - decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h80c); - decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h810); - decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h814); - decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h818); - decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h81c); - decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h820); - decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h900); - decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h904); - decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h908); - decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h90c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980); - decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00); - decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04); - decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha08); - decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha0c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha10); + decoded_reg_strb.HMAC384_LFSR_SEED[i0] = cpuif_req_masked & (cpuif_addr == 12'h130 + i0*12'h4); + end + decoded_reg_strb.HMAC384_KV_RD_KEY_CTRL = cpuif_req_masked & (cpuif_addr == 12'h600); + decoded_reg_strb.HMAC384_KV_RD_KEY_STATUS = cpuif_req_masked & (cpuif_addr == 12'h604); + decoded_reg_strb.HMAC384_KV_RD_BLOCK_CTRL = cpuif_req_masked & (cpuif_addr == 12'h608); + decoded_reg_strb.HMAC384_KV_RD_BLOCK_STATUS = cpuif_req_masked & (cpuif_addr == 12'h60c); + decoded_reg_strb.HMAC384_KV_WR_CTRL = cpuif_req_masked & (cpuif_addr == 12'h610); + decoded_reg_strb.HMAC384_KV_WR_STATUS = cpuif_req_masked & (cpuif_addr == 12'h614); + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h80c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h810); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h814); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h818); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h81c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h820); + decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h900); + decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h904); + decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h908); + decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h90c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h980); + decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha00); + decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha04); + decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha08); + decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha0c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha10); end // Pass down signals to next stage @@ -160,10 +162,6 @@ module hmac_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -706,12 +704,14 @@ module hmac_reg ( // Field: hmac_reg.HMAC384_CTRL.INIT always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_CTRL.INIT.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_CTRL.INIT.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_CTRL.INIT.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -720,7 +720,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_CTRL.INIT.value <= 'h0; + field_storage.HMAC384_CTRL.INIT.value <= 1'h0; end else if(field_combo.HMAC384_CTRL.INIT.load_next) begin field_storage.HMAC384_CTRL.INIT.value <= field_combo.HMAC384_CTRL.INIT.next; end @@ -728,12 +728,14 @@ module hmac_reg ( assign hwif_out.HMAC384_CTRL.INIT.value = field_storage.HMAC384_CTRL.INIT.value; // Field: hmac_reg.HMAC384_CTRL.NEXT always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_CTRL.NEXT.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_CTRL.NEXT.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_CTRL.NEXT.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -742,7 +744,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_CTRL.NEXT.value <= 'h0; + field_storage.HMAC384_CTRL.NEXT.value <= 1'h0; end else if(field_combo.HMAC384_CTRL.NEXT.load_next) begin field_storage.HMAC384_CTRL.NEXT.value <= field_combo.HMAC384_CTRL.NEXT.next; end @@ -750,12 +752,14 @@ module hmac_reg ( assign hwif_out.HMAC384_CTRL.NEXT.value = field_storage.HMAC384_CTRL.NEXT.value; // Field: hmac_reg.HMAC384_CTRL.ZEROIZE always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_CTRL.ZEROIZE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_CTRL.ZEROIZE.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_CTRL.ZEROIZE.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -764,7 +768,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_CTRL.ZEROIZE.value <= 'h0; + field_storage.HMAC384_CTRL.ZEROIZE.value <= 1'h0; end else if(field_combo.HMAC384_CTRL.ZEROIZE.load_next) begin field_storage.HMAC384_CTRL.ZEROIZE.value <= field_combo.HMAC384_CTRL.ZEROIZE.next; end @@ -773,8 +777,10 @@ module hmac_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: hmac_reg.HMAC384_KEY[].KEY always_comb begin - automatic logic [31:0] next_c = field_storage.HMAC384_KEY[i0].KEY.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KEY[i0].KEY.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KEY[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KEY[i0].KEY.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -790,7 +796,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KEY[i0].KEY.value <= 'h0; + field_storage.HMAC384_KEY[i0].KEY.value <= 32'h0; end else if(field_combo.HMAC384_KEY[i0].KEY.load_next) begin field_storage.HMAC384_KEY[i0].KEY.value <= field_combo.HMAC384_KEY[i0].KEY.next; end @@ -800,8 +806,10 @@ module hmac_reg ( for(genvar i0=0; i0<32; i0++) begin // Field: hmac_reg.HMAC384_BLOCK[].BLOCK always_comb begin - automatic logic [31:0] next_c = field_storage.HMAC384_BLOCK[i0].BLOCK.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_BLOCK[i0].BLOCK.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_BLOCK[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_BLOCK[i0].BLOCK.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -817,7 +825,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_BLOCK[i0].BLOCK.value <= 'h0; + field_storage.HMAC384_BLOCK[i0].BLOCK.value <= 32'h0; end else if(field_combo.HMAC384_BLOCK[i0].BLOCK.load_next) begin field_storage.HMAC384_BLOCK[i0].BLOCK.value <= field_combo.HMAC384_BLOCK[i0].BLOCK.next; end @@ -827,21 +835,23 @@ module hmac_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: hmac_reg.HMAC384_TAG[].TAG always_comb begin - automatic logic [31:0] next_c = field_storage.HMAC384_TAG[i0].TAG.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.HMAC384_TAG[i0].TAG.next; - load_next_c = '1; - end else if(hwif_in.HMAC384_TAG[i0].TAG.hwclr) begin // HW Clear + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_TAG[i0].TAG.value; + load_next_c = '0; + if(hwif_in.HMAC384_TAG[i0].TAG.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; + end else begin // HW Write + next_c = hwif_in.HMAC384_TAG[i0].TAG.next; + load_next_c = '1; end field_combo.HMAC384_TAG[i0].TAG.next = next_c; field_combo.HMAC384_TAG[i0].TAG.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_TAG[i0].TAG.value <= 'h0; + field_storage.HMAC384_TAG[i0].TAG.value <= 32'h0; end else if(field_combo.HMAC384_TAG[i0].TAG.load_next) begin field_storage.HMAC384_TAG[i0].TAG.value <= field_combo.HMAC384_TAG[i0].TAG.next; end @@ -850,8 +860,10 @@ module hmac_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: hmac_reg.HMAC384_LFSR_SEED[].LFSR_SEED always_comb begin - automatic logic [31:0] next_c = field_storage.HMAC384_LFSR_SEED[i0].LFSR_SEED.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_LFSR_SEED[i0].LFSR_SEED.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_LFSR_SEED[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_LFSR_SEED[i0].LFSR_SEED.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -861,7 +873,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_LFSR_SEED[i0].LFSR_SEED.value <= 'h3cabffb0; + field_storage.HMAC384_LFSR_SEED[i0].LFSR_SEED.value <= 32'h3cabffb0; end else if(field_combo.HMAC384_LFSR_SEED[i0].LFSR_SEED.load_next) begin field_storage.HMAC384_LFSR_SEED[i0].LFSR_SEED.value <= field_combo.HMAC384_LFSR_SEED[i0].LFSR_SEED.next; end @@ -870,8 +882,10 @@ module hmac_reg ( end // Field: hmac_reg.HMAC384_KV_RD_KEY_CTRL.read_en always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_KEY_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -884,7 +898,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value <= 'h0; + field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value <= 1'h0; end else if(field_combo.HMAC384_KV_RD_KEY_CTRL.read_en.load_next) begin field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value <= field_combo.HMAC384_KV_RD_KEY_CTRL.read_en.next; end @@ -892,8 +906,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_KEY_CTRL.read_en.value = field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value; // Field: hmac_reg.HMAC384_KV_RD_KEY_CTRL.read_entry always_comb begin - automatic logic [4:0] next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_KEY_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -903,7 +919,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value <= 'h0; + field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value <= 5'h0; end else if(field_combo.HMAC384_KV_RD_KEY_CTRL.read_entry.load_next) begin field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value <= field_combo.HMAC384_KV_RD_KEY_CTRL.read_entry.next; end @@ -911,8 +927,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_KEY_CTRL.read_entry.value = field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value; // Field: hmac_reg.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_KEY_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -922,7 +940,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value <= 'h0; + field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value <= 1'h0; end else if(field_combo.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.load_next) begin field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value <= field_combo.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.next; end @@ -930,8 +948,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value = field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value; // Field: hmac_reg.HMAC384_KV_RD_KEY_CTRL.rsvd always_comb begin - automatic logic [24:0] next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [24:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_KEY_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value & ~decoded_wr_biten[31:7]) | (decoded_wr_data[31:7] & decoded_wr_biten[31:7]); load_next_c = '1; @@ -941,7 +961,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value <= 'h0; + field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value <= 25'h0; end else if(field_combo.HMAC384_KV_RD_KEY_CTRL.rsvd.load_next) begin field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value <= field_combo.HMAC384_KV_RD_KEY_CTRL.rsvd.next; end @@ -949,8 +969,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_KEY_CTRL.rsvd.value = field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value; // Field: hmac_reg.HMAC384_KV_RD_KEY_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_RD_KEY_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_KEY_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.HMAC384_KV_RD_KEY_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -963,15 +985,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_KEY_STATUS.VALID.value <= 'h0; + field_storage.HMAC384_KV_RD_KEY_STATUS.VALID.value <= 1'h0; end else if(field_combo.HMAC384_KV_RD_KEY_STATUS.VALID.load_next) begin field_storage.HMAC384_KV_RD_KEY_STATUS.VALID.value <= field_combo.HMAC384_KV_RD_KEY_STATUS.VALID.next; end end // Field: hmac_reg.HMAC384_KV_RD_BLOCK_CTRL.read_en always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_BLOCK_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -984,7 +1008,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value <= 'h0; + field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value <= 1'h0; end else if(field_combo.HMAC384_KV_RD_BLOCK_CTRL.read_en.load_next) begin field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value <= field_combo.HMAC384_KV_RD_BLOCK_CTRL.read_en.next; end @@ -992,8 +1016,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_BLOCK_CTRL.read_en.value = field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value; // Field: hmac_reg.HMAC384_KV_RD_BLOCK_CTRL.read_entry always_comb begin - automatic logic [4:0] next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_BLOCK_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -1003,7 +1029,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value <= 'h0; + field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value <= 5'h0; end else if(field_combo.HMAC384_KV_RD_BLOCK_CTRL.read_entry.load_next) begin field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value <= field_combo.HMAC384_KV_RD_BLOCK_CTRL.read_entry.next; end @@ -1011,8 +1037,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value = field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value; // Field: hmac_reg.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_BLOCK_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -1022,7 +1050,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value <= 'h0; + field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value <= 1'h0; end else if(field_combo.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.load_next) begin field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value <= field_combo.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.next; end @@ -1030,8 +1058,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value = field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value; // Field: hmac_reg.HMAC384_KV_RD_BLOCK_CTRL.rsvd always_comb begin - automatic logic [24:0] next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [24:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_BLOCK_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value & ~decoded_wr_biten[31:7]) | (decoded_wr_data[31:7] & decoded_wr_biten[31:7]); load_next_c = '1; @@ -1041,7 +1071,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value <= 'h0; + field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value <= 25'h0; end else if(field_combo.HMAC384_KV_RD_BLOCK_CTRL.rsvd.load_next) begin field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value <= field_combo.HMAC384_KV_RD_BLOCK_CTRL.rsvd.next; end @@ -1049,8 +1079,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value = field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value; // Field: hmac_reg.HMAC384_KV_RD_BLOCK_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_RD_BLOCK_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_BLOCK_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.HMAC384_KV_RD_BLOCK_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1063,15 +1095,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_BLOCK_STATUS.VALID.value <= 'h0; + field_storage.HMAC384_KV_RD_BLOCK_STATUS.VALID.value <= 1'h0; end else if(field_combo.HMAC384_KV_RD_BLOCK_STATUS.VALID.load_next) begin field_storage.HMAC384_KV_RD_BLOCK_STATUS.VALID.value <= field_combo.HMAC384_KV_RD_BLOCK_STATUS.VALID.next; end end // Field: hmac_reg.HMAC384_KV_WR_CTRL.write_en always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_CTRL.write_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.write_en.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.write_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1084,7 +1118,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.write_en.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.write_en.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.write_en.load_next) begin field_storage.HMAC384_KV_WR_CTRL.write_en.value <= field_combo.HMAC384_KV_WR_CTRL.write_en.next; end @@ -1092,8 +1126,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.write_en.value = field_storage.HMAC384_KV_WR_CTRL.write_en.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.write_entry always_comb begin - automatic logic [4:0] next_c = field_storage.HMAC384_KV_WR_CTRL.write_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.write_entry.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.write_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -1103,7 +1139,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.write_entry.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.write_entry.value <= 5'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.write_entry.load_next) begin field_storage.HMAC384_KV_WR_CTRL.write_entry.value <= field_combo.HMAC384_KV_WR_CTRL.write_entry.next; end @@ -1111,8 +1147,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.write_entry.value = field_storage.HMAC384_KV_WR_CTRL.write_entry.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.hmac_key_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -1122,7 +1160,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.load_next) begin field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value <= field_combo.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.next; end @@ -1130,8 +1168,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value = field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.hmac_block_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value & ~decoded_wr_biten[7:7]) | (decoded_wr_data[7:7] & decoded_wr_biten[7:7]); load_next_c = '1; @@ -1141,7 +1181,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.load_next) begin field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value <= field_combo.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.next; end @@ -1149,8 +1189,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value = field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.sha_block_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]); load_next_c = '1; @@ -1160,7 +1202,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.sha_block_dest_valid.load_next) begin field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value <= field_combo.HMAC384_KV_WR_CTRL.sha_block_dest_valid.next; end @@ -1168,8 +1210,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value = field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value & ~decoded_wr_biten[9:9]) | (decoded_wr_data[9:9] & decoded_wr_biten[9:9]); load_next_c = '1; @@ -1179,7 +1223,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.load_next) begin field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value <= field_combo.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.next; end @@ -1187,8 +1231,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value = field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value & ~decoded_wr_biten[10:10]) | (decoded_wr_data[10:10] & decoded_wr_biten[10:10]); load_next_c = '1; @@ -1198,7 +1244,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.load_next) begin field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value <= field_combo.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.next; end @@ -1206,8 +1252,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value = field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.rsvd always_comb begin - automatic logic [20:0] next_c = field_storage.HMAC384_KV_WR_CTRL.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [20:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.rsvd.value & ~decoded_wr_biten[31:11]) | (decoded_wr_data[31:11] & decoded_wr_biten[31:11]); load_next_c = '1; @@ -1217,7 +1265,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.rsvd.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.rsvd.value <= 21'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.rsvd.load_next) begin field_storage.HMAC384_KV_WR_CTRL.rsvd.value <= field_combo.HMAC384_KV_WR_CTRL.rsvd.next; end @@ -1225,8 +1273,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.rsvd.value = field_storage.HMAC384_KV_WR_CTRL.rsvd.value; // Field: hmac_reg.HMAC384_KV_WR_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.HMAC384_KV_WR_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1239,15 +1289,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_STATUS.VALID.value <= 'h0; + field_storage.HMAC384_KV_WR_STATUS.VALID.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_STATUS.VALID.load_next) begin field_storage.HMAC384_KV_WR_STATUS.VALID.value <= field_combo.HMAC384_KV_WR_STATUS.VALID.next; end end // Field: hmac_reg.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1257,15 +1309,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; end end // Field: hmac_reg.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -1275,15 +1329,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; end end // Field: hmac_reg.intr_block_rf.error_intr_en_r.error0_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error0_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1293,15 +1349,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error0_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= field_combo.intr_block_rf.error_intr_en_r.error0_en.next; end end // Field: hmac_reg.intr_block_rf.error_intr_en_r.error1_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error1_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -1311,15 +1369,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error1_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= field_combo.intr_block_rf.error_intr_en_r.error1_en.next; end end // Field: hmac_reg.intr_block_rf.error_intr_en_r.error2_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error2_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -1329,15 +1389,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error2_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= field_combo.intr_block_rf.error_intr_en_r.error2_en.next; end end // Field: hmac_reg.intr_block_rf.error_intr_en_r.error3_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error3_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -1347,15 +1409,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error3_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= field_combo.intr_block_rf.error_intr_en_r.error3_en.next; end end // Field: hmac_reg.intr_block_rf.notif_intr_en_r.notif_cmd_done_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1365,25 +1429,27 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.next; end end // Field: hmac_reg.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; end @@ -1392,18 +1458,20 @@ module hmac_reg ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: hmac_reg.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; end @@ -1412,9 +1480,11 @@ module hmac_reg ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: hmac_reg.intr_block_rf.error_internal_intr_r.error0_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error0_sts.hwset) begin // HW Set @@ -1429,16 +1499,18 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error0_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error0_sts.next; end end // Field: hmac_reg.intr_block_rf.error_internal_intr_r.error1_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error1_sts.hwset) begin // HW Set @@ -1453,16 +1525,18 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error1_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error1_sts.next; end end // Field: hmac_reg.intr_block_rf.error_internal_intr_r.error2_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error2_sts.hwset) begin // HW Set @@ -1477,16 +1551,18 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error2_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error2_sts.next; end end // Field: hmac_reg.intr_block_rf.error_internal_intr_r.error3_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error3_sts.hwset) begin // HW Set @@ -1501,7 +1577,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error3_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error3_sts.next; end @@ -1513,9 +1589,11 @@ module hmac_reg ( || |(field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value & field_storage.intr_block_rf.error_intr_en_r.error3_en.value); // Field: hmac_reg.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset) begin // HW Set @@ -1530,7 +1608,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.next; end @@ -1539,12 +1617,14 @@ module hmac_reg ( |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value); // Field: hmac_reg.intr_block_rf.error_intr_trig_r.error0_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1553,19 +1633,21 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error0_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error0_trig.next; end end // Field: hmac_reg.intr_block_rf.error_intr_trig_r.error1_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1574,19 +1656,21 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error1_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error1_trig.next; end end // Field: hmac_reg.intr_block_rf.error_intr_trig_r.error2_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1595,19 +1679,21 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error2_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error2_trig.next; end end // Field: hmac_reg.intr_block_rf.error_intr_trig_r.error3_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1616,19 +1702,21 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error3_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error3_trig.next; end end // Field: hmac_reg.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1637,31 +1725,33 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.next; end end // Field: hmac_reg.intr_block_rf.error0_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error0_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error0_intr_count_r.cnt.next = next_c; @@ -1669,31 +1759,33 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error0_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= field_combo.intr_block_rf.error0_intr_count_r.cnt.next; end end // Field: hmac_reg.intr_block_rf.error1_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error1_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error1_intr_count_r.cnt.next = next_c; @@ -1701,31 +1793,33 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error1_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= field_combo.intr_block_rf.error1_intr_count_r.cnt.next; end end // Field: hmac_reg.intr_block_rf.error2_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error2_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error2_intr_count_r.cnt.next = next_c; @@ -1733,31 +1827,33 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error2_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= field_combo.intr_block_rf.error2_intr_count_r.cnt.next; end end // Field: hmac_reg.intr_block_rf.error3_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error3_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error3_intr_count_r.cnt.next = next_c; @@ -1765,31 +1861,33 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error3_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= field_combo.intr_block_rf.error3_intr_count_r.cnt.next; end end // Field: hmac_reg.intr_block_rf.notif_cmd_done_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next = next_c; @@ -1797,15 +1895,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next; end end // Field: hmac_reg.intr_block_rf.error0_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; @@ -1814,27 +1914,29 @@ module hmac_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next; end end // Field: hmac_reg.intr_block_rf.error1_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; @@ -1843,27 +1945,29 @@ module hmac_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next; end end // Field: hmac_reg.intr_block_rf.error2_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; @@ -1872,27 +1976,29 @@ module hmac_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next; end end // Field: hmac_reg.intr_block_rf.error3_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; @@ -1901,27 +2007,29 @@ module hmac_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next; end end // Field: hmac_reg.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; @@ -1930,30 +2038,39 @@ module hmac_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [42-1:0][31:0] readback_array; for(genvar i0=0; i0<2; i0++) begin @@ -2056,4 +2173,4 @@ module hmac_reg ( `CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.error_reset_b) -endmodule \ No newline at end of file +endmodule diff --git a/src/hmac/rtl/hmac_reg_pkg.sv b/src/hmac/rtl/hmac_reg_pkg.sv index 2f107b551..99a136ce1 100644 --- a/src/hmac/rtl/hmac_reg_pkg.sv +++ b/src/hmac/rtl/hmac_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package hmac_reg_pkg; + + localparam HMAC_REG_DATA_WIDTH = 32; + localparam HMAC_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic [31:0] next; } hmac_reg__HMAC384_NAME__NAME__in_t; @@ -66,7 +70,7 @@ package hmac_reg_pkg; typedef struct packed{ kv_read_ctrl_reg__read_en__in_t read_en; - } __kv_read_ctrl_reg__in_t; + } kv_read_ctrl_reg__in_t; typedef struct packed{ logic next; @@ -85,7 +89,7 @@ package hmac_reg_pkg; kv_status_reg__READY__in_t READY; kv_status_reg__VALID__in_t VALID; kv_status_reg__ERROR__in_t ERROR; - } __kv_status_reg__in_t; + } kv_status_reg__in_t; typedef struct packed{ logic hwclr; @@ -93,37 +97,37 @@ package hmac_reg_pkg; typedef struct packed{ kv_write_ctrl_reg__write_en__in_t write_en; - } __kv_write_ctrl_reg__in_t; + } kv_write_ctrl_reg__in_t; typedef struct packed{ logic hwset; - } hmac_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t; + } hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } hmac_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t; + } hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } hmac_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t; + } hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } hmac_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t; + } hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t; typedef struct packed{ - hmac_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t error0_sts; - hmac_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t error1_sts; - hmac_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t error2_sts; - hmac_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t error3_sts; + hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t error0_sts; + hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t error1_sts; + hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t error2_sts; + hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t error3_sts; } hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__in_t; typedef struct packed{ logic hwset; - } hmac_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; + } hmac_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; typedef struct packed{ - hmac_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; + hmac_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; } hmac_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__in_t; typedef struct packed{ @@ -140,12 +144,12 @@ package hmac_reg_pkg; hmac_reg__HMAC384_KEY__in_t [12-1:0]HMAC384_KEY; hmac_reg__HMAC384_BLOCK__in_t [32-1:0]HMAC384_BLOCK; hmac_reg__HMAC384_TAG__in_t [12-1:0]HMAC384_TAG; - __kv_read_ctrl_reg__in_t HMAC384_KV_RD_KEY_CTRL; - __kv_status_reg__in_t HMAC384_KV_RD_KEY_STATUS; - __kv_read_ctrl_reg__in_t HMAC384_KV_RD_BLOCK_CTRL; - __kv_status_reg__in_t HMAC384_KV_RD_BLOCK_STATUS; - __kv_write_ctrl_reg__in_t HMAC384_KV_WR_CTRL; - __kv_status_reg__in_t HMAC384_KV_WR_STATUS; + kv_read_ctrl_reg__in_t HMAC384_KV_RD_KEY_CTRL; + kv_status_reg__in_t HMAC384_KV_RD_KEY_STATUS; + kv_read_ctrl_reg__in_t HMAC384_KV_RD_BLOCK_CTRL; + kv_status_reg__in_t HMAC384_KV_RD_BLOCK_STATUS; + kv_write_ctrl_reg__in_t HMAC384_KV_WR_CTRL; + kv_status_reg__in_t HMAC384_KV_WR_STATUS; hmac_reg__intr_block_t__in_t intr_block_rf; } hmac_reg__in_t; @@ -212,7 +216,7 @@ package hmac_reg_pkg; kv_read_ctrl_reg__read_entry__out_t read_entry; kv_read_ctrl_reg__pcr_hash_extend__out_t pcr_hash_extend; kv_read_ctrl_reg__rsvd__out_t rsvd; - } __kv_read_ctrl_reg__out_t; + } kv_read_ctrl_reg__out_t; typedef struct packed{ logic value; @@ -255,7 +259,7 @@ package hmac_reg_pkg; kv_write_ctrl_reg__ecc_pkey_dest_valid__out_t ecc_pkey_dest_valid; kv_write_ctrl_reg__ecc_seed_dest_valid__out_t ecc_seed_dest_valid; kv_write_ctrl_reg__rsvd__out_t rsvd; - } __kv_write_ctrl_reg__out_t; + } kv_write_ctrl_reg__out_t; typedef struct packed{ logic intr; @@ -285,12 +289,18 @@ package hmac_reg_pkg; hmac_reg__HMAC384_KEY__out_t [12-1:0]HMAC384_KEY; hmac_reg__HMAC384_BLOCK__out_t [32-1:0]HMAC384_BLOCK; hmac_reg__HMAC384_LFSR_SEED__out_t [12-1:0]HMAC384_LFSR_SEED; - __kv_read_ctrl_reg__out_t HMAC384_KV_RD_KEY_CTRL; - __kv_read_ctrl_reg__out_t HMAC384_KV_RD_BLOCK_CTRL; - __kv_write_ctrl_reg__out_t HMAC384_KV_WR_CTRL; + kv_read_ctrl_reg__out_t HMAC384_KV_RD_KEY_CTRL; + kv_read_ctrl_reg__out_t HMAC384_KV_RD_BLOCK_CTRL; + kv_write_ctrl_reg__out_t HMAC384_KV_WR_CTRL; hmac_reg__intr_block_t__out_t intr_block_rf; } hmac_reg__out_t; + typedef enum logic [31:0] { + kv_status_reg__ERROR__kv_error_e__SUCCESS = 'h0, + kv_status_reg__ERROR__kv_error_e__KV_READ_FAIL = 'h1, + kv_status_reg__ERROR__kv_error_e__KV_WRITE_FAIL = 'h2 + } kv_status_reg__ERROR__kv_error_e_e; + localparam HMAC_REG_ADDR_WIDTH = 32'd12; endpackage \ No newline at end of file diff --git a/src/hmac_drbg/rtl/hmac_drbg.sv b/src/hmac_drbg/rtl/hmac_drbg.sv index bba6de226..2ddb1b472 100644 --- a/src/hmac_drbg/rtl/hmac_drbg.sv +++ b/src/hmac_drbg/rtl/hmac_drbg.sv @@ -180,7 +180,7 @@ module hmac_drbg end else begin - unique casez (drbg_st_reg) + unique case (drbg_st_reg) IDLE_ST: begin if (init_cmd | next_cmd) valid_reg <= 0; @@ -213,7 +213,7 @@ module hmac_drbg HMAC_init <= 0; HMAC_next <= 0; if (first_round) begin - unique casez(drbg_st_reg) + unique case(drbg_st_reg) K10_ST: HMAC_init <= 1; K11_ST: HMAC_next <= 1; V1_ST: HMAC_init <= 1; @@ -244,7 +244,7 @@ module hmac_drbg end else begin if (first_round) begin - unique casez(drbg_st_reg) + unique case(drbg_st_reg) INIT_ST: begin K_reg <= K_init; V_reg <= V_init; @@ -267,7 +267,7 @@ module hmac_drbg always_comb begin : hmac_block_update HMAC_key = K_reg; - unique casez(drbg_st_reg) + unique case(drbg_st_reg) K10_ST: HMAC_block = {V_reg, cnt_reg, entropy, nonce[383:136]}; K11_ST: HMAC_block = {nonce[135:0], 1'h1, 875'b0, 12'h888}; V1_ST: HMAC_block = {V_reg, 1'h1, ZERO_PAD_V, V_SIZE}; @@ -288,7 +288,7 @@ module hmac_drbg else if (zeroize) cnt_reg <= '0; else begin - unique casez (drbg_st_reg) + unique case (drbg_st_reg) INIT_ST: cnt_reg <= '0; NEXT_ST: cnt_reg <= cnt_reg + 1; K2_INIT_ST: cnt_reg <= cnt_reg + 1; @@ -326,11 +326,11 @@ module hmac_drbg always_comb begin: state_logic - unique casez (drbg_st_reg) + unique case (drbg_st_reg) IDLE_ST: // IDLE WAIT begin if (HMAC_ready) begin - unique casez ({init_cmd, next_cmd}) + unique case ({init_cmd, next_cmd}) 2'b10 : drbg_next_st = INIT_ST; 2'b01 : drbg_next_st = NEXT_ST; default: drbg_next_st = IDLE_ST; diff --git a/src/integration/asserts/caliptra_top_sva.sv b/src/integration/asserts/caliptra_top_sva.sv index bb6d75e67..d84b277f4 100644 --- a/src/integration/asserts/caliptra_top_sva.sv +++ b/src/integration/asserts/caliptra_top_sva.sv @@ -138,14 +138,14 @@ module caliptra_top_sva KV_debug_value0: assert property ( @(posedge `SVA_RDC_CLK) disable iff(!`KEYVAULT_PATH.cptra_pwrgood) - $rose(~`CPTRA_TOP_PATH.cptra_security_state_Latched.debug_locked || `SOC_IFC_TOP_PATH.cptra_error_fatal || `CPTRA_TOP_PATH.cptra_scan_mode_Latched) && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 0) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword] == CLP_DEBUG_MODE_KV_0) + $rose(~`CPTRA_TOP_PATH.cptra_security_state_Latched.debug_locked || `SOC_IFC_TOP_PATH.cptra_error_fatal || `CPTRA_TOP_PATH.cptra_scan_mode_Latched) && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 0) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword].data.value == CLP_DEBUG_MODE_KV_0) ) else $display("SVA ERROR: KV not flushed with correct debug values"); KV_debug_value1: assert property ( @(posedge `SVA_RDC_CLK) disable iff(!`KEYVAULT_PATH.cptra_pwrgood) - $rose(~`CPTRA_TOP_PATH.cptra_security_state_Latched.debug_locked || `SOC_IFC_TOP_PATH.cptra_error_fatal || `CPTRA_TOP_PATH.cptra_scan_mode_Latched) && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 1) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword] == CLP_DEBUG_MODE_KV_1) + $rose(~`CPTRA_TOP_PATH.cptra_security_state_Latched.debug_locked || `SOC_IFC_TOP_PATH.cptra_error_fatal || `CPTRA_TOP_PATH.cptra_scan_mode_Latched) && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 1) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword].data.value == CLP_DEBUG_MODE_KV_1) ) else $display("SVA ERROR: KV not flushed with correct debug values"); end @@ -157,42 +157,42 @@ module caliptra_top_sva //sha512 block read kv_sha512_block_r_flow: assert property ( @(posedge `SVA_RDC_CLK) - $rose(`SHA512_PATH.kv_src_done & ~`SHA512_PATH.pcr_hash_extend_ip) && (dword < (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_CTRL[`SHA512_PATH.kv_read.read_entry].last_dword + 1)) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_read.read_entry][dword] == `SHA512_PATH.block_reg[dword]) + $rose(`SHA512_PATH.kv_src_done & ~`SHA512_PATH.pcr_hash_extend_ip) && (dword < (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_CTRL[`SHA512_PATH.kv_read.read_entry].last_dword.value + 1)) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_read.read_entry][dword].data.value == `SHA512_PATH.block_reg[dword]) ) - else $display("SVA ERROR: SHA384 block mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_read.read_entry][dword], `SHA512_PATH.block_reg[dword]); + else $display("SVA ERROR: SHA384 block mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_read.read_entry][dword].data.value, `SHA512_PATH.block_reg[dword]); //sha512 digest write if (dword < SHA512_DIG_NUM_DWORDS) begin kv_sha512_digest_w_flow: assert property ( @(posedge `SVA_RDC_CLK) - `SHA512_PATH.kv_dest_done & ~`SHA512_PATH.pcr_hash_extend_ip |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_write_ctrl_reg.write_entry][dword] == `SHA512_PATH.kv_reg[(KV_NUM_DWORDS-1) - dword]) + `SHA512_PATH.kv_dest_done & ~`SHA512_PATH.pcr_hash_extend_ip |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_write_ctrl_reg.write_entry][dword].data.value == `SHA512_PATH.kv_reg[(KV_NUM_DWORDS-1) - dword]) ) - else $display("SVA ERROR: SHA384 digest mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_write_ctrl_reg.write_entry][dword], `SHA512_PATH.kv_reg[(KV_NUM_DWORDS-1) - dword]); + else $display("SVA ERROR: SHA384 digest mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_write_ctrl_reg.write_entry][dword].data.value, `SHA512_PATH.kv_reg[(KV_NUM_DWORDS-1) - dword]); end //hmac block read kv_hmac_block_r_flow: assert property ( @(posedge `SVA_RDC_CLK) - $rose(`HMAC_PATH.kv_block_done) && (dword < (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_CTRL[`HMAC_PATH.kv_read[1].read_entry].last_dword + 1)) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[1].read_entry][dword] == `HMAC_PATH.block_reg[dword]) + $rose(`HMAC_PATH.kv_block_done) && (dword < (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_CTRL[`HMAC_PATH.kv_read[1].read_entry].last_dword.value + 1)) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[1].read_entry][dword].data.value == `HMAC_PATH.block_reg[dword]) ) - else $display("SVA ERROR: HMAC384 block mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[1].read_entry][dword], `HMAC_PATH.block_reg[dword]); + else $display("SVA ERROR: HMAC384 block mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[1].read_entry][dword].data.value, `HMAC_PATH.block_reg[dword]); //hmac key read if (dword < HMAC_KEY_NUM_DWORDS) begin kv_hmac_key_r_flow: assert property ( @(posedge `SVA_RDC_CLK) - $fell(`HMAC_PATH.kv_key_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[0].read_entry][dword] == `HMAC_PATH.key_reg[dword]) + $fell(`HMAC_PATH.kv_key_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[0].read_entry][dword].data.value == `HMAC_PATH.key_reg[dword]) ) - else $display("SVA ERROR: HMAC384 key mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[0].read_entry][dword], `HMAC_PATH.key_reg[dword]); + else $display("SVA ERROR: HMAC384 key mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[0].read_entry][dword].data.value, `HMAC_PATH.key_reg[dword]); end //hmac tag write if (dword < HMAC_TAG_NUM_DWORDS) begin kv_hmac_tag_w_flow: assert property ( @(posedge `SVA_RDC_CLK) - `HMAC_PATH.kv_write_done |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_write_ctrl_reg.write_entry][dword] == `HMAC_PATH.kv_reg[(`HMAC_PATH.TAG_NUM_DWORDS-1) - dword]) + `HMAC_PATH.kv_write_done |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_write_ctrl_reg.write_entry][dword].data.value == `HMAC_PATH.kv_reg[(`HMAC_PATH.TAG_NUM_DWORDS-1) - dword]) ) - else $display("SVA ERROR: HMAC384 tag mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_write_ctrl_reg.write_entry][dword], `HMAC_PATH.kv_reg[(`HMAC_PATH.TAG_NUM_DWORDS-1) - dword]); + else $display("SVA ERROR: HMAC384 tag mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_write_ctrl_reg.write_entry][dword].data.value, `HMAC_PATH.kv_reg[(`HMAC_PATH.TAG_NUM_DWORDS-1) - dword]); end // ECC @@ -200,20 +200,20 @@ module caliptra_top_sva //ecc privkey read kv_ecc_privkey_r_flow: assert property ( @(posedge `SVA_RDC_CLK) - $fell(`ECC_PATH.kv_privkey_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[0].read_entry][dword] == `ECC_PATH.privkey_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) + $fell(`ECC_PATH.kv_privkey_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[0].read_entry][dword].data.value == `ECC_PATH.privkey_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) ) - else $display("SVA ERROR: ECC privkey read mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[0].read_entry][dword], `ECC_PATH.privkey_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); + else $display("SVA ERROR: ECC privkey read mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[0].read_entry][dword].data.value, `ECC_PATH.privkey_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); kv_ecc_seed_r_flow: assert property ( @(posedge `SVA_RDC_CLK) - $fell(`ECC_PATH.kv_seed_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[1].read_entry][dword] == `ECC_PATH.seed_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) + $fell(`ECC_PATH.kv_seed_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[1].read_entry][dword].data.value == `ECC_PATH.seed_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) ) - else $display("SVA ERROR: ECC seed mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[1].read_entry][dword], `ECC_PATH.seed_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); + else $display("SVA ERROR: ECC seed mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[1].read_entry][dword].data.value, `ECC_PATH.seed_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); //ecc privkey write kv_ecc_privkey_w_flow: assert property ( @(posedge `SVA_RDC_CLK) - `ECC_PATH.kv_write_done |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_write_ctrl_reg.write_entry][dword] == `ECC_PATH.kv_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) + `ECC_PATH.kv_write_done |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_write_ctrl_reg.write_entry][dword].data.value == `ECC_PATH.kv_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) ) - else $display("SVA ERROR: ECC privkey write mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_write_ctrl_reg.write_entry][dword], `ECC_PATH.kv_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); + else $display("SVA ERROR: ECC privkey write mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_write_ctrl_reg.write_entry][dword].data.value, `ECC_PATH.kv_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); //ecc sign r pcr_ecc_sign_r: assert property ( @@ -252,10 +252,10 @@ module caliptra_top_sva DOE_UDS_data_check: assert property ( @(posedge `SVA_RDC_CLK) disable iff (`CPTRA_TOP_PATH.scan_mode || !`CPTRA_TOP_PATH.security_state.debug_locked) - (`SERVICES_PATH.WriteData == 'hEC && `SERVICES_PATH.mailbox_write) |=> ##[1:$] $rose(`DOE_PATH.lock_uds_flow) |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword] == `SERVICES_PATH.doe_test_vector.uds_plaintext[dword]) + (`SERVICES_PATH.WriteData == 'hEC && `SERVICES_PATH.mailbox_write) |=> ##[1:$] $rose(`DOE_PATH.lock_uds_flow) |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword].data.value == `SERVICES_PATH.doe_test_vector.uds_plaintext[dword]) ) - else $display("SVA ERROR: DOE UDS output %h does not match plaintext %h!", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword], `SERVICES_PATH.doe_test_vector.uds_plaintext[dword]); + else $display("SVA ERROR: DOE UDS output %h does not match plaintext %h!", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword].data.value, `SERVICES_PATH.doe_test_vector.uds_plaintext[dword]); end end endgenerate @@ -266,9 +266,9 @@ module caliptra_top_sva DOE_FE_data_check: assert property ( @(posedge `SVA_RDC_CLK) disable iff (`CPTRA_TOP_PATH.scan_mode || !`CPTRA_TOP_PATH.security_state.debug_locked) - (`SERVICES_PATH.WriteData == 'hED && `SERVICES_PATH.mailbox_write) |=> ##[1:$] $rose(`DOE_PATH.lock_fe_flow) |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword] == `SERVICES_PATH.doe_test_vector.fe_plaintext[dword]) + (`SERVICES_PATH.WriteData == 'hED && `SERVICES_PATH.mailbox_write) |=> ##[1:$] $rose(`DOE_PATH.lock_fe_flow) |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword].data.value == `SERVICES_PATH.doe_test_vector.fe_plaintext[dword]) ) - else $display("SVA ERROR: DOE FE output %h does not match plaintext %h!", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword], `SERVICES_PATH.doe_test_vector.fe_plaintext[dword]); + else $display("SVA ERROR: DOE FE output %h does not match plaintext %h!", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword].data.value, `SERVICES_PATH.doe_test_vector.fe_plaintext[dword]); end end diff --git a/src/integration/config/compile.yml b/src/integration/config/compile.yml index 49328dbb7..d741bcb8f 100644 --- a/src/integration/config/compile.yml +++ b/src/integration/config/compile.yml @@ -46,8 +46,8 @@ targets: rtl_lint: waiver_files: - $MSFT_REPO_ROOT/src/integration/config/design_lint/sglint_waivers - black_box: - - el2_veer_wrapper + options: + - '+define+CALIPTRA_INTERNAL_TRNG' cdc: tcl_files: - $COMPILE_ROOT/config/cdc/integration_top.constraints.tcl diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv index acab4367f..b68419cc1 100755 --- a/src/integration/rtl/caliptra_top.sv +++ b/src/integration/rtl/caliptra_top.sv @@ -269,6 +269,7 @@ module caliptra_top logic lsu_addr_ph, lsu_data_ph, lsu_sel; logic ic_addr_ph, ic_data_ph, ic_sel; + always_comb begin mbox_sram_cs = mbox_sram_req.cs; mbox_sram_we = mbox_sram_req.we; diff --git a/src/keyvault/config/compile.yml b/src/keyvault/config/compile.yml index 6bebe194c..c514f36fc 100644 --- a/src/keyvault/config/compile.yml +++ b/src/keyvault/config/compile.yml @@ -53,8 +53,6 @@ targets: directories: [] waiver_files: - $MSFT_REPO_ROOT/src/keyvault/config/design_lint/keyvault/sglint_waivers - black_box: - - kv_reg global: tool: vcs: diff --git a/src/keyvault/rtl/kv.sv b/src/keyvault/rtl/kv.sv index 4188fde2f..e92ad0838 100644 --- a/src/keyvault/rtl/kv.sv +++ b/src/keyvault/rtl/kv.sv @@ -171,7 +171,7 @@ always_comb begin : keyvault_ctrl kv_reg_hwif_in.KEY_CTRL[entry].last_dword.hwclr = key_entry_clear[entry]; kv_reg_hwif_in.KEY_CTRL[entry].dest_valid.we = key_entry_ctrl_we[entry] & ~key_entry_clear[entry]; - kv_reg_hwif_in.KEY_CTRL[entry].dest_valid.next = key_entry_dest_valid_next[entry]; + kv_reg_hwif_in.KEY_CTRL[entry].dest_valid.next = {3'd0,key_entry_dest_valid_next[entry]}; kv_reg_hwif_in.KEY_CTRL[entry].last_dword.we = key_entry_ctrl_we[entry] & ~key_entry_clear[entry]; kv_reg_hwif_in.KEY_CTRL[entry].last_dword.next = key_entry_last_dword_next[entry]; end @@ -215,7 +215,7 @@ always_comb begin : keyvault_readmux kv_reg_hwif_out.KEY_ENTRY[entry][dword].data.value : '0; end //signal last when reading the last dword - kv_rd_resp[client].last |= (kv_read[client].read_entry == entry) & (kv_read[client].read_offset == kv_reg_hwif_out.KEY_CTRL[entry].last_dword); + kv_rd_resp[client].last |= (kv_read[client].read_entry == entry) & (kv_read[client].read_offset == kv_reg_hwif_out.KEY_CTRL[entry].last_dword.value); kv_rd_resp[client].error |= (kv_read[client].read_entry == entry) & (lock_use_q[entry] | ~kv_reg_hwif_out.KEY_CTRL[entry].dest_valid.value[client]); end diff --git a/src/keyvault/rtl/kv_fsm.sv b/src/keyvault/rtl/kv_fsm.sv index d0c770834..675c0b343 100644 --- a/src/keyvault/rtl/kv_fsm.sv +++ b/src/keyvault/rtl/kv_fsm.sv @@ -86,7 +86,7 @@ always_comb ready = (kv_fsm_ps == KV_IDLE); // Padding starts with a leading 1 after the valid data followed by 0's until // the length of the valid data is stored in the last 4 dwords. // HMAC adds 1024 bits to the length to account for the key -always_comb length_for_pad = (HMAC == 1) ? (num_dwords_data << 5) + 'd1024 : (num_dwords_data << 5); +always_comb length_for_pad = (HMAC == 1) ? (32'b0 | ((num_dwords_data << 5) + 'd1024)) : (32'b0 | (num_dwords_data << 5)); always_comb arc_KV_IDLE_KV_RW = start; always_comb arc_KV_RW_KV_DONE = ((PAD == 0) | pcr_hash_extend) & (offset_nxt == num_dwords_total); //jump to done when we've written all dwords @@ -107,7 +107,7 @@ always_comb begin : kv_fsm_comb offset_nxt = '0; pad_data = '0; done = '0; - unique casez (kv_fsm_ps) + unique case (kv_fsm_ps) KV_IDLE: begin if (arc_KV_IDLE_KV_RW) kv_fsm_ns = KV_RW; end @@ -155,22 +155,37 @@ always_ff @(posedge clk or negedge rst_b) begin if (!rst_b) begin kv_fsm_ps <= KV_IDLE; offset <= '0; - num_dwords_data <= '0; end else if (zeroize) begin kv_fsm_ps <= KV_IDLE; offset <= '0; - num_dwords_data <= '0; end else begin kv_fsm_ps <= kv_fsm_ns; offset <= offset_rst ? '0 : offset_en ? offset_nxt : offset; - //store the offset_nxt on the last cycle of valid data, this is the number of dwords of valid data - num_dwords_data <= arc_KV_RW_KV_PAD ? offset_nxt : num_dwords_data; end end +generate + if (PAD==1) begin + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + num_dwords_data <= '0; + end + else if (zeroize) begin + num_dwords_data <= '0; + end + else begin + //store the offset_nxt on the last cycle of valid data, this is the number of dwords of valid data + num_dwords_data <= arc_KV_RW_KV_PAD ? offset_nxt : num_dwords_data; + end + end + end else begin + always_comb num_dwords_data = '0; + end +endgenerate + always_comb read_offset = (kv_fsm_ps == KV_RW) ? offset[OFFSET_W-1:0] : '0; always_comb write_offset = offset[OFFSET_W-1:0]; diff --git a/src/keyvault/rtl/kv_reg.sv b/src/keyvault/rtl/kv_reg.sv index 1c0f31660..5e00aca5d 100644 --- a/src/keyvault/rtl/kv_reg.sv +++ b/src/keyvault/rtl/kv_reg.sv @@ -58,7 +58,9 @@ module kv_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -76,14 +78,14 @@ module kv_reg ( always_comb begin for(int i0=0; i0<32; i0++) begin - decoded_reg_strb.KEY_CTRL[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); + decoded_reg_strb.KEY_CTRL[i0] = cpuif_req_masked & (cpuif_addr == 12'h0 + i0*12'h4); end for(int i0=0; i0<32; i0++) begin for(int i1=0; i1<12; i1++) begin - decoded_reg_strb.KEY_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 'h600 + i0*'h30 + i1*'h4); + decoded_reg_strb.KEY_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 12'h600 + i0*12'h30 + i1*12'h4); end end - decoded_reg_strb.CLEAR_SECRETS = cpuif_req_masked & (cpuif_addr == 'hc00); + decoded_reg_strb.CLEAR_SECRETS = cpuif_req_masked & (cpuif_addr == 12'hc00); end // Pass down signals to next stage @@ -92,10 +94,6 @@ module kv_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -192,8 +190,10 @@ module kv_reg ( for(genvar i0=0; i0<32; i0++) begin // Field: kv_reg.KEY_CTRL[].lock_wr always_comb begin - automatic logic [0:0] next_c = field_storage.KEY_CTRL[i0].lock_wr.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].lock_wr.value; + load_next_c = '0; if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr && !(hwif_in.KEY_CTRL[i0].lock_wr.swwel)) begin // SW write next_c = (field_storage.KEY_CTRL[i0].lock_wr.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -203,7 +203,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin if(~hwif_in.core_only_rst_b) begin - field_storage.KEY_CTRL[i0].lock_wr.value <= 'h0; + field_storage.KEY_CTRL[i0].lock_wr.value <= 1'h0; end else if(field_combo.KEY_CTRL[i0].lock_wr.load_next) begin field_storage.KEY_CTRL[i0].lock_wr.value <= field_combo.KEY_CTRL[i0].lock_wr.next; end @@ -211,8 +211,10 @@ module kv_reg ( assign hwif_out.KEY_CTRL[i0].lock_wr.value = field_storage.KEY_CTRL[i0].lock_wr.value; // Field: kv_reg.KEY_CTRL[].lock_use always_comb begin - automatic logic [0:0] next_c = field_storage.KEY_CTRL[i0].lock_use.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].lock_use.value; + load_next_c = '0; if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr && !(hwif_in.KEY_CTRL[i0].lock_use.swwel)) begin // SW write next_c = (field_storage.KEY_CTRL[i0].lock_use.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -222,7 +224,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin if(~hwif_in.core_only_rst_b) begin - field_storage.KEY_CTRL[i0].lock_use.value <= 'h0; + field_storage.KEY_CTRL[i0].lock_use.value <= 1'h0; end else if(field_combo.KEY_CTRL[i0].lock_use.load_next) begin field_storage.KEY_CTRL[i0].lock_use.value <= field_combo.KEY_CTRL[i0].lock_use.next; end @@ -230,12 +232,14 @@ module kv_reg ( assign hwif_out.KEY_CTRL[i0].lock_use.value = field_storage.KEY_CTRL[i0].lock_use.value; // Field: kv_reg.KEY_CTRL[].clear always_comb begin - automatic logic [0:0] next_c = field_storage.KEY_CTRL[i0].clear.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].clear.value; + load_next_c = '0; if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.KEY_CTRL[i0].clear.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -244,7 +248,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.KEY_CTRL[i0].clear.value <= 'h0; + field_storage.KEY_CTRL[i0].clear.value <= 1'h0; end else if(field_combo.KEY_CTRL[i0].clear.load_next) begin field_storage.KEY_CTRL[i0].clear.value <= field_combo.KEY_CTRL[i0].clear.next; end @@ -252,8 +256,10 @@ module kv_reg ( assign hwif_out.KEY_CTRL[i0].clear.value = field_storage.KEY_CTRL[i0].clear.value; // Field: kv_reg.KEY_CTRL[].rsvd0 always_comb begin - automatic logic [0:0] next_c = field_storage.KEY_CTRL[i0].rsvd0.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].rsvd0.value; + load_next_c = '0; if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.KEY_CTRL[i0].rsvd0.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -266,7 +272,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.KEY_CTRL[i0].rsvd0.value <= 'h0; + field_storage.KEY_CTRL[i0].rsvd0.value <= 1'h0; end else if(field_combo.KEY_CTRL[i0].rsvd0.load_next) begin field_storage.KEY_CTRL[i0].rsvd0.value <= field_combo.KEY_CTRL[i0].rsvd0.next; end @@ -274,8 +280,10 @@ module kv_reg ( assign hwif_out.KEY_CTRL[i0].rsvd0.value = field_storage.KEY_CTRL[i0].rsvd0.value; // Field: kv_reg.KEY_CTRL[].rsvd1 always_comb begin - automatic logic [4:0] next_c = field_storage.KEY_CTRL[i0].rsvd1.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].rsvd1.value; + load_next_c = '0; if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.KEY_CTRL[i0].rsvd1.value & ~decoded_wr_biten[8:4]) | (decoded_wr_data[8:4] & decoded_wr_biten[8:4]); load_next_c = '1; @@ -285,7 +293,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.KEY_CTRL[i0].rsvd1.value <= 'h0; + field_storage.KEY_CTRL[i0].rsvd1.value <= 5'h0; end else if(field_combo.KEY_CTRL[i0].rsvd1.load_next) begin field_storage.KEY_CTRL[i0].rsvd1.value <= field_combo.KEY_CTRL[i0].rsvd1.next; end @@ -293,8 +301,10 @@ module kv_reg ( assign hwif_out.KEY_CTRL[i0].rsvd1.value = field_storage.KEY_CTRL[i0].rsvd1.value; // Field: kv_reg.KEY_CTRL[].dest_valid always_comb begin - automatic logic [7:0] next_c = field_storage.KEY_CTRL[i0].dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [7:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].dest_valid.value; + load_next_c = '0; if(hwif_in.KEY_CTRL[i0].dest_valid.we) begin // HW Write - we next_c = hwif_in.KEY_CTRL[i0].dest_valid.next; load_next_c = '1; @@ -307,7 +317,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.KEY_CTRL[i0].dest_valid.value <= 'h0; + field_storage.KEY_CTRL[i0].dest_valid.value <= 8'h0; end else if(field_combo.KEY_CTRL[i0].dest_valid.load_next) begin field_storage.KEY_CTRL[i0].dest_valid.value <= field_combo.KEY_CTRL[i0].dest_valid.next; end @@ -315,8 +325,10 @@ module kv_reg ( assign hwif_out.KEY_CTRL[i0].dest_valid.value = field_storage.KEY_CTRL[i0].dest_valid.value; // Field: kv_reg.KEY_CTRL[].last_dword always_comb begin - automatic logic [3:0] next_c = field_storage.KEY_CTRL[i0].last_dword.value; - automatic logic load_next_c = '0; + automatic logic [3:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].last_dword.value; + load_next_c = '0; if(hwif_in.KEY_CTRL[i0].last_dword.we) begin // HW Write - we next_c = hwif_in.KEY_CTRL[i0].last_dword.next; load_next_c = '1; @@ -329,7 +341,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.KEY_CTRL[i0].last_dword.value <= 'h0; + field_storage.KEY_CTRL[i0].last_dword.value <= 4'h0; end else if(field_combo.KEY_CTRL[i0].last_dword.load_next) begin field_storage.KEY_CTRL[i0].last_dword.value <= field_combo.KEY_CTRL[i0].last_dword.next; end @@ -340,8 +352,10 @@ module kv_reg ( for(genvar i1=0; i1<12; i1++) begin // Field: kv_reg.KEY_ENTRY[][].data always_comb begin - automatic logic [31:0] next_c = field_storage.KEY_ENTRY[i0][i1].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_ENTRY[i0][i1].data.value; + load_next_c = '0; if(decoded_reg_strb.KEY_ENTRY[i0][i1] && decoded_req_is_wr && !(hwif_in.KEY_ENTRY[i0][i1].data.swwel)) begin // SW write next_c = (field_storage.KEY_ENTRY[i0][i1].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -357,7 +371,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.KEY_ENTRY[i0][i1].data.value <= 'h0; + field_storage.KEY_ENTRY[i0][i1].data.value <= 32'h0; end else if(field_combo.KEY_ENTRY[i0][i1].data.load_next) begin field_storage.KEY_ENTRY[i0][i1].data.value <= field_combo.KEY_ENTRY[i0][i1].data.next; end @@ -367,12 +381,14 @@ module kv_reg ( end // Field: kv_reg.CLEAR_SECRETS.wr_debug_values always_comb begin - automatic logic [0:0] next_c = field_storage.CLEAR_SECRETS.wr_debug_values.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CLEAR_SECRETS.wr_debug_values.value; + load_next_c = '0; if(decoded_reg_strb.CLEAR_SECRETS && decoded_req_is_wr) begin // SW write next_c = (field_storage.CLEAR_SECRETS.wr_debug_values.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -381,7 +397,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.CLEAR_SECRETS.wr_debug_values.value <= 'h0; + field_storage.CLEAR_SECRETS.wr_debug_values.value <= 1'h0; end else if(field_combo.CLEAR_SECRETS.wr_debug_values.load_next) begin field_storage.CLEAR_SECRETS.wr_debug_values.value <= field_combo.CLEAR_SECRETS.wr_debug_values.next; end @@ -389,8 +405,10 @@ module kv_reg ( assign hwif_out.CLEAR_SECRETS.wr_debug_values.value = field_storage.CLEAR_SECRETS.wr_debug_values.value; // Field: kv_reg.CLEAR_SECRETS.sel_debug_value always_comb begin - automatic logic [0:0] next_c = field_storage.CLEAR_SECRETS.sel_debug_value.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CLEAR_SECRETS.sel_debug_value.value; + load_next_c = '0; if(decoded_reg_strb.CLEAR_SECRETS && decoded_req_is_wr) begin // SW write next_c = (field_storage.CLEAR_SECRETS.sel_debug_value.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -400,19 +418,28 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.CLEAR_SECRETS.sel_debug_value.value <= 'h0; + field_storage.CLEAR_SECRETS.sel_debug_value.value <= 1'h0; end else if(field_combo.CLEAR_SECRETS.sel_debug_value.load_next) begin field_storage.CLEAR_SECRETS.sel_debug_value.value <= field_combo.CLEAR_SECRETS.sel_debug_value.next; end end assign hwif_out.CLEAR_SECRETS.sel_debug_value.value = field_storage.CLEAR_SECRETS.sel_debug_value.value; + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [33-1:0][31:0] readback_array; for(genvar i0=0; i0<32; i0++) begin @@ -445,4 +472,4 @@ module kv_reg ( `CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.hard_reset_b) -endmodule \ No newline at end of file +endmodule diff --git a/src/keyvault/rtl/kv_reg_pkg.sv b/src/keyvault/rtl/kv_reg_pkg.sv index 780e9574b..279f76d66 100644 --- a/src/keyvault/rtl/kv_reg_pkg.sv +++ b/src/keyvault/rtl/kv_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package kv_reg_pkg; + + localparam KV_REG_DATA_WIDTH = 32; + localparam KV_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic swwel; } kv_reg__kvCtrl__lock_wr__in_t; diff --git a/src/kmac/config/compile.yml b/src/kmac/config/compile.yml index 7280c6a78..1c1e66774 100644 --- a/src/kmac/config/compile.yml +++ b/src/kmac/config/compile.yml @@ -22,3 +22,7 @@ targets: - $COMPILE_ROOT/rtl/sha3pad.sv - $COMPILE_ROOT/rtl/sha3.sv tops: [sha3] + rtl_lint: + directories: [] + waiver_files: [] + tops: [sha3] diff --git a/src/kmac/rtl/keccak_2share.sv b/src/kmac/rtl/keccak_2share.sv index ff25c2d0a..79f866e68 100644 --- a/src/kmac/rtl/keccak_2share.sv +++ b/src/kmac/rtl/keccak_2share.sv @@ -479,8 +479,8 @@ module keccak_2share // C[x,z] = A[x,0,z] ^ A[x,1,z] ^ A[x,2,z] ^ A[x,3,z] ^ A[x,4,z] // D[x,z] = C[x-1,z] ^ C[x+1,z-1] // theta = A[x,y,z] ^ D[x,z] - parameter int ThetaIndexX1 [5] = '{4, 0, 1, 2, 3}; // (x-1)%5 - parameter int ThetaIndexX2 [5] = '{1, 2, 3, 4, 0}; // (x+1)%5 + parameter logic [2:0] ThetaIndexX1 [5] = '{4, 0, 1, 2, 3}; // (x-1)%5 + parameter logic [2:0] ThetaIndexX2 [5] = '{1, 2, 3, 4, 0}; // (x+1)%5 function automatic box_t theta(box_t state); plane_t c; plane_t d; @@ -490,7 +490,7 @@ module keccak_2share end for (int x = 0 ; x < 5 ; x++) begin for (int z = 0 ; z < W ; z++) begin - int index_z; + logic [$clog2(W)-1:0] index_z; index_z = (z == 0) ? W-1 : z-1; // (z+1)%W d[x][z] = c[ThetaIndexX1[x]][z] ^ c[ThetaIndexX2[x]][index_z]; end @@ -544,7 +544,7 @@ module keccak_2share // pi // rearrange the position of lanes // pi[x,y,z] = state[(x+3y),x,z] - localparam int PiRotate [5][5] = '{ + localparam logic [2:0] PiRotate [5][5] = '{ //y 0 1 2 3 4 x '{ 0, 3, 1, 4, 2},// 0 '{ 1, 4, 2, 0, 3},// 1 @@ -564,8 +564,8 @@ module keccak_2share // chi // chi[x,y,z] = state[x,y,z] ^ ((state[x+1,y,z] ^ 1) & state[x+2,y,z]) - parameter int ChiIndexX1 [5] = '{1, 2, 3, 4, 0}; // (x+1)%5 - parameter int ChiIndexX2 [5] = '{2, 3, 4, 0, 1}; // (x+2)%5 + parameter logic [2:0] ChiIndexX1 [5] = '{1, 2, 3, 4, 0}; // (x+1)%5 + parameter logic [2:0] ChiIndexX2 [5] = '{2, 3, 4, 0, 1}; // (x+2)%5 function automatic box_t chi(box_t state); box_t result; for (int x = 0 ; x < 5 ; x++) begin diff --git a/src/pcrvault/config/compile.yml b/src/pcrvault/config/compile.yml index b52d4c33e..dbb6d8a12 100644 --- a/src/pcrvault/config/compile.yml +++ b/src/pcrvault/config/compile.yml @@ -53,8 +53,6 @@ targets: directories: [] waiver_files: - $MSFT_REPO_ROOT/src/pcrvault/config/design_lint/pcrvault/sglint_waivers - black_box: - - pv_reg global: tool: vcs: diff --git a/src/pcrvault/rtl/pv_gen_hash.sv b/src/pcrvault/rtl/pv_gen_hash.sv index 5ce7fb8b2..990fe9e73 100644 --- a/src/pcrvault/rtl/pv_gen_hash.sv +++ b/src/pcrvault/rtl/pv_gen_hash.sv @@ -199,6 +199,7 @@ assign block_offset = block_offset_i[BLOCK_OFFSET_W-1:0]; if (~rst_b) begin gen_hash_fsm_ps <= GEN_HASH_IDLE; block_offset_i <= '0; + nonce_offset_i <= '0; read_entry <= '0; read_offset <= '0; end diff --git a/src/pcrvault/rtl/pv_reg.sv b/src/pcrvault/rtl/pv_reg.sv index 273cdd72b..fee15c434 100644 --- a/src/pcrvault/rtl/pv_reg.sv +++ b/src/pcrvault/rtl/pv_reg.sv @@ -58,7 +58,9 @@ module pv_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -75,11 +77,11 @@ module pv_reg ( always_comb begin for(int i0=0; i0<32; i0++) begin - decoded_reg_strb.PCR_CTRL[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); + decoded_reg_strb.PCR_CTRL[i0] = cpuif_req_masked & (cpuif_addr == 12'h0 + i0*12'h4); end for(int i0=0; i0<32; i0++) begin for(int i1=0; i1<12; i1++) begin - decoded_reg_strb.PCR_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 'h600 + i0*'h30 + i1*'h4); + decoded_reg_strb.PCR_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 12'h600 + i0*12'h30 + i1*12'h4); end end end @@ -90,10 +92,6 @@ module pv_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -151,8 +149,10 @@ module pv_reg ( for(genvar i0=0; i0<32; i0++) begin // Field: pv_reg.PCR_CTRL[].lock always_comb begin - automatic logic [0:0] next_c = field_storage.PCR_CTRL[i0].lock.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.PCR_CTRL[i0].lock.value; + load_next_c = '0; if(decoded_reg_strb.PCR_CTRL[i0] && decoded_req_is_wr && !(hwif_in.PCR_CTRL[i0].lock.swwel)) begin // SW write next_c = (field_storage.PCR_CTRL[i0].lock.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -162,7 +162,7 @@ module pv_reg ( end always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin if(~hwif_in.core_only_rst_b) begin - field_storage.PCR_CTRL[i0].lock.value <= 'h0; + field_storage.PCR_CTRL[i0].lock.value <= 1'h0; end else if(field_combo.PCR_CTRL[i0].lock.load_next) begin field_storage.PCR_CTRL[i0].lock.value <= field_combo.PCR_CTRL[i0].lock.next; end @@ -170,12 +170,14 @@ module pv_reg ( assign hwif_out.PCR_CTRL[i0].lock.value = field_storage.PCR_CTRL[i0].lock.value; // Field: pv_reg.PCR_CTRL[].clear always_comb begin - automatic logic [0:0] next_c = field_storage.PCR_CTRL[i0].clear.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.PCR_CTRL[i0].clear.value; + load_next_c = '0; if(decoded_reg_strb.PCR_CTRL[i0] && decoded_req_is_wr && !(hwif_in.PCR_CTRL[i0].clear.swwel)) begin // SW write next_c = (field_storage.PCR_CTRL[i0].clear.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -184,7 +186,7 @@ module pv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.PCR_CTRL[i0].clear.value <= 'h0; + field_storage.PCR_CTRL[i0].clear.value <= 1'h0; end else if(field_combo.PCR_CTRL[i0].clear.load_next) begin field_storage.PCR_CTRL[i0].clear.value <= field_combo.PCR_CTRL[i0].clear.next; end @@ -192,8 +194,10 @@ module pv_reg ( assign hwif_out.PCR_CTRL[i0].clear.value = field_storage.PCR_CTRL[i0].clear.value; // Field: pv_reg.PCR_CTRL[].rsvd0 always_comb begin - automatic logic [0:0] next_c = field_storage.PCR_CTRL[i0].rsvd0.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.PCR_CTRL[i0].rsvd0.value; + load_next_c = '0; if(decoded_reg_strb.PCR_CTRL[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.PCR_CTRL[i0].rsvd0.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -206,7 +210,7 @@ module pv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.PCR_CTRL[i0].rsvd0.value <= 'h0; + field_storage.PCR_CTRL[i0].rsvd0.value <= 1'h0; end else if(field_combo.PCR_CTRL[i0].rsvd0.load_next) begin field_storage.PCR_CTRL[i0].rsvd0.value <= field_combo.PCR_CTRL[i0].rsvd0.next; end @@ -214,8 +218,10 @@ module pv_reg ( assign hwif_out.PCR_CTRL[i0].rsvd0.value = field_storage.PCR_CTRL[i0].rsvd0.value; // Field: pv_reg.PCR_CTRL[].rsvd1 always_comb begin - automatic logic [4:0] next_c = field_storage.PCR_CTRL[i0].rsvd1.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.PCR_CTRL[i0].rsvd1.value; + load_next_c = '0; if(decoded_reg_strb.PCR_CTRL[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.PCR_CTRL[i0].rsvd1.value & ~decoded_wr_biten[7:3]) | (decoded_wr_data[7:3] & decoded_wr_biten[7:3]); load_next_c = '1; @@ -225,7 +231,7 @@ module pv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.PCR_CTRL[i0].rsvd1.value <= 'h0; + field_storage.PCR_CTRL[i0].rsvd1.value <= 5'h0; end else if(field_combo.PCR_CTRL[i0].rsvd1.load_next) begin field_storage.PCR_CTRL[i0].rsvd1.value <= field_combo.PCR_CTRL[i0].rsvd1.next; end @@ -236,8 +242,10 @@ module pv_reg ( for(genvar i1=0; i1<12; i1++) begin // Field: pv_reg.PCR_ENTRY[][].data always_comb begin - automatic logic [31:0] next_c = field_storage.PCR_ENTRY[i0][i1].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.PCR_ENTRY[i0][i1].data.value; + load_next_c = '0; if(hwif_in.PCR_ENTRY[i0][i1].data.we) begin // HW Write - we next_c = hwif_in.PCR_ENTRY[i0][i1].data.next; load_next_c = '1; @@ -250,7 +258,7 @@ module pv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.PCR_ENTRY[i0][i1].data.value <= 'h0; + field_storage.PCR_ENTRY[i0][i1].data.value <= 32'h0; end else if(field_combo.PCR_ENTRY[i0][i1].data.load_next) begin field_storage.PCR_ENTRY[i0][i1].data.value <= field_combo.PCR_ENTRY[i0][i1].data.next; end @@ -258,13 +266,22 @@ module pv_reg ( assign hwif_out.PCR_ENTRY[i0][i1].data.value = field_storage.PCR_ENTRY[i0][i1].data.value; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [416-1:0][31:0] readback_array; for(genvar i0=0; i0<32; i0++) begin @@ -296,4 +313,4 @@ module pv_reg ( `CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.hard_reset_b) -endmodule \ No newline at end of file +endmodule diff --git a/src/pcrvault/rtl/pv_reg_pkg.sv b/src/pcrvault/rtl/pv_reg_pkg.sv index e0201b175..9ce3d28e4 100644 --- a/src/pcrvault/rtl/pv_reg_pkg.sv +++ b/src/pcrvault/rtl/pv_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package pv_reg_pkg; + + localparam PV_REG_DATA_WIDTH = 32; + localparam PV_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic swwel; } pv_reg__pvCtrl__lock__in_t; diff --git a/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv b/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv index ef5753925..d7daec330 100644 --- a/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv +++ b/src/riscv_core/veer_el2/rtl/dbg/el2_dbg.sv @@ -327,7 +327,7 @@ import el2_pkg::*; assign sbaddress0_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h39); assign sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; assign sbaddress0_reg_din[31:0]= ({32{sbaddress0_reg_wren0}} & dmi_reg_wdata[31:0]) | - ({32{sbaddress0_reg_wren1}} & (sbaddress0_reg[31:0] + {28'b0,sbaddress0_incr[3:0]})); + ({32{sbaddress0_reg_wren1}} & (32'(sbaddress0_reg[31:0] + {28'b0,sbaddress0_incr[3:0]}))); rvdffe #(32) dbg_sbaddress0_reg (.*, .din(sbaddress0_reg_din[31:0]), .dout(sbaddress0_reg[31:0]), .en(sbaddress0_reg_wren), .rst_l(dbg_dm_rst_l)); assign sbreadonaddr_access = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h39) & sbcs_reg[20]; // if readonaddr is set the next command will start upon writing of addr0 diff --git a/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv b/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv index 255e320b0..9405ddde9 100644 --- a/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/dec/el2_dec_decode_ctl.sv @@ -740,7 +740,7 @@ end : cam_array // the classes must be mutually exclusive with one another always_comb begin - i0_itype = NULL; + i0_itype = NULL_OP; if (i0_legal_decode_d) begin if (i0_dp.mul) i0_itype = MUL; diff --git a/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv b/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv index 0e753606f..80523e5de 100644 --- a/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv @@ -2104,7 +2104,6 @@ else ({1{(mhpme_vec[i][9:0] == MHPME_INST_COMMIT_32B )}} & {tlu_i0_commit_cmt & exu_pmu_i0_pc4 & ~illegal_r}) | ({1{(mhpme_vec[i][9:0] == MHPME_INST_ALIGNED )}} & ifu_pmu_instr_aligned) | ({1{(mhpme_vec[i][9:0] == MHPME_INST_DECODED )}} & dec_pmu_instr_decoded) | - ({1{(mhpme_vec[i][9:0] == MHPME_DECODE_STALL )}} & {dec_pmu_decode_stall}) | ({1{(mhpme_vec[i][9:0] == MHPME_INST_MUL )}} & {(pmu_i0_itype_qual == MUL)}) | ({1{(mhpme_vec[i][9:0] == MHPME_INST_DIV )}} & {dec_tlu_packet_r.pmu_divide & tlu_i0_commit_cmt & ~illegal_r}) | ({1{(mhpme_vec[i][9:0] == MHPME_INST_LOAD )}} & {(pmu_i0_itype_qual == LOAD)}) | @@ -2716,7 +2715,7 @@ assign dec_tlu_presync_d = presync & dec_csr_any_unq_d & ~dec_csr_wen_unq_d; assign dec_tlu_postsync_d = postsync & dec_csr_any_unq_d; // allow individual configuration of these features -assign conditionally_illegal = ((csr_mitcnt0 | csr_mitcnt1 | csr_mitb0 | csr_mitb1 | csr_mitctl0 | csr_mitctl1) & !pt.TIMER_LEGAL_EN); +assign conditionally_illegal = ((csr_mitcnt0 | csr_mitcnt1 | csr_mitb0 | csr_mitb1 | csr_mitctl0 | csr_mitctl1) & ~|pt.TIMER_LEGAL_EN); assign valid_csr = ( legal & (~(csr_dcsr | csr_dpc | csr_dmst | csr_dicawics | csr_dicad0 | csr_dicad0h | csr_dicad1 | csr_dicago) | dbg_tlu_halted_f) & ~fast_int_meicpct & ~conditionally_illegal); diff --git a/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv b/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv index 1398a10bd..9e247035a 100644 --- a/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv +++ b/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv @@ -308,12 +308,13 @@ import el2_pkg::*; // Error logic assign dma_address_error = fifo_valid[RdPtr] & ~fifo_done[RdPtr] & ~fifo_dbg[RdPtr] & (~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm)); // request not for ICCM or DCCM assign dma_alignment_error = fifo_valid[RdPtr] & ~fifo_done[RdPtr] & ~fifo_dbg[RdPtr] & ~dma_address_error & - (((dma_mem_sz_int[2:0] == 3'h1) & dma_mem_addr_int[0]) | // HW size but unaligned - ((dma_mem_sz_int[2:0] == 3'h2) & (|dma_mem_addr_int[1:0])) | // W size but unaligned - ((dma_mem_sz_int[2:0] == 3'h3) & (|dma_mem_addr_int[2:0])) | // DW size but unaligned - (dma_mem_addr_in_iccm & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11))) | // ICCM access not word size - (dma_mem_addr_in_dccm & dma_mem_write & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11))) | // DCCM write not word size - (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h2) & (dma_mem_byteen[dma_mem_addr_int[2:0]+:4] != 4'hf)) | // Write byte enables not aligned for word store + (((dma_mem_sz_int[2:0] == 3'h1) & dma_mem_addr_int[0]) | // HW size but unaligned + ((dma_mem_sz_int[2:0] == 3'h2) & (|dma_mem_addr_int[1:0])) | // W size but unaligned + ((dma_mem_sz_int[2:0] == 3'h3) & (|dma_mem_addr_int[2:0])) | // DW size but unaligned + (dma_mem_addr_in_iccm & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11))) | // ICCM access not word size + (dma_mem_addr_in_dccm & dma_mem_write & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11))) | // DCCM write not word size + (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h2) & (dma_mem_addr_int[2:0] == 3'h0) & (dma_mem_byteen[3:0] != 4'hf)) | // Write byte enables not aligned for word store + (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h2) & (dma_mem_addr_int[2:0] == 3'h4) & (dma_mem_byteen[7:4] != 4'hf)) | // Write byte enables not aligned for word store (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h3) & ~((dma_mem_byteen[7:0] == 8'h0f) | (dma_mem_byteen[7:0] == 8'hf0) | (dma_mem_byteen[7:0] == 8'hff)))); // Write byte enables not aligned for dword store diff --git a/src/riscv_core/veer_el2/rtl/el2_mem.sv b/src/riscv_core/veer_el2/rtl/el2_mem.sv index 605b3120f..fa3fbf9da 100644 --- a/src/riscv_core/veer_el2/rtl/el2_mem.sv +++ b/src/riscv_core/veer_el2/rtl/el2_mem.sv @@ -128,6 +128,8 @@ else begin assign ic_tag_perr = '0 ; assign ic_rd_data = '0 ; assign ictag_debug_rd_data = '0 ; + assign ic_debug_rd_data = '0 ; + assign ic_eccerr = '0; end // else: !if( pt.ICACHE_ENABLE ) diff --git a/src/riscv_core/veer_el2/rtl/el2_pdef.vh b/src/riscv_core/veer_el2/rtl/el2_pdef.vh index 4cef1198a..b41d35c3d 100644 --- a/src/riscv_core/veer_el2/rtl/el2_pdef.vh +++ b/src/riscv_core/veer_el2/rtl/el2_pdef.vh @@ -17,177 +17,177 @@ typedef struct packed { - bit [7:0] BHT_ADDR_HI; - bit [5:0] BHT_ADDR_LO; - bit [14:0] BHT_ARRAY_DEPTH; - bit [4:0] BHT_GHR_HASH_1; - bit [7:0] BHT_GHR_SIZE; - bit [15:0] BHT_SIZE; - bit [4:0] BITMANIP_ZBA; - bit [4:0] BITMANIP_ZBB; - bit [4:0] BITMANIP_ZBC; - bit [4:0] BITMANIP_ZBE; - bit [4:0] BITMANIP_ZBF; - bit [4:0] BITMANIP_ZBP; - bit [4:0] BITMANIP_ZBR; - bit [4:0] BITMANIP_ZBS; - bit [8:0] BTB_ADDR_HI; - bit [5:0] BTB_ADDR_LO; - bit [12:0] BTB_ARRAY_DEPTH; - bit [4:0] BTB_BTAG_FOLD; - bit [8:0] BTB_BTAG_SIZE; - bit [4:0] BTB_ENABLE; - bit [4:0] BTB_FOLD2_INDEX_HASH; - bit [4:0] BTB_FULLYA; - bit [8:0] BTB_INDEX1_HI; - bit [8:0] BTB_INDEX1_LO; - bit [8:0] BTB_INDEX2_HI; - bit [8:0] BTB_INDEX2_LO; - bit [8:0] BTB_INDEX3_HI; - bit [8:0] BTB_INDEX3_LO; - bit [13:0] BTB_SIZE; - bit [8:0] BTB_TOFFSET_SIZE; - bit [4:0] BUILD_AHB_LITE; - bit BUILD_AXI4; - bit [4:0] BUILD_AXI_NATIVE; - bit [5:0] BUS_PRTY_DEFAULT; - bit [35:0] DATA_ACCESS_ADDR0; - bit [35:0] DATA_ACCESS_ADDR1; - bit [35:0] DATA_ACCESS_ADDR2; - bit [35:0] DATA_ACCESS_ADDR3; - bit [35:0] DATA_ACCESS_ADDR4; - bit [35:0] DATA_ACCESS_ADDR5; - bit [35:0] DATA_ACCESS_ADDR6; - bit [35:0] DATA_ACCESS_ADDR7; - bit [4:0] DATA_ACCESS_ENABLE0; - bit [4:0] DATA_ACCESS_ENABLE1; - bit [4:0] DATA_ACCESS_ENABLE2; - bit [4:0] DATA_ACCESS_ENABLE3; - bit [4:0] DATA_ACCESS_ENABLE4; - bit [4:0] DATA_ACCESS_ENABLE5; - bit [4:0] DATA_ACCESS_ENABLE6; - bit [4:0] DATA_ACCESS_ENABLE7; - bit [35:0] DATA_ACCESS_MASK0; - bit [35:0] DATA_ACCESS_MASK1; - bit [35:0] DATA_ACCESS_MASK2; - bit [35:0] DATA_ACCESS_MASK3; - bit [35:0] DATA_ACCESS_MASK4; - bit [35:0] DATA_ACCESS_MASK5; - bit [35:0] DATA_ACCESS_MASK6; - bit [35:0] DATA_ACCESS_MASK7; - bit [6:0] DCCM_BANK_BITS; - bit [8:0] DCCM_BITS; - bit [6:0] DCCM_BYTE_WIDTH; - bit [9:0] DCCM_DATA_WIDTH; - bit [6:0] DCCM_ECC_WIDTH; - bit [4:0] DCCM_ENABLE; - bit [9:0] DCCM_FDATA_WIDTH; - bit [7:0] DCCM_INDEX_BITS; - bit [8:0] DCCM_NUM_BANKS; - bit [7:0] DCCM_REGION; - bit [35:0] DCCM_SADR; - bit [13:0] DCCM_SIZE; - bit [5:0] DCCM_WIDTH_BITS; - bit [6:0] DIV_BIT; - bit [4:0] DIV_NEW; - bit [6:0] DMA_BUF_DEPTH; - bit [8:0] DMA_BUS_ID; - bit [5:0] DMA_BUS_PRTY; - bit [7:0] DMA_BUS_TAG; - bit [4:0] FAST_INTERRUPT_REDIRECT; - bit [4:0] ICACHE_2BANKS; - bit [6:0] ICACHE_BANK_BITS; - bit [6:0] ICACHE_BANK_HI; - bit [5:0] ICACHE_BANK_LO; - bit [7:0] ICACHE_BANK_WIDTH; - bit [6:0] ICACHE_BANKS_WAY; - bit [7:0] ICACHE_BEAT_ADDR_HI; - bit [7:0] ICACHE_BEAT_BITS; - bit [4:0] ICACHE_BYPASS_ENABLE; - bit [17:0] ICACHE_DATA_DEPTH; - bit [6:0] ICACHE_DATA_INDEX_LO; - bit [10:0] ICACHE_DATA_WIDTH; - bit [4:0] ICACHE_ECC; - bit [4:0] ICACHE_ENABLE; - bit [10:0] ICACHE_FDATA_WIDTH; - bit [8:0] ICACHE_INDEX_HI; - bit [10:0] ICACHE_LN_SZ; - bit [7:0] ICACHE_NUM_BEATS; - bit [7:0] ICACHE_NUM_BYPASS; - bit [7:0] ICACHE_NUM_BYPASS_WIDTH; - bit [6:0] ICACHE_NUM_WAYS; - bit [4:0] ICACHE_ONLY; - bit [7:0] ICACHE_SCND_LAST; - bit [12:0] ICACHE_SIZE; - bit [6:0] ICACHE_STATUS_BITS; - bit [4:0] ICACHE_TAG_BYPASS_ENABLE; - bit [16:0] ICACHE_TAG_DEPTH; - bit [6:0] ICACHE_TAG_INDEX_LO; - bit [8:0] ICACHE_TAG_LO; - bit [7:0] ICACHE_TAG_NUM_BYPASS; - bit [7:0] ICACHE_TAG_NUM_BYPASS_WIDTH; - bit [4:0] ICACHE_WAYPACK; - bit [6:0] ICCM_BANK_BITS; - bit [8:0] ICCM_BANK_HI; - bit [8:0] ICCM_BANK_INDEX_LO; - bit [8:0] ICCM_BITS; - bit [4:0] ICCM_ENABLE; - bit [4:0] ICCM_ICACHE; - bit [7:0] ICCM_INDEX_BITS; - bit [8:0] ICCM_NUM_BANKS; - bit [4:0] ICCM_ONLY; - bit [7:0] ICCM_REGION; - bit [35:0] ICCM_SADR; - bit [13:0] ICCM_SIZE; - bit [4:0] IFU_BUS_ID; - bit [5:0] IFU_BUS_PRTY; - bit [7:0] IFU_BUS_TAG; - bit [35:0] INST_ACCESS_ADDR0; - bit [35:0] INST_ACCESS_ADDR1; - bit [35:0] INST_ACCESS_ADDR2; - bit [35:0] INST_ACCESS_ADDR3; - bit [35:0] INST_ACCESS_ADDR4; - bit [35:0] INST_ACCESS_ADDR5; - bit [35:0] INST_ACCESS_ADDR6; - bit [35:0] INST_ACCESS_ADDR7; - bit [4:0] INST_ACCESS_ENABLE0; - bit [4:0] INST_ACCESS_ENABLE1; - bit [4:0] INST_ACCESS_ENABLE2; - bit [4:0] INST_ACCESS_ENABLE3; - bit [4:0] INST_ACCESS_ENABLE4; - bit [4:0] INST_ACCESS_ENABLE5; - bit [4:0] INST_ACCESS_ENABLE6; - bit [4:0] INST_ACCESS_ENABLE7; - bit [35:0] INST_ACCESS_MASK0; - bit [35:0] INST_ACCESS_MASK1; - bit [35:0] INST_ACCESS_MASK2; - bit [35:0] INST_ACCESS_MASK3; - bit [35:0] INST_ACCESS_MASK4; - bit [35:0] INST_ACCESS_MASK5; - bit [35:0] INST_ACCESS_MASK6; - bit [35:0] INST_ACCESS_MASK7; - bit [4:0] LOAD_TO_USE_PLUS1; - bit [4:0] LSU2DMA; - bit [4:0] LSU_BUS_ID; - bit [5:0] LSU_BUS_PRTY; - bit [7:0] LSU_BUS_TAG; - bit [8:0] LSU_NUM_NBLOAD; - bit [6:0] LSU_NUM_NBLOAD_WIDTH; - bit [8:0] LSU_SB_BITS; - bit [7:0] LSU_STBUF_DEPTH; - bit [4:0] NO_ICCM_NO_ICACHE; - bit [4:0] PIC_2CYCLE; - bit [35:0] PIC_BASE_ADDR; - bit [8:0] PIC_BITS; - bit [7:0] PIC_INT_WORDS; - bit [7:0] PIC_REGION; - bit [12:0] PIC_SIZE; - bit [11:0] PIC_TOTAL_INT; - bit [12:0] PIC_TOTAL_INT_PLUS1; - bit [7:0] RET_STACK_SIZE; - bit [4:0] SB_BUS_ID; - bit [5:0] SB_BUS_PRTY; - bit [7:0] SB_BUS_TAG; - bit [4:0] TIMER_LEGAL_EN; + logic [7:0] BHT_ADDR_HI; + logic [5:0] BHT_ADDR_LO; + logic [14:0] BHT_ARRAY_DEPTH; + logic [4:0] BHT_GHR_HASH_1; + logic [7:0] BHT_GHR_SIZE; + logic [15:0] BHT_SIZE; + logic [4:0] BITMANIP_ZBA; + logic [4:0] BITMANIP_ZBB; + logic [4:0] BITMANIP_ZBC; + logic [4:0] BITMANIP_ZBE; + logic [4:0] BITMANIP_ZBF; + logic [4:0] BITMANIP_ZBP; + logic [4:0] BITMANIP_ZBR; + logic [4:0] BITMANIP_ZBS; + logic [8:0] BTB_ADDR_HI; + logic [5:0] BTB_ADDR_LO; + logic [12:0] BTB_ARRAY_DEPTH; + logic [4:0] BTB_BTAG_FOLD; + logic [8:0] BTB_BTAG_SIZE; + logic [4:0] BTB_ENABLE; + logic [4:0] BTB_FOLD2_INDEX_HASH; + logic [4:0] BTB_FULLYA; + logic [8:0] BTB_INDEX1_HI; + logic [8:0] BTB_INDEX1_LO; + logic [8:0] BTB_INDEX2_HI; + logic [8:0] BTB_INDEX2_LO; + logic [8:0] BTB_INDEX3_HI; + logic [8:0] BTB_INDEX3_LO; + logic [13:0] BTB_SIZE; + logic [8:0] BTB_TOFFSET_SIZE; + logic [4:0] BUILD_AHB_LITE; + logic BUILD_AXI4; + logic [4:0] BUILD_AXI_NATIVE; + logic [5:0] BUS_PRTY_DEFAULT; + logic [35:0] DATA_ACCESS_ADDR0; + logic [35:0] DATA_ACCESS_ADDR1; + logic [35:0] DATA_ACCESS_ADDR2; + logic [35:0] DATA_ACCESS_ADDR3; + logic [35:0] DATA_ACCESS_ADDR4; + logic [35:0] DATA_ACCESS_ADDR5; + logic [35:0] DATA_ACCESS_ADDR6; + logic [35:0] DATA_ACCESS_ADDR7; + logic [4:0] DATA_ACCESS_ENABLE0; + logic [4:0] DATA_ACCESS_ENABLE1; + logic [4:0] DATA_ACCESS_ENABLE2; + logic [4:0] DATA_ACCESS_ENABLE3; + logic [4:0] DATA_ACCESS_ENABLE4; + logic [4:0] DATA_ACCESS_ENABLE5; + logic [4:0] DATA_ACCESS_ENABLE6; + logic [4:0] DATA_ACCESS_ENABLE7; + logic [35:0] DATA_ACCESS_MASK0; + logic [35:0] DATA_ACCESS_MASK1; + logic [35:0] DATA_ACCESS_MASK2; + logic [35:0] DATA_ACCESS_MASK3; + logic [35:0] DATA_ACCESS_MASK4; + logic [35:0] DATA_ACCESS_MASK5; + logic [35:0] DATA_ACCESS_MASK6; + logic [35:0] DATA_ACCESS_MASK7; + logic [6:0] DCCM_BANK_BITS; + logic [8:0] DCCM_BITS; + logic [6:0] DCCM_BYTE_WIDTH; + logic [9:0] DCCM_DATA_WIDTH; + logic [6:0] DCCM_ECC_WIDTH; + logic [4:0] DCCM_ENABLE; + logic [9:0] DCCM_FDATA_WIDTH; + logic [7:0] DCCM_INDEX_BITS; + logic [8:0] DCCM_NUM_BANKS; + logic [7:0] DCCM_REGION; + logic [35:0] DCCM_SADR; + logic [13:0] DCCM_SIZE; + logic [5:0] DCCM_WIDTH_BITS; + logic [6:0] DIV_BIT; + logic [4:0] DIV_NEW; + logic [6:0] DMA_BUF_DEPTH; + logic [8:0] DMA_BUS_ID; + logic [5:0] DMA_BUS_PRTY; + logic [7:0] DMA_BUS_TAG; + logic [4:0] FAST_INTERRUPT_REDIRECT; + logic [4:0] ICACHE_2BANKS; + logic [6:0] ICACHE_BANK_BITS; + logic [6:0] ICACHE_BANK_HI; + logic [5:0] ICACHE_BANK_LO; + logic [7:0] ICACHE_BANK_WIDTH; + logic [6:0] ICACHE_BANKS_WAY; + logic [7:0] ICACHE_BEAT_ADDR_HI; + logic [7:0] ICACHE_BEAT_BITS; + logic [4:0] ICACHE_BYPASS_ENABLE; + logic [17:0] ICACHE_DATA_DEPTH; + logic [6:0] ICACHE_DATA_INDEX_LO; + logic [10:0] ICACHE_DATA_WIDTH; + logic [4:0] ICACHE_ECC; + logic [4:0] ICACHE_ENABLE; + logic [10:0] ICACHE_FDATA_WIDTH; + logic [8:0] ICACHE_INDEX_HI; + logic [10:0] ICACHE_LN_SZ; + logic [7:0] ICACHE_NUM_BEATS; + logic [7:0] ICACHE_NUM_BYPASS; + logic [7:0] ICACHE_NUM_BYPASS_WIDTH; + logic [6:0] ICACHE_NUM_WAYS; + logic [4:0] ICACHE_ONLY; + logic [7:0] ICACHE_SCND_LAST; + logic [12:0] ICACHE_SIZE; + logic [6:0] ICACHE_STATUS_BITS; + logic [4:0] ICACHE_TAG_BYPASS_ENABLE; + logic [16:0] ICACHE_TAG_DEPTH; + logic [6:0] ICACHE_TAG_INDEX_LO; + logic [8:0] ICACHE_TAG_LO; + logic [7:0] ICACHE_TAG_NUM_BYPASS; + logic [7:0] ICACHE_TAG_NUM_BYPASS_WIDTH; + logic [4:0] ICACHE_WAYPACK; + logic [6:0] ICCM_BANK_BITS; + logic [8:0] ICCM_BANK_HI; + logic [8:0] ICCM_BANK_INDEX_LO; + logic [8:0] ICCM_BITS; + logic [4:0] ICCM_ENABLE; + logic [4:0] ICCM_ICACHE; + logic [7:0] ICCM_INDEX_BITS; + logic [8:0] ICCM_NUM_BANKS; + logic [4:0] ICCM_ONLY; + logic [7:0] ICCM_REGION; + logic [35:0] ICCM_SADR; + logic [13:0] ICCM_SIZE; + logic [4:0] IFU_BUS_ID; + logic [5:0] IFU_BUS_PRTY; + logic [7:0] IFU_BUS_TAG; + logic [35:0] INST_ACCESS_ADDR0; + logic [35:0] INST_ACCESS_ADDR1; + logic [35:0] INST_ACCESS_ADDR2; + logic [35:0] INST_ACCESS_ADDR3; + logic [35:0] INST_ACCESS_ADDR4; + logic [35:0] INST_ACCESS_ADDR5; + logic [35:0] INST_ACCESS_ADDR6; + logic [35:0] INST_ACCESS_ADDR7; + logic [4:0] INST_ACCESS_ENABLE0; + logic [4:0] INST_ACCESS_ENABLE1; + logic [4:0] INST_ACCESS_ENABLE2; + logic [4:0] INST_ACCESS_ENABLE3; + logic [4:0] INST_ACCESS_ENABLE4; + logic [4:0] INST_ACCESS_ENABLE5; + logic [4:0] INST_ACCESS_ENABLE6; + logic [4:0] INST_ACCESS_ENABLE7; + logic [35:0] INST_ACCESS_MASK0; + logic [35:0] INST_ACCESS_MASK1; + logic [35:0] INST_ACCESS_MASK2; + logic [35:0] INST_ACCESS_MASK3; + logic [35:0] INST_ACCESS_MASK4; + logic [35:0] INST_ACCESS_MASK5; + logic [35:0] INST_ACCESS_MASK6; + logic [35:0] INST_ACCESS_MASK7; + logic [4:0] LOAD_TO_USE_PLUS1; + logic [4:0] LSU2DMA; + logic [4:0] LSU_BUS_ID; + logic [5:0] LSU_BUS_PRTY; + logic [7:0] LSU_BUS_TAG; + logic [8:0] LSU_NUM_NBLOAD; + logic [6:0] LSU_NUM_NBLOAD_WIDTH; + logic [8:0] LSU_SB_BITS; + logic [7:0] LSU_STBUF_DEPTH; + logic [4:0] NO_ICCM_NO_ICACHE; + logic [4:0] PIC_2CYCLE; + logic [35:0] PIC_BASE_ADDR; + logic [8:0] PIC_BITS; + logic [7:0] PIC_INT_WORDS; + logic [7:0] PIC_REGION; + logic [12:0] PIC_SIZE; + logic [11:0] PIC_TOTAL_INT; + logic [12:0] PIC_TOTAL_INT_PLUS1; + logic [7:0] RET_STACK_SIZE; + logic [4:0] SB_BUS_ID; + logic [5:0] SB_BUS_PRTY; + logic [7:0] SB_BUS_TAG; + logic [4:0] TIMER_LEGAL_EN; } el2_param_t; diff --git a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv index 328aa20f1..3d18b690c 100755 --- a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv +++ b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv @@ -514,6 +514,7 @@ import soc_ifc_pkg::*; wire [2:0] lsu_axi_awprot; wire [3:0] lsu_axi_awqos; + wire lsu_axi_wvalid; wire lsu_axi_wready; wire [63:0] lsu_axi_wdata; @@ -546,6 +547,17 @@ import soc_ifc_pkg::*; wire [1:0] lsu_axi_rresp; wire lsu_axi_rlast; + assign lsu_axi_awready = '0; + assign lsu_axi_wready = '0; + assign lsu_axi_bvalid = '0; + assign lsu_axi_bresp = '0; + assign lsu_axi_bid = {pt.LSU_BUS_TAG{1'b0}}; + assign lsu_axi_arready = '0; + assign lsu_axi_rvalid = '0; + assign lsu_axi_rid = {pt.LSU_BUS_TAG{1'b0}}; + assign lsu_axi_rdata = '0; + assign lsu_axi_rresp = '0; + assign lsu_axi_rlast = '0; //-------------------------- IFU AXI signals-------------------------- // AXI Write Channels wire ifu_axi_awvalid; @@ -593,6 +605,15 @@ import soc_ifc_pkg::*; wire [1:0] ifu_axi_rresp; wire ifu_axi_rlast; + assign ifu_axi_bvalid = '0; + assign ifu_axi_bresp = '0; + assign ifu_axi_bid = {pt.IFU_BUS_TAG{1'b0}}; + assign ifu_axi_arready = '0; + assign ifu_axi_rvalid = '0; + assign ifu_axi_rid = {pt.IFU_BUS_TAG{1'b0}}; + assign ifu_axi_rdata = 0; + assign ifu_axi_rresp = '0; + assign ifu_axi_rlast = '0; //-------------------------- SB AXI signals-------------------------- // AXI Write Channels wire sb_axi_awvalid; @@ -640,6 +661,17 @@ import soc_ifc_pkg::*; wire [1:0] sb_axi_rresp; wire sb_axi_rlast; + assign sb_axi_awready = '0; + assign sb_axi_wready = '0; + assign sb_axi_bvalid = '0; + assign sb_axi_bresp = '0; + assign sb_axi_bid = {pt.SB_BUS_TAG{1'b0}}; + assign sb_axi_arready = '0; + assign sb_axi_rvalid = '0; + assign sb_axi_rid = {pt.SB_BUS_TAG{1'b0}}; + assign sb_axi_rdata = '0; + assign sb_axi_rresp = '0; + assign sb_axi_rlast = '0; //-------------------------- DMA AXI signals-------------------------- // AXI Write Channels wire dma_axi_awvalid; @@ -658,11 +690,27 @@ import soc_ifc_pkg::*; wire [7:0] dma_axi_wstrb; wire dma_axi_wlast; + assign dma_axi_awvalid = 1'b0; + assign dma_axi_awid = {pt.DMA_BUS_TAG{1'b0}}; + assign dma_axi_awaddr = 32'd0; + assign dma_axi_awsize = 3'd0; + assign dma_axi_awprot = 3'd0; + assign dma_axi_awlen = 8'd0; + assign dma_axi_awburst = 2'd0; + + + assign dma_axi_wvalid = 1'b0; + assign dma_axi_wdata = 64'd0; + assign dma_axi_wstrb = 8'd0; + assign dma_axi_wlast = 1'b0; + + wire dma_axi_bvalid; wire dma_axi_bready; wire [1:0] dma_axi_bresp; wire [pt.DMA_BUS_TAG-1:0] dma_axi_bid; + assign dma_axi_bready = 1'b0; // AXI Read Channels wire dma_axi_arvalid; wire dma_axi_arready; @@ -673,6 +721,16 @@ import soc_ifc_pkg::*; wire [7:0] dma_axi_arlen; wire [1:0] dma_axi_arburst; + assign dma_axi_arvalid = 1'b0; + assign dma_axi_arid = {pt.DMA_BUS_TAG{1'b0}}; + assign dma_axi_araddr = 32'd0; + assign dma_axi_arsize = 3'd0; + assign dma_axi_arprot = 3'd0; + assign dma_axi_arlen = 8'd0; + assign dma_axi_arburst = 2'd0; + + + wire dma_axi_rvalid; wire dma_axi_rready; wire [pt.DMA_BUS_TAG-1:0] dma_axi_rid; @@ -680,6 +738,7 @@ import soc_ifc_pkg::*; wire [1:0] dma_axi_rresp; wire dma_axi_rlast; + assign dma_axi_rready = 1'b0; // AXI assign ifu_axi_awready = 1'b1; assign ifu_axi_wready = 1'b1; diff --git a/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv b/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv index 00234ef6c..749077f3b 100644 --- a/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv @@ -302,7 +302,7 @@ import el2_pkg::*; ( {31{ap_ror}} & a_in[30:0] ); - assign shift_long[62:0] = ( shift_extend[62:0] >> shift_amount[4:0] ); // 62-32 unused + assign shift_long[62:0] = 63'( shift_extend[62:0] >> shift_amount[4:0] ); // 62-32 unused assign sout[31:0] = shift_long[31:0] & shift_mask[31:0]; diff --git a/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv b/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv index e47a7d827..48e00b37b 100644 --- a/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv @@ -523,22 +523,22 @@ import el2_pkg::*; logic [31:0] xperm_b; logic [31:0] xperm_h; - assign xperm_n[03:00] = { 4{ ~rs2_in[03] }} & ( (rs1_in[31:0] >> {rs2_in[02:00],2'b0}) & 4'hf ); // This is a 8:1 mux with qualified selects - assign xperm_n[07:04] = { 4{ ~rs2_in[07] }} & ( (rs1_in[31:0] >> {rs2_in[06:04],2'b0}) & 4'hf ); - assign xperm_n[11:08] = { 4{ ~rs2_in[11] }} & ( (rs1_in[31:0] >> {rs2_in[10:08],2'b0}) & 4'hf ); - assign xperm_n[15:12] = { 4{ ~rs2_in[15] }} & ( (rs1_in[31:0] >> {rs2_in[14:12],2'b0}) & 4'hf ); - assign xperm_n[19:16] = { 4{ ~rs2_in[19] }} & ( (rs1_in[31:0] >> {rs2_in[18:16],2'b0}) & 4'hf ); - assign xperm_n[23:20] = { 4{ ~rs2_in[23] }} & ( (rs1_in[31:0] >> {rs2_in[22:20],2'b0}) & 4'hf ); - assign xperm_n[27:24] = { 4{ ~rs2_in[27] }} & ( (rs1_in[31:0] >> {rs2_in[26:24],2'b0}) & 4'hf ); - assign xperm_n[31:28] = { 4{ ~rs2_in[31] }} & ( (rs1_in[31:0] >> {rs2_in[30:28],2'b0}) & 4'hf ); - - assign xperm_b[07:00] = { 8{ ~(| rs2_in[07:02]) }} & ( (rs1_in[31:0] >> {rs2_in[01:00],3'b0}) & 8'hff ); // This is a 4:1 mux with qualified selects - assign xperm_b[15:08] = { 8{ ~(| rs2_in[15:10]) }} & ( (rs1_in[31:0] >> {rs2_in[09:08],3'b0}) & 8'hff ); - assign xperm_b[23:16] = { 8{ ~(| rs2_in[23:18]) }} & ( (rs1_in[31:0] >> {rs2_in[17:16],3'b0}) & 8'hff ); - assign xperm_b[31:24] = { 8{ ~(| rs2_in[31:26]) }} & ( (rs1_in[31:0] >> {rs2_in[25:24],3'b0}) & 8'hff ); - - assign xperm_h[15:00] = {16{ ~(| rs2_in[15:01]) }} & ( (rs1_in[31:0] >> {rs2_in[00] ,4'b0}) & 16'hffff ); // This is a 2:1 mux with qualified selects - assign xperm_h[31:16] = {16{ ~(| rs2_in[31:17]) }} & ( (rs1_in[31:0] >> {rs2_in[16] ,4'b0}) & 16'hffff ); + assign xperm_n[03:00] = { 4{ ~rs2_in[03] }} & 4'( (rs1_in[31:0] >> {rs2_in[02:00],2'b0}) & 4'hf ); // This is a 8:1 mux with qualified selects + assign xperm_n[07:04] = { 4{ ~rs2_in[07] }} & 4'( (rs1_in[31:0] >> {rs2_in[06:04],2'b0}) & 4'hf ); + assign xperm_n[11:08] = { 4{ ~rs2_in[11] }} & 4'( (rs1_in[31:0] >> {rs2_in[10:08],2'b0}) & 4'hf ); + assign xperm_n[15:12] = { 4{ ~rs2_in[15] }} & 4'( (rs1_in[31:0] >> {rs2_in[14:12],2'b0}) & 4'hf ); + assign xperm_n[19:16] = { 4{ ~rs2_in[19] }} & 4'( (rs1_in[31:0] >> {rs2_in[18:16],2'b0}) & 4'hf ); + assign xperm_n[23:20] = { 4{ ~rs2_in[23] }} & 4'( (rs1_in[31:0] >> {rs2_in[22:20],2'b0}) & 4'hf ); + assign xperm_n[27:24] = { 4{ ~rs2_in[27] }} & 4'( (rs1_in[31:0] >> {rs2_in[26:24],2'b0}) & 4'hf ); + assign xperm_n[31:28] = { 4{ ~rs2_in[31] }} & 4'( (rs1_in[31:0] >> {rs2_in[30:28],2'b0}) & 4'hf ); + + assign xperm_b[07:00] = { 8{ ~(| rs2_in[07:02]) }} & 8'( (rs1_in[31:0] >> {rs2_in[01:00],3'b0}) & 8'hff ); // This is a 4:1 mux with qualified selects + assign xperm_b[15:08] = { 8{ ~(| rs2_in[15:10]) }} & 8'( (rs1_in[31:0] >> {rs2_in[09:08],3'b0}) & 8'hff ); + assign xperm_b[23:16] = { 8{ ~(| rs2_in[23:18]) }} & 8'( (rs1_in[31:0] >> {rs2_in[17:16],3'b0}) & 8'hff ); + assign xperm_b[31:24] = { 8{ ~(| rs2_in[31:26]) }} & 8'( (rs1_in[31:0] >> {rs2_in[25:24],3'b0}) & 8'hff ); + + assign xperm_h[15:00] = {16{ ~(| rs2_in[15:01]) }} & 16'( (rs1_in[31:0] >> {rs2_in[00] ,4'b0}) & 16'hffff ); // This is a 2:1 mux with qualified selects + assign xperm_h[31:16] = {16{ ~(| rs2_in[31:17]) }} & 16'( (rs1_in[31:0] >> {rs2_in[16] ,4'b0}) & 16'hffff ); diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv index 3e1639131..7a06e194a 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv @@ -835,8 +835,8 @@ end // block: fa for ( i=0; i<2; i++) begin : BANKS wire[pt.BHT_ARRAY_DEPTH-1:0] wr0, wr1; - assign wr0 = bht_wr_en0[i] << bht_wr_addr0; - assign wr1 = bht_wr_en2[i] << bht_wr_addr2; + assign wr0 = pt.BHT_ARRAY_DEPTH'(bht_wr_en0[i] << bht_wr_addr0); + assign wr1 = pt.BHT_ARRAY_DEPTH'(bht_wr_en2[i] << bht_wr_addr2); for (genvar k=0 ; k < (pt.BHT_ARRAY_DEPTH)/NUM_BHT_LOOP ; k++) begin : BHT_CLK_GROUP assign bht_bank_clken[i][k] = (bht_wr_en0[i] & ((bht_wr_addr0[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) | (bht_wr_en2[i] & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)); @@ -890,8 +890,8 @@ function [1:0] countones; begin -countones[1:0] = {2'b0, valid[1]} + - {2'b0, valid[0]}; +countones[1:0] = {1'b0, valid[1]} + + {1'b0, valid[0]}; end endfunction endmodule // el2_ifu_bp_ctl diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv index 3ab758e5d..5e2cbdd69 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_ifc_ctl.sv @@ -126,7 +126,7 @@ end // if (pt.BTB_ENABLE=1) ({31{sel_next_addr_bf}} & {fetch_addr_next[31:1]})); // SEQ path end - assign fetch_addr_next[31:1] = {({ifc_fetch_addr_f[31:2]} + 31'b1), fetch_addr_next_1 }; + assign fetch_addr_next[31:1] = {({ifc_fetch_addr_f[31:2]} + 30'b1), fetch_addr_next_1 }; assign line_wrap = (fetch_addr_next[pt.ICACHE_TAG_INDEX_LO] ^ ifc_fetch_addr_f[pt.ICACHE_TAG_INDEX_LO]); assign fetch_addr_next_1 = line_wrap ? 1'b0 : ifc_fetch_addr_f[1]; diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv index 99d537696..f6c7896af 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv @@ -851,7 +851,7 @@ assign two_byte_instr = (ic_data_f[1:0] != 2'b11 ) ; ((ic_miss_buff_data_valid_in[bypass_index[pt.ICACHE_BEAT_ADDR_HI:3]] & ~bypass_index[2] & bypass_index[1])) | ((ic_miss_buff_data_valid_in[bypass_index[pt.ICACHE_BEAT_ADDR_HI:3]] & bypass_index[2] & ~bypass_index[1])) | ((ic_miss_buff_data_valid_in[bypass_index[pt.ICACHE_BEAT_ADDR_HI:3]] & ic_miss_buff_data_valid_in[bypass_index_5_3_inc[pt.ICACHE_BEAT_ADDR_HI:3]] & bypass_index[2] & bypass_index[1])) | - ((ic_miss_buff_data_valid_in[bypass_index[pt.ICACHE_BEAT_ADDR_HI:3]] & (bypass_index[pt.ICACHE_BEAT_ADDR_HI:3] == {pt.ICACHE_BEAT_ADDR_HI{1'b1}}))) ; + ((ic_miss_buff_data_valid_in[bypass_index[pt.ICACHE_BEAT_ADDR_HI:3]] & (bypass_index[pt.ICACHE_BEAT_ADDR_HI:3] == {pt.ICACHE_BEAT_BITS{1'b1}}))) ; @@ -923,9 +923,6 @@ logic perr_sel_invalidate; logic perr_sb_write_status ; - - rvdffe #(.WIDTH(pt.ICACHE_INDEX_HI-pt.ICACHE_TAG_INDEX_LO+1),.OVERRIDE(1)) perr_dat_ff (.din(ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]), .dout(perr_ic_index_ff[pt.ICACHE_INDEX_HI : pt.ICACHE_TAG_INDEX_LO]), .en(perr_sb_write_status), .*); - assign perr_err_inv_way[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{perr_sel_invalidate}} ; assign iccm_correct_ecc = (perr_state == ECC_CORR); assign dma_sb_err_state = (perr_state == DMA_SB_ERR); @@ -1129,7 +1126,7 @@ logic perr_sb_write_status ; assign bus_reset_data_beat_cnt = ic_act_miss_f | (bus_ifu_wr_en_ff & bus_last_data_beat) | dec_tlu_force_halt; assign bus_hold_data_beat_cnt = ~bus_inc_data_beat_cnt & ~bus_reset_data_beat_cnt ; - assign bus_new_data_beat_count[pt.ICACHE_BEAT_BITS-1:0] = ({pt.ICACHE_BEAT_BITS{bus_reset_data_beat_cnt}} & (pt.ICACHE_BEAT_BITS)'(0)) | + assign bus_new_data_beat_count[pt.ICACHE_BEAT_BITS-1:0] = ({pt.ICACHE_BEAT_BITS{bus_reset_data_beat_cnt}} & (pt.ICACHE_BEAT_BITS)'(unsigned'(0))) | ({pt.ICACHE_BEAT_BITS{bus_inc_data_beat_cnt}} & (bus_data_beat_count[pt.ICACHE_BEAT_BITS-1:0] + {{pt.ICACHE_BEAT_BITS-1{1'b0}},1'b1})) | ({pt.ICACHE_BEAT_BITS{bus_hold_data_beat_cnt}} & bus_data_beat_count[pt.ICACHE_BEAT_BITS-1:0]); @@ -1155,7 +1152,7 @@ logic perr_sb_write_status ; assign bus_hold_cmd_beat_cnt = ~bus_inc_cmd_beat_cnt & ~(ic_act_miss_f | scnd_miss_req | dec_tlu_force_halt) ; assign bus_cmd_beat_en = bus_inc_cmd_beat_cnt | ic_act_miss_f | dec_tlu_force_halt; - assign bus_new_cmd_beat_count[pt.ICACHE_BEAT_BITS-1:0] = ({pt.ICACHE_BEAT_BITS{bus_reset_cmd_beat_cnt_0}} & (pt.ICACHE_BEAT_BITS)'(0) ) | + assign bus_new_cmd_beat_count[pt.ICACHE_BEAT_BITS-1:0] = ({pt.ICACHE_BEAT_BITS{bus_reset_cmd_beat_cnt_0}} & (pt.ICACHE_BEAT_BITS)'(unsigned'(0)) ) | ({pt.ICACHE_BEAT_BITS{bus_reset_cmd_beat_cnt_secondlast}} & (pt.ICACHE_BEAT_BITS)'(pt.ICACHE_SCND_LAST)) | ({pt.ICACHE_BEAT_BITS{bus_inc_cmd_beat_cnt}} & (bus_cmd_beat_count[pt.ICACHE_BEAT_BITS-1:0] + {{pt.ICACHE_BEAT_BITS-1{1'b0}}, 1'b1})) | ({pt.ICACHE_BEAT_BITS{bus_hold_cmd_beat_cnt}} & bus_cmd_beat_count[pt.ICACHE_BEAT_BITS-1:0]) ; @@ -1281,7 +1278,6 @@ ifc_dma_access_ok_prev,dma_iccm_req_f}) assign iccm_dma_rd_ecc_double_err = iccm_dma_rvalid && iccm_dma_ecc_error; - ///////////////////////////////////////////////////////////////////////////////////// // ECC checking logic for ICCM data. // ///////////////////////////////////////////////////////////////////////////////////// @@ -1408,6 +1404,8 @@ if (pt.ICACHE_ENABLE == 1 ) begin: icache_enabled assign way_status_new_w_debug[pt.ICACHE_STATUS_BITS-1:0] = (ic_debug_wr_en & ic_debug_tag_array) ? (pt.ICACHE_STATUS_BITS == 1) ? ic_debug_wr_data[4] : ic_debug_wr_data[6:4] : way_status_new[pt.ICACHE_STATUS_BITS-1:0] ; + rvdffe #(.WIDTH(pt.ICACHE_INDEX_HI-pt.ICACHE_TAG_INDEX_LO+1),.OVERRIDE(1)) perr_dat_ff (.din(ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]), .dout(perr_ic_index_ff[pt.ICACHE_INDEX_HI : pt.ICACHE_TAG_INDEX_LO]), .en(perr_sb_write_status), .*); + rvdffie #(.WIDTH(pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO+1+pt.ICACHE_STATUS_BITS),.OVERRIDE(1)) status_misc_ff (.*, .clk(free_l2clk), @@ -1584,6 +1582,7 @@ end else begin: icache_disabled assign way_status_new[pt.ICACHE_STATUS_BITS-1:0] = '0; assign way_status_wr_en = '0; assign bus_wren[pt.ICACHE_NUM_WAYS-1:0] = '0; + assign bus_ic_wr_en[pt.ICACHE_NUM_WAYS-1:0] = '0; end @@ -1629,10 +1628,8 @@ assign ic_debug_rd_en = dec_tlu_ic_diag_pkt.icache_rd_valid ; assign ic_debug_wr_en = dec_tlu_ic_diag_pkt.icache_wr_valid ; -assign ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] = {(ic_debug_way_enc[1:0] == 2'b11), - (ic_debug_way_enc[1:0] == 2'b10), - (ic_debug_way_enc[1:0] == 2'b01), - (ic_debug_way_enc[1:0] == 2'b00) }; +assign ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] = {(ic_debug_way_enc[0] == 1'b1), + (ic_debug_way_enc[0] == 1'b0) }; assign ic_debug_tag_wr_en[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{ic_debug_wr_en & ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ; @@ -1653,18 +1650,36 @@ rvdff_fpga #(01+pt.ICACHE_NUM_WAYS) ifu_debug_sel_ff (.*, .clk (debug_c1_clk), assign debug_data_clken = ic_debug_rd_en_ff; +logic ACCESS0_okay; +logic ACCESS1_okay; +logic ACCESS2_okay; +logic ACCESS3_okay; +logic ACCESS4_okay; +logic ACCESS5_okay; +logic ACCESS6_okay; +logic ACCESS7_okay; + +assign ACCESS0_okay = pt.INST_ACCESS_ENABLE0 & ((({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK0)) == (pt.INST_ACCESS_ADDR0 | pt.INST_ACCESS_MASK0)); +assign ACCESS1_okay = pt.INST_ACCESS_ENABLE1 & ((({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK1)) == (pt.INST_ACCESS_ADDR1 | pt.INST_ACCESS_MASK1)); +assign ACCESS2_okay = pt.INST_ACCESS_ENABLE2 & ((({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK2)) == (pt.INST_ACCESS_ADDR2 | pt.INST_ACCESS_MASK2)); +assign ACCESS3_okay = pt.INST_ACCESS_ENABLE3 & ((({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK3)) == (pt.INST_ACCESS_ADDR3 | pt.INST_ACCESS_MASK3)); +assign ACCESS4_okay = pt.INST_ACCESS_ENABLE4 & ((({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK4)) == (pt.INST_ACCESS_ADDR4 | pt.INST_ACCESS_MASK4)); +assign ACCESS5_okay = pt.INST_ACCESS_ENABLE5 & ((({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK5)) == (pt.INST_ACCESS_ADDR5 | pt.INST_ACCESS_MASK5)); +assign ACCESS6_okay = pt.INST_ACCESS_ENABLE6 & ((({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK6)) == (pt.INST_ACCESS_ADDR6 | pt.INST_ACCESS_MASK6)); +assign ACCESS7_okay = pt.INST_ACCESS_ENABLE7 & ((({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK7)) == (pt.INST_ACCESS_ADDR7 | pt.INST_ACCESS_MASK7)); // memory protection - equation to look identical to the LSU equation - assign ifc_region_acc_okay = (~(|{pt.INST_ACCESS_ENABLE0,pt.INST_ACCESS_ENABLE1,pt.INST_ACCESS_ENABLE2,pt.INST_ACCESS_ENABLE3,pt.INST_ACCESS_ENABLE4,pt.INST_ACCESS_ENABLE5,pt.INST_ACCESS_ENABLE6,pt.INST_ACCESS_ENABLE7})) | - (pt.INST_ACCESS_ENABLE0 & (({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK0)) == (pt.INST_ACCESS_ADDR0 | pt.INST_ACCESS_MASK0)) | - (pt.INST_ACCESS_ENABLE1 & (({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK1)) == (pt.INST_ACCESS_ADDR1 | pt.INST_ACCESS_MASK1)) | - (pt.INST_ACCESS_ENABLE2 & (({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK2)) == (pt.INST_ACCESS_ADDR2 | pt.INST_ACCESS_MASK2)) | - (pt.INST_ACCESS_ENABLE3 & (({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK3)) == (pt.INST_ACCESS_ADDR3 | pt.INST_ACCESS_MASK3)) | - (pt.INST_ACCESS_ENABLE4 & (({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK4)) == (pt.INST_ACCESS_ADDR4 | pt.INST_ACCESS_MASK4)) | - (pt.INST_ACCESS_ENABLE5 & (({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK5)) == (pt.INST_ACCESS_ADDR5 | pt.INST_ACCESS_MASK5)) | - (pt.INST_ACCESS_ENABLE6 & (({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK6)) == (pt.INST_ACCESS_ADDR6 | pt.INST_ACCESS_MASK6)) | - (pt.INST_ACCESS_ENABLE7 & (({ifc_fetch_addr_bf[31:1],1'b0} | pt.INST_ACCESS_MASK7)) == (pt.INST_ACCESS_ADDR7 | pt.INST_ACCESS_MASK7)); + assign ifc_region_acc_okay = (~(|{pt.INST_ACCESS_ENABLE0,pt.INST_ACCESS_ENABLE1,pt.INST_ACCESS_ENABLE2,pt.INST_ACCESS_ENABLE3,pt.INST_ACCESS_ENABLE4,pt.INST_ACCESS_ENABLE5,pt.INST_ACCESS_ENABLE6,pt.INST_ACCESS_ENABLE7})) + | ACCESS0_okay + | ACCESS1_okay + | ACCESS2_okay + | ACCESS3_okay + | ACCESS4_okay + | ACCESS5_okay + | ACCESS6_okay + | ACCESS7_okay + ; assign ifc_region_acc_fault_memory_bf = ~ifc_iccm_access_bf & ~ifc_region_acc_okay & ifc_fetch_req_bf; diff --git a/src/riscv_core/veer_el2/rtl/include/el2_def.sv b/src/riscv_core/veer_el2/rtl/include/el2_def.sv index a1b239b57..5c5cc2b81 100644 --- a/src/riscv_core/veer_el2/rtl/include/el2_def.sv +++ b/src/riscv_core/veer_el2/rtl/include/el2_def.sv @@ -35,7 +35,7 @@ typedef struct packed { typedef enum logic [3:0] { - NULL = 4'b0000, + NULL_OP = 4'b0000, MUL = 4'b0001, LOAD = 4'b0010, STORE = 4'b0011, diff --git a/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv b/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv index 672f0b18e..45be48c35 100644 --- a/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv +++ b/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv @@ -209,7 +209,7 @@ import el2_pkg::*; logic [2:0] start_ptr; logic found; found = '0; - //get_nxtbyte_ptr[2:0] = current_byte_ptr[2:0]; + get_nxtbyte_ptr[2:0] = 3'd0; start_ptr[2:0] = get_next ? (current_byte_ptr[2:0] + 3'b1) : current_byte_ptr[2:0]; for (int j=0; j<8; j++) begin if (~found) begin diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv index 40410c100..5b238fd37 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv @@ -297,7 +297,7 @@ import el2_pkg::*; assign dma_dccm_wen = dma_dccm_req & dma_mem_write & addr_in_dccm_d & dma_mem_sz[1]; // Perform DMA writes only for word/dword assign dma_pic_wen = dma_dccm_req & dma_mem_write & addr_in_pic_d; - assign {dma_dccm_wdata_hi[31:0], dma_dccm_wdata_lo[31:0]} = dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}; // Shift the dma data to lower bits to make it consistent to lsu stores + assign {dma_dccm_wdata_hi[31:0], dma_dccm_wdata_lo[31:0]} = 64'(dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}); // Shift the dma data to lower bits to make it consistent to lsu stores // Generate per cycle flush signals diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv index 2abe8e183..711de464d 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv @@ -116,7 +116,7 @@ import el2_pkg::*; ); assign start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d; - assign base_reg_dccm_or_pic = ((rs1_region_d[3:0] == pt.DCCM_REGION) & pt.DCCM_ENABLE) | (rs1_region_d[3:0] == pt.PIC_REGION); + assign base_reg_dccm_or_pic = (|((rs1_region_d[3:0] == pt.DCCM_REGION) & pt.DCCM_ENABLE)) | (rs1_region_d[3:0] == pt.PIC_REGION); assign addr_in_dccm_d = (start_addr_in_dccm_d & end_addr_in_dccm_d); assign addr_in_pic_d = (start_addr_in_pic_d & end_addr_in_pic_d); @@ -127,23 +127,57 @@ import el2_pkg::*; (lsu_pkt_d.half & (start_addr_d[0] == 1'b0)) | lsu_pkt_d.by; + logic ACCESS0_STARTOK; + logic ACCESS1_STARTOK; + logic ACCESS2_STARTOK; + logic ACCESS3_STARTOK; + logic ACCESS4_STARTOK; + logic ACCESS5_STARTOK; + logic ACCESS6_STARTOK; + logic ACCESS7_STARTOK; + logic ACCESS0_ENDOK; + logic ACCESS1_ENDOK; + logic ACCESS2_ENDOK; + logic ACCESS3_ENDOK; + logic ACCESS4_ENDOK; + logic ACCESS5_ENDOK; + logic ACCESS6_ENDOK; + logic ACCESS7_ENDOK; + + assign ACCESS0_STARTOK = pt.DATA_ACCESS_ENABLE0 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK0)) == (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0); + assign ACCESS1_STARTOK = pt.DATA_ACCESS_ENABLE1 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK1)) == (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1); + assign ACCESS2_STARTOK = pt.DATA_ACCESS_ENABLE2 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK2)) == (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2); + assign ACCESS3_STARTOK = pt.DATA_ACCESS_ENABLE3 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK3)) == (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3); + assign ACCESS4_STARTOK = pt.DATA_ACCESS_ENABLE4 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK4)) == (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4); + assign ACCESS5_STARTOK = pt.DATA_ACCESS_ENABLE5 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK5)) == (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5); + assign ACCESS6_STARTOK = pt.DATA_ACCESS_ENABLE6 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK6)) == (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6); + assign ACCESS7_STARTOK = pt.DATA_ACCESS_ENABLE7 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK7)) == (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7); + assign ACCESS0_ENDOK = pt.DATA_ACCESS_ENABLE0 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK0)) == (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0); + assign ACCESS1_ENDOK = pt.DATA_ACCESS_ENABLE1 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK1)) == (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1); + assign ACCESS2_ENDOK = pt.DATA_ACCESS_ENABLE2 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK2)) == (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2); + assign ACCESS3_ENDOK = pt.DATA_ACCESS_ENABLE3 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK3)) == (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3); + assign ACCESS4_ENDOK = pt.DATA_ACCESS_ENABLE4 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK4)) == (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4); + assign ACCESS5_ENDOK = pt.DATA_ACCESS_ENABLE5 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK5)) == (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5); + assign ACCESS6_ENDOK = pt.DATA_ACCESS_ENABLE6 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK6)) == (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6); + assign ACCESS7_ENDOK = pt.DATA_ACCESS_ENABLE7 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK7)) == (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7); + assign non_dccm_access_ok = (~(|{pt.DATA_ACCESS_ENABLE0,pt.DATA_ACCESS_ENABLE1,pt.DATA_ACCESS_ENABLE2,pt.DATA_ACCESS_ENABLE3,pt.DATA_ACCESS_ENABLE4,pt.DATA_ACCESS_ENABLE5,pt.DATA_ACCESS_ENABLE6,pt.DATA_ACCESS_ENABLE7})) | - (((pt.DATA_ACCESS_ENABLE0 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK0)) == (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0)) | - (pt.DATA_ACCESS_ENABLE1 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK1)) == (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1)) | - (pt.DATA_ACCESS_ENABLE2 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK2)) == (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2)) | - (pt.DATA_ACCESS_ENABLE3 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK3)) == (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3)) | - (pt.DATA_ACCESS_ENABLE4 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK4)) == (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4)) | - (pt.DATA_ACCESS_ENABLE5 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK5)) == (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5)) | - (pt.DATA_ACCESS_ENABLE6 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK6)) == (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6)) | - (pt.DATA_ACCESS_ENABLE7 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK7)) == (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7))) & - ((pt.DATA_ACCESS_ENABLE0 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK0)) == (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0)) | - (pt.DATA_ACCESS_ENABLE1 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK1)) == (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1)) | - (pt.DATA_ACCESS_ENABLE2 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK2)) == (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2)) | - (pt.DATA_ACCESS_ENABLE3 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK3)) == (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3)) | - (pt.DATA_ACCESS_ENABLE4 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK4)) == (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4)) | - (pt.DATA_ACCESS_ENABLE5 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK5)) == (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5)) | - (pt.DATA_ACCESS_ENABLE6 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK6)) == (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6)) | - (pt.DATA_ACCESS_ENABLE7 & ((end_addr_d[31:0] | pt.DATA_ACCESS_MASK7)) == (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7)))); + (( ACCESS0_STARTOK| + ACCESS1_STARTOK| + ACCESS2_STARTOK| + ACCESS3_STARTOK| + ACCESS4_STARTOK| + ACCESS5_STARTOK| + ACCESS6_STARTOK| + ACCESS7_STARTOK) & + ( ACCESS0_ENDOK| + ACCESS1_ENDOK| + ACCESS2_ENDOK| + ACCESS3_ENDOK| + ACCESS4_ENDOK| + ACCESS5_ENDOK| + ACCESS6_ENDOK| + ACCESS7_ENDOK)); // Access fault logic // 0. Unmapped local memory : Addr in dccm region but not in dccm offset OR Addr in picm region but not in picm offset OR DCCM -> PIC cross when DCCM/PIC in same region diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv index 8e852788b..7afa9afb3 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv @@ -150,9 +150,9 @@ import el2_pkg::*; ); - // For Ld: IDLE -> WAIT -> CMD -> RESP -> DONE_PARTIAL(?) -> DONE_WAIT(?) -> DONE -> IDLE - // For St: IDLE -> WAIT -> CMD -> RESP(?) -> IDLE - typedef enum logic [2:0] {IDLE=3'b000, WAIT=3'b001, CMD=3'b010, RESP=3'b011, DONE_PARTIAL=3'b100, DONE_WAIT=3'b101, DONE=3'b110} state_t; + // For Ld: IDLE -> START_WAIT -> CMD -> RESP -> DONE_PARTIAL(?) -> DONE_WAIT(?) -> DONE -> IDLE + // For St: IDLE -> START_WAIT -> CMD -> RESP(?) -> IDLE + typedef enum logic [2:0] {IDLE=3'b000, START_WAIT=3'b001, CMD=3'b010, RESP=3'b011, DONE_PARTIAL=3'b100, DONE_WAIT=3'b101, DONE=3'b110} state_t; localparam DEPTH = pt.LSU_NUM_NBLOAD; localparam DEPTH_LOG2 = pt.LSU_NUM_NBLOAD_WIDTH; @@ -595,7 +595,7 @@ import el2_pkg::*; for (genvar i=0; i> (8*lsu_addr_m[1:0]); + assign ld_fwddata_m[63:0] = 64'({ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_m[1:0])); assign bus_read_data_m[31:0] = ld_fwddata_m[31:0]; // Fifo flops diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv index 31ea65164..be9575c33 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv @@ -232,8 +232,8 @@ import el2_pkg::*; assign dccm_dma_ecc_error = lsu_double_ecc_error_m; assign dccm_dma_rtag[2:0] = dma_mem_tag_m[2:0]; assign dccm_dma_rdata[63:0] = ldst_dual_m ? lsu_rdata_corr_m[63:0] : {2{lsu_rdata_corr_m[31:0]}}; - assign {lsu_ld_data_m_nc[63:32], lsu_ld_data_m[31:0]} = lsu_rdata_m[63:0] >> 8*lsu_addr_m[1:0]; - assign {lsu_ld_data_corr_m_nc[63:32], lsu_ld_data_corr_m[31:0]} = lsu_rdata_corr_m[63:0] >> 8*lsu_addr_m[1:0]; + assign {lsu_ld_data_m_nc[63:32], lsu_ld_data_m[31:0]} = 64'(lsu_rdata_m[63:0] >> 8*lsu_addr_m[1:0]); + assign {lsu_ld_data_corr_m_nc[63:32], lsu_ld_data_corr_m[31:0]} = 64'(lsu_rdata_corr_m[63:0] >> 8*lsu_addr_m[1:0]); assign dccm_rdata_m[63:0] = {dccm_rdata_hi_m[31:0],dccm_rdata_lo_m[31:0]}; assign dccm_rdata_corr_m[63:0] = {sec_data_hi_m[31:0],sec_data_lo_m[31:0]}; diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv index 9378bba5c..374e28e55 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_mem.sv @@ -56,9 +56,9 @@ import el2_pkg::*; ); - localparam DCCM_WIDTH_BITS = $clog2(pt.DCCM_BYTE_WIDTH); - localparam DCCM_INDEX_BITS = (pt.DCCM_BITS - pt.DCCM_BANK_BITS - pt.DCCM_WIDTH_BITS); - localparam DCCM_INDEX_DEPTH = ((pt.DCCM_SIZE)*1024)/((pt.DCCM_BYTE_WIDTH)*(pt.DCCM_NUM_BANKS)); // Depth of memory bank + localparam logic [5:0] DCCM_WIDTH_BITS = $clog2(pt.DCCM_BYTE_WIDTH); + localparam logic [7:0] DCCM_INDEX_BITS = 8'(pt.DCCM_BITS - pt.DCCM_BANK_BITS - pt.DCCM_WIDTH_BITS); + localparam logic [31:0] DCCM_INDEX_DEPTH = ((pt.DCCM_SIZE)*1024)/((pt.DCCM_BYTE_WIDTH)*(pt.DCCM_NUM_BANKS)); // Depth of memory bank logic [pt.DCCM_NUM_BANKS-1:0] wren_bank; logic [pt.DCCM_NUM_BANKS-1:0] rden_bank; diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv index d9aeb1fb1..80bf8fb6e 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv @@ -298,7 +298,7 @@ import el2_pkg::*; // Interrupt as a flush source allows the WB to occur assign lsu_commit_r = lsu_pkt_r.valid & (lsu_pkt_r.store | lsu_pkt_r.load) & ~flush_r & ~lsu_pkt_r.dma; - assign dma_mem_wdata_shifted[63:0] = dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}; // Shift the dma data to lower bits to make it consistent to lsu stores + assign dma_mem_wdata_shifted[63:0] = 64'(dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}); // Shift the dma data to lower bits to make it consistent to lsu stores assign store_data_d[31:0] = dma_dccm_req ? dma_mem_wdata_shifted[31:0] : exu_lsu_rs2_d[31:0]; // Write to PIC still happens in r stage assign store_data_m_in[31:0] = (lsu_pkt_d.store_data_bypass_d) ? lsu_result_m[31:0] : store_data_d[31:0]; diff --git a/src/sha256/config/compile.yml b/src/sha256/config/compile.yml index 15af97656..87f0de17c 100755 --- a/src/sha256/config/compile.yml +++ b/src/sha256/config/compile.yml @@ -21,8 +21,6 @@ targets: waiver_files: #- $COMPILE_ROOT/config/rtl_lint/sha256.waiver - $MSFT_REPO_ROOT/src/sha256/config/design_lint/sha256_ctrl/sglint_waivers - black_box: - - sha256_reg --- provides: [sha256_ctrl_tb] schema_version: 2.4.0 diff --git a/src/sha256/rtl/sha256.sv b/src/sha256/rtl/sha256.sv index bacea4695..0c65f05e6 100644 --- a/src/sha256/rtl/sha256.sv +++ b/src/sha256/rtl/sha256.sv @@ -199,10 +199,10 @@ module sha256 always_comb begin unique case(wntz_w) - 8'h1: wntz_iter = 'd0; //2**w - 1 (-1) (1st iteration is considered separately) - 8'h2: wntz_iter = 'd2; - 8'h4: wntz_iter = 'd14; - 8'h8: wntz_iter = 'd254; + 4'h1: wntz_iter = 'd0; //2**w - 1 (-1) (1st iteration is considered separately) + 4'h2: wntz_iter = 'd2; + 4'h4: wntz_iter = 'd14; + 4'h8: wntz_iter = 'd254; default: wntz_iter = 'd0; endcase end @@ -339,11 +339,13 @@ module sha256 ready_flag_reg <= '0; digest_reg <= '0; valid_flag_reg <= '0; + core_digest_valid_reg <= '0; end else if (zeroize_reg) begin ready_flag_reg <= '0; digest_reg <= '0; valid_flag_reg <= '0; + core_digest_valid_reg <= '0; end else begin ready_flag_reg <= ready_flag; diff --git a/src/sha256/rtl/sha256_ctrl.sv b/src/sha256/rtl/sha256_ctrl.sv index 1932b70d2..970770f42 100644 --- a/src/sha256/rtl/sha256_ctrl.sv +++ b/src/sha256/rtl/sha256_ctrl.sv @@ -53,12 +53,12 @@ module sha256_ctrl #( //---------------------------------------------------------------- // sha256 //---------------------------------------------------------------- - reg sha256_cs; - reg sha256_we; - reg [AHB_ADDR_WIDTH-1 : 0] sha256_address; - reg [31 : 0] sha256_write_data; - reg [31 : 0] sha256_read_data; - reg sha256_err; + logic sha256_cs; + logic sha256_we; + logic [AHB_ADDR_WIDTH-1 : 0] sha256_address; + logic [31 : 0] sha256_write_data; + logic [31 : 0] sha256_read_data; + logic sha256_err; sha256 #( .ADDR_WIDTH(AHB_ADDR_WIDTH), diff --git a/src/sha256/rtl/sha256_reg.sv b/src/sha256/rtl/sha256_reg.sv index bda350c79..87b7451c8 100644 --- a/src/sha256/rtl/sha256_reg.sv +++ b/src/sha256/rtl/sha256_reg.sv @@ -533,8 +533,10 @@ module sha256_reg ( // Field: sha256_reg.SHA256_CTRL.INIT always_comb begin - automatic logic [0:0] next_c = field_storage.SHA256_CTRL.INIT.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_CTRL.INIT.value; + load_next_c = '0; if(decoded_reg_strb.SHA256_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA256_CTRL.INIT.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -555,8 +557,10 @@ module sha256_reg ( assign hwif_out.SHA256_CTRL.INIT.value = field_storage.SHA256_CTRL.INIT.value; // Field: sha256_reg.SHA256_CTRL.NEXT always_comb begin - automatic logic [0:0] next_c = field_storage.SHA256_CTRL.NEXT.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_CTRL.NEXT.value; + load_next_c = '0; if(decoded_reg_strb.SHA256_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA256_CTRL.NEXT.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -577,8 +581,10 @@ module sha256_reg ( assign hwif_out.SHA256_CTRL.NEXT.value = field_storage.SHA256_CTRL.NEXT.value; // Field: sha256_reg.SHA256_CTRL.MODE always_comb begin - automatic logic [0:0] next_c = field_storage.SHA256_CTRL.MODE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_CTRL.MODE.value; + load_next_c = '0; if(decoded_reg_strb.SHA256_CTRL && decoded_req_is_wr && hwif_in.sha256_ready) begin // SW write next_c = (field_storage.SHA256_CTRL.MODE.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -596,8 +602,10 @@ module sha256_reg ( assign hwif_out.SHA256_CTRL.MODE.value = field_storage.SHA256_CTRL.MODE.value; // Field: sha256_reg.SHA256_CTRL.ZEROIZE always_comb begin - automatic logic [0:0] next_c = field_storage.SHA256_CTRL.ZEROIZE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_CTRL.ZEROIZE.value; + load_next_c = '0; if(decoded_reg_strb.SHA256_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA256_CTRL.ZEROIZE.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -618,8 +626,10 @@ module sha256_reg ( assign hwif_out.SHA256_CTRL.ZEROIZE.value = field_storage.SHA256_CTRL.ZEROIZE.value; // Field: sha256_reg.SHA256_CTRL.WNTZ_MODE always_comb begin - automatic logic [0:0] next_c = field_storage.SHA256_CTRL.WNTZ_MODE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_CTRL.WNTZ_MODE.value; + load_next_c = '0; if(decoded_reg_strb.SHA256_CTRL && decoded_req_is_wr && hwif_in.sha256_ready) begin // SW write next_c = (field_storage.SHA256_CTRL.WNTZ_MODE.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); load_next_c = '1; @@ -640,8 +650,10 @@ module sha256_reg ( assign hwif_out.SHA256_CTRL.WNTZ_MODE.value = field_storage.SHA256_CTRL.WNTZ_MODE.value; // Field: sha256_reg.SHA256_CTRL.WNTZ_W always_comb begin - automatic logic [3:0] next_c = field_storage.SHA256_CTRL.WNTZ_W.value; - automatic logic load_next_c = '0; + automatic logic [3:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_CTRL.WNTZ_W.value; + load_next_c = '0; if(decoded_reg_strb.SHA256_CTRL && decoded_req_is_wr && hwif_in.sha256_ready) begin // SW write next_c = (field_storage.SHA256_CTRL.WNTZ_W.value & ~decoded_wr_biten[8:5]) | (decoded_wr_data[8:5] & decoded_wr_biten[8:5]); load_next_c = '1; @@ -659,8 +671,10 @@ module sha256_reg ( assign hwif_out.SHA256_CTRL.WNTZ_W.value = field_storage.SHA256_CTRL.WNTZ_W.value; // Field: sha256_reg.SHA256_CTRL.WNTZ_N_MODE always_comb begin - automatic logic [0:0] next_c = field_storage.SHA256_CTRL.WNTZ_N_MODE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_CTRL.WNTZ_N_MODE.value; + load_next_c = '0; if(decoded_reg_strb.SHA256_CTRL && decoded_req_is_wr && hwif_in.sha256_ready) begin // SW write next_c = (field_storage.SHA256_CTRL.WNTZ_N_MODE.value & ~decoded_wr_biten[9:9]) | (decoded_wr_data[9:9] & decoded_wr_biten[9:9]); load_next_c = '1; @@ -679,8 +693,10 @@ module sha256_reg ( for(genvar i0=0; i0<16; i0++) begin // Field: sha256_reg.SHA256_BLOCK[].BLOCK always_comb begin - automatic logic [31:0] next_c = field_storage.SHA256_BLOCK[i0].BLOCK.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_BLOCK[i0].BLOCK.value; + load_next_c = '0; if(decoded_reg_strb.SHA256_BLOCK[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA256_BLOCK[i0].BLOCK.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -703,8 +719,10 @@ module sha256_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: sha256_reg.SHA256_DIGEST[].DIGEST always_comb begin - automatic logic [31:0] next_c = field_storage.SHA256_DIGEST[i0].DIGEST.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_DIGEST[i0].DIGEST.value; + load_next_c = '0; if(hwif_in.SHA256_DIGEST[i0].DIGEST.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; @@ -725,8 +743,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -743,8 +763,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -761,8 +783,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error_intr_en_r.error0_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error0_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -779,8 +803,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error_intr_en_r.error1_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error1_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -797,8 +823,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error_intr_en_r.error2_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error2_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -815,8 +843,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error_intr_en_r.error3_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error3_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -833,8 +863,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.notif_intr_en_r.notif_cmd_done_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -851,8 +883,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; // HW Write next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; @@ -871,8 +905,10 @@ module sha256_reg ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: sha256_reg.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; // HW Write next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; @@ -891,8 +927,10 @@ module sha256_reg ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: sha256_reg.intr_block_rf.error_internal_intr_r.error0_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; @@ -915,8 +953,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error_internal_intr_r.error1_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; @@ -939,8 +979,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error_internal_intr_r.error2_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; @@ -963,8 +1005,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error_internal_intr_r.error3_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; @@ -992,8 +1036,10 @@ module sha256_reg ( || |(field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value & field_storage.intr_block_rf.error_intr_en_r.error3_en.value); // Field: sha256_reg.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; @@ -1018,8 +1064,10 @@ module sha256_reg ( |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value); // Field: sha256_reg.intr_block_rf.error_intr_trig_r.error0_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1039,8 +1087,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error_intr_trig_r.error1_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -1060,8 +1110,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error_intr_trig_r.error2_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -1081,8 +1133,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error_intr_trig_r.error3_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -1102,8 +1156,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1123,8 +1179,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error0_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error0_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -1155,8 +1213,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error1_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error1_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -1187,8 +1247,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error2_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error2_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -1219,8 +1281,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error3_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error3_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -1251,8 +1315,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.notif_cmd_done_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -1283,8 +1349,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error0_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; @@ -1312,8 +1380,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error1_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; @@ -1341,8 +1411,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error2_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; @@ -1370,8 +1442,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.error3_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; @@ -1399,8 +1473,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; @@ -1441,7 +1517,7 @@ module sha256_reg ( logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [32-1:0][31:0] readback_array; for(genvar i0=0; i0<2; i0++) begin @@ -1517,4 +1593,4 @@ module sha256_reg ( `CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.error_reset_b) -endmodule \ No newline at end of file +endmodule diff --git a/src/sha512/config/compile.yml b/src/sha512/config/compile.yml index f7c6f56f6..4aac0bbf3 100755 --- a/src/sha512/config/compile.yml +++ b/src/sha512/config/compile.yml @@ -24,8 +24,6 @@ targets: waiver_files: #- $COMPILE_ROOT/config/rtl_lint/sha512.waiver - $MSFT_REPO_ROOT/src/sha512/config/design_lint/sha512_ctrl/sglint_waivers - black_box: - - sha512_reg --- provides: [sha512_ctrl_32bit_tb] schema_version: 2.4.0 diff --git a/src/sha512/rtl/sha512.sv b/src/sha512/rtl/sha512.sv index 95d8690d0..04ffe38b4 100644 --- a/src/sha512/rtl/sha512.sv +++ b/src/sha512/rtl/sha512.sv @@ -252,7 +252,7 @@ module sha512 end // reg_update always_comb begin - unique casez (mode_reg) + unique case (mode_reg) 2'b00 : get_mask = {{7{32'hffffffff}}, {9{32'h00000000}}}; //SHA512/224 2'b01 : get_mask = {{8{32'hffffffff}}, {8{32'h00000000}}}; //SHA512/256 2'b10 : get_mask = {{12{32'hffffffff}}, {4{32'h00000000}}}; //SHA384 diff --git a/src/sha512/rtl/sha512_core.v b/src/sha512/rtl/sha512_core.v index 159d8df5d..2b174f355 100644 --- a/src/sha512/rtl/sha512_core.v +++ b/src/sha512/rtl/sha512_core.v @@ -492,7 +492,7 @@ module sha512_core( sha512_ctrl_new = CTRL_IDLE; sha512_ctrl_we = 1'b0; - unique casez (sha512_ctrl_reg) + unique case (sha512_ctrl_reg) CTRL_IDLE: begin if (init_cmd) diff --git a/src/sha512/rtl/sha512_ctrl.sv b/src/sha512/rtl/sha512_ctrl.sv index 310a26244..882549852 100644 --- a/src/sha512/rtl/sha512_ctrl.sv +++ b/src/sha512/rtl/sha512_ctrl.sv @@ -71,12 +71,12 @@ module sha512_ctrl //---------------------------------------------------------------- // sha512 //---------------------------------------------------------------- - reg sha512_cs; - reg sha512_we; - reg [AHB_ADDR_WIDTH - 1 : 0] sha512_address; - reg [31 : 0] sha512_write_data; - reg [31 : 0] sha512_read_data; - reg sha512_err; + logic sha512_cs; + logic sha512_we; + logic [AHB_ADDR_WIDTH - 1 : 0] sha512_address; + logic [31 : 0] sha512_write_data; + logic [31 : 0] sha512_read_data; + logic sha512_err; sha512 #( .ADDR_WIDTH(AHB_ADDR_WIDTH), diff --git a/src/sha512/rtl/sha512_h_constants.v b/src/sha512/rtl/sha512_h_constants.v index a0cadca67..bd0046e2b 100644 --- a/src/sha512/rtl/sha512_h_constants.v +++ b/src/sha512/rtl/sha512_h_constants.v @@ -82,7 +82,7 @@ module sha512_h_constants( //---------------------------------------------------------------- always @* begin : mode_mux - unique casez (mode) + unique case (mode) 0: begin // SHA-512/224 diff --git a/src/sha512/rtl/sha512_k_constants.v b/src/sha512/rtl/sha512_k_constants.v index a210970b0..4270a71bb 100644 --- a/src/sha512/rtl/sha512_k_constants.v +++ b/src/sha512/rtl/sha512_k_constants.v @@ -58,7 +58,7 @@ module sha512_k_constants( //---------------------------------------------------------------- always @* begin : addr_mux - unique casez(addr) + unique case(addr) 0: tmp_K = 64'h428a2f98d728ae22; 1: tmp_K = 64'h7137449123ef65cd; 2: tmp_K = 64'hb5c0fbcfec4d3b2f; diff --git a/src/sha512/rtl/sha512_reg.sv b/src/sha512/rtl/sha512_reg.sv index da08ef382..3f893839f 100644 --- a/src/sha512/rtl/sha512_reg.sv +++ b/src/sha512/rtl/sha512_reg.sv @@ -58,7 +58,9 @@ module sha512_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -108,50 +110,50 @@ module sha512_reg ( always_comb begin for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.SHA512_NAME[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); + decoded_reg_strb.SHA512_NAME[i0] = cpuif_req_masked & (cpuif_addr == 12'h0 + i0*12'h4); end for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.SHA512_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 'h8 + i0*'h4); + decoded_reg_strb.SHA512_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 12'h8 + i0*12'h4); end - decoded_reg_strb.SHA512_CTRL = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.SHA512_STATUS = cpuif_req_masked & (cpuif_addr == 'h18); + decoded_reg_strb.SHA512_CTRL = cpuif_req_masked & (cpuif_addr == 12'h10); + decoded_reg_strb.SHA512_STATUS = cpuif_req_masked & (cpuif_addr == 12'h18); for(int i0=0; i0<32; i0++) begin - decoded_reg_strb.SHA512_BLOCK[i0] = cpuif_req_masked & (cpuif_addr == 'h80 + i0*'h4); + decoded_reg_strb.SHA512_BLOCK[i0] = cpuif_req_masked & (cpuif_addr == 12'h80 + i0*12'h4); end for(int i0=0; i0<16; i0++) begin - decoded_reg_strb.SHA512_DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 'h100 + i0*'h4); + decoded_reg_strb.SHA512_DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 12'h100 + i0*12'h4); end - decoded_reg_strb.SHA512_VAULT_RD_CTRL = cpuif_req_masked & (cpuif_addr == 'h600); - decoded_reg_strb.SHA512_VAULT_RD_STATUS = cpuif_req_masked & (cpuif_addr == 'h604); - decoded_reg_strb.SHA512_KV_WR_CTRL = cpuif_req_masked & (cpuif_addr == 'h608); - decoded_reg_strb.SHA512_KV_WR_STATUS = cpuif_req_masked & (cpuif_addr == 'h60c); + decoded_reg_strb.SHA512_VAULT_RD_CTRL = cpuif_req_masked & (cpuif_addr == 12'h600); + decoded_reg_strb.SHA512_VAULT_RD_STATUS = cpuif_req_masked & (cpuif_addr == 12'h604); + decoded_reg_strb.SHA512_KV_WR_CTRL = cpuif_req_masked & (cpuif_addr == 12'h608); + decoded_reg_strb.SHA512_KV_WR_STATUS = cpuif_req_masked & (cpuif_addr == 12'h60c); for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.SHA512_GEN_PCR_HASH_NONCE[i0] = cpuif_req_masked & (cpuif_addr == 'h610 + i0*'h4); + decoded_reg_strb.SHA512_GEN_PCR_HASH_NONCE[i0] = cpuif_req_masked & (cpuif_addr == 12'h610 + i0*12'h4); end - decoded_reg_strb.SHA512_GEN_PCR_HASH_CTRL = cpuif_req_masked & (cpuif_addr == 'h630); - decoded_reg_strb.SHA512_GEN_PCR_HASH_STATUS = cpuif_req_masked & (cpuif_addr == 'h634); + decoded_reg_strb.SHA512_GEN_PCR_HASH_CTRL = cpuif_req_masked & (cpuif_addr == 12'h630); + decoded_reg_strb.SHA512_GEN_PCR_HASH_STATUS = cpuif_req_masked & (cpuif_addr == 12'h634); for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.SHA512_GEN_PCR_HASH_DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 'h638 + i0*'h4); - end - decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800); - decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804); - decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808); - decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h80c); - decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h810); - decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h814); - decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h818); - decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h81c); - decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h820); - decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h900); - decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h904); - decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h908); - decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h90c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980); - decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00); - decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04); - decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha08); - decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha0c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha10); + decoded_reg_strb.SHA512_GEN_PCR_HASH_DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 12'h638 + i0*12'h4); + end + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h80c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h810); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h814); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h818); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h81c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h820); + decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h900); + decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h904); + decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h908); + decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h90c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h980); + decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha00); + decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha04); + decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha08); + decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha0c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha10); end // Pass down signals to next stage @@ -160,10 +162,6 @@ module sha512_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -699,12 +697,14 @@ module sha512_reg ( // Field: sha512_reg.SHA512_CTRL.INIT always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_CTRL.INIT.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_CTRL.INIT.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_CTRL.INIT.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -713,7 +713,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_CTRL.INIT.value <= 'h0; + field_storage.SHA512_CTRL.INIT.value <= 1'h0; end else if(field_combo.SHA512_CTRL.INIT.load_next) begin field_storage.SHA512_CTRL.INIT.value <= field_combo.SHA512_CTRL.INIT.next; end @@ -721,12 +721,14 @@ module sha512_reg ( assign hwif_out.SHA512_CTRL.INIT.value = field_storage.SHA512_CTRL.INIT.value; // Field: sha512_reg.SHA512_CTRL.NEXT always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_CTRL.NEXT.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_CTRL.NEXT.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_CTRL.NEXT.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -735,7 +737,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_CTRL.NEXT.value <= 'h0; + field_storage.SHA512_CTRL.NEXT.value <= 1'h0; end else if(field_combo.SHA512_CTRL.NEXT.load_next) begin field_storage.SHA512_CTRL.NEXT.value <= field_combo.SHA512_CTRL.NEXT.next; end @@ -743,8 +745,10 @@ module sha512_reg ( assign hwif_out.SHA512_CTRL.NEXT.value = field_storage.SHA512_CTRL.NEXT.value; // Field: sha512_reg.SHA512_CTRL.MODE always_comb begin - automatic logic [1:0] next_c = field_storage.SHA512_CTRL.MODE.value; - automatic logic load_next_c = '0; + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_CTRL.MODE.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_CTRL.MODE.value & ~decoded_wr_biten[3:2]) | (decoded_wr_data[3:2] & decoded_wr_biten[3:2]); load_next_c = '1; @@ -754,7 +758,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_CTRL.MODE.value <= 'h2; + field_storage.SHA512_CTRL.MODE.value <= 2'h2; end else if(field_combo.SHA512_CTRL.MODE.load_next) begin field_storage.SHA512_CTRL.MODE.value <= field_combo.SHA512_CTRL.MODE.next; end @@ -762,12 +766,14 @@ module sha512_reg ( assign hwif_out.SHA512_CTRL.MODE.value = field_storage.SHA512_CTRL.MODE.value; // Field: sha512_reg.SHA512_CTRL.ZEROIZE always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_CTRL.ZEROIZE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_CTRL.ZEROIZE.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_CTRL.ZEROIZE.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -776,7 +782,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_CTRL.ZEROIZE.value <= 'h0; + field_storage.SHA512_CTRL.ZEROIZE.value <= 1'h0; end else if(field_combo.SHA512_CTRL.ZEROIZE.load_next) begin field_storage.SHA512_CTRL.ZEROIZE.value <= field_combo.SHA512_CTRL.ZEROIZE.next; end @@ -784,8 +790,10 @@ module sha512_reg ( assign hwif_out.SHA512_CTRL.ZEROIZE.value = field_storage.SHA512_CTRL.ZEROIZE.value; // Field: sha512_reg.SHA512_CTRL.LAST always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_CTRL.LAST.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_CTRL.LAST.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_CTRL.LAST.value & ~decoded_wr_biten[5:5]) | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]); load_next_c = '1; @@ -798,7 +806,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_CTRL.LAST.value <= 'h0; + field_storage.SHA512_CTRL.LAST.value <= 1'h0; end else if(field_combo.SHA512_CTRL.LAST.load_next) begin field_storage.SHA512_CTRL.LAST.value <= field_combo.SHA512_CTRL.LAST.next; end @@ -807,8 +815,10 @@ module sha512_reg ( for(genvar i0=0; i0<32; i0++) begin // Field: sha512_reg.SHA512_BLOCK[].BLOCK always_comb begin - automatic logic [31:0] next_c = field_storage.SHA512_BLOCK[i0].BLOCK.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_BLOCK[i0].BLOCK.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_BLOCK[i0] && decoded_req_is_wr && !(hwif_in.SHA512_BLOCK[i0].BLOCK.swwel)) begin // SW write next_c = (field_storage.SHA512_BLOCK[i0].BLOCK.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -824,7 +834,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_BLOCK[i0].BLOCK.value <= 'h0; + field_storage.SHA512_BLOCK[i0].BLOCK.value <= 32'h0; end else if(field_combo.SHA512_BLOCK[i0].BLOCK.load_next) begin field_storage.SHA512_BLOCK[i0].BLOCK.value <= field_combo.SHA512_BLOCK[i0].BLOCK.next; end @@ -834,21 +844,23 @@ module sha512_reg ( for(genvar i0=0; i0<16; i0++) begin // Field: sha512_reg.SHA512_DIGEST[].DIGEST always_comb begin - automatic logic [31:0] next_c = field_storage.SHA512_DIGEST[i0].DIGEST.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.SHA512_DIGEST[i0].DIGEST.next; - load_next_c = '1; - end else if(hwif_in.SHA512_DIGEST[i0].DIGEST.hwclr) begin // HW Clear + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_DIGEST[i0].DIGEST.value; + load_next_c = '0; + if(hwif_in.SHA512_DIGEST[i0].DIGEST.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; + end else begin // HW Write + next_c = hwif_in.SHA512_DIGEST[i0].DIGEST.next; + load_next_c = '1; end field_combo.SHA512_DIGEST[i0].DIGEST.next = next_c; field_combo.SHA512_DIGEST[i0].DIGEST.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_DIGEST[i0].DIGEST.value <= 'h0; + field_storage.SHA512_DIGEST[i0].DIGEST.value <= 32'h0; end else if(field_combo.SHA512_DIGEST[i0].DIGEST.load_next) begin field_storage.SHA512_DIGEST[i0].DIGEST.value <= field_combo.SHA512_DIGEST[i0].DIGEST.next; end @@ -856,8 +868,10 @@ module sha512_reg ( end // Field: sha512_reg.SHA512_VAULT_RD_CTRL.read_en always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_VAULT_RD_CTRL.read_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_VAULT_RD_CTRL.read_en.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_VAULT_RD_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_VAULT_RD_CTRL.read_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -870,7 +884,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_VAULT_RD_CTRL.read_en.value <= 'h0; + field_storage.SHA512_VAULT_RD_CTRL.read_en.value <= 1'h0; end else if(field_combo.SHA512_VAULT_RD_CTRL.read_en.load_next) begin field_storage.SHA512_VAULT_RD_CTRL.read_en.value <= field_combo.SHA512_VAULT_RD_CTRL.read_en.next; end @@ -878,8 +892,10 @@ module sha512_reg ( assign hwif_out.SHA512_VAULT_RD_CTRL.read_en.value = field_storage.SHA512_VAULT_RD_CTRL.read_en.value; // Field: sha512_reg.SHA512_VAULT_RD_CTRL.read_entry always_comb begin - automatic logic [4:0] next_c = field_storage.SHA512_VAULT_RD_CTRL.read_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_VAULT_RD_CTRL.read_entry.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_VAULT_RD_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_VAULT_RD_CTRL.read_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -889,7 +905,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_VAULT_RD_CTRL.read_entry.value <= 'h0; + field_storage.SHA512_VAULT_RD_CTRL.read_entry.value <= 5'h0; end else if(field_combo.SHA512_VAULT_RD_CTRL.read_entry.load_next) begin field_storage.SHA512_VAULT_RD_CTRL.read_entry.value <= field_combo.SHA512_VAULT_RD_CTRL.read_entry.next; end @@ -897,8 +913,10 @@ module sha512_reg ( assign hwif_out.SHA512_VAULT_RD_CTRL.read_entry.value = field_storage.SHA512_VAULT_RD_CTRL.read_entry.value; // Field: sha512_reg.SHA512_VAULT_RD_CTRL.pcr_hash_extend always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_VAULT_RD_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -908,7 +926,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value <= 'h0; + field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value <= 1'h0; end else if(field_combo.SHA512_VAULT_RD_CTRL.pcr_hash_extend.load_next) begin field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value <= field_combo.SHA512_VAULT_RD_CTRL.pcr_hash_extend.next; end @@ -916,8 +934,10 @@ module sha512_reg ( assign hwif_out.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value = field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value; // Field: sha512_reg.SHA512_VAULT_RD_CTRL.rsvd always_comb begin - automatic logic [24:0] next_c = field_storage.SHA512_VAULT_RD_CTRL.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [24:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_VAULT_RD_CTRL.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_VAULT_RD_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_VAULT_RD_CTRL.rsvd.value & ~decoded_wr_biten[31:7]) | (decoded_wr_data[31:7] & decoded_wr_biten[31:7]); load_next_c = '1; @@ -927,7 +947,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_VAULT_RD_CTRL.rsvd.value <= 'h0; + field_storage.SHA512_VAULT_RD_CTRL.rsvd.value <= 25'h0; end else if(field_combo.SHA512_VAULT_RD_CTRL.rsvd.load_next) begin field_storage.SHA512_VAULT_RD_CTRL.rsvd.value <= field_combo.SHA512_VAULT_RD_CTRL.rsvd.next; end @@ -935,8 +955,10 @@ module sha512_reg ( assign hwif_out.SHA512_VAULT_RD_CTRL.rsvd.value = field_storage.SHA512_VAULT_RD_CTRL.rsvd.value; // Field: sha512_reg.SHA512_VAULT_RD_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_VAULT_RD_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_VAULT_RD_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.SHA512_VAULT_RD_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -949,15 +971,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_VAULT_RD_STATUS.VALID.value <= 'h0; + field_storage.SHA512_VAULT_RD_STATUS.VALID.value <= 1'h0; end else if(field_combo.SHA512_VAULT_RD_STATUS.VALID.load_next) begin field_storage.SHA512_VAULT_RD_STATUS.VALID.value <= field_combo.SHA512_VAULT_RD_STATUS.VALID.next; end end // Field: sha512_reg.SHA512_KV_WR_CTRL.write_en always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_CTRL.write_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.write_en.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.write_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -970,7 +994,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.write_en.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.write_en.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_CTRL.write_en.load_next) begin field_storage.SHA512_KV_WR_CTRL.write_en.value <= field_combo.SHA512_KV_WR_CTRL.write_en.next; end @@ -978,8 +1002,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.write_en.value = field_storage.SHA512_KV_WR_CTRL.write_en.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.write_entry always_comb begin - automatic logic [4:0] next_c = field_storage.SHA512_KV_WR_CTRL.write_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.write_entry.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.write_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -989,7 +1015,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.write_entry.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.write_entry.value <= 5'h0; end else if(field_combo.SHA512_KV_WR_CTRL.write_entry.load_next) begin field_storage.SHA512_KV_WR_CTRL.write_entry.value <= field_combo.SHA512_KV_WR_CTRL.write_entry.next; end @@ -997,8 +1023,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.write_entry.value = field_storage.SHA512_KV_WR_CTRL.write_entry.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.hmac_key_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -1008,7 +1036,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_CTRL.hmac_key_dest_valid.load_next) begin field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value <= field_combo.SHA512_KV_WR_CTRL.hmac_key_dest_valid.next; end @@ -1016,8 +1044,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value = field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.hmac_block_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value & ~decoded_wr_biten[7:7]) | (decoded_wr_data[7:7] & decoded_wr_biten[7:7]); load_next_c = '1; @@ -1027,7 +1057,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_CTRL.hmac_block_dest_valid.load_next) begin field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value <= field_combo.SHA512_KV_WR_CTRL.hmac_block_dest_valid.next; end @@ -1035,8 +1065,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value = field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.sha_block_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]); load_next_c = '1; @@ -1046,7 +1078,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_CTRL.sha_block_dest_valid.load_next) begin field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value <= field_combo.SHA512_KV_WR_CTRL.sha_block_dest_valid.next; end @@ -1054,8 +1086,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.sha_block_dest_valid.value = field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value & ~decoded_wr_biten[9:9]) | (decoded_wr_data[9:9] & decoded_wr_biten[9:9]); load_next_c = '1; @@ -1065,7 +1099,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.load_next) begin field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value <= field_combo.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.next; end @@ -1073,8 +1107,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value = field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.ecc_seed_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value & ~decoded_wr_biten[10:10]) | (decoded_wr_data[10:10] & decoded_wr_biten[10:10]); load_next_c = '1; @@ -1084,7 +1120,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.load_next) begin field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value <= field_combo.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.next; end @@ -1092,8 +1128,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value = field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.rsvd always_comb begin - automatic logic [20:0] next_c = field_storage.SHA512_KV_WR_CTRL.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [20:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.rsvd.value & ~decoded_wr_biten[31:11]) | (decoded_wr_data[31:11] & decoded_wr_biten[31:11]); load_next_c = '1; @@ -1103,7 +1141,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.rsvd.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.rsvd.value <= 21'h0; end else if(field_combo.SHA512_KV_WR_CTRL.rsvd.load_next) begin field_storage.SHA512_KV_WR_CTRL.rsvd.value <= field_combo.SHA512_KV_WR_CTRL.rsvd.next; end @@ -1111,8 +1149,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.rsvd.value = field_storage.SHA512_KV_WR_CTRL.rsvd.value; // Field: sha512_reg.SHA512_KV_WR_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.SHA512_KV_WR_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1125,7 +1165,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_STATUS.VALID.value <= 'h0; + field_storage.SHA512_KV_WR_STATUS.VALID.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_STATUS.VALID.load_next) begin field_storage.SHA512_KV_WR_STATUS.VALID.value <= field_combo.SHA512_KV_WR_STATUS.VALID.next; end @@ -1133,8 +1173,10 @@ module sha512_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: sha512_reg.SHA512_GEN_PCR_HASH_NONCE[].NONCE always_comb begin - automatic logic [31:0] next_c = field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_GEN_PCR_HASH_NONCE[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -1144,7 +1186,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value <= 'h0; + field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value <= 32'h0; end else if(field_combo.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.load_next) begin field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value <= field_combo.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.next; end @@ -1153,12 +1195,14 @@ module sha512_reg ( end // Field: sha512_reg.SHA512_GEN_PCR_HASH_CTRL.START always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_GEN_PCR_HASH_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1167,7 +1211,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value <= 'h0; + field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value <= 1'h0; end else if(field_combo.SHA512_GEN_PCR_HASH_CTRL.START.load_next) begin field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value <= field_combo.SHA512_GEN_PCR_HASH_CTRL.START.next; end @@ -1175,8 +1219,10 @@ module sha512_reg ( assign hwif_out.SHA512_GEN_PCR_HASH_CTRL.START.value = field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value; // Field: sha512_reg.SHA512_GEN_PCR_HASH_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_GEN_PCR_HASH_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_GEN_PCR_HASH_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.SHA512_GEN_PCR_HASH_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1189,7 +1235,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_GEN_PCR_HASH_STATUS.VALID.value <= 'h0; + field_storage.SHA512_GEN_PCR_HASH_STATUS.VALID.value <= 1'h0; end else if(field_combo.SHA512_GEN_PCR_HASH_STATUS.VALID.load_next) begin field_storage.SHA512_GEN_PCR_HASH_STATUS.VALID.value <= field_combo.SHA512_GEN_PCR_HASH_STATUS.VALID.next; end @@ -1197,21 +1243,23 @@ module sha512_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: sha512_reg.SHA512_GEN_PCR_HASH_DIGEST[].DIGEST always_comb begin - automatic logic [31:0] next_c = field_storage.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.next; - load_next_c = '1; - end else if(hwif_in.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.hwclr) begin // HW Clear + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.value; + load_next_c = '0; + if(hwif_in.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; + end else begin // HW Write + next_c = hwif_in.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.next; + load_next_c = '1; end field_combo.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.next = next_c; field_combo.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.value <= 'h0; + field_storage.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.value <= 32'h0; end else if(field_combo.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.load_next) begin field_storage.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.value <= field_combo.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.next; end @@ -1219,8 +1267,10 @@ module sha512_reg ( end // Field: sha512_reg.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1230,15 +1280,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; end end // Field: sha512_reg.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -1248,15 +1300,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; end end // Field: sha512_reg.intr_block_rf.error_intr_en_r.error0_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error0_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1266,15 +1320,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error0_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= field_combo.intr_block_rf.error_intr_en_r.error0_en.next; end end // Field: sha512_reg.intr_block_rf.error_intr_en_r.error1_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error1_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -1284,15 +1340,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error1_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= field_combo.intr_block_rf.error_intr_en_r.error1_en.next; end end // Field: sha512_reg.intr_block_rf.error_intr_en_r.error2_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error2_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -1302,15 +1360,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error2_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= field_combo.intr_block_rf.error_intr_en_r.error2_en.next; end end // Field: sha512_reg.intr_block_rf.error_intr_en_r.error3_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error3_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -1320,15 +1380,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error3_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= field_combo.intr_block_rf.error_intr_en_r.error3_en.next; end end // Field: sha512_reg.intr_block_rf.notif_intr_en_r.notif_cmd_done_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1338,25 +1400,27 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.next; end end // Field: sha512_reg.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; end @@ -1365,18 +1429,20 @@ module sha512_reg ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: sha512_reg.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; end @@ -1385,9 +1451,11 @@ module sha512_reg ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: sha512_reg.intr_block_rf.error_internal_intr_r.error0_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error0_sts.hwset) begin // HW Set @@ -1402,16 +1470,18 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error0_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error0_sts.next; end end // Field: sha512_reg.intr_block_rf.error_internal_intr_r.error1_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error1_sts.hwset) begin // HW Set @@ -1426,16 +1496,18 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error1_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error1_sts.next; end end // Field: sha512_reg.intr_block_rf.error_internal_intr_r.error2_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error2_sts.hwset) begin // HW Set @@ -1450,16 +1522,18 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error2_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error2_sts.next; end end // Field: sha512_reg.intr_block_rf.error_internal_intr_r.error3_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error3_sts.hwset) begin // HW Set @@ -1474,7 +1548,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error3_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error3_sts.next; end @@ -1486,9 +1560,11 @@ module sha512_reg ( || |(field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value & field_storage.intr_block_rf.error_intr_en_r.error3_en.value); // Field: sha512_reg.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset) begin // HW Set @@ -1503,7 +1579,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.next; end @@ -1512,12 +1588,14 @@ module sha512_reg ( |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value); // Field: sha512_reg.intr_block_rf.error_intr_trig_r.error0_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1526,19 +1604,21 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error0_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error0_trig.next; end end // Field: sha512_reg.intr_block_rf.error_intr_trig_r.error1_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1547,19 +1627,21 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error1_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error1_trig.next; end end // Field: sha512_reg.intr_block_rf.error_intr_trig_r.error2_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1568,19 +1650,21 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error2_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error2_trig.next; end end // Field: sha512_reg.intr_block_rf.error_intr_trig_r.error3_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1589,19 +1673,21 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error3_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error3_trig.next; end end // Field: sha512_reg.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1610,31 +1696,33 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.next; end end // Field: sha512_reg.intr_block_rf.error0_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error0_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error0_intr_count_r.cnt.next = next_c; @@ -1642,31 +1730,33 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error0_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= field_combo.intr_block_rf.error0_intr_count_r.cnt.next; end end // Field: sha512_reg.intr_block_rf.error1_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error1_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error1_intr_count_r.cnt.next = next_c; @@ -1674,31 +1764,33 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error1_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= field_combo.intr_block_rf.error1_intr_count_r.cnt.next; end end // Field: sha512_reg.intr_block_rf.error2_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error2_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error2_intr_count_r.cnt.next = next_c; @@ -1706,31 +1798,33 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error2_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= field_combo.intr_block_rf.error2_intr_count_r.cnt.next; end end // Field: sha512_reg.intr_block_rf.error3_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error3_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error3_intr_count_r.cnt.next = next_c; @@ -1738,31 +1832,33 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error3_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= field_combo.intr_block_rf.error3_intr_count_r.cnt.next; end end // Field: sha512_reg.intr_block_rf.notif_cmd_done_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next = next_c; @@ -1770,15 +1866,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next; end end // Field: sha512_reg.intr_block_rf.error0_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; @@ -1787,27 +1885,29 @@ module sha512_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next; end end // Field: sha512_reg.intr_block_rf.error1_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; @@ -1816,27 +1916,29 @@ module sha512_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next; end end // Field: sha512_reg.intr_block_rf.error2_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; @@ -1845,27 +1947,29 @@ module sha512_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next; end end // Field: sha512_reg.intr_block_rf.error3_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; @@ -1874,27 +1978,29 @@ module sha512_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next; end end // Field: sha512_reg.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; @@ -1903,30 +2009,39 @@ module sha512_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [57-1:0][31:0] readback_array; for(genvar i0=0; i0<2; i0++) begin @@ -2027,4 +2142,4 @@ module sha512_reg ( `CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.error_reset_b) -endmodule \ No newline at end of file +endmodule diff --git a/src/sha512/rtl/sha512_reg_pkg.sv b/src/sha512/rtl/sha512_reg_pkg.sv index 6d2cfe3a6..d5a980dd8 100644 --- a/src/sha512/rtl/sha512_reg_pkg.sv +++ b/src/sha512/rtl/sha512_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package sha512_reg_pkg; + + localparam SHA512_REG_DATA_WIDTH = 32; + localparam SHA512_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic [31:0] next; } sha512_reg__SHA512_NAME__NAME__in_t; @@ -65,7 +69,7 @@ package sha512_reg_pkg; typedef struct packed{ kv_read_ctrl_reg__read_en__in_t read_en; - } __kv_read_ctrl_reg__in_t; + } kv_read_ctrl_reg__in_t; typedef struct packed{ logic next; @@ -84,7 +88,7 @@ package sha512_reg_pkg; kv_status_reg__READY__in_t READY; kv_status_reg__VALID__in_t VALID; kv_status_reg__ERROR__in_t ERROR; - } __kv_status_reg__in_t; + } kv_status_reg__in_t; typedef struct packed{ logic hwclr; @@ -92,7 +96,7 @@ package sha512_reg_pkg; typedef struct packed{ kv_write_ctrl_reg__write_en__in_t write_en; - } __kv_write_ctrl_reg__in_t; + } kv_write_ctrl_reg__in_t; typedef struct packed{ logic next; @@ -119,33 +123,33 @@ package sha512_reg_pkg; typedef struct packed{ logic hwset; - } sha512_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t; + } sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } sha512_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t; + } sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } sha512_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t; + } sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } sha512_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t; + } sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t; typedef struct packed{ - sha512_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t error0_sts; - sha512_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t error1_sts; - sha512_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t error2_sts; - sha512_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t error3_sts; + sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t error0_sts; + sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t error1_sts; + sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t error2_sts; + sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t error3_sts; } sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__in_t; typedef struct packed{ logic hwset; - } sha512_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; + } sha512_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; typedef struct packed{ - sha512_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; + sha512_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; } sha512_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__in_t; typedef struct packed{ @@ -162,10 +166,10 @@ package sha512_reg_pkg; sha512_reg__SHA512_STATUS__in_t SHA512_STATUS; sha512_reg__SHA512_BLOCK__in_t [32-1:0]SHA512_BLOCK; sha512_reg__SHA512_DIGEST__in_t [16-1:0]SHA512_DIGEST; - __kv_read_ctrl_reg__in_t SHA512_VAULT_RD_CTRL; - __kv_status_reg__in_t SHA512_VAULT_RD_STATUS; - __kv_write_ctrl_reg__in_t SHA512_KV_WR_CTRL; - __kv_status_reg__in_t SHA512_KV_WR_STATUS; + kv_read_ctrl_reg__in_t SHA512_VAULT_RD_CTRL; + kv_status_reg__in_t SHA512_VAULT_RD_STATUS; + kv_write_ctrl_reg__in_t SHA512_KV_WR_CTRL; + kv_status_reg__in_t SHA512_KV_WR_STATUS; sha512_reg__SHA512_GEN_PCR_HASH_STATUS__in_t SHA512_GEN_PCR_HASH_STATUS; sha512_reg__SHA512_GEN_PCR_HASH_DIGEST__in_t [12-1:0]SHA512_GEN_PCR_HASH_DIGEST; sha512_reg__intr_block_t__in_t intr_block_rf; @@ -228,7 +232,7 @@ package sha512_reg_pkg; kv_read_ctrl_reg__read_entry__out_t read_entry; kv_read_ctrl_reg__pcr_hash_extend__out_t pcr_hash_extend; kv_read_ctrl_reg__rsvd__out_t rsvd; - } __kv_read_ctrl_reg__out_t; + } kv_read_ctrl_reg__out_t; typedef struct packed{ logic value; @@ -271,7 +275,7 @@ package sha512_reg_pkg; kv_write_ctrl_reg__ecc_pkey_dest_valid__out_t ecc_pkey_dest_valid; kv_write_ctrl_reg__ecc_seed_dest_valid__out_t ecc_seed_dest_valid; kv_write_ctrl_reg__rsvd__out_t rsvd; - } __kv_write_ctrl_reg__out_t; + } kv_write_ctrl_reg__out_t; typedef struct packed{ logic [31:0] value; @@ -315,13 +319,19 @@ package sha512_reg_pkg; typedef struct packed{ sha512_reg__SHA512_CTRL__out_t SHA512_CTRL; sha512_reg__SHA512_BLOCK__out_t [32-1:0]SHA512_BLOCK; - __kv_read_ctrl_reg__out_t SHA512_VAULT_RD_CTRL; - __kv_write_ctrl_reg__out_t SHA512_KV_WR_CTRL; + kv_read_ctrl_reg__out_t SHA512_VAULT_RD_CTRL; + kv_write_ctrl_reg__out_t SHA512_KV_WR_CTRL; sha512_reg__SHA512_GEN_PCR_HASH_NONCE__out_t [8-1:0]SHA512_GEN_PCR_HASH_NONCE; sha512_reg__SHA512_GEN_PCR_HASH_CTRL__out_t SHA512_GEN_PCR_HASH_CTRL; sha512_reg__intr_block_t__out_t intr_block_rf; } sha512_reg__out_t; + typedef enum logic [31:0] { + kv_status_reg__ERROR__kv_error_e__SUCCESS = 'h0, + kv_status_reg__ERROR__kv_error_e__KV_READ_FAIL = 'h1, + kv_status_reg__ERROR__kv_error_e__KV_WRITE_FAIL = 'h2 + } kv_status_reg__ERROR__kv_error_e_e; + localparam SHA512_REG_ADDR_WIDTH = 32'd12; endpackage \ No newline at end of file diff --git a/src/sha512_masked/config/compile.yml b/src/sha512_masked/config/compile.yml index 174837a09..dab58fa56 100755 --- a/src/sha512_masked/config/compile.yml +++ b/src/sha512_masked/config/compile.yml @@ -16,8 +16,6 @@ targets: #waiver_files: #- $COMPILE_ROOT/config/rtl_lint/sha512.waiver #- $COMPILE_ROOT/config/design_lint/sha512_ctrl/sglint_waivers - #black_box: - #- sha512_reg --- provides: [sha512_masked_core_tb] schema_version: 2.4.0 diff --git a/src/sha512_masked/rtl/sha512_masked_core.sv b/src/sha512_masked/rtl/sha512_masked_core.sv index c6b0f97c2..9ba0f1471 100644 --- a/src/sha512_masked/rtl/sha512_masked_core.sv +++ b/src/sha512_masked/rtl/sha512_masked_core.sv @@ -642,7 +642,7 @@ module sha512_masked_core init_reg_set = 1'b0; init_reg_reset = 1'b0; - unique casez (sha512_ctrl_reg) + unique case (sha512_ctrl_reg) CTRL_IDLE: begin if (init_cmd | next_cmd) diff --git a/src/soc_ifc/config/compile.yml b/src/soc_ifc/config/compile.yml index 85cdd473b..4dd2b2a39 100644 --- a/src/soc_ifc/config/compile.yml +++ b/src/soc_ifc/config/compile.yml @@ -68,17 +68,8 @@ targets: tops: [soc_ifc_top] rtl_lint: directories: [$COMPILE_ROOT/config/design_lint] - black_box: - - mbox_csr - - mbox_csr_pkg - - soc_ifc_reg - - soc_ifc_reg_pkg waiver_files: - $MSFT_REPO_ROOT/src/soc_ifc/config/design_lint/soc_ifc/sglint_waivers - black_box: - - sha512_acc_csr - - mbox_csr - - soc_ifc_reg tops: [soc_ifc_top] --- provides: [soc_ifc_tb] diff --git a/src/soc_ifc/rtl/caliptra_top_reg.h b/src/soc_ifc/rtl/caliptra_top_reg.h index 553225858..790b71cb8 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg.h +++ b/src/soc_ifc/rtl/caliptra_top_reg.h @@ -542,4 +542,4 @@ #define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (0xffff) -#endif +#endif \ No newline at end of file diff --git a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh index 9677a065e..344d910ea 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh +++ b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh @@ -542,4 +542,4 @@ `define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (32'hffff) -`endif +`endif \ No newline at end of file diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv index 5dd7207de..5504e8772 100644 --- a/src/soc_ifc/rtl/mbox.sv +++ b/src/soc_ifc/rtl/mbox.sv @@ -64,6 +64,7 @@ module mbox localparam MBOX_SIZE_IN_BYTES = SIZE_KB*1024; localparam MBOX_SIZE_IN_DW = (MBOX_SIZE_IN_BYTES)/4; localparam DEPTH = (MBOX_SIZE_IN_DW * 32) / DATA_W; +localparam DEPTH_LOG2 = $clog2(DEPTH); //this module is used to instantiate a single mailbox instance //requests within the address space of this mailbox are routed here from the top level @@ -97,12 +98,12 @@ logic arc_MBOX_EXECUTE_SOC_MBOX_ERROR; //sram logic [DATA_W-1:0] sram_wdata; logic [MBOX_ECC_DATA_W-1:0] sram_wdata_ecc; -logic [$clog2(DEPTH)-1:0] sram_waddr; -logic [$clog2(DEPTH)-1:0] mbox_wrptr, mbox_wrptr_nxt; +logic [DEPTH_LOG2-1:0] sram_waddr; +logic [DEPTH_LOG2-1:0] mbox_wrptr, mbox_wrptr_nxt; logic mbox_wr_full, mbox_wr_full_nxt; logic inc_wrptr; -logic [$clog2(DEPTH)-1:0] sram_rdaddr; -logic [$clog2(DEPTH)-1:0] mbox_rdptr, mbox_rdptr_nxt; +logic [DEPTH_LOG2-1:0] sram_rdaddr; +logic [DEPTH_LOG2-1:0] mbox_rdptr, mbox_rdptr_nxt; logic mbox_rd_full, mbox_rd_full_nxt; logic inc_rdptr; logic rst_mbox_rdptr; @@ -118,15 +119,15 @@ logic mbox_protocol_sram_rd, mbox_protocol_sram_rd_f; logic dir_req_dv_q, dir_req_rd_phase; logic dir_req_wr_ph; logic mask_rdata; -logic [$clog2(DEPTH)-1:0] dir_req_addr; +logic [DEPTH_LOG2-1:0] dir_req_addr; logic soc_has_lock, soc_has_lock_nxt; logic valid_requester; logic valid_receiver; -logic [$clog2(DEPTH):0] mbox_dlen_in_dws; +logic [DEPTH_LOG2:0] mbox_dlen_in_dws; logic latch_dlen_in_dws; -logic [$clog2(DEPTH):0] dlen_in_dws, dlen_in_dws_nxt; +logic [DEPTH_LOG2:0] dlen_in_dws, dlen_in_dws_nxt; logic rdptr_inc_valid; logic mbox_rd_valid, mbox_rd_valid_f; logic wrptr_inc_valid; @@ -219,8 +220,8 @@ always_comb arc_MBOX_EXECUTE_SOC_MBOX_ERROR = (mbox_fsm_ps == MBOX_EXECUTE_SOC) //by the client filling the mailbox is used for masking the data //Store the dlen as a ptr to the last entry always_comb latch_dlen_in_dws = arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_UC | arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_SOC | arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC; -always_comb mbox_dlen_in_dws = (hwif_out.mbox_dlen.length.value >= MBOX_SIZE_IN_BYTES) ? MBOX_SIZE_IN_DW : - (hwif_out.mbox_dlen.length.value >> 2) + (hwif_out.mbox_dlen.length.value[0] | hwif_out.mbox_dlen.length.value[1]); +always_comb mbox_dlen_in_dws = (hwif_out.mbox_dlen.length.value >= MBOX_SIZE_IN_BYTES) ? MBOX_SIZE_IN_DW[DEPTH_LOG2:0] : + DEPTH_LOG2'(hwif_out.mbox_dlen.length.value >> 2) + (hwif_out.mbox_dlen.length.value[0] | hwif_out.mbox_dlen.length.value[1]); //latched dlen is the smaller of the programmed dlen or the current wrptr //this avoids a case where a sender writes less than programmed and the receiver can read beyond that //if the mailbox is full (flag set when writing last entry), always take the programmed dlen @@ -247,7 +248,7 @@ always_comb begin : mbox_fsm_combo mbox_protocol_error_nxt = '{default: 0}; mbox_fsm_ns = mbox_fsm_ps; - unique casez (mbox_fsm_ps) + unique case (mbox_fsm_ps) MBOX_IDLE: begin if (arc_MBOX_IDLE_MBOX_RDY_FOR_CMD) begin mbox_fsm_ns = MBOX_RDY_FOR_CMD; @@ -435,7 +436,7 @@ end always_comb dir_req_dv_q = (dir_req_dv & ~dir_req_rd_phase & hwif_out.mbox_lock.lock.value & (~soc_has_lock | (mbox_fsm_ps == MBOX_EXECUTE_UC))) | sha_sram_req_dv; always_comb dir_req_wr_ph = dir_req_dv_q & ~sha_sram_req_dv & req_data.write; -always_comb dir_req_addr = sha_sram_req_dv ? sha_sram_req_addr : req_data.addr[$clog2(DEPTH)+1:2]; +always_comb dir_req_addr = sha_sram_req_dv ? sha_sram_req_addr : req_data.addr[DEPTH_LOG2+1:2]; //Direct read from uC, stall 1 clock dv_q will be de-asserted second clock always_comb req_hold = (dir_req_dv_q & ~sha_sram_req_dv & ~req_data.write) | @@ -478,8 +479,10 @@ rvecc_encode mbox_ecc_encode ( .ecc_out(sram_wdata_ecc) ); // synthesis translate_off +`ifdef CLP_ASSERT_ON initial assert(DATA_W == 32) else $error("%m::rvecc_encode supports 32-bit data width; must change SRAM ECC implementation to support DATA_W = %d", DATA_W); +`endif // synthesis translate_on rvecc_decode ecc_decode ( .en (sram_rd_ecc_en ), diff --git a/src/soc_ifc/rtl/mbox_csr.sv b/src/soc_ifc/rtl/mbox_csr.sv index dddf953be..c58f79ea2 100644 --- a/src/soc_ifc/rtl/mbox_csr.sv +++ b/src/soc_ifc/rtl/mbox_csr.sv @@ -58,7 +58,9 @@ module mbox_csr ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -81,15 +83,15 @@ module mbox_csr ( logic [31:0] decoded_wr_biten; always_comb begin - decoded_reg_strb.mbox_lock = cpuif_req_masked & (cpuif_addr == 'h0); - decoded_reg_strb.mbox_user = cpuif_req_masked & (cpuif_addr == 'h4); - decoded_reg_strb.mbox_cmd = cpuif_req_masked & (cpuif_addr == 'h8); - decoded_reg_strb.mbox_dlen = cpuif_req_masked & (cpuif_addr == 'hc); - decoded_reg_strb.mbox_datain = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.mbox_dataout = cpuif_req_masked & (cpuif_addr == 'h14); - decoded_reg_strb.mbox_execute = cpuif_req_masked & (cpuif_addr == 'h18); - decoded_reg_strb.mbox_status = cpuif_req_masked & (cpuif_addr == 'h1c); - decoded_reg_strb.mbox_unlock = cpuif_req_masked & (cpuif_addr == 'h20); + decoded_reg_strb.mbox_lock = cpuif_req_masked & (cpuif_addr == 6'h0); + decoded_reg_strb.mbox_user = cpuif_req_masked & (cpuif_addr == 6'h4); + decoded_reg_strb.mbox_cmd = cpuif_req_masked & (cpuif_addr == 6'h8); + decoded_reg_strb.mbox_dlen = cpuif_req_masked & (cpuif_addr == 6'hc); + decoded_reg_strb.mbox_datain = cpuif_req_masked & (cpuif_addr == 6'h10); + decoded_reg_strb.mbox_dataout = cpuif_req_masked & (cpuif_addr == 6'h14); + decoded_reg_strb.mbox_execute = cpuif_req_masked & (cpuif_addr == 6'h18); + decoded_reg_strb.mbox_status = cpuif_req_masked & (cpuif_addr == 6'h1c); + decoded_reg_strb.mbox_unlock = cpuif_req_masked & (cpuif_addr == 6'h20); end // Pass down signals to next stage @@ -98,10 +100,6 @@ module mbox_csr ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -249,8 +247,10 @@ module mbox_csr ( // Field: mbox_csr.mbox_lock.lock always_comb begin - automatic logic [0:0] next_c = field_storage.mbox_lock.lock.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_lock.lock.value; + load_next_c = '0; if(hwif_in.mbox_lock.lock.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; @@ -263,7 +263,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_lock.lock.value <= 'h0; + field_storage.mbox_lock.lock.value <= 1'h0; end else if(field_combo.mbox_lock.lock.load_next) begin field_storage.mbox_lock.lock.value <= field_combo.mbox_lock.lock.next; end @@ -272,8 +272,10 @@ module mbox_csr ( assign hwif_out.mbox_lock.lock.swmod = decoded_reg_strb.mbox_lock && !decoded_req_is_wr; // Field: mbox_csr.mbox_user.user always_comb begin - automatic logic [31:0] next_c = field_storage.mbox_user.user.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_user.user.value; + load_next_c = '0; if(hwif_in.lock_set) begin // HW Write - we next_c = hwif_in.mbox_user.user.next; load_next_c = '1; @@ -283,7 +285,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_user.user.value <= 'h0; + field_storage.mbox_user.user.value <= 32'h0; end else if(field_combo.mbox_user.user.load_next) begin field_storage.mbox_user.user.value <= field_combo.mbox_user.user.next; end @@ -291,8 +293,10 @@ module mbox_csr ( assign hwif_out.mbox_user.user.value = field_storage.mbox_user.user.value; // Field: mbox_csr.mbox_cmd.command always_comb begin - automatic logic [31:0] next_c = field_storage.mbox_cmd.command.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_cmd.command.value; + load_next_c = '0; if(decoded_reg_strb.mbox_cmd && decoded_req_is_wr && hwif_in.valid_requester) begin // SW write next_c = (field_storage.mbox_cmd.command.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -302,7 +306,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_cmd.command.value <= 'h0; + field_storage.mbox_cmd.command.value <= 32'h0; end else if(field_combo.mbox_cmd.command.load_next) begin field_storage.mbox_cmd.command.value <= field_combo.mbox_cmd.command.next; end @@ -310,8 +314,10 @@ module mbox_csr ( assign hwif_out.mbox_cmd.command.swmod = decoded_reg_strb.mbox_cmd && decoded_req_is_wr; // Field: mbox_csr.mbox_dlen.length always_comb begin - automatic logic [31:0] next_c = field_storage.mbox_dlen.length.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_dlen.length.value; + load_next_c = '0; if(decoded_reg_strb.mbox_dlen && decoded_req_is_wr && hwif_in.valid_requester) begin // SW write next_c = (field_storage.mbox_dlen.length.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -321,7 +327,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_dlen.length.value <= 'h0; + field_storage.mbox_dlen.length.value <= 32'h0; end else if(field_combo.mbox_dlen.length.load_next) begin field_storage.mbox_dlen.length.value <= field_combo.mbox_dlen.length.next; end @@ -330,8 +336,10 @@ module mbox_csr ( assign hwif_out.mbox_dlen.length.swmod = decoded_reg_strb.mbox_dlen && decoded_req_is_wr; // Field: mbox_csr.mbox_datain.datain always_comb begin - automatic logic [31:0] next_c = field_storage.mbox_datain.datain.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_datain.datain.value; + load_next_c = '0; if(decoded_reg_strb.mbox_datain && decoded_req_is_wr && hwif_in.valid_requester) begin // SW write next_c = (field_storage.mbox_datain.datain.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -341,7 +349,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_datain.datain.value <= 'h0; + field_storage.mbox_datain.datain.value <= 32'h0; end else if(field_combo.mbox_datain.datain.load_next) begin field_storage.mbox_datain.datain.value <= field_combo.mbox_datain.datain.next; end @@ -349,8 +357,10 @@ module mbox_csr ( assign hwif_out.mbox_datain.datain.swmod = decoded_reg_strb.mbox_datain && decoded_req_is_wr; // Field: mbox_csr.mbox_dataout.dataout always_comb begin - automatic logic [31:0] next_c = field_storage.mbox_dataout.dataout.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_dataout.dataout.value; + load_next_c = '0; if(decoded_reg_strb.mbox_dataout && decoded_req_is_wr && hwif_in.mbox_dataout.dataout.swwe) begin // SW write next_c = (field_storage.mbox_dataout.dataout.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -363,7 +373,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_dataout.dataout.value <= 'h0; + field_storage.mbox_dataout.dataout.value <= 32'h0; end else if(field_combo.mbox_dataout.dataout.load_next) begin field_storage.mbox_dataout.dataout.value <= field_combo.mbox_dataout.dataout.next; end @@ -372,8 +382,10 @@ module mbox_csr ( assign hwif_out.mbox_dataout.dataout.swacc = decoded_reg_strb.mbox_dataout; // Field: mbox_csr.mbox_execute.execute always_comb begin - automatic logic [0:0] next_c = field_storage.mbox_execute.execute.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_execute.execute.value; + load_next_c = '0; if(hwif_in.mbox_execute.execute.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; @@ -386,7 +398,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_execute.execute.value <= 'h0; + field_storage.mbox_execute.execute.value <= 1'h0; end else if(field_combo.mbox_execute.execute.load_next) begin field_storage.mbox_execute.execute.value <= field_combo.mbox_execute.execute.next; end @@ -395,8 +407,10 @@ module mbox_csr ( assign hwif_out.mbox_execute.execute.swmod = decoded_reg_strb.mbox_execute && decoded_req_is_wr; // Field: mbox_csr.mbox_status.status always_comb begin - automatic logic [3:0] next_c = field_storage.mbox_status.status.value; - automatic logic load_next_c = '0; + automatic logic [3:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_status.status.value; + load_next_c = '0; if(hwif_in.mbox_status.status.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; @@ -409,7 +423,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_status.status.value <= 'h0; + field_storage.mbox_status.status.value <= 4'h0; end else if(field_combo.mbox_status.status.load_next) begin field_storage.mbox_status.status.value <= field_combo.mbox_status.status.next; end @@ -418,8 +432,10 @@ module mbox_csr ( assign hwif_out.mbox_status.status.swmod = decoded_reg_strb.mbox_status && decoded_req_is_wr; // Field: mbox_csr.mbox_status.ecc_single_error always_comb begin - automatic logic [0:0] next_c = field_storage.mbox_status.ecc_single_error.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_status.ecc_single_error.value; + load_next_c = '0; if(!field_storage.mbox_execute.execute.value) begin // HW Write - wel next_c = field_storage.mbox_execute.execute.value; load_next_c = '1; @@ -432,7 +448,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_status.ecc_single_error.value <= 'h0; + field_storage.mbox_status.ecc_single_error.value <= 1'h0; end else if(field_combo.mbox_status.ecc_single_error.load_next) begin field_storage.mbox_status.ecc_single_error.value <= field_combo.mbox_status.ecc_single_error.next; end @@ -440,8 +456,10 @@ module mbox_csr ( assign hwif_out.mbox_status.ecc_single_error.value = field_storage.mbox_status.ecc_single_error.value; // Field: mbox_csr.mbox_status.ecc_double_error always_comb begin - automatic logic [0:0] next_c = field_storage.mbox_status.ecc_double_error.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_status.ecc_double_error.value; + load_next_c = '0; if(!field_storage.mbox_execute.execute.value) begin // HW Write - wel next_c = field_storage.mbox_execute.execute.value; load_next_c = '1; @@ -454,7 +472,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_status.ecc_double_error.value <= 'h0; + field_storage.mbox_status.ecc_double_error.value <= 1'h0; end else if(field_combo.mbox_status.ecc_double_error.load_next) begin field_storage.mbox_status.ecc_double_error.value <= field_combo.mbox_status.ecc_double_error.next; end @@ -462,18 +480,20 @@ module mbox_csr ( assign hwif_out.mbox_status.ecc_double_error.value = field_storage.mbox_status.ecc_double_error.value; // Field: mbox_csr.mbox_status.mbox_fsm_ps always_comb begin - automatic logic [2:0] next_c = field_storage.mbox_status.mbox_fsm_ps.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.mbox_status.mbox_fsm_ps.next; - load_next_c = '1; - end + automatic logic [2:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_status.mbox_fsm_ps.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.mbox_status.mbox_fsm_ps.next; + load_next_c = '1; field_combo.mbox_status.mbox_fsm_ps.next = next_c; field_combo.mbox_status.mbox_fsm_ps.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_status.mbox_fsm_ps.value <= 'h0; + field_storage.mbox_status.mbox_fsm_ps.value <= 3'h0; end else if(field_combo.mbox_status.mbox_fsm_ps.load_next) begin field_storage.mbox_status.mbox_fsm_ps.value <= field_combo.mbox_status.mbox_fsm_ps.next; end @@ -481,18 +501,20 @@ module mbox_csr ( assign hwif_out.mbox_status.mbox_fsm_ps.value = field_storage.mbox_status.mbox_fsm_ps.value; // Field: mbox_csr.mbox_status.soc_has_lock always_comb begin - automatic logic [0:0] next_c = field_storage.mbox_status.soc_has_lock.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.mbox_status.soc_has_lock.next; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_status.soc_has_lock.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.mbox_status.soc_has_lock.next; + load_next_c = '1; field_combo.mbox_status.soc_has_lock.next = next_c; field_combo.mbox_status.soc_has_lock.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_status.soc_has_lock.value <= 'h0; + field_storage.mbox_status.soc_has_lock.value <= 1'h0; end else if(field_combo.mbox_status.soc_has_lock.load_next) begin field_storage.mbox_status.soc_has_lock.value <= field_combo.mbox_status.soc_has_lock.next; end @@ -500,18 +522,20 @@ module mbox_csr ( assign hwif_out.mbox_status.soc_has_lock.value = field_storage.mbox_status.soc_has_lock.value; // Field: mbox_csr.mbox_status.mbox_rdptr always_comb begin - automatic logic [14:0] next_c = field_storage.mbox_status.mbox_rdptr.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.mbox_status.mbox_rdptr.next; - load_next_c = '1; - end + automatic logic [14:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_status.mbox_rdptr.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.mbox_status.mbox_rdptr.next; + load_next_c = '1; field_combo.mbox_status.mbox_rdptr.next = next_c; field_combo.mbox_status.mbox_rdptr.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_status.mbox_rdptr.value <= 'h0; + field_storage.mbox_status.mbox_rdptr.value <= 15'h0; end else if(field_combo.mbox_status.mbox_rdptr.load_next) begin field_storage.mbox_status.mbox_rdptr.value <= field_combo.mbox_status.mbox_rdptr.next; end @@ -519,12 +543,14 @@ module mbox_csr ( assign hwif_out.mbox_status.mbox_rdptr.value = field_storage.mbox_status.mbox_rdptr.value; // Field: mbox_csr.mbox_unlock.unlock always_comb begin - automatic logic [0:0] next_c = field_storage.mbox_unlock.unlock.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_unlock.unlock.value; + load_next_c = '0; if(decoded_reg_strb.mbox_unlock && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.mbox_unlock.unlock.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -533,19 +559,28 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_unlock.unlock.value <= 'h0; + field_storage.mbox_unlock.unlock.value <= 1'h0; end else if(field_combo.mbox_unlock.unlock.load_next) begin field_storage.mbox_unlock.unlock.value <= field_combo.mbox_unlock.unlock.next; end end assign hwif_out.mbox_unlock.unlock.value = field_storage.mbox_unlock.unlock.value; + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [9-1:0][31:0] readback_array; assign readback_array[0][0:0] = (decoded_reg_strb.mbox_lock && !decoded_req_is_wr) ? field_storage.mbox_lock.lock.value : '0; @@ -583,4 +618,4 @@ module mbox_csr ( `CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.cptra_rst_b) -endmodule \ No newline at end of file +endmodule diff --git a/src/soc_ifc/rtl/mbox_csr_pkg.sv b/src/soc_ifc/rtl/mbox_csr_pkg.sv index 1c9766e24..39f775c03 100644 --- a/src/soc_ifc/rtl/mbox_csr_pkg.sv +++ b/src/soc_ifc/rtl/mbox_csr_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package mbox_csr_pkg; + + localparam MBOX_CSR_DATA_WIDTH = 32; + localparam MBOX_CSR_MIN_ADDR_WIDTH = 6; + typedef struct packed{ logic hwclr; } mbox_csr__mbox_lock__lock__in_t; @@ -38,35 +42,35 @@ package mbox_csr_pkg; typedef struct packed{ logic hwclr; - } mbox_csr__mbox_status__status__in_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__status__in_t; typedef struct packed{ logic hwset; - } mbox_csr__mbox_status__ecc_single_error_next_e066e214_wel_e066e214__in_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_single_error_next_e066e214_wel_e066e214__in_t; typedef struct packed{ logic hwset; - } mbox_csr__mbox_status__ecc_double_error_next_e066e214_wel_e066e214__in_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_double_error_next_e066e214_wel_e066e214__in_t; typedef struct packed{ logic [2:0] next; - } mbox_csr__mbox_status__mbox_fsm_ps__in_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_fsm_ps__in_t; typedef struct packed{ logic next; - } mbox_csr__mbox_status__soc_has_lock__in_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__soc_has_lock__in_t; typedef struct packed{ logic [14:0] next; - } mbox_csr__mbox_status__mbox_rdptr__in_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_rdptr__in_t; typedef struct packed{ - mbox_csr__mbox_status__status__in_t status; - mbox_csr__mbox_status__ecc_single_error_next_e066e214_wel_e066e214__in_t ecc_single_error; - mbox_csr__mbox_status__ecc_double_error_next_e066e214_wel_e066e214__in_t ecc_double_error; - mbox_csr__mbox_status__mbox_fsm_ps__in_t mbox_fsm_ps; - mbox_csr__mbox_status__soc_has_lock__in_t soc_has_lock; - mbox_csr__mbox_status__mbox_rdptr__in_t mbox_rdptr; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__status__in_t status; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_single_error_next_e066e214_wel_e066e214__in_t ecc_single_error; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_double_error_next_e066e214_wel_e066e214__in_t ecc_double_error; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_fsm_ps__in_t mbox_fsm_ps; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__soc_has_lock__in_t soc_has_lock; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_rdptr__in_t mbox_rdptr; } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__in_t; typedef struct packed{ @@ -145,35 +149,35 @@ package mbox_csr_pkg; typedef struct packed{ logic [3:0] value; logic swmod; - } mbox_csr__mbox_status__status__out_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__status__out_t; typedef struct packed{ logic value; - } mbox_csr__mbox_status__ecc_single_error_next_e066e214_wel_e066e214__out_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_single_error_next_e066e214_wel_e066e214__out_t; typedef struct packed{ logic value; - } mbox_csr__mbox_status__ecc_double_error_next_e066e214_wel_e066e214__out_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_double_error_next_e066e214_wel_e066e214__out_t; typedef struct packed{ logic [2:0] value; - } mbox_csr__mbox_status__mbox_fsm_ps__out_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_fsm_ps__out_t; typedef struct packed{ logic value; - } mbox_csr__mbox_status__soc_has_lock__out_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__soc_has_lock__out_t; typedef struct packed{ logic [14:0] value; - } mbox_csr__mbox_status__mbox_rdptr__out_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_rdptr__out_t; typedef struct packed{ - mbox_csr__mbox_status__status__out_t status; - mbox_csr__mbox_status__ecc_single_error_next_e066e214_wel_e066e214__out_t ecc_single_error; - mbox_csr__mbox_status__ecc_double_error_next_e066e214_wel_e066e214__out_t ecc_double_error; - mbox_csr__mbox_status__mbox_fsm_ps__out_t mbox_fsm_ps; - mbox_csr__mbox_status__soc_has_lock__out_t soc_has_lock; - mbox_csr__mbox_status__mbox_rdptr__out_t mbox_rdptr; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__status__out_t status; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_single_error_next_e066e214_wel_e066e214__out_t ecc_single_error; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_double_error_next_e066e214_wel_e066e214__out_t ecc_double_error; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_fsm_ps__out_t mbox_fsm_ps; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__soc_has_lock__out_t soc_has_lock; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_rdptr__out_t mbox_rdptr; } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__out_t; typedef struct packed{ @@ -196,6 +200,23 @@ package mbox_csr_pkg; mbox_csr__mbox_unlock__out_t mbox_unlock; } mbox_csr__out_t; + typedef enum logic [31:0] { + mbox_csr__mbox_status__status__mbox_status_e__CMD_BUSY = 'h0, + mbox_csr__mbox_status__status__mbox_status_e__DATA_READY = 'h1, + mbox_csr__mbox_status__status__mbox_status_e__CMD_COMPLETE = 'h2, + mbox_csr__mbox_status__status__mbox_status_e__CMD_FAILURE = 'h3 + } mbox_csr__mbox_status__status__mbox_status_e_e; + + typedef enum logic [31:0] { + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_IDLE = 'h0, + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_RDY_FOR_CMD = 'h1, + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_RDY_FOR_DLEN = 'h3, + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_RDY_FOR_DATA = 'h2, + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_EXECUTE_UC = 'h6, + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_EXECUTE_SOC = 'h4, + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_ERROR = 'h7 + } mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e_e; + localparam MBOX_CSR_ADDR_WIDTH = 32'd6; endpackage \ No newline at end of file diff --git a/src/soc_ifc/rtl/sha512_acc_csr.sv b/src/soc_ifc/rtl/sha512_acc_csr.sv index ce570fb8c..ba52bf8ec 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr.sv +++ b/src/soc_ifc/rtl/sha512_acc_csr.sv @@ -58,7 +58,9 @@ module sha512_acc_csr ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -103,37 +105,37 @@ module sha512_acc_csr ( logic [31:0] decoded_wr_biten; always_comb begin - decoded_reg_strb.LOCK = cpuif_req_masked & (cpuif_addr == 'h0); - decoded_reg_strb.USER = cpuif_req_masked & (cpuif_addr == 'h4); - decoded_reg_strb.MODE = cpuif_req_masked & (cpuif_addr == 'h8); - decoded_reg_strb.START_ADDRESS = cpuif_req_masked & (cpuif_addr == 'hc); - decoded_reg_strb.DLEN = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.DATAIN = cpuif_req_masked & (cpuif_addr == 'h14); - decoded_reg_strb.EXECUTE = cpuif_req_masked & (cpuif_addr == 'h18); - decoded_reg_strb.STATUS = cpuif_req_masked & (cpuif_addr == 'h1c); + decoded_reg_strb.LOCK = cpuif_req_masked & (cpuif_addr == 12'h0); + decoded_reg_strb.USER = cpuif_req_masked & (cpuif_addr == 12'h4); + decoded_reg_strb.MODE = cpuif_req_masked & (cpuif_addr == 12'h8); + decoded_reg_strb.START_ADDRESS = cpuif_req_masked & (cpuif_addr == 12'hc); + decoded_reg_strb.DLEN = cpuif_req_masked & (cpuif_addr == 12'h10); + decoded_reg_strb.DATAIN = cpuif_req_masked & (cpuif_addr == 12'h14); + decoded_reg_strb.EXECUTE = cpuif_req_masked & (cpuif_addr == 12'h18); + decoded_reg_strb.STATUS = cpuif_req_masked & (cpuif_addr == 12'h1c); for(int i0=0; i0<16; i0++) begin - decoded_reg_strb.DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 'h20 + i0*'h4); - end - decoded_reg_strb.CONTROL = cpuif_req_masked & (cpuif_addr == 'h60); - decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800); - decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804); - decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808); - decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h80c); - decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h810); - decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h814); - decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h818); - decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h81c); - decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h820); - decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h900); - decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h904); - decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h908); - decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h90c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980); - decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00); - decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04); - decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha08); - decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha0c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha10); + decoded_reg_strb.DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 12'h20 + i0*12'h4); + end + decoded_reg_strb.CONTROL = cpuif_req_masked & (cpuif_addr == 12'h60); + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h80c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h810); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h814); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h818); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h81c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h820); + decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h900); + decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h904); + decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h908); + decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h90c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h980); + decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha00); + decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha04); + decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha08); + decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha0c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha10); end // Pass down signals to next stage @@ -142,10 +144,6 @@ module sha512_acc_csr ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -586,8 +584,10 @@ module sha512_acc_csr ( // Field: sha512_acc_csr.LOCK.LOCK always_comb begin - automatic logic [0:0] next_c = field_storage.LOCK.LOCK.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.LOCK.LOCK.value; + load_next_c = '0; if(decoded_reg_strb.LOCK && !decoded_req_is_wr) begin // SW set on read next_c = '1; load_next_c = '1; @@ -600,7 +600,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.LOCK.LOCK.value <= 'h1; + field_storage.LOCK.LOCK.value <= 1'h1; end else if(field_combo.LOCK.LOCK.load_next) begin field_storage.LOCK.LOCK.value <= field_combo.LOCK.LOCK.next; end @@ -609,8 +609,10 @@ module sha512_acc_csr ( assign hwif_out.LOCK.LOCK.swmod = decoded_reg_strb.LOCK; // Field: sha512_acc_csr.USER.USER always_comb begin - automatic logic [31:0] next_c = field_storage.USER.USER.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.USER.USER.value; + load_next_c = '0; if(hwif_in.lock_set) begin // HW Write - we next_c = hwif_in.USER.USER.next; load_next_c = '1; @@ -620,7 +622,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.USER.USER.value <= 'h0; + field_storage.USER.USER.value <= 32'h0; end else if(field_combo.USER.USER.load_next) begin field_storage.USER.USER.value <= field_combo.USER.USER.next; end @@ -628,8 +630,10 @@ module sha512_acc_csr ( assign hwif_out.USER.USER.value = field_storage.USER.USER.value; // Field: sha512_acc_csr.MODE.MODE always_comb begin - automatic logic [1:0] next_c = field_storage.MODE.MODE.value; - automatic logic load_next_c = '0; + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MODE.MODE.value; + load_next_c = '0; if(decoded_reg_strb.MODE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write next_c = (field_storage.MODE.MODE.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); load_next_c = '1; @@ -639,7 +643,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.MODE.MODE.value <= 'h0; + field_storage.MODE.MODE.value <= 2'h0; end else if(field_combo.MODE.MODE.load_next) begin field_storage.MODE.MODE.value <= field_combo.MODE.MODE.next; end @@ -648,8 +652,10 @@ module sha512_acc_csr ( assign hwif_out.MODE.MODE.swmod = decoded_reg_strb.MODE && decoded_req_is_wr; // Field: sha512_acc_csr.MODE.ENDIAN_TOGGLE always_comb begin - automatic logic [0:0] next_c = field_storage.MODE.ENDIAN_TOGGLE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MODE.ENDIAN_TOGGLE.value; + load_next_c = '0; if(decoded_reg_strb.MODE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write next_c = (field_storage.MODE.ENDIAN_TOGGLE.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -659,7 +665,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.MODE.ENDIAN_TOGGLE.value <= 'h0; + field_storage.MODE.ENDIAN_TOGGLE.value <= 1'h0; end else if(field_combo.MODE.ENDIAN_TOGGLE.load_next) begin field_storage.MODE.ENDIAN_TOGGLE.value <= field_combo.MODE.ENDIAN_TOGGLE.next; end @@ -667,8 +673,10 @@ module sha512_acc_csr ( assign hwif_out.MODE.ENDIAN_TOGGLE.value = field_storage.MODE.ENDIAN_TOGGLE.value; // Field: sha512_acc_csr.START_ADDRESS.ADDR always_comb begin - automatic logic [31:0] next_c = field_storage.START_ADDRESS.ADDR.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.START_ADDRESS.ADDR.value; + load_next_c = '0; if(decoded_reg_strb.START_ADDRESS && decoded_req_is_wr && hwif_in.valid_user) begin // SW write next_c = (field_storage.START_ADDRESS.ADDR.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -678,7 +686,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.START_ADDRESS.ADDR.value <= 'h0; + field_storage.START_ADDRESS.ADDR.value <= 32'h0; end else if(field_combo.START_ADDRESS.ADDR.load_next) begin field_storage.START_ADDRESS.ADDR.value <= field_combo.START_ADDRESS.ADDR.next; end @@ -686,8 +694,10 @@ module sha512_acc_csr ( assign hwif_out.START_ADDRESS.ADDR.value = field_storage.START_ADDRESS.ADDR.value; // Field: sha512_acc_csr.DLEN.LENGTH always_comb begin - automatic logic [31:0] next_c = field_storage.DLEN.LENGTH.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DLEN.LENGTH.value; + load_next_c = '0; if(decoded_reg_strb.DLEN && decoded_req_is_wr && hwif_in.valid_user) begin // SW write next_c = (field_storage.DLEN.LENGTH.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -697,7 +707,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.DLEN.LENGTH.value <= 'h0; + field_storage.DLEN.LENGTH.value <= 32'h0; end else if(field_combo.DLEN.LENGTH.load_next) begin field_storage.DLEN.LENGTH.value <= field_combo.DLEN.LENGTH.next; end @@ -705,8 +715,10 @@ module sha512_acc_csr ( assign hwif_out.DLEN.LENGTH.value = field_storage.DLEN.LENGTH.value; // Field: sha512_acc_csr.DATAIN.DATAIN always_comb begin - automatic logic [31:0] next_c = field_storage.DATAIN.DATAIN.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DATAIN.DATAIN.value; + load_next_c = '0; if(decoded_reg_strb.DATAIN && decoded_req_is_wr && hwif_in.valid_user) begin // SW write next_c = (field_storage.DATAIN.DATAIN.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -716,7 +728,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.DATAIN.DATAIN.value <= 'h0; + field_storage.DATAIN.DATAIN.value <= 32'h0; end else if(field_combo.DATAIN.DATAIN.load_next) begin field_storage.DATAIN.DATAIN.value <= field_combo.DATAIN.DATAIN.next; end @@ -724,8 +736,10 @@ module sha512_acc_csr ( assign hwif_out.DATAIN.DATAIN.swmod = decoded_reg_strb.DATAIN && decoded_req_is_wr; // Field: sha512_acc_csr.EXECUTE.EXECUTE always_comb begin - automatic logic [0:0] next_c = field_storage.EXECUTE.EXECUTE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.EXECUTE.EXECUTE.value; + load_next_c = '0; if(decoded_reg_strb.EXECUTE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write next_c = (field_storage.EXECUTE.EXECUTE.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -738,7 +752,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.EXECUTE.EXECUTE.value <= 'h0; + field_storage.EXECUTE.EXECUTE.value <= 1'h0; end else if(field_combo.EXECUTE.EXECUTE.load_next) begin field_storage.EXECUTE.EXECUTE.value <= field_combo.EXECUTE.EXECUTE.next; end @@ -746,18 +760,20 @@ module sha512_acc_csr ( assign hwif_out.EXECUTE.EXECUTE.value = field_storage.EXECUTE.EXECUTE.value; // Field: sha512_acc_csr.STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.STATUS.VALID.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.STATUS.VALID.next; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.STATUS.VALID.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.STATUS.VALID.next; + load_next_c = '1; field_combo.STATUS.VALID.next = next_c; field_combo.STATUS.VALID.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.STATUS.VALID.value <= 'h0; + field_storage.STATUS.VALID.value <= 1'h0; end else if(field_combo.STATUS.VALID.load_next) begin field_storage.STATUS.VALID.value <= field_combo.STATUS.VALID.next; end @@ -765,18 +781,20 @@ module sha512_acc_csr ( assign hwif_out.STATUS.VALID.value = field_storage.STATUS.VALID.value; // Field: sha512_acc_csr.STATUS.SOC_HAS_LOCK always_comb begin - automatic logic [0:0] next_c = field_storage.STATUS.SOC_HAS_LOCK.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.STATUS.SOC_HAS_LOCK.next; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.STATUS.SOC_HAS_LOCK.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.STATUS.SOC_HAS_LOCK.next; + load_next_c = '1; field_combo.STATUS.SOC_HAS_LOCK.next = next_c; field_combo.STATUS.SOC_HAS_LOCK.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.STATUS.SOC_HAS_LOCK.value <= 'h0; + field_storage.STATUS.SOC_HAS_LOCK.value <= 1'h0; end else if(field_combo.STATUS.SOC_HAS_LOCK.load_next) begin field_storage.STATUS.SOC_HAS_LOCK.value <= field_combo.STATUS.SOC_HAS_LOCK.next; end @@ -785,21 +803,23 @@ module sha512_acc_csr ( for(genvar i0=0; i0<16; i0++) begin // Field: sha512_acc_csr.DIGEST[].DIGEST always_comb begin - automatic logic [31:0] next_c = field_storage.DIGEST[i0].DIGEST.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.DIGEST[i0].DIGEST.next; - load_next_c = '1; - end else if(hwif_in.DIGEST[i0].DIGEST.hwclr) begin // HW Clear + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DIGEST[i0].DIGEST.value; + load_next_c = '0; + if(hwif_in.DIGEST[i0].DIGEST.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; + end else begin // HW Write + next_c = hwif_in.DIGEST[i0].DIGEST.next; + load_next_c = '1; end field_combo.DIGEST[i0].DIGEST.next = next_c; field_combo.DIGEST[i0].DIGEST.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.DIGEST[i0].DIGEST.value <= 'h0; + field_storage.DIGEST[i0].DIGEST.value <= 32'h0; end else if(field_combo.DIGEST[i0].DIGEST.load_next) begin field_storage.DIGEST[i0].DIGEST.value <= field_combo.DIGEST[i0].DIGEST.next; end @@ -807,12 +827,14 @@ module sha512_acc_csr ( end // Field: sha512_acc_csr.CONTROL.ZEROIZE always_comb begin - automatic logic [0:0] next_c = field_storage.CONTROL.ZEROIZE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CONTROL.ZEROIZE.value; + load_next_c = '0; if(decoded_reg_strb.CONTROL && decoded_req_is_wr) begin // SW write next_c = (field_storage.CONTROL.ZEROIZE.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -821,7 +843,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CONTROL.ZEROIZE.value <= 'h0; + field_storage.CONTROL.ZEROIZE.value <= 1'h0; end else if(field_combo.CONTROL.ZEROIZE.load_next) begin field_storage.CONTROL.ZEROIZE.value <= field_combo.CONTROL.ZEROIZE.next; end @@ -829,8 +851,10 @@ module sha512_acc_csr ( assign hwif_out.CONTROL.ZEROIZE.value = field_storage.CONTROL.ZEROIZE.value; // Field: sha512_acc_csr.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -840,15 +864,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; end end // Field: sha512_acc_csr.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -858,15 +884,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_en_r.error0_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error0_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -876,15 +904,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error0_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= field_combo.intr_block_rf.error_intr_en_r.error0_en.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_en_r.error1_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error1_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -894,15 +924,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error1_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= field_combo.intr_block_rf.error_intr_en_r.error1_en.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_en_r.error2_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error2_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -912,15 +944,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error2_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= field_combo.intr_block_rf.error_intr_en_r.error2_en.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_en_r.error3_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error3_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -930,15 +964,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error3_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= field_combo.intr_block_rf.error_intr_en_r.error3_en.next; end end // Field: sha512_acc_csr.intr_block_rf.notif_intr_en_r.notif_cmd_done_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -948,25 +984,27 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.next; end end // Field: sha512_acc_csr.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; end @@ -975,18 +1013,20 @@ module sha512_acc_csr ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: sha512_acc_csr.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; end @@ -995,9 +1035,11 @@ module sha512_acc_csr ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: sha512_acc_csr.intr_block_rf.error_internal_intr_r.error0_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error0_sts.hwset) begin // HW Set @@ -1012,16 +1054,18 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error0_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error0_sts.next; end end // Field: sha512_acc_csr.intr_block_rf.error_internal_intr_r.error1_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error1_sts.hwset) begin // HW Set @@ -1036,16 +1080,18 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error1_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error1_sts.next; end end // Field: sha512_acc_csr.intr_block_rf.error_internal_intr_r.error2_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error2_sts.hwset) begin // HW Set @@ -1060,16 +1106,18 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error2_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error2_sts.next; end end // Field: sha512_acc_csr.intr_block_rf.error_internal_intr_r.error3_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error3_sts.hwset) begin // HW Set @@ -1084,7 +1132,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error3_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error3_sts.next; end @@ -1096,9 +1144,11 @@ module sha512_acc_csr ( || |(field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value & field_storage.intr_block_rf.error_intr_en_r.error3_en.value); // Field: sha512_acc_csr.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset) begin // HW Set @@ -1113,7 +1163,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.next; end @@ -1122,12 +1172,14 @@ module sha512_acc_csr ( |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value); // Field: sha512_acc_csr.intr_block_rf.error_intr_trig_r.error0_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1136,19 +1188,21 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error0_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error0_trig.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_trig_r.error1_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1157,19 +1211,21 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error1_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error1_trig.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_trig_r.error2_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1178,19 +1234,21 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error2_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error2_trig.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_trig_r.error3_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1199,19 +1257,21 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error3_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error3_trig.next; end end // Field: sha512_acc_csr.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1220,31 +1280,33 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.next; end end // Field: sha512_acc_csr.intr_block_rf.error0_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error0_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error0_intr_count_r.cnt.next = next_c; @@ -1252,31 +1314,33 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error0_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= field_combo.intr_block_rf.error0_intr_count_r.cnt.next; end end // Field: sha512_acc_csr.intr_block_rf.error1_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error1_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error1_intr_count_r.cnt.next = next_c; @@ -1284,31 +1348,33 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error1_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= field_combo.intr_block_rf.error1_intr_count_r.cnt.next; end end // Field: sha512_acc_csr.intr_block_rf.error2_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error2_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error2_intr_count_r.cnt.next = next_c; @@ -1316,31 +1382,33 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error2_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= field_combo.intr_block_rf.error2_intr_count_r.cnt.next; end end // Field: sha512_acc_csr.intr_block_rf.error3_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error3_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error3_intr_count_r.cnt.next = next_c; @@ -1348,31 +1416,33 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error3_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= field_combo.intr_block_rf.error3_intr_count_r.cnt.next; end end // Field: sha512_acc_csr.intr_block_rf.notif_cmd_done_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next = next_c; @@ -1380,15 +1450,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next; end end // Field: sha512_acc_csr.intr_block_rf.error0_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; @@ -1397,27 +1469,29 @@ module sha512_acc_csr ( load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next; end end // Field: sha512_acc_csr.intr_block_rf.error1_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; @@ -1426,27 +1500,29 @@ module sha512_acc_csr ( load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next; end end // Field: sha512_acc_csr.intr_block_rf.error2_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; @@ -1455,27 +1531,29 @@ module sha512_acc_csr ( load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next; end end // Field: sha512_acc_csr.intr_block_rf.error3_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; @@ -1484,27 +1562,29 @@ module sha512_acc_csr ( load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next; end end // Field: sha512_acc_csr.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; @@ -1513,30 +1593,39 @@ module sha512_acc_csr ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [44-1:0][31:0] readback_array; assign readback_array[0][0:0] = (decoded_reg_strb.LOCK && !decoded_req_is_wr) ? field_storage.LOCK.LOCK.value : '0; @@ -1618,4 +1707,4 @@ module sha512_acc_csr ( `CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.cptra_pwrgood) -endmodule \ No newline at end of file +endmodule diff --git a/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv b/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv index 6cb6af010..71e0470dd 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv +++ b/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package sha512_acc_csr_pkg; + + localparam SHA512_ACC_CSR_DATA_WIDTH = 32; + localparam SHA512_ACC_CSR_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic [31:0] next; } sha512_acc_csr__USER__USER__in_t; @@ -42,33 +46,33 @@ package sha512_acc_csr_pkg; typedef struct packed{ logic hwset; - } sha512_acc_csr__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t; + } sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } sha512_acc_csr__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t; + } sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } sha512_acc_csr__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t; + } sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } sha512_acc_csr__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t; + } sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t; typedef struct packed{ - sha512_acc_csr__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t error0_sts; - sha512_acc_csr__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t error1_sts; - sha512_acc_csr__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t error2_sts; - sha512_acc_csr__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t error3_sts; + sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t error0_sts; + sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t error1_sts; + sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t error2_sts; + sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t error3_sts; } sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__in_t; typedef struct packed{ logic hwset; - } sha512_acc_csr__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; + } sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; typedef struct packed{ - sha512_acc_csr__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; + sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; } sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e__in_t; typedef struct packed{ @@ -209,6 +213,13 @@ package sha512_acc_csr_pkg; sha512_acc_csr__intr_block_t__out_t intr_block_rf; } sha512_acc_csr__out_t; + typedef enum logic [31:0] { + sha512_acc_csr__MODE__MODE__sha_cmd_e__SHA_STREAM_384 = 'h0, + sha512_acc_csr__MODE__MODE__sha_cmd_e__SHA_STREAM_512 = 'h1, + sha512_acc_csr__MODE__MODE__sha_cmd_e__SHA_MBOX_384 = 'h2, + sha512_acc_csr__MODE__MODE__sha_cmd_e__SHA_MBOX_512 = 'h3 + } sha512_acc_csr__MODE__MODE__sha_cmd_e_e; + localparam SHA512_ACC_CSR_ADDR_WIDTH = 32'd12; endpackage \ No newline at end of file diff --git a/src/soc_ifc/rtl/sha512_acc_top.sv b/src/soc_ifc/rtl/sha512_acc_top.sv index 79b52410a..fbad8aa87 100644 --- a/src/soc_ifc/rtl/sha512_acc_top.sv +++ b/src/soc_ifc/rtl/sha512_acc_top.sv @@ -305,8 +305,8 @@ always_comb core_digest_valid_q = core_digest_valid & ~(init_reg | next_reg); always_comb mbox_start_addr = hwif_out.START_ADDRESS.ADDR.value[MBOX_ADDR_W+1:2]; always_comb mbox_ptr_round_up = (|hwif_out.DLEN.LENGTH.value[1:0]); //detect overflow of end address to indicate we want to read to the end of the mailbox - always_comb {mbox_read_to_end, mbox_end_addr} = mbox_ptr_round_up ? mbox_start_addr + (hwif_out.DLEN.LENGTH.value>>2) + 'd1 : - mbox_start_addr + (hwif_out.DLEN.LENGTH.value>>2); + always_comb {mbox_read_to_end, mbox_end_addr} = mbox_ptr_round_up ? mbox_start_addr + MBOX_ADDR_W'(hwif_out.DLEN.LENGTH.value>>2) + 1'b1 : + mbox_start_addr + MBOX_ADDR_W'(hwif_out.DLEN.LENGTH.value>>2); always_comb mbox_read_done = (sha_fsm_ps == SHA_IDLE) | ~mailbox_mode | //If the DLEN overflowed our end address, just read to the end of the mailbox and stop //Otherwise read until read pointer == end address diff --git a/src/soc_ifc/rtl/soc_ifc_reg.sv b/src/soc_ifc/rtl/soc_ifc_reg.sv index c5e84234e..ddf5a3d80 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg.sv @@ -58,7 +58,9 @@ module soc_ifc_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -179,149 +181,149 @@ module soc_ifc_reg ( logic [31:0] decoded_wr_biten; always_comb begin - decoded_reg_strb.CPTRA_HW_ERROR_FATAL = cpuif_req_masked & (cpuif_addr == 'h0); - decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL = cpuif_req_masked & (cpuif_addr == 'h4); - decoded_reg_strb.CPTRA_FW_ERROR_FATAL = cpuif_req_masked & (cpuif_addr == 'h8); - decoded_reg_strb.CPTRA_FW_ERROR_NON_FATAL = cpuif_req_masked & (cpuif_addr == 'hc); - decoded_reg_strb.CPTRA_HW_ERROR_ENC = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.CPTRA_FW_ERROR_ENC = cpuif_req_masked & (cpuif_addr == 'h14); + decoded_reg_strb.CPTRA_HW_ERROR_FATAL = cpuif_req_masked & (cpuif_addr == 12'h0); + decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL = cpuif_req_masked & (cpuif_addr == 12'h4); + decoded_reg_strb.CPTRA_FW_ERROR_FATAL = cpuif_req_masked & (cpuif_addr == 12'h8); + decoded_reg_strb.CPTRA_FW_ERROR_NON_FATAL = cpuif_req_masked & (cpuif_addr == 12'hc); + decoded_reg_strb.CPTRA_HW_ERROR_ENC = cpuif_req_masked & (cpuif_addr == 12'h10); + decoded_reg_strb.CPTRA_FW_ERROR_ENC = cpuif_req_masked & (cpuif_addr == 12'h14); for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.CPTRA_FW_EXTENDED_ERROR_INFO[i0] = cpuif_req_masked & (cpuif_addr == 'h18 + i0*'h4); + decoded_reg_strb.CPTRA_FW_EXTENDED_ERROR_INFO[i0] = cpuif_req_masked & (cpuif_addr == 12'h18 + i0*12'h4); end - decoded_reg_strb.CPTRA_BOOT_STATUS = cpuif_req_masked & (cpuif_addr == 'h38); - decoded_reg_strb.CPTRA_FLOW_STATUS = cpuif_req_masked & (cpuif_addr == 'h3c); - decoded_reg_strb.CPTRA_RESET_REASON = cpuif_req_masked & (cpuif_addr == 'h40); - decoded_reg_strb.CPTRA_SECURITY_STATE = cpuif_req_masked & (cpuif_addr == 'h44); + decoded_reg_strb.CPTRA_BOOT_STATUS = cpuif_req_masked & (cpuif_addr == 12'h38); + decoded_reg_strb.CPTRA_FLOW_STATUS = cpuif_req_masked & (cpuif_addr == 12'h3c); + decoded_reg_strb.CPTRA_RESET_REASON = cpuif_req_masked & (cpuif_addr == 12'h40); + decoded_reg_strb.CPTRA_SECURITY_STATE = cpuif_req_masked & (cpuif_addr == 12'h44); for(int i0=0; i0<5; i0++) begin - decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] = cpuif_req_masked & (cpuif_addr == 'h48 + i0*'h4); + decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] = cpuif_req_masked & (cpuif_addr == 12'h48 + i0*12'h4); end for(int i0=0; i0<5; i0++) begin - decoded_reg_strb.CPTRA_MBOX_PAUSER_LOCK[i0] = cpuif_req_masked & (cpuif_addr == 'h5c + i0*'h4); + decoded_reg_strb.CPTRA_MBOX_PAUSER_LOCK[i0] = cpuif_req_masked & (cpuif_addr == 12'h5c + i0*12'h4); end - decoded_reg_strb.CPTRA_TRNG_VALID_PAUSER = cpuif_req_masked & (cpuif_addr == 'h70); - decoded_reg_strb.CPTRA_TRNG_PAUSER_LOCK = cpuif_req_masked & (cpuif_addr == 'h74); + decoded_reg_strb.CPTRA_TRNG_VALID_PAUSER = cpuif_req_masked & (cpuif_addr == 12'h70); + decoded_reg_strb.CPTRA_TRNG_PAUSER_LOCK = cpuif_req_masked & (cpuif_addr == 12'h74); for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.CPTRA_TRNG_DATA[i0] = cpuif_req_masked & (cpuif_addr == 'h78 + i0*'h4); - end - decoded_reg_strb.CPTRA_TRNG_CTRL = cpuif_req_masked & (cpuif_addr == 'ha8); - decoded_reg_strb.CPTRA_TRNG_STATUS = cpuif_req_masked & (cpuif_addr == 'hac); - decoded_reg_strb.CPTRA_FUSE_WR_DONE = cpuif_req_masked & (cpuif_addr == 'hb0); - decoded_reg_strb.CPTRA_TIMER_CONFIG = cpuif_req_masked & (cpuif_addr == 'hb4); - decoded_reg_strb.CPTRA_BOOTFSM_GO = cpuif_req_masked & (cpuif_addr == 'hb8); - decoded_reg_strb.CPTRA_DBG_MANUF_SERVICE_REG = cpuif_req_masked & (cpuif_addr == 'hbc); - decoded_reg_strb.CPTRA_CLK_GATING_EN = cpuif_req_masked & (cpuif_addr == 'hc0); + decoded_reg_strb.CPTRA_TRNG_DATA[i0] = cpuif_req_masked & (cpuif_addr == 12'h78 + i0*12'h4); + end + decoded_reg_strb.CPTRA_TRNG_CTRL = cpuif_req_masked & (cpuif_addr == 12'ha8); + decoded_reg_strb.CPTRA_TRNG_STATUS = cpuif_req_masked & (cpuif_addr == 12'hac); + decoded_reg_strb.CPTRA_FUSE_WR_DONE = cpuif_req_masked & (cpuif_addr == 12'hb0); + decoded_reg_strb.CPTRA_TIMER_CONFIG = cpuif_req_masked & (cpuif_addr == 12'hb4); + decoded_reg_strb.CPTRA_BOOTFSM_GO = cpuif_req_masked & (cpuif_addr == 12'hb8); + decoded_reg_strb.CPTRA_DBG_MANUF_SERVICE_REG = cpuif_req_masked & (cpuif_addr == 12'hbc); + decoded_reg_strb.CPTRA_CLK_GATING_EN = cpuif_req_masked & (cpuif_addr == 12'hc0); for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_GENERIC_INPUT_WIRES[i0] = cpuif_req_masked & (cpuif_addr == 'hc4 + i0*'h4); + decoded_reg_strb.CPTRA_GENERIC_INPUT_WIRES[i0] = cpuif_req_masked & (cpuif_addr == 12'hc4 + i0*12'h4); end for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_GENERIC_OUTPUT_WIRES[i0] = cpuif_req_masked & (cpuif_addr == 'hcc + i0*'h4); + decoded_reg_strb.CPTRA_GENERIC_OUTPUT_WIRES[i0] = cpuif_req_masked & (cpuif_addr == 12'hcc + i0*12'h4); end - decoded_reg_strb.CPTRA_HW_REV_ID = cpuif_req_masked & (cpuif_addr == 'hd4); + decoded_reg_strb.CPTRA_HW_REV_ID = cpuif_req_masked & (cpuif_addr == 12'hd4); for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_FW_REV_ID[i0] = cpuif_req_masked & (cpuif_addr == 'hd8 + i0*'h4); + decoded_reg_strb.CPTRA_FW_REV_ID[i0] = cpuif_req_masked & (cpuif_addr == 12'hd8 + i0*12'h4); end - decoded_reg_strb.CPTRA_HW_CONFIG = cpuif_req_masked & (cpuif_addr == 'he0); - decoded_reg_strb.CPTRA_WDT_TIMER1_EN = cpuif_req_masked & (cpuif_addr == 'he4); - decoded_reg_strb.CPTRA_WDT_TIMER1_CTRL = cpuif_req_masked & (cpuif_addr == 'he8); + decoded_reg_strb.CPTRA_HW_CONFIG = cpuif_req_masked & (cpuif_addr == 12'he0); + decoded_reg_strb.CPTRA_WDT_TIMER1_EN = cpuif_req_masked & (cpuif_addr == 12'he4); + decoded_reg_strb.CPTRA_WDT_TIMER1_CTRL = cpuif_req_masked & (cpuif_addr == 12'he8); for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 'hec + i0*'h4); + decoded_reg_strb.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 12'hec + i0*12'h4); end - decoded_reg_strb.CPTRA_WDT_TIMER2_EN = cpuif_req_masked & (cpuif_addr == 'hf4); - decoded_reg_strb.CPTRA_WDT_TIMER2_CTRL = cpuif_req_masked & (cpuif_addr == 'hf8); + decoded_reg_strb.CPTRA_WDT_TIMER2_EN = cpuif_req_masked & (cpuif_addr == 12'hf4); + decoded_reg_strb.CPTRA_WDT_TIMER2_CTRL = cpuif_req_masked & (cpuif_addr == 12'hf8); for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 'hfc + i0*'h4); + decoded_reg_strb.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 12'hfc + i0*12'h4); end - decoded_reg_strb.CPTRA_WDT_STATUS = cpuif_req_masked & (cpuif_addr == 'h104); - decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER = cpuif_req_masked & (cpuif_addr == 'h108); - decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK = cpuif_req_masked & (cpuif_addr == 'h10c); + decoded_reg_strb.CPTRA_WDT_STATUS = cpuif_req_masked & (cpuif_addr == 12'h104); + decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER = cpuif_req_masked & (cpuif_addr == 12'h108); + decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK = cpuif_req_masked & (cpuif_addr == 12'h10c); for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_WDT_CFG[i0] = cpuif_req_masked & (cpuif_addr == 'h110 + i0*'h4); + decoded_reg_strb.CPTRA_WDT_CFG[i0] = cpuif_req_masked & (cpuif_addr == 12'h110 + i0*12'h4); end - decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_0 = cpuif_req_masked & (cpuif_addr == 'h118); - decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_1 = cpuif_req_masked & (cpuif_addr == 'h11c); + decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_0 = cpuif_req_masked & (cpuif_addr == 12'h118); + decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_1 = cpuif_req_masked & (cpuif_addr == 12'h11c); for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_RSVD_REG[i0] = cpuif_req_masked & (cpuif_addr == 'h120 + i0*'h4); + decoded_reg_strb.CPTRA_RSVD_REG[i0] = cpuif_req_masked & (cpuif_addr == 12'h120 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.fuse_uds_seed[i0] = cpuif_req_masked & (cpuif_addr == 'h200 + i0*'h4); + decoded_reg_strb.fuse_uds_seed[i0] = cpuif_req_masked & (cpuif_addr == 12'h200 + i0*12'h4); end for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.fuse_field_entropy[i0] = cpuif_req_masked & (cpuif_addr == 'h230 + i0*'h4); + decoded_reg_strb.fuse_field_entropy[i0] = cpuif_req_masked & (cpuif_addr == 12'h230 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.fuse_key_manifest_pk_hash[i0] = cpuif_req_masked & (cpuif_addr == 'h250 + i0*'h4); + decoded_reg_strb.fuse_key_manifest_pk_hash[i0] = cpuif_req_masked & (cpuif_addr == 12'h250 + i0*12'h4); end - decoded_reg_strb.fuse_key_manifest_pk_hash_mask = cpuif_req_masked & (cpuif_addr == 'h280); + decoded_reg_strb.fuse_key_manifest_pk_hash_mask = cpuif_req_masked & (cpuif_addr == 12'h280); for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.fuse_owner_pk_hash[i0] = cpuif_req_masked & (cpuif_addr == 'h284 + i0*'h4); + decoded_reg_strb.fuse_owner_pk_hash[i0] = cpuif_req_masked & (cpuif_addr == 12'h284 + i0*12'h4); end - decoded_reg_strb.fuse_fmc_key_manifest_svn = cpuif_req_masked & (cpuif_addr == 'h2b4); + decoded_reg_strb.fuse_fmc_key_manifest_svn = cpuif_req_masked & (cpuif_addr == 12'h2b4); for(int i0=0; i0<4; i0++) begin - decoded_reg_strb.fuse_runtime_svn[i0] = cpuif_req_masked & (cpuif_addr == 'h2b8 + i0*'h4); + decoded_reg_strb.fuse_runtime_svn[i0] = cpuif_req_masked & (cpuif_addr == 12'h2b8 + i0*12'h4); end - decoded_reg_strb.fuse_anti_rollback_disable = cpuif_req_masked & (cpuif_addr == 'h2c8); + decoded_reg_strb.fuse_anti_rollback_disable = cpuif_req_masked & (cpuif_addr == 12'h2c8); for(int i0=0; i0<24; i0++) begin - decoded_reg_strb.fuse_idevid_cert_attr[i0] = cpuif_req_masked & (cpuif_addr == 'h2cc + i0*'h4); + decoded_reg_strb.fuse_idevid_cert_attr[i0] = cpuif_req_masked & (cpuif_addr == 12'h2cc + i0*12'h4); end for(int i0=0; i0<4; i0++) begin - decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] = cpuif_req_masked & (cpuif_addr == 'h32c + i0*'h4); + decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] = cpuif_req_masked & (cpuif_addr == 12'h32c + i0*12'h4); end - decoded_reg_strb.fuse_life_cycle = cpuif_req_masked & (cpuif_addr == 'h33c); - decoded_reg_strb.fuse_lms_verify = cpuif_req_masked & (cpuif_addr == 'h340); - decoded_reg_strb.fuse_lms_revocation = cpuif_req_masked & (cpuif_addr == 'h344); - decoded_reg_strb.fuse_soc_stepping_id = cpuif_req_masked & (cpuif_addr == 'h348); + decoded_reg_strb.fuse_life_cycle = cpuif_req_masked & (cpuif_addr == 12'h33c); + decoded_reg_strb.fuse_lms_verify = cpuif_req_masked & (cpuif_addr == 12'h340); + decoded_reg_strb.fuse_lms_revocation = cpuif_req_masked & (cpuif_addr == 12'h344); + decoded_reg_strb.fuse_soc_stepping_id = cpuif_req_masked & (cpuif_addr == 12'h348); for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.internal_obf_key[i0] = cpuif_req_masked & (cpuif_addr == 'h600 + i0*'h4); - end - decoded_reg_strb.internal_iccm_lock = cpuif_req_masked & (cpuif_addr == 'h620); - decoded_reg_strb.internal_fw_update_reset = cpuif_req_masked & (cpuif_addr == 'h624); - decoded_reg_strb.internal_fw_update_reset_wait_cycles = cpuif_req_masked & (cpuif_addr == 'h628); - decoded_reg_strb.internal_nmi_vector = cpuif_req_masked & (cpuif_addr == 'h62c); - decoded_reg_strb.internal_hw_error_fatal_mask = cpuif_req_masked & (cpuif_addr == 'h630); - decoded_reg_strb.internal_hw_error_non_fatal_mask = cpuif_req_masked & (cpuif_addr == 'h634); - decoded_reg_strb.internal_fw_error_fatal_mask = cpuif_req_masked & (cpuif_addr == 'h638); - decoded_reg_strb.internal_fw_error_non_fatal_mask = cpuif_req_masked & (cpuif_addr == 'h63c); - decoded_reg_strb.internal_rv_mtime_l = cpuif_req_masked & (cpuif_addr == 'h640); - decoded_reg_strb.internal_rv_mtime_h = cpuif_req_masked & (cpuif_addr == 'h644); - decoded_reg_strb.internal_rv_mtimecmp_l = cpuif_req_masked & (cpuif_addr == 'h648); - decoded_reg_strb.internal_rv_mtimecmp_h = cpuif_req_masked & (cpuif_addr == 'h64c); - decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800); - decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804); - decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808); - decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h80c); - decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h810); - decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h814); - decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h818); - decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h81c); - decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h820); - decoded_reg_strb.intr_block_rf.error_internal_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h900); - decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h904); - decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h908); - decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h90c); - decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h910); - decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h914); - decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h918); - decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h91c); - decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980); - decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h984); - decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h988); - decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h98c); - decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h990); - decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h994); - decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00); - decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04); - decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha08); - decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha0c); - decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha10); - decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha14); - decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha18); - decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha1c); - decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha20); - decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha24); - decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha28); - decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha2c); - decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha30); - decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha34); + decoded_reg_strb.internal_obf_key[i0] = cpuif_req_masked & (cpuif_addr == 12'h600 + i0*12'h4); + end + decoded_reg_strb.internal_iccm_lock = cpuif_req_masked & (cpuif_addr == 12'h620); + decoded_reg_strb.internal_fw_update_reset = cpuif_req_masked & (cpuif_addr == 12'h624); + decoded_reg_strb.internal_fw_update_reset_wait_cycles = cpuif_req_masked & (cpuif_addr == 12'h628); + decoded_reg_strb.internal_nmi_vector = cpuif_req_masked & (cpuif_addr == 12'h62c); + decoded_reg_strb.internal_hw_error_fatal_mask = cpuif_req_masked & (cpuif_addr == 12'h630); + decoded_reg_strb.internal_hw_error_non_fatal_mask = cpuif_req_masked & (cpuif_addr == 12'h634); + decoded_reg_strb.internal_fw_error_fatal_mask = cpuif_req_masked & (cpuif_addr == 12'h638); + decoded_reg_strb.internal_fw_error_non_fatal_mask = cpuif_req_masked & (cpuif_addr == 12'h63c); + decoded_reg_strb.internal_rv_mtime_l = cpuif_req_masked & (cpuif_addr == 12'h640); + decoded_reg_strb.internal_rv_mtime_h = cpuif_req_masked & (cpuif_addr == 12'h644); + decoded_reg_strb.internal_rv_mtimecmp_l = cpuif_req_masked & (cpuif_addr == 12'h648); + decoded_reg_strb.internal_rv_mtimecmp_h = cpuif_req_masked & (cpuif_addr == 12'h64c); + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h80c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h810); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h814); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h818); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h81c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h820); + decoded_reg_strb.intr_block_rf.error_internal_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h900); + decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h904); + decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h908); + decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h90c); + decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h910); + decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h914); + decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h918); + decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h91c); + decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h980); + decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h984); + decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h988); + decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h98c); + decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h990); + decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h994); + decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha00); + decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha04); + decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha08); + decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha0c); + decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha10); + decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha14); + decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha18); + decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha1c); + decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha20); + decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha24); + decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha28); + decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha2c); + decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha30); + decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha34); end // Pass down signals to next stage @@ -330,10 +332,6 @@ module soc_ifc_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -1911,8 +1909,10 @@ module soc_ifc_reg ( // Field: soc_ifc_reg.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_FATAL && decoded_req_is_wr) begin // SW write 1 clear next_c = field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value & ~(decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1925,7 +1925,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value <= 'h0; + field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value <= 1'h0; end else if(field_combo.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.load_next) begin field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value <= field_combo.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.next; end @@ -1933,8 +1933,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value = field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value; // Field: soc_ifc_reg.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_FATAL && decoded_req_is_wr) begin // SW write 1 clear next_c = field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value & ~(decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -1947,7 +1949,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value <= 'h0; + field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value <= 1'h0; end else if(field_combo.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.load_next) begin field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value <= field_combo.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.next; end @@ -1955,8 +1957,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value = field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value; // Field: soc_ifc_reg.CPTRA_HW_ERROR_FATAL.nmi_pin always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_FATAL && decoded_req_is_wr) begin // SW write 1 clear next_c = field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value & ~(decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -1969,7 +1973,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value <= 'h0; + field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value <= 1'h0; end else if(field_combo.CPTRA_HW_ERROR_FATAL.nmi_pin.load_next) begin field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value <= field_combo.CPTRA_HW_ERROR_FATAL.nmi_pin.next; end @@ -1977,8 +1981,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_FATAL.nmi_pin.value = field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value; // Field: soc_ifc_reg.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && decoded_req_is_wr) begin // SW write 1 clear next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value & ~(decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1991,7 +1997,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value <= 'h0; + field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value <= 1'h0; end else if(field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.load_next) begin field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value <= field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.next; end @@ -1999,8 +2005,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value; // Field: soc_ifc_reg.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && decoded_req_is_wr) begin // SW write 1 clear next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value & ~(decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -2013,7 +2021,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value <= 'h0; + field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value <= 1'h0; end else if(field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.load_next) begin field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value <= field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.next; end @@ -2021,8 +2029,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value; // Field: soc_ifc_reg.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && decoded_req_is_wr) begin // SW write 1 clear next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value & ~(decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -2035,7 +2045,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value <= 'h0; + field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value <= 1'h0; end else if(field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.load_next) begin field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value <= field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.next; end @@ -2043,8 +2053,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value; // Field: soc_ifc_reg.CPTRA_FW_ERROR_FATAL.error_code always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_FW_ERROR_FATAL.error_code.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FW_ERROR_FATAL.error_code.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FW_ERROR_FATAL && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_FW_ERROR_FATAL.error_code.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2057,7 +2069,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FW_ERROR_FATAL.error_code.value <= 'h0; + field_storage.CPTRA_FW_ERROR_FATAL.error_code.value <= 32'h0; end else if(field_combo.CPTRA_FW_ERROR_FATAL.error_code.load_next) begin field_storage.CPTRA_FW_ERROR_FATAL.error_code.value <= field_combo.CPTRA_FW_ERROR_FATAL.error_code.next; end @@ -2066,8 +2078,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FW_ERROR_FATAL.error_code.swmod = decoded_reg_strb.CPTRA_FW_ERROR_FATAL && decoded_req_is_wr; // Field: soc_ifc_reg.CPTRA_FW_ERROR_NON_FATAL.error_code always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FW_ERROR_NON_FATAL && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2080,7 +2094,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value <= 'h0; + field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value <= 32'h0; end else if(field_combo.CPTRA_FW_ERROR_NON_FATAL.error_code.load_next) begin field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value <= field_combo.CPTRA_FW_ERROR_NON_FATAL.error_code.next; end @@ -2089,8 +2103,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FW_ERROR_NON_FATAL.error_code.swmod = decoded_reg_strb.CPTRA_FW_ERROR_NON_FATAL && decoded_req_is_wr; // Field: soc_ifc_reg.CPTRA_HW_ERROR_ENC.error_code always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_HW_ERROR_ENC.error_code.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_ENC.error_code.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_ENC && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_HW_ERROR_ENC.error_code.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2100,7 +2116,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_ENC.error_code.value <= 'h0; + field_storage.CPTRA_HW_ERROR_ENC.error_code.value <= 32'h0; end else if(field_combo.CPTRA_HW_ERROR_ENC.error_code.load_next) begin field_storage.CPTRA_HW_ERROR_ENC.error_code.value <= field_combo.CPTRA_HW_ERROR_ENC.error_code.next; end @@ -2108,8 +2124,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_ENC.error_code.value = field_storage.CPTRA_HW_ERROR_ENC.error_code.value; // Field: soc_ifc_reg.CPTRA_FW_ERROR_ENC.error_code always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_FW_ERROR_ENC.error_code.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FW_ERROR_ENC.error_code.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FW_ERROR_ENC && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_FW_ERROR_ENC.error_code.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2119,7 +2137,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FW_ERROR_ENC.error_code.value <= 'h0; + field_storage.CPTRA_FW_ERROR_ENC.error_code.value <= 32'h0; end else if(field_combo.CPTRA_FW_ERROR_ENC.error_code.load_next) begin field_storage.CPTRA_FW_ERROR_ENC.error_code.value <= field_combo.CPTRA_FW_ERROR_ENC.error_code.next; end @@ -2128,8 +2146,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: soc_ifc_reg.CPTRA_FW_EXTENDED_ERROR_INFO[].error_info always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FW_EXTENDED_ERROR_INFO[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2139,7 +2159,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.value <= 'h0; + field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.value <= 32'h0; end else if(field_combo.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.load_next) begin field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.value <= field_combo.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.next; end @@ -2148,8 +2168,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_BOOT_STATUS.status always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_BOOT_STATUS.status.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_BOOT_STATUS.status.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_BOOT_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_BOOT_STATUS.status.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2159,7 +2181,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_BOOT_STATUS.status.value <= 'h0; + field_storage.CPTRA_BOOT_STATUS.status.value <= 32'h0; end else if(field_combo.CPTRA_BOOT_STATUS.status.load_next) begin field_storage.CPTRA_BOOT_STATUS.status.value <= field_combo.CPTRA_BOOT_STATUS.status.next; end @@ -2167,8 +2189,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_BOOT_STATUS.status.value = field_storage.CPTRA_BOOT_STATUS.status.value; // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.status always_comb begin - automatic logic [23:0] next_c = field_storage.CPTRA_FLOW_STATUS.status.value; - automatic logic load_next_c = '0; + automatic logic [23:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FLOW_STATUS.status.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_FLOW_STATUS.status.value & ~decoded_wr_biten[23:0]) | (decoded_wr_data[23:0] & decoded_wr_biten[23:0]); load_next_c = '1; @@ -2178,15 +2202,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_FLOW_STATUS.status.value <= 'h0; + field_storage.CPTRA_FLOW_STATUS.status.value <= 24'h0; end else if(field_combo.CPTRA_FLOW_STATUS.status.load_next) begin field_storage.CPTRA_FLOW_STATUS.status.value <= field_combo.CPTRA_FLOW_STATUS.status.next; end end // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.idevid_csr_ready always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value & ~decoded_wr_biten[24:24]) | (decoded_wr_data[24:24] & decoded_wr_biten[24:24]); load_next_c = '1; @@ -2196,7 +2222,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value <= 'h0; + field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value <= 1'h0; end else if(field_combo.CPTRA_FLOW_STATUS.idevid_csr_ready.load_next) begin field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value <= field_combo.CPTRA_FLOW_STATUS.idevid_csr_ready.next; end @@ -2204,8 +2230,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FLOW_STATUS.idevid_csr_ready.value = field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value; // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.ready_for_fw always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value & ~decoded_wr_biten[28:28]) | (decoded_wr_data[28:28] & decoded_wr_biten[28:28]); load_next_c = '1; @@ -2215,7 +2243,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value <= 'h0; + field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value <= 1'h0; end else if(field_combo.CPTRA_FLOW_STATUS.ready_for_fw.load_next) begin field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value <= field_combo.CPTRA_FLOW_STATUS.ready_for_fw.next; end @@ -2223,8 +2251,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FLOW_STATUS.ready_for_fw.value = field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value; // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.ready_for_runtime always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value & ~decoded_wr_biten[29:29]) | (decoded_wr_data[29:29] & decoded_wr_biten[29:29]); load_next_c = '1; @@ -2234,7 +2264,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value <= 'h0; + field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value <= 1'h0; end else if(field_combo.CPTRA_FLOW_STATUS.ready_for_runtime.load_next) begin field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value <= field_combo.CPTRA_FLOW_STATUS.ready_for_runtime.next; end @@ -2242,8 +2272,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FLOW_STATUS.ready_for_runtime.value = field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value; // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.mailbox_flow_done always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value & ~decoded_wr_biten[31:31]) | (decoded_wr_data[31:31] & decoded_wr_biten[31:31]); load_next_c = '1; @@ -2253,7 +2285,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value <= 'h0; + field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value <= 1'h0; end else if(field_combo.CPTRA_FLOW_STATUS.mailbox_flow_done.load_next) begin field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value <= field_combo.CPTRA_FLOW_STATUS.mailbox_flow_done.next; end @@ -2261,8 +2293,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FLOW_STATUS.mailbox_flow_done.value = field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value; // Field: soc_ifc_reg.CPTRA_RESET_REASON.FW_UPD_RESET always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_RESET_REASON.FW_UPD_RESET.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_RESET_REASON.FW_UPD_RESET.value; + load_next_c = '0; if(hwif_in.CPTRA_RESET_REASON.FW_UPD_RESET.we) begin // HW Write - we next_c = hwif_in.CPTRA_RESET_REASON.FW_UPD_RESET.next; load_next_c = '1; @@ -2272,7 +2306,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_RESET_REASON.FW_UPD_RESET.value <= 'h0; + field_storage.CPTRA_RESET_REASON.FW_UPD_RESET.value <= 1'h0; end else if(field_combo.CPTRA_RESET_REASON.FW_UPD_RESET.load_next) begin field_storage.CPTRA_RESET_REASON.FW_UPD_RESET.value <= field_combo.CPTRA_RESET_REASON.FW_UPD_RESET.next; end @@ -2280,18 +2314,20 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_RESET_REASON.FW_UPD_RESET.value = field_storage.CPTRA_RESET_REASON.FW_UPD_RESET.value; // Field: soc_ifc_reg.CPTRA_RESET_REASON.WARM_RESET always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_RESET_REASON.WARM_RESET.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.CPTRA_RESET_REASON.WARM_RESET.next; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_RESET_REASON.WARM_RESET.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.CPTRA_RESET_REASON.WARM_RESET.next; + load_next_c = '1; field_combo.CPTRA_RESET_REASON.WARM_RESET.next = next_c; field_combo.CPTRA_RESET_REASON.WARM_RESET.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_RESET_REASON.WARM_RESET.value <= 'h0; + field_storage.CPTRA_RESET_REASON.WARM_RESET.value <= 1'h0; end else if(field_combo.CPTRA_RESET_REASON.WARM_RESET.load_next) begin field_storage.CPTRA_RESET_REASON.WARM_RESET.value <= field_combo.CPTRA_RESET_REASON.WARM_RESET.next; end @@ -2300,8 +2336,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<5; i0++) begin // Field: soc_ifc_reg.CPTRA_MBOX_VALID_PAUSER[].PAUSER always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.swwel)) begin // SW write next_c = (field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2311,7 +2349,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value <= 'hffffffff; + field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value <= 32'hffffffff; end else if(field_combo.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.load_next) begin field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value <= field_combo.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.next; end @@ -2321,8 +2359,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<5; i0++) begin // Field: soc_ifc_reg.CPTRA_MBOX_PAUSER_LOCK[].LOCK always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_MBOX_PAUSER_LOCK[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.swwel)) begin // SW write next_c = (field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2332,7 +2372,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value <= 'h0; + field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value <= 1'h0; end else if(field_combo.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.load_next) begin field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value <= field_combo.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.next; end @@ -2341,8 +2381,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_TRNG_VALID_PAUSER.PAUSER always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TRNG_VALID_PAUSER && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_VALID_PAUSER.PAUSER.swwel)) begin // SW write next_c = (field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2352,7 +2394,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value <= 'hffffffff; + field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value <= 32'hffffffff; end else if(field_combo.CPTRA_TRNG_VALID_PAUSER.PAUSER.load_next) begin field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value <= field_combo.CPTRA_TRNG_VALID_PAUSER.PAUSER.next; end @@ -2360,8 +2402,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_TRNG_VALID_PAUSER.PAUSER.value = field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value; // Field: soc_ifc_reg.CPTRA_TRNG_PAUSER_LOCK.LOCK always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TRNG_PAUSER_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_PAUSER_LOCK.LOCK.swwel)) begin // SW write next_c = (field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2371,7 +2415,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value <= 'h0; + field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value <= 1'h0; end else if(field_combo.CPTRA_TRNG_PAUSER_LOCK.LOCK.load_next) begin field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value <= field_combo.CPTRA_TRNG_PAUSER_LOCK.LOCK.next; end @@ -2380,8 +2424,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: soc_ifc_reg.CPTRA_TRNG_DATA[].DATA always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_TRNG_DATA[i0].DATA.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TRNG_DATA[i0].DATA.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TRNG_DATA[i0] && decoded_req_is_wr && hwif_in.CPTRA_TRNG_DATA[i0].DATA.swwe) begin // SW write next_c = (field_storage.CPTRA_TRNG_DATA[i0].DATA.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2394,7 +2440,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_DATA[i0].DATA.value <= 'h0; + field_storage.CPTRA_TRNG_DATA[i0].DATA.value <= 32'h0; end else if(field_combo.CPTRA_TRNG_DATA[i0].DATA.load_next) begin field_storage.CPTRA_TRNG_DATA[i0].DATA.value <= field_combo.CPTRA_TRNG_DATA[i0].DATA.next; end @@ -2403,12 +2449,14 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_TRNG_CTRL.clear always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_TRNG_CTRL.clear.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TRNG_CTRL.clear.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TRNG_CTRL && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_TRNG_CTRL.clear.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -2417,7 +2465,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_CTRL.clear.value <= 'h0; + field_storage.CPTRA_TRNG_CTRL.clear.value <= 1'h0; end else if(field_combo.CPTRA_TRNG_CTRL.clear.load_next) begin field_storage.CPTRA_TRNG_CTRL.clear.value <= field_combo.CPTRA_TRNG_CTRL.clear.next; end @@ -2425,8 +2473,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_TRNG_CTRL.clear.value = field_storage.CPTRA_TRNG_CTRL.clear.value; // Field: soc_ifc_reg.CPTRA_TRNG_STATUS.DATA_REQ always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TRNG_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2436,7 +2486,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value <= 'h0; + field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value <= 1'h0; end else if(field_combo.CPTRA_TRNG_STATUS.DATA_REQ.load_next) begin field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value <= field_combo.CPTRA_TRNG_STATUS.DATA_REQ.next; end @@ -2444,8 +2494,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_TRNG_STATUS.DATA_REQ.value = field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value; // Field: soc_ifc_reg.CPTRA_TRNG_STATUS.DATA_WR_DONE always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TRNG_STATUS && decoded_req_is_wr && hwif_in.CPTRA_TRNG_STATUS.DATA_WR_DONE.swwe) begin // SW write next_c = (field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -2458,15 +2510,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value <= 'h0; + field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value <= 1'h0; end else if(field_combo.CPTRA_TRNG_STATUS.DATA_WR_DONE.load_next) begin field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value <= field_combo.CPTRA_TRNG_STATUS.DATA_WR_DONE.next; end end // Field: soc_ifc_reg.CPTRA_FUSE_WR_DONE.done always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_FUSE_WR_DONE.done.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FUSE_WR_DONE.done.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FUSE_WR_DONE && decoded_req_is_wr && hwif_in.CPTRA_FUSE_WR_DONE.done.swwe) begin // SW write next_c = (field_storage.CPTRA_FUSE_WR_DONE.done.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2476,7 +2530,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FUSE_WR_DONE.done.value <= 'h0; + field_storage.CPTRA_FUSE_WR_DONE.done.value <= 1'h0; end else if(field_combo.CPTRA_FUSE_WR_DONE.done.load_next) begin field_storage.CPTRA_FUSE_WR_DONE.done.value <= field_combo.CPTRA_FUSE_WR_DONE.done.next; end @@ -2485,8 +2539,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FUSE_WR_DONE.done.swmod = decoded_reg_strb.CPTRA_FUSE_WR_DONE && decoded_req_is_wr; // Field: soc_ifc_reg.CPTRA_TIMER_CONFIG.clk_period always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_TIMER_CONFIG.clk_period.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TIMER_CONFIG.clk_period.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TIMER_CONFIG && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_TIMER_CONFIG.clk_period.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2496,15 +2552,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_TIMER_CONFIG.clk_period.value <= 'h0; + field_storage.CPTRA_TIMER_CONFIG.clk_period.value <= 32'h0; end else if(field_combo.CPTRA_TIMER_CONFIG.clk_period.load_next) begin field_storage.CPTRA_TIMER_CONFIG.clk_period.value <= field_combo.CPTRA_TIMER_CONFIG.clk_period.next; end end // Field: soc_ifc_reg.CPTRA_BOOTFSM_GO.GO always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_BOOTFSM_GO.GO.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_BOOTFSM_GO.GO.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_BOOTFSM_GO && decoded_req_is_wr && hwif_in.soc_req) begin // SW write next_c = (field_storage.CPTRA_BOOTFSM_GO.GO.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2517,7 +2575,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_BOOTFSM_GO.GO.value <= 'h0; + field_storage.CPTRA_BOOTFSM_GO.GO.value <= 1'h0; end else if(field_combo.CPTRA_BOOTFSM_GO.GO.load_next) begin field_storage.CPTRA_BOOTFSM_GO.GO.value <= field_combo.CPTRA_BOOTFSM_GO.GO.next; end @@ -2525,8 +2583,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_BOOTFSM_GO.GO.value = field_storage.CPTRA_BOOTFSM_GO.GO.value; // Field: soc_ifc_reg.CPTRA_DBG_MANUF_SERVICE_REG.DATA always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_DBG_MANUF_SERVICE_REG && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2539,7 +2599,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value <= 'h0; + field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value <= 32'h0; end else if(field_combo.CPTRA_DBG_MANUF_SERVICE_REG.DATA.load_next) begin field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value <= field_combo.CPTRA_DBG_MANUF_SERVICE_REG.DATA.next; end @@ -2547,8 +2607,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value = field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value; // Field: soc_ifc_reg.CPTRA_CLK_GATING_EN.clk_gating_en always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_CLK_GATING_EN && decoded_req_is_wr && hwif_in.soc_req) begin // SW write next_c = (field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2558,7 +2620,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value <= 'h0; + field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value <= 1'h0; end else if(field_combo.CPTRA_CLK_GATING_EN.clk_gating_en.load_next) begin field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value <= field_combo.CPTRA_CLK_GATING_EN.clk_gating_en.next; end @@ -2567,18 +2629,20 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_GENERIC_INPUT_WIRES[].generic_wires always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.next; - load_next_c = '1; - end + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.next; + load_next_c = '1; field_combo.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.next = next_c; field_combo.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.value <= 'h0; + field_storage.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.value <= 32'h0; end else if(field_combo.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.load_next) begin field_storage.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.value <= field_combo.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.next; end @@ -2588,8 +2652,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_GENERIC_OUTPUT_WIRES[].generic_wires always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_GENERIC_OUTPUT_WIRES[i0] && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2599,7 +2665,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value <= 'h0; + field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value <= 32'h0; end else if(field_combo.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.load_next) begin field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value <= field_combo.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.next; end @@ -2609,8 +2675,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_FW_REV_ID[].REV_ID always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FW_REV_ID[i0] && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2620,7 +2688,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value <= 'h0; + field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value <= 32'h0; end else if(field_combo.CPTRA_FW_REV_ID[i0].REV_ID.load_next) begin field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value <= field_combo.CPTRA_FW_REV_ID[i0].REV_ID.next; end @@ -2629,8 +2697,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_WDT_TIMER1_EN.timer1_en always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_TIMER1_EN && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2640,7 +2710,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value <= 'h0; + field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value <= 1'h0; end else if(field_combo.CPTRA_WDT_TIMER1_EN.timer1_en.load_next) begin field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value <= field_combo.CPTRA_WDT_TIMER1_EN.timer1_en.next; end @@ -2648,12 +2718,14 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_WDT_TIMER1_EN.timer1_en.value = field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value; // Field: soc_ifc_reg.CPTRA_WDT_TIMER1_CTRL.timer1_restart always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_TIMER1_CTRL && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -2662,7 +2734,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value <= 'h0; + field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value <= 1'h0; end else if(field_combo.CPTRA_WDT_TIMER1_CTRL.timer1_restart.load_next) begin field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value <= field_combo.CPTRA_WDT_TIMER1_CTRL.timer1_restart.next; end @@ -2671,8 +2743,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[].timer1_timeout_period always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0] && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2682,7 +2756,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value <= 'hffffffff; + field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value <= 32'hffffffff; end else if(field_combo.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.load_next) begin field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value <= field_combo.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.next; end @@ -2691,8 +2765,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_WDT_TIMER2_EN.timer2_en always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_TIMER2_EN && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2702,7 +2778,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value <= 'h0; + field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value <= 1'h0; end else if(field_combo.CPTRA_WDT_TIMER2_EN.timer2_en.load_next) begin field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value <= field_combo.CPTRA_WDT_TIMER2_EN.timer2_en.next; end @@ -2710,12 +2786,14 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_WDT_TIMER2_EN.timer2_en.value = field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value; // Field: soc_ifc_reg.CPTRA_WDT_TIMER2_CTRL.timer2_restart always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_TIMER2_CTRL && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -2724,7 +2802,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value <= 'h0; + field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value <= 1'h0; end else if(field_combo.CPTRA_WDT_TIMER2_CTRL.timer2_restart.load_next) begin field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value <= field_combo.CPTRA_WDT_TIMER2_CTRL.timer2_restart.next; end @@ -2733,8 +2811,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[].timer2_timeout_period always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2744,7 +2824,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value <= 'hffffffff; + field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value <= 32'hffffffff; end else if(field_combo.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.load_next) begin field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value <= field_combo.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.next; end @@ -2753,12 +2833,14 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_WDT_STATUS.t1_timeout always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_WDT_STATUS.t1_timeout.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_STATUS.t1_timeout.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_STATUS.t1_timeout.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // HW Write + end else begin // HW Write next_c = hwif_in.CPTRA_WDT_STATUS.t1_timeout.next; load_next_c = '1; end @@ -2767,7 +2849,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_STATUS.t1_timeout.value <= 'h0; + field_storage.CPTRA_WDT_STATUS.t1_timeout.value <= 1'h0; end else if(field_combo.CPTRA_WDT_STATUS.t1_timeout.load_next) begin field_storage.CPTRA_WDT_STATUS.t1_timeout.value <= field_combo.CPTRA_WDT_STATUS.t1_timeout.next; end @@ -2775,12 +2857,14 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_WDT_STATUS.t1_timeout.value = field_storage.CPTRA_WDT_STATUS.t1_timeout.value; // Field: soc_ifc_reg.CPTRA_WDT_STATUS.t2_timeout always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_WDT_STATUS.t2_timeout.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_STATUS.t2_timeout.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_STATUS.t2_timeout.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // HW Write + end else begin // HW Write next_c = hwif_in.CPTRA_WDT_STATUS.t2_timeout.next; load_next_c = '1; end @@ -2789,7 +2873,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_STATUS.t2_timeout.value <= 'h0; + field_storage.CPTRA_WDT_STATUS.t2_timeout.value <= 1'h0; end else if(field_combo.CPTRA_WDT_STATUS.t2_timeout.load_next) begin field_storage.CPTRA_WDT_STATUS.t2_timeout.value <= field_combo.CPTRA_WDT_STATUS.t2_timeout.next; end @@ -2797,8 +2881,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_WDT_STATUS.t2_timeout.value = field_storage.CPTRA_WDT_STATUS.t2_timeout.value; // Field: soc_ifc_reg.CPTRA_FUSE_VALID_PAUSER.PAUSER always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_VALID_PAUSER.PAUSER.swwel)) begin // SW write next_c = (field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2808,7 +2894,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value <= 'hffffffff; + field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value <= 32'hffffffff; end else if(field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.load_next) begin field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value <= field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.next; end @@ -2816,8 +2902,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FUSE_VALID_PAUSER.PAUSER.value = field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value; // Field: soc_ifc_reg.CPTRA_FUSE_PAUSER_LOCK.LOCK always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_PAUSER_LOCK.LOCK.swwel)) begin // SW write next_c = (field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2827,7 +2915,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value <= 'h0; + field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value <= 1'h0; end else if(field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.load_next) begin field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value <= field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.next; end @@ -2836,8 +2924,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_WDT_CFG[].TIMEOUT always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_CFG[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2847,7 +2937,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value <= 'h0; + field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value <= 32'h0; end else if(field_combo.CPTRA_WDT_CFG[i0].TIMEOUT.load_next) begin field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value <= field_combo.CPTRA_WDT_CFG[i0].TIMEOUT.next; end @@ -2855,8 +2945,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold always_comb begin - automatic logic [15:0] next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value; - automatic logic load_next_c = '0; + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_0 && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); load_next_c = '1; @@ -2866,15 +2958,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value <= 'h0; + field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value <= 16'h0; end else if(field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.load_next) begin field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value <= field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.next; end end // Field: soc_ifc_reg.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold always_comb begin - automatic logic [15:0] next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value; - automatic logic load_next_c = '0; + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_0 && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]); load_next_c = '1; @@ -2884,15 +2978,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value <= 'h0; + field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value <= 16'h0; end else if(field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.load_next) begin field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value <= field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.next; end end // Field: soc_ifc_reg.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count always_comb begin - automatic logic [15:0] next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value; - automatic logic load_next_c = '0; + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_1 && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); load_next_c = '1; @@ -2902,15 +2998,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value <= 'h0; + field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value <= 16'h0; end else if(field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.load_next) begin field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value <= field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.next; end end // Field: soc_ifc_reg.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD always_comb begin - automatic logic [15:0] next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value; - automatic logic load_next_c = '0; + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_1 && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]); load_next_c = '1; @@ -2920,7 +3018,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value <= 'h0; + field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value <= 16'h0; end else if(field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.load_next) begin field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value <= field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.next; end @@ -2928,8 +3026,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_RSVD_REG[].RSVD always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_RSVD_REG[i0].RSVD.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_RSVD_REG[i0].RSVD.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_RSVD_REG[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_RSVD_REG[i0].RSVD.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2939,7 +3039,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_RSVD_REG[i0].RSVD.value <= 'h0; + field_storage.CPTRA_RSVD_REG[i0].RSVD.value <= 32'h0; end else if(field_combo.CPTRA_RSVD_REG[i0].RSVD.load_next) begin field_storage.CPTRA_RSVD_REG[i0].RSVD.value <= field_combo.CPTRA_RSVD_REG[i0].RSVD.next; end @@ -2948,8 +3048,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: soc_ifc_reg.fuse_uds_seed[].seed always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_uds_seed[i0].seed.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_uds_seed[i0].seed.value; + load_next_c = '0; if(decoded_reg_strb.fuse_uds_seed[i0] && decoded_req_is_wr && !(hwif_in.fuse_uds_seed[i0].seed.swwel)) begin // SW write next_c = (field_storage.fuse_uds_seed[i0].seed.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2962,7 +3064,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_uds_seed[i0].seed.value <= 'h0; + field_storage.fuse_uds_seed[i0].seed.value <= 32'h0; end else if(field_combo.fuse_uds_seed[i0].seed.load_next) begin field_storage.fuse_uds_seed[i0].seed.value <= field_combo.fuse_uds_seed[i0].seed.next; end @@ -2972,8 +3074,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: soc_ifc_reg.fuse_field_entropy[].seed always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_field_entropy[i0].seed.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_field_entropy[i0].seed.value; + load_next_c = '0; if(decoded_reg_strb.fuse_field_entropy[i0] && decoded_req_is_wr && !(hwif_in.fuse_field_entropy[i0].seed.swwel)) begin // SW write next_c = (field_storage.fuse_field_entropy[i0].seed.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2986,7 +3090,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_field_entropy[i0].seed.value <= 'h0; + field_storage.fuse_field_entropy[i0].seed.value <= 32'h0; end else if(field_combo.fuse_field_entropy[i0].seed.load_next) begin field_storage.fuse_field_entropy[i0].seed.value <= field_combo.fuse_field_entropy[i0].seed.next; end @@ -2996,8 +3100,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: soc_ifc_reg.fuse_key_manifest_pk_hash[].hash always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_key_manifest_pk_hash[i0].hash.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_key_manifest_pk_hash[i0].hash.value; + load_next_c = '0; if(decoded_reg_strb.fuse_key_manifest_pk_hash[i0] && decoded_req_is_wr && !(hwif_in.fuse_key_manifest_pk_hash[i0].hash.swwel)) begin // SW write next_c = (field_storage.fuse_key_manifest_pk_hash[i0].hash.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3007,7 +3113,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_key_manifest_pk_hash[i0].hash.value <= 'h0; + field_storage.fuse_key_manifest_pk_hash[i0].hash.value <= 32'h0; end else if(field_combo.fuse_key_manifest_pk_hash[i0].hash.load_next) begin field_storage.fuse_key_manifest_pk_hash[i0].hash.value <= field_combo.fuse_key_manifest_pk_hash[i0].hash.next; end @@ -3016,8 +3122,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.fuse_key_manifest_pk_hash_mask.mask always_comb begin - automatic logic [3:0] next_c = field_storage.fuse_key_manifest_pk_hash_mask.mask.value; - automatic logic load_next_c = '0; + automatic logic [3:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_key_manifest_pk_hash_mask.mask.value; + load_next_c = '0; if(decoded_reg_strb.fuse_key_manifest_pk_hash_mask && decoded_req_is_wr && !(hwif_in.fuse_key_manifest_pk_hash_mask.mask.swwel)) begin // SW write next_c = (field_storage.fuse_key_manifest_pk_hash_mask.mask.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]); load_next_c = '1; @@ -3027,7 +3135,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_key_manifest_pk_hash_mask.mask.value <= 'h0; + field_storage.fuse_key_manifest_pk_hash_mask.mask.value <= 4'h0; end else if(field_combo.fuse_key_manifest_pk_hash_mask.mask.load_next) begin field_storage.fuse_key_manifest_pk_hash_mask.mask.value <= field_combo.fuse_key_manifest_pk_hash_mask.mask.next; end @@ -3036,8 +3144,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: soc_ifc_reg.fuse_owner_pk_hash[].hash always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_owner_pk_hash[i0].hash.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_owner_pk_hash[i0].hash.value; + load_next_c = '0; if(decoded_reg_strb.fuse_owner_pk_hash[i0] && decoded_req_is_wr && !(hwif_in.fuse_owner_pk_hash[i0].hash.swwel)) begin // SW write next_c = (field_storage.fuse_owner_pk_hash[i0].hash.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3047,7 +3157,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_owner_pk_hash[i0].hash.value <= 'h0; + field_storage.fuse_owner_pk_hash[i0].hash.value <= 32'h0; end else if(field_combo.fuse_owner_pk_hash[i0].hash.load_next) begin field_storage.fuse_owner_pk_hash[i0].hash.value <= field_combo.fuse_owner_pk_hash[i0].hash.next; end @@ -3056,8 +3166,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.fuse_fmc_key_manifest_svn.svn always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_fmc_key_manifest_svn.svn.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_fmc_key_manifest_svn.svn.value; + load_next_c = '0; if(decoded_reg_strb.fuse_fmc_key_manifest_svn && decoded_req_is_wr && !(hwif_in.fuse_fmc_key_manifest_svn.svn.swwel)) begin // SW write next_c = (field_storage.fuse_fmc_key_manifest_svn.svn.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3067,7 +3179,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_fmc_key_manifest_svn.svn.value <= 'h0; + field_storage.fuse_fmc_key_manifest_svn.svn.value <= 32'h0; end else if(field_combo.fuse_fmc_key_manifest_svn.svn.load_next) begin field_storage.fuse_fmc_key_manifest_svn.svn.value <= field_combo.fuse_fmc_key_manifest_svn.svn.next; end @@ -3076,8 +3188,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<4; i0++) begin // Field: soc_ifc_reg.fuse_runtime_svn[].svn always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_runtime_svn[i0].svn.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_runtime_svn[i0].svn.value; + load_next_c = '0; if(decoded_reg_strb.fuse_runtime_svn[i0] && decoded_req_is_wr && !(hwif_in.fuse_runtime_svn[i0].svn.swwel)) begin // SW write next_c = (field_storage.fuse_runtime_svn[i0].svn.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3087,7 +3201,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_runtime_svn[i0].svn.value <= 'h0; + field_storage.fuse_runtime_svn[i0].svn.value <= 32'h0; end else if(field_combo.fuse_runtime_svn[i0].svn.load_next) begin field_storage.fuse_runtime_svn[i0].svn.value <= field_combo.fuse_runtime_svn[i0].svn.next; end @@ -3096,8 +3210,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.fuse_anti_rollback_disable.dis always_comb begin - automatic logic [0:0] next_c = field_storage.fuse_anti_rollback_disable.dis.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_anti_rollback_disable.dis.value; + load_next_c = '0; if(decoded_reg_strb.fuse_anti_rollback_disable && decoded_req_is_wr && !(hwif_in.fuse_anti_rollback_disable.dis.swwel)) begin // SW write next_c = (field_storage.fuse_anti_rollback_disable.dis.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3107,7 +3223,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_anti_rollback_disable.dis.value <= 'h0; + field_storage.fuse_anti_rollback_disable.dis.value <= 1'h0; end else if(field_combo.fuse_anti_rollback_disable.dis.load_next) begin field_storage.fuse_anti_rollback_disable.dis.value <= field_combo.fuse_anti_rollback_disable.dis.next; end @@ -3116,8 +3232,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<24; i0++) begin // Field: soc_ifc_reg.fuse_idevid_cert_attr[].cert always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_idevid_cert_attr[i0].cert.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_idevid_cert_attr[i0].cert.value; + load_next_c = '0; if(decoded_reg_strb.fuse_idevid_cert_attr[i0] && decoded_req_is_wr && !(hwif_in.fuse_idevid_cert_attr[i0].cert.swwel)) begin // SW write next_c = (field_storage.fuse_idevid_cert_attr[i0].cert.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3127,7 +3245,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_idevid_cert_attr[i0].cert.value <= 'h0; + field_storage.fuse_idevid_cert_attr[i0].cert.value <= 32'h0; end else if(field_combo.fuse_idevid_cert_attr[i0].cert.load_next) begin field_storage.fuse_idevid_cert_attr[i0].cert.value <= field_combo.fuse_idevid_cert_attr[i0].cert.next; end @@ -3137,8 +3255,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<4; i0++) begin // Field: soc_ifc_reg.fuse_idevid_manuf_hsm_id[].hsm_id always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value; + load_next_c = '0; if(decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] && decoded_req_is_wr && !(hwif_in.fuse_idevid_manuf_hsm_id[i0].hsm_id.swwel)) begin // SW write next_c = (field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3148,7 +3268,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value <= 'h0; + field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value <= 32'h0; end else if(field_combo.fuse_idevid_manuf_hsm_id[i0].hsm_id.load_next) begin field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value <= field_combo.fuse_idevid_manuf_hsm_id[i0].hsm_id.next; end @@ -3157,8 +3277,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.fuse_life_cycle.life_cycle always_comb begin - automatic logic [1:0] next_c = field_storage.fuse_life_cycle.life_cycle.value; - automatic logic load_next_c = '0; + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_life_cycle.life_cycle.value; + load_next_c = '0; if(decoded_reg_strb.fuse_life_cycle && decoded_req_is_wr && !(hwif_in.fuse_life_cycle.life_cycle.swwel)) begin // SW write next_c = (field_storage.fuse_life_cycle.life_cycle.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); load_next_c = '1; @@ -3168,7 +3290,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_life_cycle.life_cycle.value <= 'h0; + field_storage.fuse_life_cycle.life_cycle.value <= 2'h0; end else if(field_combo.fuse_life_cycle.life_cycle.load_next) begin field_storage.fuse_life_cycle.life_cycle.value <= field_combo.fuse_life_cycle.life_cycle.next; end @@ -3176,8 +3298,10 @@ module soc_ifc_reg ( assign hwif_out.fuse_life_cycle.life_cycle.value = field_storage.fuse_life_cycle.life_cycle.value; // Field: soc_ifc_reg.fuse_lms_verify.lms_verify always_comb begin - automatic logic [0:0] next_c = field_storage.fuse_lms_verify.lms_verify.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_lms_verify.lms_verify.value; + load_next_c = '0; if(decoded_reg_strb.fuse_lms_verify && decoded_req_is_wr && !(hwif_in.fuse_lms_verify.lms_verify.swwel)) begin // SW write next_c = (field_storage.fuse_lms_verify.lms_verify.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3187,7 +3311,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_lms_verify.lms_verify.value <= 'h0; + field_storage.fuse_lms_verify.lms_verify.value <= 1'h0; end else if(field_combo.fuse_lms_verify.lms_verify.load_next) begin field_storage.fuse_lms_verify.lms_verify.value <= field_combo.fuse_lms_verify.lms_verify.next; end @@ -3195,8 +3319,10 @@ module soc_ifc_reg ( assign hwif_out.fuse_lms_verify.lms_verify.value = field_storage.fuse_lms_verify.lms_verify.value; // Field: soc_ifc_reg.fuse_lms_revocation.lms_revocation always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_lms_revocation.lms_revocation.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_lms_revocation.lms_revocation.value; + load_next_c = '0; if(decoded_reg_strb.fuse_lms_revocation && decoded_req_is_wr && !(hwif_in.fuse_lms_revocation.lms_revocation.swwel)) begin // SW write next_c = (field_storage.fuse_lms_revocation.lms_revocation.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3206,7 +3332,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_lms_revocation.lms_revocation.value <= 'h0; + field_storage.fuse_lms_revocation.lms_revocation.value <= 32'h0; end else if(field_combo.fuse_lms_revocation.lms_revocation.load_next) begin field_storage.fuse_lms_revocation.lms_revocation.value <= field_combo.fuse_lms_revocation.lms_revocation.next; end @@ -3214,8 +3340,10 @@ module soc_ifc_reg ( assign hwif_out.fuse_lms_revocation.lms_revocation.value = field_storage.fuse_lms_revocation.lms_revocation.value; // Field: soc_ifc_reg.fuse_soc_stepping_id.soc_stepping_id always_comb begin - automatic logic [15:0] next_c = field_storage.fuse_soc_stepping_id.soc_stepping_id.value; - automatic logic load_next_c = '0; + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_soc_stepping_id.soc_stepping_id.value; + load_next_c = '0; if(decoded_reg_strb.fuse_soc_stepping_id && decoded_req_is_wr && !(hwif_in.fuse_soc_stepping_id.soc_stepping_id.swwel)) begin // SW write next_c = (field_storage.fuse_soc_stepping_id.soc_stepping_id.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); load_next_c = '1; @@ -3225,7 +3353,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_soc_stepping_id.soc_stepping_id.value <= 'h0; + field_storage.fuse_soc_stepping_id.soc_stepping_id.value <= 16'h0; end else if(field_combo.fuse_soc_stepping_id.soc_stepping_id.load_next) begin field_storage.fuse_soc_stepping_id.soc_stepping_id.value <= field_combo.fuse_soc_stepping_id.soc_stepping_id.next; end @@ -3234,8 +3362,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: soc_ifc_reg.internal_obf_key[].key always_comb begin - automatic logic [31:0] next_c = field_storage.internal_obf_key[i0].key.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_obf_key[i0].key.value; + load_next_c = '0; if(decoded_reg_strb.internal_obf_key[i0] && decoded_req_is_wr && hwif_in.internal_obf_key[i0].key.swwe) begin // SW write next_c = (field_storage.internal_obf_key[i0].key.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3249,6 +3379,7 @@ module soc_ifc_reg ( field_combo.internal_obf_key[i0].key.next = next_c; field_combo.internal_obf_key[i0].key.load_next = load_next_c; end + always_ff @(posedge clk) begin if(field_combo.internal_obf_key[i0].key.load_next) begin field_storage.internal_obf_key[i0].key.value <= field_combo.internal_obf_key[i0].key.next; @@ -3258,8 +3389,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.internal_iccm_lock.lock always_comb begin - automatic logic [0:0] next_c = field_storage.internal_iccm_lock.lock.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_iccm_lock.lock.value; + load_next_c = '0; if(hwif_in.internal_iccm_lock.lock.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; @@ -3272,7 +3405,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_iccm_lock.lock.value <= 'h0; + field_storage.internal_iccm_lock.lock.value <= 1'h0; end else if(field_combo.internal_iccm_lock.lock.load_next) begin field_storage.internal_iccm_lock.lock.value <= field_combo.internal_iccm_lock.lock.next; end @@ -3280,12 +3413,14 @@ module soc_ifc_reg ( assign hwif_out.internal_iccm_lock.lock.value = field_storage.internal_iccm_lock.lock.value; // Field: soc_ifc_reg.internal_fw_update_reset.core_rst always_comb begin - automatic logic [0:0] next_c = field_storage.internal_fw_update_reset.core_rst.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_fw_update_reset.core_rst.value; + load_next_c = '0; if(decoded_reg_strb.internal_fw_update_reset && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_fw_update_reset.core_rst.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -3294,7 +3429,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_fw_update_reset.core_rst.value <= 'h0; + field_storage.internal_fw_update_reset.core_rst.value <= 1'h0; end else if(field_combo.internal_fw_update_reset.core_rst.load_next) begin field_storage.internal_fw_update_reset.core_rst.value <= field_combo.internal_fw_update_reset.core_rst.next; end @@ -3302,8 +3437,10 @@ module soc_ifc_reg ( assign hwif_out.internal_fw_update_reset.core_rst.value = field_storage.internal_fw_update_reset.core_rst.value; // Field: soc_ifc_reg.internal_fw_update_reset_wait_cycles.wait_cycles always_comb begin - automatic logic [7:0] next_c = field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value; - automatic logic load_next_c = '0; + automatic logic [7:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value; + load_next_c = '0; if(decoded_reg_strb.internal_fw_update_reset_wait_cycles && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]); load_next_c = '1; @@ -3313,7 +3450,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value <= 'h5; + field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value <= 8'h5; end else if(field_combo.internal_fw_update_reset_wait_cycles.wait_cycles.load_next) begin field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value <= field_combo.internal_fw_update_reset_wait_cycles.wait_cycles.next; end @@ -3321,8 +3458,10 @@ module soc_ifc_reg ( assign hwif_out.internal_fw_update_reset_wait_cycles.wait_cycles.value = field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value; // Field: soc_ifc_reg.internal_nmi_vector.vec always_comb begin - automatic logic [31:0] next_c = field_storage.internal_nmi_vector.vec.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_nmi_vector.vec.value; + load_next_c = '0; if(decoded_reg_strb.internal_nmi_vector && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_nmi_vector.vec.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3332,7 +3471,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_nmi_vector.vec.value <= 'h0; + field_storage.internal_nmi_vector.vec.value <= 32'h0; end else if(field_combo.internal_nmi_vector.vec.load_next) begin field_storage.internal_nmi_vector.vec.value <= field_combo.internal_nmi_vector.vec.next; end @@ -3340,8 +3479,10 @@ module soc_ifc_reg ( assign hwif_out.internal_nmi_vector.vec.value = field_storage.internal_nmi_vector.vec.value; // Field: soc_ifc_reg.internal_hw_error_fatal_mask.mask_iccm_ecc_unc always_comb begin - automatic logic [0:0] next_c = field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value; + load_next_c = '0; if(decoded_reg_strb.internal_hw_error_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3351,7 +3492,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value <= 'h0; + field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value <= 1'h0; end else if(field_combo.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.load_next) begin field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value <= field_combo.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.next; end @@ -3359,8 +3500,10 @@ module soc_ifc_reg ( assign hwif_out.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value = field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value; // Field: soc_ifc_reg.internal_hw_error_fatal_mask.mask_dccm_ecc_unc always_comb begin - automatic logic [0:0] next_c = field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value; + load_next_c = '0; if(decoded_reg_strb.internal_hw_error_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -3370,7 +3513,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value <= 'h0; + field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value <= 1'h0; end else if(field_combo.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.load_next) begin field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value <= field_combo.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.next; end @@ -3378,8 +3521,10 @@ module soc_ifc_reg ( assign hwif_out.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value = field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value; // Field: soc_ifc_reg.internal_hw_error_fatal_mask.mask_nmi_pin always_comb begin - automatic logic [0:0] next_c = field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value; + load_next_c = '0; if(decoded_reg_strb.internal_hw_error_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -3389,7 +3534,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value <= 'h0; + field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value <= 1'h0; end else if(field_combo.internal_hw_error_fatal_mask.mask_nmi_pin.load_next) begin field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value <= field_combo.internal_hw_error_fatal_mask.mask_nmi_pin.next; end @@ -3397,8 +3542,10 @@ module soc_ifc_reg ( assign hwif_out.internal_hw_error_fatal_mask.mask_nmi_pin.value = field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value; // Field: soc_ifc_reg.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock always_comb begin - automatic logic [0:0] next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value; + load_next_c = '0; if(decoded_reg_strb.internal_hw_error_non_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3408,7 +3555,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value <= 'h0; + field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value <= 1'h0; end else if(field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.load_next) begin field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value <= field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.next; end @@ -3416,8 +3563,10 @@ module soc_ifc_reg ( assign hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value; // Field: soc_ifc_reg.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo always_comb begin - automatic logic [0:0] next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value; + load_next_c = '0; if(decoded_reg_strb.internal_hw_error_non_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -3427,7 +3576,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value <= 'h0; + field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value <= 1'h0; end else if(field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.load_next) begin field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value <= field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.next; end @@ -3435,8 +3584,10 @@ module soc_ifc_reg ( assign hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value; // Field: soc_ifc_reg.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc always_comb begin - automatic logic [0:0] next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value; + load_next_c = '0; if(decoded_reg_strb.internal_hw_error_non_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -3446,7 +3597,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value <= 'h0; + field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value <= 1'h0; end else if(field_combo.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.load_next) begin field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value <= field_combo.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.next; end @@ -3454,8 +3605,10 @@ module soc_ifc_reg ( assign hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value; // Field: soc_ifc_reg.internal_fw_error_fatal_mask.mask always_comb begin - automatic logic [31:0] next_c = field_storage.internal_fw_error_fatal_mask.mask.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_fw_error_fatal_mask.mask.value; + load_next_c = '0; if(decoded_reg_strb.internal_fw_error_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_fw_error_fatal_mask.mask.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3465,7 +3618,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_fw_error_fatal_mask.mask.value <= 'h0; + field_storage.internal_fw_error_fatal_mask.mask.value <= 32'h0; end else if(field_combo.internal_fw_error_fatal_mask.mask.load_next) begin field_storage.internal_fw_error_fatal_mask.mask.value <= field_combo.internal_fw_error_fatal_mask.mask.next; end @@ -3473,8 +3626,10 @@ module soc_ifc_reg ( assign hwif_out.internal_fw_error_fatal_mask.mask.value = field_storage.internal_fw_error_fatal_mask.mask.value; // Field: soc_ifc_reg.internal_fw_error_non_fatal_mask.mask always_comb begin - automatic logic [31:0] next_c = field_storage.internal_fw_error_non_fatal_mask.mask.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_fw_error_non_fatal_mask.mask.value; + load_next_c = '0; if(decoded_reg_strb.internal_fw_error_non_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_fw_error_non_fatal_mask.mask.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3484,7 +3639,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_fw_error_non_fatal_mask.mask.value <= 'h0; + field_storage.internal_fw_error_non_fatal_mask.mask.value <= 32'h0; end else if(field_combo.internal_fw_error_non_fatal_mask.mask.load_next) begin field_storage.internal_fw_error_non_fatal_mask.mask.value <= field_combo.internal_fw_error_non_fatal_mask.mask.next; end @@ -3492,26 +3647,28 @@ module soc_ifc_reg ( assign hwif_out.internal_fw_error_non_fatal_mask.mask.value = field_storage.internal_fw_error_non_fatal_mask.mask.value; // Field: soc_ifc_reg.internal_rv_mtime_l.count_l always_comb begin - automatic logic [31:0] next_c = field_storage.internal_rv_mtime_l.count_l.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_rv_mtime_l.count_l.value; + load_next_c = '0; if(decoded_reg_strb.internal_rv_mtime_l && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_rv_mtime_l.count_l.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(hwif_in.internal_rv_mtime_l.count_l.incr) begin // increment - field_combo.internal_rv_mtime_l.count_l.overflow = (((33)'(next_c) + 'h1) > 'hffffffff); - next_c = next_c + 'h1; + field_combo.internal_rv_mtime_l.count_l.overflow = (((33)'(next_c) + 32'h1) > 32'hffffffff); + next_c = next_c + 32'h1; load_next_c = '1; end else begin field_combo.internal_rv_mtime_l.count_l.overflow = '0; end - field_combo.internal_rv_mtime_l.count_l.incrthreshold = (field_storage.internal_rv_mtime_l.count_l.value >= 'hffffffff); + field_combo.internal_rv_mtime_l.count_l.incrthreshold = (field_storage.internal_rv_mtime_l.count_l.value >= 32'hffffffff); field_combo.internal_rv_mtime_l.count_l.next = next_c; field_combo.internal_rv_mtime_l.count_l.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.internal_rv_mtime_l.count_l.value <= 'h0; + field_storage.internal_rv_mtime_l.count_l.value <= 32'h0; end else if(field_combo.internal_rv_mtime_l.count_l.load_next) begin field_storage.internal_rv_mtime_l.count_l.value <= field_combo.internal_rv_mtime_l.count_l.next; end @@ -3521,26 +3678,28 @@ module soc_ifc_reg ( assign hwif_out.internal_rv_mtime_l.count_l.overflow = field_combo.internal_rv_mtime_l.count_l.overflow; // Field: soc_ifc_reg.internal_rv_mtime_h.count_h always_comb begin - automatic logic [31:0] next_c = field_storage.internal_rv_mtime_h.count_h.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_rv_mtime_h.count_h.value; + load_next_c = '0; if(decoded_reg_strb.internal_rv_mtime_h && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_rv_mtime_h.count_h.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(hwif_in.internal_rv_mtime_h.count_h.incr) begin // increment - field_combo.internal_rv_mtime_h.count_h.overflow = (((33)'(next_c) + 'h1) > 'hffffffff); - next_c = next_c + 'h1; + field_combo.internal_rv_mtime_h.count_h.overflow = (((33)'(next_c) + 32'h1) > 32'hffffffff); + next_c = next_c + 32'h1; load_next_c = '1; end else begin field_combo.internal_rv_mtime_h.count_h.overflow = '0; end - field_combo.internal_rv_mtime_h.count_h.incrthreshold = (field_storage.internal_rv_mtime_h.count_h.value >= 'hffffffff); + field_combo.internal_rv_mtime_h.count_h.incrthreshold = (field_storage.internal_rv_mtime_h.count_h.value >= 32'hffffffff); field_combo.internal_rv_mtime_h.count_h.next = next_c; field_combo.internal_rv_mtime_h.count_h.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.internal_rv_mtime_h.count_h.value <= 'h0; + field_storage.internal_rv_mtime_h.count_h.value <= 32'h0; end else if(field_combo.internal_rv_mtime_h.count_h.load_next) begin field_storage.internal_rv_mtime_h.count_h.value <= field_combo.internal_rv_mtime_h.count_h.next; end @@ -3549,8 +3708,10 @@ module soc_ifc_reg ( assign hwif_out.internal_rv_mtime_h.count_h.swmod = decoded_reg_strb.internal_rv_mtime_h && decoded_req_is_wr; // Field: soc_ifc_reg.internal_rv_mtimecmp_l.compare_l always_comb begin - automatic logic [31:0] next_c = field_storage.internal_rv_mtimecmp_l.compare_l.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_rv_mtimecmp_l.compare_l.value; + load_next_c = '0; if(decoded_reg_strb.internal_rv_mtimecmp_l && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_rv_mtimecmp_l.compare_l.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3560,7 +3721,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.internal_rv_mtimecmp_l.compare_l.value <= 'h0; + field_storage.internal_rv_mtimecmp_l.compare_l.value <= 32'h0; end else if(field_combo.internal_rv_mtimecmp_l.compare_l.load_next) begin field_storage.internal_rv_mtimecmp_l.compare_l.value <= field_combo.internal_rv_mtimecmp_l.compare_l.next; end @@ -3568,8 +3729,10 @@ module soc_ifc_reg ( assign hwif_out.internal_rv_mtimecmp_l.compare_l.value = field_storage.internal_rv_mtimecmp_l.compare_l.value; // Field: soc_ifc_reg.internal_rv_mtimecmp_h.compare_h always_comb begin - automatic logic [31:0] next_c = field_storage.internal_rv_mtimecmp_h.compare_h.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_rv_mtimecmp_h.compare_h.value; + load_next_c = '0; if(decoded_reg_strb.internal_rv_mtimecmp_h && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_rv_mtimecmp_h.compare_h.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3579,7 +3742,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.internal_rv_mtimecmp_h.compare_h.value <= 'h0; + field_storage.internal_rv_mtimecmp_h.compare_h.value <= 32'h0; end else if(field_combo.internal_rv_mtimecmp_h.compare_h.load_next) begin field_storage.internal_rv_mtimecmp_h.compare_h.value <= field_combo.internal_rv_mtimecmp_h.compare_h.next; end @@ -3587,8 +3750,10 @@ module soc_ifc_reg ( assign hwif_out.internal_rv_mtimecmp_h.compare_h.value = field_storage.internal_rv_mtimecmp_h.compare_h.value; // Field: soc_ifc_reg.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3598,15 +3763,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; end end // Field: soc_ifc_reg.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -3616,15 +3783,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_internal_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3634,15 +3803,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_internal_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_internal_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_inv_dev_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -3652,15 +3823,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_inv_dev_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_inv_dev_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_cmd_fail_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -3670,15 +3843,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_cmd_fail_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_cmd_fail_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_bad_fuse_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -3688,15 +3863,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_bad_fuse_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_bad_fuse_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_iccm_blocked_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); load_next_c = '1; @@ -3706,15 +3883,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value & ~decoded_wr_biten[5:5]) | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]); load_next_c = '1; @@ -3724,15 +3903,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -3742,15 +3923,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value & ~decoded_wr_biten[7:7]) | (decoded_wr_data[7:7] & decoded_wr_biten[7:7]); load_next_c = '1; @@ -3760,15 +3943,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3778,15 +3963,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -3796,15 +3983,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_debug_locked_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -3814,15 +4003,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_scan_mode_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -3832,15 +4023,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); load_next_c = '1; @@ -3850,15 +4043,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value & ~decoded_wr_biten[5:5]) | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]); load_next_c = '1; @@ -3868,25 +4063,27 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; end @@ -3895,18 +4092,20 @@ module soc_ifc_reg ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: soc_ifc_reg.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; end @@ -3915,9 +4114,11 @@ module soc_ifc_reg ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_internal_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset) begin // HW Set @@ -3932,16 +4133,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_internal_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_internal_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_inv_dev_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.hwset) begin // HW Set @@ -3956,16 +4159,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.hwset) begin // HW Set @@ -3980,16 +4185,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.hwset) begin // HW Set @@ -4004,16 +4211,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.hwset) begin // HW Set @@ -4028,16 +4237,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.hwset) begin // HW Set @@ -4052,16 +4263,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.hwset) begin // HW Set @@ -4076,16 +4289,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.hwset) begin // HW Set @@ -4100,7 +4315,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.next; end @@ -4116,9 +4331,11 @@ module soc_ifc_reg ( || |(field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value & field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value); // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.hwset) begin // HW Set @@ -4133,16 +4350,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.hwset) begin // HW Set @@ -4157,16 +4376,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.hwset) begin // HW Set @@ -4181,16 +4402,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.hwset) begin // HW Set @@ -4205,16 +4428,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.hwset) begin // HW Set @@ -4229,16 +4454,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.hwset) begin // HW Set @@ -4253,7 +4480,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.next; end @@ -4267,12 +4494,14 @@ module soc_ifc_reg ( || |(field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value); // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_internal_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4281,19 +4510,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_internal_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_internal_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_inv_dev_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4302,19 +4533,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4323,19 +4556,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4344,19 +4579,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4365,19 +4602,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4386,19 +4625,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4407,19 +4648,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value | (decoded_wr_data[7:7] & decoded_wr_biten[7:7]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4428,19 +4671,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4449,19 +4694,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4470,19 +4717,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4491,19 +4740,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4512,19 +4763,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4533,19 +4786,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4554,31 +4809,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_internal_intr_count_r.cnt.next = next_c; @@ -4586,31 +4843,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_internal_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_internal_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_inv_dev_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.next = next_c; @@ -4618,31 +4877,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_cmd_fail_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.next = next_c; @@ -4650,31 +4911,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_bad_fuse_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.next = next_c; @@ -4682,31 +4945,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_iccm_blocked_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.next = next_c; @@ -4714,31 +4979,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.next = next_c; @@ -4746,31 +5013,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.next = next_c; @@ -4778,31 +5047,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.next = next_c; @@ -4810,31 +5081,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_cmd_avail_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.next = next_c; @@ -4842,31 +5115,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.next = next_c; @@ -4874,31 +5149,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_debug_locked_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.next = next_c; @@ -4906,31 +5183,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_scan_mode_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.next = next_c; @@ -4938,31 +5217,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.next = next_c; @@ -4970,31 +5251,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.next = next_c; @@ -5002,15 +5285,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; load_next_c = '1; @@ -5019,27 +5304,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value; load_next_c = '1; @@ -5048,27 +5335,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value; load_next_c = '1; @@ -5077,27 +5366,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value; load_next_c = '1; @@ -5106,27 +5397,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value; load_next_c = '1; @@ -5135,27 +5428,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value; load_next_c = '1; @@ -5164,27 +5459,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value; load_next_c = '1; @@ -5193,27 +5490,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value; load_next_c = '1; @@ -5222,27 +5521,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value; load_next_c = '1; @@ -5251,27 +5552,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value; load_next_c = '1; @@ -5280,27 +5583,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value; load_next_c = '1; @@ -5309,27 +5614,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value; load_next_c = '1; @@ -5338,27 +5645,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value; load_next_c = '1; @@ -5367,27 +5676,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value; load_next_c = '1; @@ -5396,30 +5707,39 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.next; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [186-1:0][31:0] readback_array; assign readback_array[0][0:0] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value : '0; @@ -5451,7 +5771,7 @@ module soc_ifc_reg ( assign readback_array[17][1:0] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? hwif_in.CPTRA_SECURITY_STATE.device_lifecycle.next : '0; assign readback_array[17][2:2] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? hwif_in.CPTRA_SECURITY_STATE.debug_locked.next : '0; assign readback_array[17][3:3] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? hwif_in.CPTRA_SECURITY_STATE.scan_mode.next : '0; - assign readback_array[17][31:4] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? 'h0 : '0; + assign readback_array[17][31:4] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? 28'h0 : '0; for(genvar i0=0; i0<5; i0++) begin assign readback_array[i0*1 + 18][31:0] = (decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value : '0; end @@ -5484,7 +5804,7 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin assign readback_array[i0*1 + 51][31:0] = (decoded_reg_strb.CPTRA_GENERIC_OUTPUT_WIRES[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value : '0; end - assign readback_array[53][15:0] = (decoded_reg_strb.CPTRA_HW_REV_ID && !decoded_req_is_wr) ? 'h1 : '0; + assign readback_array[53][15:0] = (decoded_reg_strb.CPTRA_HW_REV_ID && !decoded_req_is_wr) ? 16'h1 : '0; assign readback_array[53][31:16] = (decoded_reg_strb.CPTRA_HW_REV_ID && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_REV_ID.SOC_STEPPING_ID.next : '0; for(genvar i0=0; i0<2; i0++) begin assign readback_array[i0*1 + 54][31:0] = (decoded_reg_strb.CPTRA_FW_REV_ID[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value : '0; @@ -5686,4 +6006,4 @@ module soc_ifc_reg ( `CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.cptra_pwrgood) -endmodule \ No newline at end of file +endmodule diff --git a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv index 960293743..5ed0446ca 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package soc_ifc_reg_pkg; + + localparam SOC_IFC_REG_DATA_WIDTH = 32; + localparam SOC_IFC_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic next; logic we; @@ -339,78 +343,78 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_inv_dev_sts_enable_e83f2724_next_8318aff8_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_inv_dev_sts_enable_e83f2724_next_8318aff8_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_cmd_fail_sts_enable_d535c05b_next_eee7e362_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_cmd_fail_sts_enable_d535c05b_next_eee7e362_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_bad_fuse_sts_enable_fceb289f_next_14761353_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_bad_fuse_sts_enable_fceb289f_next_14761353_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_iccm_blocked_sts_enable_4ccfea15_next_86c0a4d2_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_iccm_blocked_sts_enable_4ccfea15_next_86c0a4d2_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_mbox_ecc_unc_sts_enable_18d80a94_next_91af8aa5_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_mbox_ecc_unc_sts_enable_18d80a94_next_91af8aa5_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_wdt_timer1_timeout_sts_enable_fa7e6d0f_next_293a6067_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_wdt_timer1_timeout_sts_enable_fa7e6d0f_next_293a6067_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_wdt_timer2_timeout_sts_enable_38137b0c_next_1084f7bd_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_wdt_timer2_timeout_sts_enable_38137b0c_next_1084f7bd_resetsignal_f7aac87a__in_t; typedef struct packed{ - soc_ifc_reg__intr_block_t__error_intr_t__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_f7aac87a__in_t error_internal_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_inv_dev_sts_enable_e83f2724_next_8318aff8_resetsignal_f7aac87a__in_t error_inv_dev_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_cmd_fail_sts_enable_d535c05b_next_eee7e362_resetsignal_f7aac87a__in_t error_cmd_fail_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_bad_fuse_sts_enable_fceb289f_next_14761353_resetsignal_f7aac87a__in_t error_bad_fuse_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_iccm_blocked_sts_enable_4ccfea15_next_86c0a4d2_resetsignal_f7aac87a__in_t error_iccm_blocked_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_mbox_ecc_unc_sts_enable_18d80a94_next_91af8aa5_resetsignal_f7aac87a__in_t error_mbox_ecc_unc_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_wdt_timer1_timeout_sts_enable_fa7e6d0f_next_293a6067_resetsignal_f7aac87a__in_t error_wdt_timer1_timeout_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_wdt_timer2_timeout_sts_enable_38137b0c_next_1084f7bd_resetsignal_f7aac87a__in_t error_wdt_timer2_timeout_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_f7aac87a__in_t error_internal_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_inv_dev_sts_enable_e83f2724_next_8318aff8_resetsignal_f7aac87a__in_t error_inv_dev_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_cmd_fail_sts_enable_d535c05b_next_eee7e362_resetsignal_f7aac87a__in_t error_cmd_fail_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_bad_fuse_sts_enable_fceb289f_next_14761353_resetsignal_f7aac87a__in_t error_bad_fuse_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_iccm_blocked_sts_enable_4ccfea15_next_86c0a4d2_resetsignal_f7aac87a__in_t error_iccm_blocked_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_mbox_ecc_unc_sts_enable_18d80a94_next_91af8aa5_resetsignal_f7aac87a__in_t error_mbox_ecc_unc_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_wdt_timer1_timeout_sts_enable_fa7e6d0f_next_293a6067_resetsignal_f7aac87a__in_t error_wdt_timer1_timeout_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_wdt_timer2_timeout_sts_enable_38137b0c_next_1084f7bd_resetsignal_f7aac87a__in_t error_wdt_timer2_timeout_sts; } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__notif_intr_t__notif_cmd_avail_sts_enable_f40f37a0_next_6afe0a88__in_t; + } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_cmd_avail_sts_enable_f40f37a0_next_6afe0a88__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__notif_intr_t__notif_mbox_ecc_cor_sts_enable_c4f9db68_next_96c01bef__in_t; + } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_mbox_ecc_cor_sts_enable_c4f9db68_next_96c01bef__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__notif_intr_t__notif_debug_locked_sts_enable_097fcd5b_next_36fa44d8__in_t; + } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_debug_locked_sts_enable_097fcd5b_next_36fa44d8__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__notif_intr_t__notif_scan_mode_sts_enable_ed1d9036_next_eb34855d__in_t; + } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_scan_mode_sts_enable_ed1d9036_next_eb34855d__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__notif_intr_t__notif_soc_req_lock_sts_enable_52b75726_next_228b63de__in_t; + } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_soc_req_lock_sts_enable_52b75726_next_228b63de__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__notif_intr_t__notif_gen_in_toggle_sts_enable_9918ab15_next_e02c99b9__in_t; + } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_gen_in_toggle_sts_enable_9918ab15_next_e02c99b9__in_t; typedef struct packed{ - soc_ifc_reg__intr_block_t__notif_intr_t__notif_cmd_avail_sts_enable_f40f37a0_next_6afe0a88__in_t notif_cmd_avail_sts; - soc_ifc_reg__intr_block_t__notif_intr_t__notif_mbox_ecc_cor_sts_enable_c4f9db68_next_96c01bef__in_t notif_mbox_ecc_cor_sts; - soc_ifc_reg__intr_block_t__notif_intr_t__notif_debug_locked_sts_enable_097fcd5b_next_36fa44d8__in_t notif_debug_locked_sts; - soc_ifc_reg__intr_block_t__notif_intr_t__notif_scan_mode_sts_enable_ed1d9036_next_eb34855d__in_t notif_scan_mode_sts; - soc_ifc_reg__intr_block_t__notif_intr_t__notif_soc_req_lock_sts_enable_52b75726_next_228b63de__in_t notif_soc_req_lock_sts; - soc_ifc_reg__intr_block_t__notif_intr_t__notif_gen_in_toggle_sts_enable_9918ab15_next_e02c99b9__in_t notif_gen_in_toggle_sts; + soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_cmd_avail_sts_enable_f40f37a0_next_6afe0a88__in_t notif_cmd_avail_sts; + soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_mbox_ecc_cor_sts_enable_c4f9db68_next_96c01bef__in_t notif_mbox_ecc_cor_sts; + soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_debug_locked_sts_enable_097fcd5b_next_36fa44d8__in_t notif_debug_locked_sts; + soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_scan_mode_sts_enable_ed1d9036_next_eb34855d__in_t notif_scan_mode_sts; + soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_soc_req_lock_sts_enable_52b75726_next_228b63de__in_t notif_soc_req_lock_sts; + soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_gen_in_toggle_sts_enable_9918ab15_next_e02c99b9__in_t notif_gen_in_toggle_sts; } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__in_t; typedef struct packed{ @@ -1022,6 +1026,12 @@ package soc_ifc_reg_pkg; soc_ifc_reg__intr_block_t__out_t intr_block_rf; } soc_ifc_reg__out_t; + typedef enum logic [31:0] { + soc_ifc_reg__CPTRA_SECURITY_STATE__device_lifecycle_e__DEVICE_UNPROVISIONED = 'h0, + soc_ifc_reg__CPTRA_SECURITY_STATE__device_lifecycle_e__DEVICE_MANUFACTURING = 'h1, + soc_ifc_reg__CPTRA_SECURITY_STATE__device_lifecycle_e__DEVICE_PRODUCTION = 'h3 + } soc_ifc_reg__CPTRA_SECURITY_STATE__device_lifecycle_e_e; + localparam SOC_IFC_REG_ADDR_WIDTH = 32'd12; endpackage \ No newline at end of file diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv index a5d862690..28350fad0 100644 --- a/src/soc_ifc/rtl/soc_ifc_top.sv +++ b/src/soc_ifc/rtl/soc_ifc_top.sv @@ -843,10 +843,10 @@ i_mbox ( //------------------------- //Watchdog timer //------------------------- -assign timer1_en = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_EN.timer1_en; -assign timer2_en = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_EN.timer2_en; -assign timer1_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_CTRL.timer1_restart; -assign timer2_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_CTRL.timer2_restart; +assign timer1_en = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_EN.timer1_en.value; +assign timer2_en = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_EN.timer2_en.value; +assign timer1_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value; +assign timer2_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value; for (genvar i = 0; i < WDT_TIMEOUT_PERIOD_NUM_DWORDS; i++) begin assign timer1_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i].timer1_timeout_period.value; @@ -884,7 +884,7 @@ always_ff @(posedge soc_ifc_clk_cg or negedge cptra_noncore_rst_b) begin wdt_error_t1_intr_serviced <= 1'b0; wdt_error_t2_intr_serviced <= 1'b0; end - else if (soc_ifc_reg_req_dv && soc_ifc_reg_req_data.write && (soc_ifc_reg_req_data.addr[SOC_IFC_REG_ADDR_WIDTH-1:0] == `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R)) begin + else if (soc_ifc_reg_req_dv && soc_ifc_reg_req_data.write && (soc_ifc_reg_req_data.addr[SOC_IFC_REG_ADDR_WIDTH-1:0] == SOC_IFC_REG_ADDR_WIDTH'(`SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R))) begin wdt_error_t1_intr_serviced <= soc_ifc_reg_req_data.wdata[`SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_LOW] && t1_timeout; wdt_error_t2_intr_serviced <= soc_ifc_reg_req_data.wdata[`SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_LOW] && t2_timeout && timer2_en; end @@ -965,7 +965,7 @@ always_comb cptra_uncore_dmi_reg_rdata_in = ({32{(cptra_uncore_dmi_reg_addr == D ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_BOOT_STATUS)}} & soc_ifc_reg_hwif_out.CPTRA_BOOT_STATUS.status.value) | ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_HW_ERRROR_ENC)}} & soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_ENC.error_code.value) | ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_FW_ERROR_ENC)}} & soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_ENC.error_code.value) | - ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_BOOTFSM_GO)}} & soc_ifc_reg_hwif_out.CPTRA_BOOTFSM_GO.GO.value) | + ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_BOOTFSM_GO)}} & {31'b0, soc_ifc_reg_hwif_out.CPTRA_BOOTFSM_GO.GO.value}) | ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_DBG_MANUF_SERVICE_REG)}} & soc_ifc_reg_hwif_out.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value) ; //Increment the read pointer when we had a dmi read to data out and no access this clock diff --git a/src/spi_host/rtl/spi_host_reg_pkg.sv b/src/spi_host/rtl/spi_host_reg_pkg.sv index 3a5a9ba09..fe35abb5c 100644 --- a/src/spi_host/rtl/spi_host_reg_pkg.sv +++ b/src/spi_host/rtl/spi_host_reg_pkg.sv @@ -345,7 +345,7 @@ package spi_host_reg_pkg; parameter logic [31:0] SPI_HOST_TXDATA_TXDATA_RESVAL = 32'h 0; // Register index - typedef enum int { + typedef enum logic [31:0] { SPI_HOST_INTR_STATE, SPI_HOST_INTR_ENABLE, SPI_HOST_INTR_TEST, diff --git a/src/uart/rtl/uart_reg_pkg.sv b/src/uart/rtl/uart_reg_pkg.sv index 355afaff1..376414606 100644 --- a/src/uart/rtl/uart_reg_pkg.sv +++ b/src/uart/rtl/uart_reg_pkg.sv @@ -360,7 +360,7 @@ package uart_reg_pkg; parameter logic [15:0] UART_VAL_RESVAL = 16'h 0; // Register index - typedef enum int { + typedef enum logic [31:0] { UART_INTR_STATE, UART_INTR_ENABLE, UART_INTR_TEST, diff --git a/tools/scripts/rdl_post_process.py b/tools/scripts/rdl_post_process.py index 876c000ea..014fdbf30 100644 --- a/tools/scripts/rdl_post_process.py +++ b/tools/scripts/rdl_post_process.py @@ -39,6 +39,7 @@ def scrub_line_by_line(fname): has_struct = re.search(r'\bstruct\b\s*(?:unpacked)?', line) is_endmodule = re.search(r'\bendmodule\b', line) has_reset = re.search(r'\bnegedge\b', line) + has_enum = re.search(r'\btypedef enum\b', line) if (has_reset is not None and found_hard_reset is None): substring = re.search(r"negedge (\w+.\w+)", line) reset_name = substring.group(1) @@ -49,6 +50,10 @@ def scrub_line_by_line(fname): # only want to scrub signal definitions for unpacked arrays if (has_assign is not None or has_reg_strb is not None): mod_lines+=line + elif (has_enum is not None): + line = re.sub('enum', 'enum logic [31:0]', line) + mod_lines+=line + mod_cnt+=1 elif (has_struct is not None): line = re.sub(r'(\bstruct\b)\s*(?:unpacked)?', r'\1 packed', line) mod_lines+=line diff --git a/tools/scripts/reg_gen.py b/tools/scripts/reg_gen.py index eed084da1..2bb316453 100644 --- a/tools/scripts/reg_gen.py +++ b/tools/scripts/reg_gen.py @@ -39,6 +39,7 @@ from math import log, ceil, floor import sys import os +import re import rdl_post_process #output directory for dumping files @@ -57,7 +58,7 @@ def enter_Addrmap(self,node): pkg_file_path = str(self.regfile_name + "_pkg.sv") self.file = open(pkg_file_path, 'r') for line in self.file.readlines(): - if (line != "endpackage"): + if (re.search(r'\bendpackage\b', line) is None): self.orig_file += line self.file.close() self.file = open(pkg_file_path, 'w')