From fae37d00c69675cc0865c335d2f2b6fe0aa1ed37 Mon Sep 17 00:00:00 2001 From: Caleb Whitehead Date: Thu, 28 Mar 2024 16:50:31 -0700 Subject: [PATCH] Squashed commit of the following: commit e08900ff26f6daede9825bb4a9e184318fa10d87 Author: Michael Norris Date: Thu Mar 28 11:00:58 2024 -0700 rolling back packed struct removal enabling lint on integrated TRNG files fixes for integrated TRNG lint violations commit 75ecd6c6209b50ae5150e59e0a8eff0424212c8c Author: Michael Norris Date: Wed Mar 27 12:59:24 2024 -0700 fixing lint errors from LMS changes commit 3049b981e425e9e4e3dad289034943cfaf3dc954 Author: Caleb Whitehead Date: Thu Mar 28 16:44:43 2024 -0700 Squashed commit of the following: commit f03b9ba6a1434319f39a02f9c3a2ea75f17030f3 Merge: bc73a526 55f5f95f Author: Michael Norris Date: Wed Mar 27 12:51:20 2024 -0700 Merge remote-tracking branch 'chips/main' into user/dev/michnorris/lint_fix commit bc73a5263e368a7b320737c471dabee552684495 Author: Michael Norris Date: Wed Mar 27 12:45:42 2024 -0700 removing change from other lint pr branch, not sure where it came from. commit 697a74059d37eb2dfc86346f859ae90dd9aa7b68 Author: Michael Norris Date: Wed Mar 27 12:20:42 2024 -0700 removing lint blackboxes removed packed struct post processing from generated reg files. cast width of dynamic shifts to make lint happy casting some arithmetic widths, math parameter widths etc commit a16581dde8fe2cfaf849127ac337ac6d7ff15abe Author: Michael Norris Date: Tue Mar 26 15:00:06 2024 -0700 initial round of lint fixes --- src/aes/config/compile.yml | 4 ++ src/aes/rtl/aes_pkg.sv | 2 +- src/aes/rtl/aes_reg_pkg.sv | 2 +- .../rtl/caliptra_prim_packer_fifo.sv | 2 +- src/caliptra_prim/rtl/caliptra_prim_pkg.sv | 2 +- src/csrng/config/compile.yml | 5 +++ src/csrng/rtl/csrng_reg_pkg.sv | 2 +- src/datavault/config/compile.yml | 2 - src/doe/config/compile.yml | 2 - src/ecc/config/compile.yml | 2 - src/ecc/rtl/ecc_add_sub_mod_alter.sv | 2 +- src/ecc/rtl/ecc_dsa_ctrl.sv | 6 +-- src/entropy_src/config/compile.yml | 5 +++ src/entropy_src/rtl/entropy_src_reg_pkg.sv | 2 +- .../rtl/entropy_src_watermark_reg.sv | 33 +++++++++----- src/hmac/config/compile.yml | 2 - src/integration/asserts/caliptra_top_sva.sv | 44 +++++++++---------- src/integration/config/compile.yml | 4 +- src/integration/rtl/caliptra_top.sv | 5 ++- src/keyvault/config/compile.yml | 2 - src/keyvault/rtl/kv.sv | 2 +- src/keyvault/rtl/kv_fsm.sv | 23 ++++++++-- src/kmac/config/compile.yml | 4 ++ src/kmac/rtl/keccak_2share.sv | 12 ++--- src/pcrvault/config/compile.yml | 2 - src/pcrvault/rtl/pv_gen_hash.sv | 1 + src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv | 13 +++--- .../veer_el2/rtl/exu/el2_exu_alu_ctl.sv | 2 +- .../veer_el2/rtl/exu/el2_exu_mul_ctl.sv | 32 +++++++------- .../veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv | 4 +- .../veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv | 13 +++--- src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv | 2 +- .../veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv | 8 ++-- .../veer_el2/rtl/lsu/el2_lsu_bus_intf.sv | 2 +- .../veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv | 4 +- .../veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv | 2 +- src/sha256/config/compile.yml | 2 - src/sha256/rtl/sha256_reg.sv | 2 +- src/sha512/config/compile.yml | 2 - src/sha512_masked/config/compile.yml | 2 - src/soc_ifc/config/compile.yml | 9 ---- src/soc_ifc/rtl/mbox.sv | 23 +++++----- src/soc_ifc/rtl/sha512_acc_top.sv | 4 +- src/soc_ifc/rtl/soc_ifc_top.sv | 8 ++-- 44 files changed, 164 insertions(+), 144 deletions(-) diff --git a/src/aes/config/compile.yml b/src/aes/config/compile.yml index fc4379b07..445d407e6 100644 --- a/src/aes/config/compile.yml +++ b/src/aes/config/compile.yml @@ -39,3 +39,7 @@ targets: - $COMPILE_ROOT/rtl/aes_prng_masking.sv - $COMPILE_ROOT/rtl/aes_key_expand.sv tops: [aes_cipher_core] + rtl_lint: + directories: [] + waiver_files: [] + tops: [aes_cipher_core] diff --git a/src/aes/rtl/aes_pkg.sv b/src/aes/rtl/aes_pkg.sv index 170be20f2..1ec439032 100644 --- a/src/aes/rtl/aes_pkg.sv +++ b/src/aes/rtl/aes_pkg.sv @@ -68,7 +68,7 @@ parameter masking_lfsr_perm_t RndCnstMaskingLfsrPermDefault = { 256'h808d419d63982a16995e0e3b57826a36718a9329452492533d83115a75316e15 }; -typedef enum integer { +typedef enum logic [31:0] { SBoxImplLut, // Unmasked LUT-based S-Box SBoxImplCanright, // Unmasked Canright S-Box, see aes_sbox_canright.sv SBoxImplCanrightMasked, // First-order masked Canright S-Box diff --git a/src/aes/rtl/aes_reg_pkg.sv b/src/aes/rtl/aes_reg_pkg.sv index 657bc046a..d3b3d4b7d 100644 --- a/src/aes/rtl/aes_reg_pkg.sv +++ b/src/aes/rtl/aes_reg_pkg.sv @@ -336,7 +336,7 @@ package aes_reg_pkg; parameter logic [0:0] AES_CTRL_SHADOWED_MANUAL_OPERATION_RESVAL = 1'h 0; // Register index - typedef enum int { + typedef enum logic [31:0] { AES_ALERT_TEST, AES_KEY_SHARE0_0, AES_KEY_SHARE0_1, diff --git a/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv b/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv index 24fdd1429..7f0b2d364 100644 --- a/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv +++ b/src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv @@ -132,7 +132,7 @@ module caliptra_prim_packer_fifo #( assign lsb_is_one = {{DepthW{1'b0}},1'b1}; assign max_value = FullDepth; - assign rdata_shifted = data_q >> ptr_q*OutW; + assign rdata_shifted = MaxW'(data_q >> ptr_q*OutW); assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q; assign clear_data = (ClearOnRead && clear_status) || clr_q; assign load_data = wvalid_i && wready_o; diff --git a/src/caliptra_prim/rtl/caliptra_prim_pkg.sv b/src/caliptra_prim/rtl/caliptra_prim_pkg.sv index 97242c359..2d69a31dc 100755 --- a/src/caliptra_prim/rtl/caliptra_prim_pkg.sv +++ b/src/caliptra_prim/rtl/caliptra_prim_pkg.sv @@ -9,7 +9,7 @@ package caliptra_prim_pkg; // Implementation target specialization - typedef enum integer { + typedef enum logic [31:0] { ImplGeneric, ImplXilinx, ImplBadbit diff --git a/src/csrng/config/compile.yml b/src/csrng/config/compile.yml index 146c5653c..ebd6e931d 100644 --- a/src/csrng/config/compile.yml +++ b/src/csrng/config/compile.yml @@ -41,6 +41,11 @@ targets: - $COMPILE_ROOT/rtl/csrng_cmd_stage.sv - $COMPILE_ROOT/rtl/csrng.sv tops: [csrng] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/csrng/config/design_lint/sglint_waivers + tops: [csrng] --- provides: [csrng_tb] schema_version: 2.4.0 diff --git a/src/csrng/rtl/csrng_reg_pkg.sv b/src/csrng/rtl/csrng_reg_pkg.sv index aedce98b7..1b294fce6 100644 --- a/src/csrng/rtl/csrng_reg_pkg.sv +++ b/src/csrng/rtl/csrng_reg_pkg.sv @@ -364,7 +364,7 @@ package csrng_reg_pkg; parameter logic [31:0] CSRNG_INT_STATE_VAL_RESVAL = 32'h 0; // Register index - typedef enum int { + typedef enum logic [31:0] { CSRNG_INTR_STATE, CSRNG_INTR_ENABLE, CSRNG_INTR_TEST, diff --git a/src/datavault/config/compile.yml b/src/datavault/config/compile.yml index 2691979d4..76042b5b3 100644 --- a/src/datavault/config/compile.yml +++ b/src/datavault/config/compile.yml @@ -37,8 +37,6 @@ targets: directories: [] waiver_files: - $COMPILE_ROOT/config/design_lint/datavault/sglint_waivers - black_box: - - dv_reg global: tool: vcs: diff --git a/src/doe/config/compile.yml b/src/doe/config/compile.yml index 39c70d8c4..c02910420 100755 --- a/src/doe/config/compile.yml +++ b/src/doe/config/compile.yml @@ -39,8 +39,6 @@ targets: directories: [] waiver_files: - $COMPILE_ROOT/config/design_lint/doe_ctrl/sglint_waivers - black_box: - - doe_reg --- provides: [doe_cbc_tb] schema_version: 2.4.0 diff --git a/src/ecc/config/compile.yml b/src/ecc/config/compile.yml index 369d1ed2c..c33b55679 100755 --- a/src/ecc/config/compile.yml +++ b/src/ecc/config/compile.yml @@ -41,8 +41,6 @@ targets: directories: [] waiver_files: - $COMPILE_ROOT/config/design_lint/ecc_top/sglint_waivers - black_box: - - ecc_reg --- provides: [ecc_top_tb] schema_version: 2.4.0 diff --git a/src/ecc/rtl/ecc_add_sub_mod_alter.sv b/src/ecc/rtl/ecc_add_sub_mod_alter.sv index 2bf3eb332..ae11bcbe6 100644 --- a/src/ecc/rtl/ecc_add_sub_mod_alter.sv +++ b/src/ecc/rtl/ecc_add_sub_mod_alter.sv @@ -105,7 +105,7 @@ module ecc_add_sub_mod_alter #( else if (add_en_i) push_result_reg <= 2'b10; else // one shift to right - push_result_reg <= (push_result_reg >> 1); + push_result_reg <= 2'(push_result_reg >> 1); end assign ready_o = push_result_reg[0]; diff --git a/src/ecc/rtl/ecc_dsa_ctrl.sv b/src/ecc/rtl/ecc_dsa_ctrl.sv index 1dcb6dfae..c4a9c5b1d 100644 --- a/src/ecc/rtl/ecc_dsa_ctrl.sv +++ b/src/ecc/rtl/ecc_dsa_ctrl.sv @@ -297,7 +297,7 @@ module ecc_dsa_ctrl always_comb begin : SCA_config - scalar_out_reg = (sca_scalar_rnd_en)? scalar_out : (scalar_in_reg << RND_SIZE); + scalar_out_reg = (sca_scalar_rnd_en)? scalar_out : (REG_SIZE+RND_SIZE)'(scalar_in_reg << RND_SIZE); lambda_reg = (sca_point_rnd_en)? lambda : ONE_CONST; masking_rnd_reg = (sca_mask_sign_en)? masking_rnd : ZERO_CONST; end // SCA_config @@ -595,8 +595,8 @@ module ecc_dsa_ctrl end else if (prog_instr.opcode == DSA_UOP_WR_SCALAR) begin unique case (prog_instr.reg_id) - SCALAR_PK_ID : write_reg = (scalar_PK_reg << RND_SIZE); - SCALAR_G_ID : write_reg = (scalar_G_reg << RND_SIZE); + SCALAR_PK_ID : write_reg = (REG_SIZE+RND_SIZE)'(scalar_PK_reg << RND_SIZE); + SCALAR_G_ID : write_reg = (REG_SIZE+RND_SIZE)'(scalar_G_reg << RND_SIZE); SCALAR_ID : write_reg = scalar_out_reg; // SCA default : write_reg = '0; endcase diff --git a/src/entropy_src/config/compile.yml b/src/entropy_src/config/compile.yml index 9cdb9c50a..d74440352 100644 --- a/src/entropy_src/config/compile.yml +++ b/src/entropy_src/config/compile.yml @@ -43,6 +43,11 @@ targets: - $COMPILE_ROOT/rtl/entropy_src_ack_sm.sv - $COMPILE_ROOT/rtl/entropy_src.sv tops: [entropy_src] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/entropy_src/config/design_lint/sglint_waivers + tops: [entropy_src] tb: directories: [$COMPILE_ROOT/tb] files: diff --git a/src/entropy_src/rtl/entropy_src_reg_pkg.sv b/src/entropy_src/rtl/entropy_src_reg_pkg.sv index b95a710cf..d85cc0949 100644 --- a/src/entropy_src/rtl/entropy_src_reg_pkg.sv +++ b/src/entropy_src/rtl/entropy_src_reg_pkg.sv @@ -893,7 +893,7 @@ package entropy_src_reg_pkg; parameter logic [0:0] ENTROPY_SRC_DEBUG_STATUS_MAIN_SM_IDLE_RESVAL = 1'h 1; // Register index - typedef enum int { + typedef enum logic [31:0] { ENTROPY_SRC_INTR_STATE, ENTROPY_SRC_INTR_ENABLE, ENTROPY_SRC_INTR_TEST, diff --git a/src/entropy_src/rtl/entropy_src_watermark_reg.sv b/src/entropy_src/rtl/entropy_src_watermark_reg.sv index ae9cd1022..1b9e094c9 100644 --- a/src/entropy_src/rtl/entropy_src_watermark_reg.sv +++ b/src/entropy_src/rtl/entropy_src_watermark_reg.sv @@ -26,29 +26,40 @@ module entropy_src_watermark_reg #( // flops logic [RegWidth-1:0] event_cntr_q, event_cntr_d; - always_ff @(posedge clk_i or negedge rst_ni) - if (!rst_ni) begin - event_cntr_q <= reg_reset; - end else begin - event_cntr_q <= event_cntr_d; - end - - assign event_cntr_d = clear_i ? reg_reset : - event_i ? event_cntr_change : - event_cntr_q; - // Set mode of this counter to be either a high or low watermark if (HighWatermark) begin : gen_hi_wm assign reg_reset = {RegWidth{1'b0}}; assign event_cntr_change = (value_i > event_cntr_q) ? (value_i) : event_cntr_q; + + assign event_cntr_d = clear_i ? reg_reset : + event_i ? event_cntr_change : + event_cntr_q; + + always_ff @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + event_cntr_q <= {RegWidth{1'b0}}; + end else begin + event_cntr_q <= event_cntr_d; + end end else begin : gen_lo_wm assign reg_reset = {RegWidth{1'b1}}; assign event_cntr_change = (value_i < event_cntr_q) ? (value_i) : event_cntr_q; + + assign event_cntr_d = clear_i ? reg_reset : + event_i ? event_cntr_change : + event_cntr_q; + + always_ff @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + event_cntr_q <= {RegWidth{1'b1}}; + end else begin + event_cntr_q <= event_cntr_d; + end end diff --git a/src/hmac/config/compile.yml b/src/hmac/config/compile.yml index 181ae1ce8..ebf83e4b5 100755 --- a/src/hmac/config/compile.yml +++ b/src/hmac/config/compile.yml @@ -20,8 +20,6 @@ targets: directories: [] waiver_files: - $COMPILE_ROOT/config/design_lint/hmac_ctrl/sglint_waivers - black_box: - - hmac_reg --- provides: [hmac_ctrl_tb] schema_version: 2.4.0 diff --git a/src/integration/asserts/caliptra_top_sva.sv b/src/integration/asserts/caliptra_top_sva.sv index cdb92c125..9cdebe7ba 100644 --- a/src/integration/asserts/caliptra_top_sva.sv +++ b/src/integration/asserts/caliptra_top_sva.sv @@ -131,14 +131,14 @@ module caliptra_top_sva KV_debug_value0: assert property ( @(posedge `SVA_RDC_CLK) disable iff(!`KEYVAULT_PATH.cptra_pwrgood) - $rose(~`CPTRA_TOP_PATH.cptra_security_state_Latched.debug_locked || `SOC_IFC_TOP_PATH.cptra_error_fatal || `CPTRA_TOP_PATH.cptra_scan_mode_Latched) && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 0) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword] == CLP_DEBUG_MODE_KV_0) + $rose(~`CPTRA_TOP_PATH.cptra_security_state_Latched.debug_locked || `SOC_IFC_TOP_PATH.cptra_error_fatal || `CPTRA_TOP_PATH.cptra_scan_mode_Latched) && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 0) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword].data.value == CLP_DEBUG_MODE_KV_0) ) else $display("SVA ERROR: KV not flushed with correct debug values"); KV_debug_value1: assert property ( @(posedge `SVA_RDC_CLK) disable iff(!`KEYVAULT_PATH.cptra_pwrgood) - $rose(~`CPTRA_TOP_PATH.cptra_security_state_Latched.debug_locked || `SOC_IFC_TOP_PATH.cptra_error_fatal || `CPTRA_TOP_PATH.cptra_scan_mode_Latched) && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 1) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword] == CLP_DEBUG_MODE_KV_1) + $rose(~`CPTRA_TOP_PATH.cptra_security_state_Latched.debug_locked || `SOC_IFC_TOP_PATH.cptra_error_fatal || `CPTRA_TOP_PATH.cptra_scan_mode_Latched) && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 1) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword].data.value == CLP_DEBUG_MODE_KV_1) ) else $display("SVA ERROR: KV not flushed with correct debug values"); end @@ -150,42 +150,42 @@ module caliptra_top_sva //sha512 block read kv_sha512_block_r_flow: assert property ( @(posedge `SVA_RDC_CLK) - $rose(`SHA512_PATH.kv_src_done & ~`SHA512_PATH.pcr_hash_extend_ip) && (dword < (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_CTRL[`SHA512_PATH.kv_read.read_entry].last_dword + 1)) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_read.read_entry][dword] == `SHA512_PATH.block_reg[dword]) + $rose(`SHA512_PATH.kv_src_done & ~`SHA512_PATH.pcr_hash_extend_ip) && (dword < (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_CTRL[`SHA512_PATH.kv_read.read_entry].last_dword.value + 1)) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_read.read_entry][dword].data.value == `SHA512_PATH.block_reg[dword]) ) - else $display("SVA ERROR: SHA384 block mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_read.read_entry][dword], `SHA512_PATH.block_reg[dword]); + else $display("SVA ERROR: SHA384 block mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_read.read_entry][dword].data.value, `SHA512_PATH.block_reg[dword]); //sha512 digest write if (dword < SHA512_DIG_NUM_DWORDS) begin kv_sha512_digest_w_flow: assert property ( @(posedge `SVA_RDC_CLK) - `SHA512_PATH.kv_dest_done & ~`SHA512_PATH.pcr_hash_extend_ip |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_write_ctrl_reg.write_entry][dword] == `SHA512_PATH.kv_reg[(KV_NUM_DWORDS-1) - dword]) + `SHA512_PATH.kv_dest_done & ~`SHA512_PATH.pcr_hash_extend_ip |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_write_ctrl_reg.write_entry][dword].data.value == `SHA512_PATH.kv_reg[(KV_NUM_DWORDS-1) - dword]) ) - else $display("SVA ERROR: SHA384 digest mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_write_ctrl_reg.write_entry][dword], `SHA512_PATH.kv_reg[(KV_NUM_DWORDS-1) - dword]); + else $display("SVA ERROR: SHA384 digest mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_write_ctrl_reg.write_entry][dword].data.value, `SHA512_PATH.kv_reg[(KV_NUM_DWORDS-1) - dword]); end //hmac block read kv_hmac_block_r_flow: assert property ( @(posedge `SVA_RDC_CLK) - $rose(`HMAC_PATH.kv_block_done) && (dword < (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_CTRL[`HMAC_PATH.kv_read[1].read_entry].last_dword + 1)) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[1].read_entry][dword] == `HMAC_PATH.block_reg[dword]) + $rose(`HMAC_PATH.kv_block_done) && (dword < (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_CTRL[`HMAC_PATH.kv_read[1].read_entry].last_dword.value + 1)) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[1].read_entry][dword].data.value == `HMAC_PATH.block_reg[dword]) ) - else $display("SVA ERROR: HMAC384 block mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[1].read_entry][dword], `HMAC_PATH.block_reg[dword]); + else $display("SVA ERROR: HMAC384 block mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[1].read_entry][dword].data.value, `HMAC_PATH.block_reg[dword]); //hmac key read if (dword < HMAC_KEY_NUM_DWORDS) begin kv_hmac_key_r_flow: assert property ( @(posedge `SVA_RDC_CLK) - $fell(`HMAC_PATH.kv_key_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[0].read_entry][dword] == `HMAC_PATH.key_reg[dword]) + $fell(`HMAC_PATH.kv_key_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[0].read_entry][dword].data.value == `HMAC_PATH.key_reg[dword]) ) - else $display("SVA ERROR: HMAC384 key mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[0].read_entry][dword], `HMAC_PATH.key_reg[dword]); + else $display("SVA ERROR: HMAC384 key mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[0].read_entry][dword].data.value, `HMAC_PATH.key_reg[dword]); end //hmac tag write if (dword < HMAC_TAG_NUM_DWORDS) begin kv_hmac_tag_w_flow: assert property ( @(posedge `SVA_RDC_CLK) - `HMAC_PATH.kv_write_done |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_write_ctrl_reg.write_entry][dword] == `HMAC_PATH.kv_reg[(`HMAC_PATH.TAG_NUM_DWORDS-1) - dword]) + `HMAC_PATH.kv_write_done |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_write_ctrl_reg.write_entry][dword].data.value == `HMAC_PATH.kv_reg[(`HMAC_PATH.TAG_NUM_DWORDS-1) - dword]) ) - else $display("SVA ERROR: HMAC384 tag mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_write_ctrl_reg.write_entry][dword], `HMAC_PATH.kv_reg[(`HMAC_PATH.TAG_NUM_DWORDS-1) - dword]); + else $display("SVA ERROR: HMAC384 tag mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_write_ctrl_reg.write_entry][dword].data.value, `HMAC_PATH.kv_reg[(`HMAC_PATH.TAG_NUM_DWORDS-1) - dword]); end // ECC @@ -193,20 +193,20 @@ module caliptra_top_sva //ecc privkey read kv_ecc_privkey_r_flow: assert property ( @(posedge `SVA_RDC_CLK) - $fell(`ECC_PATH.kv_privkey_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[0].read_entry][dword] == `ECC_PATH.privkey_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) + $fell(`ECC_PATH.kv_privkey_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[0].read_entry][dword].data.value == `ECC_PATH.privkey_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) ) - else $display("SVA ERROR: ECC privkey read mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[0].read_entry][dword], `ECC_PATH.privkey_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); + else $display("SVA ERROR: ECC privkey read mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[0].read_entry][dword].data.value, `ECC_PATH.privkey_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); kv_ecc_seed_r_flow: assert property ( @(posedge `SVA_RDC_CLK) - $fell(`ECC_PATH.kv_seed_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[1].read_entry][dword] == `ECC_PATH.seed_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) + $fell(`ECC_PATH.kv_seed_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[1].read_entry][dword].data.value == `ECC_PATH.seed_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) ) - else $display("SVA ERROR: ECC seed mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[1].read_entry][dword], `ECC_PATH.seed_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); + else $display("SVA ERROR: ECC seed mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[1].read_entry][dword].data.value, `ECC_PATH.seed_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); //ecc privkey write kv_ecc_privkey_w_flow: assert property ( @(posedge `SVA_RDC_CLK) - `ECC_PATH.kv_write_done |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_write_ctrl_reg.write_entry][dword] == `ECC_PATH.kv_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) + `ECC_PATH.kv_write_done |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_write_ctrl_reg.write_entry][dword].data.value == `ECC_PATH.kv_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) ) - else $display("SVA ERROR: ECC privkey write mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_write_ctrl_reg.write_entry][dword], `ECC_PATH.kv_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); + else $display("SVA ERROR: ECC privkey write mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_write_ctrl_reg.write_entry][dword].data.value, `ECC_PATH.kv_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); //ecc sign r pcr_ecc_sign_r: assert property ( @@ -232,10 +232,10 @@ module caliptra_top_sva DOE_UDS_data_check: assert property ( @(posedge `SVA_RDC_CLK) disable iff (`CPTRA_TOP_PATH.scan_mode || !`CPTRA_TOP_PATH.security_state.debug_locked) - (`SERVICES_PATH.WriteData == 'hEC && `SERVICES_PATH.mailbox_write) |=> ##[1:$] $rose(`DOE_PATH.lock_uds_flow) |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword] == `SERVICES_PATH.doe_test_vector.uds_plaintext[dword]) + (`SERVICES_PATH.WriteData == 'hEC && `SERVICES_PATH.mailbox_write) |=> ##[1:$] $rose(`DOE_PATH.lock_uds_flow) |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword].data.value == `SERVICES_PATH.doe_test_vector.uds_plaintext[dword]) ) - else $display("SVA ERROR: DOE UDS output %h does not match plaintext %h!", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword], `SERVICES_PATH.doe_test_vector.uds_plaintext[dword]); + else $display("SVA ERROR: DOE UDS output %h does not match plaintext %h!", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword].data.value, `SERVICES_PATH.doe_test_vector.uds_plaintext[dword]); end end endgenerate @@ -246,9 +246,9 @@ module caliptra_top_sva DOE_FE_data_check: assert property ( @(posedge `SVA_RDC_CLK) disable iff (`CPTRA_TOP_PATH.scan_mode || !`CPTRA_TOP_PATH.security_state.debug_locked) - (`SERVICES_PATH.WriteData == 'hED && `SERVICES_PATH.mailbox_write) |=> ##[1:$] $rose(`DOE_PATH.lock_fe_flow) |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword] == `SERVICES_PATH.doe_test_vector.fe_plaintext[dword]) + (`SERVICES_PATH.WriteData == 'hED && `SERVICES_PATH.mailbox_write) |=> ##[1:$] $rose(`DOE_PATH.lock_fe_flow) |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword].data.value == `SERVICES_PATH.doe_test_vector.fe_plaintext[dword]) ) - else $display("SVA ERROR: DOE FE output %h does not match plaintext %h!", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword], `SERVICES_PATH.doe_test_vector.fe_plaintext[dword]); + else $display("SVA ERROR: DOE FE output %h does not match plaintext %h!", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword].data.value, `SERVICES_PATH.doe_test_vector.fe_plaintext[dword]); end end diff --git a/src/integration/config/compile.yml b/src/integration/config/compile.yml index ef8f9ca6f..90c060828 100644 --- a/src/integration/config/compile.yml +++ b/src/integration/config/compile.yml @@ -46,8 +46,8 @@ targets: rtl_lint: waiver_files: - $COMPILE_ROOT/config/design_lint/sglint_waivers - black_box: - - el2_veer_wrapper + options: + - '+define+CALIPTRA_INTERNAL_TRNG' cdc: tcl_files: - $COMPILE_ROOT/config/cdc/integration_top.constraints.tcl diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv index 223697994..675069035 100755 --- a/src/integration/rtl/caliptra_top.sv +++ b/src/integration/rtl/caliptra_top.sv @@ -269,6 +269,7 @@ module caliptra_top logic lsu_addr_ph, lsu_data_ph, lsu_sel; logic ic_addr_ph, ic_data_ph, ic_sel; + always_comb begin mbox_sram_cs = mbox_sram_req.cs; mbox_sram_we = mbox_sram_req.we; @@ -325,8 +326,8 @@ end .hclk ( clk_cg ), .hreset_n ( cptra_noncore_rst_b ), .force_bus_idle ( fw_update_rst_window ), - .ahb_lite_responders ( responder_inst ), - .ahb_lite_initiator ( initiator_inst ), + .ahb_lite_responders ( responder_inst.Responder_Interface_Ports), + .ahb_lite_initiator ( initiator_inst.Initiator_Interface_Ports), .ahb_lite_resp_disable_i ( ahb_lite_resp_disable ), .ahb_lite_resp_access_blocked_o( ahb_lite_resp_access_blocked), .ahb_lite_start_addr_i ( `CALIPTRA_SLAVE_BASE_ADDR ), diff --git a/src/keyvault/config/compile.yml b/src/keyvault/config/compile.yml index e0d516e0e..07c51a361 100644 --- a/src/keyvault/config/compile.yml +++ b/src/keyvault/config/compile.yml @@ -53,8 +53,6 @@ targets: directories: [] waiver_files: - $COMPILE_ROOT/config/design_lint/keyvault/sglint_waivers - black_box: - - kv_reg global: tool: vcs: diff --git a/src/keyvault/rtl/kv.sv b/src/keyvault/rtl/kv.sv index 72424ad26..e92ad0838 100644 --- a/src/keyvault/rtl/kv.sv +++ b/src/keyvault/rtl/kv.sv @@ -215,7 +215,7 @@ always_comb begin : keyvault_readmux kv_reg_hwif_out.KEY_ENTRY[entry][dword].data.value : '0; end //signal last when reading the last dword - kv_rd_resp[client].last |= (kv_read[client].read_entry == entry) & (kv_read[client].read_offset == kv_reg_hwif_out.KEY_CTRL[entry].last_dword); + kv_rd_resp[client].last |= (kv_read[client].read_entry == entry) & (kv_read[client].read_offset == kv_reg_hwif_out.KEY_CTRL[entry].last_dword.value); kv_rd_resp[client].error |= (kv_read[client].read_entry == entry) & (lock_use_q[entry] | ~kv_reg_hwif_out.KEY_CTRL[entry].dest_valid.value[client]); end diff --git a/src/keyvault/rtl/kv_fsm.sv b/src/keyvault/rtl/kv_fsm.sv index 7b7ca330a..675c0b343 100644 --- a/src/keyvault/rtl/kv_fsm.sv +++ b/src/keyvault/rtl/kv_fsm.sv @@ -155,22 +155,37 @@ always_ff @(posedge clk or negedge rst_b) begin if (!rst_b) begin kv_fsm_ps <= KV_IDLE; offset <= '0; - num_dwords_data <= '0; end else if (zeroize) begin kv_fsm_ps <= KV_IDLE; offset <= '0; - num_dwords_data <= '0; end else begin kv_fsm_ps <= kv_fsm_ns; offset <= offset_rst ? '0 : offset_en ? offset_nxt : offset; - //store the offset_nxt on the last cycle of valid data, this is the number of dwords of valid data - num_dwords_data <= arc_KV_RW_KV_PAD ? offset_nxt : num_dwords_data; end end +generate + if (PAD==1) begin + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + num_dwords_data <= '0; + end + else if (zeroize) begin + num_dwords_data <= '0; + end + else begin + //store the offset_nxt on the last cycle of valid data, this is the number of dwords of valid data + num_dwords_data <= arc_KV_RW_KV_PAD ? offset_nxt : num_dwords_data; + end + end + end else begin + always_comb num_dwords_data = '0; + end +endgenerate + always_comb read_offset = (kv_fsm_ps == KV_RW) ? offset[OFFSET_W-1:0] : '0; always_comb write_offset = offset[OFFSET_W-1:0]; diff --git a/src/kmac/config/compile.yml b/src/kmac/config/compile.yml index 7280c6a78..1c1e66774 100644 --- a/src/kmac/config/compile.yml +++ b/src/kmac/config/compile.yml @@ -22,3 +22,7 @@ targets: - $COMPILE_ROOT/rtl/sha3pad.sv - $COMPILE_ROOT/rtl/sha3.sv tops: [sha3] + rtl_lint: + directories: [] + waiver_files: [] + tops: [sha3] diff --git a/src/kmac/rtl/keccak_2share.sv b/src/kmac/rtl/keccak_2share.sv index ff25c2d0a..79f866e68 100644 --- a/src/kmac/rtl/keccak_2share.sv +++ b/src/kmac/rtl/keccak_2share.sv @@ -479,8 +479,8 @@ module keccak_2share // C[x,z] = A[x,0,z] ^ A[x,1,z] ^ A[x,2,z] ^ A[x,3,z] ^ A[x,4,z] // D[x,z] = C[x-1,z] ^ C[x+1,z-1] // theta = A[x,y,z] ^ D[x,z] - parameter int ThetaIndexX1 [5] = '{4, 0, 1, 2, 3}; // (x-1)%5 - parameter int ThetaIndexX2 [5] = '{1, 2, 3, 4, 0}; // (x+1)%5 + parameter logic [2:0] ThetaIndexX1 [5] = '{4, 0, 1, 2, 3}; // (x-1)%5 + parameter logic [2:0] ThetaIndexX2 [5] = '{1, 2, 3, 4, 0}; // (x+1)%5 function automatic box_t theta(box_t state); plane_t c; plane_t d; @@ -490,7 +490,7 @@ module keccak_2share end for (int x = 0 ; x < 5 ; x++) begin for (int z = 0 ; z < W ; z++) begin - int index_z; + logic [$clog2(W)-1:0] index_z; index_z = (z == 0) ? W-1 : z-1; // (z+1)%W d[x][z] = c[ThetaIndexX1[x]][z] ^ c[ThetaIndexX2[x]][index_z]; end @@ -544,7 +544,7 @@ module keccak_2share // pi // rearrange the position of lanes // pi[x,y,z] = state[(x+3y),x,z] - localparam int PiRotate [5][5] = '{ + localparam logic [2:0] PiRotate [5][5] = '{ //y 0 1 2 3 4 x '{ 0, 3, 1, 4, 2},// 0 '{ 1, 4, 2, 0, 3},// 1 @@ -564,8 +564,8 @@ module keccak_2share // chi // chi[x,y,z] = state[x,y,z] ^ ((state[x+1,y,z] ^ 1) & state[x+2,y,z]) - parameter int ChiIndexX1 [5] = '{1, 2, 3, 4, 0}; // (x+1)%5 - parameter int ChiIndexX2 [5] = '{2, 3, 4, 0, 1}; // (x+2)%5 + parameter logic [2:0] ChiIndexX1 [5] = '{1, 2, 3, 4, 0}; // (x+1)%5 + parameter logic [2:0] ChiIndexX2 [5] = '{2, 3, 4, 0, 1}; // (x+2)%5 function automatic box_t chi(box_t state); box_t result; for (int x = 0 ; x < 5 ; x++) begin diff --git a/src/pcrvault/config/compile.yml b/src/pcrvault/config/compile.yml index 8e17ba963..c5a5aa2d3 100644 --- a/src/pcrvault/config/compile.yml +++ b/src/pcrvault/config/compile.yml @@ -53,8 +53,6 @@ targets: directories: [] waiver_files: - $COMPILE_ROOT/config/design_lint/pcrvault/sglint_waivers - black_box: - - pv_reg global: tool: vcs: diff --git a/src/pcrvault/rtl/pv_gen_hash.sv b/src/pcrvault/rtl/pv_gen_hash.sv index 5ce7fb8b2..990fe9e73 100644 --- a/src/pcrvault/rtl/pv_gen_hash.sv +++ b/src/pcrvault/rtl/pv_gen_hash.sv @@ -199,6 +199,7 @@ assign block_offset = block_offset_i[BLOCK_OFFSET_W-1:0]; if (~rst_b) begin gen_hash_fsm_ps <= GEN_HASH_IDLE; block_offset_i <= '0; + nonce_offset_i <= '0; read_entry <= '0; read_offset <= '0; end diff --git a/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv b/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv index 1398a10bd..9e247035a 100644 --- a/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv +++ b/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv @@ -308,12 +308,13 @@ import el2_pkg::*; // Error logic assign dma_address_error = fifo_valid[RdPtr] & ~fifo_done[RdPtr] & ~fifo_dbg[RdPtr] & (~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm)); // request not for ICCM or DCCM assign dma_alignment_error = fifo_valid[RdPtr] & ~fifo_done[RdPtr] & ~fifo_dbg[RdPtr] & ~dma_address_error & - (((dma_mem_sz_int[2:0] == 3'h1) & dma_mem_addr_int[0]) | // HW size but unaligned - ((dma_mem_sz_int[2:0] == 3'h2) & (|dma_mem_addr_int[1:0])) | // W size but unaligned - ((dma_mem_sz_int[2:0] == 3'h3) & (|dma_mem_addr_int[2:0])) | // DW size but unaligned - (dma_mem_addr_in_iccm & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11))) | // ICCM access not word size - (dma_mem_addr_in_dccm & dma_mem_write & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11))) | // DCCM write not word size - (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h2) & (dma_mem_byteen[dma_mem_addr_int[2:0]+:4] != 4'hf)) | // Write byte enables not aligned for word store + (((dma_mem_sz_int[2:0] == 3'h1) & dma_mem_addr_int[0]) | // HW size but unaligned + ((dma_mem_sz_int[2:0] == 3'h2) & (|dma_mem_addr_int[1:0])) | // W size but unaligned + ((dma_mem_sz_int[2:0] == 3'h3) & (|dma_mem_addr_int[2:0])) | // DW size but unaligned + (dma_mem_addr_in_iccm & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11))) | // ICCM access not word size + (dma_mem_addr_in_dccm & dma_mem_write & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11))) | // DCCM write not word size + (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h2) & (dma_mem_addr_int[2:0] == 3'h0) & (dma_mem_byteen[3:0] != 4'hf)) | // Write byte enables not aligned for word store + (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h2) & (dma_mem_addr_int[2:0] == 3'h4) & (dma_mem_byteen[7:4] != 4'hf)) | // Write byte enables not aligned for word store (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h3) & ~((dma_mem_byteen[7:0] == 8'h0f) | (dma_mem_byteen[7:0] == 8'hf0) | (dma_mem_byteen[7:0] == 8'hff)))); // Write byte enables not aligned for dword store diff --git a/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv b/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv index 00234ef6c..749077f3b 100644 --- a/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/exu/el2_exu_alu_ctl.sv @@ -302,7 +302,7 @@ import el2_pkg::*; ( {31{ap_ror}} & a_in[30:0] ); - assign shift_long[62:0] = ( shift_extend[62:0] >> shift_amount[4:0] ); // 62-32 unused + assign shift_long[62:0] = 63'( shift_extend[62:0] >> shift_amount[4:0] ); // 62-32 unused assign sout[31:0] = shift_long[31:0] & shift_mask[31:0]; diff --git a/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv b/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv index e47a7d827..48e00b37b 100644 --- a/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/exu/el2_exu_mul_ctl.sv @@ -523,22 +523,22 @@ import el2_pkg::*; logic [31:0] xperm_b; logic [31:0] xperm_h; - assign xperm_n[03:00] = { 4{ ~rs2_in[03] }} & ( (rs1_in[31:0] >> {rs2_in[02:00],2'b0}) & 4'hf ); // This is a 8:1 mux with qualified selects - assign xperm_n[07:04] = { 4{ ~rs2_in[07] }} & ( (rs1_in[31:0] >> {rs2_in[06:04],2'b0}) & 4'hf ); - assign xperm_n[11:08] = { 4{ ~rs2_in[11] }} & ( (rs1_in[31:0] >> {rs2_in[10:08],2'b0}) & 4'hf ); - assign xperm_n[15:12] = { 4{ ~rs2_in[15] }} & ( (rs1_in[31:0] >> {rs2_in[14:12],2'b0}) & 4'hf ); - assign xperm_n[19:16] = { 4{ ~rs2_in[19] }} & ( (rs1_in[31:0] >> {rs2_in[18:16],2'b0}) & 4'hf ); - assign xperm_n[23:20] = { 4{ ~rs2_in[23] }} & ( (rs1_in[31:0] >> {rs2_in[22:20],2'b0}) & 4'hf ); - assign xperm_n[27:24] = { 4{ ~rs2_in[27] }} & ( (rs1_in[31:0] >> {rs2_in[26:24],2'b0}) & 4'hf ); - assign xperm_n[31:28] = { 4{ ~rs2_in[31] }} & ( (rs1_in[31:0] >> {rs2_in[30:28],2'b0}) & 4'hf ); - - assign xperm_b[07:00] = { 8{ ~(| rs2_in[07:02]) }} & ( (rs1_in[31:0] >> {rs2_in[01:00],3'b0}) & 8'hff ); // This is a 4:1 mux with qualified selects - assign xperm_b[15:08] = { 8{ ~(| rs2_in[15:10]) }} & ( (rs1_in[31:0] >> {rs2_in[09:08],3'b0}) & 8'hff ); - assign xperm_b[23:16] = { 8{ ~(| rs2_in[23:18]) }} & ( (rs1_in[31:0] >> {rs2_in[17:16],3'b0}) & 8'hff ); - assign xperm_b[31:24] = { 8{ ~(| rs2_in[31:26]) }} & ( (rs1_in[31:0] >> {rs2_in[25:24],3'b0}) & 8'hff ); - - assign xperm_h[15:00] = {16{ ~(| rs2_in[15:01]) }} & ( (rs1_in[31:0] >> {rs2_in[00] ,4'b0}) & 16'hffff ); // This is a 2:1 mux with qualified selects - assign xperm_h[31:16] = {16{ ~(| rs2_in[31:17]) }} & ( (rs1_in[31:0] >> {rs2_in[16] ,4'b0}) & 16'hffff ); + assign xperm_n[03:00] = { 4{ ~rs2_in[03] }} & 4'( (rs1_in[31:0] >> {rs2_in[02:00],2'b0}) & 4'hf ); // This is a 8:1 mux with qualified selects + assign xperm_n[07:04] = { 4{ ~rs2_in[07] }} & 4'( (rs1_in[31:0] >> {rs2_in[06:04],2'b0}) & 4'hf ); + assign xperm_n[11:08] = { 4{ ~rs2_in[11] }} & 4'( (rs1_in[31:0] >> {rs2_in[10:08],2'b0}) & 4'hf ); + assign xperm_n[15:12] = { 4{ ~rs2_in[15] }} & 4'( (rs1_in[31:0] >> {rs2_in[14:12],2'b0}) & 4'hf ); + assign xperm_n[19:16] = { 4{ ~rs2_in[19] }} & 4'( (rs1_in[31:0] >> {rs2_in[18:16],2'b0}) & 4'hf ); + assign xperm_n[23:20] = { 4{ ~rs2_in[23] }} & 4'( (rs1_in[31:0] >> {rs2_in[22:20],2'b0}) & 4'hf ); + assign xperm_n[27:24] = { 4{ ~rs2_in[27] }} & 4'( (rs1_in[31:0] >> {rs2_in[26:24],2'b0}) & 4'hf ); + assign xperm_n[31:28] = { 4{ ~rs2_in[31] }} & 4'( (rs1_in[31:0] >> {rs2_in[30:28],2'b0}) & 4'hf ); + + assign xperm_b[07:00] = { 8{ ~(| rs2_in[07:02]) }} & 8'( (rs1_in[31:0] >> {rs2_in[01:00],3'b0}) & 8'hff ); // This is a 4:1 mux with qualified selects + assign xperm_b[15:08] = { 8{ ~(| rs2_in[15:10]) }} & 8'( (rs1_in[31:0] >> {rs2_in[09:08],3'b0}) & 8'hff ); + assign xperm_b[23:16] = { 8{ ~(| rs2_in[23:18]) }} & 8'( (rs1_in[31:0] >> {rs2_in[17:16],3'b0}) & 8'hff ); + assign xperm_b[31:24] = { 8{ ~(| rs2_in[31:26]) }} & 8'( (rs1_in[31:0] >> {rs2_in[25:24],3'b0}) & 8'hff ); + + assign xperm_h[15:00] = {16{ ~(| rs2_in[15:01]) }} & 16'( (rs1_in[31:0] >> {rs2_in[00] ,4'b0}) & 16'hffff ); // This is a 2:1 mux with qualified selects + assign xperm_h[31:16] = {16{ ~(| rs2_in[31:17]) }} & 16'( (rs1_in[31:0] >> {rs2_in[16] ,4'b0}) & 16'hffff ); diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv index bea089823..7a06e194a 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_bp_ctl.sv @@ -835,8 +835,8 @@ end // block: fa for ( i=0; i<2; i++) begin : BANKS wire[pt.BHT_ARRAY_DEPTH-1:0] wr0, wr1; - assign wr0 = bht_wr_en0[i] << bht_wr_addr0; - assign wr1 = bht_wr_en2[i] << bht_wr_addr2; + assign wr0 = pt.BHT_ARRAY_DEPTH'(bht_wr_en0[i] << bht_wr_addr0); + assign wr1 = pt.BHT_ARRAY_DEPTH'(bht_wr_en2[i] << bht_wr_addr2); for (genvar k=0 ; k < (pt.BHT_ARRAY_DEPTH)/NUM_BHT_LOOP ; k++) begin : BHT_CLK_GROUP assign bht_bank_clken[i][k] = (bht_wr_en0[i] & ((bht_wr_addr0[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) | (bht_wr_en2[i] & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)); diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv index d259be3c8..580de955f 100644 --- a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv @@ -923,9 +923,6 @@ logic perr_sel_invalidate; logic perr_sb_write_status ; - - rvdffe #(.WIDTH(pt.ICACHE_INDEX_HI-pt.ICACHE_TAG_INDEX_LO+1),.OVERRIDE(1)) perr_dat_ff (.din(ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]), .dout(perr_ic_index_ff[pt.ICACHE_INDEX_HI : pt.ICACHE_TAG_INDEX_LO]), .en(perr_sb_write_status), .*); - assign perr_err_inv_way[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{perr_sel_invalidate}} ; assign iccm_correct_ecc = (perr_state == ECC_CORR); assign dma_sb_err_state = (perr_state == DMA_SB_ERR); @@ -1407,6 +1404,8 @@ if (pt.ICACHE_ENABLE == 1 ) begin: icache_enabled assign way_status_new_w_debug[pt.ICACHE_STATUS_BITS-1:0] = (ic_debug_wr_en & ic_debug_tag_array) ? (pt.ICACHE_STATUS_BITS == 1) ? ic_debug_wr_data[4] : ic_debug_wr_data[6:4] : way_status_new[pt.ICACHE_STATUS_BITS-1:0] ; + rvdffe #(.WIDTH(pt.ICACHE_INDEX_HI-pt.ICACHE_TAG_INDEX_LO+1),.OVERRIDE(1)) perr_dat_ff (.din(ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]), .dout(perr_ic_index_ff[pt.ICACHE_INDEX_HI : pt.ICACHE_TAG_INDEX_LO]), .en(perr_sb_write_status), .*); + rvdffie #(.WIDTH(pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO+1+pt.ICACHE_STATUS_BITS),.OVERRIDE(1)) status_misc_ff (.*, .clk(free_l2clk), @@ -1629,10 +1628,8 @@ assign ic_debug_rd_en = dec_tlu_ic_diag_pkt.icache_rd_valid ; assign ic_debug_wr_en = dec_tlu_ic_diag_pkt.icache_wr_valid ; -assign ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] = {(ic_debug_way_enc[1:0] == 2'b11), - (ic_debug_way_enc[1:0] == 2'b10), - (ic_debug_way_enc[1:0] == 2'b01), - (ic_debug_way_enc[1:0] == 2'b00) }; +assign ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] = {(ic_debug_way_enc[0] == 1'b1), + (ic_debug_way_enc[0] == 1'b0) }; assign ic_debug_tag_wr_en[pt.ICACHE_NUM_WAYS-1:0] = {pt.ICACHE_NUM_WAYS{ic_debug_wr_en & ic_debug_tag_array}} & ic_debug_way[pt.ICACHE_NUM_WAYS-1:0] ; @@ -1673,7 +1670,7 @@ assign ACCESS7_okay = pt.INST_ACCESS_ENABLE7 & ((({ifc_fetch_addr_bf[31:1],1'b0} // memory protection - equation to look identical to the LSU equation - assign ifc_region_acc_okay = (~(|{pt.INST_ACCESS_ENABLE0,pt.INST_ACCESS_ENABLE1,pt.INST_ACCESS_ENABLE2,pt.INST_ACCESS_ENABLE3,pt.INST_ACCESS_ENABLE4,pt.INST_ACCESS_ENABLE5,pt.INST_ACCESS_ENABLE6,pt.INST_ACCESS_ENABLE7})) | + assign ifc_region_acc_okay = (~(|{pt.INST_ACCESS_ENABLE0,pt.INST_ACCESS_ENABLE1,pt.INST_ACCESS_ENABLE2,pt.INST_ACCESS_ENABLE3,pt.INST_ACCESS_ENABLE4,pt.INST_ACCESS_ENABLE5,pt.INST_ACCESS_ENABLE6,pt.INST_ACCESS_ENABLE7})) | ACCESS0_okay | ACCESS1_okay | ACCESS2_okay diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv index 40410c100..5b238fd37 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu.sv @@ -297,7 +297,7 @@ import el2_pkg::*; assign dma_dccm_wen = dma_dccm_req & dma_mem_write & addr_in_dccm_d & dma_mem_sz[1]; // Perform DMA writes only for word/dword assign dma_pic_wen = dma_dccm_req & dma_mem_write & addr_in_pic_d; - assign {dma_dccm_wdata_hi[31:0], dma_dccm_wdata_lo[31:0]} = dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}; // Shift the dma data to lower bits to make it consistent to lsu stores + assign {dma_dccm_wdata_hi[31:0], dma_dccm_wdata_lo[31:0]} = 64'(dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}); // Shift the dma data to lower bits to make it consistent to lsu stores // Generate per cycle flush signals diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv index 8e852788b..ff1e13c03 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv @@ -758,9 +758,9 @@ import el2_pkg::*; // buffer full logic always_comb begin - buf_numvld_any[3:0] = ({1'b0,lsu_busreq_m} << ldst_dual_m) + - ({1'b0,lsu_busreq_r} << ldst_dual_r) + - ibuf_valid; + buf_numvld_any[3:0] = 4'(({1'b0,lsu_busreq_m} << ldst_dual_m) + + ({1'b0,lsu_busreq_r} << ldst_dual_r) + + ibuf_valid); buf_numvld_wrcmd_any[3:0] = 4'b0; buf_numvld_cmd_any[3:0] = 4'b0; buf_numvld_pend_any[3:0] = 4'b0; @@ -885,7 +885,7 @@ import el2_pkg::*; end end assign lsu_imprecise_error_load_any = lsu_nonblock_load_data_error & ~lsu_imprecise_error_store_any; // This is to make sure we send only one imprecise error for load/store - assign lsu_imprecise_error_addr_any[31:0] = lsu_imprecise_error_store_any ? buf_addr[lsu_imprecise_error_store_tag] : buf_addr[lsu_nonblock_load_data_tag]; + assign lsu_imprecise_error_addr_any[31:0] = lsu_imprecise_error_store_any ? buf_addr[lsu_imprecise_error_store_tag[DEPTH_LOG2-1:0]] : buf_addr[lsu_nonblock_load_data_tag[DEPTH_LOG2-1:0]]; // PMU signals assign lsu_pmu_bus_trxn = (lsu_axi_awvalid & lsu_axi_awready) | (lsu_axi_wvalid & lsu_axi_wready) | (lsu_axi_arvalid & lsu_axi_arready); diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv index 96c917258..2efcbfe81 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv @@ -256,7 +256,7 @@ import el2_pkg::*; // This will be high if all the bytes of load hit the stores in pipe/write buffer (m/r/wrbuf) assign ld_full_hit_m = ld_full_hit_lo_m & ld_full_hit_hi_m & lsu_busreq_m & lsu_pkt_m.load & ~is_sideeffects_m; - assign ld_fwddata_m[63:0] = {ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_m[1:0]); + assign ld_fwddata_m[63:0] = 64'({ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_m[1:0])); assign bus_read_data_m[31:0] = ld_fwddata_m[31:0]; // Fifo flops diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv index 31ea65164..be9575c33 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_dccm_ctl.sv @@ -232,8 +232,8 @@ import el2_pkg::*; assign dccm_dma_ecc_error = lsu_double_ecc_error_m; assign dccm_dma_rtag[2:0] = dma_mem_tag_m[2:0]; assign dccm_dma_rdata[63:0] = ldst_dual_m ? lsu_rdata_corr_m[63:0] : {2{lsu_rdata_corr_m[31:0]}}; - assign {lsu_ld_data_m_nc[63:32], lsu_ld_data_m[31:0]} = lsu_rdata_m[63:0] >> 8*lsu_addr_m[1:0]; - assign {lsu_ld_data_corr_m_nc[63:32], lsu_ld_data_corr_m[31:0]} = lsu_rdata_corr_m[63:0] >> 8*lsu_addr_m[1:0]; + assign {lsu_ld_data_m_nc[63:32], lsu_ld_data_m[31:0]} = 64'(lsu_rdata_m[63:0] >> 8*lsu_addr_m[1:0]); + assign {lsu_ld_data_corr_m_nc[63:32], lsu_ld_data_corr_m[31:0]} = 64'(lsu_rdata_corr_m[63:0] >> 8*lsu_addr_m[1:0]); assign dccm_rdata_m[63:0] = {dccm_rdata_hi_m[31:0],dccm_rdata_lo_m[31:0]}; assign dccm_rdata_corr_m[63:0] = {sec_data_hi_m[31:0],sec_data_lo_m[31:0]}; diff --git a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv index d9aeb1fb1..80bf8fb6e 100644 --- a/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv +++ b/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_lsc_ctl.sv @@ -298,7 +298,7 @@ import el2_pkg::*; // Interrupt as a flush source allows the WB to occur assign lsu_commit_r = lsu_pkt_r.valid & (lsu_pkt_r.store | lsu_pkt_r.load) & ~flush_r & ~lsu_pkt_r.dma; - assign dma_mem_wdata_shifted[63:0] = dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}; // Shift the dma data to lower bits to make it consistent to lsu stores + assign dma_mem_wdata_shifted[63:0] = 64'(dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}); // Shift the dma data to lower bits to make it consistent to lsu stores assign store_data_d[31:0] = dma_dccm_req ? dma_mem_wdata_shifted[31:0] : exu_lsu_rs2_d[31:0]; // Write to PIC still happens in r stage assign store_data_m_in[31:0] = (lsu_pkt_d.store_data_bypass_d) ? lsu_result_m[31:0] : store_data_d[31:0]; diff --git a/src/sha256/config/compile.yml b/src/sha256/config/compile.yml index 03ecae0e0..b1657cb80 100755 --- a/src/sha256/config/compile.yml +++ b/src/sha256/config/compile.yml @@ -21,8 +21,6 @@ targets: waiver_files: #- $COMPILE_ROOT/config/rtl_lint/sha256.waiver - $COMPILE_ROOT/config/design_lint/sha256_ctrl/sglint_waivers - black_box: - - sha256_reg --- provides: [sha256_ctrl_tb] schema_version: 2.4.0 diff --git a/src/sha256/rtl/sha256_reg.sv b/src/sha256/rtl/sha256_reg.sv index d6c9e4749..e3cb19219 100644 --- a/src/sha256/rtl/sha256_reg.sv +++ b/src/sha256/rtl/sha256_reg.sv @@ -1425,4 +1425,4 @@ module sha256_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; -endmodule \ No newline at end of file +endmodule diff --git a/src/sha512/config/compile.yml b/src/sha512/config/compile.yml index 690ae1c4a..3b54fea06 100755 --- a/src/sha512/config/compile.yml +++ b/src/sha512/config/compile.yml @@ -24,8 +24,6 @@ targets: waiver_files: #- $COMPILE_ROOT/config/rtl_lint/sha512.waiver - $COMPILE_ROOT/config/design_lint/sha512_ctrl/sglint_waivers - black_box: - - sha512_reg --- provides: [sha512_ctrl_32bit_tb] schema_version: 2.4.0 diff --git a/src/sha512_masked/config/compile.yml b/src/sha512_masked/config/compile.yml index 224e563cd..786a6b588 100755 --- a/src/sha512_masked/config/compile.yml +++ b/src/sha512_masked/config/compile.yml @@ -16,8 +16,6 @@ targets: #waiver_files: #- $COMPILE_ROOT/config/rtl_lint/sha512.waiver #- $COMPILE_ROOT/config/design_lint/sha512_ctrl/sglint_waivers - #black_box: - #- sha512_reg --- provides: [sha512_masked_core_tb] schema_version: 2.4.0 diff --git a/src/soc_ifc/config/compile.yml b/src/soc_ifc/config/compile.yml index 203ddb636..a83fe6840 100644 --- a/src/soc_ifc/config/compile.yml +++ b/src/soc_ifc/config/compile.yml @@ -68,17 +68,8 @@ targets: tops: [soc_ifc_top] rtl_lint: directories: [$COMPILE_ROOT/config/design_lint] - black_box: - - mbox_csr - - mbox_csr_pkg - - soc_ifc_reg - - soc_ifc_reg_pkg waiver_files: - $COMPILE_ROOT/config/design_lint/soc_ifc/sglint_waivers - black_box: - - sha512_acc_csr - - mbox_csr - - soc_ifc_reg tops: [soc_ifc_top] --- provides: [soc_ifc_tb] diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv index 9d6bdf863..2fd211ff3 100644 --- a/src/soc_ifc/rtl/mbox.sv +++ b/src/soc_ifc/rtl/mbox.sv @@ -64,6 +64,7 @@ module mbox localparam MBOX_SIZE_IN_BYTES = SIZE_KB*1024; localparam MBOX_SIZE_IN_DW = (MBOX_SIZE_IN_BYTES)/4; localparam DEPTH = (MBOX_SIZE_IN_DW * 32) / DATA_W; +localparam DEPTH_LOG2 = $clog2(DEPTH); //this module is used to instantiate a single mailbox instance //requests within the address space of this mailbox are routed here from the top level @@ -97,12 +98,12 @@ logic arc_MBOX_EXECUTE_SOC_MBOX_ERROR; //sram logic [DATA_W-1:0] sram_wdata; logic [MBOX_ECC_DATA_W-1:0] sram_wdata_ecc; -logic [$clog2(DEPTH)-1:0] sram_waddr; -logic [$clog2(DEPTH)-1:0] mbox_wrptr, mbox_wrptr_nxt; +logic [DEPTH_LOG2-1:0] sram_waddr; +logic [DEPTH_LOG2-1:0] mbox_wrptr, mbox_wrptr_nxt; logic mbox_wr_full, mbox_wr_full_nxt; logic inc_wrptr; -logic [$clog2(DEPTH)-1:0] sram_rdaddr; -logic [$clog2(DEPTH)-1:0] mbox_rdptr, mbox_rdptr_nxt; +logic [DEPTH_LOG2-1:0] sram_rdaddr; +logic [DEPTH_LOG2-1:0] mbox_rdptr, mbox_rdptr_nxt; logic mbox_rd_full, mbox_rd_full_nxt; logic inc_rdptr; logic rst_mbox_rdptr; @@ -118,15 +119,15 @@ logic mbox_protocol_sram_rd, mbox_protocol_sram_rd_f; logic dir_req_dv_q, dir_req_rd_phase; logic dir_req_wr_ph; logic mask_rdata; -logic [$clog2(DEPTH)-1:0] dir_req_addr; +logic [DEPTH_LOG2-1:0] dir_req_addr; logic soc_has_lock, soc_has_lock_nxt; logic valid_requester; logic valid_receiver; -logic [$clog2(DEPTH):0] mbox_dlen_in_dws; +logic [DEPTH_LOG2:0] mbox_dlen_in_dws; logic latch_dlen_in_dws; -logic [$clog2(DEPTH):0] dlen_in_dws, dlen_in_dws_nxt; +logic [DEPTH_LOG2:0] dlen_in_dws, dlen_in_dws_nxt; logic rdptr_inc_valid; logic mbox_rd_valid, mbox_rd_valid_f; logic wrptr_inc_valid; @@ -219,8 +220,8 @@ always_comb arc_MBOX_EXECUTE_SOC_MBOX_ERROR = (mbox_fsm_ps == MBOX_EXECUTE_SOC) //by the client filling the mailbox is used for masking the data //Store the dlen as a ptr to the last entry always_comb latch_dlen_in_dws = arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_UC | arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_SOC | arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC; -always_comb mbox_dlen_in_dws = (hwif_out.mbox_dlen.length.value >= MBOX_SIZE_IN_BYTES) ? MBOX_SIZE_IN_DW : - (hwif_out.mbox_dlen.length.value >> 2) + (hwif_out.mbox_dlen.length.value[0] | hwif_out.mbox_dlen.length.value[1]); +always_comb mbox_dlen_in_dws = (hwif_out.mbox_dlen.length.value >= MBOX_SIZE_IN_BYTES) ? MBOX_SIZE_IN_DW[DEPTH_LOG2:0] : + DEPTH_LOG2'(hwif_out.mbox_dlen.length.value >> 2) + (hwif_out.mbox_dlen.length.value[0] | hwif_out.mbox_dlen.length.value[1]); //latched dlen is the smaller of the programmed dlen or the current wrptr //this avoids a case where a sender writes less than programmed and the receiver can read beyond that //if the mailbox is full (flag set when writing last entry), always take the programmed dlen @@ -435,7 +436,7 @@ end always_comb dir_req_dv_q = (dir_req_dv & ~dir_req_rd_phase & hwif_out.mbox_lock.lock.value & (~soc_has_lock | (mbox_fsm_ps == MBOX_EXECUTE_UC))) | sha_sram_req_dv; always_comb dir_req_wr_ph = dir_req_dv_q & ~sha_sram_req_dv & req_data.write; -always_comb dir_req_addr = sha_sram_req_dv ? sha_sram_req_addr : req_data.addr[$clog2(DEPTH)+1:2]; +always_comb dir_req_addr = sha_sram_req_dv ? sha_sram_req_addr : req_data.addr[DEPTH_LOG2+1:2]; //Direct read from uC, stall 1 clock dv_q will be de-asserted second clock always_comb req_hold = (dir_req_dv_q & ~sha_sram_req_dv & ~req_data.write) | @@ -478,8 +479,10 @@ rvecc_encode mbox_ecc_encode ( .ecc_out(sram_wdata_ecc) ); // synthesis translate_off +`ifdef CLP_ASSERT_ON initial assert(DATA_W == 32) else $error("%m::rvecc_encode supports 32-bit data width; must change SRAM ECC implementation to support DATA_W = %d", DATA_W); +`endif // synthesis translate_on rvecc_decode ecc_decode ( .en (sram_rd_ecc_en ), diff --git a/src/soc_ifc/rtl/sha512_acc_top.sv b/src/soc_ifc/rtl/sha512_acc_top.sv index 79b52410a..fbad8aa87 100644 --- a/src/soc_ifc/rtl/sha512_acc_top.sv +++ b/src/soc_ifc/rtl/sha512_acc_top.sv @@ -305,8 +305,8 @@ always_comb core_digest_valid_q = core_digest_valid & ~(init_reg | next_reg); always_comb mbox_start_addr = hwif_out.START_ADDRESS.ADDR.value[MBOX_ADDR_W+1:2]; always_comb mbox_ptr_round_up = (|hwif_out.DLEN.LENGTH.value[1:0]); //detect overflow of end address to indicate we want to read to the end of the mailbox - always_comb {mbox_read_to_end, mbox_end_addr} = mbox_ptr_round_up ? mbox_start_addr + (hwif_out.DLEN.LENGTH.value>>2) + 'd1 : - mbox_start_addr + (hwif_out.DLEN.LENGTH.value>>2); + always_comb {mbox_read_to_end, mbox_end_addr} = mbox_ptr_round_up ? mbox_start_addr + MBOX_ADDR_W'(hwif_out.DLEN.LENGTH.value>>2) + 1'b1 : + mbox_start_addr + MBOX_ADDR_W'(hwif_out.DLEN.LENGTH.value>>2); always_comb mbox_read_done = (sha_fsm_ps == SHA_IDLE) | ~mailbox_mode | //If the DLEN overflowed our end address, just read to the end of the mailbox and stop //Otherwise read until read pointer == end address diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv index 2ef6e0f4e..18c1b7f99 100644 --- a/src/soc_ifc/rtl/soc_ifc_top.sv +++ b/src/soc_ifc/rtl/soc_ifc_top.sv @@ -843,10 +843,10 @@ i_mbox ( //------------------------- //Watchdog timer //------------------------- -assign timer1_en = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_EN.timer1_en; -assign timer2_en = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_EN.timer2_en; -assign timer1_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_CTRL.timer1_restart; -assign timer2_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_CTRL.timer2_restart; +assign timer1_en = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_EN.timer1_en.value; +assign timer2_en = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_EN.timer2_en.value; +assign timer1_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value; +assign timer2_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value; for (genvar i = 0; i < WDT_TIMEOUT_PERIOD_NUM_DWORDS; i++) begin assign timer1_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i].timer1_timeout_period.value;