diff --git a/.github/scripts/parse_testlist.py b/.github/scripts/parse_testlist.py
new file mode 100644
index 00000000..9b36c559
--- /dev/null
+++ b/.github/scripts/parse_testlist.py
@@ -0,0 +1,26 @@
+import sys
+from json import dumps
+from yaml import load, Loader
+from typing import Generator
+
+
+def parse_yaml(path: str) -> Generator[str, None, None]:
+    with open(path, 'rb') as fd:
+        tests = load(fd, Loader=Loader)
+    for test in tests:
+        if 'import' in test:
+            import_path = test['import'].split('/', 1)[1]
+            yield from parse_yaml(import_path)
+        elif 'test' in test:
+            yield test['test']
+
+
+if __name__ == "__main__":
+    if len(sys.argv) == 2:
+        testlist = parse_yaml(f'target/{sys.argv[1]}/testlist.yaml')
+    else:
+        testlist = parse_yaml('yaml/base_testlist.yaml')
+    testlist = list(testlist)
+    # remove, will cause incomplete sim, need customized RTL
+    testlist.remove("riscv_csr_test")
+    print(dumps(testlist))
diff --git a/.github/workflows/run-tests.yml b/.github/workflows/run-tests.yml
index 3d8e3013..dd93d0cf 100644
--- a/.github/workflows/run-tests.yml
+++ b/.github/workflows/run-tests.yml
@@ -4,22 +4,119 @@ on:
   push:
   pull_request:
 
+env:
+  RISCV_TARGET: rv32imc
+
 jobs:
   build-spike:
     uses: ./.github/workflows/build-spike.yml
-  test-pyflow:
+
+  generate-config:
+    runs-on: ubuntu-latest
+    outputs:
+      test-types: ${{ steps.test-types.outputs.tests }}
+      hash: ${{ steps.hash.outputs.files-hash }}
+    steps:
+      - uses: actions/checkout@v4
+      - id: test-types
+        name: Prepare test types
+        run: |
+          python3 -m pip install pyyaml
+          echo "tests=$(python3 .github/scripts/parse_testlist.py $RISCV_TARGET)" | tee -a $GITHUB_OUTPUT
+      - id: hash
+        name: Prepare files' hash
+        run: |
+          echo "files-hash=$(sha256sum **/*.sv **/*.py **/*.yml **/*.yaml | cut -d\  -f1 | sha256sum | cut -d\  -f1)" | tee -a $GITHUB_OUTPUT
+          
+
+  generate-code:
+    runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
+    container: centos:8
+    needs: generate-config
     strategy:
       fail-fast: false
       matrix:
-        test:
-          - riscv_arithmetic_basic_test
+        test: ${{ fromJSON(needs.generate-config.outputs.test-types) }}
+        version: [ uvm ]
+        include:
+          - test: riscv_arithmetic_basic_test 
+            version: pyflow
+    env:
+      GHA_EXTERNAL_DISK: additional-tools
+      CACHE_HASH: ${{ needs.generate-config.outputs.hash }}
+    steps:
+      - uses: actions/checkout@v3
+
+      - name: Setup Cache Metadata
+        id: cache_metadata
+        run: |
+          cache_code=cache_${{ matrix.test }}_${{ matrix.version }}
+          echo "cache_code=${cache_code}_${{ env.CACHE_HASH }}" | tee -a "$GITHUB_ENV"
+
+      - name: Cache Code
+        uses: actions/cache@v3
+        id: cache-code
+        timeout-minutes: 60
+        with:
+          path: test/asm_test
+          key: ${{ env.cache_code }}
+
+      - name: Prepare Environment
+        if: steps.cache-code.outputs.cache-hit != 'true'
+        run: _secret_environment
+
+      - name: Setup Python 3.9
+        if: steps.cache-code.outputs.cache-hit != 'true'
+        run: |
+          yum update -y
+          yum install -y python39
+          python3.9 -m pip install -r requirements.txt
+
+      - name: Generate UVM Tests
+        if: steps.cache-code.outputs.cache-hit != 'true' && matrix.version == 'uvm'
+        run: _secret_riscv
+        env:
+          RISCV_TEST: ${{ matrix.test }}
+          RISCV_TARGET: ${{ env.RISCV_TARGET }}
+
+      - name: Generate PyFlow Tests
+        if: steps.cache-code.outputs.cache-hit != 'true' && matrix.version == 'pyflow'
+        run: |
+          set -eo pipefail
+          python3 run.py --simulator pyflow \
+            --test ${{ matrix.test }} --iss spike \
+            --start_seed 999 --iterations 1 --batch_size 1 \
+            --isa $RISCV_TARGET --mabi ilp32 --steps gen -v -o test 2>&1 | tee test/generate.log
+
+      - name: Upload Artifacts
+        uses: actions/upload-artifact@v3
+        if: always()
+        with:
+          path: |
+            test/asm_test/*.S
+
+
+  run-tests:
     runs-on: ubuntu-latest
-    needs: [build-spike]
+    needs: [ build-spike, generate-code, generate-config ]
+    strategy:
+      fail-fast: false
+      matrix:
+        test: ${{ fromJSON(needs.generate-config.outputs.test-types) }}
+        version:
+          - uvm
+        include:
+          - test: riscv_arithmetic_basic_test
+            version: pyflow
+    env:
+      TOOL_VERSION: d70ea67d
+      CACHE_HASH: ${{ needs.generate-config.outputs.hash }}
+
     steps:
       - uses: actions/checkout@v4
 
       - name: Install dependencies
-        run: sudo apt-get -qqy update && sudo apt-get -qqy install gcc-riscv64-linux-gnu device-tree-compiler
+        run: sudo apt-get -qqy update && sudo apt-get -qqy install gcc-riscv64-unknown-elf device-tree-compiler
 
       - name: Setup python
         # python dependencies cannot be properly downloaded with new versions of python
@@ -36,10 +133,12 @@ jobs:
           date=$(date +"%Y_%m_%d")
           time=$(date +"%Y%m%d_%H%M%S_%N")
           cache_spike_restore_key=cache_spike_
-          cache_spike_key=${cache_spike_restore_key}d70ea67d_${date}
+          cache_spike_key=${cache_spike_restore_key}${{ env.TOOL_VERSION }}_${date}
+          cache_code=cache_${{ matrix.test }}_${{ matrix.version }}
 
           echo "cache_spike_restore_key=$cache_spike_restore_key" | tee -a "$GITHUB_ENV"
           echo "cache_spike_key=$cache_spike_key" | tee -a "$GITHUB_ENV"
+          echo "cache_code=${cache_code}_${{ env.CACHE_HASH }}" | tee -a "$GITHUB_ENV"
 
       - name: Restore Spike cache
         id: cache-spike-restore
@@ -53,31 +152,28 @@ jobs:
 
       - name: Set variables
         run: |
-          echo "RISCV_GCC=riscv64-linux-gnu-gcc" >> $GITHUB_ENV
-          echo "RISCV_OBJCOPY=riscv64-linux-gnu-objcopy" >> $GITHUB_ENV
+          echo "RISCV_GCC=riscv64-unknown-elf-gcc" >> $GITHUB_ENV
+          echo "RISCV_OBJCOPY=riscv64-unknown-elf-objcopy" >> $GITHUB_ENV
           echo "SPIKE_PATH=/opt/spike/bin" >> $GITHUB_ENV
           echo "PYTHONPATH=pygen" >> $GITHUB_ENV
 
-      - name: Generate Tests
-        run: |
-          set -eo pipefail
-          python3 run.py --simulator pyflow \
-            --test ${{ matrix.test }} --iss spike \
-            --start_seed 999 --iterations 1 --batch_size 1 \
-            --isa rv32imc --mabi ilp32 --steps gen -v -o test 2>&1 | tee test/generate.log
-
-      - name: Patch Tests
-        run: find test/asm_test -name "*.S" -exec python3 .github/scripts/code_fixup.py -i {} -o {} \;
+      - name: Cache Code Restore
+        uses: actions/cache/restore@v3
+        id: cache-code-restore
+        timeout-minutes: 60
+        with:
+          path: test/asm_test
+          key: ${{ env.cache_code }}
 
-      - name: Run tests
+      - name: Run Tests
         run: |
           set -eo pipefail
           python3 run.py --simulator pyflow \
             --test ${{ matrix.test }} --iss spike --iss_timeout 60 \
             --start_seed 999 --iterations 1 --batch_size 1 \
-            --isa rv32imc --mabi ilp32 --steps gcc_compile,iss_sim -v -o test 2>&1 | tee -a test/generate.log
+            --isa $RISCV_TARGET --mabi ilp32 --steps gcc_compile,iss_sim -v -o test 2>&1 | tee -a test/generate.log
 
-      - name: Upload logs
+      - name: Upload Artifacts
         uses: actions/upload-artifact@v3
         if: always()
         with:
diff --git a/euvm/README.md b/euvm/README.md
index a31a6860..c47460dd 100644
--- a/euvm/README.md
+++ b/euvm/README.md
@@ -10,6 +10,8 @@ The RISCV-DV eUVM port is a line-by-line translation of the RISCV-DV SystemVeril
 
 If you want to build/use the eUVM port, you need an eUVM installation. Please follow the instructions on https://github.com/coverify/euvm/releases to install and setup eUVM.
 
+Please use euvm 1.0-beta36 or later release for compiling and running RISCV-DV.
+
 ## Building eUVM port of RISCV-DV
 
 A makefile to build and run the eUVM port is available in the euvm/build folder. To build the code, use the following commands (assuming bash shell):
@@ -41,3 +43,15 @@ You can change the number of instructions to be generated by passsing INSTRCOUNT
 ```bash
 make run INSTRCOUNT=1000000
 ```
+
+To run arithmatic_only_test for 10 million instructions:
+
+```
+make run_riscv_arithmetic_only_test INSTRCOUNT=10000000
+```
+
+To run arithmatic_only_test for 10 million instructions using 32 threads:
+
+```
+make run_riscv_arithmetic_only_test INSTRCOUNT=10000000 THREADS=32
+```
diff --git a/euvm/build/makefile b/euvm/build/makefile
index e82e9aa4..47296b9b 100644
--- a/euvm/build/makefile
+++ b/euvm/build/makefile
@@ -1,15 +1,19 @@
 # Runtime Paramters
+GCOPTS = # --DRT-gcopt=parallel:0
 INSTRCOUNT = 100000
 VERBOSITY = NONE
+VERSION = NOVERSION
 RANDSEED = 1
+THREADS = 1
+CPU = 4
 
 # Compile Paramters
 MTRIPLE = -m64
 TARGET = RV64IMC
 CC = gcc
 DEBUG = NONE
-DFLAGS = $(MTRIPLE) -d-version=$(TARGET) -w -d-debug=$(DEBUG) -O3  -release -boundscheck=off # --lowmem # -d-version=CHECK_COMPILE
-DBGDFLAGS = $(MTRIPLE) -d-version=$(TARGET) -w -d-debug=$(DEBUG) -g
+DFLAGS = $(MTRIPLE) -d-version=$(TARGET) -d-version=$(VERSION) -w -d-debug=$(DEBUG) -O3 -mcpu=native -release -boundscheck=off # -defaultlib=phobos2-ldc-lto,druntime-ldc-lto # --lowmem # -d-version=CHECK_COMPILE
+DBGDFLAGS = $(MTRIPLE) -d-version=$(TARGET) -w -mcpu=native -d-debug=$(DEBUG) -g
 LDC2 = ldc2
 PICOBJDIR = picobj-ldc
 DBGPICOBJDIR = picobj-dbg-ldc
@@ -20,6 +24,8 @@ PICDBGOBJDIR = picobj-dbg-ldc
 DBGOBJDIR = obj-dbg-ldc
 
 PHOBOS = phobos2-ldc-shared
+PHOBOSDBG = phobos2-ldc-debug-shared
+
 
 DATE = $(shell date '+%Y-%m-%d')
 
@@ -27,7 +33,9 @@ GEN_FILES = riscv/gen/package.d riscv/gen/riscv_amo_instr_lib.d		\
 	    riscv/gen/riscv_data_page_gen.d				\
 	    riscv/gen/riscv_directed_instr_lib.d			\
 	    riscv/gen/riscv_instr_gen_config.d				\
+	    riscv/gen/riscv_opcodes_pkg.d				\
 	    riscv/gen/riscv_instr_pkg.d					\
+	    riscv/gen/riscv_opcodes_pkg.d				\
 	    riscv/gen/riscv_instr_registry.d				\
 	    riscv/gen/riscv_instr_sequence.d				\
 	    riscv/gen/riscv_instr_stream.d				\
@@ -53,11 +61,13 @@ GEN_FILES = riscv/gen/package.d riscv/gen/riscv_amo_instr_lib.d		\
 	    riscv/gen/target/rv64gc/riscv_core_setting.d		\
 	    riscv/gen/target/rv64imcb/riscv_core_setting.d		\
 	    riscv/gen/target/rv32imafdc/riscv_core_setting.d		\
+	    riscv/gen/target/rv64imafdc/riscv_core_setting.d		\
 	    riscv/gen/target/ml/riscv_core_setting.d			\
 	    riscv/gen/target/multi_harts/riscv_core_setting.d		\
 	    riscv/gen/target/rv32imc_sv32/riscv_core_setting.d		\
 	    riscv/gen/target/rv32i/riscv_core_setting.d			\
 	    riscv/gen/target/rv64imc/riscv_core_setting.d		\
+	    riscv/gen/target/rv64imp/riscv_core_setting.d		\
 	    riscv/gen/target/rv32imc/riscv_core_setting.d
 
 
@@ -65,6 +75,7 @@ ISA_FILES = riscv/gen/isa/package.d riscv/gen/isa/riscv_amo_instr.d	\
             riscv/gen/isa/riscv_compressed_instr.d			\
             riscv/gen/isa/riscv_floating_point_instr.d			\
             riscv/gen/isa/riscv_instr.d riscv/gen/isa/riscv_b_instr.d	\
+            riscv/gen/isa/riscv_csr_instr.d			        \
             riscv/gen/isa/riscv_vector_instr.d				\
             riscv/gen/isa/riscv_instr_register.d			\
             riscv/gen/isa/riscv_zba_instr.d				\
@@ -87,7 +98,10 @@ ISA_FILES = riscv/gen/isa/package.d riscv/gen/isa/riscv_amo_instr.d	\
             riscv/gen/isa/rv32zbs_instr.d				\
             riscv/gen/isa/rv64zba_instr.d				\
             riscv/gen/isa/rv64zbb_instr.d				\
-            riscv/gen/isa/custom/riscv_custom_instr.d			\
+	    riscv/gen/isa/rvzpn_instr.d					\
+	    riscv/gen/isa/rv32zpn_instr.d				\
+	    riscv/gen/isa/rv64zpn_instr.d				\
+	    riscv/gen/isa/custom/riscv_custom_instr.d			\
             riscv/gen/isa/custom/riscv_custom_instr_enum.d
 
 TEST_FILES = riscv/test/riscv_instr_base_test.d                         \
@@ -118,17 +132,17 @@ $(DBGPICOBJDIR)/%.o: ../%.d
 libriscv-dv-ldc-shared.so: $(addprefix $(PICOBJDIR)/,$(GEN_OBJS)) \
 			   $(addprefix $(PICOBJDIR)/,$(ISA_OBJS)) \
 			   $(addprefix $(PICOBJDIR)/,$(TEST_OBJS))
-	CC=$(CC) $(LDC2) -shared $(DFLAGS) -relocation-model=pic -of$@ -I.. $^ -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lphobos2-ldc-shared -L-ldruntime-ldc-shared -L-lz3
+	CC=$(CC) $(LDC2) -shared $(DFLAGS) -relocation-model=pic -of$@ -I.. $^ -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lphobos2-ldc-shared -L-ldruntime-ldc-shared -L-lz3 # -L-lboolector
 
 libriscv-dv-ldc-debug-shared.so: $(addprefix $(DBGPICOBJDIR)/,$(GEN_OBJS)) \
 			         $(addprefix $(DBGPICOBJDIR)/,$(ISA_OBJS)) \
 			         $(addprefix $(DBGPICOBJDIR)/,$(TEST_OBJS))
-	CC=$(CC) $(LDC2) -shared $(DBGDFLAGS) -relocation-model=pic -of$@ -I.. $^ -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lphobos2-ldc-shared -L-ldruntime-ldc-shared -L-lz3
+	CC=$(CC) $(LDC2) -shared $(DBGDFLAGS) -relocation-model=pic -of$@ -I.. $^ -L-luvm-ldc-debug-shared -L-lesdl-ldc-debug-shared -L-lphobos2-ldc-debug-shared -L-ldruntime-ldc-debug-shared -L-lz3 # -L-lboolector
 
 libriscv-dv-ldc-shared-alt.so: $(addprefix ../,$(GEN_FILES)) \
 			       $(addprefix ../,$(ISA_FILES)) \
 			       $(addprefix $(PICOBJDIR)/,$(TEST_OBJS))
-	CC=$(CC) $(LDC2) -shared $(DFLAGS) -relocation-model=pic -of$@ -I.. $^ -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lphobos2-ldc-shared -L-ldruntime-ldc-shared -L-lz3
+	CC=$(CC) $(LDC2) -shared $(DFLAGS) -relocation-model=pic -of$@ -I.. $^ -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lphobos2-ldc-shared -L-ldruntime-ldc-shared -L-lz3  # -L-lboolector
 
 libriscv-dv-ldc.a: $(addprefix $(PICOBJDIR)/,$(GEN_OBJS)) \
 	           $(addprefix $(PICOBJDIR)/,$(ISA_OBJS)) \
@@ -141,13 +155,13 @@ TAGS: $(addprefix ../,$(GEN_FILES)) \
 	dscanner --etags $^ > $@
 
 riscv_instr_gen: ../riscv/test/riscv_instr_gen.d libriscv-dv-ldc-shared.so
-	$(LDC2) -link-defaultlib-shared $(DFLAGS) -of$@ -I.. -L--no-as-needed -L-R./ -L-L./ $< -L-lriscv-dv-ldc-shared -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lphobos2-ldc-shared -L-lz3 -L-ldl 
+	$(LDC2) -link-defaultlib-shared $(DFLAGS) -of$@ -I.. -L--no-as-needed -L-R./ -L-L./ $< -L-lriscv-dv-ldc-shared -L-luvm-ldc-shared -L-lesdl-ldc-shared -L-lz3 -L-ldl  # -L-lboolector # -defaultlib=phobos2-ldc-lto,druntime-ldc-lto
 
 riscv_instr_gen_debug: ../riscv/test/riscv_instr_gen.d libriscv-dv-ldc-debug-shared.so
-	$(LDC2) -link-defaultlib-shared $(DBGDFLAGS) -of$@ -I.. -L--no-as-needed -L-R./ -L-L./ $< -L-lriscv-dv-ldc-debug-shared -L-luvm-ldc-debug-shared -L-lesdl-ldc-debug-shared -L-lphobos2-ldc-shared -L-lz3 -L-ldl
+	$(LDC2) -link-defaultlib-shared $(DBGDFLAGS) -of$@ -I.. -L--no-as-needed -L-R./ -L-L./ $< -L-lriscv-dv-ldc-debug-shared -L-luvm-ldc-debug-shared -L-lesdl-ldc-debug-shared -L-lphobos2-ldc-debug-shared -L-ldruntime-ldc-debug-shared -L-lz3 -L-ldl  # -L-lboolector
 
 run: riscv_instr_gen
-	./riscv_instr_gen +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_$(DATE)/asm_test/riscv_rand_instr_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=5 \
+	./riscv_instr_gen $(GCOPTS) +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +par_num_threads=$(THREADS) +thread_index=$(CPU) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_$(DATE)/asm_test/riscv_rand_instr_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=5 \
 	+directed_instr_0=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_rand_instr_stream,4 \
 	+directed_instr_1=riscv.gen.riscv_load_store_instr_lib.riscv_hazard_instr_stream,4 \
 	+directed_instr_2=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_hazard_instr_stream,4 \
@@ -157,7 +171,7 @@ run: riscv_instr_gen
 	+directed_instr_6=riscv.gen.riscv_loop_instr.riscv_loop_instr,4
 
 run_debug: riscv_instr_gen_debug
-	./riscv_instr_gen_debug +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_2021-08-10/asm_test/riscv_rand_instr_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=5 \
+	./riscv_instr_gen_debug $(GCOPTS) +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +par_num_threads=$(THREADS) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_2021-08-10/asm_test/riscv_rand_instr_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=5 \
 	+directed_instr_0=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_rand_instr_stream,4 \
 	+directed_instr_1=riscv.gen.riscv_load_store_instr_lib.riscv_hazard_instr_stream,4 \
 	+directed_instr_2=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_hazard_instr_stream,4 \
@@ -167,7 +181,22 @@ run_debug: riscv_instr_gen_debug
 	+directed_instr_6=riscv.gen.riscv_loop_instr.riscv_loop_instr,4
 
 run_riscv_arithmetic_basic_test: riscv_instr_gen
-	./riscv_instr_gen +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_2021-08-10/asm_test/riscv_arithmetic_basic_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=0 +directed_instr_0=riscv.gen.riscv_directed_instr_lib.riscv_int_numeric_corner_stream,4 +no_fence=true +no_data_page=true +no_branch_jump=true +boot_mode=m +no_csr_instr=true 
+	./riscv_instr_gen $(GCOPTS) +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +par_num_threads=$(THREADS) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_2021-08-10/asm_test/riscv_arithmetic_basic_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=0 +directed_instr_0=riscv.gen.riscv_directed_instr_lib.riscv_int_numeric_corner_stream,4 +no_fence=true +no_data_page=true +no_branch_jump=true +boot_mode=m +no_csr_instr=true 
 
 run_riscv_arithmetic_only_test: riscv_instr_gen
-	./riscv_instr_gen +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_2021-08-10/asm_test/riscv_arithmetic_basic_test +instr_cnt=$(INSTRCOUNT) +no_fence=true +no_data_page=true +num_of_sub_program=0 +no_branch_jump=true +boot_mode=m +no_csr_instr=true 
+	./riscv_instr_gen $(GCOPTS) +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +par_num_threads=$(THREADS) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_2021-08-10/asm_test/riscv_arithmetic_basic_test +instr_cnt=$(INSTRCOUNT) +no_fence=true +no_data_page=true +num_of_sub_program=0 +no_branch_jump=true +boot_mode=m +no_csr_instr=true 
+
+run_pmp_test: riscv_instr_gen
+	./riscv_instr_gen $(GCOPTS) +UVM_VERBOSITY=$(VERBOSITY) +random_seed=$(RANDSEED) +par_num_threads=$(THREADS) +UVM_TESTNAME=riscv.test.riscv_instr_base_test.riscv_instr_base_test +num_of_tests=1 +start_idx=0 +asm_file_name=out_$(DATE)/asm_test/riscv_rand_instr_test +instr_cnt=$(INSTRCOUNT) +num_of_sub_program=5 \
+	+directed_instr_0=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_rand_instr_stream,4 \
+	+directed_instr_1=riscv.gen.riscv_load_store_instr_lib.riscv_hazard_instr_stream,4 \
+	+directed_instr_2=riscv.gen.riscv_load_store_instr_lib.riscv_load_store_hazard_instr_stream,4 \
+	+directed_instr_3=riscv.gen.riscv_load_store_instr_lib.riscv_multi_page_load_store_instr_stream,4 \
+	+directed_instr_4=riscv.gen.riscv_load_store_instr_lib.riscv_mem_region_stress_test,4 \
+	+directed_instr_5=riscv.gen.riscv_directed_instr_lib.riscv_jal_instr,4 \
+	+directed_instr_6=riscv.gen.riscv_loop_instr.riscv_loop_instr,4 \
+	+pmp_randomize=false \
+	+pmp_num_regions=1 \
+        +pmp_granularity=1 \
+        +pmp_region_0=L:false,A:TOR,X:true,W:true,R:true,ADDR:FFFFFFFF
+
diff --git a/euvm/riscv/gen/isa/custom/riscv_custom_instr.d b/euvm/riscv/gen/isa/custom/riscv_custom_instr.d
index 2178d255..cb189c1a 100644
--- a/euvm/riscv/gen/isa/custom/riscv_custom_instr.d
+++ b/euvm/riscv/gen/isa/custom/riscv_custom_instr.d
@@ -22,7 +22,7 @@ module riscv.gen.isa.custom.riscv_custom_instr;
 import riscv.gen.riscv_instr_pkg: riscv_instr_group_t,
   riscv_instr_name_t, MAX_INSTR_STR_LEN, riscv_fpr_t,
   riscv_instr_format_t, riscv_instr_category_t,
-  format_string, f_rounding_mode_t;
+  f_rounding_mode_t;
 import riscv.gen.isa.riscv_instr: riscv_instr;
 import std.string: toUpper, toLower;
 import std.format: format;
@@ -48,10 +48,17 @@ class riscv_custom_instr: riscv_instr
     // TODO: Add custom instruction name encoding here
   }
 
+  override char[] get_instr_name(char[] buf) {
+    import std.format: sformat;
+    char[] str_instr_name = sformat!("%s")(buf, instr_name);
+    return str_instr_name;
+  }
+
   // Convert the instruction to assembly code
   override string convert2asm(string prefix = "") {
     string asm_str;
-    asm_str = format_string("nop", MAX_INSTR_STR_LEN);
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    asm_str = format!FMT("nop");
     /* TODO: Convert custom instruction to assembly format. Example:
     asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN);
     case (instr_name)
@@ -65,4 +72,32 @@ class riscv_custom_instr: riscv_instr
     }
     return asm_str.toLower();
   }
+
+  override char[] convert2asm(char[] buf, string prefix = "") {
+    import std.string: toLower, toLowerInPlace;
+    import std.format: sformat;
+
+    char[32] instr_buf;
+    char[MAX_INSTR_STR_LEN+8] instr_name_buf;
+
+    char[] asm_buf;
+
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    char[] instr_name_str = sformat!FMT(instr_name_buf, "nop");
+
+    /* TODO: Convert custom instruction to assembly format. Example:
+       asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN);
+       case (instr_name)
+       CUSTOM_1: asm_str = $sformatf("%0s %0s, (%0s)", asm_str, rd.name(), rs1.name());
+       CUSTOM_2: asm_str = $sformatf("%0s %0s", asm_str, r3.name());
+       endcase
+    */
+
+    asm_buf = sformat!("%s #%s %s")(buf, instr_name_str, get_instr_name(instr_buf), comment);
+
+    toLowerInPlace(asm_buf);
+
+    assert(asm_buf.ptr is buf.ptr);
+    return asm_buf;
+  }
 }
diff --git a/euvm/riscv/gen/isa/package.d b/euvm/riscv/gen/isa/package.d
index 0aaa8dc0..bf3ddb86 100644
--- a/euvm/riscv/gen/isa/package.d
+++ b/euvm/riscv/gen/isa/package.d
@@ -36,6 +36,9 @@ public import riscv.gen.isa.rv32zba_instr;
 public import riscv.gen.isa.rv32zbb_instr;
 public import riscv.gen.isa.rv32zbc_instr;
 public import riscv.gen.isa.rv32zbs_instr;
+public import riscv.gen.isa.rvzpn_instr;
+public import riscv.gen.isa.rv32zpn_instr;
+public import riscv.gen.isa.rv64zpn_instr;
 
 public import riscv.gen.isa.custom.riscv_custom_instr;
 public import riscv.gen.isa.custom.riscv_custom_instr_enum;
diff --git a/euvm/riscv/gen/isa/riscv_amo_instr.d b/euvm/riscv/gen/isa/riscv_amo_instr.d
index aebd6ab2..f9597219 100644
--- a/euvm/riscv/gen/isa/riscv_amo_instr.d
+++ b/euvm/riscv/gen/isa/riscv_amo_instr.d
@@ -17,7 +17,7 @@
 
 module riscv.gen.isa.riscv_amo_instr;
 
-import riscv.gen.riscv_instr_pkg: riscv_instr_group_t, format_string,
+import riscv.gen.riscv_instr_pkg: riscv_instr_group_t,
   riscv_instr_name_t, MAX_INSTR_STR_LEN;
 import riscv.gen.isa.riscv_instr: riscv_instr;
 import std.format: format;
@@ -62,10 +62,45 @@ class riscv_amo_instr: riscv_instr
     return instr_name_str;
   }
 
+  override char[] get_instr_name(char[] buf) {
+    import std.format: sformat;
+    
+    char[] instr_name_str = sformat!("%s")(buf, instr_name);
+    
+    if (group == riscv_instr_group_t.RV32A) {
+      instr_name_str[$-2..$]  = ".w";
+      if (aq) {
+	instr_name_str = buf[0..instr_name_str.length+3];
+	instr_name_str[$-3..$]  = ".aq";
+      }
+      else if(rl) {
+	instr_name_str = buf[0..instr_name_str.length+3];
+	instr_name_str[$-3..$]  = ".rl";
+      }
+    }
+    else if (group == riscv_instr_group_t.RV64A) {
+      instr_name_str[$-2..$]  = ".d";
+      if (aq) {
+	instr_name_str = buf[0..instr_name_str.length+3];
+	instr_name_str[$-3..$]  = ".aq";
+      }
+      else if(rl) {
+	instr_name_str = buf[0..instr_name_str.length+3];
+	instr_name_str[$-3..$]  = ".rl";
+      }
+    }
+    else {
+      uvm_fatal(get_full_name(), format("Unexpected amo instr group: %0s / %0s",
+					group, instr_name));
+    }
+    return instr_name_str;
+  }
+
   // Convert the instruction to assembly code
   override string convert2asm(string prefix = "") {
     import std.string: toLower;
-    string asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN);
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    string asm_str = format!FMT(get_instr_name());
     if (group.inside(riscv_instr_group_t.RV32A, riscv_instr_group_t.RV64A))  {
       if (instr_name.inside(riscv_instr_name_t.LR_W, riscv_instr_name_t.LR_D)) {
         asm_str = format("%0s %0s, (%0s)", asm_str, rd, rs1);
@@ -78,11 +113,48 @@ class riscv_amo_instr: riscv_instr
       uvm_fatal(get_full_name(), format("Unexpected amo instr group: %0s / %0s",
 					group, instr_name));
     }
-    if(comment != "")
+    if (comment != "")
       asm_str ~= " #" ~ comment;
     return asm_str.toLower();
   }
 
+  override char[] convert2asm(char[] buf, string prefix = "") {
+    import std.string: toLower, toLowerInPlace;
+    import std.format: sformat;
+
+    char[32] instr_buf;
+    char[MAX_INSTR_STR_LEN+8] instr_name_buf;
+
+    char[] asm_buf;
+
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    char[] instr_name_str = sformat!FMT(instr_name_buf, get_instr_name(instr_buf));
+
+    if (group.inside(riscv_instr_group_t.RV32A, riscv_instr_group_t.RV64A))  {
+      if (instr_name.inside(riscv_instr_name_t.LR_W, riscv_instr_name_t.LR_D)) {
+        asm_buf = sformat!("%0s %0s, (%0s)")(buf, instr_name_str, rd, rs1);
+      }
+      else {
+        asm_buf = sformat!("%0s %0s, %0s, (%0s)")(buf, instr_name_str, rd, rs2, rs1);
+      }
+    }
+    else {
+      uvm_fatal(get_full_name(), format("Unexpected amo instr group: %0s / %0s",
+					group, instr_name));
+    }
+
+    if (comment != "") {
+      buf[asm_buf.length..asm_buf.length+2] = " #";
+      buf[asm_buf.length+2..asm_buf.length+2+comment.length] = comment;
+      asm_buf = buf[0..asm_buf.length+2+comment.length];
+    }
+
+    toLowerInPlace(asm_buf);
+
+    assert(asm_buf.ptr is buf.ptr);
+    return asm_buf;
+  }
+
   override void do_copy(uvm_object rhs) {
     super.copy(rhs);
     riscv_amo_instr rhs_ = cast(riscv_amo_instr) rhs;
diff --git a/euvm/riscv/gen/isa/riscv_b_instr.d b/euvm/riscv/gen/isa/riscv_b_instr.d
index 9154cb8f..78505372 100644
--- a/euvm/riscv/gen/isa/riscv_b_instr.d
+++ b/euvm/riscv/gen/isa/riscv_b_instr.d
@@ -20,14 +20,14 @@ module riscv.gen.isa.riscv_b_instr;
 
 import riscv.gen.riscv_instr_pkg: riscv_reg_t, riscv_instr_name_t, b_ext_group_t,
   riscv_instr_category_t, riscv_instr_format_t, riscv_instr_group_t,
-  MAX_INSTR_STR_LEN, format_string;
+  MAX_INSTR_STR_LEN;
 import riscv.gen.target: XLEN;
 import riscv.gen.riscv_instr_gen_config: riscv_instr_gen_config;
 import riscv.gen.isa.riscv_instr: riscv_instr;
 import std.format: format;
 
 import esdl.rand: rand;
-import esdl.data.bvec: ubvec, toubvec, clog2;
+import esdl.data.bvec: ubvec, UBVEC, clog2;
 import std.algorithm: canFind;
 
 import std.string: toLower;
@@ -84,12 +84,12 @@ class riscv_b_instr: riscv_instr
     if ([riscv_instr_format_t.I_FORMAT].canFind(instr_format)) {
       if ([riscv_instr_category_t.SHIFT,
 	   riscv_instr_category_t.LOGICAL].canFind(category)) {
-	imm_len = toubvec!5(clog2(XLEN));
+	imm_len = UBVEC!(5, clog2(XLEN));
       }
       // ARITHMETIC RV32B
       if ([riscv_instr_name_t.SHFLI,
 	   riscv_instr_name_t.UNSHFLI].canFind(instr_name)) {
-        imm_len = toubvec!5(clog2(XLEN) - 1);
+        imm_len = UBVEC!(5, clog2(XLEN) - 1);
       }
     }
 
@@ -99,7 +99,8 @@ class riscv_b_instr: riscv_instr
   // Convert the instruction to assembly code
   override string convert2asm(string prefix = "") {
     string asm_str_final, asm_str;
-    asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN);
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    asm_str = format!FMT(get_instr_name());
 
     switch (instr_format) {
     case riscv_instr_format_t.I_FORMAT:
@@ -129,23 +130,72 @@ class riscv_b_instr: riscv_instr
     return asm_str_final.toLower();
   }
 
+  override char[] convert2asm(char[] buf, string prefix = "") {
+    import std.string: toLower, toLowerInPlace;
+    import std.format: sformat;
+
+    char[32] instr_buf;
+    char[MAX_INSTR_STR_LEN+8] instr_name_buf;
+
+    char[] asm_buf;
+
+
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    char[] instr_name_str = sformat!FMT(instr_name_buf, get_instr_name(instr_buf));
+
+    switch (instr_format) {
+    case riscv_instr_format_t.I_FORMAT: 
+      if ([riscv_instr_name_t.FSRI,
+	   riscv_instr_name_t.FSRIW].canFind(instr_name)) {  // instr rd,rs1,rs3,imm
+	asm_buf = sformat!("%0s%0s, %0s, %0s, %0s")(buf, instr_name_str, rd, rs1,
+						    rs3, get_imm());
+      }
+      break;
+    case riscv_instr_format_t.R_FORMAT:  //instr rd rs1
+      if (! has_rs2) {
+	asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, rd, rs1);
+      }
+      break;
+    case riscv_instr_format_t.R4_FORMAT: // instr rd,rs1,rs2,rs3
+      asm_buf = sformat!("%0s%0s, %0s, %0s, %0s")(buf, instr_name_str, rd, rs1,
+						  rs2, rs3);
+      break;
+    default: uvm_info(get_full_name(), format("Unsupported format %0s", instr_format), UVM_LOW);
+    }
+
+    if (asm_buf == "") {
+      return super.convert2asm(buf, prefix);
+    }
+
+    if (comment != "") {
+      buf[asm_buf.length..asm_buf.length+2] = " #";
+      buf[asm_buf.length+2..asm_buf.length+2+comment.length] = comment;
+      asm_buf = buf[0..asm_buf.length+2+comment.length];
+    }
+
+    toLowerInPlace(asm_buf);
+
+    assert(asm_buf.ptr is buf.ptr);
+    return asm_buf;
+  }
+
   override ubvec!7 get_opcode() {
     switch (instr_name) {
     case riscv_instr_name_t.GORC,
       riscv_instr_name_t.SLO,
       riscv_instr_name_t.SRO,
       riscv_instr_name_t.GREV,
-      riscv_instr_name_t.XPERM_N,
-      riscv_instr_name_t.XPERM_B,
-      riscv_instr_name_t.XPERM_H,
-      riscv_instr_name_t.XPERM_W: return toubvec!7(0b0110011);
+      riscv_instr_name_t.XPERM4,
+      riscv_instr_name_t.XPERM8,
+      riscv_instr_name_t.XPERM16,
+      riscv_instr_name_t.XPERM32: return UBVEC!(7, 0b0110011);
     case riscv_instr_name_t.GORCI,
       riscv_instr_name_t.SLOI,
       riscv_instr_name_t.SROI,
       riscv_instr_name_t.GREVI,
       riscv_instr_name_t.CMIX,
       riscv_instr_name_t.CMOV,
-      riscv_instr_name_t.FSL: return toubvec!7(0b0010011);
+      riscv_instr_name_t.FSL: return UBVEC!(7, 0b0010011);
     case riscv_instr_name_t.FSR,
       riscv_instr_name_t.FSRI,
       riscv_instr_name_t.BMATFLIP,
@@ -153,10 +203,10 @@ class riscv_b_instr: riscv_instr
       riscv_instr_name_t.CRC32_H,
       riscv_instr_name_t.CRC32_W,
       riscv_instr_name_t.CRC32C_B,
-      riscv_instr_name_t.CRC32C_H: return toubvec!7(0b0010011);
+      riscv_instr_name_t.CRC32C_H: return UBVEC!(7, 0b0010011);
     case riscv_instr_name_t.CRC32C_W,
       riscv_instr_name_t.CRC32_D,
-      riscv_instr_name_t.CRC32C_D: return toubvec!7(0b0010011);
+      riscv_instr_name_t.CRC32C_D: return UBVEC!(7, 0b0010011);
     case riscv_instr_name_t.SHFL,
       riscv_instr_name_t.UNSHFL,
       riscv_instr_name_t.BCOMPRESS,
@@ -166,166 +216,166 @@ class riscv_b_instr: riscv_instr
       riscv_instr_name_t.BMATOR,
       riscv_instr_name_t.BMATXOR,
       riscv_instr_name_t.PACKH,
-      riscv_instr_name_t.BFP: return toubvec!7(0b0110011);
+      riscv_instr_name_t.BFP: return UBVEC!(7, 0b0110011);
     case riscv_instr_name_t.SHFLI,
-      riscv_instr_name_t.UNSHFLI: return toubvec!7(0b0010011);
+      riscv_instr_name_t.UNSHFLI: return UBVEC!(7, 0b0010011);
     case riscv_instr_name_t.SLOW,
       riscv_instr_name_t.SROW,
       riscv_instr_name_t.GORCW,
-      riscv_instr_name_t.GREVW: return toubvec!7(0b0111011);
+      riscv_instr_name_t.GREVW: return UBVEC!(7, 0b0111011);
     case riscv_instr_name_t.SLOIW,
       riscv_instr_name_t.SROIW,
       riscv_instr_name_t.GORCIW,
-      riscv_instr_name_t.GREVIW: return toubvec!7(0b0011011);
+      riscv_instr_name_t.GREVIW: return UBVEC!(7, 0b0011011);
     case riscv_instr_name_t.FSLW,
-      riscv_instr_name_t.FSRW: return toubvec!7(0b0111011);
-    case riscv_instr_name_t.FSRIW: return toubvec!7(0b0011011);
+      riscv_instr_name_t.FSRW: return UBVEC!(7, 0b0111011);
+    case riscv_instr_name_t.FSRIW: return UBVEC!(7, 0b0011011);
     case riscv_instr_name_t.SHFLW,
       riscv_instr_name_t.UNSHFLW,
       riscv_instr_name_t.BCOMPRESSW,
       riscv_instr_name_t.BDECOMPRESSW,
       riscv_instr_name_t.PACKW,
       riscv_instr_name_t.PACKUW,
-      riscv_instr_name_t.BFPW: return toubvec!7(0b0111011);
+      riscv_instr_name_t.BFPW: return UBVEC!(7, 0b0111011);
     default:                   return super.get_opcode();
     }
   }
 
   override ubvec!3 get_func3() {
     switch (instr_name) {
-    case riscv_instr_name_t.GORC: return toubvec!3(0b101);
-    case riscv_instr_name_t.GORCI: return toubvec!3(0b101);
-    case riscv_instr_name_t.SLO: return toubvec!3(0b001);
-    case riscv_instr_name_t.SRO: return toubvec!3(0b101);
-    case riscv_instr_name_t.SLOI: return toubvec!3(0b001);
-    case riscv_instr_name_t.SROI: return toubvec!3(0b101);
-    case riscv_instr_name_t.GREV: return toubvec!3(0b101);
-    case riscv_instr_name_t.GREVI: return toubvec!3(0b101);
-    case riscv_instr_name_t.CMIX: return toubvec!3(0b001);
-    case riscv_instr_name_t.CMOV: return toubvec!3(0b101);
-    case riscv_instr_name_t.FSL: return toubvec!3(0b001);
-    case riscv_instr_name_t.FSR: return toubvec!3(0b101);
-    case riscv_instr_name_t.FSRI: return toubvec!3(0b101);
-    case riscv_instr_name_t.BMATFLIP: return toubvec!3(0b001);
-    case riscv_instr_name_t.CRC32_B: return toubvec!3(0b001);
-    case riscv_instr_name_t.CRC32_H: return toubvec!3(0b001);
-    case riscv_instr_name_t.CRC32_W: return toubvec!3(0b001);
-    case riscv_instr_name_t.CRC32C_B: return toubvec!3(0b001);
-    case riscv_instr_name_t.CRC32C_H: return toubvec!3(0b001);
-    case riscv_instr_name_t.CRC32C_W: return toubvec!3(0b001);
-    case riscv_instr_name_t.CRC32_D: return toubvec!3(0b001);
-    case riscv_instr_name_t.CRC32C_D: return toubvec!3(0b001);
-    case riscv_instr_name_t.SHFL: return toubvec!3(0b001);
-    case riscv_instr_name_t.UNSHFL: return toubvec!3(0b101);
-    case riscv_instr_name_t.BCOMPRESS: return toubvec!3(0b110);
-    case riscv_instr_name_t.BDECOMPRESS: return toubvec!3(0b110);
-    case riscv_instr_name_t.PACK: return toubvec!3(0b100);
-    case riscv_instr_name_t.PACKU: return toubvec!3(0b100);
-    case riscv_instr_name_t.BMATOR: return toubvec!3(0b011);
-    case riscv_instr_name_t.BMATXOR: return toubvec!3(0b011);
-    case riscv_instr_name_t.PACKH: return toubvec!3(0b111);
-    case riscv_instr_name_t.BFP: return toubvec!3(0b111);
-    case riscv_instr_name_t.SHFLI: return toubvec!3(0b001);
-    case riscv_instr_name_t.UNSHFLI: return toubvec!3(0b101);
-    case riscv_instr_name_t.SLOW: return toubvec!3(0b001);
-    case riscv_instr_name_t.SROW: return toubvec!3(0b101);
-    case riscv_instr_name_t.ROLW: return toubvec!3(0b001);
-    case riscv_instr_name_t.GORCW: return toubvec!3(0b101);
-    case riscv_instr_name_t.GREVW: return toubvec!3(0b101);
-    case riscv_instr_name_t.SLOIW: return toubvec!3(0b001);
-    case riscv_instr_name_t.SROIW: return toubvec!3(0b101);
-    case riscv_instr_name_t.RORIW: return toubvec!3(0b101);
-    case riscv_instr_name_t.GORCIW: return toubvec!3(0b101);
-    case riscv_instr_name_t.GREVIW: return toubvec!3(0b101);
-    case riscv_instr_name_t.FSLW: return toubvec!3(0b001);
-    case riscv_instr_name_t.FSRW: return toubvec!3(0b101);
-    case riscv_instr_name_t.FSRIW: return toubvec!3(0b101);
-    case riscv_instr_name_t.SHFLW: return toubvec!3(0b001);
-    case riscv_instr_name_t.UNSHFLW: return toubvec!3(0b101);
-    case riscv_instr_name_t.BCOMPRESSW: return toubvec!3(0b110);
-    case riscv_instr_name_t.BDECOMPRESSW: return toubvec!3(0b110);
-    case riscv_instr_name_t.PACKW: return toubvec!3(0b100);
-    case riscv_instr_name_t.PACKUW: return toubvec!3(0b100);
-    case riscv_instr_name_t.BFPW: return toubvec!3(0b111);
-    case riscv_instr_name_t.XPERM_N: return toubvec!3(0b010);
-    case riscv_instr_name_t.XPERM_B: return toubvec!3(0b100);
-    case riscv_instr_name_t.XPERM_H: return toubvec!3(0b110);
-    case riscv_instr_name_t.XPERM_W: return toubvec!3(0b000);
+    case riscv_instr_name_t.GORC: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.GORCI: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.SLO: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.SRO: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.SLOI: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.SROI: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.GREV: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.GREVI: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.CMIX: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CMOV: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.FSL: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.FSR: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.FSRI: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.BMATFLIP: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CRC32_B: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CRC32_H: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CRC32_W: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CRC32C_B: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CRC32C_H: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CRC32C_W: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CRC32_D: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CRC32C_D: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.SHFL: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.UNSHFL: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.BCOMPRESS: return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.BDECOMPRESS: return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.PACK: return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.PACKU: return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.BMATOR: return UBVEC!(3, 0b011);
+    case riscv_instr_name_t.BMATXOR: return UBVEC!(3, 0b011);
+    case riscv_instr_name_t.PACKH: return UBVEC!(3, 0b111);
+    case riscv_instr_name_t.BFP: return UBVEC!(3, 0b111);
+    case riscv_instr_name_t.SHFLI: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.UNSHFLI: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.SLOW: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.SROW: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.ROLW: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.GORCW: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.GREVW: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.SLOIW: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.SROIW: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.RORIW: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.GORCIW: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.GREVIW: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.FSLW: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.FSRW: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.FSRIW: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.SHFLW: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.UNSHFLW: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.BCOMPRESSW: return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.BDECOMPRESSW: return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.PACKW: return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.PACKUW: return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.BFPW: return UBVEC!(3, 0b111);
+    case riscv_instr_name_t.XPERM4: return UBVEC!(3, 0b010);
+    case riscv_instr_name_t.XPERM8: return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.XPERM16: return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.XPERM32: return UBVEC!(3, 0b000);
     default:                         return super.get_func3();
     }
   }
 
   override ubvec!7 get_func7() {
     switch (instr_name) {
-    case riscv_instr_name_t.ANDN: return toubvec!7(0b0100000);
-    case riscv_instr_name_t.ORN: return toubvec!7(0b0100000);
-    case riscv_instr_name_t.XNOR: return toubvec!7(0b0100000);
-    case riscv_instr_name_t.GORC: return toubvec!7(0b0010100);
-    case riscv_instr_name_t.SLO: return toubvec!7(0b0010000);
-    case riscv_instr_name_t.SRO: return toubvec!7(0b0010000);
-    case riscv_instr_name_t.ROL: return toubvec!7(0b0110000);
-    case riscv_instr_name_t.ROR: return toubvec!7(0b0110000);
-    case riscv_instr_name_t.GREV: return toubvec!7(0b0110100);
-    case riscv_instr_name_t.BMATFLIP: return toubvec!7(0b0110000);
-    case riscv_instr_name_t.CRC32_B: return toubvec!7(0b0110000);
-    case riscv_instr_name_t.CRC32_H: return toubvec!7(0b0110000);
-    case riscv_instr_name_t.CRC32_W: return toubvec!7(0b0110000);
-    case riscv_instr_name_t.CRC32C_B: return toubvec!7(0b0110000);
-    case riscv_instr_name_t.CRC32C_H: return toubvec!7(0b0110000);
-    case riscv_instr_name_t.CRC32C_W: return toubvec!7(0b0110000);
-    case riscv_instr_name_t.CRC32_D: return toubvec!7(0b0110000);
-    case riscv_instr_name_t.CRC32C_D: return toubvec!7(0b0110000);
-    case riscv_instr_name_t.SHFL: return toubvec!7(0b0000100);
-    case riscv_instr_name_t.UNSHFL: return toubvec!7(0b0000100);
-    case riscv_instr_name_t.BCOMPRESS: return toubvec!7(0b0000100);
-    case riscv_instr_name_t.BDECOMPRESS: return toubvec!7(0b0100100);
-    case riscv_instr_name_t.PACK: return toubvec!7(0b0000100);
-    case riscv_instr_name_t.PACKU: return toubvec!7(0b0100100);
-    case riscv_instr_name_t.BMATOR: return toubvec!7(0b0000100);
-    case riscv_instr_name_t.BMATXOR: return toubvec!7(0b0100100);
-    case riscv_instr_name_t.PACKH: return toubvec!7(0b0000100);
-    case riscv_instr_name_t.BFP: return toubvec!7(0b0100100);
-    case riscv_instr_name_t.SLOW: return toubvec!7(0b0010000);
-    case riscv_instr_name_t.SROW: return toubvec!7(0b0010000);
-    case riscv_instr_name_t.GORCW: return toubvec!7(0b0010100);
-    case riscv_instr_name_t.GORCIW: return toubvec!7(0b0010100);
-    case riscv_instr_name_t.GREVW: return toubvec!7(0b0110100);
-    case riscv_instr_name_t.GREVIW: return toubvec!7(0b0110100);
-    case riscv_instr_name_t.SLOIW: return toubvec!7(0b0010000);
-    case riscv_instr_name_t.SROIW: return toubvec!7(0b0010000);
-    case riscv_instr_name_t.SHFLW: return toubvec!7(0b0000100);
-    case riscv_instr_name_t.UNSHFLW: return toubvec!7(0b0000100);
-    case riscv_instr_name_t.BCOMPRESSW: return toubvec!7(0b0000100);
-    case riscv_instr_name_t.BDECOMPRESSW: return toubvec!7(0b0100100);
-    case riscv_instr_name_t.PACKW: return toubvec!7(0b0000100);
-    case riscv_instr_name_t.PACKUW: return toubvec!7(0b0100100);
-    case riscv_instr_name_t.BFPW: return toubvec!7(0b0100100);
-    case riscv_instr_name_t.XPERM_N: return toubvec!7(0b0010100);
-    case riscv_instr_name_t.XPERM_B: return toubvec!7(0b0010100);
-    case riscv_instr_name_t.XPERM_H: return toubvec!7(0b0010100);
-    case riscv_instr_name_t.XPERM_W: return toubvec!7(0b0010100);
+    case riscv_instr_name_t.ANDN: return UBVEC!(7, 0b0100000);
+    case riscv_instr_name_t.ORN: return UBVEC!(7, 0b0100000);
+    case riscv_instr_name_t.XNOR: return UBVEC!(7, 0b0100000);
+    case riscv_instr_name_t.GORC: return UBVEC!(7, 0b0010100);
+    case riscv_instr_name_t.SLO: return UBVEC!(7, 0b0010000);
+    case riscv_instr_name_t.SRO: return UBVEC!(7, 0b0010000);
+    case riscv_instr_name_t.ROL: return UBVEC!(7, 0b0110000);
+    case riscv_instr_name_t.ROR: return UBVEC!(7, 0b0110000);
+    case riscv_instr_name_t.GREV: return UBVEC!(7, 0b0110100);
+    case riscv_instr_name_t.BMATFLIP: return UBVEC!(7, 0b0110000);
+    case riscv_instr_name_t.CRC32_B: return UBVEC!(7, 0b0110000);
+    case riscv_instr_name_t.CRC32_H: return UBVEC!(7, 0b0110000);
+    case riscv_instr_name_t.CRC32_W: return UBVEC!(7, 0b0110000);
+    case riscv_instr_name_t.CRC32C_B: return UBVEC!(7, 0b0110000);
+    case riscv_instr_name_t.CRC32C_H: return UBVEC!(7, 0b0110000);
+    case riscv_instr_name_t.CRC32C_W: return UBVEC!(7, 0b0110000);
+    case riscv_instr_name_t.CRC32_D: return UBVEC!(7, 0b0110000);
+    case riscv_instr_name_t.CRC32C_D: return UBVEC!(7, 0b0110000);
+    case riscv_instr_name_t.SHFL: return UBVEC!(7, 0b0000100);
+    case riscv_instr_name_t.UNSHFL: return UBVEC!(7, 0b0000100);
+    case riscv_instr_name_t.BCOMPRESS: return UBVEC!(7, 0b0000100);
+    case riscv_instr_name_t.BDECOMPRESS: return UBVEC!(7, 0b0100100);
+    case riscv_instr_name_t.PACK: return UBVEC!(7, 0b0000100);
+    case riscv_instr_name_t.PACKU: return UBVEC!(7, 0b0100100);
+    case riscv_instr_name_t.BMATOR: return UBVEC!(7, 0b0000100);
+    case riscv_instr_name_t.BMATXOR: return UBVEC!(7, 0b0100100);
+    case riscv_instr_name_t.PACKH: return UBVEC!(7, 0b0000100);
+    case riscv_instr_name_t.BFP: return UBVEC!(7, 0b0100100);
+    case riscv_instr_name_t.SLOW: return UBVEC!(7, 0b0010000);
+    case riscv_instr_name_t.SROW: return UBVEC!(7, 0b0010000);
+    case riscv_instr_name_t.GORCW: return UBVEC!(7, 0b0010100);
+    case riscv_instr_name_t.GORCIW: return UBVEC!(7, 0b0010100);
+    case riscv_instr_name_t.GREVW: return UBVEC!(7, 0b0110100);
+    case riscv_instr_name_t.GREVIW: return UBVEC!(7, 0b0110100);
+    case riscv_instr_name_t.SLOIW: return UBVEC!(7, 0b0010000);
+    case riscv_instr_name_t.SROIW: return UBVEC!(7, 0b0010000);
+    case riscv_instr_name_t.SHFLW: return UBVEC!(7, 0b0000100);
+    case riscv_instr_name_t.UNSHFLW: return UBVEC!(7, 0b0000100);
+    case riscv_instr_name_t.BCOMPRESSW: return UBVEC!(7, 0b0000100);
+    case riscv_instr_name_t.BDECOMPRESSW: return UBVEC!(7, 0b0100100);
+    case riscv_instr_name_t.PACKW: return UBVEC!(7, 0b0000100);
+    case riscv_instr_name_t.PACKUW: return UBVEC!(7, 0b0100100);
+    case riscv_instr_name_t.BFPW: return UBVEC!(7, 0b0100100);
+    case riscv_instr_name_t.XPERM4: return UBVEC!(7, 0b0010100);
+    case riscv_instr_name_t.XPERM8: return UBVEC!(7, 0b0010100);
+    case riscv_instr_name_t.XPERM16: return UBVEC!(7, 0b0010100);
+    case riscv_instr_name_t.XPERM32: return UBVEC!(7, 0b0010100);
     default:                         return super.get_func7();
     }
   }
 
   ubvec!5 get_func5() {
     switch (instr_name) {
-    case riscv_instr_name_t.SLOI: return toubvec!5(0b00100);
-    case riscv_instr_name_t.SROI: return toubvec!5(0b00100);
-    case riscv_instr_name_t.RORI: return toubvec!5(0b01100);
-    case riscv_instr_name_t.GORCI: return toubvec!5(0b00101);
-    case riscv_instr_name_t.GREVI: return toubvec!5(0b01101);
-
-    case riscv_instr_name_t.CRC32_B: return toubvec!5(0b10000);
-    case riscv_instr_name_t.CRC32_H: return toubvec!5(0b10001);
-    case riscv_instr_name_t.CRC32_W: return toubvec!5(0b10010);
-    case riscv_instr_name_t.CRC32C_B: return toubvec!5(0b11000);
-    case riscv_instr_name_t.CRC32C_H: return toubvec!5(0b11001);
-    case riscv_instr_name_t.CRC32C_W: return toubvec!5(0b11010);
-    case riscv_instr_name_t.CRC32_D: return toubvec!5(0b10011);
-    case riscv_instr_name_t.CRC32C_D: return toubvec!5(0b11011);
-
-    case riscv_instr_name_t.BMATFLIP: return toubvec!5(0b00011);
+    case riscv_instr_name_t.SLOI: return UBVEC!(5, 0b00100);
+    case riscv_instr_name_t.SROI: return UBVEC!(5, 0b00100);
+    case riscv_instr_name_t.RORI: return UBVEC!(5, 0b01100);
+    case riscv_instr_name_t.GORCI: return UBVEC!(5, 0b00101);
+    case riscv_instr_name_t.GREVI: return UBVEC!(5, 0b01101);
+
+    case riscv_instr_name_t.CRC32_B: return UBVEC!(5, 0b10000);
+    case riscv_instr_name_t.CRC32_H: return UBVEC!(5, 0b10001);
+    case riscv_instr_name_t.CRC32_W: return UBVEC!(5, 0b10010);
+    case riscv_instr_name_t.CRC32C_B: return UBVEC!(5, 0b11000);
+    case riscv_instr_name_t.CRC32C_H: return UBVEC!(5, 0b11001);
+    case riscv_instr_name_t.CRC32C_W: return UBVEC!(5, 0b11010);
+    case riscv_instr_name_t.CRC32_D: return UBVEC!(5, 0b10011);
+    case riscv_instr_name_t.CRC32C_D: return UBVEC!(5, 0b11011);
+
+    case riscv_instr_name_t.BMATFLIP: return UBVEC!(5, 0b00011);
     default: uvm_fatal(get_full_name(), format("Unsupported instruction %0s", instr_name));
       assert (false);
     }
@@ -333,13 +383,13 @@ class riscv_b_instr: riscv_instr
 
   ubvec!2 get_func2() {
     switch (instr_name) {
-    case riscv_instr_name_t.CMIX: return toubvec!2(0b11);
-    case riscv_instr_name_t.CMOV: return toubvec!2(0b11);
-    case riscv_instr_name_t.FSL: return toubvec!2(0b10);
-    case riscv_instr_name_t.FSR: return toubvec!2(0b10);
-    case riscv_instr_name_t.FSLW: return toubvec!2(0b10);
-    case riscv_instr_name_t.FSRW: return toubvec!2(0b10);
-    case riscv_instr_name_t.FSRIW: return toubvec!2(0b10);
+    case riscv_instr_name_t.CMIX: return UBVEC!(2, 0b11);
+    case riscv_instr_name_t.CMOV: return UBVEC!(2, 0b11);
+    case riscv_instr_name_t.FSL: return UBVEC!(2, 0b10);
+    case riscv_instr_name_t.FSR: return UBVEC!(2, 0b10);
+    case riscv_instr_name_t.FSLW: return UBVEC!(2, 0b10);
+    case riscv_instr_name_t.FSRW: return UBVEC!(2, 0b10);
+    case riscv_instr_name_t.FSRIW: return UBVEC!(2, 0b10);
     default: uvm_fatal(get_full_name(), format("Unsupported instruction %0s", instr_name));
       assert (false);
     }
@@ -359,8 +409,8 @@ class riscv_b_instr: riscv_instr
 	     riscv_instr_name_t.CRC32C_H,
 	     riscv_instr_name_t.CRC32C_W].canFind(instr_name)) {
 	  binary =
-	    format("%8h", get_func7() ~ get_func5() ~ toubvec!5(rs1) ~ get_func3() ~
-		   toubvec!5(rd) ~ get_opcode());
+	    format("%8h", get_func7() ~ get_func5() ~ rs1 ~ get_func3() ~
+		   rd ~ get_opcode());
 	}
       }
 
@@ -370,8 +420,8 @@ class riscv_b_instr: riscv_instr
 	     riscv_instr_name_t.CRC32C_D,
 	     riscv_instr_name_t.BMATFLIP].canFind(instr_name)) {
 	  binary =
-	    format("%8h", get_func7() ~ get_func5() ~ toubvec!5(rs1) ~ get_func3() ~
-		   toubvec!5(rd) ~ get_opcode());
+	    format("%8h", get_func7() ~ get_func5() ~ rs1 ~ get_func3() ~
+		   rd ~ get_opcode());
 	}
       }
       break;
@@ -379,37 +429,37 @@ class riscv_b_instr: riscv_instr
       if (([riscv_instr_category_t.SHIFT,
 	    riscv_instr_category_t.LOGICAL].canFind(category)) &&
 	  (group == riscv_instr_group_t.RV32B)) {
-	binary = format("%8h", get_func5() ~ cast(ubvec!7) imm[0..7] ~ toubvec!5(rs1) ~
-			get_func3() ~ toubvec!5(rd) ~ get_opcode());
+	binary = format("%8h", get_func5() ~ cast(ubvec!7) imm[0..7] ~ rs1 ~
+			get_func3() ~ rd ~ get_opcode());
       }
       else if (([riscv_instr_category_t.SHIFT,
 		 riscv_instr_category_t.LOGICAL].canFind(category)) &&
 	       (group == riscv_instr_group_t.RV64B)) {
-	binary = format("%8h", get_func7() ~ cast(ubvec!5) imm[0..5] ~ toubvec!5(rs1) ~
-			get_func3() ~ toubvec!5(rd) ~ get_opcode());
+	binary = format("%8h", get_func7() ~ cast(ubvec!5) imm[0..5] ~ rs1 ~
+			get_func3() ~ rd ~ get_opcode());
       }
 
       if ([riscv_instr_name_t.FSRI].canFind(instr_name)) {
-	binary = format("%8h", toubvec!5(rs3) ~ toubvec!1(0b1) ~ cast(ubvec!6) imm[0..6] ~
-			toubvec!5(rs1) ~ get_func3() ~ toubvec!5(rd) ~ get_opcode());
+	binary = format("%8h", rs3 ~ UBVEC!(1, 0b1) ~ cast(ubvec!6) imm[0..6] ~
+			rs1 ~ get_func3() ~ rd ~ get_opcode());
       }
 
       if (([riscv_instr_category_t.ARITHMETIC].canFind(category)) &&
 	  (group == riscv_instr_group_t.RV32B)) {
-	binary = format("%8h", toubvec!6(0b00_0010) ~ cast(ubvec!6) (imm[0..6]) ~
-			toubvec!5(rs1) ~ get_func3() ~ toubvec!5(rd) ~ get_opcode());
+	binary = format("%8h", UBVEC!(6, 0b00_0010) ~ cast(ubvec!6) (imm[0..6]) ~
+			rs1 ~ get_func3() ~ rd ~ get_opcode());
       }
 
       if (([riscv_instr_category_t.ARITHMETIC].canFind(category)) &&
 	  (group == riscv_instr_group_t.RV64B)) {
-	binary = format("%8h", cast(ubvec!12) imm[0..12] ~ toubvec!5(rs1) ~ get_func3() ~
-			toubvec!5(rd) ~ get_opcode());
+	binary = format("%8h", cast(ubvec!12) imm[0..12] ~ rs1 ~ get_func3() ~
+			rd ~ get_opcode());
       }
       break;
 
     case riscv_instr_format_t.R4_FORMAT:
-      binary = format("%8h", toubvec!5(rs3) ~ get_func2() ~ toubvec!5(rs2) ~ toubvec!5(rs1) ~
-		      get_func3() ~ toubvec!5(rd) ~ get_opcode());
+      binary = format("%8h", rs3 ~ get_func2() ~ rs2 ~ rs1 ~
+		      get_func3() ~ rd ~ get_opcode());
       break;
     default:
       if (binary == "") binary = super.convert2bin(prefix);
@@ -436,8 +486,8 @@ class riscv_b_instr: riscv_instr
 	 riscv_instr_name_t.SHFL, riscv_instr_name_t.SHFLW,
 	 riscv_instr_name_t.UNSHFL, riscv_instr_name_t.UNSHFLW,
 	 riscv_instr_name_t.SHFLI, riscv_instr_name_t.UNSHFLI,
-	 riscv_instr_name_t.XPERM_N, riscv_instr_name_t.XPERM_B,
-	 riscv_instr_name_t.XPERM_H, riscv_instr_name_t.XPERM_W,
+	 riscv_instr_name_t.XPERM4, riscv_instr_name_t.XPERM8,
+	 riscv_instr_name_t.XPERM16, riscv_instr_name_t.XPERM32,
 	 riscv_instr_name_t.SLO, riscv_instr_name_t.SLOW,
 	 riscv_instr_name_t.SLOI, riscv_instr_name_t.SLOIW,
 	 riscv_instr_name_t.SRO, riscv_instr_name_t.SROW,
diff --git a/euvm/riscv/gen/isa/riscv_compressed_instr.d b/euvm/riscv/gen/isa/riscv_compressed_instr.d
index e77855d3..c87262e0 100644
--- a/euvm/riscv/gen/isa/riscv_compressed_instr.d
+++ b/euvm/riscv/gen/isa/riscv_compressed_instr.d
@@ -17,14 +17,14 @@
 
 module riscv.gen.isa.riscv_compressed_instr;
 
-import riscv.gen.riscv_instr_pkg: format_string, riscv_instr_name_t, MAX_INSTR_STR_LEN,
+import riscv.gen.riscv_instr_pkg: riscv_instr_name_t, MAX_INSTR_STR_LEN,
   riscv_instr_format_t, riscv_reg_t, riscv_instr_category_t, imm_t;
 import riscv.gen.target: XLEN;
 import riscv.gen.isa.riscv_instr: riscv_instr;
 import std.format: format;
 
 import esdl.rand: constraint, rand;
-import esdl.data.bvec: ubvec, toubvec;
+import esdl.data.bvec: ubvec, UBVEC;
 
 import uvm;
 
@@ -34,76 +34,76 @@ class riscv_compressed_instr: riscv_instr
 
   int imm_align;
 
-  constraint! q{
-    //  Registers specified by the three-bit rs1’, rs2’, and rd’
-    if (instr_format inside [riscv_instr_format_t.CIW_FORMAT,
-			     riscv_instr_format_t.CL_FORMAT,
-			     riscv_instr_format_t.CS_FORMAT,
-			     riscv_instr_format_t.CB_FORMAT,
-			     riscv_instr_format_t.CA_FORMAT]) {
-      if (has_rs1) {
-	rs1 inside [riscv_reg_t.S0:riscv_reg_t.A5];
-      }
-      if (has_rs2) {
-	rs2 inside [riscv_reg_t.S0:riscv_reg_t.A5];
-      }
-      if (has_rd) {
-	rd inside [riscv_reg_t.S0:riscv_reg_t.A5];
-      }
-    }
-    // C_ADDI16SP is only valid when rd == SP
-    if (instr_name == riscv_instr_name_t.C_ADDI16SP) {
-      rd  == riscv_reg_t.SP;
-    }
-    if (instr_name inside [riscv_instr_name_t.C_JR, riscv_instr_name_t.C_JALR]) {
-      rs2 == riscv_reg_t.ZERO;
-      rs1 != riscv_reg_t.ZERO;
-    }
-  } rvc_csr_c ;
+  // constraint! q{
+  //   //  Registers specified by the three-bit rs1’, rs2’, and rd’
+  //   if (instr_format inside [riscv_instr_format_t.CIW_FORMAT,
+  // 			     riscv_instr_format_t.CL_FORMAT,
+  // 			     riscv_instr_format_t.CS_FORMAT,
+  // 			     riscv_instr_format_t.CB_FORMAT,
+  // 			     riscv_instr_format_t.CA_FORMAT]) {
+  //     if (has_rs1) {
+  // 	rs1 inside [riscv_reg_t.S0:riscv_reg_t.A5];
+  //     }
+  //     if (has_rs2) {
+  // 	rs2 inside [riscv_reg_t.S0:riscv_reg_t.A5];
+  //     }
+  //     if (has_rd) {
+  // 	rd inside [riscv_reg_t.S0:riscv_reg_t.A5];
+  //     }
+  //   }
+  //   // C_ADDI16SP is only valid when rd == SP
+  //   // if (instr_name == riscv_instr_name_t.C_ADDI16SP) {
+  //   //   rd  == riscv_reg_t.SP;
+  //   // }
+  //   // if (instr_name inside [riscv_instr_name_t.C_JR, riscv_instr_name_t.C_JALR]) {
+  //   //   rs2 == riscv_reg_t.ZERO;
+  //   //   rs1 != riscv_reg_t.ZERO;
+  //   // }
+  // } rvc_csr_c ;
 
-  constraint! q{
-    if(imm_type inside [imm_t.NZIMM, imm_t.NZUIMM]) {
-      imm[0..6] != 0;
-      if (instr_name == riscv_instr_name_t.C_LUI) {
-        // TODO(taliu) Check why bit 6 cannot be zero
-        imm[5..32] == 0;
-      }
-      if (instr_name inside [riscv_instr_name_t.C_SRAI,
-			     riscv_instr_name_t.C_SRLI,
-			     riscv_instr_name_t.C_SLLI]) {
-	imm[5..32] == 0;
-      }
-    }
-    if (instr_name == riscv_instr_name_t.C_ADDI4SPN) {
-      imm[0..2] == 0;
-    }
-  } imm_val_c ;
+  // constraint! q{
+  //   if(imm_type inside [imm_t.NZIMM, imm_t.NZUIMM]) {
+  //     imm[0..6] != 0;
+  //     if (instr_name == riscv_instr_name_t.C_LUI) {
+  //       // TODO(taliu) Check why bit 6 cannot be zero
+  //       imm[5..32] == 0;
+  //     }
+  //     if (instr_name inside [riscv_instr_name_t.C_SRAI,
+  // 			     riscv_instr_name_t.C_SRLI,
+  // 			     riscv_instr_name_t.C_SLLI]) {
+  // 	imm[5..32] == 0;
+  //     }
+  //   }
+  //   if (instr_name == riscv_instr_name_t.C_ADDI4SPN) {
+  //     imm[0..2] == 0;
+  //   }
+  // } imm_val_c ;
 
   // C_JAL is RV32C only instruction
-  constraint! q{
-    if (XLEN != 32) {
-      instr_name != riscv_instr_name_t.C_JAL;
-    }
-  } jal_c ;
+  // constraint! q{
+  //   if (XLEN != 32) {
+  //     instr_name != riscv_instr_name_t.C_JAL;
+  //   }
+  // } jal_c ;
 
   // Avoid generating HINT or illegal instruction by default as it's not supported by the compiler
-  constraint! q{
-    if (instr_name inside [riscv_instr_name_t.C_ADDI, riscv_instr_name_t.C_ADDIW,
-			   riscv_instr_name_t.C_LI, riscv_instr_name_t.C_LUI,
-			   riscv_instr_name_t.C_SLLI, riscv_instr_name_t.C_SLLI64,
-                           riscv_instr_name_t.C_LQSP, riscv_instr_name_t.C_LDSP,
-			   riscv_instr_name_t.C_MV, riscv_instr_name_t.C_ADD,
-			   riscv_instr_name_t.C_LWSP]) {
-      rd != riscv_reg_t.ZERO;
-    }
-    if (instr_name == riscv_instr_name_t.C_JR) {
-      rs1 != riscv_reg_t.ZERO;
-    }
-    if (instr_name inside [riscv_instr_name_t.C_ADD, riscv_instr_name_t.C_MV]) {
-      rs2 != riscv_reg_t.ZERO;
-    }
-    (instr_name == riscv_instr_name_t.C_LUI) -> (rd != riscv_reg_t.SP);
-  } no_hint_illegal_instr_c ;
+  // constraint! q{
+  //   if (instr_name inside [riscv_instr_name_t.C_ADDI, riscv_instr_name_t.C_ADDIW,
+  // 			   riscv_instr_name_t.C_LI, riscv_instr_name_t.C_LUI,
+  // 			   riscv_instr_name_t.C_SLLI, riscv_instr_name_t.C_SLLI64,
+  //                          riscv_instr_name_t.C_LQSP, riscv_instr_name_t.C_LDSP,
+  // 			   riscv_instr_name_t.C_MV, riscv_instr_name_t.C_ADD,
+  // 			   riscv_instr_name_t.C_LWSP]) {
+  //     rd != riscv_reg_t.ZERO;
+  //   }
+  //   if (instr_name == riscv_instr_name_t.C_JR) {
+  //     rs1 != riscv_reg_t.ZERO;
+  //   }
+  //   if (instr_name inside [riscv_instr_name_t.C_ADD, riscv_instr_name_t.C_MV]) {
+  //     rs2 != riscv_reg_t.ZERO;
+  //   }
+  //   (instr_name == riscv_instr_name_t.C_LUI) -> (rd != riscv_reg_t.SP);
+  // } no_hint_illegal_instr_c ;
 
   this(string name = "") {
     super(name);
@@ -116,24 +116,24 @@ class riscv_compressed_instr: riscv_instr
 
   override void set_imm_len() {
     if ( instr_format.inside(riscv_instr_format_t.CI_FORMAT, riscv_instr_format_t.CSS_FORMAT)) {
-      imm_len = toubvec!5(6);
+      imm_len = UBVEC!(5, 6);
     }
     else if (instr_format.inside(riscv_instr_format_t.CL_FORMAT, riscv_instr_format_t.CS_FORMAT)) {
-      imm_len = toubvec!5(5);
+      imm_len = UBVEC!(5, 5);
     }
     else if (instr_format == riscv_instr_format_t.CJ_FORMAT) {
-      imm_len = toubvec!5(11);
+      imm_len = UBVEC!(5, 11);
     }
     else if (instr_format == riscv_instr_format_t.CB_FORMAT) {
       if (instr_name == riscv_instr_name_t.C_ANDI) {
-        imm_len = toubvec!5(6);
+        imm_len = UBVEC!(5, 6);
       }
       else {
-        imm_len = toubvec!5(7);
+        imm_len = UBVEC!(5, 7);
       }
     }
     else if (instr_format.inside(riscv_instr_format_t.CB_FORMAT, riscv_instr_format_t.CIW_FORMAT)) {
-      imm_len = toubvec!5(8);
+      imm_len = UBVEC!(5, 8);
     }
     if (instr_name.inside(riscv_instr_name_t.C_SQ, riscv_instr_name_t.C_LQ,
 			  riscv_instr_name_t.C_LQSP, riscv_instr_name_t.C_SQSP,
@@ -218,7 +218,8 @@ class riscv_compressed_instr: riscv_instr
   // Convert the instruction to assembly code
   override string convert2asm(string prefix = "") {
     import std.string: toLower;
-    string asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN);
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    string asm_str = format!FMT(get_instr_name());
     if (category != riscv_instr_category_t.SYSTEM) {
       switch(instr_format) {
       case riscv_instr_format_t.CI_FORMAT,
@@ -284,6 +285,99 @@ class riscv_compressed_instr: riscv_instr
     return asm_str.toLower();
   }
 
+  override char[] convert2asm(char[] buf, string prefix = "") {
+    import std.string: toLower, toLowerInPlace;
+    import std.format: sformat;
+
+    char[32] instr_buf;
+    char[MAX_INSTR_STR_LEN+8] instr_name_buf;
+
+    string asm_str;
+    char[] asm_buf;
+
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    char[] instr_name_str = sformat!FMT(instr_name_buf, get_instr_name(instr_buf));
+
+    if (category != riscv_instr_category_t.SYSTEM) {
+      switch(instr_format) {
+      case riscv_instr_format_t.CI_FORMAT,
+	riscv_instr_format_t.CIW_FORMAT :
+	if (instr_name == riscv_instr_name_t.C_NOP)
+	  asm_str = "c.nop";
+	else if (instr_name == riscv_instr_name_t.C_ADDI16SP)
+	  asm_buf = sformat!("%0ssp, %0s")(buf, instr_name_str, get_imm());
+	else if (instr_name == riscv_instr_name_t.C_ADDI4SPN)
+	  asm_buf = sformat!("%0s%0s, sp, %0s")(buf, instr_name_str, rd, get_imm());
+	else if (instr_name.inside(riscv_instr_name_t.C_LDSP, riscv_instr_name_t.C_LWSP,
+				   riscv_instr_name_t.C_LQSP))
+	  asm_buf = sformat!("%0s%0s, %0s(sp)")(buf, instr_name_str, rd, get_imm());
+	else
+	  asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, rd, get_imm());
+	break;
+      case riscv_instr_format_t.CL_FORMAT :
+	asm_buf = sformat!("%0s%0s, %0s(%0s)")(buf, instr_name_str, rd, get_imm(), rs1);
+	break;
+      case riscv_instr_format_t.CS_FORMAT:
+	if (category == riscv_instr_category_t.STORE)
+	  asm_buf = sformat!("%0s%0s, %0s(%0s)")(buf, instr_name_str, rs2, get_imm(), rs1);
+	else
+	  asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, rs1, rs2);
+	break;
+      case riscv_instr_format_t.CA_FORMAT :
+	asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, rd, rs2);
+	break;
+      case riscv_instr_format_t.CB_FORMAT:
+	asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, rs1, get_imm());
+	break;
+      case riscv_instr_format_t.CSS_FORMAT:
+	if (category == riscv_instr_category_t.STORE)
+	  asm_buf = sformat!("%0s%0s, %0s(sp)")(buf, instr_name_str, rs2, get_imm());
+	else
+	  asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, rs2, get_imm());
+	break;
+      case riscv_instr_format_t.CR_FORMAT:
+	if (instr_name.inside(riscv_instr_name_t.C_JR, riscv_instr_name_t.C_JALR)) {
+	  asm_buf = sformat!("%0s%0s")(buf, instr_name_str, rs1);
+	}
+	else {
+	  asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, rd, rs2);
+	}
+	break;
+      case riscv_instr_format_t.CJ_FORMAT:
+	asm_buf = sformat!("%0s%0s")(buf, instr_name_str, get_imm());
+	break;
+      default: uvm_info(get_full_name(),
+			format("Unsupported format %0s", instr_format), UVM_LOW);
+	break; 
+      }
+    }
+    else {
+      // For EBREAK,C.EBREAK, making sure pc+4 is a valid instruction boundary
+      // This is needed to resume execution from epc+4 after ebreak handling
+      if (instr_name == riscv_instr_name_t.C_EBREAK) {
+	asm_str = "c.ebreak; c.nop;";
+      }
+    }
+
+    if (asm_str.length > 0) {
+      assert (asm_buf.length == 0);
+      buf[0..asm_str.length] = asm_str;
+      asm_buf = buf[0..asm_str.length];
+    }
+
+    
+    if (comment != "") {
+      buf[asm_buf.length..asm_buf.length+2] = " #";
+      buf[asm_buf.length+2..asm_buf.length+2+comment.length] = comment;
+      asm_buf = buf[0..asm_buf.length+2+comment.length];
+    }
+
+    toLowerInPlace(asm_buf);
+
+    assert(asm_buf.ptr is buf.ptr);
+    return asm_buf;
+  }
+
   // Convert the instruction to assembly code
   override string convert2bin(string prefix = "") {
     string binary;
@@ -297,11 +391,11 @@ class riscv_compressed_instr: riscv_instr
 			      get_c_gpr(rs1) ~ cast(ubvec!2) imm[6..8] ~ get_c_gpr(rd) ~
 			      get_c_opcode()));
       break;
-    case riscv_instr_name_t.C_FLD, riscv_instr_name_t.C_LD:
+    case riscv_instr_name_t.C_LD:
       binary = format("%4h", (get_func3() ~ cast(ubvec!3) imm[3..6] ~ get_c_gpr(rs1) ~
 			      cast(ubvec!2) imm[6..8] ~ get_c_gpr(rd) ~ get_c_opcode()));
       break;
-    case riscv_instr_name_t.C_LW, riscv_instr_name_t.C_FLW:
+    case riscv_instr_name_t.C_LW:
       binary = format("%4h", (get_func3() ~ cast(ubvec!3) imm[3..6] ~ get_c_gpr(rs1) ~
 			      imm[2] ~ imm[6] ~ get_c_gpr(rd) ~ get_c_opcode()));
       break;
@@ -310,17 +404,17 @@ class riscv_compressed_instr: riscv_instr
 			      get_c_gpr(rs1) ~ cast(ubvec!2) imm[6..8] ~ get_c_gpr(rs2) ~
 			      get_c_opcode()));
       break;
-    case riscv_instr_name_t.C_FSD, riscv_instr_name_t.C_SD:
+    case riscv_instr_name_t.C_SD:
       binary = format("%4h", (get_func3() ~ cast(ubvec!3) imm[3..6] ~ get_c_gpr(rs1) ~
 			      cast(ubvec!2) imm[6..8] ~ get_c_gpr(rs2) ~ get_c_opcode()));
       break;
-    case riscv_instr_name_t.C_SW, riscv_instr_name_t.C_FSW:
+    case riscv_instr_name_t.C_SW:
       binary = format("%4h", (get_func3() ~ cast(ubvec!3) imm[3..6] ~ get_c_gpr(rs1) ~
 			      imm[2] ~ imm[6] ~ get_c_gpr(rs2) ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_NOP, riscv_instr_name_t.C_ADDI,
       riscv_instr_name_t.C_LI, riscv_instr_name_t.C_ADDIW:
-      binary = format("%4h", (get_func3() ~ imm[5] ~ toubvec!5(rd) ~ cast(ubvec!5) imm[0..5] ~
+      binary = format("%4h", (get_func3() ~ imm[5] ~ rd ~ cast(ubvec!5) imm[0..5] ~
 			      get_c_opcode()));
       break;
     case riscv_instr_name_t.C_JAL, riscv_instr_name_t.C_J:
@@ -329,56 +423,56 @@ class riscv_compressed_instr: riscv_instr
 			      get_c_opcode()));
       break;
     case riscv_instr_name_t.C_ADDI16SP:
-      binary = format("%4h", (get_func3() ~ imm[9] ~ toubvec!5(0b10) ~
+      binary = format("%4h", (get_func3() ~ imm[9] ~ UBVEC!(5, 0b10) ~
 			      imm[4] ~ imm[6] ~ cast(ubvec!2) imm[7..9] ~ imm[5] ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_LUI:
-      binary = format("%4h", (get_func3() ~ imm[5] ~ toubvec!5(rd) ~ cast(ubvec!5) imm[0..5] ~
+      binary = format("%4h", (get_func3() ~ imm[5] ~ rd ~ cast(ubvec!5) imm[0..5] ~
 			      get_c_opcode()));
       break;
     case riscv_instr_name_t.C_SRLI:
-      binary = format("%4h", (get_func3() ~ imm[5] ~ toubvec!2(0b0) ~ get_c_gpr(rd) ~
+      binary = format("%4h", (get_func3() ~ imm[5] ~ UBVEC!(2, 0b0) ~ get_c_gpr(rd) ~
 			      cast(ubvec!5) imm[0..5] ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_SRLI64:
-      binary = format("%4h", (get_func3() ~ toubvec!3(0b0) ~ get_c_gpr(rd) ~ toubvec!5(0b0) ~
+      binary = format("%4h", (get_func3() ~ UBVEC!(3, 0b0) ~ get_c_gpr(rd) ~ UBVEC!(5, 0b0) ~
 			      get_c_opcode()));
       break;
     case riscv_instr_name_t.C_SRAI:
-      binary = format("%4h", (get_func3() ~ imm[5] ~ toubvec!2(0b01) ~ get_c_gpr(rd) ~
+      binary = format("%4h", (get_func3() ~ imm[5] ~ UBVEC!(2, 0b01) ~ get_c_gpr(rd) ~
 			      cast(ubvec!5) imm[0..5] ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_SRAI64:
-      binary = format("%4h", (get_func3() ~ toubvec!3(0b001) ~
-			      get_c_gpr(rd) ~ toubvec!5(0b0) ~ get_c_opcode()));
+      binary = format("%4h", (get_func3() ~ UBVEC!(3, 0b001) ~
+			      get_c_gpr(rd) ~ UBVEC!(5, 0b0) ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_ANDI:
-      binary = format("%4h", (get_func3() ~ imm[5] ~ toubvec!2(0b10) ~ get_c_gpr(rd) ~
+      binary = format("%4h", (get_func3() ~ imm[5] ~ UBVEC!(2, 0b10) ~ get_c_gpr(rd) ~
 			      cast(ubvec!5) imm[0..5] ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_SUB:
-      binary = format("%4h", (get_func3() ~ toubvec!3(0b011) ~ get_c_gpr(rd) ~
-			      toubvec!2(0b00) ~ get_c_gpr(rs2) ~ get_c_opcode()));
+      binary = format("%4h", (get_func3() ~ UBVEC!(3, 0b011) ~ get_c_gpr(rd) ~
+			      UBVEC!(2, 0b00) ~ get_c_gpr(rs2) ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_XOR:
-      binary = format("%4h", (get_func3() ~ toubvec!3(0b011) ~ get_c_gpr(rd) ~
-			      toubvec!2(0b01) ~ get_c_gpr(rs2) ~ get_c_opcode()));
+      binary = format("%4h", (get_func3() ~ UBVEC!(3, 0b011) ~ get_c_gpr(rd) ~
+			      UBVEC!(2, 0b01) ~ get_c_gpr(rs2) ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_OR:
-      binary = format("%4h", (get_func3() ~ toubvec!3(0b011) ~ get_c_gpr(rd) ~
-			      toubvec!2(0b10) ~ get_c_gpr(rs2) ~ get_c_opcode()));
+      binary = format("%4h", (get_func3() ~ UBVEC!(3, 0b011) ~ get_c_gpr(rd) ~
+			      UBVEC!(2, 0b10) ~ get_c_gpr(rs2) ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_AND:
-      binary = format("%4h", (get_func3() ~ toubvec!3(0b011) ~ get_c_gpr(rd) ~
-			      toubvec!2(0b11) ~ get_c_gpr(rs2) ~ get_c_opcode()));
+      binary = format("%4h", (get_func3() ~ UBVEC!(3, 0b011) ~ get_c_gpr(rd) ~
+			      UBVEC!(2, 0b11) ~ get_c_gpr(rs2) ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_SUBW:
-      binary = format("%4h", (get_func3() ~ toubvec!3(0b111) ~ get_c_gpr(rd) ~
-			      toubvec!2(0b00) ~ get_c_gpr(rs2) ~ get_c_opcode()));
+      binary = format("%4h", (get_func3() ~ UBVEC!(3, 0b111) ~ get_c_gpr(rd) ~
+			      UBVEC!(2, 0b00) ~ get_c_gpr(rs2) ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_ADDW:
-      binary = format("%4h", (get_func3() ~ toubvec!3(0b111) ~ get_c_gpr(rd) ~
-			      toubvec!2(0b01) ~ get_c_gpr(rs2) ~ get_c_opcode()));
+      binary = format("%4h", (get_func3() ~ UBVEC!(3, 0b111) ~ get_c_gpr(rd) ~
+			      UBVEC!(2, 0b01) ~ get_c_gpr(rs2) ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_BEQZ, riscv_instr_name_t.C_BNEZ:
       binary = format("%4h", (get_func3() ~ imm[8] ~ cast(ubvec!2) imm[3..5] ~
@@ -386,56 +480,56 @@ class riscv_compressed_instr: riscv_instr
 			      imm[5] ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_SLLI:
-      binary = format("%4h", (get_func3() ~ imm[5] ~ toubvec!5(rd) ~ cast(ubvec!5) imm[0..5] ~
+      binary = format("%4h", (get_func3() ~ imm[5] ~ rd ~ cast(ubvec!5) imm[0..5] ~
 			      get_c_opcode()));
       break;
     case riscv_instr_name_t.C_SLLI64:
-      binary = format("%4h", (get_func3() ~ toubvec!1(0b0) ~ toubvec!5(rd) ~ toubvec!5(0b00000) ~
+      binary = format("%4h", (get_func3() ~ UBVEC!(1, 0b0) ~ rd ~ UBVEC!(5, 0b00000) ~
 			      get_c_opcode()));
       break;
-    case riscv_instr_name_t.C_FLDSP, riscv_instr_name_t.C_LDSP:
-      binary = format("%4h", (get_func3() ~ imm[5] ~ toubvec!5(rd) ~ cast(ubvec!2) imm[3..5] ~
+    case riscv_instr_name_t.C_LDSP:
+      binary = format("%4h", (get_func3() ~ imm[5] ~ rd ~ cast(ubvec!2) imm[3..5] ~
 			      cast(ubvec!3) imm[6..9] ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_LQSP:
-      binary = format("%4h", (get_func3() ~ imm[5] ~ toubvec!5(rd) ~ imm[4] ~
+      binary = format("%4h", (get_func3() ~ imm[5] ~ rd ~ imm[4] ~
 			      cast(ubvec!4) imm[6..10] ~ get_c_opcode()));
       break;
-    case riscv_instr_name_t.C_LWSP, riscv_instr_name_t.C_FLWSP:
-      binary = format("%4h", (get_func3() ~ imm[5] ~ toubvec!5(rd) ~ cast(ubvec!3) imm[2..5] ~
+    case riscv_instr_name_t.C_LWSP:
+      binary = format("%4h", (get_func3() ~ imm[5] ~ rd ~ cast(ubvec!3) imm[2..5] ~
 			      cast(ubvec!2) imm[6..8]  ~ get_c_opcode()));
       break;
     case riscv_instr_name_t.C_JR:
-      binary = format("%4h", (get_func3() ~ toubvec!1(0b0) ~ toubvec!5(rs1) ~ toubvec!5(0b0) ~
+      binary = format("%4h", (get_func3() ~ UBVEC!(1, 0b0) ~ rs1 ~ UBVEC!(5, 0b0) ~
 			      get_c_opcode()));
       break;
     case riscv_instr_name_t.C_MV:
-      binary = format("%4h", (get_func3() ~ toubvec!1(0b0) ~ toubvec!5(rd) ~ toubvec!5(rs2) ~
+      binary = format("%4h", (get_func3() ~ UBVEC!(1, 0b0) ~ rd ~ rs2 ~
 			      get_c_opcode()));
       break;
     case riscv_instr_name_t.C_EBREAK:
-      binary = format("%4h", (get_func3() ~ toubvec!1(0b1) ~ toubvec!10(0b0) ~
+      binary = format("%4h", (get_func3() ~ UBVEC!(1, 0b1) ~ rs1 ~ UBVEC!(5, 0b0) ~
 			      get_c_opcode()));
       break;
     case riscv_instr_name_t.C_JALR:
-      binary = format("%4h", (get_func3() ~ toubvec!1(0b1) ~ toubvec!10(0b0) ~
+      binary = format("%4h", (get_func3() ~ UBVEC!(1, 0b1) ~ UBVEC!(5, 0b0) ~
 			      get_c_opcode()));
       break;
     case riscv_instr_name_t.C_ADD:
-      binary = format("%4h", (get_func3() ~ toubvec!1(0b1) ~ toubvec!5(rd) ~ toubvec!5(rs2) ~
+      binary = format("%4h", (get_func3() ~ UBVEC!(1, 0b1) ~ rd ~ rs2 ~
 			      get_c_opcode()));
       break;
-    case riscv_instr_name_t.C_FSDSP, riscv_instr_name_t.C_SDSP:
+    case riscv_instr_name_t.C_SDSP:
       binary = format("%4h", (get_func3() ~ cast(ubvec!3) imm[3..6] ~ cast(ubvec!3) imm[6..9]  ~
-			      toubvec!5(rs2) ~ get_c_opcode()));
+			      rs2 ~ get_c_opcode()));
       break;
-    case riscv_instr_name_t.C_SQSP :
+    case riscv_instr_name_t.C_SQSP:
       binary = format("%4h", (get_func3() ~ cast(ubvec!2) imm[4..6] ~ cast(ubvec!4) imm[6..10] ~
-			      toubvec!5(rs2) ~ get_c_opcode()));
+			      rs2 ~ get_c_opcode()));
       break;
-    case riscv_instr_name_t.C_SWSP, riscv_instr_name_t.C_FSWSP  :
+    case riscv_instr_name_t.C_SWSP:
       binary = format("%4h", (get_func3() ~ cast(ubvec!4) imm[2..6] ~ cast(ubvec!2) imm[6..8] ~
-			      toubvec!5(rs2) ~ get_c_opcode()));
+			      rs2 ~ get_c_opcode()));
       break;
     default : uvm_fatal(get_full_name(),
 			format("Unsupported instruction %0s", instr_name));
@@ -448,16 +542,13 @@ class riscv_compressed_instr: riscv_instr
   ubvec!2 get_c_opcode() {
     switch(instr_name) {
     case riscv_instr_name_t.C_ADDI4SPN,
-      riscv_instr_name_t.C_FLD,
       riscv_instr_name_t.C_LQ,
       riscv_instr_name_t.C_LW,
-      riscv_instr_name_t.C_FLW,
       riscv_instr_name_t.C_LD,
       riscv_instr_name_t.C_FSD,
       riscv_instr_name_t.C_SQ,
       riscv_instr_name_t.C_SW,
-      riscv_instr_name_t.C_FSW,
-      riscv_instr_name_t.C_SD : return toubvec!2(0b00);
+      riscv_instr_name_t.C_SD : return UBVEC!(2, 0b00);
     case riscv_instr_name_t.C_NOP,
       riscv_instr_name_t.C_ADDI,
       riscv_instr_name_t.C_JAL,
@@ -478,24 +569,20 @@ class riscv_compressed_instr: riscv_instr
       riscv_instr_name_t.C_ADDW,
       riscv_instr_name_t.C_J,
       riscv_instr_name_t.C_BEQZ,
-      riscv_instr_name_t.C_BNEZ : return toubvec!2(0b01);
+      riscv_instr_name_t.C_BNEZ : return UBVEC!(2, 0b01);
     case riscv_instr_name_t.C_SLLI,
       riscv_instr_name_t.C_SLLI64,
-      riscv_instr_name_t.C_FLDSP,
       riscv_instr_name_t.C_LQSP,
       riscv_instr_name_t.C_LWSP,
-      riscv_instr_name_t.C_FLWSP,
       riscv_instr_name_t.C_LDSP,
       riscv_instr_name_t.C_JR,
       riscv_instr_name_t.C_MV,
       riscv_instr_name_t.C_EBREAK,
       riscv_instr_name_t.C_JALR,
       riscv_instr_name_t.C_ADD,
-      riscv_instr_name_t.C_FSDSP,
       riscv_instr_name_t.C_SQSP,
       riscv_instr_name_t.C_SWSP,
-      riscv_instr_name_t.C_FSWSP,
-      riscv_instr_name_t.C_SDSP : return toubvec!2(0b10);
+      riscv_instr_name_t.C_SDSP : return UBVEC!(2, 0b10);
     default :
       uvm_fatal(get_full_name(), format("Unsupported instruction %0s", instr_name));
       assert (false);
@@ -505,55 +592,47 @@ class riscv_compressed_instr: riscv_instr
   //ubvec!3 get_func3()
   override ubvec!3 get_func3() {
     switch(instr_name) {
-    case riscv_instr_name_t.C_ADDI4SPN : return toubvec!3(0b000);
-    case riscv_instr_name_t.C_FLD      : return toubvec!3(0b001);
-    case riscv_instr_name_t.C_LQ       : return toubvec!3(0b001);
-    case riscv_instr_name_t.C_LW       : return toubvec!3(0b010);
-    case riscv_instr_name_t.C_FLW      : return toubvec!3(0b011);
-    case riscv_instr_name_t.C_LD       : return toubvec!3(0b011);
-    case riscv_instr_name_t.C_FSD      : return toubvec!3(0b101);
-    case riscv_instr_name_t.C_SQ       : return toubvec!3(0b101);
-    case riscv_instr_name_t.C_SW       : return toubvec!3(0b110);
-    case riscv_instr_name_t.C_FSW      : return toubvec!3(0b111);
-    case riscv_instr_name_t.C_SD       : return toubvec!3(0b111);
-    case riscv_instr_name_t.C_NOP      : return toubvec!3(0b000);
-    case riscv_instr_name_t.C_ADDI     : return toubvec!3(0b000);
-    case riscv_instr_name_t.C_JAL      : return toubvec!3(0b001);
-    case riscv_instr_name_t.C_ADDIW    : return toubvec!3(0b001);
-    case riscv_instr_name_t.C_LI       : return toubvec!3(0b010);
-    case riscv_instr_name_t.C_ADDI16SP : return toubvec!3(0b011);
-    case riscv_instr_name_t.C_LUI      : return toubvec!3(0b011);
-    case riscv_instr_name_t.C_SRLI     : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_SRLI64   : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_SRAI     : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_SRAI64   : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_ANDI     : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_SUB      : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_XOR      : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_OR       : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_AND      : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_SUBW     : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_ADDW     : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_J        : return toubvec!3(0b101);
-    case riscv_instr_name_t.C_BEQZ     : return toubvec!3(0b110);
-    case riscv_instr_name_t.C_BNEZ     : return toubvec!3(0b111);
-    case riscv_instr_name_t.C_SLLI     : return toubvec!3(0b000);
-    case riscv_instr_name_t.C_SLLI64   : return toubvec!3(0b000);
-    case riscv_instr_name_t.C_FLDSP    : return toubvec!3(0b001);
-    case riscv_instr_name_t.C_LQSP     : return toubvec!3(0b001);
-    case riscv_instr_name_t.C_LWSP     : return toubvec!3(0b010);
-    case riscv_instr_name_t.C_FLWSP    : return toubvec!3(0b011);
-    case riscv_instr_name_t.C_LDSP     : return toubvec!3(0b011);
-    case riscv_instr_name_t.C_JR       : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_MV       : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_EBREAK   : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_JALR     : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_ADD      : return toubvec!3(0b100);
-    case riscv_instr_name_t.C_FSDSP    : return toubvec!3(0b101);
-    case riscv_instr_name_t.C_SQSP     : return toubvec!3(0b101);
-    case riscv_instr_name_t.C_SWSP     : return toubvec!3(0b110);
-    case riscv_instr_name_t.C_FSWSP    : return toubvec!3(0b111);
-    case riscv_instr_name_t.C_SDSP     : return toubvec!3(0b111);
+    case riscv_instr_name_t.C_ADDI4SPN : return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.C_LQ       : return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.C_LW       : return UBVEC!(3, 0b010);
+    case riscv_instr_name_t.C_LD       : return UBVEC!(3, 0b011);
+    case riscv_instr_name_t.C_SQ       : return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.C_SW       : return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.C_SD       : return UBVEC!(3, 0b111);
+    case riscv_instr_name_t.C_NOP      : return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.C_ADDI     : return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.C_JAL      : return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.C_ADDIW    : return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.C_LI       : return UBVEC!(3, 0b010);
+    case riscv_instr_name_t.C_ADDI16SP : return UBVEC!(3, 0b011);
+    case riscv_instr_name_t.C_LUI      : return UBVEC!(3, 0b011);
+    case riscv_instr_name_t.C_SRLI     : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_SRLI64   : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_SRAI     : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_SRAI64   : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_ANDI     : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_SUB      : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_XOR      : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_OR       : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_AND      : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_SUBW     : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_ADDW     : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_J        : return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.C_BEQZ     : return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.C_BNEZ     : return UBVEC!(3, 0b111);
+    case riscv_instr_name_t.C_SLLI     : return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.C_SLLI64   : return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.C_LQSP     : return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.C_LWSP     : return UBVEC!(3, 0b010);
+    case riscv_instr_name_t.C_LDSP     : return UBVEC!(3, 0b011);
+    case riscv_instr_name_t.C_JR       : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_MV       : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_EBREAK   : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_JALR     : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_ADD      : return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.C_SQSP     : return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.C_SWSP     : return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.C_SDSP     : return UBVEC!(3, 0b111);
     default : uvm_fatal(get_full_name(), format("Unsupported instruction %0s", instr_name));
       assert (false);
     }
diff --git a/euvm/riscv/gen/isa/riscv_csr_instr.d b/euvm/riscv/gen/isa/riscv_csr_instr.d
new file mode 100644
index 00000000..a90e2b67
--- /dev/null
+++ b/euvm/riscv/gen/isa/riscv_csr_instr.d
@@ -0,0 +1,216 @@
+/*
+ * Copyright 2019 Google LLC
+ * Copyright 2023 Coverify Systems Technology
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+module riscv.gen.isa.riscv_csr_instr;
+
+import riscv.gen.riscv_instr_pkg: riscv_instr_group_t, riscv_instr_name_t,
+  riscv_instr_format_t, riscv_instr_category_t, MAX_INSTR_STR_LEN, format_string;
+import riscv.gen.isa.riscv_instr: riscv_instr;
+import riscv.gen.target: XLEN;
+import riscv.gen.riscv_instr_gen_config: riscv_instr_gen_config;
+import riscv.gen.target: supported_isa;
+
+import std.format: format;
+
+import esdl.data.bvec: ubvec, UBVEC, clog2;
+import esdl.rand: constraint, rand;
+import uvm;
+
+import std.algorithm: canFind;
+
+
+class riscv_csr_instr: riscv_instr
+{
+  // Moved to riscv_instr_gen_config
+  // Privileged CSR filter
+  // static ubvec!12[]    exclude_reg[];
+  // static ubvec!12[]    include_reg[];
+  // static ubvec!12[]    include_write_reg;
+  // When set writes to read-only CSRs can be generated
+  // static bit allow_ro_write;
+
+  @rand bool write_csr;
+
+  // m_cfg is declared in the base class
+
+  constraint! q{
+    if (m_cfg.csr_cfg.include_reg.length > 0) {
+      csr inside [m_cfg.csr_cfg.include_reg];
+    }
+    if (m_cfg.csr_cfg.exclude_reg.length > 0) {
+      csr !inside [m_cfg.csr_cfg.exclude_reg];
+    }
+  }  csr_addr_c;
+
+  constraint! q{
+    // We can only write a CSR if:
+    // - It's a read-only CSR and we're generating writes to read-only CSRs
+    // - Specific CSRs to write to are specified and this CSR is one
+    // - No specific CSRs to write to are specified and this isn't a read-only CSR
+    if (!((csr[10..12] == 0b11 && m_cfg.csr_cfg.allow_ro_write) ||
+	  ((m_cfg.csr_cfg.include_write_reg.length > 0) &&
+	   (csr inside [m_cfg.csr_cfg.include_write_reg])) ||
+	  ((csr[10..12] != 0b11) && (m_cfg.csr_cfg.include_write_reg.length == 0)))) {
+      write_csr == false;
+    }
+  } write_csr_c;
+
+ constraint! q{ 
+    if (instr_name == riscv_instr_name_t.CSRRW ||
+	instr_name == riscv_instr_name_t.CSRRWI) {
+      write_csr == true;
+    }
+  } csr_csrrw;
+
+  constraint! q{
+    if (instr_name == riscv_instr_name_t.CSRRS ||
+	instr_name == riscv_instr_name_t.CSRRC) {
+      write_csr == true || rs1 == 0;
+    }
+  } csr_csrrsc;
+
+  constraint! q{
+    if (instr_name == riscv_instr_name_t.CSRRSI ||
+	instr_name == riscv_instr_name_t.CSRRCI) {
+      write_csr == true || imm == 0;
+    }
+  } csr_csrrsci;
+
+  constraint! q{
+    // Choose a CSR before rs1 and imm values. This ensures read-only accesses to read-only CSRs
+    // with similar probability to other CSR accesses.
+    solve csr before write_csr;
+    solve csr before rs1;
+    solve csr before imm;
+    // EUVM -- Uncommenting the next two results in non-converging constraints
+    // solve write_csr before rs1;
+    // solve write_csr before imm;
+  } order;
+
+
+  mixin uvm_object_utils;
+
+  this(string name = "") {
+    super(name);
+  }
+
+  static void create_csr_filter(riscv_instr_gen_config cfg) {
+    cfg.csr_cfg.create_csr_filter(cfg);
+  }
+
+  override void set_rand_mode() {
+    super.set_rand_mode();
+
+    has_rs2 = false;
+    if (instr_format == riscv_instr_format_t.I_FORMAT) {
+      has_rs1 = false;
+    }
+  }
+
+  // Convert the instruction to assembly code
+  override string convert2asm(string prefix = "") {
+    import std.string: toLower;
+    string asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN);
+
+    switch (instr_format) {
+    case riscv_instr_format_t.I_FORMAT: // instr rd,rs1,imm
+      asm_str = format("%0s%0s, 0x%0x, %0s", asm_str, rd, csr, get_imm());
+      break;
+    case riscv_instr_format_t.R_FORMAT: // instr rd,rs1,rs2
+      asm_str = format("%0s%0s, 0x%0x, %0s", asm_str, rd, csr, rs1);
+      break;
+    default:
+      uvm_fatal(get_full_name(), format("Unsupported format %0s [%0s]", instr_format,
+					instr_name));
+    }
+
+    if (comment != "")
+      asm_str ~= " #" ~ comment;
+    return asm_str.toLower();
+  }
+
+  override char[] convert2asm(char[] buf, string prefix = "") {
+    import std.string: toLower, toLowerInPlace;
+    import std.format: sformat;
+    
+    char[32] instr_buf;
+    char[MAX_INSTR_STR_LEN+8] instr_name_buf;
+
+    string asm_str;
+    char[] asm_buf;
+
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    char[] instr_name_str = sformat!FMT(instr_name_buf, get_instr_name(instr_buf));
+
+    switch (instr_format) {
+    case riscv_instr_format_t.I_FORMAT: // instr rd,rs1,imm
+      asm_buf = sformat!("%0s%0s, 0x%0x, %0s")(buf, instr_name_str, rd, csr, get_imm());
+      break;
+    case riscv_instr_format_t.R_FORMAT: // instr rd,rs1,rs2
+      asm_buf = sformat!("%0s%0s, 0x%0x, %0s")(buf, instr_name_str, rd, csr, rs1);
+      break;
+    default:
+      uvm_fatal(get_full_name(), format("Unsupported format %0s [%0s]", instr_format,
+					instr_name));
+    }
+
+    if (comment != "") {
+      buf[asm_buf.length..asm_buf.length+2] = " #";
+      buf[asm_buf.length+2..asm_buf.length+2+comment.length] = comment;
+      asm_buf = buf[0..asm_buf.length+2+comment.length];
+    }
+
+    toLowerInPlace(asm_buf);
+
+    assert(asm_buf.ptr is buf.ptr);
+    return asm_buf;
+  }
+
+  override ubvec!7 get_opcode() {
+    return UBVEC!(7, 0b1110011);
+  }
+
+  override ubvec!3 get_func3() {
+    switch (instr_name) {
+    case riscv_instr_name_t.CSRRW:  return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CSRRS:  return UBVEC!(3, 0b010);
+    case riscv_instr_name_t.CSRRC:  return UBVEC!(3, 0b011);
+    case riscv_instr_name_t.CSRRWI: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.CSRRSI: return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.CSRRCI: return UBVEC!(3, 0b111);
+    default:     return super.get_func3();
+    }
+  }
+
+  override string convert2bin(string prefix = "") {
+    string binary;
+
+    switch (instr_format) {
+    case riscv_instr_format_t.I_FORMAT: binary =
+	format("%8h", csr ~ cast(ubvec!5)(imm[0..5]) ~ get_func3() ~ rd ~ get_opcode());
+      break;
+    case riscv_instr_format_t.R_FORMAT: binary =
+	format("%8h", csr ~ rs1 ~ get_func3() ~ rd ~ get_opcode());
+      break;
+    default: uvm_fatal(get_full_name(),
+		       format("Unsupported format %0s", instr_format));
+      break;
+    }
+
+    return  prefix ~ binary;
+  }
+}
diff --git a/euvm/riscv/gen/isa/riscv_floating_point_instr.d b/euvm/riscv/gen/isa/riscv_floating_point_instr.d
index 783eaff9..6fef948d 100644
--- a/euvm/riscv/gen/isa/riscv_floating_point_instr.d
+++ b/euvm/riscv/gen/isa/riscv_floating_point_instr.d
@@ -20,13 +20,13 @@ module riscv.gen.isa.riscv_floating_point_instr;
 import riscv.gen.riscv_instr_pkg: riscv_instr_group_t,
   riscv_instr_name_t, MAX_INSTR_STR_LEN, riscv_fpr_t,
   riscv_instr_format_t, riscv_instr_category_t,
-  format_string, f_rounding_mode_t;
+  f_rounding_mode_t, riscv_reg_t;
 import riscv.gen.isa.riscv_instr: riscv_instr;
 import std.string: toUpper, toLower;
 import std.format: format;
 import std.algorithm: canFind;
 
-import esdl.rand: rand;
+import esdl.rand: rand, constraint;
 import esdl.data.bvec: ubvec;
 import uvm;
 
@@ -51,12 +51,30 @@ class riscv_floating_point_instr: riscv_instr
     super(name);
   }
 
+  constraint! q{
+    if (instr_format inside [riscv_instr_format_t.CL_FORMAT,
+			     riscv_instr_format_t.CS_FORMAT,
+			     riscv_instr_format_t.CI_FORMAT,
+			     riscv_instr_format_t.CSS_FORMAT]) {
+      if (has_rs1) {
+        rs1 inside [riscv_reg_t.S0:riscv_reg_t.A5];
+      }
+      if (has_fs2) {
+        fs2 inside [riscv_fpr_t.FS0:riscv_fpr_t.FS1];
+      }
+      if (has_fd) {
+        fd inside [riscv_fpr_t.FA0:riscv_fpr_t.FA5];
+      }
+    }
+  } rvfc_csr_c;
+ 
 
   // Convert the instruction to assembly code
   override string convert2asm(string prefix = "") {
     import std.conv: to;
     string asm_str;
-    asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN);
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    asm_str = format!FMT(get_instr_name());
     switch (instr_format) {
     case riscv_instr_format_t.I_FORMAT:
       if (category == riscv_instr_category_t.LOAD) {
@@ -113,6 +131,12 @@ class riscv_floating_point_instr: riscv_instr
     case riscv_instr_format_t.CS_FORMAT:
       asm_str = format("%0s%0s, %0s(%0s)", asm_str, fs2, get_imm(), rs1);
       break;
+    case riscv_instr_format_t.CSS_FORMAT:
+      asm_str = format("%0s%0s, %0s(sp)", asm_str, fs2, get_imm());
+      break;
+    case riscv_instr_format_t.CI_FORMAT:
+      asm_str = format("%0s%0s, %0s", asm_str, fd, get_imm());
+      break;
     default:
       uvm_fatal(get_full_name(), format("Unsupported floating point format: %0s", instr_format));
     }
@@ -135,7 +159,119 @@ class riscv_floating_point_instr: riscv_instr
     return asm_str.toLower();
   }
 
-  override void do_copy(uvm_object rhs) {
+  // Convert the instruction to assembly code
+  override char[] convert2asm(char[] buf, string prefix = "") {
+    import std.string: toLower, toLowerInPlace;
+    import std.format: sformat;
+    import std.conv: to;
+
+    char[32] instr_buf;
+    char[MAX_INSTR_STR_LEN+8] instr_name_buf;
+
+    // string asm_str;
+    char[] asm_buf;
+
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    char[] instr_name_str = sformat!FMT(instr_name_buf, get_instr_name(instr_buf));
+
+    
+    switch (instr_format) {
+    case riscv_instr_format_t.I_FORMAT:
+      if (category == riscv_instr_category_t.LOAD) {
+	asm_buf = sformat!("%0s%0s, %0s(%0s)")(buf, instr_name_str, fd, get_imm(), rs1);
+      }
+      else if (instr_name.inside (riscv_instr_name_t.FMV_X_W,
+				  riscv_instr_name_t.FMV_X_D,
+				  riscv_instr_name_t.FCVT_W_S,
+				  riscv_instr_name_t.FCVT_WU_S,
+				  riscv_instr_name_t.FCVT_L_S,
+				  riscv_instr_name_t.FCVT_LU_S,
+				  riscv_instr_name_t.FCVT_L_D,
+				  riscv_instr_name_t.FCVT_LU_D,
+				  riscv_instr_name_t.FCVT_W_D,
+				  riscv_instr_name_t.FCVT_WU_D)) {
+	asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, rd, fs1);
+      }
+      else if (instr_name.inside(riscv_instr_name_t.FMV_W_X,
+				 riscv_instr_name_t.FMV_D_X,
+				 riscv_instr_name_t.FCVT_S_W,
+				 riscv_instr_name_t.FCVT_S_WU,
+				 riscv_instr_name_t.FCVT_S_L,
+				 riscv_instr_name_t.FCVT_D_L,
+				 riscv_instr_name_t.FCVT_S_LU,
+				 riscv_instr_name_t.FCVT_D_W,
+				 riscv_instr_name_t.FCVT_D_LU,
+				 riscv_instr_name_t.FCVT_D_WU)) {
+	asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, fd, rs1);
+      }
+      else {
+	asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, fd, fs1);
+      }
+      break;
+    case riscv_instr_format_t.S_FORMAT:
+      asm_buf = sformat!("%0s%0s, %0s(%0s)")(buf, instr_name_str, fs2, get_imm(), rs1);
+      break;
+    case riscv_instr_format_t.R_FORMAT:
+      if (category == riscv_instr_category_t.COMPARE) {
+	asm_buf = sformat!("%0s%0s, %0s, %0s")(buf, instr_name_str, rd, fs1, fs2);
+      }
+      else if (instr_name.inside(riscv_instr_name_t.FCLASS_S, riscv_instr_name_t.FCLASS_D)) {
+	asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, rd, fs1);
+      }
+      else {
+	asm_buf = sformat!("%0s%0s, %0s, %0s")(buf, instr_name_str, fd, fs1, fs2);
+      }
+      break;
+    case riscv_instr_format_t.R4_FORMAT:
+      asm_buf = sformat!("%0s%0s, %0s, %0s, %0s")(buf, instr_name_str, fd, fs1, fs2, fs3);
+      break;
+    case riscv_instr_format_t.CL_FORMAT:
+      asm_buf = sformat!("%0s%0s, %0s(%0s)")(buf, instr_name_str, fd, get_imm(), rs1);
+      break;
+    case riscv_instr_format_t.CS_FORMAT:
+      asm_buf = sformat!("%0s%0s, %0s(%0s)")(buf, instr_name_str, fs2, get_imm(), rs1);
+      break;
+    default:
+      uvm_fatal(get_full_name(), format("Unsupported floating point format: %0s", instr_format));
+    }
+    if ((category == riscv_instr_category_t.ARITHMETIC) && use_rounding_mode_from_instr &&
+        !(instr_name.inside(riscv_instr_name_t.FMIN_S, riscv_instr_name_t.FMAX_S,
+			    riscv_instr_name_t.FMIN_D, riscv_instr_name_t.FMAX_D,
+			    riscv_instr_name_t.FMV_W_X, riscv_instr_name_t.FMV_X_W,
+			    riscv_instr_name_t.FMV_D_X, riscv_instr_name_t.FMV_X_D,
+			    riscv_instr_name_t.FCLASS_S, riscv_instr_name_t.FCLASS_D,
+			    riscv_instr_name_t.FCVT_D_S, riscv_instr_name_t.FCVT_D_W,
+			    riscv_instr_name_t.FCVT_D_WU, riscv_instr_name_t.FSGNJ_S,
+			    riscv_instr_name_t.FSGNJN_S, riscv_instr_name_t.FSGNJX_S,
+			    riscv_instr_name_t.FSGNJ_D, riscv_instr_name_t.FSGNJN_D,
+			    riscv_instr_name_t.FSGNJX_D))) {
+      char[] rm_suffix = sformat!(", %s")(buf[asm_buf.length..$], rm);
+      asm_buf = buf[0..asm_buf.length+rm_suffix.length];
+    }
+
+    if (comment != "") {
+      buf[asm_buf.length..asm_buf.length+2] = " #";
+      buf[asm_buf.length+2..asm_buf.length+2+comment.length] = comment;
+      asm_buf = buf[0..asm_buf.length+2+comment.length];
+    }
+
+    toLowerInPlace(asm_buf);
+
+    assert(asm_buf.ptr is buf.ptr);
+    return asm_buf;
+  }
+
+  override void set_imm_len() {
+    import esdl.data.bvec: UBVEC;
+    if (instr_format == riscv_instr_format_t.CL_FORMAT ||
+	instr_format == riscv_instr_format_t.CS_FORMAT)
+      imm_len = UBVEC!(5, 5);
+    if (instr_format == riscv_instr_format_t.CI_FORMAT ||
+	instr_format == riscv_instr_format_t.CSS_FORMAT)
+      imm_len = UBVEC!(5, 6);
+  }
+
+ override void do_copy(uvm_object rhs) {
     riscv_floating_point_instr rhs_;
     super.copy(rhs);
     rhs_ = cast(riscv_floating_point_instr) rhs;
@@ -226,6 +362,14 @@ class riscv_floating_point_instr: riscv_instr
       has_fs1 = false;
       has_fd = false;
       break;
+    case riscv_instr_format_t.CSS_FORMAT:
+      has_rs1 = false;
+      has_fd = false;
+      break;
+    case riscv_instr_format_t.CI_FORMAT:
+      has_rs1 = false;
+      has_fs2 = false;
+      break;
     default: uvm_info(get_full_name() , format("Unsupported format %0s", instr_format), UVM_LOW);
     }
   }
diff --git a/euvm/riscv/gen/isa/riscv_instr.d b/euvm/riscv/gen/isa/riscv_instr.d
index b22cf31d..2be32d16 100644
--- a/euvm/riscv/gen/isa/riscv_instr.d
+++ b/euvm/riscv/gen/isa/riscv_instr.d
@@ -18,16 +18,16 @@
 module riscv.gen.isa.riscv_instr;
 
 import riscv.gen.riscv_instr_pkg: riscv_instr_group_t, riscv_instr_format_t,
-  riscv_instr_category_t, riscv_instr_name_t, imm_t, riscv_reg_t, format_string,
+  riscv_instr_category_t, riscv_instr_name_t, imm_t, riscv_reg_t,
   MAX_INSTR_STR_LEN;
 import riscv.gen.target: XLEN;
 import riscv.gen.riscv_instr_gen_config: riscv_instr_gen_config;
 // import riscv.gen.riscv_instr_registry: riscv_instr_registry;
 
-import esdl.data.bvec: bvec, ubvec, toubvec;
+import esdl.data.bvec: bvec, ubvec, UBVEC;
 import esdl.rand: rand, constraint;
 
-import std.format: format;
+import std.format: format, sformat;
 import std.algorithm.searching: canFind;
 
 import uvm;
@@ -76,34 +76,23 @@ class riscv_instr: uvm_object
   bool                       has_imm = true;
 
 
-  constraint! q{
-    if (instr_name inside [riscv_instr_name_t.SLLIW,
-			   riscv_instr_name_t.SRLIW,
-			   riscv_instr_name_t.SRAIW]) {
-      imm[5..12] == 0;
-    }
-    if (instr_name inside [riscv_instr_name_t.SLLI,
-			   riscv_instr_name_t.SRLI,
-			   riscv_instr_name_t.SRAI]) {
-      if (XLEN == 32) {
-        imm[5..12] == 0;
-      }
-      else {
-        imm[6..12] == 0;
-      }
-    }
-  } imm_c;
-
-  constraint!  q{
-    if (category == riscv_instr_category_t.CSR) {
-      if (m_cfg.instr_registry.include_reg.length > 0) {
-        csr inside [m_cfg.instr_registry.include_reg];
-      }
-      if (m_cfg.instr_registry.exclude_reg.length > 0) {
-        csr !inside [m_cfg.instr_registry.exclude_reg];
-      }
-    }
-  } csr_c;
+  // constraint! q{
+  //   if (instr_name inside [riscv_instr_name_t.SLLIW,
+  // 			   riscv_instr_name_t.SRLIW,
+  // 			   riscv_instr_name_t.SRAIW]) {
+  //     imm[5..12] == 0;
+  //   }
+  //   if (instr_name inside [riscv_instr_name_t.SLLI,
+  // 			   riscv_instr_name_t.SRLI,
+  // 			   riscv_instr_name_t.SRAI]) {
+  //     if (XLEN == 32) {
+  //       imm[5..12] == 0;
+  //     }
+  //     else {
+  //       imm[6..12] == 0;
+  //     }
+  //   }
+  // } imm_c;
 
   this(string name = "") {
     super(name);
@@ -132,12 +121,6 @@ class riscv_instr: uvm_object
       break;
     default: break;
     }
-    if (category == riscv_instr_category_t.CSR) {
-      has_rs2 = false;
-      if (instr_format ==riscv_instr_format_t.I_FORMAT) {
-	has_rs1 = false;
-      }
-    }
   }
 
   void pre_randomize() {
@@ -153,16 +136,16 @@ class riscv_instr: uvm_object
   void set_imm_len() {
     if (instr_format == riscv_instr_format_t.U_FORMAT ||
 	instr_format == riscv_instr_format_t.J_FORMAT) {
-      imm_len = toubvec!5(20);
+      imm_len = UBVEC!(5, 20);
     }
     else if (instr_format == riscv_instr_format_t.I_FORMAT ||
 	     instr_format == riscv_instr_format_t.S_FORMAT ||
 	     instr_format == riscv_instr_format_t.B_FORMAT) {
       if (imm_type == imm_t.UIMM) {
-	imm_len = toubvec!5(5);
+	imm_len = UBVEC!(5, 5);
       }
       else {
-	imm_len = toubvec!5(11);
+	imm_len = UBVEC!(5, 12);
       }
     }
     imm_mask = imm_mask << imm_len;
@@ -190,7 +173,8 @@ class riscv_instr: uvm_object
   string convert2asm(string prefix = "") {
     import std.string: toLower;
     string asm_str;
-    asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN);
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    asm_str = format!FMT(get_instr_name());
     if (category != riscv_instr_category_t.SYSTEM) {
       switch (instr_format) {
       case riscv_instr_format_t.J_FORMAT, riscv_instr_format_t.U_FORMAT: // instr rd,imm
@@ -207,8 +191,6 @@ class riscv_instr: uvm_object
 	  asm_str = "fence.i";
 	else if (category == riscv_instr_category_t.LOAD) // Use psuedo instruction format
 	  asm_str = format("%0s%0s, %0s(%0s)", asm_str, rd, get_imm(), rs1);
-	else if (category == riscv_instr_category_t.CSR)
-	  asm_str = format("%0s%0s, 0x%0x, %0s", asm_str,rd, csr, get_imm());
 	else
 	  asm_str = format("%0s%0s, %0s, %0s", asm_str, rd, rs1, get_imm());
 	break;
@@ -219,10 +201,7 @@ class riscv_instr: uvm_object
 	  asm_str = format("%0s%0s, %0s, %0s", asm_str, rs1, rs2, get_imm());
 	break;
       case riscv_instr_format_t.R_FORMAT: // instr rd,rs1,rs2
-	if (category ==  riscv_instr_category_t.CSR) {
-	  asm_str = format("%0s%0s, 0x%0x, %0s", asm_str, rd, csr, rs1);
-	}
-	else if (instr_name == riscv_instr_name_t.SFENCE_VMA) {
+	if (instr_name == riscv_instr_name_t.SFENCE_VMA) {
 	  asm_str = "sfence.vma x0, x0"; // TODO: Support all possible sfence
 	}
 	else {
@@ -246,29 +225,107 @@ class riscv_instr: uvm_object
     return toLower(asm_str);
   }
 
+  // Convert the instruction to assembly code
+  char[] convert2asm(char[] buf, string prefix = "") {
+    import std.string: toLower, toLowerInPlace;
+    import std.format: sformat;
+
+    char[32] instr_buf;
+    char[MAX_INSTR_STR_LEN+8] instr_name_buf;
+
+    string asm_str;
+    char[] asm_buf;
+
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    char[] instr_name_str = sformat!FMT(instr_name_buf, get_instr_name(instr_buf));
+
+    if (category != riscv_instr_category_t.SYSTEM) {
+      switch (instr_format) {
+      case riscv_instr_format_t.J_FORMAT, riscv_instr_format_t.U_FORMAT: // instr rd,imm
+	asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, rd, get_imm());
+	break;
+      case riscv_instr_format_t.I_FORMAT: // instr rd,rs1,imm
+	if (instr_name == riscv_instr_name_t.NOP)
+	  asm_str = "nop";
+	else if (instr_name == riscv_instr_name_t.WFI)
+	  asm_str = "wfi";
+	else if (instr_name == riscv_instr_name_t.FENCE)
+	  asm_str = "fence"; // format("fence"); // TODO: Support all fence combinations
+	else if (instr_name == riscv_instr_name_t.FENCE_I)
+	  asm_str = "fence.i";
+	else if (category == riscv_instr_category_t.LOAD) // Use psuedo instruction format
+	  asm_buf = sformat!("%0s%0s, %0s(%0s)")(buf,  instr_name_str, rd, get_imm(), rs1);
+	else
+	  asm_buf = sformat!("%0s%0s, %0s, %0s")(buf, instr_name_str, rd, rs1, get_imm());
+	break; 
+      case riscv_instr_format_t.S_FORMAT, riscv_instr_format_t.B_FORMAT: // instr rs1,rs2,imm
+	if (category == riscv_instr_category_t.STORE) // Use psuedo instruction format
+	  asm_buf = sformat!("%0s%0s, %0s(%0s)")(buf, instr_name_str, rs2, get_imm(), rs1);
+	else
+	  asm_buf = sformat!("%0s%0s, %0s, %0s")(buf, instr_name_str, rs1, rs2, get_imm());
+	break;  
+      case riscv_instr_format_t.R_FORMAT: // instr rd,rs1,rs2
+	if (instr_name == riscv_instr_name_t.SFENCE_VMA) {
+	  asm_str = "sfence.vma x0, x0"; // TODO: Support all possible sfence
+	}
+	else {
+	  asm_buf = sformat!("%0s%0s, %0s, %0s")(buf, instr_name_str, rd, rs1, rs2);
+	}
+	break; 
+      default: uvm_fatal(get_full_name(), format("Unsupported format %0s [%0s]",
+						   instr_format, instr_name));
+	break;
+      }
+    }
+    else {
+      // For EBREAK,C.EBREAK, making sure pc+4 is a valid instruction boundary
+      // This is needed to resume execution from epc+4 after ebreak handling
+      if (instr_name == riscv_instr_name_t.EBREAK) {
+	asm_str = ".4byte 0x00100073 # ebreak";
+      }
+    }
+
+    if (asm_str.length > 0) {
+      assert (asm_buf.length == 0);
+      buf[0..asm_str.length] = asm_str;
+      asm_buf = buf[0..asm_str.length];
+    }
+
+    if (comment != "") {
+      buf[asm_buf.length..asm_buf.length+2] = " #";
+      buf[asm_buf.length+2..asm_buf.length+2+comment.length] = comment;
+      asm_buf = buf[0..asm_buf.length+2+comment.length];
+    }
+
+    toLowerInPlace(asm_buf);
+
+    assert(asm_buf.ptr is buf.ptr);
+    return asm_buf;
+  }
+  
   ubvec!7 get_opcode() {
     switch (instr_name) {
-    case riscv_instr_name_t.LUI:       return toubvec!7(0b0110111);
-    case riscv_instr_name_t.AUIPC:     return toubvec!7(0b0010111);
-    case riscv_instr_name_t.JAL:       return toubvec!7(0b1101111);
-    case riscv_instr_name_t.JALR:      return toubvec!7(0b1100111);
+    case riscv_instr_name_t.LUI:       return UBVEC!(7, 0b0110111);
+    case riscv_instr_name_t.AUIPC:     return UBVEC!(7, 0b0010111);
+    case riscv_instr_name_t.JAL:       return UBVEC!(7, 0b1101111);
+    case riscv_instr_name_t.JALR:      return UBVEC!(7, 0b1100111);
     case riscv_instr_name_t.BEQ,
       riscv_instr_name_t.BNE,
       riscv_instr_name_t.BLT,
       riscv_instr_name_t.BGE,
       riscv_instr_name_t.BLTU,
-      riscv_instr_name_t.BGEU:         return toubvec!7(0b1100011);
+      riscv_instr_name_t.BGEU:         return UBVEC!(7, 0b1100011);
     case riscv_instr_name_t.LB,
       riscv_instr_name_t.LH,
       riscv_instr_name_t.LW,
       riscv_instr_name_t.LBU,
       riscv_instr_name_t.LHU,
       riscv_instr_name_t.LWU,
-      riscv_instr_name_t.LD:           return toubvec!7(0b0000011);
+      riscv_instr_name_t.LD:           return UBVEC!(7, 0b0000011);
     case riscv_instr_name_t.SB,
       riscv_instr_name_t.SH,
       riscv_instr_name_t.SW,
-      riscv_instr_name_t.SD:           return toubvec!7(0b0100011);
+      riscv_instr_name_t.SD:           return UBVEC!(7, 0b0100011);
     case riscv_instr_name_t.ADDI,
       riscv_instr_name_t.SLTI,
       riscv_instr_name_t.SLTIU,
@@ -278,7 +335,7 @@ class riscv_instr: uvm_object
       riscv_instr_name_t.SLLI,
       riscv_instr_name_t.SRLI,
       riscv_instr_name_t.SRAI,
-      riscv_instr_name_t.NOP:          return toubvec!7(0b0010011);
+      riscv_instr_name_t.NOP:          return UBVEC!(7, 0b0010011);
     case riscv_instr_name_t.ADD,
       riscv_instr_name_t.SUB,
       riscv_instr_name_t.SLL,
@@ -296,26 +353,22 @@ class riscv_instr: uvm_object
       riscv_instr_name_t.DIV,
       riscv_instr_name_t.DIVU,
       riscv_instr_name_t.REM,
-      riscv_instr_name_t.REMU:         return toubvec!7(0b0110011);
+      riscv_instr_name_t.REMU:         return UBVEC!(7, 0b0110011);
     case riscv_instr_name_t.ADDIW,
       riscv_instr_name_t.SLLIW,
       riscv_instr_name_t.SRLIW,
-      riscv_instr_name_t.SRAIW:        return toubvec!7(0b0011011);
+      riscv_instr_name_t.SRAIW:        return UBVEC!(7, 0b0011011);
     // case riscv_instr_name_t.MULH,
     //   riscv_instr_name_t.MULHSU,
     //   riscv_instr_name_t.MULHU,
     //   riscv_instr_name_t.DIV,
     //   riscv_instr_name_t.DIVU,
     //   riscv_instr_name_t.REM,
-    //   riscv_instr_name_t.REMU: { return toubvec!0b0110011;
+    //   riscv_instr_name_t.REMU: return UBVEC!(7, 0b0110011);
     case riscv_instr_name_t.FENCE,
-      riscv_instr_name_t.FENCE_I:      return toubvec!7(0b0001111);
-    case riscv_instr_name_t.CSRRW,
-      riscv_instr_name_t.CSRRS,
-      riscv_instr_name_t.CSRRC,
-      riscv_instr_name_t.CSRRWI,
-      riscv_instr_name_t.CSRRSI,
-      riscv_instr_name_t.CSRRCI:       return toubvec!7(0b1110011);
+      riscv_instr_name_t.FENCE_I,
+      riscv_instr_name_t.PAUSE,
+      riscv_instr_name_t.FENCE_TSO:      return UBVEC!(7, 0b0001111);
     case riscv_instr_name_t.ADDW,
       riscv_instr_name_t.SUBW,
       riscv_instr_name_t.SLLW,
@@ -325,15 +378,17 @@ class riscv_instr: uvm_object
       riscv_instr_name_t.DIVW,
       riscv_instr_name_t.DIVUW,
       riscv_instr_name_t.REMW,
-      riscv_instr_name_t.REMUW:        return toubvec!7(0b0111011);
+      riscv_instr_name_t.REMUW:        return UBVEC!(7, 0b0111011);
     case riscv_instr_name_t.ECALL,
+      riscv_instr_name_t.SCALL,
       riscv_instr_name_t.EBREAK,
-      riscv_instr_name_t.URET,
+      riscv_instr_name_t.SBREAK,
+      // riscv_instr_name_t.URET,
       riscv_instr_name_t.SRET,
       riscv_instr_name_t.MRET,
       riscv_instr_name_t.DRET,
       riscv_instr_name_t.WFI,
-      riscv_instr_name_t.SFENCE_VMA:   return toubvec!7(0b1110011);
+      riscv_instr_name_t.SFENCE_VMA:   return UBVEC!(7, 0b1110011);
     default: uvm_fatal(get_full_name(), format("Unsupported instruction %0s", instr_name));
       assert (false);
     }
@@ -341,84 +396,82 @@ class riscv_instr: uvm_object
 
   ubvec!3 get_func3() {
     switch (instr_name) {
-    case riscv_instr_name_t.JALR:       return toubvec!3(0b000);
-    case riscv_instr_name_t.BEQ:        return toubvec!3(0b000);
-    case riscv_instr_name_t.BNE:        return toubvec!3(0b001);
-    case riscv_instr_name_t.BLT:        return toubvec!3(0b100);
-    case riscv_instr_name_t.BGE:        return toubvec!3(0b101);
-    case riscv_instr_name_t.BLTU:       return toubvec!3(0b110);
-    case riscv_instr_name_t.BGEU:       return toubvec!3(0b111);
-    case riscv_instr_name_t.LB:         return toubvec!3(0b000);
-    case riscv_instr_name_t.LH:         return toubvec!3(0b001);
-    case riscv_instr_name_t.LW:         return toubvec!3(0b010);
-    case riscv_instr_name_t.LBU:        return toubvec!3(0b100);
-    case riscv_instr_name_t.LHU:        return toubvec!3(0b101);
-    case riscv_instr_name_t.SB:         return toubvec!3(0b000);
-    case riscv_instr_name_t.SH:         return toubvec!3(0b001);
-    case riscv_instr_name_t.SW:         return toubvec!3(0b010);
-    case riscv_instr_name_t.ADDI:       return toubvec!3(0b000);
-    case riscv_instr_name_t.NOP:        return toubvec!3(0b000);
-    case riscv_instr_name_t.SLTI:       return toubvec!3(0b010);
-    case riscv_instr_name_t.SLTIU:      return toubvec!3(0b011);
-    case riscv_instr_name_t.XORI:       return toubvec!3(0b100);
-    case riscv_instr_name_t.ORI:        return toubvec!3(0b110);
-    case riscv_instr_name_t.ANDI:       return toubvec!3(0b111);
-    case riscv_instr_name_t.SLLI:       return toubvec!3(0b001);
-    case riscv_instr_name_t.SRLI:       return toubvec!3(0b101);
-    case riscv_instr_name_t.SRAI:       return toubvec!3(0b101);
-    case riscv_instr_name_t.ADD:        return toubvec!3(0b000);
-    case riscv_instr_name_t.SUB:        return toubvec!3(0b000);
-    case riscv_instr_name_t.SLL:        return toubvec!3(0b001);
-    case riscv_instr_name_t.SLT:        return toubvec!3(0b010);
-    case riscv_instr_name_t.SLTU:       return toubvec!3(0b011);
-    case riscv_instr_name_t.XOR:        return toubvec!3(0b100);
-    case riscv_instr_name_t.SRL:        return toubvec!3(0b101);
-    case riscv_instr_name_t.SRA:        return toubvec!3(0b101);
-    case riscv_instr_name_t.OR:         return toubvec!3(0b110);
-    case riscv_instr_name_t.AND:        return toubvec!3(0b111);
-    case riscv_instr_name_t.FENCE:      return toubvec!3(0b000);
-    case riscv_instr_name_t.FENCE_I:    return toubvec!3(0b001);
-      // case riscv_instr_name_t.ECALL:      return toubvec!3(0b000);
-      // case riscv_instr_name_t.EBREAK:     return toubvec!3(0b000);
-    case riscv_instr_name_t.CSRRW:      return toubvec!3(0b001);
-    case riscv_instr_name_t.CSRRS:      return toubvec!3(0b010);
-    case riscv_instr_name_t.CSRRC:      return toubvec!3(0b011);
-    case riscv_instr_name_t.CSRRWI:     return toubvec!3(0b101);
-    case riscv_instr_name_t.CSRRSI:     return toubvec!3(0b110);
-    case riscv_instr_name_t.CSRRCI:     return toubvec!3(0b111);
-    case riscv_instr_name_t.LWU:        return toubvec!3(0b110);
-    case riscv_instr_name_t.LD:         return toubvec!3(0b011);
-    case riscv_instr_name_t.SD:         return toubvec!3(0b011);
-    case riscv_instr_name_t.ADDIW:      return toubvec!3(0b000);
-    case riscv_instr_name_t.SLLIW:      return toubvec!3(0b001);
-    case riscv_instr_name_t.SRLIW:      return toubvec!3(0b101);
-    case riscv_instr_name_t.SRAIW:      return toubvec!3(0b101);
-    case riscv_instr_name_t.ADDW:       return toubvec!3(0b000);
-    case riscv_instr_name_t.SUBW:       return toubvec!3(0b000);
-    case riscv_instr_name_t.SLLW:       return toubvec!3(0b001);
-    case riscv_instr_name_t.SRLW:       return toubvec!3(0b101);
-    case riscv_instr_name_t.SRAW:       return toubvec!3(0b101);
-    case riscv_instr_name_t.MUL:        return toubvec!3(0b000);
-    case riscv_instr_name_t.MULH:       return toubvec!3(0b001);
-    case riscv_instr_name_t.MULHSU:     return toubvec!3(0b010);
-    case riscv_instr_name_t.MULHU:      return toubvec!3(0b011);
-    case riscv_instr_name_t.DIV:        return toubvec!3(0b100);
-    case riscv_instr_name_t.DIVU:       return toubvec!3(0b101);
-    case riscv_instr_name_t.REM:        return toubvec!3(0b110);
-    case riscv_instr_name_t.REMU:       return toubvec!3(0b111);
-    case riscv_instr_name_t.MULW:       return toubvec!3(0b000);
-    case riscv_instr_name_t.DIVW:       return toubvec!3(0b100);
-    case riscv_instr_name_t.DIVUW:      return toubvec!3(0b101);
-    case riscv_instr_name_t.REMW:       return toubvec!3(0b110);
-    case riscv_instr_name_t.REMUW:      return toubvec!3(0b111);
+    case riscv_instr_name_t.JALR:       return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.BEQ:        return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.BNE:        return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.BLT:        return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.BGE:        return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.BLTU:       return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.BGEU:       return UBVEC!(3, 0b111);
+    case riscv_instr_name_t.LB:         return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.LH:         return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.LW:         return UBVEC!(3, 0b010);
+    case riscv_instr_name_t.LBU:        return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.LHU:        return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.SB:         return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.SH:         return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.SW:         return UBVEC!(3, 0b010);
+    case riscv_instr_name_t.ADDI:       return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.NOP:        return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.SLTI:       return UBVEC!(3, 0b010);
+    case riscv_instr_name_t.SLTIU:      return UBVEC!(3, 0b011);
+    case riscv_instr_name_t.XORI:       return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.ORI:        return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.ANDI:       return UBVEC!(3, 0b111);
+    case riscv_instr_name_t.SLLI:       return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.SRLI:       return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.SRAI:       return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.ADD:        return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.SUB:        return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.SLL:        return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.SLT:        return UBVEC!(3, 0b010);
+    case riscv_instr_name_t.SLTU:       return UBVEC!(3, 0b011);
+    case riscv_instr_name_t.XOR:        return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.SRL:        return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.SRA:        return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.OR:         return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.AND:        return UBVEC!(3, 0b111);
+    case riscv_instr_name_t.FENCE:      return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.FENCE_I:    return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.FENCE_TSO:  return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.PAUSE:  return UBVEC!(3, 0b001);
+      // case riscv_instr_name_t.ECALL:      return UBVEC!(3, 0b000);
+      // case riscv_instr_name_t.EBREAK:     return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.LWU:        return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.LD:         return UBVEC!(3, 0b011);
+    case riscv_instr_name_t.SD:         return UBVEC!(3, 0b011);
+    case riscv_instr_name_t.ADDIW:      return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.SLLIW:      return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.SRLIW:      return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.SRAIW:      return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.ADDW:       return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.SUBW:       return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.SLLW:       return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.SRLW:       return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.SRAW:       return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.MUL:        return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.MULH:       return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.MULHSU:     return UBVEC!(3, 0b010);
+    case riscv_instr_name_t.MULHU:      return UBVEC!(3, 0b011);
+    case riscv_instr_name_t.DIV:        return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.DIVU:       return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.REM:        return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.REMU:       return UBVEC!(3, 0b111);
+    case riscv_instr_name_t.MULW:       return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.DIVW:       return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.DIVUW:      return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.REMW:       return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.REMUW:      return UBVEC!(3, 0b111);
     case riscv_instr_name_t.ECALL,
+      riscv_instr_name_t.SCALL,
       riscv_instr_name_t.EBREAK,
-      riscv_instr_name_t.URET,
+      riscv_instr_name_t.SBREAK,
+      // riscv_instr_name_t.URET,
       riscv_instr_name_t.SRET,
       riscv_instr_name_t.MRET,
       riscv_instr_name_t.DRET,
       riscv_instr_name_t.WFI,
-      riscv_instr_name_t.SFENCE_VMA: return toubvec!3(0b000);
+      riscv_instr_name_t.SFENCE_VMA: return UBVEC!(3, 0b000);
     default: uvm_fatal(get_full_name(), format("Unsupported instruction %0s", instr_name));
       assert (false);
     }
@@ -426,55 +479,61 @@ class riscv_instr: uvm_object
 
   ubvec!7 get_func7() {
     switch (instr_name) {
-    case riscv_instr_name_t.SLLI:       return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SRLI:       return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SRAI:       return toubvec!7(0b0100000);
-    case riscv_instr_name_t.ADD:        return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SUB:        return toubvec!7(0b0100000);
-    case riscv_instr_name_t.SLL:        return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SLT:        return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SLTU:       return toubvec!7(0b0000000);
-    case riscv_instr_name_t.XOR:        return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SRL:        return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SRA:        return toubvec!7(0b0100000);
-    case riscv_instr_name_t.OR:         return toubvec!7(0b0000000);
-    case riscv_instr_name_t.AND:        return toubvec!7(0b0000000);
-    case riscv_instr_name_t.FENCE:      return toubvec!7(0b0000000);
-    case riscv_instr_name_t.FENCE_I:    return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SLLIW:      return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SRLIW:      return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SRAIW:      return toubvec!7(0b0100000);
-    case riscv_instr_name_t.ADDW:       return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SUBW:       return toubvec!7(0b0100000);
-    case riscv_instr_name_t.SLLW:       return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SRLW:       return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SRAW:       return toubvec!7(0b0100000);
-    case riscv_instr_name_t.MUL:        return toubvec!7(0b0000001);
-    case riscv_instr_name_t.MULH:       return toubvec!7(0b0000001);
-    case riscv_instr_name_t.MULHSU:     return toubvec!7(0b0000001);
-    case riscv_instr_name_t.MULHU:      return toubvec!7(0b0000001);
-    case riscv_instr_name_t.DIV:        return toubvec!7(0b0000001);
-    case riscv_instr_name_t.DIVU:       return toubvec!7(0b0000001);
-    case riscv_instr_name_t.REM:        return toubvec!7(0b0000001);
-    case riscv_instr_name_t.REMU:       return toubvec!7(0b0000001);
-    case riscv_instr_name_t.MULW:       return toubvec!7(0b0000001);
-    case riscv_instr_name_t.DIVW:       return toubvec!7(0b0000001);
-    case riscv_instr_name_t.DIVUW:      return toubvec!7(0b0000001);
-    case riscv_instr_name_t.REMW:       return toubvec!7(0b0000001);
-    case riscv_instr_name_t.REMUW:      return toubvec!7(0b0000001);
-    case riscv_instr_name_t.ECALL:      return toubvec!7(0b0000000);
-    case riscv_instr_name_t.EBREAK:     return toubvec!7(0b0000000);
-    case riscv_instr_name_t.URET:       return toubvec!7(0b0000000);
-    case riscv_instr_name_t.SRET:       return toubvec!7(0b0001000);
-    case riscv_instr_name_t.MRET:       return toubvec!7(0b0011000);
-    case riscv_instr_name_t.DRET:       return toubvec!7(0b0111101);
-    case riscv_instr_name_t.WFI:        return toubvec!7(0b0001000);
-    case riscv_instr_name_t.SFENCE_VMA: return toubvec!7(0b0001001);
+    case riscv_instr_name_t.SLLI:       return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SRLI:       return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SRAI:       return UBVEC!(7, 0b0100000);
+    case riscv_instr_name_t.ADD:        return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SUB:        return UBVEC!(7, 0b0100000);
+    case riscv_instr_name_t.SLL:        return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SLT:        return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SLTU:       return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.XOR:        return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SRL:        return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SRA:        return UBVEC!(7, 0b0100000);
+    case riscv_instr_name_t.OR:         return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.AND:        return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.FENCE:      return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.FENCE_I:    return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.FENCE_TSO:  return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.PAUSE:  return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SLLIW:      return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SRLIW:      return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SRAIW:      return UBVEC!(7, 0b0100000);
+    case riscv_instr_name_t.ADDW:       return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SUBW:       return UBVEC!(7, 0b0100000);
+    case riscv_instr_name_t.SLLW:       return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SRLW:       return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SRAW:       return UBVEC!(7, 0b0100000);
+    case riscv_instr_name_t.MUL:        return UBVEC!(7, 0b0000001);
+    case riscv_instr_name_t.MULH:       return UBVEC!(7, 0b0000001);
+    case riscv_instr_name_t.MULHSU:     return UBVEC!(7, 0b0000001);
+    case riscv_instr_name_t.MULHU:      return UBVEC!(7, 0b0000001);
+    case riscv_instr_name_t.DIV:        return UBVEC!(7, 0b0000001);
+    case riscv_instr_name_t.DIVU:       return UBVEC!(7, 0b0000001);
+    case riscv_instr_name_t.REM:        return UBVEC!(7, 0b0000001);
+    case riscv_instr_name_t.REMU:       return UBVEC!(7, 0b0000001);
+    case riscv_instr_name_t.MULW:       return UBVEC!(7, 0b0000001);
+    case riscv_instr_name_t.DIVW:       return UBVEC!(7, 0b0000001);
+    case riscv_instr_name_t.DIVUW:      return UBVEC!(7, 0b0000001);
+    case riscv_instr_name_t.REMW:       return UBVEC!(7, 0b0000001);
+    case riscv_instr_name_t.REMUW:      return UBVEC!(7, 0b0000001);
+    case riscv_instr_name_t.ECALL:      return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.EBREAK:     return UBVEC!(7, 0b0000000);
+      // case riscv_instr_name_t.URET:       return UBVEC!(7, 0b0000000);
+    case riscv_instr_name_t.SRET:       return UBVEC!(7, 0b0001000);
+    case riscv_instr_name_t.MRET:       return UBVEC!(7, 0b0011000);
+    case riscv_instr_name_t.DRET:       return UBVEC!(7, 0b0111101);
+    case riscv_instr_name_t.WFI:        return UBVEC!(7, 0b0001000);
+    case riscv_instr_name_t.SFENCE_VMA: return UBVEC!(7, 0b0001001);
     default: uvm_fatal(get_full_name(), format("Unsupported instruction %0s", instr_name));
       assert (false);
     }
   }
 
+  ubvec!32 get_bin() {
+    return UBVEC!(32, 0);
+  }
+  
   // Convert the instruction to assembly code
   string convert2bin(string prefix = "") {
     import std.conv: to;
@@ -485,71 +544,64 @@ class riscv_instr: uvm_object
 	~ cast(ubvec!10) imm[1..11]
 	~ cast(ubvec!1) imm[11]
 	~ cast(ubvec!8) imm[12..20]
-	~ toubvec!5(rd)
+	~ rd
 	~ get_opcode();
       break;
     case riscv_instr_format_t.U_FORMAT:
       vec = cast(ubvec!20) imm[12..32]
-	~ toubvec!5(rd)
+	~ rd
 	~ get_opcode();
       break;
     case riscv_instr_format_t.I_FORMAT:
       if (canFind( [riscv_instr_name_t.FENCE, riscv_instr_name_t.FENCE_I], instr_name)) {
-	vec = toubvec!17(0b00000000000000000)
+	vec = UBVEC!(17, 0b00000000000000000)
 	  ~ get_func3()
-	  ~ toubvec!5(0b00000)
+	  ~ UBVEC!(5, 0b00000)
 	  ~ get_opcode();
       }  // 17 bit zero and 5 bit zero
-      else if (category == riscv_instr_category_t.CSR) {
-	vec = csr // cast(ubvec!11) csr[0..11] SV BUG?
-	  ~ cast(ubvec!5) imm[0..5]
-	  ~ get_func3()
-	  ~ toubvec!5(rd)
-	  ~ get_opcode();
-      }
       else if (instr_name == riscv_instr_name_t.ECALL) {
 	vec = get_func7()
-	  ~ toubvec!18(0b000000000000000000)
+	  ~ UBVEC!(18, 0b000000000000000000)
 	  ~ get_opcode();
       } //  18 bit zero
-      else if (canFind([riscv_instr_name_t.URET,
+      else if (canFind([// riscv_instr_name_t.URET,
 			riscv_instr_name_t.SRET,
 			riscv_instr_name_t.MRET], instr_name )) {
 	vec = get_func7()
-	  ~ toubvec!5(0b00010)
-	  ~ toubvec!13(0b0000000000000)
+	  ~ UBVEC!(5, 0b00010)
+	  ~ UBVEC!(13, 0b0000000000000)
 	  ~ get_opcode();
       } // 13 bit zero
       else if (instr_name  ==  riscv_instr_name_t.DRET) {
 	vec = get_func7()
-	  ~ toubvec!5(0b10010)
-	  ~ toubvec!13(0b0000000000000)
+	  ~ UBVEC!(5, 0b10010)
+	  ~ UBVEC!(13, 0b0000000000000)
 	  ~ get_opcode();
       }  // 13 bit zero
       else if (instr_name ==  riscv_instr_name_t.EBREAK) {
 	vec = get_func7()
-	  ~ toubvec!5(0b00001)
-	  ~ toubvec!13(0b0000000000000)
+	  ~ UBVEC!(5, 0b00001)
+	  ~ UBVEC!(13, 0b0000000000000)
 	  ~ get_opcode();
       }  // 13 bit zero
       else if (instr_name == riscv_instr_name_t.WFI) {
 	vec = get_func7()
-	  ~ toubvec!5(0b00101)
-	  ~ toubvec!13(0b0000000000000)
+	  ~ UBVEC!(5, 0b00101)
+	  ~ UBVEC!(13, 0b0000000000000)
 	  ~ get_opcode();
       }
       else {
 	vec = cast(ubvec!12) imm[0..12]
-	  ~ toubvec!5(rs1)
+	  ~ rs1
 	  ~ get_func3()
-	  ~ toubvec!5(rd)
+	  ~ rd
 	  ~ get_opcode();
       }
       break;
     case riscv_instr_format_t.S_FORMAT:
       vec = cast(ubvec!7) imm[5..12]
-	~ toubvec!5(rs2)
-	~ toubvec!5(rs1)
+	~ rs2
+	~ rs1
 	~ get_func3()
 	~ cast(ubvec!5) imm[0..5]
 	~ get_opcode();
@@ -557,32 +609,25 @@ class riscv_instr: uvm_object
     case riscv_instr_format_t.B_FORMAT:
       vec = cast(ubvec!1) imm[12]
 	~ cast(ubvec!6) imm[5..11]
-	~ toubvec!5(rs2)
-	~ toubvec!5(rs1)
+	~ rs2
+	~ rs1
 	~ get_func3()
 	~ cast(ubvec!4) imm[1..5]
 	~ cast(ubvec!1) imm[11]
 	~ get_opcode();
       break;
     case riscv_instr_format_t.R_FORMAT:
-      if (category == riscv_instr_category_t.CSR) {
-	vec = csr // cast(ubvec!11) csr[0..11] -- SV BUG?
-	  ~ toubvec!5(rs1)
-	  ~ get_func3()
-	  ~ toubvec!5(rd)
-	  ~ get_opcode();
-      }
-      else if (instr_name == riscv_instr_name_t.SFENCE_VMA) {
+      if (instr_name == riscv_instr_name_t.SFENCE_VMA) {
 	vec = get_func7()
-	  ~ toubvec!18(0b000000000000000000)
+	  ~ UBVEC!(18, 0b000000000000000000)
 	  ~ get_opcode();
       } // 18 bits zero
       else {
 	vec = get_func7()
-	  ~ toubvec!5(rs2)
-	  ~ toubvec!5(rs1)
+	  ~ rs2
+	  ~ rs1
 	  ~ get_func3()
-	  ~ toubvec!5(rd)
+	  ~ rd
 	  ~ get_opcode();
       }
       break;
@@ -599,10 +644,17 @@ class riscv_instr: uvm_object
     return str_instr_name.replace( '_', '.');
   }
 
+  char[] get_instr_name(char[] buf) {
+    import std.format: sformat;
+
+    char[] str_instr_name = sformat!("%s")(buf, instr_name);
+    foreach(ref c; str_instr_name) if (c == '_') c = '.';
+    return str_instr_name;
+  }
+
   // // Get RVC register name for CIW, CL, CS, CB format
   ubvec!3  get_c_gpr(riscv_reg_t gpr) {
-    ubvec!8 c_gpr = toubvec!8(gpr);
-    return cast(ubvec!3) c_gpr[0..3];
+    return cast(ubvec!3) gpr[0..3];
   }
 
   // // Default return imm value directly, can be overriden to use labels and symbols
@@ -643,8 +695,15 @@ class riscv_instr: uvm_object
     }
   }
 
+  char[32] _imm_str_buf;
+
+  char[] imm_str_buf() {
+    return _imm_str_buf[];
+  }
+
   void update_imm_str() {
-    imm_str = format("%0d", cast(bvec!32) imm);
+    imm_str = cast(string)
+      sformat!("%0d")(_imm_str_buf, cast(int) imm);
   }
 
   //`include "isa/riscv_instr_cov.svh"
diff --git a/euvm/riscv/gen/isa/riscv_instr_register.d b/euvm/riscv/gen/isa/riscv_instr_register.d
index 0587ca90..7dd89b22 100644
--- a/euvm/riscv/gen/isa/riscv_instr_register.d
+++ b/euvm/riscv/gen/isa/riscv_instr_register.d
@@ -29,7 +29,7 @@ void register(alias MOD, INSTRS...)(riscv_instr_registry registry) {
     alias INSTR=__traits(getMember, MOD, INSTRS[0]);
     static if (is (INSTR == class) && is (INSTR: riscv_instr)) {
       // pragma(msg, "register ", fullyQualifiedName!INSTR);
-      registry.register(INSTR.RISCV_INSTR_NAME_T, fullyQualifiedName!INSTR);
+      registry.register(INSTR.RISCV_INSTR_NAME, fullyQualifiedName!INSTR);
     }
     register!(MOD, INSTRS[1..$])(registry);
     return;
@@ -65,6 +65,9 @@ void register_isa(riscv_instr_registry registry) {
   import riscv.gen.isa.rv32zbb_instr;
   import riscv.gen.isa.rv32zbc_instr;
   import riscv.gen.isa.rv32zbs_instr;
+  import riscv.gen.isa.rvzpn_instr;
+  import riscv.gen.isa.rv32zpn_instr;
+  import riscv.gen.isa.rv64zpn_instr;
 
   register_module!(riscv.gen.isa.rv128c_instr)(registry);
   register_module!(riscv.gen.isa.rv32a_instr)(registry);
@@ -84,4 +87,7 @@ void register_isa(riscv_instr_registry registry) {
   register_module!(riscv.gen.isa.rv64f_instr)(registry);
   register_module!(riscv.gen.isa.rv64i_instr)(registry);
   register_module!(riscv.gen.isa.rv64m_instr)(registry);
+  register_module!(riscv.gen.isa.rvzpn_instr)(registry);
+  register_module!(riscv.gen.isa.rv32zpn_instr)(registry);
+  register_module!(riscv.gen.isa.rv64zpn_instr)(registry);
 }
diff --git a/euvm/riscv/gen/isa/riscv_vector_instr.d b/euvm/riscv/gen/isa/riscv_vector_instr.d
index c7c34ec3..9b1e7d5f 100644
--- a/euvm/riscv/gen/isa/riscv_vector_instr.d
+++ b/euvm/riscv/gen/isa/riscv_vector_instr.d
@@ -21,7 +21,7 @@
 module riscv.gen.isa.riscv_vector_instr;
 
 import riscv.gen.riscv_instr_pkg: riscv_vreg_t, va_variant_t,
-  riscv_instr_name_t, riscv_instr_format_t, format_string,
+  riscv_instr_name_t, riscv_instr_format_t, va_base_instr,
   MAX_INSTR_STR_LEN, riscv_instr_category_t;
 import riscv.gen.isa.riscv_instr: riscv_instr;
 import riscv.gen.isa.riscv_floating_point_instr: riscv_floating_point_instr;
@@ -63,6 +63,8 @@ class riscv_vector_instr: riscv_floating_point_instr
   bool               rand_nfields;
   @rand ubvec!4      emul;
 
+  enum va_base_instr VA_BASE = va_base_instr.VA_NO_BASE;
+
   constraint!q{
     if (m_cfg.vector_cfg.reserved_vregs.length > 0) {
       !(vd inside [m_cfg.vector_cfg.reserved_vregs]);
@@ -126,14 +128,14 @@ class riscv_vector_instr: riscv_floating_point_instr
     if (m_cfg.vector_cfg.vtype.vlmul  > 1) {
       // For vadc and vsbc, an illegal instruction exception is raised if the
       // destination vector register is v0 and LMUL> 1
-      if (instr_name inside [riscv_instr_name_t.VADC,
-			     riscv_instr_name_t.VSBC]) {
+      if (VA_BASE inside [va_base_instr.VADC,
+			  va_base_instr.VSBC]) {
 	vd != 0;
       }
       // For vmadc and vmsbc, an illegal instruction exception is raised if the
       // destination vector register overlaps asource vector register group and LMUL > 1
-      if (instr_name inside [riscv_instr_name_t.VMADC,
-			     riscv_instr_name_t.VMSBC]) {
+      if (VA_BASE inside [va_base_instr.VMADC,
+			  va_base_instr.VMSBC]) {
 	vd != vs2;
 	vd != vs1;
       }
@@ -175,10 +177,10 @@ class riscv_vector_instr: riscv_floating_point_instr
   // The destination vector register group for vslideup cannot overlap the vector register
   // group of the source vector register group or the mask register
   constraint!q{
-    if (instr_name inside [riscv_instr_name_t.VSLIDEUP,
-			   riscv_instr_name_t.VSLIDE1UP,
-			   riscv_instr_name_t.VSLIDEDOWN,
-			   riscv_instr_name_t.VSLIDE1DOWN]) {
+    if (VA_BASE inside [va_base_instr.VSLIDEUP,
+			va_base_instr.VSLIDE1UP,
+			va_base_instr.VSLIDEDOWN,
+			va_base_instr.VSLIDE1DOWN]) {
       vd != vs2;
       vd != vs1;
       (vm == false) -> (vd != 0);
@@ -189,7 +191,7 @@ class riscv_vector_instr: riscv_floating_point_instr
   // For any vrgather instruction, the destination vector register group cannot overlap
   // with the source vector register group
   constraint!q{
-    if (instr_name == riscv_instr_name_t.VRGATHER) {
+    if (VA_BASE == va_base_instr.VRGATHER) {
       vd != vs2;
       vd != vs1;
       (vm == false) -> (vd != 0);
@@ -200,7 +202,7 @@ class riscv_vector_instr: riscv_floating_point_instr
   // The destination vector register group cannot overlap the source vector register
   // group or the source vector mask register
   constraint!q{
-    if (instr_name == riscv_instr_name_t.VCOMPRESS) {
+    if (VA_BASE == va_base_instr.VCOMPRESS) {
       vd != vs2;
       vd != vs1;
       (vm == false) -> (vd != 0);
@@ -257,18 +259,18 @@ class riscv_vector_instr: riscv_floating_point_instr
 
   constraint!q{
     // Below instruction is always masked
-    if (instr_name inside [riscv_instr_name_t.VMERGE,
-			   riscv_instr_name_t.VFMERGE,
-			   riscv_instr_name_t.VADC,
-			   riscv_instr_name_t.VSBC]) {
+    if (VA_BASE inside [va_base_instr.VMERGE,
+			va_base_instr.VFMERGE,
+			va_base_instr.VADC,
+			va_base_instr.VSBC]) {
       vm == false;
     }
   } vector_mask_enable_c;
 
   constraint!q{
     // (vm=0) is reserved for below ops
-    if (instr_name inside [riscv_instr_name_t.VMV, riscv_instr_name_t.VFMV,
-			   riscv_instr_name_t.VCOMPRESS, riscv_instr_name_t.VFMV_F_S,
+    if (instr_name inside [riscv_instr_name_t.VMV_V_V, riscv_instr_name_t.VMV_V_X, riscv_instr_name_t.VMV_V_I,
+			   riscv_instr_name_t.VFMV_V_F, riscv_instr_name_t.VCOMPRESS_VM, riscv_instr_name_t.VFMV_F_S,
 			   riscv_instr_name_t.VFMV_S_F, riscv_instr_name_t.VMV_X_S,
 			   riscv_instr_name_t.VMV_S_X, riscv_instr_name_t.VMV1R_V,
 			   riscv_instr_name_t.VMV2R_V, riscv_instr_name_t.VMV4R_V,
@@ -285,11 +287,12 @@ class riscv_vector_instr: riscv_floating_point_instr
     }
   } vector_mask_instr_c;
 
-  constraint!q{
-    if (! m_cfg.vector_cfg.vec_fp) {
-      va_variant != va_variant_t.VF;
-    }
-  } disable_floating_point_varaint_c;
+  // This is now dealt with in config object
+  // constraint!q{
+  //   if (! m_cfg.vector_cfg.vec_fp) {
+  //     va_variant != va_variant_t.VF;
+  //   }
+  // } disable_floating_point_varaint_c;
 
   constraint!q{
     // TODO: Check why this is needed?
@@ -351,8 +354,8 @@ class riscv_vector_instr: riscv_floating_point_instr
     string name = instr_name.to!string();
     // 19.2.2. Vector Add with Carry/Subtract with Borrow Reserved under EDIV>1
     if ((cfg.vector_cfg.vtype.vediv > 1) &&
-	(instr_name.inside(riscv_instr_name_t.VADC, riscv_instr_name_t.VSBC,
-			   riscv_instr_name_t.VMADC, riscv_instr_name_t.VMSBC))) {
+	(VA_BASE.inside(va_base_instr.VADC, va_base_instr.VSBC,
+			va_base_instr.VMADC, va_base_instr.VMSBC))) {
       return false;
     }
     // Disable widening/narrowing instruction when LMUL == 8
@@ -364,11 +367,11 @@ class riscv_vector_instr: riscv_floating_point_instr
       return false;
     }
     // TODO: Clean up this list, it's causing gcc compile error now
-    if (instr_name.inside(riscv_instr_name_t.VWMACCSU,
-			  riscv_instr_name_t.VMERGE,
-			  riscv_instr_name_t.VFMERGE,
-			  riscv_instr_name_t.VMADC,
-			  riscv_instr_name_t.VMSBC)) {
+    if (VA_BASE.inside(va_base_instr.VWMACCSU,
+		       va_base_instr.VMERGE,
+		       va_base_instr.VFMERGE,
+		       va_base_instr.VMADC,
+		       va_base_instr.VMSBC)) {
       return false;
     }
     // The standard vector floating-point instructions treat 16-bit, 32-bit, 64-bit,
@@ -387,14 +390,33 @@ class riscv_vector_instr: riscv_floating_point_instr
     string name = super.get_instr_name();
     if (category.inside(riscv_instr_category_t.LOAD, riscv_instr_category_t.STORE)) {
       // Add eew before ".v" or "ff.v" suffix
-      if (instr_name.inside(riscv_instr_name_t.VLEFF_V, riscv_instr_name_t.VLSEGEFF_V)) {
-	name = name[0..name.length - 4];
-        name = format("%0s%0dFF.V", name, eew);
-      }
-      else {
-        name = name[0..name.length - 2];
-        name = format("%0s%0d.V", name, eew);
-      }
+      // if (instr_name.inside(riscv_instr_name_t.VLEFF_V, riscv_instr_name_t.VLSEGEFF_V)) {
+      // 	name = name[0..name.length - 4];
+      //   name = format("%0s%0dFF.V", name, eew);
+      // }
+      // else {
+      name = name[0..name.length - 2];
+      name = format("%0s%0d.V", name, eew);
+      // }
+      uvm_info(get_full_name(), format("%0s -> %0s", super.get_instr_name(), name), UVM_LOW);
+    }
+    return name;
+  }
+
+  override char[] get_instr_name(char[] buf) {
+    import std.format: sformat;
+    char[32] buf_;
+    char[] name = super.get_instr_name(buf_);
+    if (category.inside(riscv_instr_category_t.LOAD, riscv_instr_category_t.STORE)) {
+      // Add eew before ".v" or "ff.v" suffix
+      // if (instr_name.inside(riscv_instr_name_t.VLEFF_V, riscv_instr_name_t.VLSEGEFF_V)) {
+      // 	name = name[0..name.length - 4];
+      //   name = sformat!("%0s%0dFF.V")(buf, name, eew);
+      // }
+      // else {
+      name = name[0..name.length - 2];
+      name = sformat!("%0s%0d.V")(buf, name, eew);
+      // }
       uvm_info(get_full_name(), format("%0s -> %0s", super.get_instr_name(), name), UVM_LOW);
     }
     return name;
@@ -418,7 +440,7 @@ class riscv_vector_instr: riscv_floating_point_instr
       }
       break;
     case riscv_instr_format_t.VA_FORMAT:
-      if (instr_name == riscv_instr_name_t.VMV) {
+      if (VA_BASE == va_base_instr.VMV) {
 	switch (va_variant) {
 	case va_variant_t.VV:
 	  asm_str = format("vmv.v.v %s,%s", vd, vs1);
@@ -432,7 +454,7 @@ class riscv_vector_instr: riscv_floating_point_instr
 	default: uvm_info(get_full_name(), format("Unsupported va_variant %0s", va_variant), UVM_LOW);
 	}
       }
-      else if (instr_name == riscv_instr_name_t.VFMV) {
+      else if (VA_BASE == va_base_instr.VFMV) {
 	asm_str = format("vfmv.v.f %s,%s", vd, fs1);
       }
       else if (instr_name == riscv_instr_name_t.VMV_X_S) {
@@ -448,14 +470,14 @@ class riscv_vector_instr: riscv_floating_point_instr
 	asm_str = format("vfmv.s.f %s,%s", vd, fs1);
       }
       else {
+	enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
 	if (!has_va_variant) {
-	  asm_str = format("%0s ", get_instr_name());
-	  asm_str = format_string(asm_str, MAX_INSTR_STR_LEN);
+	  asm_str = format!FMT(get_instr_name());
 	  asm_str = asm_str ~ format("%0s,%0s,%0s", vd, vs2, vs1);
 	}
 	else {
 	  asm_str = format("%0s.%0s ", get_instr_name(), va_variant);
-	  asm_str = format_string(asm_str, MAX_INSTR_STR_LEN);
+	  asm_str = format!FMT(asm_str);
 	  switch (va_variant) {
 	  case va_variant_t.WV,
 	    va_variant_t.VV,
@@ -470,18 +492,18 @@ class riscv_vector_instr: riscv_floating_point_instr
 	    break;
 	  case va_variant_t.VF,
 	    va_variant_t.VFM:
-	    if (instr_name.inside(riscv_instr_name_t.VFMADD,
-				  riscv_instr_name_t.VFNMADD,
-				  riscv_instr_name_t.VFMACC,
-				  riscv_instr_name_t.VFNMACC,
-				  riscv_instr_name_t.VFNMSUB,
-				  riscv_instr_name_t.VFWNMSAC,
-				  riscv_instr_name_t.VFWMACC,
-				  riscv_instr_name_t.VFMSUB,
-				  riscv_instr_name_t.VFMSAC,
-				  riscv_instr_name_t.VFNMSAC,
-				  riscv_instr_name_t.VFWNMACC,
-				  riscv_instr_name_t.VFWMSAC)) {
+	    if (VA_BASE.inside(va_base_instr.VFMADD,
+			       va_base_instr.VFNMADD,
+			       va_base_instr.VFMACC,
+			       va_base_instr.VFNMACC,
+			       va_base_instr.VFNMSUB,
+			       va_base_instr.VFWNMSAC,
+			       va_base_instr.VFWMACC,
+			       va_base_instr.VFMSUB,
+			       va_base_instr.VFMSAC,
+			       va_base_instr.VFNMSAC,
+			       va_base_instr.VFWNMACC,
+			       va_base_instr.VFWMSAC)) {
 	      asm_str = asm_str ~ format("%0s,%0s,%0s", vd, fs1, vs2);
 	    }
 	    else {
@@ -491,14 +513,14 @@ class riscv_vector_instr: riscv_floating_point_instr
 	  case va_variant_t.WX,
 	    va_variant_t.VX,
 	    va_variant_t.VXM:
-	    if (instr_name.inside(riscv_instr_name_t.VMADD,
-				  riscv_instr_name_t.VNMSUB,
-				  riscv_instr_name_t.VMACC,
-				  riscv_instr_name_t.VNMSAC,
-				  riscv_instr_name_t.VWMACCSU,
-				  riscv_instr_name_t.VWMACCU,
-				  riscv_instr_name_t.VWMACCUS,
-				  riscv_instr_name_t.VWMACC)) {
+	    if (VA_BASE.inside(va_base_instr.VMADD,
+			       va_base_instr.VNMSUB,
+			       va_base_instr.VMACC,
+			       va_base_instr.VNMSAC,
+			       va_base_instr.VWMACCSU,
+			       va_base_instr.VWMACCU,
+			       va_base_instr.VWMACCUS,
+			       va_base_instr.VWMACC)) {
 	      asm_str ~= format("%0s,%0s,%0s", vd, rs1, vs2);
 	    }
 	    else {
@@ -589,6 +611,213 @@ class riscv_vector_instr: riscv_floating_point_instr
     return asm_str.toLower();
   }
 
+  override char[] convert2asm(char[] buf, string prefix = "") {
+    import std.string: toLower, toLowerInPlace;
+    import std.format: sformat;
+
+    char[64] instr_name_buf;
+    char[32] instr_buf;
+
+    char[64] nfields_buf;
+
+    string asm_str;
+    char[] asm_buf;
+
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+
+    switch (instr_format) {
+    case riscv_instr_format_t.VS2_FORMAT:
+      if (instr_name == riscv_instr_name_t.VID_V) {
+	asm_buf = sformat!("vid.v %s")(buf, vd);
+      }
+      else if (instr_name.inside(riscv_instr_name_t.VPOPC_M,
+				 riscv_instr_name_t.VFIRST_M)) {
+	asm_buf = sformat!("%0s %0s,%0s")(buf, get_instr_name(instr_buf), rd, vs2);
+      }
+      else {
+	asm_buf = sformat!("%0s %0s,%0s")(buf, get_instr_name(instr_buf), vd, vs2);
+      }
+      break;
+    case riscv_instr_format_t.VA_FORMAT:
+      if (VA_BASE == va_base_instr.VMV) {
+	switch (va_variant) {
+	case va_variant_t.VV:
+	  asm_buf = sformat!("vmv.v.v %s,%s")(buf, vd, vs1);
+	  break;
+	case va_variant_t.VX:
+	  asm_buf = sformat!("vmv.v.x %s,%s")(buf, vd, rs1);
+	  break;
+	case va_variant_t.VI:
+	  asm_buf = sformat!("vmv.v.i %s,%s")(buf, vd, imm_str);
+	  break;
+	default: uvm_info(get_full_name(), format("Unsupported va_variant %0s", va_variant), UVM_LOW);
+	}
+      }
+      else if (VA_BASE == va_base_instr.VFMV) {
+	asm_buf = sformat!("vfmv.v.f %s,%s")(buf, vd, fs1);
+      }
+      else if (instr_name == riscv_instr_name_t.VMV_X_S) {
+	asm_buf = sformat!("vmv.x.s %s,%s")(buf, rd, vs2);
+      }
+      else if (instr_name == riscv_instr_name_t.VMV_S_X) {
+	asm_buf = sformat!("vmv.s.x %s,%s")(buf, vd, rs1);
+      }
+      else if (instr_name == riscv_instr_name_t.VFMV_F_S) {
+	asm_buf = sformat!("vfmv.f.s %s,%s")(buf, fd, vs2);
+      }
+      else if (instr_name == riscv_instr_name_t.VFMV_S_F) {
+	asm_buf = sformat!("vfmv.s.f %s,%s")(buf, vd, fs1);
+      }
+      else {
+	if (!has_va_variant) {
+	  char[] instr_name_str = sformat!FMT(instr_name_buf, get_instr_name(instr_buf));
+	  asm_buf = sformat!("%0s%0s,%0s,%0s")(buf, instr_name_str, vd, vs2, vs1);
+	}
+	else {
+	  char[64] instr_name_buf2;
+	  char[] instr_name_str2 = sformat!("%0s.%0s ")(instr_name_buf2, get_instr_name(instr_buf), va_variant);
+	  char[] instr_name_str = sformat!FMT(instr_name_buf, instr_name_str2);
+	  switch (va_variant) {
+	  case va_variant_t.WV, 
+	    va_variant_t.VV,
+	    va_variant_t.VVM,
+	    va_variant_t.VM:
+	    asm_buf = sformat!("%0s%0s,%0s,%0s")(buf, instr_name_str, vd, vs2, vs1);
+	    break;
+	  case va_variant_t.WI,
+	    va_variant_t.VI,
+	    va_variant_t.VIM:
+	    asm_buf = sformat!("%0s%0s,%0s,%0s")(buf, instr_name_str, vd, vs2, imm_str);
+	    break;
+	  case va_variant_t.VF,
+	    va_variant_t.VFM:
+	    if (VA_BASE.inside(va_base_instr.VFMADD,
+			       va_base_instr.VFNMADD,
+			       va_base_instr.VFMACC,
+			       va_base_instr.VFNMACC,
+			       va_base_instr.VFNMSUB,
+			       va_base_instr.VFWNMSAC,
+			       va_base_instr.VFWMACC,
+			       va_base_instr.VFMSUB,
+			       va_base_instr.VFMSAC,
+			       va_base_instr.VFNMSAC,
+			       va_base_instr.VFWNMACC,
+			       va_base_instr.VFWMSAC)) {
+	      asm_buf = sformat!("%0s%0s,%0s,%0s")(buf, instr_name_str, vd, fs1, vs2);
+	    }
+	    else {
+	      asm_buf = sformat!("%0s%0s,%0s,%0s")(buf, instr_name_str, vd, vs2, fs1);
+	    }
+	    break;
+	  case va_variant_t.WX,
+	    va_variant_t.VX,
+	    va_variant_t.VXM:
+	    if (VA_BASE.inside(va_base_instr.VMADD,
+			       va_base_instr.VNMSUB,
+			       va_base_instr.VMACC,
+			       va_base_instr.VNMSAC,
+			       va_base_instr.VWMACCSU,
+			       va_base_instr.VWMACCU,
+			       va_base_instr.VWMACCUS,
+			       va_base_instr.VWMACC)) {
+	      asm_buf = sformat!("%0s%0s,%0s,%0s")(buf, instr_name_str, vd, rs1, vs2);
+	    }
+	    else {
+	      asm_buf = sformat!("%0s%0s,%0s,%0s")(buf, instr_name_str, vd, vs2, rs1);
+	    }
+	    break;
+	  default: break;
+	  }
+	}
+      }
+      break;
+    case riscv_instr_format_t.VL_FORMAT:
+      if (sub_extension == "zvlsseg") {
+	asm_buf = sformat!("%0s %s,(%s)")(buf, add_nfields(nfields_buf, get_instr_name(instr_buf), "vlseg"),
+					  vd, rs1);
+      }
+      else {
+	asm_buf = sformat!("%0s %s,(%s)")(buf, get_instr_name(instr_buf), vd, rs1);
+      }
+      break;
+    case riscv_instr_format_t.VS_FORMAT:
+      if (sub_extension == "zvlsseg") {
+	asm_buf = sformat!("%0s %s,(%s)")(buf, add_nfields(nfields_buf, get_instr_name(instr_buf), "vsseg"),
+					  vs3, rs1);
+      }
+      else {
+	asm_buf = sformat!("%0s %s,(%s)")(buf, get_instr_name(instr_buf), vs3, rs1);
+      }
+      break;
+    case riscv_instr_format_t.VLS_FORMAT:
+      if (sub_extension == "zvlsseg") {
+	asm_buf = sformat!("%0s %0s,(%0s),%0s")(buf, add_nfields(nfields_buf, get_instr_name(instr_buf), "vlsseg"),
+						vd, rs1, rs2);
+      }
+      else {
+	asm_buf = sformat!("%0s %0s,(%0s),%0s")(buf, get_instr_name(instr_buf),
+						vd, rs1, rs2);
+      }
+      break;
+    case riscv_instr_format_t.VSS_FORMAT:
+      if (sub_extension == "zvlsseg") {
+	asm_buf = sformat!("%0s %0s,(%0s),%0s")(buf, add_nfields(nfields_buf, get_instr_name(instr_buf), "vssseg"),
+						vs3, rs1, rs2);
+      }
+      else {
+	asm_buf = sformat!("%0s %0s,(%0s),%0s")(buf, get_instr_name(instr_buf),
+						vs3, rs1, rs2);
+      }
+      break;
+    case riscv_instr_format_t.VLX_FORMAT:
+      if (sub_extension == "zvlsseg") {
+	asm_buf = sformat!("%0s %0s,(%0s),%0s")(buf, add_nfields(nfields_buf, get_instr_name(instr_buf), "vlxseg"),
+						vd, rs1, vs2);
+      }
+      else {
+	asm_buf = sformat!("%0s %0s,(%0s),%0s")(buf, get_instr_name(instr_buf),
+						vd, rs1, vs2);
+      }
+      break;
+    case riscv_instr_format_t.VSX_FORMAT:
+      if (sub_extension == "zvlsseg") {
+	asm_buf = sformat!("%0s %0s,(%0s),%0s")(buf, add_nfields(nfields_buf, get_instr_name(instr_buf), "vsxseg"),
+						vs3, rs1, vs2);
+      }
+      else {
+	asm_buf = sformat!("%0s %0s,(%0s),%0s")(buf, get_instr_name(instr_buf),
+						vs3, rs1, vs2);
+      }
+      break;
+    case riscv_instr_format_t.VAMO_FORMAT:
+      if (wd) {
+	asm_buf = sformat!("%0s %0s,(%0s),%0s,%0s")(buf, get_instr_name(instr_buf), vd,
+						    rs1, vs2, vd);
+      }
+      else {
+	asm_buf = sformat!("%0s x0,(%0s),%0s,%0s")(buf, get_instr_name(instr_buf),
+						   rs1, vs2, vs3);
+      }
+      break;
+    default:
+      uvm_fatal(get_full_name(), format("Unsupported format %0s", instr_format));
+    }
+
+    // Add vector mask
+    string vm_str = vec_vm_str();
+    if (vm_str != "") {
+      buf[asm_buf.length..asm_buf.length+vm_str.length] = vm_str;
+      asm_buf = buf[0..asm_buf.length+vm_str.length];
+    }
+
+
+    toLowerInPlace(asm_buf);
+
+    assert(asm_buf.ptr is buf.ptr);
+    return asm_buf;
+  }
+
+
   override void pre_randomize() {
     super.pre_randomize();
     rand_mode!q{vs1}(has_vs1);
@@ -648,12 +877,12 @@ class riscv_vector_instr: riscv_floating_point_instr
       return "";
     }
     else {
-      if (instr_name.inside(riscv_instr_name_t.VMERGE,
-			    riscv_instr_name_t.VFMERGE,
-			    riscv_instr_name_t.VADC,
-			    riscv_instr_name_t.VSBC,
-			    riscv_instr_name_t.VMADC,
-			    riscv_instr_name_t.VMSBC)) {
+      if (VA_BASE.inside(va_base_instr.VMERGE,
+			 va_base_instr.VFMERGE,
+			 va_base_instr.VADC,
+			 va_base_instr.VSBC,
+			 va_base_instr.VMADC,
+			 va_base_instr.VMSBC)) {
         return ",v0";
       }
       else {
@@ -667,6 +896,18 @@ class riscv_vector_instr: riscv_floating_point_instr
     return format("%0s%0d%0s", prefix, nfields + 1, suffix);
   }
 
+  char[] add_nfields(char[] buf, string instr_name, string prefix) {
+    import std.format: sformat;
+    string suffix = instr_name[prefix.length..instr_name.length];
+    return sformat!("%0s%0d%0s")(buf, prefix, nfields + 1, suffix);
+  }
+
+  char[] add_nfields(char[] buf, char[] instr_name, string prefix) {
+    import std.format: sformat;
+    char[] suffix = instr_name[prefix.length..instr_name.length];
+    return sformat!("%0s%0d%0s")(buf, prefix, nfields + 1, suffix);
+  }
+
   string add_eew(string instr_name, string prefix) {
     string suffix = instr_name[prefix.length..instr_name.length];
     return format("%0s%0d%0s", prefix,  eew, suffix);
diff --git a/euvm/riscv/gen/isa/riscv_zba_instr.d b/euvm/riscv/gen/isa/riscv_zba_instr.d
index b3a5d3f9..49fc4c94 100644
--- a/euvm/riscv/gen/isa/riscv_zba_instr.d
+++ b/euvm/riscv/gen/isa/riscv_zba_instr.d
@@ -25,7 +25,7 @@ import riscv.gen.target: supported_isa;
 
 import std.format: format;
 
-import esdl.data.bvec: ubvec, toubvec, clog2;
+import esdl.data.bvec: ubvec, UBVEC, clog2;
 import uvm;
 
 import std.algorithm: canFind;
@@ -44,10 +44,10 @@ class riscv_zba_instr: riscv_instr
 
   override void set_imm_len() {
     if (instr_name != riscv_instr_name_t.SLLI_UW) {
-      imm_len = toubvec!5(clog2(XLEN) - 1);
+      imm_len = UBVEC!(5, clog2(XLEN) - 1);
     }
     else {
-      imm_len = toubvec!5(clog2(XLEN));
+      imm_len = UBVEC!(5, clog2(XLEN));
     }
     imm_mask = imm_mask << imm_len;
   }
@@ -56,39 +56,39 @@ class riscv_zba_instr: riscv_instr
     switch (instr_name) {
     case riscv_instr_name_t.SH1ADD,
       riscv_instr_name_t.SH2ADD,
-      riscv_instr_name_t.SH3ADD:     return toubvec!7(0b0110011);
+      riscv_instr_name_t.SH3ADD:     return UBVEC!(7, 0b0110011);
     case riscv_instr_name_t.SH1ADD_UW,
       riscv_instr_name_t.SH2ADD_UW,
-      riscv_instr_name_t.SH3ADD_UW:    return toubvec!7(0b0111011);
-    case riscv_instr_name_t.SLLI_UW:   return toubvec!7(0b0011011);
+      riscv_instr_name_t.SH3ADD_UW:    return UBVEC!(7, 0b0111011);
+    case riscv_instr_name_t.SLLI_UW:   return UBVEC!(7, 0b0011011);
     default:                           return super.get_opcode();
     }
   }
 
   override ubvec!3 get_func3() {
     switch (instr_name) {
-    case riscv_instr_name_t.ADD_UW:    return toubvec!3(0b000);
-    case riscv_instr_name_t.SH1ADD:    return toubvec!3(0b010);
-    case riscv_instr_name_t.SH2ADD:    return toubvec!3(0b100);
-    case riscv_instr_name_t.SH3ADD:    return toubvec!3(0b110);
-    case riscv_instr_name_t.SH1ADD_UW: return toubvec!3(0b010);
-    case riscv_instr_name_t.SH2ADD_UW: return toubvec!3(0b100);
-    case riscv_instr_name_t.SH3ADD_UW: return toubvec!3(0b110);
-    case riscv_instr_name_t.SLLI_UW:   return toubvec!3(0b001);
+    case riscv_instr_name_t.ADD_UW:    return UBVEC!(3, 0b000);
+    case riscv_instr_name_t.SH1ADD:    return UBVEC!(3, 0b010);
+    case riscv_instr_name_t.SH2ADD:    return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.SH3ADD:    return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.SH1ADD_UW: return UBVEC!(3, 0b010);
+    case riscv_instr_name_t.SH2ADD_UW: return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.SH3ADD_UW: return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.SLLI_UW:   return UBVEC!(3, 0b001);
     default:                           return super.get_func3();
     }
   }
 
   override ubvec!7 get_func7() {
     switch (instr_name) {
-    case riscv_instr_name_t.ADD_UW:    return toubvec!7(0b0000100);
-    case riscv_instr_name_t.SH1ADD:    return toubvec!7(0b0010000);
-    case riscv_instr_name_t.SH2ADD:    return toubvec!7(0b0010000);
-    case riscv_instr_name_t.SH3ADD:    return toubvec!7(0b0010000);
-    case riscv_instr_name_t.SH1ADD_UW: return toubvec!7(0b0010000);
-    case riscv_instr_name_t.SH2ADD_UW: return toubvec!7(0b0010000);
-    case riscv_instr_name_t.SH3ADD_UW: return toubvec!7(0b0010000);
-    case riscv_instr_name_t.SLLI_UW:   return toubvec!7(0b0010000);
+    case riscv_instr_name_t.ADD_UW:    return UBVEC!(7, 0b0000100);
+    case riscv_instr_name_t.SH1ADD:    return UBVEC!(7, 0b0010000);
+    case riscv_instr_name_t.SH2ADD:    return UBVEC!(7, 0b0010000);
+    case riscv_instr_name_t.SH3ADD:    return UBVEC!(7, 0b0010000);
+    case riscv_instr_name_t.SH1ADD_UW: return UBVEC!(7, 0b0010000);
+    case riscv_instr_name_t.SH2ADD_UW: return UBVEC!(7, 0b0010000);
+    case riscv_instr_name_t.SH3ADD_UW: return UBVEC!(7, 0b0010000);
+    case riscv_instr_name_t.SLLI_UW:   return UBVEC!(7, 0b0010000);
     default:                           return super.get_func7();
     }
   }
@@ -96,7 +96,7 @@ class riscv_zba_instr: riscv_instr
   override string convert2bin(string prefix = "") {
     string binary = "";
     if (instr_name == riscv_instr_name_t.SLLI_UW) {
-      binary = format("%8h", toubvec!5(0b0_0001) ~ cast(ubvec!7)(imm[0..6]) ~
+      binary = format("%8h", UBVEC!(5, 0b0_0001) ~ cast(ubvec!7)(imm[0..6]) ~
 		      rs1 ~ get_func3() ~ rd ~ get_opcode());
     }
     else {
diff --git a/euvm/riscv/gen/isa/riscv_zbb_instr.d b/euvm/riscv/gen/isa/riscv_zbb_instr.d
index b181b69e..ceb5fb5d 100644
--- a/euvm/riscv/gen/isa/riscv_zbb_instr.d
+++ b/euvm/riscv/gen/isa/riscv_zbb_instr.d
@@ -18,7 +18,7 @@
 module riscv.gen.isa.riscv_zbb_instr;
 
 import riscv.gen.riscv_instr_pkg: riscv_instr_group_t, riscv_instr_name_t,
-  riscv_instr_format_t, format_string, MAX_INSTR_STR_LEN;
+  riscv_instr_format_t, MAX_INSTR_STR_LEN;
 import riscv.gen.target: XLEN;
 import riscv.gen.isa.riscv_instr: riscv_instr;
 import riscv.gen.riscv_instr_gen_config: riscv_instr_gen_config;
@@ -27,7 +27,7 @@ import riscv.gen.target: supported_isa;
 import std.format: format;
 import std.string: toLower;
 
-import esdl.data.bvec: ubvec, toubvec, clog2;
+import esdl.data.bvec: ubvec, toubvec, clog2, UBVEC;
 import uvm;
 
 import std.algorithm: canFind;
@@ -73,10 +73,10 @@ class riscv_zbb_instr: riscv_instr
   override void set_imm_len() {
     if (instr_format == riscv_instr_format_t.I_FORMAT) {
       if (instr_name == riscv_instr_name_t.RORI) {
-        imm_len = toubvec!5(clog2(XLEN));
+        imm_len = UBVEC!(5, clog2(XLEN));
       }
       else {
-        imm_len = toubvec!5(5);
+        imm_len = UBVEC!(5, 5);
       }
     }
     imm_mask = imm_mask << imm_len;
@@ -86,7 +86,8 @@ class riscv_zbb_instr: riscv_instr
     string asm_str_final;
     string asm_str;
 
-    asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN);
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    asm_str = format!FMT(get_instr_name());
 
     switch (instr_format) {
     case riscv_instr_format_t.I_FORMAT: // instr rd rs1
@@ -116,6 +117,52 @@ class riscv_zbb_instr: riscv_instr
     return asm_str_final.toLower();
   }
 
+  override char[] convert2asm(char[] buf, string prefix = "") {
+    import std.string: toLower, toLowerInPlace;
+    import std.format: sformat;
+
+    char[32] instr_buf;
+    char[MAX_INSTR_STR_LEN+8] instr_name_buf;
+
+    string asm_str;
+    char[] asm_buf;
+
+    enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s";
+    char[] instr_name_str = sformat!FMT(instr_name_buf, get_instr_name(instr_buf));
+
+    switch (instr_format) {
+    case riscv_instr_format_t.I_FORMAT: // instr rd rs1
+      if (! has_imm) {
+	asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, rd, rs1);
+      }
+      break;
+    case riscv_instr_format_t.R_FORMAT: // instr rd rs1
+      if (! has_rs2) {
+	asm_buf = sformat!("%0s%0s, %0s")(buf, instr_name_str, rd, rs1);
+      }
+      break;
+    default: uvm_info(get_full_name(),
+		      format("Unsupported format %0s", instr_format),
+		      UVM_LOW);
+      break;
+    }
+
+    if (asm_buf == "") {
+      return super.convert2asm(buf, prefix);
+    }
+
+    if (comment != "") {
+      buf[asm_buf.length..asm_buf.length+2] = " #";
+      buf[asm_buf.length+2..asm_buf.length+2+comment.length] = comment;
+      asm_buf = buf[0..asm_buf.length+2+comment.length];
+    }
+
+    toLowerInPlace(asm_buf);
+
+    assert(asm_buf.ptr is buf.ptr);
+    return asm_buf;
+  }
+
   override ubvec!7 get_opcode() {
     switch (instr_name) {
     case riscv_instr_name_t.ANDN,
@@ -126,11 +173,11 @@ class riscv_zbb_instr: riscv_instr
       riscv_instr_name_t.ORN,
       riscv_instr_name_t.ROL,
       riscv_instr_name_t.ROR,
-      riscv_instr_name_t.XNOR:      return toubvec!7(0b011_0011);
+      riscv_instr_name_t.XNOR:      return UBVEC!(7, 0b011_0011);
     case riscv_instr_name_t.ZEXT_H:
-      return toubvec!7(0b011_0011 | (toubvec!7(is_rv64()) << 3));
+      return (UBVEC!(7, 0b011_0011) | (toubvec!7(is_rv64()) << 3));
     case riscv_instr_name_t.ROLW,
-      riscv_instr_name_t.RORW:      return toubvec!7(0b011_1011);
+      riscv_instr_name_t.RORW:      return UBVEC!(7, 0b011_1011);
     case riscv_instr_name_t.CLZ,
       riscv_instr_name_t.CPOP,
       riscv_instr_name_t.CTZ,
@@ -138,57 +185,57 @@ class riscv_zbb_instr: riscv_instr
       riscv_instr_name_t.CLZW,
       riscv_instr_name_t.CPOPW,
       riscv_instr_name_t.CTZW,
-      riscv_instr_name_t.RORIW:     return toubvec!7(0b001_1011);
+      riscv_instr_name_t.RORIW:     return UBVEC!(7, 0b001_1011);
     case riscv_instr_name_t.REV8,
       riscv_instr_name_t.RORI,
       riscv_instr_name_t.SEXT_B,
-      riscv_instr_name_t.SEXT_H:    return toubvec!7(0b001_0011);
+      riscv_instr_name_t.SEXT_H:    return UBVEC!(7, 0b001_0011);
     default:                        return super.get_opcode();
     }
   }
 
   override ubvec!3 get_func3() {
     switch (instr_name) {
-    case riscv_instr_name_t.ANDN:   return toubvec!3(0b111);
-    case riscv_instr_name_t.CLZ:    return toubvec!3(0b001);
-    case riscv_instr_name_t.CLZW:   return toubvec!3(0b001);
-    case riscv_instr_name_t.CPOP:   return toubvec!3(0b001);
-    case riscv_instr_name_t.CPOPW:  return toubvec!3(0b001);
-    case riscv_instr_name_t.CTZ:    return toubvec!3(0b001);
-    case riscv_instr_name_t.CTZW:   return toubvec!3(0b001);
-    case riscv_instr_name_t.MAX:    return toubvec!3(0b110);
-    case riscv_instr_name_t.MAXU:   return toubvec!3(0b111);
-    case riscv_instr_name_t.MIN:    return toubvec!3(0b100);
-    case riscv_instr_name_t.MINU:   return toubvec!3(0b101);
-    case riscv_instr_name_t.ORC_B:  return toubvec!3(0b101);
-    case riscv_instr_name_t.ORN:    return toubvec!3(0b110);
-    case riscv_instr_name_t.REV8:   return toubvec!3(0b101);
-    case riscv_instr_name_t.ROL:    return toubvec!3(0b001);
-    case riscv_instr_name_t.ROLW:   return toubvec!3(0b001);
-    case riscv_instr_name_t.ROR:    return toubvec!3(0b101);
-    case riscv_instr_name_t.RORW:   return toubvec!3(0b101);
-    case riscv_instr_name_t.RORI:   return toubvec!3(0b101);
-    case riscv_instr_name_t.RORIW:  return toubvec!3(0b101);
-    case riscv_instr_name_t.SEXT_B: return toubvec!3(0b001);
-    case riscv_instr_name_t.SEXT_H: return toubvec!3(0b001);
-    case riscv_instr_name_t.XNOR:   return toubvec!3(0b100);
-    case riscv_instr_name_t.ZEXT_H: return toubvec!3(0b100);
+    case riscv_instr_name_t.ANDN:   return UBVEC!(3, 0b111);
+    case riscv_instr_name_t.CLZ:    return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CLZW:   return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CPOP:   return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CPOPW:  return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CTZ:    return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CTZW:   return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.MAX:    return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.MAXU:   return UBVEC!(3, 0b111);
+    case riscv_instr_name_t.MIN:    return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.MINU:   return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.ORC_B:  return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.ORN:    return UBVEC!(3, 0b110);
+    case riscv_instr_name_t.REV8:   return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.ROL:    return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.ROLW:   return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.ROR:    return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.RORW:   return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.RORI:   return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.RORIW:  return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.SEXT_B: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.SEXT_H: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.XNOR:   return UBVEC!(3, 0b100);
+    case riscv_instr_name_t.ZEXT_H: return UBVEC!(3, 0b100);
     default:                        return super.get_func3();
     }
   }
 
   ubvec!5 get_func5() {
     switch (instr_name) {
-    case riscv_instr_name_t.CLZ:    return toubvec!5(0b0_0000);
-    case riscv_instr_name_t.CLZW:   return toubvec!5(0b0_0000);
-    case riscv_instr_name_t.CPOP:   return toubvec!5(0b0_0010);
-    case riscv_instr_name_t.CPOPW:  return toubvec!5(0b0_0010);
-    case riscv_instr_name_t.CTZ:    return toubvec!5(0b0_0001);
-    case riscv_instr_name_t.CTZW:   return toubvec!5(0b0_0001);
-    case riscv_instr_name_t.ORC_B:  return toubvec!5(0b0_0111);
-    case riscv_instr_name_t.REV8:   return toubvec!5(0b1_1000);
-    case riscv_instr_name_t.SEXT_B: return toubvec!5(0b0_0100);
-    case riscv_instr_name_t.SEXT_H: return toubvec!5(0b0_0101);
+    case riscv_instr_name_t.CLZ:    return UBVEC!(5, 0b0_0000);
+    case riscv_instr_name_t.CLZW:   return UBVEC!(5, 0b0_0000);
+    case riscv_instr_name_t.CPOP:   return UBVEC!(5, 0b0_0010);
+    case riscv_instr_name_t.CPOPW:  return UBVEC!(5, 0b0_0010);
+    case riscv_instr_name_t.CTZ:    return UBVEC!(5, 0b0_0001);
+    case riscv_instr_name_t.CTZW:   return UBVEC!(5, 0b0_0001);
+    case riscv_instr_name_t.ORC_B:  return UBVEC!(5, 0b0_0111);
+    case riscv_instr_name_t.REV8:   return UBVEC!(5, 0b1_1000);
+    case riscv_instr_name_t.SEXT_B: return UBVEC!(5, 0b0_0100);
+    case riscv_instr_name_t.SEXT_H: return UBVEC!(5, 0b0_0101);
     default: uvm_fatal(get_full_name(), format("Unsupported instruction %0s", instr_name));
       assert (false);
     }
@@ -196,31 +243,31 @@ class riscv_zbb_instr: riscv_instr
 
   override ubvec!7 get_func7() {
     switch (instr_name) {
-    case riscv_instr_name_t.ANDN:   return toubvec!7(0b010_0000);
-    case riscv_instr_name_t.CLZ:    return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.CLZW:   return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.CPOP:   return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.CPOPW:  return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.CTZ:    return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.CTZW:   return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.MAX:    return toubvec!7(0b000_0101);
-    case riscv_instr_name_t.MAXU:   return toubvec!7(0b000_0101);
-    case riscv_instr_name_t.MIN:    return toubvec!7(0b000_0101);
-    case riscv_instr_name_t.MINU:   return toubvec!7(0b000_0101);
-    case riscv_instr_name_t.ORC_B:  return toubvec!7(0b001_0100);
-    case riscv_instr_name_t.ORN:    return toubvec!7(0b010_0000);
+    case riscv_instr_name_t.ANDN:   return UBVEC!(7, 0b010_0000);
+    case riscv_instr_name_t.CLZ:    return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.CLZW:   return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.CPOP:   return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.CPOPW:  return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.CTZ:    return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.CTZW:   return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.MAX:    return UBVEC!(7, 0b000_0101);
+    case riscv_instr_name_t.MAXU:   return UBVEC!(7, 0b000_0101);
+    case riscv_instr_name_t.MIN:    return UBVEC!(7, 0b000_0101);
+    case riscv_instr_name_t.MINU:   return UBVEC!(7, 0b000_0101);
+    case riscv_instr_name_t.ORC_B:  return UBVEC!(7, 0b001_0100);
+    case riscv_instr_name_t.ORN:    return UBVEC!(7, 0b010_0000);
     case riscv_instr_name_t.REV8:
-      return toubvec!7(0b011_0100 | toubvec!7(is_rv64())); // 0110101 64 bit
-    case riscv_instr_name_t.ROL:    return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.ROLW:   return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.ROR:    return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.RORW:   return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.RORI:   return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.RORIW:  return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.SEXT_B: return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.SEXT_H: return toubvec!7(0b011_0000);
-    case riscv_instr_name_t.XNOR:   return toubvec!7(0b010_0000);
-    case riscv_instr_name_t.ZEXT_H: return toubvec!7(0b000_0100);
+      return (UBVEC!(7, 0b011_0100) | toubvec!7(is_rv64())); // 0110101 64 bit
+    case riscv_instr_name_t.ROL:    return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.ROLW:   return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.ROR:    return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.RORW:   return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.RORI:   return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.RORIW:  return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.SEXT_B: return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.SEXT_H: return UBVEC!(7, 0b011_0000);
+    case riscv_instr_name_t.XNOR:   return UBVEC!(7, 0b010_0000);
+    case riscv_instr_name_t.ZEXT_H: return UBVEC!(7, 0b000_0100);
     default:                        return super.get_func7();
     }
   }
diff --git a/euvm/riscv/gen/isa/riscv_zbc_instr.d b/euvm/riscv/gen/isa/riscv_zbc_instr.d
index 7c12c64f..7416c360 100644
--- a/euvm/riscv/gen/isa/riscv_zbc_instr.d
+++ b/euvm/riscv/gen/isa/riscv_zbc_instr.d
@@ -24,7 +24,7 @@ import riscv.gen.target: supported_isa;
 
 import std.format: format;
 
-import esdl.data.bvec: ubvec, toubvec, clog2;
+import esdl.data.bvec: ubvec, UBVEC, clog2;
 import uvm;
 
 import std.algorithm: canFind;
@@ -45,25 +45,25 @@ class riscv_zbc_instr: riscv_instr
     switch (instr_name) {
     case riscv_instr_name_t.CLMUL,
       riscv_instr_name_t.CLMULH,
-      riscv_instr_name_t.CLMULR: return toubvec!7(0b011_0011);
+      riscv_instr_name_t.CLMULR: return UBVEC!(7, 0b011_0011);
     default:                     return super.get_opcode();
     }
   }
 
   override ubvec!3 get_func3() {
     switch (instr_name) {
-    case riscv_instr_name_t.CLMUL:  return toubvec!3(0b001);
-    case riscv_instr_name_t.CLMULH: return toubvec!3(0b011);
-    case riscv_instr_name_t.CLMULR: return toubvec!3(0b010);
+    case riscv_instr_name_t.CLMUL:  return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.CLMULH: return UBVEC!(3, 0b011);
+    case riscv_instr_name_t.CLMULR: return UBVEC!(3, 0b010);
     default:                        return super.get_func3();
     }
   }
 
   override ubvec!7 get_func7() {
     switch (instr_name) {
-    case riscv_instr_name_t.CLMUL:  return toubvec!7(0b000_0101);
-    case riscv_instr_name_t.CLMULH: return toubvec!7(0b000_0101);
-    case riscv_instr_name_t.CLMULR: return toubvec!7(0b000_0101);
+    case riscv_instr_name_t.CLMUL:  return UBVEC!(7, 0b000_0101);
+    case riscv_instr_name_t.CLMULH: return UBVEC!(7, 0b000_0101);
+    case riscv_instr_name_t.CLMULR: return UBVEC!(7, 0b000_0101);
     default:                        return super.get_func7();
     }
   }
diff --git a/euvm/riscv/gen/isa/riscv_zbs_instr.d b/euvm/riscv/gen/isa/riscv_zbs_instr.d
index 8f52eeec..cb929760 100644
--- a/euvm/riscv/gen/isa/riscv_zbs_instr.d
+++ b/euvm/riscv/gen/isa/riscv_zbs_instr.d
@@ -26,7 +26,7 @@ import riscv.gen.target: supported_isa, XLEN;
 
 import std.format: format;
 
-import esdl.data.bvec: ubvec, toubvec, clog2;
+import esdl.data.bvec: ubvec, UBVEC, clog2;
 import uvm;
 
 import std.algorithm: canFind;
@@ -51,7 +51,7 @@ class riscv_zbs_instr: riscv_instr
     if (instr_format == riscv_instr_format_t.I_FORMAT) {
       if ([riscv_instr_name_t.BCLRI, riscv_instr_name_t.BEXTI,
 	   riscv_instr_name_t.BINVI, riscv_instr_name_t.BSETI].canFind(instr_name)) {
-	imm_len = toubvec!5(clog2(XLEN));
+	imm_len = UBVEC!(5, clog2(XLEN));
       }
     }
     imm_mask = imm_mask << imm_len;
@@ -66,35 +66,35 @@ class riscv_zbs_instr: riscv_instr
       riscv_instr_name_t.BCLRI,
       riscv_instr_name_t.BEXTI,
       riscv_instr_name_t.BINVI,
-      riscv_instr_name_t.BSETI: return toubvec!7(0b0010011);
+      riscv_instr_name_t.BSETI: return UBVEC!(7, 0b0010011);
     default : return super.get_opcode();
     }
   }
 
   override ubvec!3 get_func3() {
     switch (instr_name) {
-    case riscv_instr_name_t.BCLR:  return toubvec!3(0b001);
-    case riscv_instr_name_t.BCLRI: return toubvec!3(0b001);
-    case riscv_instr_name_t.BEXT:  return toubvec!3(0b101);
-    case riscv_instr_name_t.BEXTI: return toubvec!3(0b101);
-    case riscv_instr_name_t.BINV:  return toubvec!3(0b001);
-    case riscv_instr_name_t.BINVI: return toubvec!3(0b001);
-    case riscv_instr_name_t.BSET:  return toubvec!3(0b001);
-    case riscv_instr_name_t.BSETI: return toubvec!3(0b001);
+    case riscv_instr_name_t.BCLR:  return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.BCLRI: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.BEXT:  return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.BEXTI: return UBVEC!(3, 0b101);
+    case riscv_instr_name_t.BINV:  return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.BINVI: return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.BSET:  return UBVEC!(3, 0b001);
+    case riscv_instr_name_t.BSETI: return UBVEC!(3, 0b001);
     default: return super.get_func3();
     }
   }
 
   override ubvec!7 get_func7() {
     switch (instr_name) {
-    case riscv_instr_name_t.BCLR:  return toubvec!7(0b0100100);
-    case riscv_instr_name_t.BCLRI: return toubvec!7(0b0100100);
-    case riscv_instr_name_t.BEXT:  return toubvec!7(0b0100100);
-    case riscv_instr_name_t.BEXTI: return toubvec!7(0b0100100);
-    case riscv_instr_name_t.BINV:  return toubvec!7(0b0110100);
-    case riscv_instr_name_t.BINVI: return toubvec!7(0b0110100);
-    case riscv_instr_name_t.BSET:  return toubvec!7(0b0010100);
-    case riscv_instr_name_t.BSETI: return toubvec!7(0b0010100);
+    case riscv_instr_name_t.BCLR:  return UBVEC!(7, 0b0100100);
+    case riscv_instr_name_t.BCLRI: return UBVEC!(7, 0b0100100);
+    case riscv_instr_name_t.BEXT:  return UBVEC!(7, 0b0100100);
+    case riscv_instr_name_t.BEXTI: return UBVEC!(7, 0b0100100);
+    case riscv_instr_name_t.BINV:  return UBVEC!(7, 0b0110100);
+    case riscv_instr_name_t.BINVI: return UBVEC!(7, 0b0110100);
+    case riscv_instr_name_t.BSET:  return UBVEC!(7, 0b0010100);
+    case riscv_instr_name_t.BSETI: return UBVEC!(7, 0b0010100);
     default : return super.get_func7();
     }
   }
diff --git a/euvm/riscv/gen/isa/rv32b_instr.d b/euvm/riscv/gen/isa/rv32b_instr.d
index a06efd5e..361bb85a 100644
--- a/euvm/riscv/gen/isa/rv32b_instr.d
+++ b/euvm/riscv/gen/isa/rv32b_instr.d
@@ -33,9 +33,9 @@ version (RISCV_INSTR_STRING_MIXIN) {
   mixin (riscv_b_instr_mixin(PACK,     R_FORMAT, LOGICAL, RV32B));
   mixin (riscv_b_instr_mixin(PACKU,    R_FORMAT, LOGICAL, RV32B));
   mixin (riscv_b_instr_mixin(PACKH,    R_FORMAT, LOGICAL, RV32B));
-  mixin (riscv_b_instr_mixin(XPERM_N,  R_FORMAT, LOGICAL, RV32B));
-  mixin (riscv_b_instr_mixin(XPERM_B,  R_FORMAT, LOGICAL, RV32B));
-  mixin (riscv_b_instr_mixin(XPERM_H,  R_FORMAT, LOGICAL, RV32B));
+  mixin (riscv_b_instr_mixin(XPERM5,  R_FORMAT, LOGICAL, RV32B));
+  mixin (riscv_b_instr_mixin(XPERM8,  R_FORMAT, LOGICAL, RV32B));
+  mixin (riscv_b_instr_mixin(XPERM16,  R_FORMAT, LOGICAL, RV32B));
   // SHIFT intructions
   mixin (riscv_b_instr_mixin(SLO,    R_FORMAT, SHIFT, RV32B));
   mixin (riscv_b_instr_mixin(SRO,    R_FORMAT, SHIFT, RV32B));
@@ -77,12 +77,12 @@ version (RISCV_INSTR_STRING_MIXIN) {
    { mixin RISCV_INSTR_MIXIN!(PACKU,    R_FORMAT, LOGICAL, RV32B); }
    class riscv_PACKH_instr: riscv_b_instr
    { mixin RISCV_INSTR_MIXIN!(PACKH,    R_FORMAT, LOGICAL, RV32B); }
-   class riscv_XPERM_N_instr: riscv_b_instr
-   { mixin RISCV_INSTR_MIXIN!(XPERM_N,  R_FORMAT, LOGICAL, RV32B); }
-   class riscv_XPERM_B_instr: riscv_b_instr
-   { mixin RISCV_INSTR_MIXIN!(XPERM_B,  R_FORMAT, LOGICAL, RV32B); }
-   class riscv_XPERM_H_instr: riscv_b_instr
-   { mixin RISCV_INSTR_MIXIN!(XPERM_H,  R_FORMAT, LOGICAL, RV32B); }
+   class riscv_XPERM4_instr: riscv_b_instr
+   { mixin RISCV_INSTR_MIXIN!(XPERM4,  R_FORMAT, LOGICAL, RV32B); }
+   class riscv_XPERM8_instr: riscv_b_instr
+   { mixin RISCV_INSTR_MIXIN!(XPERM8,  R_FORMAT, LOGICAL, RV32B); }
+   class riscv_XPERM16_instr: riscv_b_instr
+   { mixin RISCV_INSTR_MIXIN!(XPERM16,  R_FORMAT, LOGICAL, RV32B); }
    // SHIFT intructions
    class riscv_SLO_instr: riscv_b_instr
    { mixin RISCV_INSTR_MIXIN!(SLO,    R_FORMAT, SHIFT, RV32B); }
@@ -123,6 +123,10 @@ version (RISCV_INSTR_STRING_MIXIN) {
    { mixin RISCV_INSTR_MIXIN!(SHFLI,       I_FORMAT, ARITHMETIC, RV32B, UIMM); }
    class riscv_UNSHFLI_instr: riscv_b_instr
    { mixin RISCV_INSTR_MIXIN!(UNSHFLI,     I_FORMAT, ARITHMETIC, RV32B, UIMM); }
+   class riscv_UNZIP8_instr: riscv_b_instr
+   { mixin RISCV_INSTR_MIXIN!(UNZIP8,     I_FORMAT, ARITHMETIC, RV32B, UIMM); }
+   class riscv_UNZIP16_instr: riscv_b_instr
+   { mixin RISCV_INSTR_MIXIN!(UNZIP16,     I_FORMAT, ARITHMETIC, RV32B, UIMM); }
    class riscv_BCOMPRESS_instr: riscv_b_instr
    { mixin RISCV_INSTR_MIXIN!(BCOMPRESS,   R_FORMAT, ARITHMETIC, RV32B); }
    class riscv_BDECOMPRESS_instr: riscv_b_instr
diff --git a/euvm/riscv/gen/isa/rv32c_instr.d b/euvm/riscv/gen/isa/rv32c_instr.d
index 91607c4a..2ef05a65 100644
--- a/euvm/riscv/gen/isa/rv32c_instr.d
+++ b/euvm/riscv/gen/isa/rv32c_instr.d
@@ -52,57 +52,57 @@ version (RISCV_INSTR_STRING_MIXIN) {
  }
  else {
    class riscv_C_LW_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_LW,       CL_FORMAT, LOAD, RV32C, UIMM); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_LW,       CL_FORMAT, LOAD, RV32C, UIMM); }
    class riscv_C_SW_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_SW,       CS_FORMAT, STORE, RV32C, UIMM); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_SW,       CS_FORMAT, STORE, RV32C, UIMM); }
    class riscv_C_LWSP_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_LWSP,     CI_FORMAT, LOAD, RV32C, UIMM); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_LWSP,     CI_FORMAT, LOAD, RV32C, UIMM); }
    class riscv_C_SWSP_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_SWSP,     CSS_FORMAT, STORE, RV32C, UIMM); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_SWSP,     CSS_FORMAT, STORE, RV32C, UIMM); }
    class riscv_C_ADDI4SPN_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_ADDI4SPN, CIW_FORMAT, ARITHMETIC, RV32C, NZUIMM); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_ADDI4SPN, CIW_FORMAT, ARITHMETIC, RV32C, NZUIMM); }
    class riscv_C_ADDI_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_ADDI,     CI_FORMAT, ARITHMETIC, RV32C, NZIMM); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_ADDI,     CI_FORMAT, ARITHMETIC, RV32C, NZIMM); }
    class riscv_C_ADDI16SP_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_ADDI16SP, CI_FORMAT, ARITHMETIC, RV32C, NZIMM); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_ADDI16SP, CI_FORMAT, ARITHMETIC, RV32C, NZIMM); }
    class riscv_C_LI_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_LI,       CI_FORMAT, ARITHMETIC, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_LI,       CI_FORMAT, ARITHMETIC, RV32C); }
    class riscv_C_LUI_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_LUI,      CI_FORMAT, ARITHMETIC, RV32C, NZIMM); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_LUI,      CI_FORMAT, ARITHMETIC, RV32C, NZIMM); }
    class riscv_C_SUB_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_SUB,      CA_FORMAT, ARITHMETIC, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_SUB,      CA_FORMAT, ARITHMETIC, RV32C); }
    class riscv_C_ADD_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_ADD,      CR_FORMAT, ARITHMETIC, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_ADD,      CR_FORMAT, ARITHMETIC, RV32C); }
    class riscv_C_NOP_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_NOP,      CI_FORMAT, ARITHMETIC, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_NOP,      CI_FORMAT, ARITHMETIC, RV32C); }
    class riscv_C_MV_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_MV,       CR_FORMAT, ARITHMETIC, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_MV,       CR_FORMAT, ARITHMETIC, RV32C); }
    class riscv_C_ANDI_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_ANDI,     CB_FORMAT, LOGICAL, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_ANDI,     CB_FORMAT, LOGICAL, RV32C); }
    class riscv_C_XOR_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_XOR,      CA_FORMAT, LOGICAL, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_XOR,      CA_FORMAT, LOGICAL, RV32C); }
    class riscv_C_OR_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_OR,       CA_FORMAT, LOGICAL, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_OR,       CA_FORMAT, LOGICAL, RV32C); }
    class riscv_C_AND_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_AND,      CA_FORMAT, LOGICAL, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_AND,      CA_FORMAT, LOGICAL, RV32C); }
    class riscv_C_BEQZ_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_BEQZ,     CB_FORMAT, BRANCH, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_BEQZ,     CB_FORMAT, BRANCH, RV32C); }
    class riscv_C_BNEZ_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_BNEZ,     CB_FORMAT, BRANCH, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_BNEZ,     CB_FORMAT, BRANCH, RV32C); }
    class riscv_C_SRLI_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_SRLI,     CB_FORMAT, SHIFT, RV32C, NZUIMM); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_SRLI,     CB_FORMAT, SHIFT, RV32C, NZUIMM); }
    class riscv_C_SRAI_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_SRAI,     CB_FORMAT, SHIFT, RV32C, NZUIMM); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_SRAI,     CB_FORMAT, SHIFT, RV32C, NZUIMM); }
    class riscv_C_SLLI_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_SLLI,     CI_FORMAT, SHIFT, RV32C, NZUIMM); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_SLLI,     CI_FORMAT, SHIFT, RV32C, NZUIMM); }
    class riscv_C_J_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_J,        CJ_FORMAT, JUMP, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_J,        CJ_FORMAT, JUMP, RV32C); }
    class riscv_C_JAL_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_JAL,      CJ_FORMAT, JUMP, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_JAL,      CJ_FORMAT, JUMP, RV32C); }
    class riscv_C_JR_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_JR,       CR_FORMAT, JUMP, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_JR,       CR_FORMAT, JUMP, RV32C); }
    class riscv_C_JALR_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_JALR,     CR_FORMAT, JUMP, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_JALR,     CR_FORMAT, JUMP, RV32C); }
    class riscv_C_EBREAK_INSTR: riscv_compressed_instr
-   { mixin RISCV_INSTR_MIXIN!(C_EBREAK,   CI_FORMAT, SYSTEM, RV32C); }
+   { mixin RISCV_C_INSTR_MIXIN!(C_EBREAK,   CI_FORMAT, SYSTEM, RV32C); }
  }
diff --git a/euvm/riscv/gen/isa/rv32f_instr.d b/euvm/riscv/gen/isa/rv32f_instr.d
index ed49295b..06cd5b05 100644
--- a/euvm/riscv/gen/isa/rv32f_instr.d
+++ b/euvm/riscv/gen/isa/rv32f_instr.d
@@ -41,6 +41,7 @@ version (RISCV_INSTR_STRING_MIXIN) {
   mixin (riscv_fp_instr_mixin(FCVT_W_S,  I_FORMAT, ARITHMETIC, RV32F));
   mixin (riscv_fp_instr_mixin(FCVT_WU_S, I_FORMAT, ARITHMETIC, RV32F));
   mixin (riscv_fp_instr_mixin(FMV_X_W,   I_FORMAT, ARITHMETIC, RV32F));
+  mixin (riscv_fp_instr_mixin(FMV_X_S,   I_FORMAT, ARITHMETIC, RV32F));
   mixin (riscv_fp_instr_mixin(FEQ_S,     R_FORMAT, COMPARE, RV32F));
   mixin (riscv_fp_instr_mixin(FLT_S,     R_FORMAT, COMPARE, RV32F));
   mixin (riscv_fp_instr_mixin(FLE_S,     R_FORMAT, COMPARE, RV32F));
@@ -48,6 +49,7 @@ version (RISCV_INSTR_STRING_MIXIN) {
   mixin (riscv_fp_instr_mixin(FCVT_S_W,  I_FORMAT, ARITHMETIC, RV32F));
   mixin (riscv_fp_instr_mixin(FCVT_S_WU, I_FORMAT, ARITHMETIC, RV32F));
   mixin (riscv_fp_instr_mixin(FMV_W_X,   I_FORMAT, ARITHMETIC, RV32F));
+  mixin (riscv_fp_instr_mixin(FMV_S_X,   I_FORMAT, ARITHMETIC, RV32F));
  }
  else {
    class riscv_FLW_instr: riscv_floating_point_instr
@@ -88,6 +90,8 @@ version (RISCV_INSTR_STRING_MIXIN) {
    { mixin RISCV_INSTR_MIXIN!(FCVT_WU_S, I_FORMAT, ARITHMETIC, RV32F); }
    class riscv_FMV_X_W_instr: riscv_floating_point_instr
    { mixin RISCV_INSTR_MIXIN!(FMV_X_W,   I_FORMAT, ARITHMETIC, RV32F); }
+   class riscv_FMV_X_S_instr: riscv_floating_point_instr
+   { mixin RISCV_INSTR_MIXIN!(FMV_X_S,   I_FORMAT, ARITHMETIC, RV32F); }
    class riscv_FEQ_S_instr: riscv_floating_point_instr
    { mixin RISCV_INSTR_MIXIN!(FEQ_S,     R_FORMAT, COMPARE, RV32F); }
    class riscv_FLT_S_instr: riscv_floating_point_instr
@@ -102,4 +106,6 @@ version (RISCV_INSTR_STRING_MIXIN) {
    { mixin RISCV_INSTR_MIXIN!(FCVT_S_WU, I_FORMAT, ARITHMETIC, RV32F); }
    class riscv_FMV_W_X_instr: riscv_floating_point_instr
    { mixin RISCV_INSTR_MIXIN!(FMV_W_X,   I_FORMAT, ARITHMETIC, RV32F); }
+   class riscv_FMV_S_X_instr: riscv_floating_point_instr
+   { mixin RISCV_INSTR_MIXIN!(FMV_S_X,   I_FORMAT, ARITHMETIC, RV32F); }
  }
diff --git a/euvm/riscv/gen/isa/rv32i_instr.d b/euvm/riscv/gen/isa/rv32i_instr.d
index 0b179cbc..69f21237 100644
--- a/euvm/riscv/gen/isa/rv32i_instr.d
+++ b/euvm/riscv/gen/isa/rv32i_instr.d
@@ -17,6 +17,7 @@
 module riscv.gen.isa.rv32i_instr;
 
 import riscv.gen.riscv_defines;
+import riscv.gen.isa.riscv_instr: riscv_instr;
 
 import uvm;
 
@@ -71,22 +72,36 @@ version (RISCV_INSTR_STRING_MIXIN) {
   // SYNCH instructions
   mixin (riscv_instr_mixin(FENCE,  I_FORMAT, SYNCH, RV32I));
   mixin (riscv_instr_mixin(FENCE_I, I_FORMAT, SYNCH, RV32I));
+  mixin (riscv_instr_mixin(FENCE_TSO, I_FORMAT, SYNCH, RV32I));
+  mixin (riscv_instr_mixin(PAUSE, I_FORMAT, SYNCH, RV32I));
   mixin (riscv_instr_mixin(SFENCE_VMA, R_FORMAT, SYNCH, RV32I));
   // SYSTEM instructions
   mixin (riscv_instr_mixin(ECALL,   I_FORMAT, SYSTEM, RV32I));
+  mixin (riscv_instr_mixin(SCALL,   I_FORMAT, SYSTEM, RV32I));
   mixin (riscv_instr_mixin(EBREAK,  I_FORMAT, SYSTEM, RV32I));
-  mixin (riscv_instr_mixin(URET,    I_FORMAT, SYSTEM, RV32I));
+  mixin (riscv_instr_mixin(SBREAK,  I_FORMAT, SYSTEM, RV32I));
+  // mixin (riscv_instr_mixin(URET,    I_FORMAT, SYSTEM, RV32I));  -- deprecated
   mixin (riscv_instr_mixin(SRET,    I_FORMAT, SYSTEM, RV32I));
   mixin (riscv_instr_mixin(MRET,    I_FORMAT, SYSTEM, RV32I));
   mixin (riscv_instr_mixin(DRET,    I_FORMAT, SYSTEM, RV32I));
   mixin (riscv_instr_mixin(WFI,     I_FORMAT, INTERRUPT, RV32I));
   // CSR instructions
-  mixin (riscv_instr_mixin(CSRRW,  R_FORMAT, CSR, RV32I, UIMM));
-  mixin (riscv_instr_mixin(CSRRS,  R_FORMAT, CSR, RV32I, UIMM));
-  mixin (riscv_instr_mixin(CSRRC,  R_FORMAT, CSR, RV32I, UIMM));
-  mixin (riscv_instr_mixin(CSRRWI, I_FORMAT, CSR, RV32I, UIMM));
-  mixin (riscv_instr_mixin(CSRRSI, I_FORMAT, CSR, RV32I, UIMM));
-  mixin (riscv_instr_mixin(CSRRCI, I_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(CSRRW,  R_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(CSRRS,  R_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(CSRRC,  R_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(CSRRWI, I_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(CSRRSI, I_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(CSRRCI, I_FORMAT, CSR, RV32I, UIMM));
+
+  mixin (riscv_csr_instr_mixin(FRCSR,  R_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(FRFLAGS,  R_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(FRRM,  R_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(RDCYCLE,  R_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(RDCYCLEH,  R_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(RDINSTRET,  R_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(RDINSTRETH,  R_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(RDTIME,  R_FORMAT, CSR, RV32I, UIMM));
+  mixin (riscv_csr_instr_mixin(RDTIMEH,  R_FORMAT, CSR, RV32I, UIMM));
  }
  else {
    // LOAD instructions
@@ -178,15 +193,23 @@ version (RISCV_INSTR_STRING_MIXIN) {
    { mixin RISCV_INSTR_MIXIN!(FENCE,  I_FORMAT, SYNCH, RV32I); }
    class riscv_FENCE_I_instr: riscv_instr
    { mixin RISCV_INSTR_MIXIN!(FENCE_I, I_FORMAT, SYNCH, RV32I); }
+   class riscv_FENCE_TSO_instr: riscv_instr
+   { mixin RISCV_INSTR_MIXIN!(FENCE_TSO, I_FORMAT, SYNCH, RV32I); }
+   class riscv_PAUSE_instr: riscv_instr
+   { mixin RISCV_INSTR_MIXIN!(PAUSE, I_FORMAT, SYNCH, RV32I); }
    class riscv_SFENCE_VMA_instr: riscv_instr
    { mixin RISCV_INSTR_MIXIN!(SFENCE_VMA, R_FORMAT, SYNCH, RV32I); }
    // SYSTEM instructions
    class riscv_ECALL_instr: riscv_instr
    { mixin RISCV_INSTR_MIXIN!(ECALL,   I_FORMAT, SYSTEM, RV32I); }
+   class riscv_SCALL_instr: riscv_instr
+   { mixin RISCV_INSTR_MIXIN!(SCALL,   I_FORMAT, SYSTEM, RV32I); }
    class riscv_EBREAK_instr: riscv_instr
    { mixin RISCV_INSTR_MIXIN!(EBREAK,  I_FORMAT, SYSTEM, RV32I); }
-   class riscv_URET_instr: riscv_instr
-   { mixin RISCV_INSTR_MIXIN!(URET,    I_FORMAT, SYSTEM, RV32I); }
+   class riscv_SBREAK_instr: riscv_instr
+   { mixin RISCV_INSTR_MIXIN!(SBREAK,  I_FORMAT, SYSTEM, RV32I); }
+   // class riscv_URET_instr: riscv_instr -- deprecated
+   // { mixin RISCV_INSTR_MIXIN!(URET,    I_FORMAT, SYSTEM, RV32I); }
    class riscv_SRET_instr: riscv_instr
    { mixin RISCV_INSTR_MIXIN!(SRET,    I_FORMAT, SYSTEM, RV32I); }
    class riscv_MRET_instr: riscv_instr
@@ -196,16 +219,48 @@ version (RISCV_INSTR_STRING_MIXIN) {
    class riscv_WFI_instr: riscv_instr
    { mixin RISCV_INSTR_MIXIN!(WFI,     I_FORMAT, INTERRUPT, RV32I); }
    // CSR instructions
-   class riscv_CSRRW_instr: riscv_instr
+   class riscv_CSRRW_instr: riscv_csr_instr
    { mixin RISCV_INSTR_MIXIN!(CSRRW,  R_FORMAT, CSR, RV32I, UIMM); }
-   class riscv_CSRRS_instr: riscv_instr
+   class riscv_CSRRS_instr: riscv_csr_instr
    { mixin RISCV_INSTR_MIXIN!(CSRRS,  R_FORMAT, CSR, RV32I, UIMM); }
-   class riscv_CSRRC_instr: riscv_instr
+   class riscv_CSRRC_instr: riscv_csr_instr
    { mixin RISCV_INSTR_MIXIN!(CSRRC,  R_FORMAT, CSR, RV32I, UIMM); }
-   class riscv_CSRRWI_instr: riscv_instr
+   class riscv_CSRRWI_instr: riscv_csr_instr
    { mixin RISCV_INSTR_MIXIN!(CSRRWI, I_FORMAT, CSR, RV32I, UIMM); }
-   class riscv_CSRRSI_instr: riscv_instr
+   class riscv_CSRRSI_instr: riscv_csr_instr
    { mixin RISCV_INSTR_MIXIN!(CSRRSI, I_FORMAT, CSR, RV32I, UIMM); }
-   class riscv_CSRRCI_instr: riscv_instr
+   class riscv_CSRRCI_instr: riscv_csr_instr
    { mixin RISCV_INSTR_MIXIN!(CSRRCI, I_FORMAT, CSR, RV32I, UIMM); }
+
+   class riscv_FSCSR_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(FSCSR,  R_FORMAT, CSR, RV32I, UIMM); }
+   class riscv_FSFLAGS_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(FSFLAGS,  R_FORMAT, CSR, RV32I, UIMM); }
+   class riscv_FSRM_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(FSRM,  R_FORMAT, CSR, RV32I, UIMM); }
+
+   class riscv_FRCSR_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(FRCSR,  R_FORMAT, CSR, RV32I, UIMM); }
+   class riscv_FRFLAGS_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(FRFLAGS,  R_FORMAT, CSR, RV32I, UIMM); }
+   class riscv_FRRM_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(FRRM,  R_FORMAT, CSR, RV32I, UIMM); }
+   class riscv_RDCYCLE_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(RDCYCLE,  R_FORMAT, CSR, RV32I, UIMM); }
+   class riscv_RDCYCLEH_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(RDCYCLEH,  R_FORMAT, CSR, RV32I, UIMM); }
+   class riscv_RDINSTRET_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(RDINSTRET,  R_FORMAT, CSR, RV32I, UIMM); }
+   class riscv_RDINSTRETH_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(RDINSTRETH,  R_FORMAT, CSR, RV32I, UIMM); }
+   class riscv_RDTIME_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(RDTIME,  R_FORMAT, CSR, RV32I, UIMM); }
+   class riscv_RDTIMEH_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(RDTIMEH,  R_FORMAT, CSR, RV32I, UIMM); }
+
+   class riscv_FSFLAGSI_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(FSFLAGSI, I_FORMAT, CSR, RV32I, UIMM); }
+   class riscv_FSRMI_instr: riscv_csr_instr
+   { mixin RISCV_INSTR_MIXIN!(FSRMI, I_FORMAT, CSR, RV32I, UIMM); }
+   
  }
diff --git a/euvm/riscv/gen/isa/rv32m_instr.d b/euvm/riscv/gen/isa/rv32m_instr.d
index 87f07fc1..91937145 100644
--- a/euvm/riscv/gen/isa/rv32m_instr.d
+++ b/euvm/riscv/gen/isa/rv32m_instr.d
@@ -17,6 +17,7 @@
 module riscv.gen.isa.rv32m_instr;
 
 import riscv.gen.riscv_defines;
+import riscv.gen.isa.riscv_instr: riscv_instr;
 
 import uvm;
 
diff --git a/euvm/riscv/gen/isa/rv32v_instr.d b/euvm/riscv/gen/isa/rv32v_instr.d
index 8352bfbd..cb81b8d4 100644
--- a/euvm/riscv/gen/isa/rv32v_instr.d
+++ b/euvm/riscv/gen/isa/rv32v_instr.d
@@ -19,12 +19,14 @@
 module riscv.gen.isa.rv32v_instr;
 
 import riscv.gen.riscv_defines;
+import riscv.gen.isa.riscv_instr: riscv_instr;
 
 import uvm;
 
 version (RISCV_INSTR_STRING_MIXIN) {
   // Vector CSR access instruction
-  mixin (riscv_instr_mixin(VSETVLI,    VSET_FORMAT, CSR, RVV));
+  mixin (riscv_instr_mixin(SETVLI,    VSET_FORMAT, CSR, RVV));
+  mixin (riscv_instr_mixin(VSETIVLI,    VSET_FORMAT, CSR, RVV));
   mixin (riscv_instr_mixin(VSETVL,     VSET_FORMAT, CSR, RVV));
 
   // Vector integer arithmetic instruction
@@ -122,6 +124,7 @@ version (RISCV_INSTR_STRING_MIXIN) {
   mixin (riscv_va_instr_mixin(VFWMSAC,  VA_FORMAT, ARITHMETIC, RVV, [VV, VF]));
   mixin (riscv_va_instr_mixin(VFWNMSAC, VA_FORMAT, ARITHMETIC, RVV, [VV, VF]));
   mixin (riscv_va_instr_mixin(VFSQRT_V, VS2_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VFRSQRT7_V, VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFMIN,    VA_FORMAT, ARITHMETIC, RVV, [VV, VF]));
   mixin (riscv_va_instr_mixin(VFMAX,    VA_FORMAT, ARITHMETIC, RVV, [VV, VF]));
   mixin (riscv_va_instr_mixin(VFSGNJ,   VA_FORMAT, ARITHMETIC, RVV, [VV, VF]));
@@ -134,21 +137,28 @@ version (RISCV_INSTR_STRING_MIXIN) {
   mixin (riscv_va_instr_mixin(VMFGT,    VA_FORMAT, COMPARE, RVV, [VF]));
   mixin (riscv_va_instr_mixin(VMFGE,    VA_FORMAT, COMPARE, RVV, [VF]));
   mixin (riscv_va_instr_mixin(VFCLASS_V,VS2_FORMAT, COMPARE, RVV));
+  mixin (riscv_va_instr_mixin(VFREC7_V, VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFMERGE,  VA_FORMAT, ARITHMETIC, RVV, [VFM]));
   mixin (riscv_va_instr_mixin(VFMV,     VA_FORMAT, ARITHMETIC, RVV, [VF]));
 
   // Vector conversion instructions
   mixin (riscv_va_instr_mixin(VFCVT_XU_F_V,     VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFCVT_X_F_V,      VS2_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VFCVT_RTZ_XU_F_V, VS2_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VFCVT_RTZ_X_F_V,  VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFCVT_F_XU_V,     VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFCVT_F_X_V,      VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFWCVT_XU_F_V,    VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFWCVT_X_F_V,     VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFWCVT_F_XU_V,    VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFWCVT_F_X_V,     VS2_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VFWCVT_RTZ_XU_F_V,    VS2_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VFWCVT_RTZ_X_F_V,     VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFWCVT_F_F_V,     VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFNCVT_XU_F_W,    VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFNCVT_X_F_W,     VS2_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VFNCVT_RTZ_XU_F_W,VS2_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VFNCVT_RTZ_X_F_W, VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFNCVT_F_XU_W,    VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFNCVT_F_X_W,     VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFNCVT_F_F_W,     VS2_FORMAT, ARITHMETIC, RVV));
@@ -166,22 +176,28 @@ version (RISCV_INSTR_STRING_MIXIN) {
   mixin (riscv_va_instr_mixin(VWREDSUMU_VS,  VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VWREDSUM_VS,   VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFREDOSUM_VS,  VA_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VFREDUSUM_VS,  VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFREDSUM_VS,   VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFREDMAX_VS,   VA_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VFREDMIN_VS,   VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFWREDOSUM_VS, VA_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VFWREDUSUM_VS, VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFWREDSUM_VS,  VA_FORMAT, ARITHMETIC, RVV));
 
   // Vector mask instruction
   mixin (riscv_va_instr_mixin(VMAND_MM,    VA_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VMANDN_MM,    VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VMNAND_MM,   VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VMANDNOT_MM, VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VMXOR_MM,    VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VMOR_MM,     VA_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VMORN_MM,     VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VMNOR_MM,    VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VMORNOT_MM,  VA_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VMXNOR_MM,   VA_FORMAT, ARITHMETIC, RVV));
 
   mixin (riscv_va_instr_mixin(VPOPC_M,   VS2_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VCPOP_M,   VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VFIRST_M,  VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VMSBF_M,   VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VMSIF_M,   VS2_FORMAT, ARITHMETIC, RVV));
@@ -199,6 +215,8 @@ version (RISCV_INSTR_STRING_MIXIN) {
   mixin (riscv_va_instr_mixin(VSLIDEDOWN,  VA_FORMAT, ARITHMETIC, RVV, [VI, VX]));
   mixin (riscv_va_instr_mixin(VSLIDE1UP,   VA_FORMAT, ARITHMETIC, RVV, [VX]));
   mixin (riscv_va_instr_mixin(VSLIDE1DOWN, VA_FORMAT, ARITHMETIC, RVV, [VX]));
+  mixin (riscv_va_instr_mixin(VFSLIDE1UP,   VA_FORMAT, ARITHMETIC, RVV, [VF]));
+  mixin (riscv_va_instr_mixin(VFSLIDE1DOWN, VA_FORMAT, ARITHMETIC, RVV, [VF]));
   mixin (riscv_va_instr_mixin(VRGATHER,    VA_FORMAT, ARITHMETIC, RVV, [VV, VX, VI]));
   mixin (riscv_va_instr_mixin(VCOMPRESS,   VA_FORMAT, ARITHMETIC, RVV, [VM]));
 
@@ -207,12 +225,19 @@ version (RISCV_INSTR_STRING_MIXIN) {
   mixin (riscv_va_instr_mixin(VMV4R_V, VS2_FORMAT, ARITHMETIC, RVV));
   mixin (riscv_va_instr_mixin(VMV8R_V, VS2_FORMAT, ARITHMETIC, RVV));
 
+  mixin (riscv_va_instr_mixin(VS1R_V, VS2_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VS2R_V, VS2_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VS4R_V, VS2_FORMAT, ARITHMETIC, RVV));
+  mixin (riscv_va_instr_mixin(VS8R_V, VS2_FORMAT, ARITHMETIC, RVV));
+
   // -------------------------------------------------------------------------
   //  Section 7. Vector Loads and Stores
   // -------------------------------------------------------------------------
   // Section 7.4 - Vector Unit-Stride Instructions
-  mixin (riscv_va_instr_mixin(VLE_V, VL_FORMAT, LOAD, RVV));
-  mixin (riscv_va_instr_mixin(VSE_V, VS_FORMAT, STORE, RVV));
+
+  //   mixin (riscv_va_instr_mixin(VLM_V, VL_FORMAT, LOAD, RVV));   // mismatch with riscv-opcodes
+  //   mixin (riscv_va_instr_mixin(VSM_V, VS_FORMAT, STORE, RVV));  // mismatch with riscv-opcodes
+
   // Section 7.5 - Vector Strided Instructions
   mixin (riscv_va_instr_mixin(VLSE_V, VLS_FORMAT, LOAD, RVV));
   mixin (riscv_va_instr_mixin(VSSE_V, VSS_FORMAT, STORE, RVV));
@@ -253,414 +278,646 @@ version (RISCV_INSTR_STRING_MIXIN) {
    // Vector CSR access instruction
    class riscv_VSETVLI_instr: riscv_instr
    { mixin RISCV_INSTR_MIXIN!(VSETVLI,    VSET_FORMAT, CSR, RVV); }
+   class riscv_VSETIVLI_instr: riscv_instr
+   { mixin RISCV_INSTR_MIXIN!(VSETIVLI,   VSET_FORMAT, CSR, RVV); }
    class riscv_VSETVL_instr: riscv_instr
    { mixin RISCV_INSTR_MIXIN!(VSETVL,     VSET_FORMAT, CSR, RVV); }
 
    // Vector integer arithmetic instruction
-   class riscv_VADD_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VADD,     VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
-   class riscv_VSUB_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSUB,     VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VRSUB_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VRSUB,    VA_FORMAT, ARITHMETIC, RVV, VX, VI); }
-   class riscv_VWADDU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VWADDU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); }
-   class riscv_VWSUBU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VWSUBU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); }
-   class riscv_VWADD_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VWADD,    VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); }
-   class riscv_VWSUB_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VWSUB,    VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); }
-   class riscv_VADC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VADC,     VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VIM); }
-   class riscv_VMADC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMADC,    VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VIM, VV, VX, VI); }
-   class riscv_VSBC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSBC,     VA_FORMAT, ARITHMETIC, RVV, VVM, VXM); }
-   class riscv_VMSBC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMSBC,    VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VV, VX); }
-   class riscv_VAND_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VAND,     VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
-   class riscv_VOR_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VOR,      VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
-   class riscv_VXOR_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VXOR,     VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
-   class riscv_VSLL_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSLL,     VA_FORMAT, SHIFT, RVV, VV, VX, VI); }
-   class riscv_VSRL_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSRL,     VA_FORMAT, SHIFT, RVV, VV, VX, VI); }
-   class riscv_VSRA_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSRA,     VA_FORMAT, SHIFT, RVV, VV, VX, VI); }
-   class riscv_VNSRL_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VNSRL,    VA_FORMAT, SHIFT, RVV, WV, WX, WI); }
-   class riscv_VNSRA_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VNSRA,    VA_FORMAT, SHIFT, RVV, WV, WX, WI); }
-   class riscv_VMSEQ_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMSEQ,    VA_FORMAT, COMPARE, RVV, VV, VX, VI); }
-   class riscv_VMSNE_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMSNE,    VA_FORMAT, COMPARE, RVV, VV, VX, VI); }
-   class riscv_VMSLTU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMSLTU,   VA_FORMAT, COMPARE, RVV, VV, VX); }
-   class riscv_VMSLT_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMSLT,    VA_FORMAT, COMPARE, RVV, VV, VX); }
-   class riscv_VMSLEU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMSLEU,   VA_FORMAT, COMPARE, RVV, VV, VX, VI); }
-   class riscv_VMSLE_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMSLE,    VA_FORMAT, COMPARE, RVV, VV, VX, VI); }
-   class riscv_VMSGTU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMSGTU,   VA_FORMAT, COMPARE, RVV, VX, VI); }
-   class riscv_VMSGT_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMSGT,    VA_FORMAT, COMPARE, RVV, VX, VI); }
-   class riscv_VMINU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMINU,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VMIN_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMIN,     VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VMAXU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMAXU,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VMAX_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMAX,     VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VMUL_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMUL,     VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VMULH_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMULH,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VMULHU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMULHU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VMULHSU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMULHSU,  VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VDIVU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VDIVU,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VDIV_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VDIV,     VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VREMU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VREMU,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VREM_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VREM,     VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VWMUL_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VWMUL,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VWMULU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VWMULU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VWMULSU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VWMULSU,  VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VMACC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMACC,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VNMSAC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VNMSAC,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VMADD_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMADD,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VNMSUB_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VNMSUB,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VWMACCU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VWMACCU,  VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VWMACC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VWMACC,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VWMACCSU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VWMACCSU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VWMACCUS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VWMACCUS, VA_FORMAT, ARITHMETIC, RVV, VX); }
-   /* Quad widening is not yet supported
-      class riscv_VQMACCU_instr: riscv_vector_instr
-      { mixin RISCV_VA_INSTR_MIXIN!(VQMACCU,  VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-      class riscv_VQMACC_instr: riscv_vector_instr
-      { mixin RISCV_VA_INSTR_MIXIN!(VQMACC,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-      class riscv_VQMACCSU_instr: riscv_vector_instr
-      { mixin RISCV_VA_INSTR_MIXIN!(VQMACCSU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-      class riscv_VQMACCUS_instr: riscv_vector_instr
-      { mixin RISCV_VA_INSTR_MIXIN!(VQMACCUS, VA_FORMAT, ARITHMETIC, RVV, VX); }
-   */
-   class riscv_VMERGE_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMERGE,   VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VIM); }
-   class riscv_VMV_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMV,      VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
+   // class riscv_VADD_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VADD,     VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
+   class riscv_VADD_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VADD
+   class riscv_VADD_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VADD_VX, VA_FORMAT, ARITHMETIC, RVV); } // VADD
+   class riscv_VADD_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VADD_VI, VA_FORMAT, ARITHMETIC, RVV); } // VADD
+   // class riscv_VSUB_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSUB,     VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VSUB_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VSUB
+   class riscv_VSUB_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSUB_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSUB
+   // class riscv_VRSUB_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VRSUB,    VA_FORMAT, ARITHMETIC, RVV, VX, VI); }
+   class riscv_VRSUB_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VRSUB_VX, VA_FORMAT, ARITHMETIC, RVV); } // VRSUB
+   class riscv_VRSUB_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VRSUB_VI, VA_FORMAT, ARITHMETIC, RVV); } // VRSUB
+   // class riscv_VWADDU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VWADDU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); }
+   class riscv_VWADDU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWADDU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWADDU
+   class riscv_VWADDU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWADDU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWADDU
+   class riscv_VWADDU_WV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWADDU_WV, VA_FORMAT, ARITHMETIC, RVV); } // VWADDU
+   class riscv_VWADDU_WX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWADDU_WX, VA_FORMAT, ARITHMETIC, RVV); } // VWADDU
+   // class riscv_VWSUBU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VWSUBU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); }
+   class riscv_VWSUBU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWSUBU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWSUBU
+   class riscv_VWSUBU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWSUBU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWSUBU
+   class riscv_VWSUBU_WV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWSUBU_WV, VA_FORMAT, ARITHMETIC, RVV); } // VWSUBU
+   class riscv_VWSUBU_WX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWSUBU_WX, VA_FORMAT, ARITHMETIC, RVV); } // VWSUBU
+   // class riscv_VWADD_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VWADD,    VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); }
+   class riscv_VWADD_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWADD
+   class riscv_VWADD_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWADD_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWADD
+   class riscv_VWADD_WV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWADD_WV, VA_FORMAT, ARITHMETIC, RVV); } // VWADD
+   class riscv_VWADD_WX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWADD_WX, VA_FORMAT, ARITHMETIC, RVV); } // VWADD
+   // class riscv_VWSUB_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VWSUB,    VA_FORMAT, ARITHMETIC, RVV, VV, VX, WV, WX); }
+   class riscv_VWSUB_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWSUB
+   class riscv_VWSUB_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWSUB_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWSUB
+   class riscv_VWSUB_WV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWSUB_WV, VA_FORMAT, ARITHMETIC, RVV); } // VWSUB
+   class riscv_VWSUB_WX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWSUB_WX, VA_FORMAT, ARITHMETIC, RVV); } // VWSUB
+   // class riscv_VADC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VADC,     VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VIM); }
+   class riscv_VADC_VVM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VADC_VVM, VA_FORMAT, ARITHMETIC, RVV); } // VADC
+   class riscv_VADC_VXM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VADC_VXM, VA_FORMAT, ARITHMETIC, RVV); } // VADC
+   class riscv_VADC_VIM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VADC_VIM, VA_FORMAT, ARITHMETIC, RVV); } // VADC
+   // class riscv_VMADC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMADC,    VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VIM, VV, VX, VI); }
+   class riscv_VMADC_VVM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMADC_VVM, VA_FORMAT, ARITHMETIC, RVV); } // VMADC
+   class riscv_VMADC_VXM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMADC_VXM, VA_FORMAT, ARITHMETIC, RVV); } // VMADC
+   class riscv_VMADC_VIM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMADC_VIM, VA_FORMAT, ARITHMETIC, RVV); } // VMADC
+   class riscv_VMADC_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMADC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMADC
+   class riscv_VMADC_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMADC_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMADC
+   class riscv_VMADC_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMADC_VI, VA_FORMAT, ARITHMETIC, RVV); } // VMADC
+   // class riscv_VSBC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSBC,     VA_FORMAT, ARITHMETIC, RVV, VVM, VXM); }
+   class riscv_VSBC_VVM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSBC_VVM, VA_FORMAT, ARITHMETIC, RVV); } // VSBC
+   class riscv_VSBC_VXM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSBC_VXM, VA_FORMAT, ARITHMETIC, RVV); } // VSBC
+   // class riscv_VMSBC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMSBC,    VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VV, VX); }
+   class riscv_VMSBC_VVM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSBC_VVM, VA_FORMAT, ARITHMETIC, RVV); } // VMSBC
+   class riscv_VMSBC_VXM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSBC_VXM, VA_FORMAT, ARITHMETIC, RVV); } // VMSBC
+   class riscv_VMSBC_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSBC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMSBC
+   class riscv_VMSBC_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSBC_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMSBC
+   // class riscv_VAND_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VAND,     VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
+   class riscv_VAND_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VAND_VV, VA_FORMAT, ARITHMETIC, RVV); } // VAND
+   class riscv_VAND_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VAND_VX, VA_FORMAT, ARITHMETIC, RVV); } // VAND
+   class riscv_VAND_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VAND_VI, VA_FORMAT, ARITHMETIC, RVV); } // VAND
+   // class riscv_VOR_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VOR,      VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
+   class riscv_VOR_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VOR_VV, VA_FORMAT, ARITHMETIC, RVV); } // VOR
+   class riscv_VOR_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VOR_VX, VA_FORMAT, ARITHMETIC, RVV); } // VOR
+   class riscv_VOR_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VOR_VI, VA_FORMAT, ARITHMETIC, RVV); } // VOR
+   // class riscv_VXOR_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VXOR,     VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
+   class riscv_VXOR_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VXOR_VV, VA_FORMAT, ARITHMETIC, RVV); } // VXOR
+   class riscv_VXOR_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VXOR_VX, VA_FORMAT, ARITHMETIC, RVV); } // VXOR
+   class riscv_VXOR_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VXOR_VI, VA_FORMAT, ARITHMETIC, RVV); } // VXOR
+   // class riscv_VSLL_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSLL,     VA_FORMAT, SHIFT, RVV, VV, VX, VI); }
+   class riscv_VSLL_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSLL_VV, VA_FORMAT, SHIFT, RVV); } // VSLL
+   class riscv_VSLL_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSLL_VX, VA_FORMAT, SHIFT, RVV); } // VSLL
+   class riscv_VSLL_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSLL_VI, VA_FORMAT, SHIFT, RVV); } // VSLL
+   // class riscv_VSRL_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSRL,     VA_FORMAT, SHIFT, RVV, VV, VX, VI); }
+   class riscv_VSRL_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSRL_VV, VA_FORMAT, SHIFT, RVV); } // VSRL
+   class riscv_VSRL_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSRL_VX, VA_FORMAT, SHIFT, RVV); } // VSRL
+   class riscv_VSRL_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSRL_VI, VA_FORMAT, SHIFT, RVV); } // VSRL
+   // class riscv_VSRA_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSRA,     VA_FORMAT, SHIFT, RVV, VV, VX, VI); }
+   class riscv_VSRA_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSRA_VV, VA_FORMAT, SHIFT, RVV); } // VSRA
+   class riscv_VSRA_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSRA_VX, VA_FORMAT, SHIFT, RVV); } // VSRA
+   class riscv_VSRA_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSRA_VI, VA_FORMAT, SHIFT, RVV); } // VSRA
+   // class riscv_VNSRL_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VNSRL,    VA_FORMAT, SHIFT, RVV, WV, WX, WI); }
+   class riscv_VNSRL_WV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNSRL_WV, VA_FORMAT, SHIFT, RVV); } // VNSRL
+   class riscv_VNSRL_WX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNSRL_WX, VA_FORMAT, SHIFT, RVV); } // VNSRL
+   class riscv_VNSRL_WI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNSRL_WI, VA_FORMAT, SHIFT, RVV); } // VNSRL
+   // class riscv_VNSRA_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VNSRA,    VA_FORMAT, SHIFT, RVV, WV, WX, WI); }
+   class riscv_VNSRA_WV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNSRA_WV, VA_FORMAT, SHIFT, RVV); } // VNSRA
+   class riscv_VNSRA_WX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNSRA_WX, VA_FORMAT, SHIFT, RVV); } // VNSRA
+   class riscv_VNSRA_WI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNSRA_WI, VA_FORMAT, SHIFT, RVV); } // VNSRA
+   // class riscv_VMSEQ_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMSEQ,    VA_FORMAT, COMPARE, RVV, VV, VX, VI); }
+   class riscv_VMSEQ_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSEQ_VV, VA_FORMAT, COMPARE, RVV); } // VMSEQ
+   class riscv_VMSEQ_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSEQ_VX, VA_FORMAT, COMPARE, RVV); } // VMSEQ
+   class riscv_VMSEQ_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSEQ_VI, VA_FORMAT, COMPARE, RVV); } // VMSEQ
+   // class riscv_VMSNE_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMSNE,    VA_FORMAT, COMPARE, RVV, VV, VX, VI); }
+   class riscv_VMSNE_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSNE_VV, VA_FORMAT, COMPARE, RVV); } // VMSNE
+   class riscv_VMSNE_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSNE_VX, VA_FORMAT, COMPARE, RVV); } // VMSNE
+   class riscv_VMSNE_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSNE_VI, VA_FORMAT, COMPARE, RVV); } // VMSNE
+   // class riscv_VMSLTU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMSLTU,   VA_FORMAT, COMPARE, RVV, VV, VX); }
+   class riscv_VMSLTU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSLTU_VV, VA_FORMAT, COMPARE, RVV); } // VMSLTU
+   class riscv_VMSLTU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSLTU_VX, VA_FORMAT, COMPARE, RVV); } // VMSLTU
+   // class riscv_VMSLT_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMSLT,    VA_FORMAT, COMPARE, RVV, VV, VX); }
+   class riscv_VMSLT_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSLT_VV, VA_FORMAT, COMPARE, RVV); } // VMSLT
+   class riscv_VMSLT_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSLT_VX, VA_FORMAT, COMPARE, RVV); } // VMSLT
+   // class riscv_VMSLEU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMSLEU,   VA_FORMAT, COMPARE, RVV, VV, VX, VI); }
+   class riscv_VMSLEU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSLEU_VV, VA_FORMAT, COMPARE, RVV); } // VMSLEU
+   class riscv_VMSLEU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSLEU_VX, VA_FORMAT, COMPARE, RVV); } // VMSLEU
+   class riscv_VMSLEU_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSLEU_VI, VA_FORMAT, COMPARE, RVV); } // VMSLEU
+   // class riscv_VMSLE_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMSLE,    VA_FORMAT, COMPARE, RVV, VV, VX, VI); }
+   class riscv_VMSLE_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSLE_VV, VA_FORMAT, COMPARE, RVV); } // VMSLE
+   class riscv_VMSLE_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSLE_VX, VA_FORMAT, COMPARE, RVV); } // VMSLE
+   class riscv_VMSLE_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSLE_VI, VA_FORMAT, COMPARE, RVV); } // VMSLE
+   // class riscv_VMSGTU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMSGTU,   VA_FORMAT, COMPARE, RVV, VX, VI); }
+   class riscv_VMSGTU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSGTU_VX, VA_FORMAT, COMPARE, RVV); } // VMSGTU
+   class riscv_VMSGTU_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSGTU_VI, VA_FORMAT, COMPARE, RVV); } // VMSGTU
+   // class riscv_VMSGT_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMSGT,    VA_FORMAT, COMPARE, RVV, VX, VI); }
+   class riscv_VMSGT_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSGT_VX, VA_FORMAT, COMPARE, RVV); } // VMSGT
+   class riscv_VMSGT_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSGT_VI, VA_FORMAT, COMPARE, RVV); } // VMSGT
+   // class riscv_VMINU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMINU,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VMINU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMINU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMINU
+   class riscv_VMINU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMINU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMINU
+   // class riscv_VMIN_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMIN,     VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VMIN_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMIN_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMIN
+   class riscv_VMIN_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMIN_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMIN
+   // class riscv_VMAXU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMAXU,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VMAXU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMAXU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMAXU
+   class riscv_VMAXU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMAXU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMAXU
+   // class riscv_VMAX_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMAX,     VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VMAX_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMAX_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMAX
+   class riscv_VMAX_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMAX_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMAX
+   // class riscv_VMUL_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMUL,     VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VMUL_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMUL_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMUL
+   class riscv_VMUL_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMUL_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMUL
+   // class riscv_VMULH_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMULH,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VMULH_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMULH_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMULH
+   class riscv_VMULH_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMULH_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMULH
+   // class riscv_VMULHU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMULHU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VMULHU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMULHU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMULHU
+   class riscv_VMULHU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMULHU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMULHU
+   // class riscv_VMULHSU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMULHSU,  VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VMULHSU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMULHSU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMULHSU
+   class riscv_VMULHSU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMULHSU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMULHSU
+   // class riscv_VDIVU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VDIVU,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VDIVU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VDIVU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VDIVU
+   class riscv_VDIVU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VDIVU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VDIVU
+   // class riscv_VDIV_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VDIV,     VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VDIV_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VDIV_VV, VA_FORMAT, ARITHMETIC, RVV); } // VDIV
+   class riscv_VDIV_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VDIV_VX, VA_FORMAT, ARITHMETIC, RVV); } // VDIV
+   // class riscv_VREMU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VREMU,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VREMU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VREMU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VREMU
+   class riscv_VREMU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VREMU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VREMU
+   // class riscv_VREM_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VREM,     VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VREM_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VREM_VV, VA_FORMAT, ARITHMETIC, RVV); } // VREM
+   class riscv_VREM_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VREM_VX, VA_FORMAT, ARITHMETIC, RVV); } // VREM
+   // class riscv_VWMUL_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VWMUL,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VWMUL_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWMUL_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWMUL
+   class riscv_VWMUL_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWMUL_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMUL
+   // class riscv_VWMULU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VWMULU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VWMULU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWMULU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWMULU
+   class riscv_VWMULU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWMULU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMULU
+   // class riscv_VWMULSU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VWMULSU,  VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VWMULSU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWMULSU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWMULSU
+   class riscv_VWMULSU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWMULSU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMULSU
+   // class riscv_VMACC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMACC,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VMACC_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMACC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMACC
+   class riscv_VMACC_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMACC_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMACC
+   // class riscv_VNMSAC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VNMSAC,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VNMSAC_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNMSAC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VNMSAC
+   class riscv_VNMSAC_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNMSAC_VX, VA_FORMAT, ARITHMETIC, RVV); } // VNMSAC
+   // class riscv_VMADD_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMADD,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VMADD_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VMADD
+   class riscv_VMADD_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMADD_VX, VA_FORMAT, ARITHMETIC, RVV); } // VMADD
+   // class riscv_VNMSUB_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VNMSUB,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VNMSUB_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNMSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VNMSUB
+   class riscv_VNMSUB_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNMSUB_VX, VA_FORMAT, ARITHMETIC, RVV); } // VNMSUB
+   // class riscv_VWMACCU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VWMACCU,  VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VWMACCU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWMACCU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWMACCU
+   class riscv_VWMACCU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWMACCU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMACCU
+   // class riscv_VWMACC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VWMACC,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VWMACC_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWMACC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWMACC
+   class riscv_VWMACC_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWMACC_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMACC
+   // class riscv_VWMACCSU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VWMACCSU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VWMACCSU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWMACCSU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VWMACCSU
+   class riscv_VWMACCSU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWMACCSU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMACCSU
+   // class riscv_VWMACCUS_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VWMACCUS, VA_FORMAT, ARITHMETIC, RVV, VX); }
+   class riscv_VWMACCUS_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWMACCUS_VX, VA_FORMAT, ARITHMETIC, RVV); } // VWMACCUS
+   // /* Quad widening is not yet supported
+   //    class riscv_VQMACCU_instr: riscv_vector_instr   //    { mixin RISCV_VA_INSTR_MIXIN!(VQMACCU,  VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   //    class riscv_VQMACC_instr: riscv_vector_instr   //    { mixin RISCV_VA_INSTR_MIXIN!(VQMACC,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   //    class riscv_VQMACCSU_instr: riscv_vector_instr   //    { mixin RISCV_VA_INSTR_MIXIN!(VQMACCSU, VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   //    class riscv_VQMACCUS_instr: riscv_vector_instr   //    { mixin RISCV_VA_INSTR_MIXIN!(VQMACCUS, VA_FORMAT, ARITHMETIC, RVV, VX); }
+   // */
+   // class riscv_VMERGE_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMERGE,   VA_FORMAT, ARITHMETIC, RVV, VVM, VXM, VIM); }
+   // class riscv_VMV_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMV,      VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
+   class riscv_VMERGE_VVM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMERGE_VVM, VA_FORMAT, ARITHMETIC, RVV); } // VMERGE
+   class riscv_VMERGE_VXM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMERGE_VXM, VA_FORMAT, ARITHMETIC, RVV); } // VMERGE
+   class riscv_VMERGE_VIM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMERGE_VIM, VA_FORMAT, ARITHMETIC, RVV); } // VMERGE
+   class riscv_VMV_V_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMV_V_V, VA_FORMAT, ARITHMETIC, RVV); } // VMV
+   class riscv_VMV_V_X_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMV_V_X, VA_FORMAT, ARITHMETIC, RVV); } // VMV
+   class riscv_VMV_V_I_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMV_V_I, VA_FORMAT, ARITHMETIC, RVV); } // VMV
 
    // Vector Fixed-Point Arithmetic Instructions
-   class riscv_VSADDU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSADDU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
-   class riscv_VSADD_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSADD,    VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
-   class riscv_VSSUBU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSSUBU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VSSUB_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSSUB,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VAADDU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VAADDU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VAADD_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VAADD,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VASUBU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VASUBU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VASUB_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VASUB,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
-   class riscv_VSSRL_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSSRL,    VA_FORMAT, SHIFT, RVV, VV, VX, VI); }
-   class riscv_VSSRA_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSSRA,    VA_FORMAT, SHIFT, RVV, VV, VX, VI); }
-   class riscv_VNCLIPU_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VNCLIPU,  VA_FORMAT, ARITHMETIC, RVV, WV, WX, WI); }
-   class riscv_VNCLIP_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VNCLIP,   VA_FORMAT, ARITHMETIC, RVV, WV, WX, WI); }
+   // class riscv_VSADDU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSADDU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
+   class riscv_VSADDU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSADDU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VSADDU
+   class riscv_VSADDU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSADDU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSADDU
+   class riscv_VSADDU_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSADDU_VI, VA_FORMAT, ARITHMETIC, RVV); } // VSADDU
+   // class riscv_VSADD_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSADD,    VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
+   class riscv_VSADD_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VSADD
+   class riscv_VSADD_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSADD_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSADD
+   class riscv_VSADD_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSADD_VI, VA_FORMAT, ARITHMETIC, RVV); } // VSADD
+   // class riscv_VSSUBU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSSUBU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VSSUBU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSUBU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VSSUBU
+   class riscv_VSSUBU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSUBU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSSUBU
+   // class riscv_VSSUB_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSSUB,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VSSUB_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VSSUB
+   class riscv_VSSUB_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSUB_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSSUB
+   // VSMUL
+   class riscv_VSMUL_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSMUL_VV, VA_FORMAT, ARITHMETIC, RVV); } // VSMUL
+   class riscv_VSMUL_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSMUL_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSMUL
+   // class riscv_VAADDU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VAADDU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VAADDU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VAADDU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VAADDU
+   class riscv_VAADDU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VAADDU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VAADDU
+   // class riscv_VAADD_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VAADD,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VAADD_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VAADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VAADD
+   class riscv_VAADD_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VAADD_VX, VA_FORMAT, ARITHMETIC, RVV); } // VAADD
+   // class riscv_VASUBU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VASUBU,   VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VASUBU_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VASUBU_VV, VA_FORMAT, ARITHMETIC, RVV); } // VASUBU
+   class riscv_VASUBU_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VASUBU_VX, VA_FORMAT, ARITHMETIC, RVV); } // VASUBU
+   // class riscv_VASUB_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VASUB,    VA_FORMAT, ARITHMETIC, RVV, VV, VX); }
+   class riscv_VASUB_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VASUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VASUB
+   class riscv_VASUB_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VASUB_VX, VA_FORMAT, ARITHMETIC, RVV); } // VASUB
+   // class riscv_VSSRL_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSSRL,    VA_FORMAT, SHIFT, RVV, VV, VX, VI); }
+   class riscv_VSSRL_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSRL_VV, VA_FORMAT, SHIFT, RVV); } // VSSRL
+   class riscv_VSSRL_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSRL_VX, VA_FORMAT, SHIFT, RVV); } // VSSRL
+   class riscv_VSSRL_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSRL_VI, VA_FORMAT, SHIFT, RVV); } // VSSRL
+   // class riscv_VSSRA_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSSRA,    VA_FORMAT, SHIFT, RVV, VV, VX, VI); }
+   class riscv_VSSRA_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSRA_VV, VA_FORMAT, SHIFT, RVV); } // VSSRA
+   class riscv_VSSRA_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSRA_VX, VA_FORMAT, SHIFT, RVV); } // VSSRA
+   class riscv_VSSRA_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSRA_VI, VA_FORMAT, SHIFT, RVV); } // VSSRA
+   // class riscv_VNCLIPU_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VNCLIPU,  VA_FORMAT, ARITHMETIC, RVV, WV, WX, WI); }
+   class riscv_VNCLIPU_WV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNCLIPU_WV, VA_FORMAT, ARITHMETIC, RVV); } // VNCLIPU
+   class riscv_VNCLIPU_WX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNCLIPU_WX, VA_FORMAT, ARITHMETIC, RVV); } // VNCLIPU
+   class riscv_VNCLIPU_WI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNCLIPU_WI, VA_FORMAT, ARITHMETIC, RVV); } // VNCLIPU
+   // class riscv_VNCLIP_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VNCLIP,   VA_FORMAT, ARITHMETIC, RVV, WV, WX, WI); }
+   class riscv_VNCLIP_WV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNCLIP_WV, VA_FORMAT, ARITHMETIC, RVV); } // VNCLIP
+   class riscv_VNCLIP_WX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNCLIP_WX, VA_FORMAT, ARITHMETIC, RVV); } // VNCLIP
+   class riscv_VNCLIP_WI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VNCLIP_WI, VA_FORMAT, ARITHMETIC, RVV); } // VNCLIP
 
    // Vector Floating-Point Instructions
-   class riscv_VFADD_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFADD,    VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFSUB_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFSUB,    VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFRSUB_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFRSUB,   VA_FORMAT, ARITHMETIC, RVV, VF); }
-   class riscv_VFMUL_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFMUL,    VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFDIV_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFDIV,    VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFRDIV_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFRDIV,   VA_FORMAT, ARITHMETIC, RVV, VF); }
-   class riscv_VFWMUL_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFWMUL,   VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFMACC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFMACC,   VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFNMACC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFNMACC,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFMSAC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFMSAC,   VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFNMSAC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFNMSAC,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFMADD_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFMADD,   VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFNMADD_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFNMADD,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFMSUB_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFMSUB,   VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFNMSUB_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFNMSUB,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFWMACC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFWMACC,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFWNMACC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFWNMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFWMSAC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFWMSAC,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFWNMSAC_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFWNMSAC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFSQRT_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFSQRT_V, VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFMIN_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFMIN,    VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFMAX_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFMAX,    VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFSGNJ_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJ,   VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFSGNJN_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJN,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VFSGNJX_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJX,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
-   class riscv_VMFEQ_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMFEQ,    VA_FORMAT, COMPARE, RVV, VV, VF); }
-   class riscv_VMFNE_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMFNE,    VA_FORMAT, COMPARE, RVV, VV, VF); }
-   class riscv_VMFLT_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMFLT,    VA_FORMAT, COMPARE, RVV, VV, VF); }
-   class riscv_VMFLE_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMFLE,    VA_FORMAT, COMPARE, RVV, VV, VF); }
-   class riscv_VMFGT_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMFGT,    VA_FORMAT, COMPARE, RVV, VF); }
-   class riscv_VMFGE_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMFGE,    VA_FORMAT, COMPARE, RVV, VF); }
-   class riscv_VFCLASS_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFCLASS_V,VS2_FORMAT, COMPARE, RVV); }
-   class riscv_VFMERGE_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFMERGE,  VA_FORMAT, ARITHMETIC, RVV, VFM); }
-   class riscv_VFMV_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFMV,     VA_FORMAT, ARITHMETIC, RVV, VF); }
+   // class riscv_VFADD_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFADD,    VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFADD_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFADD
+   class riscv_VFADD_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFADD_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFADD
+   // class riscv_VFSUB_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFSUB,    VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFSUB_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFSUB
+   class riscv_VFSUB_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFSUB_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFSUB
+   // class riscv_VFRSUB_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFRSUB,   VA_FORMAT, ARITHMETIC, RVV, VF); }
+   class riscv_VFRSUB_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFRSUB_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFRSUB
+   // class riscv_VFMUL_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFMUL,    VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFMUL_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMUL_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMUL
+   class riscv_VFMUL_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMUL_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMUL
+   // class riscv_VFDIV_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFDIV,    VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFDIV_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFDIV_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFDIV
+   class riscv_VFDIV_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFDIV_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFDIV
+   // class riscv_VFRDIV_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFRDIV,   VA_FORMAT, ARITHMETIC, RVV, VF); }
+   class riscv_VFRDIV_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFRDIV_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFRDIV
+   // class riscv_VFWMUL_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFWMUL,   VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFWMUL_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWMUL_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFWMUL
+   class riscv_VFWMUL_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWMUL_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFWMUL
+   // class riscv_VFMACC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFMACC,   VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFMACC_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMACC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMACC
+   class riscv_VFMACC_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMACC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMACC
+   // class riscv_VFNMACC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFNMACC,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFNMACC_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNMACC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFNMACC
+   class riscv_VFNMACC_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNMACC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFNMACC
+   // class riscv_VFMSAC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFMSAC,   VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFMSAC_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMSAC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMSAC
+   class riscv_VFMSAC_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMSAC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMSAC
+   // class riscv_VFNMSAC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFNMSAC,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFNMSAC_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNMSAC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFNMSAC
+   class riscv_VFNMSAC_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNMSAC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFNMSAC
+   // class riscv_VFMADD_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFMADD,   VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFMADD_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMADD
+   class riscv_VFMADD_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMADD_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMADD
+   // class riscv_VFNMADD_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFNMADD,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFNMADD_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNMADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFNMADD
+   class riscv_VFNMADD_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNMADD_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFNMADD
+   // class riscv_VFMSUB_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFMSUB,   VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFMSUB_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMSUB
+   class riscv_VFMSUB_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMSUB_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMSUB
+   // class riscv_VFNMSUB_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFNMSUB,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFNMSUB_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNMSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFNMSUB
+   class riscv_VFNMSUB_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNMSUB_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFNMSUB
+   // class riscv_VFWMACC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFWMACC,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFWMACC_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWMACC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFWMACC
+   class riscv_VFWMACC_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWMACC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFWMACC
+   // class riscv_VFWNMACC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFWNMACC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFWNMACC_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWNMACC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFWNMACC
+   class riscv_VFWNMACC_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWNMACC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFWNMACC
+   // class riscv_VFWMSAC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFWMSAC,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFWMSAC_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWMSAC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFWMSAC
+   class riscv_VFWMSAC_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWMSAC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFWMSAC
+   // class riscv_VFWNMSAC_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFWNMSAC, VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFWNMSAC_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWNMSAC_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFWNMSAC
+   class riscv_VFWNMSAC_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWNMSAC_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFWNMSAC
+
+   class riscv_VFSQRT_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFSQRT_V, VS2_FORMAT, ARITHMETIC, RVV); }
+
+   class riscv_VFRSQRT7_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFRSQRT7_V, VS2_FORMAT, ARITHMETIC, RVV); }
+
+   // class riscv_VFMIN_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFMIN,    VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFMIN_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMIN_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMIN
+   class riscv_VFMIN_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMIN_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMIN
+   // class riscv_VFMAX_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFMAX,    VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFMAX_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMAX_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFMAX
+   class riscv_VFMAX_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMAX_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFMAX
+   // class riscv_VFSGNJ_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJ,   VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFSGNJ_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJ_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFSGNJ
+   class riscv_VFSGNJ_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJ_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFSGNJ
+   // class riscv_VFSGNJN_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJN,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFSGNJN_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJN_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFSGNJN
+   class riscv_VFSGNJN_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJN_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFSGNJN
+   // class riscv_VFSGNJX_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJX,  VA_FORMAT, ARITHMETIC, RVV, VV, VF); }
+   class riscv_VFSGNJX_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJX_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFSGNJX
+   class riscv_VFSGNJX_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFSGNJX_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFSGNJX
+   // class riscv_VMFEQ_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMFEQ,    VA_FORMAT, COMPARE, RVV, VV, VF); }
+   class riscv_VMFEQ_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMFEQ_VV, VA_FORMAT, COMPARE, RVV); } // VMFEQ
+   class riscv_VMFEQ_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMFEQ_VF, VA_FORMAT, COMPARE, RVV); } // VMFEQ
+   // class riscv_VMFNE_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMFNE,    VA_FORMAT, COMPARE, RVV, VV, VF); }
+   class riscv_VMFNE_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMFNE_VV, VA_FORMAT, COMPARE, RVV); } // VMFNE
+   class riscv_VMFNE_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMFNE_VF, VA_FORMAT, COMPARE, RVV); } // VMFNE
+   // class riscv_VMFLT_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMFLT,    VA_FORMAT, COMPARE, RVV, VV, VF); }
+   class riscv_VMFLT_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMFLT_VV, VA_FORMAT, COMPARE, RVV); } // VMFLT
+   class riscv_VMFLT_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMFLT_VF, VA_FORMAT, COMPARE, RVV); } // VMFLT
+   // class riscv_VMFLE_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMFLE,    VA_FORMAT, COMPARE, RVV, VV, VF); }
+   class riscv_VMFLE_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMFLE_VV, VA_FORMAT, COMPARE, RVV); } // VMFLE
+   class riscv_VMFLE_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMFLE_VF, VA_FORMAT, COMPARE, RVV); } // VMFLE
+   // class riscv_VMFGT_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMFGT,    VA_FORMAT, COMPARE, RVV, VF); }
+   class riscv_VMFGT_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMFGT_VF, VA_FORMAT, COMPARE, RVV); } // VMFGT
+   // class riscv_VMFGE_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VMFGE,    VA_FORMAT, COMPARE, RVV, VF); }
+   class riscv_VMFGE_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMFGE_VF, VA_FORMAT, COMPARE, RVV); } // VMFGE
+
+   class riscv_VFCLASS_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFCLASS_V,VS2_FORMAT, COMPARE, RVV); }
+
+   // class riscv_VFMERGE_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFMERGE,  VA_FORMAT, ARITHMETIC, RVV, VFM); }
+   class riscv_VFMERGE_VFM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMERGE_VFM, VA_FORMAT, ARITHMETIC, RVV); } // VFMERGE
+   // class riscv_VFMV_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFMV,     VA_FORMAT, ARITHMETIC, RVV, VF); }
+   class riscv_VFMV_V_F_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMV_V_F, VA_FORMAT, ARITHMETIC, RVV); } // VFMV
+   // VFWADD
+   class riscv_VFWADD_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWADD_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFWADD
+   class riscv_VFWADD_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWADD_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFWADD
+   class riscv_VFWADD_WF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWADD_WF, VA_FORMAT, ARITHMETIC, RVV); } // VFWADD
+   class riscv_VFWADD_WV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWADD_WV, VA_FORMAT, ARITHMETIC, RVV); } // VFWADD
+   // VFWSUB
+   class riscv_VFWSUB_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWSUB_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFWSUB
+   class riscv_VFWSUB_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWSUB_VV, VA_FORMAT, ARITHMETIC, RVV); } // VFWSUB
+   class riscv_VFWSUB_WF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWSUB_WF, VA_FORMAT, ARITHMETIC, RVV); } // VFWSUB
+   class riscv_VFWSUB_WV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWSUB_WV, VA_FORMAT, ARITHMETIC, RVV); } // VFWSUB
 
    // Vector conversion instructions
-   class riscv_VFCVT_XU_F_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_XU_F_V,     VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFCVT_X_F_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_X_F_V,      VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFCVT_F_XU_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_F_XU_V,     VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFCVT_F_X_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_F_X_V,      VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFWCVT_XU_F_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_XU_F_V,    VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFWCVT_X_F_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_X_F_V,     VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFWCVT_F_XU_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_F_XU_V,    VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFWCVT_F_X_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_F_X_V,     VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFWCVT_F_F_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_F_F_V,     VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFNCVT_XU_F_W_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_XU_F_W,    VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFNCVT_X_F_W_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_X_F_W,     VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFNCVT_F_XU_W_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_F_XU_W,    VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFNCVT_F_X_W_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_F_X_W,     VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFNCVT_F_F_W_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_F_F_W,     VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFNCVT_ROD_F_F_W_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_ROD_F_F_W, VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFCVT_XU_F_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_XU_F_V,     VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFCVT_X_F_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_X_F_V,      VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFCVT_RTZ_XU_F_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_RTZ_XU_F_V,     VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFCVT_RTZ_X_F_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_RTZ_X_F_V,      VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFCVT_F_XU_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_F_XU_V,     VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFCVT_F_X_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFCVT_F_X_V,      VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFWCVT_XU_F_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_XU_F_V,    VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFNCVT_RTZ_XU_F_W_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_RTZ_XU_F_W,     VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFNCVT_RTZ_X_F_W_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_RTZ_X_F_W,      VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFWCVT_X_F_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_X_F_V,     VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFWCVT_F_XU_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_F_XU_V,    VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFWCVT_F_X_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_F_X_V,     VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFWCVT_RTZ_XU_F_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_RTZ_XU_F_V,    VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFWCVT_RTZ_X_F_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_RTZ_X_F_V,     VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFWCVT_F_F_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWCVT_F_F_V,     VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFNCVT_XU_F_W_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_XU_F_W,    VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFNCVT_X_F_W_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_X_F_W,     VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFNCVT_F_XU_W_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_F_XU_W,    VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFNCVT_F_X_W_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_F_X_W,     VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFNCVT_F_F_W_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_F_F_W,     VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFNCVT_ROD_F_F_W_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFNCVT_ROD_F_F_W, VS2_FORMAT, ARITHMETIC, RVV); }
 
    // Vector reduction instruction
-   class riscv_VREDSUM_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VREDSUM_VS,    VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VREDMAXU_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VREDMAXU_VS,   VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VREDMAX_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VREDMAX_VS,    VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VREDMINU_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VREDMINU_VS,   VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VREDMIN_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VREDMIN_VS,    VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VREDAND_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VREDAND_VS,    VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VREDOR_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VREDOR_VS,     VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VREDXOR_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VREDXOR_VS,    VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VWREDSUMU_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VWREDSUMU_VS,  VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VWREDSUM_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VWREDSUM_VS,   VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFREDOSUM_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFREDOSUM_VS,  VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFREDSUM_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFREDSUM_VS,   VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFREDMAX_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFREDMAX_VS,   VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFWREDOSUM_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFWREDOSUM_VS, VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFWREDSUM_VS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFWREDSUM_VS,  VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VREDSUM_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VREDSUM_VS,    VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VREDMAXU_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VREDMAXU_VS,   VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VREDMAX_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VREDMAX_VS,    VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VREDMINU_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VREDMINU_VS,   VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VREDMIN_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VREDMIN_VS,    VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VREDAND_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VREDAND_VS,    VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VREDOR_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VREDOR_VS,     VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VREDXOR_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VREDXOR_VS,    VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VWREDSUMU_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWREDSUMU_VS,  VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VWREDSUM_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VWREDSUM_VS,   VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFREDOSUM_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFREDOSUM_VS,  VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFREDUSUM_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFREDUSUM_VS,    VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFREDSUM_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFREDSUM_VS,   VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFREDMAX_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFREDMAX_VS,   VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFREDMIN_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFREDMIN_VS,   VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFWREDOSUM_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWREDOSUM_VS, VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFWREDUSUM_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWREDUSUM_VS, VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFWREDSUM_VS_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFWREDSUM_VS,  VA_FORMAT, ARITHMETIC, RVV); }
 
    // Vector mask instruction
-   class riscv_VMAND_MM_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMAND_MM,    VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMNAND_MM_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMNAND_MM,   VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMANDNOT_MM_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMANDNOT_MM, VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMXOR_MM_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMXOR_MM,    VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMOR_MM_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMOR_MM,     VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMNOR_MM_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMNOR_MM,    VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMORNOT_MM_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMORNOT_MM,  VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMXNOR_MM_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMXNOR_MM,   VA_FORMAT, ARITHMETIC, RVV); }
-
-   class riscv_VPOPC_M_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VPOPC_M,   VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFIRST_M_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFIRST_M,  VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMSBF_M_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMSBF_M,   VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMSIF_M_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMSIF_M,   VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMSOF_M_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMSOF_M,   VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VIOTA_M_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VIOTA_M,   VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VID_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VID_V,     VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMAND_MM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMAND_MM,    VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMANDN_MM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMANDN_MM,    VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMNAND_MM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMNAND_MM,   VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMANDNOT_MM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMANDNOT_MM, VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMXOR_MM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMXOR_MM,    VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMOR_MM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMOR_MM,     VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMORN_MM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMORN_MM,     VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMNOR_MM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMNOR_MM,    VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMORNOT_MM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMORNOT_MM,  VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMXNOR_MM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMXNOR_MM,   VA_FORMAT, ARITHMETIC, RVV); }
+
+   class riscv_VPOPC_M_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VPOPC_M,   VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VCPOP_M_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VCPOP_M,   VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFIRST_M_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFIRST_M,  VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMSBF_M_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSBF_M,   VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMSIF_M_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSIF_M,   VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMSOF_M_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMSOF_M,   VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VIOTA_M_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VIOTA_M,   VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VID_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VID_V,     VS2_FORMAT, ARITHMETIC, RVV); }
 
    // Vector permutation instruction
-   class riscv_VMV_X_S_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMV_X_S,  VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMV_S_X_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMV_S_X,  VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFMV_F_S_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFMV_F_S, VA_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VFMV_S_F_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VFMV_S_F, VA_FORMAT, ARITHMETIC, RVV); }
-
-   class riscv_VSLIDEUP_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEUP,    VA_FORMAT, ARITHMETIC, RVV, VI, VX); }
-   class riscv_VSLIDEDOWN_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEDOWN,  VA_FORMAT, ARITHMETIC, RVV, VI, VX); }
-   class riscv_VSLIDE1UP_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSLIDE1UP,   VA_FORMAT, ARITHMETIC, RVV, VX); }
-   class riscv_VSLIDE1DOWN_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSLIDE1DOWN, VA_FORMAT, ARITHMETIC, RVV, VX); }
-   class riscv_VRGATHER_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VRGATHER,    VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
-   class riscv_VCOMPRESS_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VCOMPRESS,   VA_FORMAT, ARITHMETIC, RVV, VM); }
-
-   class riscv_VMV1R_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMV1R_V, VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMV2R_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMV2R_V, VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMV4R_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMV4R_V, VS2_FORMAT, ARITHMETIC, RVV); }
-   class riscv_VMV8R_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VMV8R_V, VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMV_X_S_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMV_X_S,  VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMV_S_X_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMV_S_X,  VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFMV_F_S_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMV_F_S, VA_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VFMV_S_F_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFMV_S_F, VA_FORMAT, ARITHMETIC, RVV); }
+
+
+   // class riscv_VSLIDEUP_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEUP,    VA_FORMAT, ARITHMETIC, RVV, VI, VX); }
+   class riscv_VSLIDEUP_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEUP_VI, VA_FORMAT, ARITHMETIC, RVV); } // VSLIDEUP
+   class riscv_VSLIDEUP_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEUP_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSLIDEUP
+   // class riscv_VSLIDEDOWN_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEDOWN,  VA_FORMAT, ARITHMETIC, RVV, VI, VX); }
+   class riscv_VSLIDEDOWN_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEDOWN_VI, VA_FORMAT, ARITHMETIC, RVV); } // VSLIDEDOWN
+   class riscv_VSLIDEDOWN_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSLIDEDOWN_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSLIDEDOWN
+   // class riscv_VSLIDE1UP_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSLIDE1UP,   VA_FORMAT, ARITHMETIC, RVV, VX); }
+   class riscv_VSLIDE1UP_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSLIDE1UP_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSLIDE1UP
+   // class riscv_VFSLIDE1UP_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFSLIDE1UP,   VA_FORMAT, ARITHMETIC, RVV, VF); }
+   class riscv_VFSLIDE1UP_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFSLIDE1UP_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFSLIDE1UP
+   // class riscv_VSLIDE1DOWN_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VSLIDE1DOWN, VA_FORMAT, ARITHMETIC, RVV, VX); }
+   class riscv_VSLIDE1DOWN_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSLIDE1DOWN_VX, VA_FORMAT, ARITHMETIC, RVV); } // VSLIDE1DOWN
+   // class riscv_VFSLIDE1DOWN_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VFSLIDE1DOWN, VA_FORMAT, ARITHMETIC, RVV, VF); }
+   class riscv_VFSLIDE1DOWN_VF_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VFSLIDE1DOWN_VF, VA_FORMAT, ARITHMETIC, RVV); } // VFSLIDE1DOWN
+   // class riscv_VRGATHER_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VRGATHER,    VA_FORMAT, ARITHMETIC, RVV, VV, VX, VI); }
+   class riscv_VRGATHER_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VRGATHER_VV, VA_FORMAT, ARITHMETIC, RVV); } // VRGATHER
+   class riscv_VRGATHER_VX_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VRGATHER_VX, VA_FORMAT, ARITHMETIC, RVV); } // VRGATHER
+   class riscv_VRGATHER_VI_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VRGATHER_VI, VA_FORMAT, ARITHMETIC, RVV); } // VRGATHER
+   // class riscv_VRGATHEREI16_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VRGATHEREI16,    VA_FORMAT, ARITHMETIC, RVV, VV); }
+   class riscv_VRGATHEREI16_VV_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VRGATHEREI16_VV, VA_FORMAT, ARITHMETIC, RVV); } // VRGATHEREI16
+   // class riscv_VCOMPRESS_instr: riscv_vector_instr   // { mixin RISCV_VA_INSTR_MIXIN!(VCOMPRESS,   VA_FORMAT, ARITHMETIC, RVV, VM); }
+   class riscv_VCOMPRESS_VM_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VCOMPRESS_VM, VA_FORMAT, ARITHMETIC, RVV); } // VCOMPRESS
+
+   class riscv_VMV1R_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMV1R_V, VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMV2R_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMV2R_V, VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMV4R_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMV4R_V, VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VMV8R_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VMV8R_V, VS2_FORMAT, ARITHMETIC, RVV); }
+
+   class riscv_VS1R_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VS1R_V, VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VS2R_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VS2R_V, VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VS4R_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VS4R_V, VS2_FORMAT, ARITHMETIC, RVV); }
+   class riscv_VS8R_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VS8R_V, VS2_FORMAT, ARITHMETIC, RVV); }
 
    // -------------------------------------------------------------------------
    //  Section 7. Vector Loads and Stores
    // -------------------------------------------------------------------------
    // Section 7.4 - Vector Unit-Stride Instructions
-   class riscv_VLE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VLE_V, VL_FORMAT, LOAD, RVV); }
-   class riscv_VSE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSE_V, VS_FORMAT, STORE, RVV); }
-   // Section 7.5 - Vector Strided Instructions
-   class riscv_VLSE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VLSE_V, VLS_FORMAT, LOAD, RVV); }
-   class riscv_VSSE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSSE_V, VSS_FORMAT, STORE, RVV); }
-   // Section 7.6 - Vector Indexed Instructions
-   class riscv_VLXEI_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VLXEI_V, VLX_FORMAT, LOAD, RVV); }
-   class riscv_VSXEI_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSXEI_V, VSX_FORMAT, STORE, RVV); }
-   class riscv_VSUXEI_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VSUXEI_V, VSX_FORMAT, STORE, RVV); }
-   // Section 7.7 - Vector Unit-Stride Fault-Only-First Loads
-   class riscv_VLEFF_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!(VLEFF_V, VL_FORMAT, LOAD, RVV); }
-   // Section 7.8 - Vector Load/Store Segment Instructions (Zvlsseg)
-   // 7.8.1. Vector Unit Strided Segment Loads and Stores
-   class riscv_VLSEGE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLSEGE_V, VL_FORMAT, LOAD, RVV); }
-   class riscv_VSSEGE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSSEGE_V, VS_FORMAT, STORE, RVV); }
-   class riscv_VLSEGEFF_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLSEGEFF_V, VL_FORMAT, LOAD, RVV); }
-   // 7.8.2. Vector Strided Segment Loads and Stores
-   class riscv_VLSSEGE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLSSEGE_V, VLS_FORMAT, LOAD, RVV); }
-   class riscv_VSSSEGE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSSSEGE_V, VSS_FORMAT, STORE, RVV); }
-   // 7.8.3. Vector Indexed Segment Loads and Stores
-   class riscv_VLXSEGEI_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLXSEGEI_V, VLX_FORMAT, LOAD, RVV); }
-   class riscv_VSXSEGEI_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSXSEGEI_V, VSX_FORMAT, STORE, RVV); }
-   class riscv_VSUXSEGEI_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSUXSEGEI_V, VSX_FORMAT, STORE, RVV); }
+   class riscv_VLM_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLM_V, VL_FORMAT, LOAD, RVV); }   // mismatch with riscv-opcodes
+   class riscv_VLE1_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE1_V, VL_FORMAT, LOAD, RVV); }   // mismatch with riscv-opcodes
+   class riscv_VSM_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSM_V, VS_FORMAT, STORE, RVV); }   // mismatch with riscv-opcodes
+   class riscv_VSE1_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSE1_V, VS_FORMAT, STORE, RVV); }   // mismatch with riscv-opcodes
 
-   // -------------------------------------------------------------------------
-   //  Section 8. Vector AMO Operations (Zvamo)
-   // -------------------------------------------------------------------------
-   // EEW vector AMOs
-   class riscv_VAMOSWAPE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOSWAPE_V, VAMO_FORMAT, AMO, RVV); }
-   class riscv_VAMOADDE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOADDE_V, VAMO_FORMAT, AMO, RVV); }
-   class riscv_VAMOXORE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOXORE_V, VAMO_FORMAT, AMO, RVV); }
-   class riscv_VAMOANDE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOANDE_V, VAMO_FORMAT, AMO, RVV); }
-   class riscv_VAMOORE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOORE_V, VAMO_FORMAT, AMO, RVV); }
-   class riscv_VAMOMINE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINE_V, VAMO_FORMAT, AMO, RVV); }
-   class riscv_VAMOMAXE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXE_V, VAMO_FORMAT, AMO, RVV); }
-   class riscv_VAMOMINUE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINUE_V, VAMO_FORMAT, AMO, RVV); }
-   class riscv_VAMOMAXUE_V_instr: riscv_vector_instr
-   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXUE_V, VAMO_FORMAT, AMO, RVV); }
+   // // Section 7.5 - Vector Strided Instructions
+   class riscv_VLE8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE8_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE16_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE32_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE64_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE128_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE128_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE256_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE256_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE512_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE512_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE1024_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE1024_V, VLS_FORMAT, LOAD, RVV); }
+
+   class riscv_VLE8FF_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE8FF_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE16FF_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE16FF_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE32FF_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE32FF_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE64FF_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE64FF_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE128FF_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE128FF_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE256FF_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE256FF_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE512FF_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE512FF_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLE1024FF_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLE1024FF_V, VLS_FORMAT, LOAD, RVV); }
+
+   class riscv_VSE8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSE8_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSE16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSE16_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSE32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSE32_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSE64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSE64_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSE128_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSE128_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSE256_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSE256_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSE512_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSE512_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSE1024_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSE1024_V, VLS_FORMAT, LOAD, RVV); }
+
+   class riscv_VLSE8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLSE8_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLSE16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLSE16_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLSE32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLSE32_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLSE64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLSE64_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLSE128_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLSE128_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLSE256_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLSE256_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLSE512_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLSE512_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLSE1024_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLSE1024_V, VLS_FORMAT, LOAD, RVV); }
+
+   class riscv_VSSE8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSE8_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSSE16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSE16_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSSE32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSE32_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSSE64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSE64_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSSE128_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSE128_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSSE256_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSE256_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSSE512_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSE512_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSSE1024_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSSE1024_V, VLS_FORMAT, LOAD, RVV); }
+
+   class riscv_VLOXEI8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLOXEI8_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLOXEI16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLOXEI16_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLOXEI32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLOXEI32_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLOXEI64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLOXEI64_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLOXEI128_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLOXEI128_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLOXEI256_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLOXEI256_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLOXEI512_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLOXEI512_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLOXEI1024_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLOXEI1024_V, VLS_FORMAT, LOAD, RVV); }
+
+   class riscv_VLUXEI8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLUXEI8_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLUXEI16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLUXEI16_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLUXEI32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLUXEI32_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLUXEI64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLUXEI64_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLUXEI128_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLUXEI128_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLUXEI256_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLUXEI256_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLUXEI512_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLUXEI512_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VLUXEI1024_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLUXEI1024_V, VLS_FORMAT, LOAD, RVV); }
+
+   class riscv_VSOXEI8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSOXEI8_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSOXEI16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSOXEI16_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSOXEI32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSOXEI32_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSOXEI64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSOXEI64_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSOXEI128_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSOXEI128_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSOXEI256_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSOXEI256_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSOXEI512_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSOXEI512_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSOXEI1024_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSOXEI1024_V, VLS_FORMAT, LOAD, RVV); }
+
+   class riscv_VSUXEI8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSUXEI8_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSUXEI16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSUXEI16_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSUXEI32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSUXEI32_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSUXEI64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSUXEI64_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSUXEI128_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSUXEI128_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSUXEI256_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSUXEI256_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSUXEI512_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSUXEI512_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSUXEI1024_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSUXEI1024_V, VLS_FORMAT, LOAD, RVV); }
+
+   class riscv_VL1R_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL1R_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL1RE8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL1RE8_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL1RE16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL1RE16_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL1RE32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL1RE32_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL1RE64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL1RE64_V, VLS_FORMAT, LOAD, RVV); }
+
+   class riscv_VL2R_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL2R_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL2RE8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL2RE8_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL2RE16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL2RE16_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL2RE32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL2RE32_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL2RE64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL2RE64_V, VLS_FORMAT, LOAD, RVV); }
+
+   class riscv_VL4R_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL4R_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL4RE8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL4RE8_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL4RE16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL4RE16_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL4RE32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL4RE32_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL4RE64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL4RE64_V, VLS_FORMAT, LOAD, RVV); }
+
+   class riscv_VL8R_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL8R_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL8RE8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL8RE8_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL8RE16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL8RE16_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL8RE32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL8RE32_V, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VL8RE64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VL8RE64_V, VLS_FORMAT, LOAD, RVV); }
+
+   // // Section 7.6 - Vector Indexed Instructions
+   // class riscv_VLXEI_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLXEI_V, VLX_FORMAT, LOAD, RVV); }
+   // class riscv_VSXEI_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSXEI_V, VSX_FORMAT, STORE, RVV); }
+   // class riscv_VSUXEI_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSUXEI_V, VSX_FORMAT, STORE, RVV); }
+   // // Section 7.7 - Vector Unit-Stride Fault-Only-First Loads
+   // class riscv_VLEFF_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VLEFF_V, VL_FORMAT, LOAD, RVV); }
+   // // Section 7.8 - Vector Load/Store Segment Instructions (Zvlsseg)
+   // // 7.8.1. Vector Unit Strided Segment Loads and Stores
+   // class riscv_VLSEGE_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLSEGE_V, VL_FORMAT, LOAD, RVV); }
+   // class riscv_VSSEGE_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSSEGE_V, VS_FORMAT, STORE, RVV); }
+   // class riscv_VLSEGEFF_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLSEGEFF_V, VL_FORMAT, LOAD, RVV); }
+   // // 7.8.2. Vector Strided Segment Loads and Stores
+   // class riscv_VLSSEGE_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLSSEGE_V, VLS_FORMAT, LOAD, RVV); }
+   // class riscv_VSSSEGE_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSSSEGE_V, VSS_FORMAT, STORE, RVV); }
+   // // 7.8.3. Vector Indexed Segment Loads and Stores
+   // class riscv_VLXSEGEI_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VLXSEGEI_V, VLX_FORMAT, LOAD, RVV); }
+   // class riscv_VSXSEGEI_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSXSEGEI_V, VSX_FORMAT, STORE, RVV); }
+   // class riscv_VSUXSEGEI_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvlsseg", VSUXSEGEI_V, VSX_FORMAT, STORE, RVV); }
+
+   class riscv_VSEXT_VF2_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSEXT_VF2, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSEXT_VF4_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSEXT_VF4, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VSEXT_VF8_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VSEXT_VF8, VLS_FORMAT, LOAD, RVV); }
+   
+   class riscv_VZEXT_VF2_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VZEXT_VF2, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VZEXT_VF4_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VZEXT_VF4, VLS_FORMAT, LOAD, RVV); }
+   class riscv_VZEXT_VF8_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!(VZEXT_VF8, VLS_FORMAT, LOAD, RVV); }
+   
+
+   // // -------------------------------------------------------------------------
+   // //  Section 8. Vector AMO Operations (Zvamo)
+   // // -------------------------------------------------------------------------
+   // // EEW vector AMOs
+   // class riscv_VAMOADDEI8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOADDEI8_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOADDEI16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOADDEI16_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOADDEI32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOADDEI32_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOADDEI64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOADDEI64_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOANDEI8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOANDEI8_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOANDEI16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOANDEI16_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOANDEI32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOANDEI32_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOANDEI64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOANDEI64_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMAXEI8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXEI8_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMAXEI16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXEI16_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMAXEI32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXEI32_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMAXEI64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXEI64_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMAXUEI8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXUEI8_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMAXUEI16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXUEI16_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMAXUEI32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXUEI32_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMAXUEI64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMAXUEI64_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMINEI8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINEI8_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMINEI16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINEI16_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMINEI32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINEI32_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMINEI64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINEI64_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMINUEI8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINUEI8_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMINUEI16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINUEI16_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMINUEI32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINUEI32_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOMINUEI64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOMINUEI64_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOOREI8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOOREI8_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOOREI16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOOREI16_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOOREI32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOOREI32_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOOREI64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOOREI64_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOSWAPEI8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOSWAPEI8_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOSWAPEI16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOSWAPEI16_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOSWAPEI32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOSWAPEI32_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOSWAPEI64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOSWAPEI64_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOXOREI8_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOXOREI8_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOXOREI16_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOXOREI16_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOXOREI32_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOXOREI32_V, VAMO_FORMAT, AMO, RVV); }
+   // class riscv_VAMOXOREI64_V_instr: riscv_vector_instr   { mixin RISCV_VA_INSTR_MIXIN!("zvamo", VAMOXOREI64_V, VAMO_FORMAT, AMO, RVV); }
  }
diff --git a/euvm/riscv/gen/isa/rv32zpn_instr.d b/euvm/riscv/gen/isa/rv32zpn_instr.d
new file mode 100644
index 00000000..7f0b18e3
--- /dev/null
+++ b/euvm/riscv/gen/isa/rv32zpn_instr.d
@@ -0,0 +1,10 @@
+module riscv.gen.isa.rv32zpn_instr;
+
+import riscv.gen.riscv_defines;
+import riscv.gen.isa.riscv_instr: riscv_instr;
+
+import uvm;
+
+
+class riscv_MULH_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(MULH, I_FORMAT, ARITHMETIC, RV32ZPN); }
diff --git a/euvm/riscv/gen/isa/rv64b_instr.d b/euvm/riscv/gen/isa/rv64b_instr.d
index da6a5afa..bef80826 100644
--- a/euvm/riscv/gen/isa/rv64b_instr.d
+++ b/euvm/riscv/gen/isa/rv64b_instr.d
@@ -51,7 +51,7 @@ version (RISCV_INSTR_STRING_MIXIN) {
   mixin (riscv_b_instr_mixin(GORCIW,  I_FORMAT, LOGICAL, RV64B, UIMM));
   mixin (riscv_b_instr_mixin(PACKW,   R_FORMAT, LOGICAL, RV64B));
   mixin (riscv_b_instr_mixin(PACKUW,  R_FORMAT, LOGICAL, RV64B));
-  mixin (riscv_b_instr_mixin(XPERM_W, R_FORMAT, LOGICAL, RV64B));
+  mixin (riscv_b_instr_mixin(XPERM32, R_FORMAT, LOGICAL, RV64B));
  }
  else {
   // ARITHMETIC intructions
@@ -103,6 +103,6 @@ version (RISCV_INSTR_STRING_MIXIN) {
    { mixin RISCV_INSTR_MIXIN!(PACKW,   R_FORMAT, LOGICAL, RV64B); }
    class riscv_PACKUW_instr: riscv_b_instr
    { mixin RISCV_INSTR_MIXIN!(PACKUW,  R_FORMAT, LOGICAL, RV64B); }
-   class riscv_XPERM_W_instr: riscv_b_instr
-   { mixin RISCV_INSTR_MIXIN!(XPERM_W, R_FORMAT, LOGICAL, RV64B); }
+   class riscv_XPERM32_instr: riscv_b_instr
+   { mixin RISCV_INSTR_MIXIN!(XPERM32, R_FORMAT, LOGICAL, RV64B); }
  }
diff --git a/euvm/riscv/gen/isa/rv64i_instr.d b/euvm/riscv/gen/isa/rv64i_instr.d
index 525756d7..9ef0a06c 100644
--- a/euvm/riscv/gen/isa/rv64i_instr.d
+++ b/euvm/riscv/gen/isa/rv64i_instr.d
@@ -18,6 +18,7 @@
 module riscv.gen.isa.rv64i_instr;
 
 import riscv.gen.riscv_defines;
+import riscv.gen.isa.riscv_instr: riscv_instr;
 
 import uvm;
 
diff --git a/euvm/riscv/gen/isa/rv64m_instr.d b/euvm/riscv/gen/isa/rv64m_instr.d
index 7fd35a42..ffde1d54 100644
--- a/euvm/riscv/gen/isa/rv64m_instr.d
+++ b/euvm/riscv/gen/isa/rv64m_instr.d
@@ -18,6 +18,7 @@
 module riscv.gen.isa.rv64m_instr;
 
 import riscv.gen.riscv_defines;
+import riscv.gen.isa.riscv_instr: riscv_instr;
 
 import uvm;
 
diff --git a/euvm/riscv/gen/isa/rv64zpn_instr.d b/euvm/riscv/gen/isa/rv64zpn_instr.d
new file mode 100644
index 00000000..89859eb8
--- /dev/null
+++ b/euvm/riscv/gen/isa/rv64zpn_instr.d
@@ -0,0 +1,247 @@
+module riscv.gen.isa.rv64zpn_instr;
+
+import riscv.gen.riscv_defines;
+import riscv.gen.isa.riscv_instr: riscv_instr;
+
+import uvm;
+
+
+class riscv_MULH_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(MULH, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_ADD32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(ADD32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_INSB_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(INSB, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_PKBB16_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(PKBB16, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_PKTT16_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(PKTT16, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_RADD32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(RADD32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_URADD32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(URADD32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KADD32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KADD32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_UKADD32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(UKADD32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SUB32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SUB32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_RSUB32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(RSUB32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_URSUB32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(URSUB32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KSUB32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KSUB32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_UKSUB32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(UKSUB32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_CRAS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(CRAS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_RCRAS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(RCRAS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_URCRAS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(URCRAS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KCRAS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KCRAS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_UKCRAS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(UKCRAS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_CRSA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(CRSA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_RCRSA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(RCRSA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_URCRSA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(URCRSA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KCRSA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KCRSA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_UKCRSA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(UKCRSA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_STAS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(STAS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_RSTAS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(RSTAS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_URSTAS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(URSTAS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KSTAS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KSTAS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_UKSTAS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(UKSTAS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_STSA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(STSA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_URSTSA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(URSTSA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KSTSA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KSTSA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_UKSTSA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(UKSTSA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SMMUL_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SMMUL, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SRA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SRA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SRAI_U_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SRAI_U, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SRAI32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SRAI32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SRA32_U_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SRA32_U, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SRAI32_U_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SRAI32_U, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SRL32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SRL32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SRLI32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SRLI32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SRL32_U_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SRL32_U, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SLL32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SLL32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SLLI32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SLLI32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KSLL32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KSLL32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KSLLI32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KSLLI32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KSLRA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KSLRA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KSLRA32_U_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KSLRA32_U, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SMIN32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SMIN32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_UMIN32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(UMIN32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SMAX32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SMAX32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KHMBB16_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KHMBB16, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KHMBT16_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KHMBT16, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KHMTT16_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KHMTT16, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KDMBB16_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KDMBB16, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KDMBT16_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KDMBT16, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KDMTT16_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KDMTT16, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KDMABB16_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KDMABB16, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KDMABT16_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KDMABT16, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KDMATT16_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KDMATT16, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SMBT32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SMBT32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SMTT32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SMTT32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KMABB32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KMABB32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KMABT32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KMABT32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KMATT32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KMATT32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KMDA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KMDA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KMXDA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KMXDA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KMAXDA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KMAXDA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KMADS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KMADS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KMADRS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KMADRS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KMAXDS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KMAXDS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KMSDA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KMSDA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KMSXDA32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KMSXDA32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SMDS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SMDS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SMDRS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SMDRS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SMXDS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SMXDS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_SRAIW_U_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(SRAIW_U, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_PKBT32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(PKBT32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_PKTB32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(PKTB32, I_FORMAT, ARITHMETIC, RV64ZPN); }
+
+class riscv_KABS32_instr: riscv_instr
+{mixin RISCV_INSTR_MIXIN!(KABS32, I_FORMAT, ARITHMETIC, RV64ZPN); }
diff --git a/euvm/riscv/gen/isa/rvzpn_instr.d b/euvm/riscv/gen/isa/rvzpn_instr.d
new file mode 100644
index 00000000..cd2c5d0c
--- /dev/null
+++ b/euvm/riscv/gen/isa/rvzpn_instr.d
@@ -0,0 +1,390 @@
+module riscv.gen.isa.rvzpn_instr;
+
+import riscv.gen.riscv_defines;
+import riscv.gen.isa.riscv_instr: riscv_instr;
+
+import uvm;
+
+
+class riscv_ADD16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(ADD16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_ADD8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(ADD8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_AVE_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(AVE, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_CLRS16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(CLRS16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_CLRS32_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(CLRS32, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_CLRS8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(CLRS8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_CLZ16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(CLZ16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_CLZ32_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(CLZ32, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_CLZ8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(CLZ8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_CMPEQ16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(CMPEQ16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_CMPEQ8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(CMPEQ8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_CRAS16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(CRAS16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_CRSA16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(CRSA16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KABS16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KABS16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KABS8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KABS8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KABSW_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KABSW, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KADD16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KADD16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KADD8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KADD8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KADDH_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KADDH, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KADDW_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KADDW, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KCRAS16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KCRAS16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KCRSA16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KCRSA16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KDMABB_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KDMABB, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KDMABT_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KDMABT, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KDMATT_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KDMATT, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KDMBB_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KDMBB, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KDMBT_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KDMBT, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KDMTT_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KDMTT, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KHM16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KHM16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KHM8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KHM8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KHMBB_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KHMBB, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KHMBT_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KHMBT, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KHMTT_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KHMTT, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KHMX16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KHMX16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KHMX8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KHMX8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMABB_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMABB, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMABT_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMABT, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMADA_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMADA, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMADRS_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMADRS, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMADS_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMADS, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMATT_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMATT, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMAXDA_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMAXDA, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMAXDS_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMAXDS, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMDA_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMDA, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMAC_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMAC, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMAC_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMAC_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMAWB_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMAWB, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMAWB_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMAWB_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMAWB2_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMAWB2, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMAWB2_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMAWB2_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMAWT_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMAWT, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMAWT_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMAWT_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMAWT2_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMAWT2, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMAWT2_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMAWT2_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMSB_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMSB, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMSB_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMSB_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMWB2_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMWB2, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMWB2_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMWB2_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMWT2_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMWT2, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMMWT2_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMMWT2_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMSDA_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMSDA, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMSXDA_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMSXDA, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KMXDA_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KMXDA, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSLL16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSLL16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSLL8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSLL8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSLLI16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSLLI16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSLLI8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSLLI8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSLLIW_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSLLIW, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSLLW_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSLLW, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSLRA16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSLRA16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSLRA16_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSLRA16_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSLRA8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSLRA8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSLRA8_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSLRA8_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSLRAW_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSLRAW, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSLRAW_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSLRAW_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSTAS16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSTAS16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSTSA16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSTSA16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSUB16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSUB16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSUB8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSUB8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSUBH_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSUBH, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KSUBW_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KSUBW, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KWMMUL_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KWMMUL, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_KWMMUL_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(KWMMUL_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_MADDR32_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(MADDR32, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_MSUBR32_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(MSUBR32, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_PBSAD_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(PBSAD, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_PBSADA_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(PBSADA, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_PKBT16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(PKBT16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_PKTB16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(PKTB16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_RADD16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(RADD16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_RADD8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(RADD8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_RADDW_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(RADDW, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_RCRAS16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(RCRAS16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_RCRSA16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(RCRSA16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_RSTAS16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(RSTAS16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_RSUB16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(RSUB16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_RSUB8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(RSUB8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_RSUBW_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(RSUBW, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SCLIP16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SCLIP16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SCLIP32_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SCLIP32, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SCLIP8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SCLIP8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SCMPLE16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SCMPLE16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SCMPLE8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SCMPLE8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SCMPLT16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SCMPLT16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SCMPLT8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SCMPLT8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SLL16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SLL16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SLL8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SLL8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SLLI16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SLLI16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SLLI8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SLLI8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMAQA_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMAQA, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMAQA_SU_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMAQA_SU, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMAX16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMAX16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMAX8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMAX8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMBB16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMBB16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMBT16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMBT16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMDRS_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMDRS, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMDS_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMDS, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMIN16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMIN16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMIN8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMIN8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMMUL_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMMUL_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMMWB_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMMWB, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMMWB_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMMWB_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMMWT_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMMWT, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMMWT_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMMWT_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMTT16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMTT16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SMXDS_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SMXDS, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRA_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRA_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRA16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRA16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRA16_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRA16_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRA8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRA8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRA8_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRA8_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRAI16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRAI16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRAI16_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRAI16_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRAI8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRAI8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRAI8_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRAI8_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRL16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRL16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRL16_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRL16_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRL8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRL8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRL8_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRL8_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRLI16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRLI16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRLI16_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRLI16_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRLI8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRLI8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SRLI8_U_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SRLI8_U, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_STAS16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(STAS16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_STSA16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(STSA16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SUB16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SUB16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SUB8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SUB8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SUNPKD810_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SUNPKD810, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SUNPKD820_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SUNPKD820, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SUNPKD830_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SUNPKD830, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SUNPKD831_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SUNPKD831, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_SUNPKD832_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(SUNPKD832, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UCLIP16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UCLIP16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UCLIP32_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UCLIP32, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UCLIP8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UCLIP8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UCMPLE16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UCMPLE16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UCMPLE8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UCMPLE8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UCMPLT16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UCMPLT16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UCMPLT8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UCMPLT8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UKADD16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UKADD16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UKADD8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UKADD8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UKADDH_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UKADDH, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UKADDW_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UKADDW, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UKCRAS16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UKCRAS16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UKCRSA16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UKCRSA16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UKSTAS16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UKSTAS16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UKSTSA16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UKSTSA16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UKSUB16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UKSUB16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UKSUB8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UKSUB8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UKSUBH_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UKSUBH, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UKSUBW_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UKSUBW, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UMAQA_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UMAQA, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UMAX16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UMAX16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UMAX8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UMAX8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UMIN16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UMIN16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_UMIN8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(UMIN8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_URADD16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(URADD16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_URADD8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(URADD8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_URADDW_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(URADDW, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_URCRAS16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(URCRAS16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_URCRSA16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(URCRSA16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_URSTAS16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(URSTAS16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_URSTSA16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(URSTSA16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_URSUB16_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(URSUB16, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_URSUB8_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(URSUB8, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_URSUBW_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(URSUBW, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_ZUNPKD810_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(ZUNPKD810, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_ZUNPKD820_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(ZUNPKD820, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_ZUNPKD830_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(ZUNPKD830, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_ZUNPKD831_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(ZUNPKD831, I_FORMAT, ARITHMETIC, RVZPN); }
+class riscv_ZUNPKD832_instr: riscv_instr
+{ mixin RISCV_INSTR_MIXIN!(ZUNPKD832, I_FORMAT, ARITHMETIC, RVZPN); }
diff --git a/euvm/riscv/gen/package.d b/euvm/riscv/gen/package.d
index b8da18b3..4d7b09af 100644
--- a/euvm/riscv/gen/package.d
+++ b/euvm/riscv/gen/package.d
@@ -18,6 +18,7 @@ public import riscv.gen.riscv_instr_sequence;
 public import riscv.gen.riscv_instr_stream;
 public import riscv.gen.riscv_load_store_instr_lib;
 public import riscv.gen.riscv_loop_instr;
+public import riscv.gen.riscv_opcodes_pkg;
 public import riscv.gen.riscv_page_table;
 public import riscv.gen.riscv_page_table_entry;
 public import riscv.gen.riscv_page_table_exception_cfg;
diff --git a/euvm/riscv/gen/riscv_amo_instr_lib.d b/euvm/riscv/gen/riscv_amo_instr_lib.d
index 414b1645..a52c0344 100644
--- a/euvm/riscv/gen/riscv_amo_instr_lib.d
+++ b/euvm/riscv/gen/riscv_amo_instr_lib.d
@@ -29,7 +29,7 @@ import riscv.gen.isa.riscv_instr: riscv_instr;
 import std.format: format;
 import std.algorithm: canFind;
 
-import esdl.rand: constraint, rand, randomize_with;
+import esdl.rand: constraint, rand, randomize_with, constraint_override;
 import esdl.base.rand: urandom;
 
 import uvm;
@@ -58,7 +58,7 @@ class riscv_amo_base_instr_stream : riscv_mem_access_stream
   } num_of_rs1_reg_c;
 
   constraint! q{
-    // solve num_of_rs1_reg before rs1_reg;
+    solve num_of_rs1_reg before rs1_reg;
     rs1_reg.length == num_of_rs1_reg;
     offset.length == num_of_rs1_reg;
     foreach (rreg; rs1_reg) {
@@ -98,12 +98,15 @@ class riscv_amo_base_instr_stream : riscv_mem_access_stream
   // Use "la" instruction to initialize the offset regiseter
   void init_offset_reg() {
     import std.conv: to;
+    import std.format: sformat;
+
     foreach (i, rreg; rs1_reg) {
       riscv_pseudo_instr la_instr;
       la_instr = riscv_pseudo_instr.type_id.create("la_instr");
       la_instr.pseudo_instr_name = riscv_pseudo_instr_name_t.LA;
       la_instr.rd = rreg;
-      la_instr.imm_str = format("%0s+%0d", cfg.amo_region[data_page_id], offset[i]);
+      la_instr.imm_str = cast(string)
+	sformat!("%0s+%0d")(la_instr.imm_str_buf(), cfg.amo_region[data_page_id], offset[i]);
       append_instr(la_instr);
     }
   }
@@ -214,6 +217,7 @@ class riscv_amo_instr_stream: riscv_amo_base_instr_stream
     num_mixed_instr inside [0..num_amo+1];
   } reasonable_c;
 
+  @constraint_override
   constraint! q{
     solve num_amo before num_of_rs1_reg;
     num_of_rs1_reg inside [1..num_amo+1];
@@ -258,11 +262,11 @@ class riscv_vector_amo_instr_stream: riscv_vector_load_store_instr_stream
   }
 
   void add_element_vec_load_stores() {
-    allowed_instr = [riscv_instr_name_t.VAMOSWAPE_V, riscv_instr_name_t.VAMOADDE_V,
-		     riscv_instr_name_t.VAMOXORE_V,  riscv_instr_name_t.VAMOANDE_V,
-		     riscv_instr_name_t.VAMOORE_V,   riscv_instr_name_t.VAMOMINE_V,
-		     riscv_instr_name_t.VAMOMAXE_V,  riscv_instr_name_t.VAMOMINUE_V,
-		     riscv_instr_name_t.VAMOMAXUE_V] ~ allowed_instr;
+    // allowed_instr = [riscv_instr_name_t.VAMOSWAPE_V, riscv_instr_name_t.VAMOADDE_V,
+    // 		     riscv_instr_name_t.VAMOXORE_V,  riscv_instr_name_t.VAMOANDE_V,
+    // 		     riscv_instr_name_t.VAMOORE_V,   riscv_instr_name_t.VAMOMINE_V,
+    // 		     riscv_instr_name_t.VAMOMAXE_V,  riscv_instr_name_t.VAMOMINUE_V,
+    // 		     riscv_instr_name_t.VAMOMAXUE_V] ~ allowed_instr;
   }
 
 }
diff --git a/euvm/riscv/gen/riscv_asm_program_gen.d b/euvm/riscv/gen/riscv_asm_program_gen.d
index 98324ac4..71c0ed30 100644
--- a/euvm/riscv/gen/riscv_asm_program_gen.d
+++ b/euvm/riscv/gen/riscv_asm_program_gen.d
@@ -29,8 +29,8 @@ import riscv.gen.riscv_signature_pkg: core_status_t, signature_type_t, test_resu
 import riscv.gen.riscv_instr_gen_config: riscv_instr_gen_config;
 
 import riscv.gen.riscv_instr_pkg: privileged_reg_t, privileged_mode_t,
-  exception_cause_t, interrupt_cause_t, get_label, indent, hart_prefix,
-  riscv_instr_group_t, satp_mode_t, program_id_t, format_string, misa_ext_t,
+  exception_cause_t, interrupt_cause_t, get_label, INDENT, hart_prefix,
+  riscv_instr_group_t, satp_mode_t, program_id_t, misa_ext_t,
   vreg_init_method_t, mem_region_t, mtvec_mode_t, push_gpr_to_kernel_stack,
   pop_gpr_from_kernel_stack, riscv_reg_t,
   DATA_WIDTH, SINGLE_PRECISION_FRACTION_BITS, LABEL_STR_LEN,
@@ -53,11 +53,12 @@ import std.string: toLower;
 import std.format: format;
 
 import esdl.data.queue: Queue;
-import esdl.data.bvec: ubvec, toubvec;
+import esdl.data.bvec: ubvec, toubvec, UBVEC;
 import esdl.rand: randomize;
 import esdl.base.rand: urandom, shuffle;
 import esdl.solver: CstVecDistSolver, CstVecDistRange;
 import esdl.base.cmdl: CommandLine;
+import esdl.base.core: fork, Fork;
 
 import uvm;
 
@@ -100,6 +101,11 @@ class riscv_asm_program_gen : uvm_object
 
   // This is the main function to generate all sections of the program.
   void gen_program() {
+    // Prevent generation of PMP exception handling code where PMP is not supported
+    if (! support_pmp) {
+      cfg.pmp_cfg.enable_pmp_exception_handler = false;
+    }
+
     instr_stream.length = 0;
     // Generate program header
     gen_program_header();
@@ -159,8 +165,8 @@ class riscv_asm_program_gen : uvm_object
       instr_stream ~= main_program[hart].instr_string_list.toArray();
       // If PMP is supported, need to jump from end of main program to test_done section at the end
       // of main_program, as the test_done will have moved to the beginning of the program
-      instr_stream ~= format("%sla x%0d, test_done", indent, cfg.scratch_reg);
-      instr_stream ~= format("%sjalr x0, x%0d, 0", indent, cfg.scratch_reg);
+      instr_stream ~= format("%sla x%0d, test_done", INDENT, cfg.scratch_reg);
+      instr_stream ~= format("%sjalr x0, x%0d, 0", INDENT, cfg.scratch_reg);
       // Test done section
       // If PMP isn't supported, generate this in the normal location
       if ((hart == 0) & !support_pmp) {
@@ -462,15 +468,15 @@ class riscv_asm_program_gen : uvm_object
   }
 
   void gen_init_section(int hart) {
-    string str;
-    str = format_string(get_label("init:", hart), LABEL_STR_LEN);
+    enum string FMT = "%-" ~ LABEL_STR_LEN.stringof ~ "s";
+    string str = format!FMT(get_label("init:", hart));
     instr_stream ~= str;
     if (cfg.enable_floating_point) {
       init_floating_point_gpr();
     }
     init_gpr();
     // Init stack pointer to point to the end of the user stack
-    str = indent ~ format("la x%0d, %0suser_stack_end", cfg.sp, hart_prefix(hart));
+    str = INDENT ~ format("la x%0d, %0suser_stack_end", cfg.sp, hart_prefix(hart));
     instr_stream ~= str;
     if (cfg.enable_vector_extension) {
       randomize_vec_gpr_and_csr();
@@ -478,7 +484,7 @@ class riscv_asm_program_gen : uvm_object
     core_is_initialized();
     gen_dummy_csr_write(); // TODO add a way to disable xStatus read
     if (support_pmp) {
-      str = indent ~  "j main";
+      str = INDENT ~  "j main";
       instr_stream ~= str;
     }
   }
@@ -486,10 +492,10 @@ class riscv_asm_program_gen : uvm_object
   // Setup MISA based on supported extensions
   void setup_misa() {
     ubvec!XLEN   misa;
-    misa[XLEN-2..XLEN] = (XLEN == 32) ? toubvec!2(0b01) :
-      (XLEN == 64) ? toubvec!2(0b10) : toubvec!2(0b11);
+    misa[XLEN-2..XLEN] = (XLEN == 32) ? UBVEC!(2, 0b01) :
+      (XLEN == 64) ? UBVEC!(2, 0b10) : UBVEC!(2, 0b11);
     if (cfg.check_misa_init_val) {
-      instr_stream ~= indent ~ format("csrr x15, 0x%0x", privileged_reg_t.MISA);
+      instr_stream ~= INDENT ~ format("csrr x15, 0x%0x", privileged_reg_t.MISA);
     }
     foreach (sisa; supported_isa) {
       switch  (sisa) {
@@ -513,15 +519,17 @@ class riscv_asm_program_gen : uvm_object
       case riscv_instr_group_t.RV32ZBA,	riscv_instr_group_t.RV32ZBB,
 	riscv_instr_group_t.RV32ZBC, riscv_instr_group_t.RV32ZBS,
         riscv_instr_group_t.RV64ZBA, riscv_instr_group_t.RV64ZBB,
-	riscv_instr_group_t.RV64ZBC, riscv_instr_group_t.RV64ZBS: break; // No Misa bit for Zb* extensions
+	riscv_instr_group_t.RV64ZBC, riscv_instr_group_t.RV64ZBS,
+	riscv_instr_group_t.RVZPN, riscv_instr_group_t.RV32ZPN,
+	riscv_instr_group_t.RV64ZPN : break; // No Misa bit for Zb* extensions
       default : uvm_fatal(get_full_name(), format("%0s is not yet supported", sisa));
       }
     }
     if (canFind(supported_privileged_mode, privileged_mode_t.SUPERVISOR_MODE)) {
       misa[misa_ext_t.MISA_EXT_S] = true;
     }
-    instr_stream ~= indent ~ format("li x%0d, 0x%0x", cfg.gpr[0], misa);
-    instr_stream ~= indent ~ format("csrw 0x%0x, x%0d", privileged_reg_t.MISA, cfg.gpr[0]);
+    instr_stream ~= INDENT ~ format("li x%0d, 0x%0x", cfg.gpr[0], misa);
+    instr_stream ~= INDENT ~ format("csrw 0x%0x, x%0d", privileged_reg_t.MISA, cfg.gpr[0]);
   }
 
   // Write to the signature_addr with values to indicate to the core testbench
@@ -605,7 +613,7 @@ class riscv_asm_program_gen : uvm_object
 							  1, false);
       }
       reg_val = _gpr_solver.urandom();
-      str = format("%0sli x%0d, 0x%0x", indent, i, reg_val);
+      str = format("%0sli x%0d, 0x%0x", INDENT, i, reg_val);
       instr_stream ~= str;
     }
   }
@@ -622,29 +630,29 @@ class riscv_asm_program_gen : uvm_object
     SEW = (ELEN <= XLEN) ? ELEN : XLEN;
     instr_stream ~= format("li x%0d, %0d", cfg.gpr[1], cfg.vector_cfg.vl);
     instr_stream ~= format("%svsetvli x%0d, x%0d, e%0d, m%0d, d%0d",
-			   indent, cfg.gpr[0], cfg.gpr[1], SEW, LMUL, EDIV);
+			   INDENT, cfg.gpr[0], cfg.gpr[1], SEW, LMUL, EDIV);
     instr_stream ~= "vec_reg_init:";
 
     // Vector registers will be initialized using one of the following three methods
     switch (cfg.vreg_init_method) {
     case vreg_init_method_t.SAME_VALUES_ALL_ELEMS:
       for (int v = 0; v < NUM_VEC_GPR; v++) {
-	instr_stream ~= format("%0svmv.v.x v%0d, x%0d", indent, v, v);
+	instr_stream ~= format("%0svmv.v.x v%0d, x%0d", INDENT, v, v);
       }
       break;
     case vreg_init_method_t.RANDOM_VALUES_VMV:
       for (int v = 0; v < NUM_VEC_GPR; v++) {
 	for (int e = 0; e < num_elements; e++) {
-	  if (e > 0) instr_stream ~= format("%0svmv.v.v v0, v%0d", indent, v);
+	  if (e > 0) instr_stream ~= format("%0svmv.v.v v0, v%0d", INDENT, v);
 	  instr_stream ~= format("%0sli x%0d, 0x%0x",
-				 indent, cfg.gpr[0], urandom(0, 2 ^^ SEW));
+				 INDENT, cfg.gpr[0], urandom(0, 2 ^^ SEW));
 	  if (v > 0) {
 	    instr_stream ~= format("%0svslide1up.vx v%0d, v0, x%0d",
-				   indent, v, cfg.gpr[0]);
+				   INDENT, v, cfg.gpr[0]);
 	  }
 	  else {
 	    instr_stream ~= format("%0svslide1up.vx v%0d, v1, x%0d",
-				   indent, v, cfg.gpr[0]);
+				   INDENT, v, cfg.gpr[0]);
 	  }
 	}
       }
@@ -661,8 +669,8 @@ class riscv_asm_program_gen : uvm_object
       for (int v = 0; v < NUM_VEC_GPR; v++) {
 	assert (valid_mem_region.length != 0);
 	uint region = urandom(0, cast(uint) valid_mem_region.length);
-	instr_stream ~= format("%0sla t0, %0s", indent, valid_mem_region[region]);
-	instr_stream ~= format("%0svle.v v%0d, (t0)", indent, v);
+	instr_stream ~= format("%0sla t0, %0s", INDENT, valid_mem_region[region]);
+	instr_stream ~= format("%0svle.v v%0d, (t0)", INDENT, v);
       }
       break;
     default : break;
@@ -681,7 +689,7 @@ class riscv_asm_program_gen : uvm_object
       else init_floating_point_gpr_with_spf(i);
     }
     // Initialize rounding mode of FCSR
-    str = format("%0sfsrmi %0d", indent, cfg.fcsr_rm);
+    str = format("%0sfsrmi %0d", INDENT, cfg.fcsr_rm);
     instr_stream ~= str;
   }
 
@@ -689,9 +697,9 @@ class riscv_asm_program_gen : uvm_object
   void init_floating_point_gpr_with_spf(int int_floating_gpr) {
     string str;
     ubvec!32 imm = cast(ubvec!32) get_rand_spf_value();
-    str = format("%0sli x%0d, %0d", indent, cfg.gpr[0], imm);
+    str = format("%0sli x%0d, %0d", INDENT, cfg.gpr[0], imm);
     instr_stream ~= str;
-    str = format("%0sfmv.w.x f%0d, x%0d", indent, int_floating_gpr, cfg.gpr[0]);
+    str = format("%0sfmv.w.x f%0d, x%0d", INDENT, int_floating_gpr, cfg.gpr[0]);
     instr_stream ~= str;
   }
 
@@ -702,18 +710,18 @@ class riscv_asm_program_gen : uvm_object
     int int_gpr1 = cfg.gpr[0];
     int int_gpr2 = cfg.gpr[1];
 
-    str = format("%0sli x%0d, %0d", indent, int_gpr1, imm[32..64]);
+    str = format("%0sli x%0d, %0d", INDENT, int_gpr1, imm[32..64]);
     instr_stream ~= str;
     // shift to upper 32bits
     for(int i=0 ; i<2 ; ++i) {
-      str = format("%0sslli x%0d, x%0d, 16", indent, int_gpr1, int_gpr1);
+      str = format("%0sslli x%0d, x%0d, 16", INDENT, int_gpr1, int_gpr1);
       instr_stream ~= str;
     }
-    str = format("%0sli x%0d, %0d", indent, int_gpr2, imm[0..32]);
+    str = format("%0sli x%0d, %0d", INDENT, int_gpr2, imm[0..32]);
     instr_stream ~= str;
-    str = format("%0sor x%0d, x%0d, x%0d", indent, int_gpr2, int_gpr2, int_gpr1);
+    str = format("%0sor x%0d, x%0d, x%0d", INDENT, int_gpr2, int_gpr2, int_gpr1);
     instr_stream ~= str;
-    str = format("%0sfmv.d.x f%0d, x%0d", indent, int_floating_gpr, int_gpr2);
+    str = format("%0sfmv.d.x f%0d, x%0d", INDENT, int_floating_gpr, int_gpr2);
     instr_stream ~= str;
   }
 
@@ -736,7 +744,7 @@ class riscv_asm_program_gen : uvm_object
   }
 
   // get a random double precision floating value
-  ubvec!XLEN get_rand_dpf_value() {
+  ubvec!64 get_rand_dpf_value() {
     ubvec!64 value;
 
     int randint = urandom(0,6);
@@ -750,19 +758,20 @@ class riscv_asm_program_gen : uvm_object
     case 5: value[DOUBLE_PRECISION_FRACTION_BITS..63] = 0; break;
     default: break;
     }
-    return value;
+    return cast(ubvec!XLEN) value;
   }
 
   // Generate "test_done" section, test is finished by an ECALL instruction
   // The ECALL trap handler will handle the clean up procedure before finishing the test.
   void gen_test_done() {
-    string str = format_string("test_done:", LABEL_STR_LEN);
+    enum string FMT = "%-" ~ LABEL_STR_LEN.stringof ~ "s";
+    string str = format!FMT("test_done:");
     instr_stream ~= str;
-    instr_stream ~= (indent ~ "li gp, 1");
+    instr_stream ~= (INDENT ~ "li gp, 1");
     if (cfg.bare_program_mode) {
-      instr_stream ~= indent ~ "j write_tohost";
+      instr_stream ~= INDENT ~ "j write_tohost";
     } else {
-      instr_stream ~= indent ~ "ecall";
+      instr_stream ~= INDENT ~ "ecall";
     }
   }
 
@@ -907,8 +916,16 @@ class riscv_asm_program_gen : uvm_object
   void setup_pmp(int hart) {
     string[] instr;
     if (support_pmp) {
-      cfg.pmp_cfg.setup_pmp();
-      cfg.pmp_cfg.gen_pmp_instr([cfg.scratch_reg, cfg.gpr[0]], instr);
+      if(cfg.pmp_cfg.suppress_pmp_setup) {
+        // When PMP setup is suppressed generate a configuration that gives unrestricted access to
+        // all memory for both M and U mode
+        cfg.pmp_cfg.gen_pmp_enable_all(cfg.scratch_reg, instr);
+      }
+      else {
+        cfg.pmp_cfg.setup_pmp();
+        cfg.pmp_cfg.gen_pmp_instr([cfg.scratch_reg, cfg.gpr[0]], instr);
+      }
+
       gen_section(get_label("pmp_setup", hart), instr);
     }
   }
@@ -919,7 +936,7 @@ class riscv_asm_program_gen : uvm_object
   void gen_pmp_csr_write(int hart) {
     string[] instr;
     if (support_pmp && cfg.pmp_cfg.enable_write_pmp_csr) {
-      cfg.pmp_cfg.gen_pmp_write_test([cfg.scratch_reg, cfg.pmp_reg], instr);
+      cfg.pmp_cfg.gen_pmp_write_test([cfg.scratch_reg, cfg.pmp_reg[0]], instr);
       gen_section(get_label("pmp_csr_write_test", hart), instr);
     }
   }
@@ -1343,7 +1360,8 @@ class riscv_asm_program_gen : uvm_object
     gen_signature_handshake(instr, signature_type_t.WRITE_CSR, core_status_t.INITIALIZED,
 			    test_result_t.TEST_FAIL, privileged_reg_t.MCAUSE);
     if (cfg.pmp_cfg.enable_pmp_exception_handler) {
-      cfg.pmp_cfg.gen_pmp_exception_routine(cfg.gpr ~ cfg.scratch_reg ~ cfg.pmp_reg,
+      cfg.pmp_cfg.gen_pmp_exception_routine(cfg.gpr ~ cfg.scratch_reg ~
+					    cfg.pmp_reg[0] ~ cfg.pmp_reg[1],
                                             exception_cause_t.INSTRUCTION_ACCESS_FAULT,
                                             instr);
     }
@@ -1362,7 +1380,8 @@ class riscv_asm_program_gen : uvm_object
 			    test_result_t.TEST_FAIL,
 			    privileged_reg_t.MCAUSE);
     if (cfg.pmp_cfg.enable_pmp_exception_handler) {
-      cfg.pmp_cfg.gen_pmp_exception_routine(cfg.gpr ~ cfg.scratch_reg ~ cfg.pmp_reg,
+      cfg.pmp_cfg.gen_pmp_exception_routine(cfg.gpr ~ cfg.scratch_reg ~
+					    cfg.pmp_reg[0] ~ cfg.pmp_reg[1],
                                             exception_cause_t.LOAD_ACCESS_FAULT,
                                             instr);
     }
@@ -1381,7 +1400,8 @@ class riscv_asm_program_gen : uvm_object
 			    test_result_t.TEST_FAIL,
 			    privileged_reg_t.MCAUSE);
     if (cfg.pmp_cfg.enable_pmp_exception_handler) {
-      cfg.pmp_cfg.gen_pmp_exception_routine(cfg.gpr ~ cfg.scratch_reg ~ cfg.pmp_reg,
+      cfg.pmp_cfg.gen_pmp_exception_routine(cfg.gpr ~ cfg.scratch_reg ~
+					    cfg.pmp_reg[0] ~ cfg.pmp_reg[1],
                                             exception_cause_t.STORE_AMO_ACCESS_FAULT,
                                             instr);
     }
@@ -1540,14 +1560,16 @@ class riscv_asm_program_gen : uvm_object
 
   // Format a code section, without generating it
   void format_section(ref Queue!string instr) {
-    string prefix = format_string(" ", LABEL_STR_LEN);
+    enum string FMT = "%-" ~ LABEL_STR_LEN.stringof ~ "s";
+    string prefix = format!FMT(" ");
     foreach (ii; instr) {
       ii = prefix ~ ii;
     }
   }
 
   void format_section(ref string[] instr) {
-    string prefix = format_string(" ", LABEL_STR_LEN);
+    enum string FMT = "%-" ~ LABEL_STR_LEN.stringof ~ "s";
+    string prefix = format!FMT(" ");
     foreach (ii; instr) {
       ii = prefix ~ ii;
     }
@@ -1557,11 +1579,12 @@ class riscv_asm_program_gen : uvm_object
   void gen_section(string label, Queue!string instr) {
     string str;
     if (label != "") {
-      str = format_string(format("%0s:", label), LABEL_STR_LEN);
+      enum string FMT = "%-" ~ LABEL_STR_LEN.stringof ~ "s";
+      str = format!FMT(format("%0s:", label));
       instr_stream ~= str;
     }
     foreach (ii; instr) {
-      str = indent ~ ii;
+      str = INDENT ~ ii;
       instr_stream ~= str;
     }
     instr_stream ~= "";
@@ -1570,11 +1593,12 @@ class riscv_asm_program_gen : uvm_object
   void gen_section(string label, string[] instr) {
     string str;
     if(label != "") {
-      str = format_string(format("%0s:", label), LABEL_STR_LEN);
+      enum string FMT = "%-" ~ LABEL_STR_LEN.stringof ~ "s";
+      str = format!FMT(format("%0s:", label));
       instr_stream ~= str;
     }
     foreach(i; instr) {
-      str = indent ~ i;
+      str = INDENT ~ i;
       instr_stream ~= str;
     }
     instr_stream ~= "";
@@ -1799,43 +1823,71 @@ class riscv_asm_program_gen : uvm_object
 				      in uint  min_insert_cnt,
 				      in bool kernel_mode,
 				      out riscv_instr_stream[] instr_stream) {
-    uvm_object object_h;
-    uint  instr_insert_cnt;
-    uint  idx;
-    uvm_coreservice_t coreservice = uvm_coreservice_t.get();
-    uvm_factory factory = coreservice.get_factory();
     if (cfg.no_directed_instr) return;
-    foreach (instr_stream_name, ref ratio; directed_instr_stream_ratio) {
-      instr_insert_cnt = original_instr_cnt * ratio / 1000;
-      if(instr_insert_cnt <= min_insert_cnt) {
-        instr_insert_cnt = min_insert_cnt;
+    else {
+      Fork[] forks;
+      uint stream_length = 0;
+      uint stream_idx = 0;
+      uvm_coreservice_t coreservice = uvm_coreservice_t.get();
+      uvm_factory factory = coreservice.get_factory();
+      foreach (instr_stream_name, ratio; directed_instr_stream_ratio) {
+	uint  insert_cnt = original_instr_cnt * ratio / 1000;
+	if (insert_cnt <= min_insert_cnt) insert_cnt = min_insert_cnt;
+	stream_length += insert_cnt;
+	uvm_info(get_full_name(), format("Insert directed instr stream %0s %0d/%0d times",
+					 instr_stream_name, insert_cnt, original_instr_cnt), UVM_LOW);
+	// capture instr_stream_name, ratio, stream_idx and insert_cnt and fork
+	Fork new_fork = (string name, uint idx, uint cnt) {
+	  return fork ({
+	      generate_directed_instr_stream(hart, label, kernel_mode,
+					     name, instr_stream, idx, cnt);
+	    });
+	} (instr_stream_name, stream_idx, insert_cnt);
+	new_fork.set_thread_affinity(forks.length);
+	forks ~= new_fork;
+	stream_idx += insert_cnt;
       }
-      uvm_info(get_full_name(), format("Insert directed instr stream %0s %0d/%0d times",
-				       instr_stream_name, instr_insert_cnt, original_instr_cnt), UVM_LOW);
-      for (int i = 0; i < instr_insert_cnt; i++) {
-        string name = format("%0s_%0d", instr_stream_name, i);
-        object_h = factory.create_object_by_name(instr_stream_name, get_full_name(), name);
-        if (object_h is null) {
-          uvm_fatal(get_full_name(), format("Cannot create instr stream %0s", name));
-        }
+      instr_stream.length = stream_length;
+      foreach (f; forks) f.join();
+      // import esdl.rand.meta: printSolverStats;
+      // import std.stdio;
+      // writeln("printing solver stats");
+      // printSolverStats();
+      assert (stream_idx == instr_stream.length);
+      instr_stream.shuffle();
+    }
+  }
 
-	riscv_rand_instr_stream new_instr_stream = cast(riscv_rand_instr_stream) object_h;
-        if (new_instr_stream !is null) {
-	  assert (cfg !is null);
-          new_instr_stream.cfg = cfg;
-          new_instr_stream.hart = hart;
-          new_instr_stream.label = format("%0s_%0d", label, idx);
-          new_instr_stream.kernel_mode = kernel_mode;
-          new_instr_stream.randomize();
-          instr_stream ~= new_instr_stream;
-        }
-	else {
-          uvm_fatal(get_full_name(), format("Cannot cast instr stream %0s", name));
-        }
-        idx += 1;
+  void generate_directed_instr_stream(in int hart,
+				      in string label,
+				      in bool kernel_mode,
+				      in string instr_stream_name,
+				      ref riscv_instr_stream[] instr_stream,
+				      in uint stream_idx,
+				      in uint insert_cnt) {
+    uvm_coreservice_t coreservice = uvm_coreservice_t.get();
+    uvm_factory factory = coreservice.get_factory();
+    for (uint i = 0; i < insert_cnt; i++) {
+      string name = format("%0s_%0d", instr_stream_name, i);
+      uvm_object object_h = factory.create_object_by_name(instr_stream_name, get_full_name(), name);
+      if (object_h is null) {
+	uvm_fatal(get_full_name(), format("Cannot create instr stream %0s", name));
+      }
+	
+      riscv_rand_instr_stream new_instr_stream = cast(riscv_rand_instr_stream) object_h;
+      if (new_instr_stream !is null) {
+	assert (cfg !is null);
+	new_instr_stream.cfg = cfg;
+	new_instr_stream.hart = hart;
+	new_instr_stream.label = format("%0s_%0d", label, i);
+	new_instr_stream.kernel_mode = kernel_mode;
+	new_instr_stream.randomize();
+	instr_stream[stream_idx+i] = new_instr_stream;
+      }
+      else {
+	uvm_fatal(get_full_name(), format("Cannot cast instr stream %0s", name));
       }
     }
-    instr_stream.shuffle();
   }
 
   //---------------------------------------------------------------------------------------
@@ -1859,8 +1911,8 @@ class riscv_asm_program_gen : uvm_object
   void randomize_vec_gpr_and_csr() {
     string lmul;
     if (!(canFind(supported_isa, riscv_instr_group_t.RVV ) )) return;
-    instr_stream ~= indent ~ format("csrwi vxsat, %0d", cfg.vector_cfg.vxsat);
-    instr_stream ~= indent ~ format("csrwi vxrm, %0d", cfg.vector_cfg.vxrm);
+    instr_stream ~= INDENT ~ format("csrwi vxsat, %0d", cfg.vector_cfg.vxsat);
+    instr_stream ~= INDENT ~ format("csrwi vxrm, %0d", cfg.vector_cfg.vxrm);
     init_vec_gpr(); // GPR init uses a temporary SEW/LMUL setting before the final value set below.
     instr_stream ~= format("li x%0d, %0d", cfg.gpr[1], cfg.vector_cfg.vl);
     if ((cfg.vector_cfg.vtype.vlmul > 1) && (cfg.vector_cfg.vtype.fractional_lmul)) {
@@ -1870,7 +1922,7 @@ class riscv_asm_program_gen : uvm_object
       lmul = format("m%0d", cfg.vector_cfg.vtype.vlmul);
     }
     instr_stream ~= format("%svsetvli x%0d, x%0d, e%0d, m%0d, d%0d",
-			   indent,
+			   INDENT,
 			   cfg.gpr[0],
 			   cfg.gpr[1],
 			   cfg.vector_cfg.vtype.vsew,
diff --git a/euvm/riscv/gen/riscv_data_page_gen.d b/euvm/riscv/gen/riscv_data_page_gen.d
index b5d7a95c..75ef4bf4 100644
--- a/euvm/riscv/gen/riscv_data_page_gen.d
+++ b/euvm/riscv/gen/riscv_data_page_gen.d
@@ -22,7 +22,7 @@
 
 module riscv.gen.riscv_data_page_gen;
 
-import riscv.gen.riscv_instr_pkg: mem_region_t, data_pattern_t, hart_prefix, format_string,
+import riscv.gen.riscv_instr_pkg: mem_region_t, data_pattern_t, hart_prefix,
   format_data, LABEL_STR_LEN;
 import riscv.gen.riscv_instr_gen_config: riscv_instr_gen_config;
 
@@ -119,7 +119,8 @@ class riscv_data_page_gen: uvm_object
 	else {
           gen_data(i, pattern, page_size-i, tmp_data);
         }
-        tmp_str = format_string(format(".word %0s", format_data(tmp_data)), LABEL_STR_LEN);
+	enum string FMT = "%-" ~ LABEL_STR_LEN.stringof ~ "s";
+        tmp_str = format!FMT(format(".word %0s", format_data(tmp_data)));
         data_page_str ~= tmp_str;
       }
       if (cfg.use_push_data_section) {
diff --git a/euvm/riscv/gen/riscv_debug_rom_gen.d b/euvm/riscv/gen/riscv_debug_rom_gen.d
index 7605fd61..4d6e23c5 100644
--- a/euvm/riscv/gen/riscv_debug_rom_gen.d
+++ b/euvm/riscv/gen/riscv_debug_rom_gen.d
@@ -25,7 +25,7 @@
 module riscv.gen.riscv_debug_rom_gen;
 
 import riscv.gen.riscv_instr_pkg: privileged_reg_t, hart_prefix, push_gpr_to_kernel_stack,
-  indent, pop_gpr_from_kernel_stack, privileged_mode_t;
+  INDENT, pop_gpr_from_kernel_stack, privileged_mode_t;
 import riscv.gen.target: supported_privileged_mode;
 import riscv.gen.riscv_instr_sequence: riscv_instr_sequence;
 import riscv.gen.riscv_asm_program_gen: riscv_asm_program_gen;
@@ -116,8 +116,8 @@ class riscv_debug_rom_gen : riscv_asm_program_gen
       main_program[hart].post_process_instr();
       main_program[hart].generate_instr_stream(true);
       debug_main ~= main_program[hart].instr_string_list.toArray ~
-	format("%sla x%0d, debug_end", indent, cfg.scratch_reg) ~
-	format("%sjalr x0, x%0d, 0", indent, cfg.scratch_reg);
+	format("%sla x%0d, debug_end", INDENT, cfg.scratch_reg) ~
+	format("%sjalr x0, x%0d, 0", INDENT, cfg.scratch_reg);
       insert_sub_program(sub_program[hart], debug_main);
       gen_section(format("%0sdebug_rom", hart_prefix(hart)), debug_main);
       if (cfg.enable_ebreak_in_debug_rom) {
diff --git a/euvm/riscv/gen/riscv_defines.d b/euvm/riscv/gen/riscv_defines.d
index 73f8de5e..f47e2256 100644
--- a/euvm/riscv/gen/riscv_defines.d
+++ b/euvm/riscv/gen/riscv_defines.d
@@ -16,6 +16,7 @@
  */
 
 module riscv.gen.riscv_defines;
+import riscv.gen.riscv_opcodes_pkg;
 
 public import riscv.gen.riscv_instr_pkg: riscv_instr_name_t, riscv_instr_group_t,
   riscv_instr_category_t, riscv_instr_format_t, va_variant_t, imm_t;
@@ -29,6 +30,7 @@ mixin(declareEnums!imm_t());
 
 
 public import riscv.gen.isa.riscv_instr: riscv_instr;
+public import riscv.gen.isa.riscv_csr_instr: riscv_csr_instr;
 public import riscv.gen.isa.riscv_floating_point_instr: riscv_floating_point_instr;
 public import riscv.gen.isa.riscv_compressed_instr: riscv_compressed_instr;
 public import riscv.gen.isa.riscv_amo_instr: riscv_amo_instr;
@@ -114,25 +116,51 @@ string riscv_va_instr_mixin_tmpl(BASE_TYPE)(riscv_instr_name_t instr_name,
   return class_str;
 }
 
-class RISCV_INSTR_TMPL(riscv_instr_name_t instr_n,
-		       riscv_instr_format_t instr_format,
-		       riscv_instr_category_t instr_category,
-		       riscv_instr_group_t instr_group,
-		       imm_t imm_tp,
-		       BASE_TYPE): BASE_TYPE
+// class RISCV_INSTR_TMPL(riscv_instr_name_t instr_n,
+// 		       riscv_instr_format_t instr_format,
+// 		       riscv_instr_category_t instr_category,
+// 		       riscv_instr_group_t instr_group,
+// 		       imm_t imm_tp,
+// 		       BASE_TYPE): BASE_TYPE
+// {
+//   enum riscv_instr_name_t RISCV_INSTR_NAME = instr_n;
+//   mixin uvm_object_utils;
+//   this(string name="") {
+//     super(name);
+//     this.instr_name = instr_n;
+//     this.instr_format = instr_format;
+//     this.group = instr_group;
+//     this.category = instr_category;
+//     this.imm_type = imm_tp;
+//     set_imm_len();
+//     set_rand_mode();
+//   }
+// }
+
+void print_class_info(T)(T inst) {
+  static if (is (T B == super)) {
+    // pragma(msg, B.stringof);
+    import std.stdio: writeln;
+    writeln("Randomized ", B[0].stringof);
+  }
+}
+
+// string riscv_instr_var_return_mixin(riscv_instr_var_t VAR) {
+//   import std.format: format;
+//   return format("return _%s;\n", VAR);
+// }
+
+string riscv_instr_var_mixin(riscv_instr_var_t[] vars)
 {
-  enum riscv_instr_name_t RISCV_INSTR_NAME_T = instr_n;
-  mixin uvm_object_utils;
-  this(string name="") {
-    super(name);
-    this.instr_name = instr_n;
-    this.instr_format = instr_format;
-    this.group = instr_group;
-    this.category = instr_category;
-    this.imm_type = imm_tp;
-    set_imm_len();
-    set_rand_mode();
+  import std.format: format;
+  string var_decls;
+  foreach (var; vars) {
+    riscv_instr_var_params_s params = riscv_instr_var_params[var];
+    assert (params._arg == var);
+    var_decls ~= (format("@rand ubvec!%s _%s;\n",
+			 params._msb - params._lsb, var));
   }
+  return var_decls;
 }
 
 mixin template RISCV_INSTR_MIXIN(riscv_instr_name_t instr_n,
@@ -141,7 +169,72 @@ mixin template RISCV_INSTR_MIXIN(riscv_instr_name_t instr_n,
 				 riscv_instr_group_t instr_group,
 				 imm_t imm_tp=imm_t.IMM)
 {
-  enum riscv_instr_name_t RISCV_INSTR_NAME_T = instr_n;
+  import riscv.gen.riscv_opcodes_pkg;
+  import esdl: rand, ubvec;
+
+  static bool hasReg(riscv_instr_var_t r, riscv_instr_var_t[] vars) {
+    foreach (var; vars) if (var is r) return true;
+      else continue;
+    return false;
+  }
+
+  static bool hasReg(riscv_instr_var_t[] regs, riscv_instr_var_t[] vars) {
+    foreach (r; regs) if (hasReg(r, vars)) return true;
+      else continue;
+    return false;
+  }
+
+  auto get_var_value(riscv_instr_var_t VAR)() {
+    import std.format: format;
+    return __traits(getMember, this, format("_%s", VAR));
+  }
+
+  void fill_var_val(riscv_instr_var_t[] VL)(ref ubvec!32 match) {
+    static if (VL.length == 0) return;
+    else {
+      enum VAR = VL[0];
+      enum lsb = riscv_instr_var_params[VAR]._lsb;
+      enum msb = riscv_instr_var_params[VAR]._msb;
+      // pragma(msg, "lsb: ", lsb, ", msb: ", msb);
+      match[lsb..msb] = get_var_value!VAR;
+      fill_var_val!(VL[1..$])(match);
+    }
+  }
+
+  override ubvec!32 get_bin() {
+    enum params = riscv_instr_params[instr_n];
+    ubvec!32 mask = params._mask;
+    ubvec!32 match = params._match;
+
+    ubvec!32 retval = match;
+    
+    
+    enum var_list = params._var_list;
+
+    fill_var_val!(var_list)(retval);
+    
+    return retval;
+  }
+
+  // static if (hasReg(riscv_instr_var_t.rs1)) {
+  //   @rand ubvec!5 rs1;
+  // }
+
+  
+  enum riscv_instr_name_t RISCV_INSTR_NAME = instr_n;
+  // enum RISCV_INSTR_VAR_T = riscv_opcode_params_list[instr_n]._var_t;
+  // pragma (msg, riscv_opcode_params_list[instr_n]);
+  // enum RISCV_VAR = riscv_instr_variables[instr_n];
+  // enum HAS_RS1 = hasReg(riscv_instr_var_t.rs1, RISCV_VAR);
+
+  enum RISCV_PARAMS = riscv_instr_params[instr_n];
+  static assert (RISCV_PARAMS._name == instr_n);
+  enum HAS_RS1 = hasReg(riscv_instr_var_t.rs1, RISCV_PARAMS._var_list);
+
+  // pragma(msg, riscv_instr_var_mixin(RISCV_PARAMS._var_list));
+  mixin(riscv_instr_var_mixin(RISCV_PARAMS._var_list));
+
+  // pragma(msg, instr_n.stringof ~ " " ~ HAS_RS1.stringof);
   mixin uvm_object_utils;
   this(string name="") {
     super(name);
@@ -153,17 +246,73 @@ mixin template RISCV_INSTR_MIXIN(riscv_instr_name_t instr_n,
     set_imm_len();
     set_rand_mode();
   }
+
+  // override void post_randomize() {
+  //   print_class_info(this);
+  // }
+
+  static if (instr_n == riscv_instr_name_t.SLLIW ||
+	     instr_n == riscv_instr_name_t.SRLIW ||
+	     instr_n == riscv_instr_name_t.SRAIW) {
+    import esdl.rand: constraint;
+    constraint!q{
+      imm[5..12] == 0;
+    } imm_sw_cstr;
+  }
+
+  static if (instr_n == riscv_instr_name_t.SLLI ||
+	     instr_n == riscv_instr_name_t.SRLI ||
+	     instr_n == riscv_instr_name_t.SRAI) {
+    import riscv.gen.target: XLEN;
+    import esdl.rand: constraint;
+    static if (XLEN) {
+      constraint!q{
+	imm[5..12] == 0;
+      }  imm_s_cstr;
+    }
+    else {
+    import esdl.rand: constraint;
+      constraint!q{
+	imm[6:0] == 0;
+      } imm_s_cstr;
+    }
+  }
+
 }
 
-class RISCV_VA_INSTR_TMPL(string ext, riscv_instr_name_t instr_n,
-			  riscv_instr_format_t instr_format,
-			  riscv_instr_category_t instr_category,
-			  riscv_instr_group_t instr_group,
-			  imm_t imm_tp,
-			  BASE_TYPE,
-			  vav...): BASE_TYPE
+mixin template RISCV_C_INSTR_MIXIN(riscv_instr_name_t instr_n,
+				   riscv_instr_format_t instr_format,
+				   riscv_instr_category_t instr_category,
+				   riscv_instr_group_t instr_group,
+				   imm_t imm_tp=imm_t.IMM)
 {
-  enum riscv_instr_name_t RISCV_INSTR_NAME_T = instr_n;
+  import riscv.gen.riscv_opcodes_pkg;
+  import esdl.rand: constraint;
+  import riscv.gen.riscv_instr_pkg: riscv_reg_t;
+
+  static bool hasReg(riscv_instr_var_t r, riscv_instr_var_t[] vars) {
+    foreach (var; vars) if (var is r) return true;
+      else continue;
+    return false;
+  }
+
+  static bool hasReg(riscv_instr_var_t[] regs, riscv_instr_var_t[] vars) {
+    foreach (r; regs) if (hasReg(r, vars)) return true;
+      else continue;
+    return false;
+  }
+
+  enum riscv_instr_name_t RISCV_INSTR_NAME = instr_n;
+  // enum RISCV_INSTR_VAR_T = riscv_opcode_params_list[instr_n]._var_t;
+  // pragma (msg, riscv_opcode_params_list[instr_n]);
+  // enum RISCV_VAR = riscv_instr_variables[instr_n];
+  // enum HAS_RS1 = hasReg(riscv_instr_var_t.rs1, RISCV_VAR);
+
+  enum RISCV_PARAMS = riscv_instr_params[instr_n];
+  static assert (RISCV_PARAMS._name == instr_n);
+  enum HAS_RS1 = hasReg(riscv_instr_var_t.rs1, RISCV_PARAMS._var_list);
+
+  // pragma(msg, instr_n.stringof ~ " " ~ HAS_RS1.stringof);
   mixin uvm_object_utils;
   this(string name="") {
     super(name);
@@ -172,20 +321,147 @@ class RISCV_VA_INSTR_TMPL(string ext, riscv_instr_name_t instr_n,
     this.group = instr_group;
     this.category = instr_category;
     this.imm_type = imm_tp;
-    this.allowed_va_variants = [vav];
-    this.sub_extension = ext;
     set_imm_len();
     set_rand_mode();
   }
+
+  // override void post_randomize() {
+  //   print_class_info(this);
+  // }
+
+  static if (imm_tp == imm_t.NZIMM || imm_tp == imm_t.NZUIMM) {
+    constraint! q{
+      imm[0..6] != 0;
+    } c_imm_val_cst;
+  }
+
+  static if (RISCV_INSTR_NAME == riscv_instr_name_t.C_LUI) {
+    // TODO(taliu) Check why bit 6 cannot be zero
+    constraint! q{
+      imm[5..32] == 0;
+    } c_lui_imm_val_cst;
+  }
+
+  static if (RISCV_INSTR_NAME == riscv_instr_name_t.C_SRAI ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_SRLI ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_SLLI) {
+    constraint! q{
+      imm[5..32] == 0;
+    } c_sh_imm_val_cst;
+  }
+
+  static if (RISCV_INSTR_NAME == riscv_instr_name_t.C_ADDI4SPN) {
+    constraint! q{
+      imm[0..2] == 0;
+    } imm_addi4spn_cst;
+  }
+
+  static if (RISCV_INSTR_NAME == riscv_instr_name_t.C_ADDI16SP) {
+    constraint! q{
+      rd  == riscv_reg_t.SP;
+    } c_addi16sp_sp_cst;
+  }
+
+  static if (RISCV_INSTR_NAME == riscv_instr_name_t.C_JR ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_JALR) {
+    constraint! q{
+      rs2 == riscv_reg_t.ZERO;
+      rs1 != riscv_reg_t.ZERO;
+    } c_j_cst;
+  }
+
+  static if (RISCV_INSTR_NAME == riscv_instr_name_t.C_ADDI ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_ADDIW ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_LI ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_LUI ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_SLLI ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_SLLI64 ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_LQSP ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_LDSP ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_MV ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_ADD ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_LWSP) {
+    constraint! q{
+      rd != riscv_reg_t.ZERO;
+    } c_rdn0_cst;
+  }
+
+  static if (RISCV_INSTR_NAME == riscv_instr_name_t.C_JR) {
+    constraint! q{
+      rs1 != riscv_reg_t.ZERO;
+    } c_rs1n0_cst;
+  }
+
+  static if (RISCV_INSTR_NAME == riscv_instr_name_t.C_ADD ||
+	     RISCV_INSTR_NAME == riscv_instr_name_t.C_MV) {
+    constraint! q{
+      rs2 != riscv_reg_t.ZERO;
+    } c_rs2n0_cst;
+  }
+
+  static if (RISCV_INSTR_NAME == riscv_instr_name_t.C_LUI) {
+    constraint! q{
+      rd != riscv_reg_t.SP;
+    } c_rdnsp_cst;
+  }
+  
+  static if (hasReg(riscv_instr_var_t.rs1_p, RISCV_PARAMS._var_list) ||
+	     hasReg(riscv_instr_var_t.rd_rs1_p, RISCV_PARAMS._var_list) ||
+	     hasReg(riscv_instr_var_t.c_sreg1, RISCV_PARAMS._var_list)) {
+    constraint! q{
+      rs1 inside [riscv_reg_t.S0:riscv_reg_t.A5];
+    } c_rs1_cst;
+  }
+
+  static if (hasReg(riscv_instr_var_t.rs2_p, RISCV_PARAMS._var_list) ||
+	     hasReg(riscv_instr_var_t.c_sreg2, RISCV_PARAMS._var_list)) {
+    constraint! q{
+      rs2 inside [riscv_reg_t.S0:riscv_reg_t.A5];
+    } c_rs2_cst;
+  }
+
+  static if (hasReg(riscv_instr_var_t.rd_p, RISCV_PARAMS._var_list) ||
+	     hasReg(riscv_instr_var_t.rd_rs1_p, RISCV_PARAMS._var_list)) {
+    constraint! q{
+      rd inside [riscv_reg_t.S0:riscv_reg_t.A5];
+    } c_rd_cst;
+  }
+
+  
+  
+
+
 }
+// class RISCV_VA_INSTR_TMPL(string ext, riscv_instr_name_t instr_n,
+// 			  riscv_instr_format_t instr_format,
+// 			  riscv_instr_category_t instr_category,
+// 			  riscv_instr_group_t instr_group,
+// 			  imm_t imm_tp,
+// 			  BASE_TYPE,
+// 			  vav...): BASE_TYPE
+// {
+//   enum riscv_instr_name_t RISCV_INSTR_NAME = instr_n;
+//   mixin uvm_object_utils;
+//   this(string name="") {
+//     super(name);
+//     this.instr_name = instr_n;
+//     this.instr_format = instr_format;
+//     this.group = instr_group;
+//     this.category = instr_category;
+//     this.imm_type = imm_tp;
+//     this.allowed_va_variants = [vav];
+//     this.sub_extension = ext;
+//     set_imm_len();
+//     set_rand_mode();
+//   }
+// }
 
 mixin template RISCV_VA_INSTR_MIXIN(string ext, riscv_instr_name_t instr_n,
 				    riscv_instr_format_t instr_format,
 				    riscv_instr_category_t instr_category,
-				    riscv_instr_group_t instr_group,
-				    vav...)
+				    riscv_instr_group_t instr_group)
 {
-  enum riscv_instr_name_t RISCV_INSTR_NAME_T = instr_n;
+  enum riscv_instr_name_t RISCV_INSTR_NAME = instr_n;
   mixin uvm_object_utils;
   this(string name="") {
     super(name);
@@ -194,20 +470,23 @@ mixin template RISCV_VA_INSTR_MIXIN(string ext, riscv_instr_name_t instr_n,
     this.group = instr_group;
     this.category = instr_category;
     this.imm_type = imm_t.IMM;
-    this.allowed_va_variants = [vav];
+    this.allowed_va_variants = [];
     this.sub_extension = ext;
     set_imm_len();
     set_rand_mode();
   }
+  override void post_randomize() {
+    print_class_info(this);
+  }
+
 }
 
 mixin template RISCV_VA_INSTR_MIXIN(riscv_instr_name_t instr_n,
 				    riscv_instr_format_t instr_format,
 				    riscv_instr_category_t instr_category,
-				    riscv_instr_group_t instr_group,
-				    vav...)
+				    riscv_instr_group_t instr_group)
 {
-  enum riscv_instr_name_t RISCV_INSTR_NAME_T = instr_n;
+  enum riscv_instr_name_t RISCV_INSTR_NAME = instr_n;
   mixin uvm_object_utils;
   this(string name="") {
     super(name);
@@ -216,115 +495,128 @@ mixin template RISCV_VA_INSTR_MIXIN(riscv_instr_name_t instr_n,
     this.group = instr_group;
     this.category = instr_category;
     this.imm_type = imm_t.IMM;
-    this.allowed_va_variants = [vav];
+    this.allowed_va_variants = [];
     this.sub_extension = "";
     set_imm_len();
     set_rand_mode();
   }
+  override void post_randomize() {
+    print_class_info(this);
+  }
+
 }
 
 alias riscv_instr_mixin = riscv_instr_mixin_tmpl!riscv_instr;
 
-alias RISCV_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
-		  riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
-		  imm_t imm_tp = imm_t.IMM) =
-  RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
-		    riscv_instr);
-
-alias riscv_fp_instr_mixin = riscv_instr_mixin_tmpl!riscv_floating_point_instr;
-
-alias RISCV_FP_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
-		     riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
-		     imm_t imm_tp = imm_t.IMM) =
-  RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
-		    riscv_floating_point_instr);
-
-alias riscv_amo_instr_mixin = riscv_instr_mixin_tmpl!riscv_amo_instr;
-
-alias RISCV_AMO_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
-		      riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
-		      imm_t imm_tp = imm_t.IMM) =
-  RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
-		    riscv_amo_instr);
-
-alias riscv_c_instr_mixin = riscv_instr_mixin_tmpl!riscv_compressed_instr;
-
-alias RISCV_C_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
-		    riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
-		    imm_t imm_tp = imm_t.IMM) =
-  RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
-		    riscv_compressed_instr);
-
-alias riscv_fc_instr_mixin = riscv_instr_mixin_tmpl!riscv_compressed_instr;
-
-alias RISCV_FC_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
-		     riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
-		     imm_t imm_tp = imm_t.IMM) =
-  RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
-		    riscv_compressed_instr);
-
-alias riscv_va_instr_mixin = riscv_va_instr_mixin_tmpl!riscv_vector_instr;
-
-alias RISCV_VA_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
-		     riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
-		     vav...) =
-  RISCV_VA_INSTR_TMPL!("", instr_n, instr_format, instr_category, instr_group, imm_t.IMM,
-		       riscv_vector_instr, vav);
-
-alias RISCV_VA_INSTR(string ext, riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
-		     riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
-		     vav...) =
-  RISCV_VA_INSTR_TMPL!(ext, instr_n, instr_format, instr_category, instr_group, imm_t.IMM,
-		       riscv_vector_instr, vav);
-
-alias riscv_custom_instr_mixin = riscv_instr_mixin_tmpl!riscv_custom_instr;
-
-alias RISCV_CUSTOM_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
-			 riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
-			 imm_t imm_tp = imm_t.IMM) =
-  RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
-		    riscv_custom_instr);
-
-alias riscv_b_instr_mixin = riscv_instr_mixin_tmpl!riscv_b_instr;
-
-alias RISCV_B_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
-		    riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
-		    imm_t imm_tp = imm_t.IMM) =
-  RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
-		    riscv_b_instr);
-
-//Zba-extension instruction
-alias riscv_zba_instr_mixin = riscv_instr_mixin_tmpl!riscv_zba_instr;
-
-alias RISCV_ZBA_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
-		      riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
-		      imm_t imm_tp = imm_t.IMM)	=
-  RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
-		    riscv_zba_instr);
-
-//Zbb-extension instruction
-alias riscv_zbb_instr_mixin = riscv_instr_mixin_tmpl!riscv_zbb_instr;
-
-alias RISCV_ZBB_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
-		      riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
-		      imm_t imm_tp = imm_t.IMM)	=
-  RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
-		    riscv_zbb_instr);
-
-//Zbc-extension instruction
-alias riscv_zbc_instr_mixin = riscv_instr_mixin_tmpl!riscv_zbc_instr;
-
-alias RISCV_ZBC_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
-		      riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
-		      imm_t imm_tp = imm_t.IMM)	=
-  RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
-		    riscv_zbc_instr);
-
-//Zbs-extension instruction
-alias riscv_zbs_instr_mixin = riscv_instr_mixin_tmpl!riscv_zbs_instr;
-
-alias RISCV_ZBS_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
-		      riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
-		      imm_t imm_tp = imm_t.IMM)	=
-  RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
-		    riscv_zbs_instr);
+// alias RISCV_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 		  riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 		  imm_t imm_tp = imm_t.IMM) =
+//   RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
+// 		    riscv_instr);
+
+// alias RISCV_CSR_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 		  riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 		  imm_t imm_tp = imm_t.IMM) =
+//   RISCV_CSR_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
+// 		    riscv_csr_instr);
+
+// alias riscv_csr_instr_mixin = riscv_instr_mixin_tmpl!riscv_csr_instr;
+
+// alias riscv_fp_instr_mixin = riscv_instr_mixin_tmpl!riscv_floating_point_instr;
+
+// alias RISCV_FP_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 		     riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 		     imm_t imm_tp = imm_t.IMM) =
+//   RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
+// 		    riscv_floating_point_instr);
+
+// alias riscv_amo_instr_mixin = riscv_instr_mixin_tmpl!riscv_amo_instr;
+
+// alias RISCV_AMO_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 		      riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 		      imm_t imm_tp = imm_t.IMM) =
+//   RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
+// 		    riscv_amo_instr);
+
+// alias riscv_c_instr_mixin = riscv_instr_mixin_tmpl!riscv_compressed_instr;
+
+// alias RISCV_C_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 		    riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 		    imm_t imm_tp = imm_t.IMM) =
+//   RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
+// 		    riscv_compressed_instr);
+
+// alias riscv_fc_instr_mixin = riscv_instr_mixin_tmpl!riscv_floating_point_instr;
+
+// alias RISCV_FC_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 		     riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 		     imm_t imm_tp = imm_t.IMM) =
+//   RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
+// 		    riscv_floating_point_instr);
+
+// alias riscv_va_instr_mixin = riscv_va_instr_mixin_tmpl!riscv_vector_instr;
+
+// alias RISCV_VA_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 		     riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 		     vav...) =
+//   RISCV_VA_INSTR_TMPL!("", instr_n, instr_format, instr_category, instr_group, imm_t.IMM,
+// 		       riscv_vector_instr, vav);
+
+// alias RISCV_VA_INSTR(string ext, riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 		     riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 		     vav...) =
+//   RISCV_VA_INSTR_TMPL!(ext, instr_n, instr_format, instr_category, instr_group, imm_t.IMM,
+// 		       riscv_vector_instr, vav);
+
+// alias riscv_custom_instr_mixin = riscv_instr_mixin_tmpl!riscv_custom_instr;
+
+// alias RISCV_CUSTOM_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 			 riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 			 imm_t imm_tp = imm_t.IMM) =
+//   RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
+// 		    riscv_custom_instr);
+
+// alias riscv_b_instr_mixin = riscv_instr_mixin_tmpl!riscv_b_instr;
+
+// alias RISCV_B_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 		    riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 		    imm_t imm_tp = imm_t.IMM) =
+//   RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
+// 		    riscv_b_instr);
+
+// //Zba-extension instruction
+// alias riscv_zba_instr_mixin = riscv_instr_mixin_tmpl!riscv_zba_instr;
+
+// alias RISCV_ZBA_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 		      riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 		      imm_t imm_tp = imm_t.IMM)	=
+//   RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
+// 		    riscv_zba_instr);
+
+// //Zbb-extension instruction
+// alias riscv_zbb_instr_mixin = riscv_instr_mixin_tmpl!riscv_zbb_instr;
+
+// alias RISCV_ZBB_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 		      riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 		      imm_t imm_tp = imm_t.IMM)	=
+//   RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
+// 		    riscv_zbb_instr);
+
+// //Zbc-extension instruction
+// alias riscv_zbc_instr_mixin = riscv_instr_mixin_tmpl!riscv_zbc_instr;
+
+// alias RISCV_ZBC_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 		      riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 		      imm_t imm_tp = imm_t.IMM)	=
+//   RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
+// 		    riscv_zbc_instr);
+
+// //Zbs-extension instruction
+// alias riscv_zbs_instr_mixin = riscv_instr_mixin_tmpl!riscv_zbs_instr;
+
+// alias RISCV_ZBS_INSTR(riscv_instr_name_t instr_n, riscv_instr_format_t instr_format,
+// 		      riscv_instr_category_t instr_category, riscv_instr_group_t instr_group,
+// 		      imm_t imm_tp = imm_t.IMM)	=
+//   RISCV_INSTR_TMPL!(instr_n, instr_format, instr_category, instr_group, imm_tp,
+// 		    riscv_zbs_instr)
+  ;
diff --git a/euvm/riscv/gen/riscv_directed_instr_lib.d b/euvm/riscv/gen/riscv_directed_instr_lib.d
index db2adce8..5f2f97ce 100644
--- a/euvm/riscv/gen/riscv_directed_instr_lib.d
+++ b/euvm/riscv/gen/riscv_directed_instr_lib.d
@@ -31,7 +31,7 @@ import std.algorithm: canFind;
 
 import esdl.rand: rand, constraint, randomize_with, randomize;
 import esdl.base.rand: urandom, shuffle;
-import esdl.data.bvec: ubvec, toubvec;
+import esdl.data.bvec: ubvec, UBVEC;
 import uvm;
 
 class riscv_directed_instr_stream: riscv_rand_instr_stream
@@ -93,21 +93,25 @@ class riscv_mem_access_stream : riscv_directed_instr_stream
 
   // Use "la" instruction to initialize the base regiseter
   void add_rs1_init_la_instr(riscv_reg_t gpr, int id, int base = 0) {
+    import std.format: sformat;
     riscv_pseudo_instr la_instr;
     la_instr = riscv_pseudo_instr.type_id.create("la_instr");
     la_instr.pseudo_instr_name = riscv_pseudo_instr_name_t.LA;
     la_instr.rd = gpr;
     if (load_store_shared_memory) {
-      la_instr.imm_str = format("%0s+%0d", cfg.amo_region[id].name, base);
+      la_instr.imm_str = cast(string)
+	sformat!("%0s+%0d")(la_instr.imm_str_buf(), cfg.amo_region[id].name, base);
 
     }
     else if(kernel_mode) {
-      la_instr.imm_str = format("%0s%0s+%0d",
-				hart_prefix(hart), cfg.s_mem_region[id].name, base);
+      la_instr.imm_str = cast(string)
+	sformat!("%0s%0s+%0d")(la_instr.imm_str_buf(),
+			       hart_prefix(hart), cfg.s_mem_region[id].name, base);
     }
     else {
-      la_instr.imm_str = format("%0s%0s+%0d",
-				hart_prefix(hart), cfg.mem_region[id].name, base);
+      la_instr.imm_str = cast(string)
+	sformat!("%0s%0s+%0d")(la_instr.imm_str_buf(),
+			       hart_prefix(hart), cfg.mem_region[id].name, base);
     }
     prepend_instr(la_instr);
   }
@@ -179,6 +183,8 @@ class riscv_jump_instr: riscv_directed_instr_stream
   }
 
   override void post_randomize() {
+    import std.format: sformat;
+
     riscv_instr[] instr;
     jump.randomize_with! q{
       if (has_rd == true) {
@@ -202,17 +208,17 @@ class riscv_jump_instr: riscv_directed_instr_stream
     if (jump.instr_name.inside(riscv_instr_name_t.JALR, riscv_instr_name_t.C_JALR)) {
       // JALR is expected to set lsb to 0
       int offset = urandom!q{[]}(0, 1);
-      addi.imm_str = format("%0d", imm + offset);
+      addi.imm_str = cast(string) sformat!("%0d")(addi.imm_str_buf(), imm + offset);
     }
     else {
-      addi.imm_str = format("%0d", imm);
+      addi.imm_str = cast(string) sformat!("%0d")(addi.imm_str_buf(), imm);
     }
     if (cfg.enable_misaligned_instr) {
       // Jump to a misaligned address
-      jump.imm_str = format("%0d", -imm + 2);
+      jump.imm_str = cast(string) sformat!("%0d")(jump.imm_str_buf(), -imm + 2);
     }
     else {
-      jump.imm_str = format("%0d", -imm);
+      jump.imm_str = cast(string) sformat!("%0d")(jump.imm_str_buf(), -imm);
     }
     // The branch instruction is always inserted right before the jump instruction to avoid
     // skipping other required instructions like restore stack, load jump base etc.
@@ -246,6 +252,8 @@ class riscv_jump_instr: riscv_directed_instr_stream
 // Stress back to back jump instruction
 class riscv_jal_instr : riscv_rand_instr_stream
 {
+  import std.format: sformat;
+  
   riscv_instr[]        jump;
   riscv_instr          jump_start;
   riscv_instr          jump_end;
@@ -263,6 +271,8 @@ class riscv_jal_instr : riscv_rand_instr_stream
   }
 
   void post_randomize() {
+    import std.format: sformat;
+
     int[]  order;
     order.length  = num_of_jump_instr;
     jump.length  = num_of_jump_instr;
@@ -282,18 +292,19 @@ class riscv_jal_instr : riscv_rand_instr_stream
     jump_start = cfg.instr_registry.get_instr(riscv_instr_name_t.JAL);
     //`DV_CHECK_RANDOMIZE_WITH_FATAL(jump_start, rd == cfg.ra;)
     jump_start.randomize_with! q{rd == $0;} (cfg.ra);
-    jump_start.imm_str = format("%0df", order[0]);
+    jump_start.imm_str = cast(string) sformat!("%0df")(jump_start.imm_str_buf(), order[0]);
     jump_start.label = label;
     // Last instruction
     randomize_instr(jump_end);
-    jump_end.label = format("%0d", num_of_jump_instr);
+    jump_end.label = format!("%0d")(num_of_jump_instr);
     foreach (i, ref jj ; jump) {
       jj = cfg.instr_registry.get_rand_instr(jal);
       //DV_CHECK_RANDOMIZE_WITH_FATAL(jump[i],
       // Giving randomization error
       jj.randomize_with! q{
 	if (has_rd == true ) {
-	  rd dist [riscv_reg_t.RA := 5, riscv_reg_t.T1 := 2, riscv_reg_t.SP..riscv_reg_t.T0 :/ 1, riscv_reg_t.T2..riscv_reg_t.T6 :/ 2];
+	  rd dist [riscv_reg_t.RA := 5, riscv_reg_t.T1 := 2,
+		   riscv_reg_t.SP..riscv_reg_t.T0 :/ 1, riscv_reg_t.T2..riscv_reg_t.T6 :/ 2];
 	  rd !inside [$0];
 	}
       } (cfg.reserved_regs);
@@ -301,14 +312,17 @@ class riscv_jal_instr : riscv_rand_instr_stream
     }
     foreach (i, rr; order) {
       if (i == num_of_jump_instr - 1) {
-	jump[rr].imm_str = format("%0df", num_of_jump_instr);
+	jump[rr].imm_str = cast(string)
+	  sformat!("%0df")(jump[rr].imm_str_buf(), num_of_jump_instr);
       }
       else {
 	if (order[i+1] > rr) {
-          jump[rr].imm_str = format("%0df", order[i+1]);
+          jump[rr].imm_str = cast(string)
+	    sformat!("%0df")(jump[rr].imm_str_buf(), order[i+1]);
 	}
 	else {
-          jump[rr].imm_str = format("%0db", order[i+1]);
+          jump[rr].imm_str = cast(string)
+	    sformat!("%0db")(jump[rr].imm_str_buf(), order[i+1]);
 	}
       }
     }
@@ -322,7 +336,7 @@ class riscv_jal_instr : riscv_rand_instr_stream
 }
 
 // Push stack instruction stream
-class riscv_push_stack_instr : riscv_rand_instr_stream
+class riscv_push_stack_instr: riscv_rand_instr_stream
 {
   int                      stack_len;
   int                      num_of_reg_to_save;
@@ -353,6 +367,8 @@ class riscv_push_stack_instr : riscv_rand_instr_stream
   }
 
   void gen_push_stack_instr(int stack_len, bool allow_branch = true) {
+    import std.format: sformat;
+
     this.stack_len = stack_len;
     init();
     gen_instr(true);
@@ -365,7 +381,8 @@ class riscv_push_stack_instr : riscv_rand_instr_stream
     //DV_CHECK_RANDOMIZE_WITH_FATAL(push_stack_instr[0],
     push_stack_instr[0].randomize_with! q{ rd == $0; rs1 == $0;
       imm == $1;} (cfg.sp, ~stack_len + 1);
-    push_stack_instr[0].imm_str = format("-%0d", stack_len);
+    push_stack_instr[0].imm_str = cast(string)
+      sformat!("-%0d")(push_stack_instr[0].imm_str_buf(), stack_len);
     foreach (i, sreg;  saved_regs) {
       if (XLEN == 32) {
         push_stack_instr[i+1] = cfg.instr_registry.get_instr(riscv_instr_name_t.SW);
@@ -441,6 +458,7 @@ class riscv_pop_stack_instr: riscv_rand_instr_stream
   }
 
   void gen_pop_stack_instr(int stack_len, riscv_reg_t[] saved_regs) {
+    import std.format: sformat;
     this.stack_len = stack_len;
     this.saved_regs = saved_regs;
     init();
@@ -472,7 +490,8 @@ class riscv_pop_stack_instr: riscv_rand_instr_stream
     pop_stack_instr[num_of_reg_to_save].randomize_with! q{
       rd == $0; rs1 == $0; imm == $1;
     } ( cfg.sp, stack_len);
-    pop_stack_instr[num_of_reg_to_save].imm_str = format("%0d", stack_len);
+    pop_stack_instr[num_of_reg_to_save].imm_str = cast(string)
+      sformat!("%0d")(pop_stack_instr[num_of_reg_to_save].imm_str_buf(), stack_len);
     mix_instr_stream(pop_stack_instr);
     foreach (instr; instr_list) {
       instr.atomic = true;
@@ -494,7 +513,7 @@ class riscv_int_numeric_corner_stream: riscv_directed_instr_stream
 
   uint                  num_of_avail_regs = 10;
   @rand uint            num_of_instr;
-  @rand ubvec!XLEN[]    init_val; // becasue of compile error it has been commented.
+  @rand ubvec!XLEN[]    init_val;
   @rand int_numeric_e[] init_val_type;
   riscv_pseudo_instr[]  init_instr;
 
@@ -525,21 +544,23 @@ class riscv_int_numeric_corner_stream: riscv_directed_instr_stream
   }
 
   override  void post_randomize() {
+    import std.format: sformat;
     init_instr.length = num_of_avail_regs;
     foreach (i, ref ivtype; init_val_type) {
       if (ivtype == int_numeric_e.Zero) {
-        init_val[i] = toubvec!XLEN(0);
+        init_val[i] = UBVEC!(XLEN, 0);
       }
       else if (ivtype == int_numeric_e.AllOne) {
-        init_val[i] = toubvec!XLEN(-1);
+        init_val[i] = UBVEC!(XLEN, -1);
       }
       else if (ivtype == int_numeric_e.NegativeMax) {
-        init_val[i] = toubvec!XLEN(1UL << (XLEN-1));
+        init_val[i] = UBVEC!(XLEN, 1UL << (XLEN-1));
       }
       init_instr[i] = new riscv_pseudo_instr;
       init_instr[i].rd = avail_regs[i];
       init_instr[i].pseudo_instr_name = riscv_pseudo_instr_name_t.LI;
-      init_instr[i].imm_str = format("0x%0x", init_val[i]);
+      init_instr[i].imm_str = cast(string)
+	sformat!("0x%0x")(init_instr[i].imm_str_buf(), init_val[i]);
       append_instr(init_instr[i]);
     }
     for (int i = 0; i < num_of_instr; i++) {
diff --git a/euvm/riscv/gen/riscv_illegal_instr.d b/euvm/riscv/gen/riscv_illegal_instr.d
index 0f16a64b..5b3de079 100644
--- a/euvm/riscv/gen/riscv_illegal_instr.d
+++ b/euvm/riscv/gen/riscv_illegal_instr.d
@@ -31,7 +31,7 @@ import std.traits: EnumMembers;
 import std.format: format;
 import std.algorithm: canFind;
 
-import esdl.data.bvec: ubvec, toubvec;
+import esdl.data.bvec: ubvec, UBVEC;
 import esdl.rand: rand, constraint;
 
 import uvm;
@@ -72,26 +72,26 @@ class riscv_illegal_instr: uvm_object
   }
 
   // Default legal opcode for RV32I instructions
-  ubvec!7[]  legal_opcode = [0b0000011.toubvec!7,
-			     0b0001111.toubvec!7,
-			     0b0010011.toubvec!7,
-			     0b0010111.toubvec!7,
-			     0b0100011.toubvec!7,
-			     0b0110111.toubvec!7,
-			     0b1100011.toubvec!7,
-			     0b0110011.toubvec!7,
-			     0b1100111.toubvec!7,
-			     0b1110011.toubvec!7,
-			     0b1101111.toubvec!7];
+  ubvec!7[]  legal_opcode = [UBVEC!(7, 0b0000011),
+			     UBVEC!(7, 0b0001111),
+			     UBVEC!(7, 0b0010011),
+			     UBVEC!(7, 0b0010111),
+			     UBVEC!(7, 0b0100011),
+			     UBVEC!(7, 0b0110111),
+			     UBVEC!(7, 0b1100011),
+			     UBVEC!(7, 0b0110011),
+			     UBVEC!(7, 0b1100111),
+			     UBVEC!(7, 0b1110011),
+			     UBVEC!(7, 0b1101111)];
 
   // Default legal opcode for RV32C instructions
-  ubvec!3[] legal_c00_opcode = [0b000.toubvec!3,
-				0b010.toubvec!3,
-				0b110.toubvec!3];
-  ubvec!3[] legal_c10_opcode = [0b000.toubvec!3,
-				0b010.toubvec!3,
-				0b100.toubvec!3,
-				0b110.toubvec!3];
+  ubvec!3[] legal_c00_opcode = [UBVEC!(3, 0b000),
+				UBVEC!(3, 0b010),
+				UBVEC!(3, 0b110)];
+  ubvec!3[] legal_c10_opcode = [UBVEC!(3, 0b000),
+				UBVEC!(3, 0b010),
+				UBVEC!(3, 0b100),
+				UBVEC!(3, 0b110)];
 
   @rand illegal_instr_type_e  exception;
   @rand reserved_c_instr_e    reserved_c;
@@ -433,23 +433,23 @@ class riscv_illegal_instr: uvm_object
     this.cfg = cfg;
     if ((canFind(supported_isa, riscv_instr_group_t.RV32F) ||
 	 canFind(supported_isa, riscv_instr_group_t.RV32D))) {
-      legal_opcode ~= [0b0000111.toubvec!7, 0b0100111.toubvec!7, 0b1000011.toubvec!7,
-		       0b1000111.toubvec!7, 0b1001011.toubvec!7, 0b1001111.toubvec!7,
-		       0b1010011.toubvec!7] ;
+      legal_opcode ~= [UBVEC!(7, 0b0000111), UBVEC!(7, 0b0100111), UBVEC!(7, 0b1000011),
+		       UBVEC!(7, 0b1000111), UBVEC!(7, 0b1001011), UBVEC!(7, 0b1001111),
+		       UBVEC!(7, 0b1010011)] ;
     }
     if (canFind(supported_isa, riscv_instr_group_t.RV64I)) {
-      legal_opcode ~= [0b0011011.toubvec!7];
+      legal_opcode ~= [UBVEC!(7, 0b0011011)];
     }
     if (canFind(supported_isa, riscv_instr_group_t.RV32A)) {
-      legal_opcode ~= [0b0101111.toubvec!7];
+      legal_opcode ~= [UBVEC!(7, 0b0101111)];
     }
     if (canFind(supported_isa, riscv_instr_group_t.RV64I)  ||
 	canFind(supported_isa,  riscv_instr_group_t.RV64M )) {
-      legal_opcode ~= [0b0111011.toubvec!7];
+      legal_opcode ~= [UBVEC!(7, 0b0111011)];
     }
     if (canFind(supported_isa, riscv_instr_group_t.RV64I)) {
-      legal_c00_opcode ~= [0b011.toubvec!3, 0b111.toubvec!3];
-      legal_c10_opcode ~= [0b011.toubvec!3, 0b111.toubvec!3];
+      legal_c00_opcode ~= [UBVEC!(3, 0b011), UBVEC!(3, 0b111)];
+      legal_c10_opcode ~= [UBVEC!(3, 0b011), UBVEC!(3, 0b111)];
     }
     // csr = csr.first();
     // for (int i = 0; i < csr.num(); i = i + 1) begin
diff --git a/euvm/riscv/gen/riscv_instr_gen_config.d b/euvm/riscv/gen/riscv_instr_gen_config.d
index 1397dcec..73ea35b8 100644
--- a/euvm/riscv/gen/riscv_instr_gen_config.d
+++ b/euvm/riscv/gen/riscv_instr_gen_config.d
@@ -23,14 +23,15 @@ module riscv.gen.riscv_instr_gen_config;
 import riscv.gen.riscv_instr_pkg: data_pattern_t, vreg_init_method_t, exception_cause_t,
   interrupt_cause_t, privileged_mode_t, mtvec_mode_t, f_rounding_mode_t, riscv_reg_t,
   mem_region_t, privileged_reg_t, riscv_instr_category_t, b_ext_group_t,
-  riscv_instr_group_t, get_int_arg_value, get_bool_arg_value, get_hex_arg_value,
-  cmdline_enum_processor, satp_mode_t;
+  riscv_instr_group_t, get_int_arg_value, get_uint_arg_value,
+  get_bool_arg_value, get_hex_arg_value, cmdline_enum_processor, satp_mode_t,
+  default_include_csr_write, riscv_csr_t;
 
 import riscv.gen.riscv_instr_registry: riscv_instr_registry;
 import riscv.gen.isa.riscv_instr_register: register_isa;
 
 import riscv.gen.target: NUM_HARTS, XLEN, supported_privileged_mode, supported_isa,
-  SATP_MODE, implemented_csr, support_sfence, support_debug_mode, supported_interrupt_mode;
+  SATP_MODE, implemented_csr, support_sfence, support_debug_mode, supported_interrupt_mode, custom_csr;
 import riscv.gen.riscv_pmp_cfg: riscv_pmp_cfg;
 import riscv.gen.riscv_vector_cfg: riscv_vector_cfg;
 
@@ -125,7 +126,7 @@ class riscv_instr_gen_config: uvm_object
   // Can overlap with the other GPRs used in the random generation,
   // as PMP exception handler is hardcoded and does not include any
   // random instructions.
-  @rand riscv_reg_t       pmp_reg;
+  @rand riscv_reg_t[2]       pmp_reg;
   // Use a random register for stack pointer/thread pointer
   @rand @UVM_DEFAULT riscv_reg_t       sp;
   @rand @UVM_DEFAULT riscv_reg_t       tp;
@@ -185,6 +186,10 @@ class riscv_instr_gen_config: uvm_object
   int                    num_of_sub_program = 5;
   int                    instr_cnt = 200;
   int                    num_of_tests = 1;
+
+  uint                   par_num_threads = 8;
+  uint                   par_instr_threshold = 4000;
+
   // For tests doesn't involve load/store, the data section generation could be skipped
   @UVM_DEFAULT bool                    no_data_page;
   // Options to turn off some specific types of instructions
@@ -192,12 +197,21 @@ class riscv_instr_gen_config: uvm_object
   @UVM_DEFAULT bool                    no_load_store;      // No load/store instruction
   @UVM_DEFAULT bool                    no_csr_instr;       // No csr instruction
   @UVM_DEFAULT bool                    no_ebreak = true;      // No ebreak instruction
+  // Only enable ecall if you have overriden the test_done mechanism.
+  @UVM_DEFAULT bool                    no_ecall = true;       // No ecall instruction
   @UVM_DEFAULT bool                    no_dret = true;        // No dret instruction
   @UVM_DEFAULT bool                    no_fence;           // No fence instruction
   @UVM_DEFAULT bool                    no_wfi = true;         // No WFI instruction
   @UVM_DEFAULT bool                    enable_unaligned_load_store;
   @UVM_DEFAULT int                     illegal_instr_ratio;
   @UVM_DEFAULT int                     hint_instr_ratio;
+
+  // CSR instruction control
+  @UVM_DEFAULT bool                    gen_all_csrs_by_default = false; // Generate CSR instructions that use all supported CSRs. Other options below only take effect if this is enabled.
+  @UVM_DEFAULT bool                    gen_csr_ro_write = false;        // Generate CSR writes to read-only CSRs
+  @UVM_DEFAULT privileged_reg_t[]       add_csr_write = [];        // CSRs to add to the set of writeable CSRs
+  @UVM_DEFAULT privileged_reg_t[]       remove_csr_write = [];     // CSRs to remove from the set of writeable CSRs
+
   // Number of harts to be simulated, must be <= NUM_HARTS
   @UVM_DEFAULT int                     num_of_harts = NUM_HARTS;
   // Use SP as stack pointer
@@ -462,10 +476,13 @@ class riscv_instr_gen_config: uvm_object
     scratch_reg !inside [riscv_reg_t.ZERO, sp, tp, ra, riscv_reg_t.GP];
   } reserve_scratch_reg_c;
 
-  // This reg is only used inside PMP exception routine,
+  // These registers is only used inside PMP exception routine,
   // so we can be a bit looser with constraints.
   constraint! q{
-    pmp_reg !inside [riscv_reg_t.ZERO, sp, tp];
+    foreach (preg; pmp_reg) {
+      preg !inside [riscv_reg_t.ZERO, sp, tp, scratch_reg];
+    }
+    unique [pmp_reg];
   } reserve_pmp_reg_c;
 
 
@@ -590,8 +607,11 @@ class riscv_instr_gen_config: uvm_object
     get_bool_arg_value("+enable_nested_interrupt=", enable_nested_interrupt);
     get_bool_arg_value("+enable_timer_irq=", enable_timer_irq);
     get_int_arg_value("+num_of_sub_program=", num_of_sub_program);
+    get_uint_arg_value("+par_num_threads=", par_num_threads);
+    get_uint_arg_value("+par_instr_threshold=", par_instr_threshold);
     get_int_arg_value("+instr_cnt=", instr_cnt);
     get_bool_arg_value("+no_ebreak=", no_ebreak);
+    get_bool_arg_value("+no_ecall=", no_ecall);
     get_bool_arg_value("+no_dret=", no_dret);
     get_bool_arg_value("+no_wfi=", no_wfi);
     get_bool_arg_value("+no_branch_jump=", no_branch_jump);
@@ -610,6 +630,13 @@ class riscv_instr_gen_config: uvm_object
     get_bool_arg_value("+no_delegation=", no_delegation);
     get_int_arg_value("+illegal_instr_ratio=", illegal_instr_ratio);
     get_int_arg_value("+hint_instr_ratio=", hint_instr_ratio);
+    get_bool_arg_value("+gen_all_csrs_by_default=", gen_all_csrs_by_default);
+    get_bool_arg_value("+gen_csr_ro_write=", gen_csr_ro_write);
+    cmdline_enum_processor!(privileged_reg_t).get_array_values("+add_csr_write=",
+							       true, add_csr_write);
+    cmdline_enum_processor!(privileged_reg_t).get_array_values("+remove_csr_write=",
+							       true, remove_csr_write);
+   
     get_int_arg_value("+num_of_harts=", num_of_harts);
     get_bool_arg_value("+enable_unaligned_load_store=", enable_unaligned_load_store);
     get_bool_arg_value("+force_m_delegation=", force_m_delegation);
@@ -641,7 +668,7 @@ class riscv_instr_gen_config: uvm_object
     get_bool_arg_value("+enable_zbc_extension=", enable_zbc_extension);
     get_bool_arg_value("+enable_zbs_extension=", enable_zbs_extension);
     cmdline_enum_processor!(b_ext_group_t).get_array_values("+enable_bitmanip_groups=",
-							    enable_bitmanip_groups);
+							    false, enable_bitmanip_groups);
     if (uvm_cmdline_processor.get_inst().get_arg_value("+boot_mode=", boot_mode_opts)) {
       uvm_info(get_full_name(), format("Got boot mode option - %0s", boot_mode_opts), UVM_LOW);
       switch(boot_mode_opts) {
@@ -662,7 +689,7 @@ class riscv_instr_gen_config: uvm_object
 				     supported_privileged_mode.length), UVM_LOW);
     uvm_cmdline_processor.get_inst().get_arg_value("+asm_test_suffix=", asm_test_suffix);
     // Directed march list from the runtime options, ex. RV32I, RV32M etc.
-    cmdline_enum_processor !(riscv_instr_group_t).get_array_values("+march=", march_isa);
+    cmdline_enum_processor !(riscv_instr_group_t).get_array_values("+march=", false, march_isa);
     if (march_isa.length != 0) supported_isa = march_isa;
 
     if (!(canFind(supported_isa, riscv_instr_group_t.RV32C))) {
@@ -692,7 +719,7 @@ class riscv_instr_gen_config: uvm_object
     vector_cfg = riscv_vector_cfg.type_id.create("vector_cfg");
     pmp_cfg = riscv_pmp_cfg.type_id.create("pmp_cfg");
     rand_mode!q{pmp_cfg}(pmp_cfg.pmp_randomize);
-    pmp_cfg.initialize(require_signature_addr);
+    pmp_cfg.initialize(signature_addr);
     setup_instr_distribution();
     get_invalid_priv_lvl_csr();
   }
@@ -745,11 +772,6 @@ class riscv_instr_gen_config: uvm_object
     min_stack_len_per_program = 2 * (XLEN/8);
     // Check if the setting is legal
     check_setting();
-    // WFI is not supported in umode
-    if (init_privileged_mode == privileged_mode_t.USER_MODE) {
-      no_wfi = true;
-    }
-    instr_registry.create_instr_list(this);
   }
 
   void check_setting() {
@@ -818,4 +840,69 @@ class riscv_instr_gen_config: uvm_object
       }
     }
   }
+
+  struct csr_config {
+    // Privileged CSR filter
+    privileged_reg_t[]         exclude_reg;
+    privileged_reg_t[]         include_reg;
+    privileged_reg_t[]         include_write_reg;
+
+    bool allow_ro_write;
+
+    void create_csr_filter(riscv_instr_gen_config cfg) {
+      include_reg.length = 0;
+      exclude_reg.length = 0;
+      allow_ro_write = true;
+      
+      if (cfg.enable_illegal_csr_instruction) {
+	exclude_reg = implemented_csr;
+      }
+      else if (cfg.enable_access_invalid_csr_level) {
+	include_reg = cfg.invalid_priv_mode_csrs;
+      }
+      else if (cfg.gen_all_csrs_by_default) {
+	allow_ro_write = cfg.gen_csr_ro_write;
+	include_reg = implemented_csr;
+	foreach (i, ccsr; custom_csr) {
+	  default_include_csr_write ~= cast(riscv_csr_t) ccsr;
+	}
+
+	create_include_write_reg(cfg.add_csr_write, cfg.remove_csr_write, default_include_csr_write);
+      }
+      else {
+	// Use scratch register to avoid the side effect of modifying other privileged mode CSR.
+	if (cfg.init_privileged_mode == privileged_mode_t.MACHINE_MODE) {
+	  include_reg = [privileged_reg_t.MSCRATCH];
+	}
+	else if (cfg.init_privileged_mode == privileged_mode_t.SUPERVISOR_MODE) {
+	  include_reg = [privileged_reg_t.SSCRATCH];
+	}
+	else {
+	  include_reg = [privileged_reg_t.USCRATCH];
+	}
+      }
+    }
+
+    void create_include_write_reg(privileged_reg_t[] add_csr,
+				  privileged_reg_t[] remove_csr,
+				  riscv_csr_t[] initial_csrs) {
+      import std.algorithm.searching: canFind;
+      
+      include_write_reg.length = 0;
+
+      foreach (icsr; initial_csrs) {
+	if (!(remove_csr.canFind(initial_csrs))) {
+	  include_write_reg ~= cast(privileged_reg_t) icsr;
+	}
+      }
+
+      foreach (acsr; add_csr) {
+	include_write_reg ~= acsr;
+      }
+    }
+  }
+
+  csr_config csr_cfg;
 }
+
+  
diff --git a/euvm/riscv/gen/riscv_instr_pkg.d b/euvm/riscv/gen/riscv_instr_pkg.d
index b9287957..0c61ec46 100644
--- a/euvm/riscv/gen/riscv_instr_pkg.d
+++ b/euvm/riscv/gen/riscv_instr_pkg.d
@@ -18,11 +18,13 @@
 
 
 module riscv.gen.riscv_instr_pkg;
+public import riscv.gen.riscv_opcodes_pkg;
 
 import riscv.gen.target: XLEN, NUM_HARTS, SATP_MODE, implemented_csr;
+
 import std.traits: EnumMembers;
 
-import esdl.data.bvec: bvec, ubvec;
+import esdl.data.bvec: bvec, ubvec, toubvec, UBVEC, isBitVector;
 import esdl.rand: rand;
 import uvm;
 
@@ -45,41 +47,41 @@ enum vreg_init_method_t: ubyte {
   RANDOM_VALUES_LOAD
 }
 
-enum satp_mode_t: ubyte {
-  BARE = 0b0000,
-  SV32 = 0b0001,
-  SV39 = 0b1000,
-  SV48 = 0b1001,
-  SV57 = 0b1010,
-  SV64 = 0b1011
+enum satp_mode_t: ubvec!4 {
+  BARE = UBVEC!(4, 0b0000),
+  SV32 = UBVEC!(4, 0b0001),
+  SV39 = UBVEC!(4, 0b1000),
+  SV48 = UBVEC!(4, 0b1001),
+  SV57 = UBVEC!(4, 0b1010),
+  SV64 = UBVEC!(4, 0b1011)
 }
 
-enum f_rounding_mode_t: ubyte {
-  RNE = 0b000,
-  RTZ = 0b001,
-  RDN = 0b010,
-  RUP = 0b011,
-  RMM = 0b100
+enum f_rounding_mode_t: ubvec!3 {
+  RNE = UBVEC!(3, 0b000),
+  RTZ = UBVEC!(3, 0b001),
+  RDN = UBVEC!(3, 0b010),
+  RUP = UBVEC!(3, 0b011),
+  RMM = UBVEC!(3, 0b100)
 }
 
-enum mtvec_mode_t: ubyte {
-  DIRECT   = 0b00,
-  VECTORED = 0b01
+enum mtvec_mode_t: ubvec!2 {
+  DIRECT   = UBVEC!(2, 0b00),
+  VECTORED = UBVEC!(2, 0b01)
 }
 
-enum imm_t: ubyte {
-  IMM,    // Signed immediate
-  UIMM,   // Unsigned immediate
-  NZUIMM, // Non-zero unsigned immediate
-  NZIMM   // Non-zero signed immediate
+enum imm_t: ubvec!3 {
+  IMM    = UBVEC!(3, 0b000),    // Signed immediate
+  UIMM   = UBVEC!(3, 0b001),   // Unsigned immediate
+  NZUIMM = UBVEC!(3, 0b010), // Non-zero unsigned immediate
+  NZIMM  = UBVEC!(3, 0b011)   // Non-zero signed immediate
 }
 
 // Privileged mode
-enum privileged_mode_t: ubyte {
-  USER_MODE       = 0b00,
-  SUPERVISOR_MODE = 0b01,
-  RESERVED_MODE   = 0b10,
-  MACHINE_MODE    = 0b11
+enum privileged_mode_t: ubvec!2 {
+  USER_MODE       = UBVEC!(2, 0b00),
+  SUPERVISOR_MODE = UBVEC!(2, 0b01),
+  RESERVED_MODE   = UBVEC!(2, 0b10),
+  MACHINE_MODE    = UBVEC!(2, 0b11)
 }
 
 enum riscv_instr_group_t: ubyte {
@@ -111,344 +113,993 @@ enum riscv_instr_group_t: ubyte {
   RV64ZBC,
   RV64ZBS,
   RV32X,
-  RV64X
+  RV64X,
+  RVZPN,
+  RV32ZPN,
+  RV64ZPN
 }
 
 
-enum riscv_instr_name_t: ushort  {
-  // RV32I instructions
-  LUI,
-  AUIPC,
-  JAL,
-  JALR,
-  BEQ,
-  BNE,
-  BLT,
-  BGE,
-  BLTU,
-  BGEU,
-  LB,
-  LH,
-  LW,
-  LBU,
-  LHU,
-  SB,
-  SH,
-  SW,
-  ADDI,
-  SLTI,
-  SLTIU,
-  XORI,
-  ORI,
-  ANDI,
-  SLLI,
-  SRLI,
-  SRAI,
-  ADD,
-  SUB,
-  SLL,
-  SLT,
-  SLTU,
-  XOR,
-  SRL,
-  SRA,
-  OR,
-  AND,
-  NOP,
-  FENCE,
-  FENCE_I,
-  ECALL,
-  EBREAK,
-  CSRRW,
-  CSRRS,
-  CSRRC,
-  CSRRWI,
-  CSRRSI,
-  CSRRCI,
-  // RV32ZBA instructions
-  SH1ADD,
-  SH2ADD,
-  SH3ADD,
-  // RV32ZBB instructions
-  ANDN,
-  CLZ,
-  CPOP,
-  CTZ,
-  MAX,
-  MAXU,
-  MIN,
-  MINU,
-  ORC_B,
-  ORN,
-  REV8,
-  ROL,
-  ROR,
-  RORI,
-  SEXT_B,
-  SEXT_H,
-  XNOR,
-  ZEXT_H,
-  // RV32ZBC instructions
-  CLMUL,
-  CLMULH,
-  CLMULR,
-  // RV32ZBS instructions
-  BCLR,
-  BCLRI,
-  BEXT,
-  BEXTI,
-  BINV,
-  BINVI,
-  BSET,
-  BSETI,
-  // RV32B instructions
-  // Remaining bitmanip instructions of draft v.0.93 not ratified in v.1.00 (Zba, Zbb, Zbc, Zbs).
-  GORC,
-  GORCI,
-  CMIX,
-  CMOV,
-  PACK,
-  PACKU,
-  PACKH,
-  XPERM_N,
-  XPERM_B,
-  XPERM_H,
-  SLO,
-  SRO,
-  SLOI,
-  SROI,
-  GREV,
-  GREVI,
-  FSL,
-  FSR,
-  FSRI,
-  CRC32_B,
-  CRC32_H,
-  CRC32_W,
-  CRC32C_B,
-  CRC32C_H,
-  CRC32C_W,
-  SHFL,
-  UNSHFL,
-  SHFLI,
-  UNSHFLI,
-  BCOMPRESS,
-  BDECOMPRESS,
-  BFP,
-  // RV64ZBA instructions
-  ADD_UW,
-  SH1ADD_UW,
-  SH2ADD_UW,
-  SH3ADD_UW,
-  SLLI_UW,
-  // RV64ZBB instructions
-  CLZW,
-  CPOPW,
-  CTZW,
-  ROLW,
-  RORW,
-  RORIW,
-  //RV64B instructions
-  // Remaining bitmanip instructions of draft v.0.93 not ratified in v.1.00 (Zba, Zbb, Zbc, Zbs).
-  BMATOR,
-  BMATXOR,
-  BMATFLIP,
-  CRC32_D,
-  CRC32C_D,
-  SHFLW,
-  UNSHFLW,
-  BCOMPRESSW,
-  BDECOMPRESSW,
-  BFPW,
-  SLOW,
-  SROW,
-  SLOIW,
-  SROIW,
-  GREVW,
-  GREVIW,
-  FSLW,
-  FSRW,
-  FSRIW,
-  GORCW,
-  GORCIW,
-  PACKW,
-  PACKUW,
-  XPERM_W,
-  // RV32M instructions
-  MUL,
-  MULH,
-  MULHSU,
-  MULHU,
-  DIV,
-  DIVU,
-  REM,
-  REMU,
-  // RV64M instructions
-  MULW,
-  DIVW,
-  DIVUW,
-  REMW,
-  REMUW,
-  // RV32F instructions
-  FLW,
-  FSW,
-  FMADD_S,
-  FMSUB_S,
-  FNMSUB_S,
-  FNMADD_S,
-  FADD_S,
-  FSUB_S,
-  FMUL_S,
-  FDIV_S,
-  FSQRT_S,
-  FSGNJ_S,
-  FSGNJN_S,
-  FSGNJX_S,
-  FMIN_S,
-  FMAX_S,
-  FCVT_W_S,
-  FCVT_WU_S,
-  FMV_X_W,
-  FEQ_S,
-  FLT_S,
-  FLE_S,
-  FCLASS_S,
-  FCVT_S_W,
-  FCVT_S_WU,
-  FMV_W_X,
-  // RV64F instruction
-  FCVT_L_S,
-  FCVT_LU_S,
-  FCVT_S_L,
-  FCVT_S_LU,
-  // RV32D instructions
-  FLD,
-  FSD,
-  FMADD_D,
-  FMSUB_D,
-  FNMSUB_D,
-  FNMADD_D,
-  FADD_D,
-  FSUB_D,
-  FMUL_D,
-  FDIV_D,
-  FSQRT_D,
-  FSGNJ_D,
-  FSGNJN_D,
-  FSGNJX_D,
-  FMIN_D,
-  FMAX_D,
-  FCVT_S_D,
-  FCVT_D_S,
-  FEQ_D,
-  FLT_D,
-  FLE_D,
-  FCLASS_D,
-  FCVT_W_D,
-  FCVT_WU_D,
-  FCVT_D_W,
-  FCVT_D_WU,
-  // RV64D
-  FCVT_L_D,
-  FCVT_LU_D,
-  FMV_X_D,
-  FCVT_D_L,
-  FCVT_D_LU,
-  FMV_D_X,
-  // RV64I
-  LWU,
-  LD,
-  SD,
-  ADDIW,
-  SLLIW,
-  SRLIW,
-  SRAIW,
-  ADDW,
-  SUBW,
-  SLLW,
-  SRLW,
-  SRAW,
-  // RV32C
-  C_LW,
-  C_SW,
-  C_LWSP,
-  C_SWSP,
-  C_ADDI4SPN,
-  C_ADDI,
-  C_LI,
-  C_ADDI16SP,
-  C_LUI,
-  C_SRLI,
-  C_SRAI,
-  C_ANDI,
-  C_SUB,
-  C_XOR,
-  C_OR,
-  C_AND,
-  C_BEQZ,
-  C_BNEZ,
-  C_SLLI,
-  C_MV,
-  C_EBREAK,
-  C_ADD,
-  C_NOP,
-  C_J,
-  C_JAL,
-  C_JR,
-  C_JALR,
-  // RV64C
-  C_ADDIW,
-  C_SUBW,
-  C_ADDW,
-  C_LD,
-  C_SD,
-  C_LDSP,
-  C_SDSP,
-  // RV128C
-  C_SRLI64,
-  C_SRAI64,
-  C_SLLI64,
-  C_LQ,
-  C_SQ,
-  C_LQSP,
-  C_SQSP,
-  // RV32FC
-  C_FLW,
-  C_FSW,
-  C_FLWSP,
-  C_FSWSP,
-  // RV32DC
-  C_FLD,
-  C_FSD,
-  C_FLDSP,
-  C_FSDSP,
-  // RV32A
-  LR_W,
-  SC_W,
-  AMOSWAP_W,
-  AMOADD_W,
-  AMOAND_W,
-  AMOOR_W,
-  AMOXOR_W,
-  AMOMIN_W,
-  AMOMAX_W,
-  AMOMINU_W,
-  AMOMAXU_W,
-  // RV64A
-  LR_D,
-  SC_D,
-  AMOSWAP_D,
-  AMOADD_D,
-  AMOAND_D,
-  AMOOR_D,
-  AMOXOR_D,
-  AMOMIN_D,
-  AMOMAX_D,
-  AMOMINU_D,
-  AMOMAXU_D,
-  // Vector instructions
-  VSETVL,
-  VSETVLI,
+// enum riscv_instr_name_t: ushort {
+//   // RV32I instructions
+//   LUI,
+//   AUIPC,
+//   JAL,
+//   JALR,
+//   BEQ,
+//   BNE,
+//   BLT,
+//   BGE,
+//   BLTU,
+//   BGEU,
+//   LB,
+//   LH,
+//   LW,
+//   LBU,
+//   LHU,
+//   SB,
+//   SH,
+//   SW,
+//   ADDI,
+//   SLTI,
+//   SLTIU,
+//   XORI,
+//   ORI,
+//   ANDI,
+//   SLLI,
+//   SRLI,
+//   SRAI,
+//   ADD,
+//   SUB,
+//   SLL,
+//   SLT,
+//   SLTU,
+//   XOR,
+//   SRL,
+//   SRA,
+//   OR,
+//   AND,
+//   NOP,
+//   FENCE,
+//   FENCE_I,
+//   FENCE_TSO,
+//   PAUSE,
+//   ECALL,
+//   SCALL,
+//   EBREAK,
+//   SBREAK,
+//   // RV32ZBA instructions
+//   SH1ADD,
+//   SH2ADD,
+//   SH3ADD,
+//   // RV32ZBB instructions
+//   ANDN,
+//   CLZ,
+//   CPOP,
+//   CTZ,
+//   MAX,
+//   MAXU,
+//   MIN,
+//   MINU,
+//   ORC_B,
+//   ORN,
+//   REV8,
+//   ROL,
+//   ROR,
+//   RORI,
+//   SEXT_B,
+//   SEXT_H,
+//   XNOR,
+//   ZEXT_H,
+//   // RV32ZBC instructions
+//   CLMUL,
+//   CLMULH,
+//   CLMULR,
+//   // RV32ZBS instructions
+//   BCLR,
+//   BCLRI,
+//   BEXT,
+//   BEXTI,
+//   BINV,
+//   BINVI,
+//   BSET,
+//   BSETI,
+//   // RV32B instructions
+//   // Remaining bitmanip instructions of draft v.0.93 not ratified in v.1.00 (Zba, Zbb, Zbc, Zbs).
+//   GORC,
+//   GORCI,
+//   CMIX,
+//   CMOV,
+//   PACK,
+//   PACKU,
+//   PACKH,
+//   XPERM4,
+//   XPERM8,
+//   XPERM16,
+//   SLO,
+//   SRO,
+//   SLOI,
+//   SROI,
+//   GREV,
+//   GREVI,
+//   FSL,
+//   FSR,
+//   FSRI,
+//   CRC32_B,
+//   CRC32_H,
+//   CRC32_W,
+//   CRC32C_B,
+//   CRC32C_H,
+//   CRC32C_W,
+//   SHFL,
+//   UNSHFL,
+//   SHFLI,
+//   UNSHFLI,
+//   UNZIP8,
+//   UNZIP16,
+//   BCOMPRESS,
+//   BDECOMPRESS,
+//   BFP,
+//   // RV64ZBA instructions
+//   ADD_UW,
+//   SH1ADD_UW,
+//   SH2ADD_UW,
+//   SH3ADD_UW,
+//   SLLI_UW,
+//   // RV64ZBB instructions
+//   CLZW,
+//   CPOPW,
+//   CTZW,
+//   ROLW,
+//   RORW,
+//   RORIW,
+//   //RV64B instructions
+//   // Remaining bitmanip instructions of draft v.0.93 not ratified in v.1.00 (Zba, Zbb, Zbc, Zbs).
+//   BMATOR,
+//   BMATXOR,
+//   BMATFLIP,
+//   CRC32_D,
+//   CRC32C_D,
+//   SHFLW,
+//   UNSHFLW,
+//   BCOMPRESSW,
+//   BDECOMPRESSW,
+//   BFPW,
+//   SLOW,
+//   SROW,
+//   SLOIW,
+//   SROIW,
+//   GREVW,
+//   GREVIW,
+//   FSLW,
+//   FSRW,
+//   FSRIW,
+//   GORCW,
+//   GORCIW,
+//   PACKW,
+//   PACKUW,
+//   XPERM32,
+//   // RV32M instructions
+//   MUL,
+//   MULH,
+//   MULHSU,
+//   MULHU,
+//   DIV,
+//   DIVU,
+//   REM,
+//   REMU,
+//   // RV64M instructions
+//   MULW,
+//   DIVW,
+//   DIVUW,
+//   REMW,
+//   REMUW,
+//   // RV32F instructions
+//   FLW,
+//   FSW,
+//   FMADD_S,
+//   FMSUB_S,
+//   FNMSUB_S,
+//   FNMADD_S,
+//   FADD_S,
+//   FSUB_S,
+//   FMUL_S,
+//   FDIV_S,
+//   FSQRT_S,
+//   FSGNJ_S,
+//   FSGNJN_S,
+//   FSGNJX_S,
+//   FMIN_S,
+//   FMAX_S,
+//   FCVT_W_S,
+//   FCVT_WU_S,
+//   FMV_X_W,
+//   FMV_X_S,
+//   FEQ_S,
+//   FLT_S,
+//   FLE_S,
+//   FCLASS_S,
+//   FCVT_S_W,
+//   FCVT_S_WU,
+//   FMV_W_X,
+//   FMV_S_X,
+//   // RV64F instruction
+//   FCVT_L_S,
+//   FCVT_LU_S,
+//   FCVT_S_L,
+//   FCVT_S_LU,
+//   // RV32D instructions
+//   FLD,
+//   FSD,
+//   FMADD_D,
+//   FMSUB_D,
+//   FNMSUB_D,
+//   FNMADD_D,
+//   FADD_D,
+//   FSUB_D,
+//   FMUL_D,
+//   FDIV_D,
+//   FSQRT_D,
+//   FSGNJ_D,
+//   FSGNJN_D,
+//   FSGNJX_D,
+//   FMIN_D,
+//   FMAX_D,
+//   FCVT_S_D,
+//   FCVT_D_S,
+//   FEQ_D,
+//   FLT_D,
+//   FLE_D,
+//   FCLASS_D,
+//   FCVT_W_D,
+//   FCVT_WU_D,
+//   FCVT_D_W,
+//   FCVT_D_WU,
+//   // RV64D
+//   FCVT_L_D,
+//   FCVT_LU_D,
+//   FMV_X_D,
+//   FCVT_D_L,
+//   FCVT_D_LU,
+//   FMV_D_X,
+//   // RV64I
+//   LWU,
+//   LD,
+//   SD,
+//   ADDIW,
+//   SLLIW,
+//   SRLIW,
+//   SRAIW,
+//   ADDW,
+//   SUBW,
+//   SLLW,
+//   SRLW,
+//   SRAW,
+//   // RV32C
+//   C_LW,
+//   C_SW,
+//   C_LWSP,
+//   C_SWSP,
+//   C_ADDI4SPN,
+//   C_ADDI,
+//   C_LI,
+//   C_ADDI16SP,
+//   C_LUI,
+//   C_SRLI,
+//   C_SRAI,
+//   C_ANDI,
+//   C_SUB,
+//   C_XOR,
+//   C_OR,
+//   C_AND,
+//   C_BEQZ,
+//   C_BNEZ,
+//   C_SLLI,
+//   C_MV,
+//   C_EBREAK,
+//   C_ADD,
+//   C_NOP,
+//   C_J,
+//   C_JAL,
+//   C_JR,
+//   C_JALR,
+//   // RV64C
+//   C_ADDIW,
+//   C_SUBW,
+//   C_ADDW,
+//   C_LD,
+//   C_SD,
+//   C_LDSP,
+//   C_SDSP,
+//   // RV128C
+//   C_SRLI64,
+//   C_SRAI64,
+//   C_SLLI64,
+//   C_LQ,
+//   C_SQ,
+//   C_LQSP,
+//   C_SQSP,
+//   // RV32FC
+//   C_FLW,
+//   C_FSW,
+//   C_FLWSP,
+//   C_FSWSP,
+//   // RV32DC
+//   C_FLD,
+//   C_FSD,
+//   C_FLDSP,
+//   C_FSDSP,
+//   // RV32A
+//   LR_W,
+//   SC_W,
+//   AMOSWAP_W,
+//   AMOADD_W,
+//   AMOAND_W,
+//   AMOOR_W,
+//   AMOXOR_W,
+//   AMOMIN_W,
+//   AMOMAX_W,
+//   AMOMINU_W,
+//   AMOMAXU_W,
+//   // RV64A
+//   LR_D,
+//   SC_D,
+//   AMOSWAP_D,
+//   AMOADD_D,
+//   AMOAND_D,
+//   AMOOR_D,
+//   AMOXOR_D,
+//   AMOMIN_D,
+//   AMOMAX_D,
+//   AMOMINU_D,
+//   AMOMAXU_D,
+//   // Vector instructions
+//   VSETVL,
+//   VSETVLI,
+//   VSETIVLI,
+//   VADD_VV,
+//   VADD_VX,
+//   VADD_VI,
+//   // // // VADD,  #  #  #
+//   VSUB_VV,
+//   VSUB_VX,
+//   // // VSUB,  #  #
+//   VRSUB_VX,
+//   VRSUB_VI,
+//   // // VRSUB,  #  #
+//   VWADDU_VV,
+//   VWADDU_VX,
+//   VWADDU_WV,
+//   VWADDU_WX,
+//   // // // // VWADDU,  #  #  #  #
+//   VWSUBU_VV,
+//   VWSUBU_VX,
+//   VWSUBU_WV,
+//   VWSUBU_WX,
+//   // // // // VWSUBU,  #  #  #  #
+//   VWADD_VV,
+//   VWADD_VX,
+//   VWADD_WV,
+//   VWADD_WX,
+//   // // // // VWADD,  #  #  #  #
+//   VWSUB_VV,
+//   VWSUB_VX,
+//   VWSUB_WV,
+//   VWSUB_WX,
+//   // // // // VWSUB,  #  #  #  #
+//   VADC_VVM,
+//   VADC_VXM,
+//   VADC_VIM,
+//   // // // VADC,  #  #  #
+//   VMADC_VVM,
+//   VMADC_VXM,
+//   VMADC_VIM,
+//   VMADC_VV,
+//   VMADC_VX,
+//   VMADC_VI,
+//   // // // // // // VMADC,  #  #  #  #  #  #
+//   VSBC_VVM,
+//   VSBC_VXM,
+//   // // VSBC,  #  #
+//   VMSBC_VVM,
+//   VMSBC_VXM,
+//   VMSBC_VV,
+//   VMSBC_VX,
+//   // // // // VMSBC,  #  #  #  #
+//   VAND_VV,
+//   VAND_VX,
+//   VAND_VI,
+//   // // // VAND,  #  #  #
+//   VOR_VV,
+//   VOR_VX,
+//   VOR_VI,
+//   // // // VOR,  #  #  #
+//   VXOR_VV,
+//   VXOR_VX,
+//   VXOR_VI,
+//   // // // VXOR,  #  #  #
+//   VSLL_VV,
+//   VSLL_VX,
+//   VSLL_VI,
+//   // // // VSLL,  #  #  #
+//   VSRL_VV,
+//   VSRL_VX,
+//   VSRL_VI,
+//   // // // VSRL,  #  #  #
+//   VSRA_VV,
+//   VSRA_VX,
+//   VSRA_VI,
+//   // // // VSRA,  #  #  #
+//   VNSRL_WV,
+//   VNSRL_WX,
+//   VNSRL_WI,
+//   // // // VNSRL,  #  #  #
+//   VNSRA_WV,
+//   VNSRA_WX,
+//   VNSRA_WI,
+//   // // // VNSRA,  #  #  #
+//   VMSEQ_VV,
+//   VMSEQ_VX,
+//   VMSEQ_VI,
+//   // // // VMSEQ,  #  #  #
+//   VMSNE_VV,
+//   VMSNE_VX,
+//   VMSNE_VI,
+//   // // // VMSNE,  #  #  #
+//   VMSLTU_VV,
+//   VMSLTU_VX,
+//   // // VMSLTU,  #  #
+//   VMSLT_VV,
+//   VMSLT_VX,
+//   // // VMSLT,  #  #
+//   VMSLEU_VV,
+//   VMSLEU_VX,
+//   VMSLEU_VI,
+//   // // // VMSLEU,  #  #  #
+//   VMSLE_VV,
+//   VMSLE_VX,
+//   VMSLE_VI,
+//   // // // VMSLE,  #  #  #
+//   VMSGTU_VX,
+//   VMSGTU_VI,
+//   // // VMSGTU,  #  #
+//   VMSGT_VX,
+//   VMSGT_VI,
+//   // // VMSGT,  #  #
+//   VMINU_VV,
+//   VMINU_VX,
+//   // // VMINU,  #  #
+//   VMIN_VV,
+//   VMIN_VX,
+//   // // VMIN,  #  #
+//   VMAXU_VV,
+//   VMAXU_VX,
+//   // // VMAXU,  #  #
+//   VMAX_VV,
+//   VMAX_VX,
+//   // // VMAX,  #  #
+//   VMUL_VV,
+//   VMUL_VX,
+//   // // VMUL,  #  #
+//   VMULH_VV,
+//   VMULH_VX,
+//   // // VMULH,  #  #
+//   VMULHU_VV,
+//   VMULHU_VX,
+//   // // VMULHU,  #  #
+//   VMULHSU_VV,
+//   VMULHSU_VX,
+//   // // VMULHSU,  #  #
+//   VDIVU_VV,
+//   VDIVU_VX,
+//   // // VDIVU,  #  #
+//   VDIV_VV,
+//   VDIV_VX,
+//   // // VDIV,  #  #
+//   VREMU_VV,
+//   VREMU_VX,
+//   // // VREMU,  #  #
+//   VREM_VV,
+//   VREM_VX,
+//   // // VREM,  #  #
+//   VWMUL_VV,
+//   VWMUL_VX,
+//   // // VWMUL,  #  #
+//   VWMULU_VV,
+//   VWMULU_VX,
+//   // // VWMULU,  #  #
+//   VWMULSU_VV,
+//   VWMULSU_VX,
+//   // // VWMULSU,  #  #
+//   VMACC_VV,
+//   VMACC_VX,
+//   // // VMACC,  #  #
+//   VNMSAC_VV,
+//   VNMSAC_VX,
+//   // // VNMSAC,  #  #
+//   VMADD_VV,
+//   VMADD_VX,
+//   // // VMADD,  #  #
+//   VNMSUB_VV,
+//   VNMSUB_VX,
+//   // // VNMSUB,  #  #
+//   VWMACCU_VV,
+//   VWMACCU_VX,
+//   // // VWMACCU,  #  #
+//   VWMACC_VV,
+//   VWMACC_VX,
+//   // // VWMACC,  #  #
+//   VWMACCSU_VV,
+//   VWMACCSU_VX,
+//   // // VWMACCSU,  #  #
+//   VWMACCUS_VX,
+//   // VWMACCUS,  #
+//   //VQMACCU,
+//   //VQMACC,
+//   //VQMACCSU,
+//   //VQMACCUS,
+//   VMERGE_VVM,
+//   VMERGE_VXM,
+//   VMERGE_VIM,
+//   // // // VMERGE,  #  #  #
+//   VMV_V_V,
+//   VMV_V_X,
+//   VMV_V_I,
+//   // // // VMV,  #  #  #
+//   VSADDU_VV,
+//   VSADDU_VX,
+//   VSADDU_VI,
+//   // // // VSADDU,  #  #  #
+//   VSADD_VV,
+//   VSADD_VX,
+//   VSADD_VI,
+//   // VSMUL
+//   VSMUL_VV,
+//   VSMUL_VX,
+//   // // // VSADD,  #  #  #
+//   VSSUBU_VV,
+//   VSSUBU_VX,
+//   // // VSSUBU,  #  #
+//   VSSUB_VV,
+//   VSSUB_VX,
+//   // // VSSUB,  #  #
+//   VAADDU_VV,
+//   VAADDU_VX,
+//   // // VAADDU,  #  #
+//   VAADD_VV,
+//   VAADD_VX,
+//   // // VAADD,  #  #
+//   VASUBU_VV,
+//   VASUBU_VX,
+//   // // VASUBU,  #  #
+//   VASUB_VV,
+//   VASUB_VX,
+//   // // VASUB,  #  #
+//   VSSRL_VV,
+//   VSSRL_VX,
+//   VSSRL_VI,
+//   // // // VSSRL,  #  #  #
+//   VSSRA_VV,
+//   VSSRA_VX,
+//   VSSRA_VI,
+//   // // // VSSRA,  #  #  #
+//   VNCLIPU_WV,
+//   VNCLIPU_WX,
+//   VNCLIPU_WI,
+//   // // // VNCLIPU,  #  #  #
+//   VNCLIP_WV,
+//   VNCLIP_WX,
+//   VNCLIP_WI,
+//   // // // VNCLIP,  #  #  #
+//   // 14. Vector Floating-Point Instructions
+//   VFADD_VV,
+//   VFADD_VF,
+//   // // VFADD,  #  #
+//   VFSUB_VV,
+//   VFSUB_VF,
+//   // // VFSUB,  #  #
+//   VFRSUB_VF,
+//   // VFRSUB,  #
+//   VFMUL_VV,
+//   VFMUL_VF,
+//   // // VFMUL,  #  #
+//   VFDIV_VV,
+//   VFDIV_VF,
+//   // // VFDIV,  #  #
+//   VFRDIV_VF,
+//   // VFRDIV,  #
+//   VFWMUL_VV,
+//   VFWMUL_VF,
+//   // // VFWMUL,  #  #
+//   VFMACC_VV,
+//   VFMACC_VF,
+//   // // VFMACC,  #  #
+//   VFNMACC_VV,
+//   VFNMACC_VF,
+//   // // VFNMACC,  #  #
+//   VFMSAC_VV,
+//   VFMSAC_VF,
+//   // // VFMSAC,  #  #
+//   VFNMSAC_VV,
+//   VFNMSAC_VF,
+//   // // VFNMSAC,  #  #
+//   VFMADD_VV,
+//   VFMADD_VF,
+//   // // VFMADD,  #  #
+//   VFNMADD_VV,
+//   VFNMADD_VF,
+//   // // VFNMADD,  #  #
+//   VFMSUB_VV,
+//   VFMSUB_VF,
+//   // // VFMSUB,  #  #
+//   VFNMSUB_VV,
+//   VFNMSUB_VF,
+//   // // VFNMSUB,  #  #
+//   VFWMACC_VV,
+//   VFWMACC_VF,
+//   // // VFWMACC,  #  #
+//   VFWNMACC_VV,
+//   VFWNMACC_VF,
+//   // // VFWNMACC,  #  #
+//   VFWMSAC_VV,
+//   VFWMSAC_VF,
+//   // // VFWMSAC,  #  #
+//   VFWNMSAC_VV,
+//   VFWNMSAC_VF,
+//   // // VFWNMSAC,  #  #
+//   VFSQRT_V,
+//   VFRSQRT7_V,
+//   VFMIN_VV,
+//   VFMIN_VF,
+//   // // VFMIN,  #  #
+//   VFMAX_VV,
+//   VFMAX_VF,
+//   // // VFMAX,  #  #
+//   VFSGNJ_VV,
+//   VFSGNJ_VF,
+//   // // VFSGNJ,  #  #
+//   VFSGNJN_VV,
+//   VFSGNJN_VF,
+//   // // VFSGNJN,  #  #
+//   VFSGNJX_VV,
+//   VFSGNJX_VF,
+//   // // VFSGNJX,  #  #
+//   VMFEQ_VV,
+//   VMFEQ_VF,
+//   // // VMFEQ,  #  #
+//   VMFNE_VV,
+//   VMFNE_VF,
+//   // // VMFNE,  #  #
+//   VMFLT_VV,
+//   VMFLT_VF,
+//   // // VMFLT,  #  #
+//   VMFLE_VV,
+//   VMFLE_VF,
+//   // // VMFLE,  #  #
+//   VMFGT_VF,
+//   // VMFGT,  #
+//   VMFGE_VF,
+//   // VMFGE,  #
+//   VFCLASS_V,
+//   VFREC7_V,
+//   VFMERGE_VFM,
+//   // VFMERGE,  #
+//   VFMV_V_F,
+//   // VFMV,  #
+//   VFCVT_XU_F_V,
+//   VFCVT_X_F_V,
+//   VFCVT_RTZ_XU_F_V,
+//   VFCVT_RTZ_X_F_V,
+//   VFCVT_F_XU_V,
+//   VFCVT_F_X_V,
+//   VFWCVT_XU_F_V,
+//   VFWCVT_X_F_V,
+//   VFWCVT_F_XU_V,
+//   VFWCVT_F_X_V,
+//   VFWCVT_RTZ_XU_F_V,
+//   VFWCVT_RTZ_X_F_V,
+//   VFWCVT_F_F_V,
+//   VFNCVT_XU_F_W,
+//   VFNCVT_X_F_W,
+//   VFNCVT_RTZ_XU_F_W,
+//   VFNCVT_RTZ_X_F_W,
+//   VFNCVT_F_XU_W,
+//   VFNCVT_F_X_W,
+//   VFNCVT_F_F_W,
+//   VFNCVT_ROD_F_F_W,
+//   // 15. Vector reduction instruction
+//   VREDSUM_VS,
+//   VREDMAXU_VS,
+//   VREDMAX_VS,
+//   VREDMINU_VS,
+//   VREDMIN_VS,
+//   VREDAND_VS,
+//   VREDOR_VS,
+//   VREDXOR_VS,
+//   VWREDSUMU_VS,
+//   VWREDSUM_VS,
+//   VFREDSUM_VS,
+//   VFREDOSUM_VS,
+//   VFREDUSUM_VS,
+//   VFREDMAX_VS,
+//   VFREDMIN_VS,
+//   VFWREDOSUM_VS,
+//   VFWREDUSUM_VS,
+//   VFWREDSUM_VS,
+//   // Vector mask instruction
+//   VMAND_MM,
+//   VMANDN_MM,
+//   VMNAND_MM,
+//   VMANDNOT_MM,
+//   VMXOR_MM,
+//   VMOR_MM,
+//   VMORN_MM,
+//   VMNOR_MM,
+//   VMORNOT_MM,
+//   VMXNOR_MM,
+//   VPOPC_M,
+//   VCPOP_M,
+//   VFIRST_M,
+//   VMSBF_M,
+//   VMSIF_M,
+//   VMSOF_M,
+//   VIOTA_M,
+//   VID_V,
+//   // Vector permutation instruction
+//   VMV_X_S,
+//   VMV_S_X,
+//   VFMV_F_S,
+//   VFMV_S_F,
+//   VSLIDEUP_VI,
+//   VSLIDEUP_VX,
+//   // // VSLIDEUP,  #  #
+//   VSLIDEDOWN_VI,
+//   VSLIDEDOWN_VX,
+//   // // VSLIDEDOWN,  #  #
+//   VSLIDE1UP_VX,
+//   // VSLIDE1UP,  #
+//   VFSLIDE1UP_VF,
+//   // VFSLIDE1UP,  #
+//   VSLIDE1DOWN_VX,
+//   // VFSLIDE1UP,  #
+//   VFSLIDE1DOWN_VF,
+//   // VSLIDE1DOWN,  #
+//   VRGATHER_VV,
+//   VRGATHER_VX,
+//   VRGATHER_VI,
+//   // // // VRGATHER,  #  #  #
+//   VRGATHEREI16_VV,
+//   // VRGATHEREI16,  #
+//   VCOMPRESS_VM,
+//   // VCOMPRESS,  #
+//   VMV1R_V,
+//   VMV2R_V,
+//   VMV4R_V,
+//   VMV8R_V,
+//   VS1R_V,
+//   VS2R_V,
+//   VS4R_V,
+//   VS8R_V,
+//   // Vector load/store instruction
+//   VLE8_V,
+//   VLE16_V,
+//   VLE32_V,
+//   VLE64_V,
+//   VLE128_V,
+//   VLE256_V,
+//   VLE512_V,
+//   VLE1024_V,
+
+//   VLE8FF_V,
+//   VLE16FF_V,
+//   VLE32FF_V,
+//   VLE64FF_V,
+//   VLE128FF_V,
+//   VLE256FF_V,
+//   VLE512FF_V,
+//   VLE1024FF_V,
+
+//   VSE8_V,
+//   VSE16_V,
+//   VSE32_V,
+//   VSE64_V,
+//   VSE128_V,
+//   VSE256_V,
+//   VSE512_V,
+//   VSE1024_V,
+
+//   VLSE8_V,
+//   VLSE16_V,
+//   VLSE32_V,
+//   VLSE64_V,
+//   VLSE128_V,
+//   VLSE256_V,
+//   VLSE512_V,
+//   VLSE1024_V,
+
+//   VSSE8_V,
+//   VSSE16_V,
+//   VSSE32_V,
+//   VSSE64_V,
+//   VSSE128_V,
+//   VSSE256_V,
+//   VSSE512_V,
+//   VSSE1024_V,
+
+//   VLOXEI8_V,
+//   VLOXEI16_V,
+//   VLOXEI32_V,
+//   VLOXEI64_V,
+//   VLOXEI128_V,
+//   VLOXEI256_V,
+//   VLOXEI512_V,
+//   VLOXEI1024_V,
+
+//   VLUXEI8_V,
+//   VLUXEI16_V,
+//   VLUXEI32_V,
+//   VLUXEI64_V,
+//   VLUXEI128_V,
+//   VLUXEI256_V,
+//   VLUXEI512_V,
+//   VLUXEI1024_V,
+
+//   VSOXEI8_V,
+//   VSOXEI16_V,
+//   VSOXEI32_V,
+//   VSOXEI64_V,
+//   VSOXEI128_V,
+//   VSOXEI256_V,
+//   VSOXEI512_V,
+//   VSOXEI1024_V,
+
+//   VSUXEI8_V,
+//   VSUXEI16_V,
+//   VSUXEI32_V,
+//   VSUXEI64_V,
+//   VSUXEI128_V,
+//   VSUXEI256_V,
+//   VSUXEI512_V,
+//   VSUXEI1024_V,
+
+//   VL1R_V,
+//   VL1RE8_V,
+//   VL1RE16_V,
+//   VL1RE32_V,
+//   VL1RE64_V,
+
+//   VL2R_V,
+//   VL2RE8_V,
+//   VL2RE16_V,
+//   VL2RE32_V,
+//   VL2RE64_V,
+
+//   VL4R_V,
+//   VL4RE8_V,
+//   VL4RE16_V,
+//   VL4RE32_V,
+//   VL4RE64_V,
+
+//   VL8R_V,
+//   VL8RE8_V,
+//   VL8RE16_V,
+//   VL8RE32_V,
+//   VL8RE64_V,
+
+//   VLM_V,
+//   VLE1_V,
+//   VSM_V,
+//   VSE1_V,
+
+//   VSEXT_VF2,
+//   VSEXT_VF4,
+//   VSEXT_VF8,
+
+//   VZEXT_VF2,
+//   VZEXT_VF4,
+//   VZEXT_VF8,
+
+//   // VLXEI_V,
+//   // VSXEI_V,
+//   // VSUXEI_V,
+//   // VLEFF_V,
+//   // Segmented load/store instruction
+//   // VLSEGE_V,
+//   // VSSEGE_V,
+//   // VLSEGEFF_V,
+//   // VLSSEGE_V,
+//   // VSSSEGE_V,
+//   // VLXSEGEI_V,
+//   // VSXSEGEI_V,
+//   // VSUXSEGEI_V,
+//   // Vector AMO instruction
+//   // EEW vector AMOs
+
+//   // VAMOADDEI8_V,
+//   // VAMOADDEI16_V,
+//   // VAMOADDEI32_V,
+//   // VAMOADDEI64_V,
+//   // VAMOANDEI8_V,
+//   // VAMOANDEI16_V,
+//   // VAMOANDEI32_V,
+//   // VAMOANDEI64_V,
+//   // VAMOMAXEI8_V,
+//   // VAMOMAXEI16_V,
+//   // VAMOMAXEI32_V,
+//   // VAMOMAXEI64_V,
+//   // VAMOMAXUEI8_V,
+//   // VAMOMAXUEI16_V,
+//   // VAMOMAXUEI32_V,
+//   // VAMOMAXUEI64_V,
+//   // VAMOMINEI8_V,
+//   // VAMOMINEI16_V,
+//   // VAMOMINEI32_V,
+//   // VAMOMINEI64_V,
+//   // VAMOMINUEI8_V,
+//   // VAMOMINUEI16_V,
+//   // VAMOMINUEI32_V,
+//   // VAMOMINUEI64_V,
+//   // VAMOOREI8_V,
+//   // VAMOOREI16_V,
+//   // VAMOOREI32_V,
+//   // VAMOOREI64_V,
+//   // VAMOSWAPEI8_V,
+//   // VAMOSWAPEI16_V,
+//   // VAMOSWAPEI32_V,
+//   // VAMOSWAPEI64_V,
+//   // VAMOXOREI8_V,
+//   // VAMOXOREI16_V,
+//   // VAMOXOREI32_V,
+//   // VAMOXOREI64_V,
+//   VFWADD_VF,
+//   VFWADD_VV,
+//   VFWADD_WF,
+//   VFWADD_WV,
+//   VFWSUB_VF,
+//   VFWSUB_VV,
+//   VFWSUB_WF,
+//   VFWSUB_WV,
+//   // Supervisor instruction
+//   DRET,
+//   MRET,
+//   // URET,                       // deprecated
+//   SRET,
+//   WFI,
+//   SFENCE_VMA,
+//   // rv_zicsr
+//   CSRRC,
+//   CSRRCI,
+//   CSRRS,
+//   CSRRSI,
+//   CSRRW,
+//   CSRRWI,
+
+//   FRCSR,
+//   FRFLAGS,
+//   FRRM,
+//   RDCYCLE,
+//   RDCYCLEH,
+//   RDINSTRET,
+//   RDINSTRETH,
+//   RDTIME,
+//   RDTIMEH,
+
+//   FSCSR,
+//   FSFLAGS,
+//   FSRM,
+
+//   FSFLAGSI,
+//   FSRMI,
+
+  
+//   // Custom instructions
+//   // `include "isa/custom/riscv_custom_instr_enum.sv"
+//   // You can add other instructions here
+//   INVALID_INSTR
+// }
+
+
+enum va_base_instr: byte {
   VADD,
   VSUB,
   VRSUB,
@@ -499,14 +1150,11 @@ enum riscv_instr_name_t: ushort  {
   VWMACC,
   VWMACCSU,
   VWMACCUS,
-  //VQMACCU,
-  //VQMACC,
-  //VQMACCSU,
-  //VQMACCUS,
   VMERGE,
   VMV,
   VSADDU,
   VSADD,
+  VSMUL,
   VSSUBU,
   VSSUB,
   VAADDU,
@@ -517,7 +1165,6 @@ enum riscv_instr_name_t: ushort  {
   VSSRA,
   VNCLIPU,
   VNCLIP,
-  // 14. Vector Floating-Point Instructions
   VFADD,
   VFSUB,
   VFRSUB,
@@ -537,7 +1184,6 @@ enum riscv_instr_name_t: ushort  {
   VFWNMACC,
   VFWMSAC,
   VFWNMSAC,
-  VFSQRT_V,
   VFMIN,
   VFMAX,
   VFSGNJ,
@@ -549,113 +1195,275 @@ enum riscv_instr_name_t: ushort  {
   VMFLE,
   VMFGT,
   VMFGE,
-  VFCLASS_V,
   VFMERGE,
   VFMV,
-  VFCVT_XU_F_V,
-  VFCVT_X_F_V,
-  VFCVT_F_XU_V,
-  VFCVT_F_X_V,
-  VFWCVT_XU_F_V,
-  VFWCVT_X_F_V,
-  VFWCVT_F_XU_V,
-  VFWCVT_F_X_V,
-  VFWCVT_F_F_V,
-  VFNCVT_XU_F_W,
-  VFNCVT_X_F_W,
-  VFNCVT_F_XU_W,
-  VFNCVT_F_X_W,
-  VFNCVT_F_F_W,
-  VFNCVT_ROD_F_F_W,
-  // 15. Vector reduction instruction
-  VREDSUM_VS,
-  VREDMAXU_VS,
-  VREDMAX_VS,
-  VREDMINU_VS,
-  VREDMIN_VS,
-  VREDAND_VS,
-  VREDOR_VS,
-  VREDXOR_VS,
-  VWREDSUMU_VS,
-  VWREDSUM_VS,
-  VFREDOSUM_VS,
-  VFREDSUM_VS,
-  VFREDMAX_VS,
-  VFWREDOSUM_VS,
-  VFWREDSUM_VS,
-  // Vector mask instruction
-  VMAND_MM,
-  VMNAND_MM,
-  VMANDNOT_MM,
-  VMXOR_MM,
-  VMOR_MM,
-  VMNOR_MM,
-  VMORNOT_MM,
-  VMXNOR_MM,
-  VPOPC_M,
-  VFIRST_M,
-  VMSBF_M,
-  VMSIF_M,
-  VMSOF_M,
-  VIOTA_M,
-  VID_V,
-  // Vector permutation instruction
-  VMV_X_S,
-  VMV_S_X,
-  VFMV_F_S,
-  VFMV_S_F,
   VSLIDEUP,
   VSLIDEDOWN,
   VSLIDE1UP,
+  VFSLIDE1UP,
   VSLIDE1DOWN,
+  VFSLIDE1DOWN,
   VRGATHER,
+  VRGATHEREI16,
   VCOMPRESS,
-  VMV1R_V,
-  VMV2R_V,
-  VMV4R_V,
-  VMV8R_V,
-  // Vector load/store instruction
-  VLE_V,
-  VSE_V,
-  VLSE_V,
-  VSSE_V,
-  VLXEI_V,
-  VSXEI_V,
-  VSUXEI_V,
-  VLEFF_V,
-  // Segmented load/store instruction
-  VLSEGE_V,
-  VSSEGE_V,
-  VLSEGEFF_V,
-  VLSSEGE_V,
-  VSSSEGE_V,
-  VLXSEGEI_V,
-  VSXSEGEI_V,
-  VSUXSEGEI_V,
-  // Vector AMO instruction
-  // EEW vector AMOs
-  VAMOSWAPE_V,
-  VAMOADDE_V,
-  VAMOXORE_V,
-  VAMOANDE_V,
-  VAMOORE_V,
-  VAMOMINE_V,
-  VAMOMAXE_V,
-  VAMOMINUE_V,
-  VAMOMAXUE_V,
-  // Supervisor instruction
-  DRET,
-  MRET,
-  URET,
-  SRET,
-  WFI,
-  SFENCE_VMA,
-  // Custom instructions
-  // `include "isa/custom/riscv_custom_instr_enum.sv"
-  // You can add other instructions here
-  INVALID_INSTR
+  VFWADD,
+  VFWSUB,
+  // Not every Vector Instruction has a base
+  VA_NO_BASE,
+}
+
+va_base_instr va_get_base(riscv_instr_name_t INSTR) {
+  switch (INSTR) {
+  case riscv_instr_name_t.VADD_VV: return va_base_instr.VADD;
+  case riscv_instr_name_t.VADD_VX: return va_base_instr.VADD;
+  case riscv_instr_name_t.VADD_VI: return va_base_instr.VADD;
+  case riscv_instr_name_t.VSUB_VV: return va_base_instr.VSUB;
+  case riscv_instr_name_t.VSUB_VX: return va_base_instr.VSUB;
+  case riscv_instr_name_t.VRSUB_VX: return va_base_instr.VRSUB;
+  case riscv_instr_name_t.VRSUB_VI: return va_base_instr.VRSUB;
+  case riscv_instr_name_t.VWADDU_VV: return va_base_instr.VWADDU;
+  case riscv_instr_name_t.VWADDU_VX: return va_base_instr.VWADDU;
+  case riscv_instr_name_t.VWADDU_WV: return va_base_instr.VWADDU;
+  case riscv_instr_name_t.VWADDU_WX: return va_base_instr.VWADDU;
+  case riscv_instr_name_t.VWSUBU_VV: return va_base_instr.VWSUBU;
+  case riscv_instr_name_t.VWSUBU_VX: return va_base_instr.VWSUBU;
+  case riscv_instr_name_t.VWSUBU_WV: return va_base_instr.VWSUBU;
+  case riscv_instr_name_t.VWSUBU_WX: return va_base_instr.VWSUBU;
+  case riscv_instr_name_t.VWADD_VV: return va_base_instr.VWADD;
+  case riscv_instr_name_t.VWADD_VX: return va_base_instr.VWADD;
+  case riscv_instr_name_t.VWADD_WV: return va_base_instr.VWADD;
+  case riscv_instr_name_t.VWADD_WX: return va_base_instr.VWADD;
+  case riscv_instr_name_t.VWSUB_VV: return va_base_instr.VWSUB;
+  case riscv_instr_name_t.VWSUB_VX: return va_base_instr.VWSUB;
+  case riscv_instr_name_t.VWSUB_WV: return va_base_instr.VWSUB;
+  case riscv_instr_name_t.VWSUB_WX: return va_base_instr.VWSUB;
+  case riscv_instr_name_t.VADC_VVM: return va_base_instr.VADC;
+  case riscv_instr_name_t.VADC_VXM: return va_base_instr.VADC;
+  case riscv_instr_name_t.VADC_VIM: return va_base_instr.VADC;
+  case riscv_instr_name_t.VMADC_VVM: return va_base_instr.VMADC;
+  case riscv_instr_name_t.VMADC_VXM: return va_base_instr.VMADC;
+  case riscv_instr_name_t.VMADC_VIM: return va_base_instr.VMADC;
+  case riscv_instr_name_t.VMADC_VV: return va_base_instr.VMADC;
+  case riscv_instr_name_t.VMADC_VX: return va_base_instr.VMADC;
+  case riscv_instr_name_t.VMADC_VI: return va_base_instr.VMADC;
+  case riscv_instr_name_t.VSBC_VVM: return va_base_instr.VSBC;
+  case riscv_instr_name_t.VSBC_VXM: return va_base_instr.VSBC;
+  case riscv_instr_name_t.VMSBC_VVM: return va_base_instr.VMSBC;
+  case riscv_instr_name_t.VMSBC_VXM: return va_base_instr.VMSBC;
+  case riscv_instr_name_t.VMSBC_VV: return va_base_instr.VMSBC;
+  case riscv_instr_name_t.VMSBC_VX: return va_base_instr.VMSBC;
+  case riscv_instr_name_t.VAND_VV: return va_base_instr.VAND;
+  case riscv_instr_name_t.VAND_VX: return va_base_instr.VAND;
+  case riscv_instr_name_t.VAND_VI: return va_base_instr.VAND;
+  case riscv_instr_name_t.VOR_VV: return va_base_instr.VOR;
+  case riscv_instr_name_t.VOR_VX: return va_base_instr.VOR;
+  case riscv_instr_name_t.VOR_VI: return va_base_instr.VOR;
+  case riscv_instr_name_t.VXOR_VV: return va_base_instr.VXOR;
+  case riscv_instr_name_t.VXOR_VX: return va_base_instr.VXOR;
+  case riscv_instr_name_t.VXOR_VI: return va_base_instr.VXOR;
+  case riscv_instr_name_t.VSLL_VV: return va_base_instr.VSLL;
+  case riscv_instr_name_t.VSLL_VX: return va_base_instr.VSLL;
+  case riscv_instr_name_t.VSLL_VI: return va_base_instr.VSLL;
+  case riscv_instr_name_t.VSRL_VV: return va_base_instr.VSRL;
+  case riscv_instr_name_t.VSRL_VX: return va_base_instr.VSRL;
+  case riscv_instr_name_t.VSRL_VI: return va_base_instr.VSRL;
+  case riscv_instr_name_t.VSRA_VV: return va_base_instr.VSRA;
+  case riscv_instr_name_t.VSRA_VX: return va_base_instr.VSRA;
+  case riscv_instr_name_t.VSRA_VI: return va_base_instr.VSRA;
+  case riscv_instr_name_t.VNSRL_WV: return va_base_instr.VNSRL;
+  case riscv_instr_name_t.VNSRL_WX: return va_base_instr.VNSRL;
+  case riscv_instr_name_t.VNSRL_WI: return va_base_instr.VNSRL;
+  case riscv_instr_name_t.VNSRA_WV: return va_base_instr.VNSRA;
+  case riscv_instr_name_t.VNSRA_WX: return va_base_instr.VNSRA;
+  case riscv_instr_name_t.VNSRA_WI: return va_base_instr.VNSRA;
+  case riscv_instr_name_t.VMSEQ_VV: return va_base_instr.VMSEQ;
+  case riscv_instr_name_t.VMSEQ_VX: return va_base_instr.VMSEQ;
+  case riscv_instr_name_t.VMSEQ_VI: return va_base_instr.VMSEQ;
+  case riscv_instr_name_t.VMSNE_VV: return va_base_instr.VMSNE;
+  case riscv_instr_name_t.VMSNE_VX: return va_base_instr.VMSNE;
+  case riscv_instr_name_t.VMSNE_VI: return va_base_instr.VMSNE;
+  case riscv_instr_name_t.VMSLTU_VV: return va_base_instr.VMSLTU;
+  case riscv_instr_name_t.VMSLTU_VX: return va_base_instr.VMSLTU;
+  case riscv_instr_name_t.VMSLT_VV: return va_base_instr.VMSLT;
+  case riscv_instr_name_t.VMSLT_VX: return va_base_instr.VMSLT;
+  case riscv_instr_name_t.VMSLEU_VV: return va_base_instr.VMSLEU;
+  case riscv_instr_name_t.VMSLEU_VX: return va_base_instr.VMSLEU;
+  case riscv_instr_name_t.VMSLEU_VI: return va_base_instr.VMSLEU;
+  case riscv_instr_name_t.VMSLE_VV: return va_base_instr.VMSLE;
+  case riscv_instr_name_t.VMSLE_VX: return va_base_instr.VMSLE;
+  case riscv_instr_name_t.VMSLE_VI: return va_base_instr.VMSLE;
+  case riscv_instr_name_t.VMSGTU_VX: return va_base_instr.VMSGTU;
+  case riscv_instr_name_t.VMSGTU_VI: return va_base_instr.VMSGTU;
+  case riscv_instr_name_t.VMSGT_VX: return va_base_instr.VMSGT;
+  case riscv_instr_name_t.VMSGT_VI: return va_base_instr.VMSGT;
+  case riscv_instr_name_t.VMINU_VV: return va_base_instr.VMINU;
+  case riscv_instr_name_t.VMINU_VX: return va_base_instr.VMINU;
+  case riscv_instr_name_t.VMIN_VV: return va_base_instr.VMIN;
+  case riscv_instr_name_t.VMIN_VX: return va_base_instr.VMIN;
+  case riscv_instr_name_t.VMAXU_VV: return va_base_instr.VMAXU;
+  case riscv_instr_name_t.VMAXU_VX: return va_base_instr.VMAXU;
+  case riscv_instr_name_t.VMAX_VV: return va_base_instr.VMAX;
+  case riscv_instr_name_t.VMAX_VX: return va_base_instr.VMAX;
+  case riscv_instr_name_t.VMUL_VV: return va_base_instr.VMUL;
+  case riscv_instr_name_t.VMUL_VX: return va_base_instr.VMUL;
+  case riscv_instr_name_t.VMULH_VV: return va_base_instr.VMULH;
+  case riscv_instr_name_t.VMULH_VX: return va_base_instr.VMULH;
+  case riscv_instr_name_t.VMULHU_VV: return va_base_instr.VMULHU;
+  case riscv_instr_name_t.VMULHU_VX: return va_base_instr.VMULHU;
+  case riscv_instr_name_t.VMULHSU_VV: return va_base_instr.VMULHSU;
+  case riscv_instr_name_t.VMULHSU_VX: return va_base_instr.VMULHSU;
+  case riscv_instr_name_t.VDIVU_VV: return va_base_instr.VDIVU;
+  case riscv_instr_name_t.VDIVU_VX: return va_base_instr.VDIVU;
+  case riscv_instr_name_t.VDIV_VV: return va_base_instr.VDIV;
+  case riscv_instr_name_t.VDIV_VX: return va_base_instr.VDIV;
+  case riscv_instr_name_t.VREMU_VV: return va_base_instr.VREMU;
+  case riscv_instr_name_t.VREMU_VX: return va_base_instr.VREMU;
+  case riscv_instr_name_t.VREM_VV: return va_base_instr.VREM;
+  case riscv_instr_name_t.VREM_VX: return va_base_instr.VREM;
+  case riscv_instr_name_t.VWMUL_VV: return va_base_instr.VWMUL;
+  case riscv_instr_name_t.VWMUL_VX: return va_base_instr.VWMUL;
+  case riscv_instr_name_t.VWMULU_VV: return va_base_instr.VWMULU;
+  case riscv_instr_name_t.VWMULU_VX: return va_base_instr.VWMULU;
+  case riscv_instr_name_t.VWMULSU_VV: return va_base_instr.VWMULSU;
+  case riscv_instr_name_t.VWMULSU_VX: return va_base_instr.VWMULSU;
+  case riscv_instr_name_t.VMACC_VV: return va_base_instr.VMACC;
+  case riscv_instr_name_t.VMACC_VX: return va_base_instr.VMACC;
+  case riscv_instr_name_t.VNMSAC_VV: return va_base_instr.VNMSAC;
+  case riscv_instr_name_t.VNMSAC_VX: return va_base_instr.VNMSAC;
+  case riscv_instr_name_t.VMADD_VV: return va_base_instr.VMADD;
+  case riscv_instr_name_t.VMADD_VX: return va_base_instr.VMADD;
+  case riscv_instr_name_t.VNMSUB_VV: return va_base_instr.VNMSUB;
+  case riscv_instr_name_t.VNMSUB_VX: return va_base_instr.VNMSUB;
+  case riscv_instr_name_t.VWMACCU_VV: return va_base_instr.VWMACCU;
+  case riscv_instr_name_t.VWMACCU_VX: return va_base_instr.VWMACCU;
+  case riscv_instr_name_t.VWMACC_VV: return va_base_instr.VWMACC;
+  case riscv_instr_name_t.VWMACC_VX: return va_base_instr.VWMACC;
+  case riscv_instr_name_t.VWMACCSU_VV: return va_base_instr.VWMACCSU;
+  case riscv_instr_name_t.VWMACCSU_VX: return va_base_instr.VWMACCSU;
+  case riscv_instr_name_t.VWMACCUS_VX: return va_base_instr.VWMACCUS;
+  case riscv_instr_name_t.VMERGE_VVM: return va_base_instr.VMERGE;
+  case riscv_instr_name_t.VMERGE_VXM: return va_base_instr.VMERGE;
+  case riscv_instr_name_t.VMERGE_VIM: return va_base_instr.VMERGE;
+  case riscv_instr_name_t.VMV_V_V: return va_base_instr.VMV;
+  case riscv_instr_name_t.VMV_V_X: return va_base_instr.VMV;
+  case riscv_instr_name_t.VMV_V_I: return va_base_instr.VMV;
+  case riscv_instr_name_t.VSADDU_VV: return va_base_instr.VSADDU;
+  case riscv_instr_name_t.VSADDU_VX: return va_base_instr.VSADDU;
+  case riscv_instr_name_t.VSADDU_VI: return va_base_instr.VSADDU;
+  case riscv_instr_name_t.VSADD_VV: return va_base_instr.VSADD;
+  case riscv_instr_name_t.VSADD_VX: return va_base_instr.VSADD;
+  case riscv_instr_name_t.VSADD_VI: return va_base_instr.VSADD;
+  case riscv_instr_name_t.VSSUBU_VV: return va_base_instr.VSSUBU;
+  case riscv_instr_name_t.VSSUBU_VX: return va_base_instr.VSSUBU;
+  case riscv_instr_name_t.VSSUB_VV: return va_base_instr.VSSUB;
+  case riscv_instr_name_t.VSSUB_VX: return va_base_instr.VSSUB;
+  case riscv_instr_name_t.VSMUL_VV: return va_base_instr.VSMUL;
+  case riscv_instr_name_t.VSMUL_VX: return va_base_instr.VSMUL;
+  case riscv_instr_name_t.VAADDU_VV: return va_base_instr.VAADDU;
+  case riscv_instr_name_t.VAADDU_VX: return va_base_instr.VAADDU;
+  case riscv_instr_name_t.VAADD_VV: return va_base_instr.VAADD;
+  case riscv_instr_name_t.VAADD_VX: return va_base_instr.VAADD;
+  case riscv_instr_name_t.VASUBU_VV: return va_base_instr.VASUBU;
+  case riscv_instr_name_t.VASUBU_VX: return va_base_instr.VASUBU;
+  case riscv_instr_name_t.VASUB_VV: return va_base_instr.VASUB;
+  case riscv_instr_name_t.VASUB_VX: return va_base_instr.VASUB;
+  case riscv_instr_name_t.VSSRL_VV: return va_base_instr.VSSRL;
+  case riscv_instr_name_t.VSSRL_VX: return va_base_instr.VSSRL;
+  case riscv_instr_name_t.VSSRL_VI: return va_base_instr.VSSRL;
+  case riscv_instr_name_t.VSSRA_VV: return va_base_instr.VSSRA;
+  case riscv_instr_name_t.VSSRA_VX: return va_base_instr.VSSRA;
+  case riscv_instr_name_t.VSSRA_VI: return va_base_instr.VSSRA;
+  case riscv_instr_name_t.VNCLIPU_WV: return va_base_instr.VNCLIPU;
+  case riscv_instr_name_t.VNCLIPU_WX: return va_base_instr.VNCLIPU;
+  case riscv_instr_name_t.VNCLIPU_WI: return va_base_instr.VNCLIPU;
+  case riscv_instr_name_t.VNCLIP_WV: return va_base_instr.VNCLIP;
+  case riscv_instr_name_t.VNCLIP_WX: return va_base_instr.VNCLIP;
+  case riscv_instr_name_t.VNCLIP_WI: return va_base_instr.VNCLIP;
+  case riscv_instr_name_t.VFADD_VV: return va_base_instr.VFADD;
+  case riscv_instr_name_t.VFADD_VF: return va_base_instr.VFADD;
+  case riscv_instr_name_t.VFSUB_VV: return va_base_instr.VFSUB;
+  case riscv_instr_name_t.VFSUB_VF: return va_base_instr.VFSUB;
+  case riscv_instr_name_t.VFRSUB_VF: return va_base_instr.VFRSUB;
+  case riscv_instr_name_t.VFMUL_VV: return va_base_instr.VFMUL;
+  case riscv_instr_name_t.VFMUL_VF: return va_base_instr.VFMUL;
+  case riscv_instr_name_t.VFDIV_VV: return va_base_instr.VFDIV;
+  case riscv_instr_name_t.VFDIV_VF: return va_base_instr.VFDIV;
+  case riscv_instr_name_t.VFRDIV_VF: return va_base_instr.VFRDIV;
+  case riscv_instr_name_t.VFWMUL_VV: return va_base_instr.VFWMUL;
+  case riscv_instr_name_t.VFWMUL_VF: return va_base_instr.VFWMUL;
+  case riscv_instr_name_t.VFMACC_VV: return va_base_instr.VFMACC;
+  case riscv_instr_name_t.VFMACC_VF: return va_base_instr.VFMACC;
+  case riscv_instr_name_t.VFNMACC_VV: return va_base_instr.VFNMACC;
+  case riscv_instr_name_t.VFNMACC_VF: return va_base_instr.VFNMACC;
+  case riscv_instr_name_t.VFMSAC_VV: return va_base_instr.VFMSAC;
+  case riscv_instr_name_t.VFMSAC_VF: return va_base_instr.VFMSAC;
+  case riscv_instr_name_t.VFNMSAC_VV: return va_base_instr.VFNMSAC;
+  case riscv_instr_name_t.VFNMSAC_VF: return va_base_instr.VFNMSAC;
+  case riscv_instr_name_t.VFMADD_VV: return va_base_instr.VFMADD;
+  case riscv_instr_name_t.VFMADD_VF: return va_base_instr.VFMADD;
+  case riscv_instr_name_t.VFNMADD_VV: return va_base_instr.VFNMADD;
+  case riscv_instr_name_t.VFNMADD_VF: return va_base_instr.VFNMADD;
+  case riscv_instr_name_t.VFMSUB_VV: return va_base_instr.VFMSUB;
+  case riscv_instr_name_t.VFMSUB_VF: return va_base_instr.VFMSUB;
+  case riscv_instr_name_t.VFNMSUB_VV: return va_base_instr.VFNMSUB;
+  case riscv_instr_name_t.VFNMSUB_VF: return va_base_instr.VFNMSUB;
+  case riscv_instr_name_t.VFWMACC_VV: return va_base_instr.VFWMACC;
+  case riscv_instr_name_t.VFWMACC_VF: return va_base_instr.VFWMACC;
+  case riscv_instr_name_t.VFWNMACC_VV: return va_base_instr.VFWNMACC;
+  case riscv_instr_name_t.VFWNMACC_VF: return va_base_instr.VFWNMACC;
+  case riscv_instr_name_t.VFWMSAC_VV: return va_base_instr.VFWMSAC;
+  case riscv_instr_name_t.VFWMSAC_VF: return va_base_instr.VFWMSAC;
+  case riscv_instr_name_t.VFWNMSAC_VV: return va_base_instr.VFWNMSAC;
+  case riscv_instr_name_t.VFWNMSAC_VF: return va_base_instr.VFWNMSAC;
+  case riscv_instr_name_t.VFMIN_VV: return va_base_instr.VFMIN;
+  case riscv_instr_name_t.VFMIN_VF: return va_base_instr.VFMIN;
+  case riscv_instr_name_t.VFMAX_VV: return va_base_instr.VFMAX;
+  case riscv_instr_name_t.VFMAX_VF: return va_base_instr.VFMAX;
+  case riscv_instr_name_t.VFSGNJ_VV: return va_base_instr.VFSGNJ;
+  case riscv_instr_name_t.VFSGNJ_VF: return va_base_instr.VFSGNJ;
+  case riscv_instr_name_t.VFSGNJN_VV: return va_base_instr.VFSGNJN;
+  case riscv_instr_name_t.VFSGNJN_VF: return va_base_instr.VFSGNJN;
+  case riscv_instr_name_t.VFSGNJX_VV: return va_base_instr.VFSGNJX;
+  case riscv_instr_name_t.VFSGNJX_VF: return va_base_instr.VFSGNJX;
+  case riscv_instr_name_t.VMFEQ_VV: return va_base_instr.VMFEQ;
+  case riscv_instr_name_t.VMFEQ_VF: return va_base_instr.VMFEQ;
+  case riscv_instr_name_t.VMFNE_VV: return va_base_instr.VMFNE;
+  case riscv_instr_name_t.VMFNE_VF: return va_base_instr.VMFNE;
+  case riscv_instr_name_t.VMFLT_VV: return va_base_instr.VMFLT;
+  case riscv_instr_name_t.VMFLT_VF: return va_base_instr.VMFLT;
+  case riscv_instr_name_t.VMFLE_VV: return va_base_instr.VMFLE;
+  case riscv_instr_name_t.VMFLE_VF: return va_base_instr.VMFLE;
+  case riscv_instr_name_t.VMFGT_VF: return va_base_instr.VMFGT;
+  case riscv_instr_name_t.VMFGE_VF: return va_base_instr.VMFGE;
+  case riscv_instr_name_t.VFMERGE_VFM: return va_base_instr.VFMERGE;
+  case riscv_instr_name_t.VFMV_V_F: return va_base_instr.VFMV;
+  case riscv_instr_name_t.VSLIDEUP_VI: return va_base_instr.VSLIDEUP;
+  case riscv_instr_name_t.VSLIDEUP_VX: return va_base_instr.VSLIDEUP;
+  case riscv_instr_name_t.VSLIDEDOWN_VI: return va_base_instr.VSLIDEDOWN;
+  case riscv_instr_name_t.VSLIDEDOWN_VX: return va_base_instr.VSLIDEDOWN;
+  case riscv_instr_name_t.VFSLIDE1UP_VF: return va_base_instr.VFSLIDE1UP;
+  case riscv_instr_name_t.VSLIDE1UP_VX: return va_base_instr.VSLIDE1UP;
+  case riscv_instr_name_t.VFSLIDE1DOWN_VF: return va_base_instr.VFSLIDE1DOWN;
+  case riscv_instr_name_t.VSLIDE1DOWN_VX: return va_base_instr.VSLIDE1DOWN;
+  case riscv_instr_name_t.VRGATHER_VV: return va_base_instr.VRGATHER;
+  case riscv_instr_name_t.VRGATHER_VX: return va_base_instr.VRGATHER;
+  case riscv_instr_name_t.VRGATHER_VI: return va_base_instr.VRGATHER;
+  case riscv_instr_name_t.VRGATHEREI16_VV: return va_base_instr.VRGATHEREI16;
+  case riscv_instr_name_t.VCOMPRESS_VM: return va_base_instr.VCOMPRESS;
+  case riscv_instr_name_t.VFWADD_VF: return va_base_instr.VFWADD;
+  case riscv_instr_name_t.VFWADD_VV: return va_base_instr.VFWADD;
+  case riscv_instr_name_t.VFWADD_WF: return va_base_instr.VFWADD;
+  case riscv_instr_name_t.VFWADD_WV: return va_base_instr.VFWADD;
+  case riscv_instr_name_t.VFWSUB_VF: return va_base_instr.VFWSUB;
+  case riscv_instr_name_t.VFWSUB_VV: return va_base_instr.VFWSUB;
+  case riscv_instr_name_t.VFWSUB_WF: return va_base_instr.VFWSUB;
+  case riscv_instr_name_t.VFWSUB_WV: return va_base_instr.VFWSUB;
+    
+  default: return va_base_instr.VA_NO_BASE;
+  }
 }
 
+
 // Maximum virtual address bits used by the program
 enum uint MAX_USED_VADDR_BITS = 30;
 
@@ -663,23 +1471,111 @@ enum uint SINGLE_PRECISION_FRACTION_BITS = 23;
 enum uint DOUBLE_PRECISION_FRACTION_BITS = 52;
 
 
-enum riscv_reg_t: ubyte {	// 5'b
-  ZERO = 0b00000,
-  RA, SP, GP, TP, T0, T1, T2, S0, S1, A0, A1, A2, A3, A4, A5, A6, A7,
-  S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, T3, T4, T5, T6
+enum riscv_reg_t: ubvec!5 {	// 5'b
+  ZERO = UBVEC!(5, 0),
+  RA   = UBVEC!(5, 1),  
+  SP   = UBVEC!(5, 2),  
+  GP   = UBVEC!(5, 3),  
+  TP   = UBVEC!(5, 4),  
+  T0   = UBVEC!(5, 5),  
+  T1   = UBVEC!(5, 6),  
+  T2   = UBVEC!(5, 7),  
+  S0   = UBVEC!(5, 8),  
+  S1   = UBVEC!(5, 9),  
+  A0   = UBVEC!(5, 10),  
+  A1   = UBVEC!(5, 11),  
+  A2   = UBVEC!(5, 12),  
+  A3   = UBVEC!(5, 13),  
+  A4   = UBVEC!(5, 14),  
+  A5   = UBVEC!(5, 15),  
+  A6   = UBVEC!(5, 16),  
+  A7   = UBVEC!(5, 17),  
+  S2   = UBVEC!(5, 18),  
+  S3   = UBVEC!(5, 19),  
+  S4   = UBVEC!(5, 20),  
+  S5   = UBVEC!(5, 21),  
+  S6   = UBVEC!(5, 22),  
+  S7   = UBVEC!(5, 23),  
+  S8   = UBVEC!(5, 24),  
+  S9   = UBVEC!(5, 25),  
+  S10  = UBVEC!(5, 26),  
+  S11  = UBVEC!(5, 27),  
+  T3   = UBVEC!(5, 28),  
+  T4   = UBVEC!(5, 29),  
+  T5   = UBVEC!(5, 30),  
+  T6   = UBVEC!(5, 31) 
 }
-
-enum riscv_fpr_t: ubyte { 	// 5'b
-  FT0, FT1, FT2, FT3, FT4, FT5, FT6, FT7, FS0, FS1, FA0, FA1, FA2, FA3, FA4, FA5,
-  FA6, FA7, FS2, FS3, FS4, FS5, FS6, FS7, FS8, FS9, FS10, FS11, FT8, FT9, FT10, FT11
+ 
+enum riscv_fpr_t: ubvec!5 { 	// 5'b
+  FT0  = UBVEC!(5, 0), 
+  FT1  = UBVEC!(5, 1), 
+  FT2  = UBVEC!(5, 2), 
+  FT3  = UBVEC!(5, 3), 
+  FT4  = UBVEC!(5, 4), 
+  FT5  = UBVEC!(5, 5), 
+  FT6  = UBVEC!(5, 6), 
+  FT7  = UBVEC!(5, 7), 
+  FS0  = UBVEC!(5, 8), 
+  FS1  = UBVEC!(5, 9), 
+  FA0  = UBVEC!(5, 10),
+  FA1  = UBVEC!(5, 11),
+  FA2  = UBVEC!(5, 12),
+  FA3  = UBVEC!(5, 13),
+  FA4  = UBVEC!(5, 14),
+  FA5  = UBVEC!(5, 15),
+  FA6  = UBVEC!(5, 16),
+  FA7  = UBVEC!(5, 17),
+  FS2  = UBVEC!(5, 18),
+  FS3  = UBVEC!(5, 19),
+  FS4  = UBVEC!(5, 20),
+  FS5  = UBVEC!(5, 21),
+  FS6  = UBVEC!(5, 22),
+  FS7  = UBVEC!(5, 23),
+  FS8  = UBVEC!(5, 24),
+  FS9  = UBVEC!(5, 25),
+  FS10 = UBVEC!(5, 26), 
+  FS11 = UBVEC!(5, 27), 
+  FT8  = UBVEC!(5, 28),
+  FT9  = UBVEC!(5, 29),
+  FT10 = UBVEC!(5, 30), 
+  FT11 = UBVEC!(5, 31)
 }
 
-enum riscv_vreg_t: ubyte {
-  V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15,
-  V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, V28, V29, V30, V31
+enum riscv_vreg_t: ubvec!5 {
+  V0  = UBVEC!(5, 0), 
+  V1  = UBVEC!(5, 1), 
+  V2  = UBVEC!(5, 2), 
+  V3  = UBVEC!(5, 3), 
+  V4  = UBVEC!(5, 4), 
+  V5  = UBVEC!(5, 5), 
+  V6  = UBVEC!(5, 6), 
+  V7  = UBVEC!(5, 7), 
+  V8  = UBVEC!(5, 8), 
+  V9  = UBVEC!(5, 9), 
+  V10 = UBVEC!(5, 10), 
+  V11 = UBVEC!(5, 11), 
+  V12 = UBVEC!(5, 12), 
+  V13 = UBVEC!(5, 13), 
+  V14 = UBVEC!(5, 14), 
+  V15 = UBVEC!(5, 15), 
+  V16 = UBVEC!(5, 16), 
+  V17 = UBVEC!(5, 17), 
+  V18 = UBVEC!(5, 18), 
+  V19 = UBVEC!(5, 19), 
+  V20 = UBVEC!(5, 20), 
+  V21 = UBVEC!(5, 21), 
+  V22 = UBVEC!(5, 22), 
+  V23 = UBVEC!(5, 23), 
+  V24 = UBVEC!(5, 24), 
+  V25 = UBVEC!(5, 25), 
+  V26 = UBVEC!(5, 26), 
+  V27 = UBVEC!(5, 27), 
+  V28 = UBVEC!(5, 28), 
+  V29 = UBVEC!(5, 29), 
+  V30 = UBVEC!(5, 30), 
+  V31 = UBVEC!(5, 31)
 }
 
-
 enum riscv_instr_format_t: ubyte {	// 6'b
   J_FORMAT = 0,
   U_FORMAT,
@@ -713,20 +1609,21 @@ enum riscv_instr_format_t: ubyte {	// 6'b
 
 
 // Vector arithmetic instruction variant
-enum va_variant_t: ubyte {
-  VV,
-  VI,
-  VX,
-  VF,
-  WV,
-  WI,
-  WX,
-  VVM,
-  VIM,
-  VXM,
-  VFM,
-  VS,
-  VM
+enum va_variant_t: ubvec!4 {
+  VV   = UBVEC!(4, 0),  
+  VI   = UBVEC!(4, 1),  
+  VX   = UBVEC!(4, 2),  
+  VF   = UBVEC!(4, 3),  
+  WV   = UBVEC!(4, 4),  
+  WI   = UBVEC!(4, 5),  
+  WX   = UBVEC!(4, 6),  
+  VVM  = UBVEC!(4, 7),  
+  VIM  = UBVEC!(4, 8),  
+  VXM  = UBVEC!(4, 9),  
+  VFM  = UBVEC!(4, 10), 
+  VS   = UBVEC!(4, 11), 
+  VM   = UBVEC!(4, 12),
+  NONE = UBVEC!(4, 13)
 }
 
 enum riscv_instr_category_t: ubyte {	// 6'b
@@ -751,379 +1648,379 @@ enum riscv_instr_category_t: ubyte {	// 6'b
 
 alias riscv_csr_t = ubvec!12;
 
-enum privileged_reg_t: ushort {	// 12'b
+enum privileged_reg_t: ubvec!12 {	// 12'b
     // User mode register
-    USTATUS         = 0x000,  // User status
-    UIE             = 0x004,  // User interrupt-enable register
-    UTVEC           = 0x005,  // User trap-handler base address
-    USCRATCH        = 0x040,  // Scratch register for user trap handlers
-    UEPC            = 0x041,  // User exception program counter
-    UCAUSE          = 0x042,  // User trap cause
-    UTVAL           = 0x043,  // User bad address or instruction
-    UIP             = 0x044,  // User interrupt pending
+    USTATUS         = UBVEC!(12, 0x000),  // User status
+    UIE             = UBVEC!(12, 0x004),  // User interrupt-enable register
+    UTVEC           = UBVEC!(12, 0x005),  // User trap-handler base address
+    USCRATCH        = UBVEC!(12, 0x040),  // Scratch register for user trap handlers
+    UEPC            = UBVEC!(12, 0x041),  // User exception program counter
+    UCAUSE          = UBVEC!(12, 0x042),  // User trap cause
+    UTVAL           = UBVEC!(12, 0x043),  // User bad address or instruction
+    UIP             = UBVEC!(12, 0x044),  // User interrupt pending
     // Unprivileged Floating-Point CSRs
-    FFLAGS          = 0x001,  // Floating-Point Accrued Exceptions
-    FRM             = 0x002,  // Floating-Point Dynamic Rounding Mode
-    FCSR            = 0x003,  // Floating-Point Control/Status Register (FRM + FFLAGS)
+    FFLAGS          = UBVEC!(12, 0x001),  // Floating-Point Accrued Exceptions
+    FRM             = UBVEC!(12, 0x002),  // Floating-Point Dynamic Rounding Mode
+    FCSR            = UBVEC!(12, 0x003),  // Floating-Point Control/Status Register (FRM + FFLAGS)
     // Unprivileged Counter/Timers
-    CYCLE           = 0xC00,  // Cycle counter for RDCYCLE instruction
-    TIME            = 0xC01,  // Timer for RDTIME instruction
-    INSTRET         = 0xC02,  // Instructions-retired counter for RDINSTRET instruction
-    HPMCOUNTER3     = 0xC03,  // Performance-monitoring counter
-    HPMCOUNTER4     = 0xC04,  // Performance-monitoring counter
-    HPMCOUNTER5     = 0xC05,  // Performance-monitoring counter
-    HPMCOUNTER6     = 0xC06,  // Performance-monitoring counter
-    HPMCOUNTER7     = 0xC07,  // Performance-monitoring counter
-    HPMCOUNTER8     = 0xC08,  // Performance-monitoring counter
-    HPMCOUNTER9     = 0xC09,  // Performance-monitoring counter
-    HPMCOUNTER10    = 0xC0A,  // Performance-monitoring counter
-    HPMCOUNTER11    = 0xC0B,  // Performance-monitoring counter
-    HPMCOUNTER12    = 0xC0C,  // Performance-monitoring counter
-    HPMCOUNTER13    = 0xC0D,  // Performance-monitoring counter
-    HPMCOUNTER14    = 0xC0E,  // Performance-monitoring counter
-    HPMCOUNTER15    = 0xC0F,  // Performance-monitoring counter
-    HPMCOUNTER16    = 0xC10,  // Performance-monitoring counter
-    HPMCOUNTER17    = 0xC11,  // Performance-monitoring counter
-    HPMCOUNTER18    = 0xC12,  // Performance-monitoring counter
-    HPMCOUNTER19    = 0xC13,  // Performance-monitoring counter
-    HPMCOUNTER20    = 0xC14,  // Performance-monitoring counter
-    HPMCOUNTER21    = 0xC15,  // Performance-monitoring counter
-    HPMCOUNTER22    = 0xC16,  // Performance-monitoring counter
-    HPMCOUNTER23    = 0xC17,  // Performance-monitoring counter
-    HPMCOUNTER24    = 0xC18,  // Performance-monitoring counter
-    HPMCOUNTER25    = 0xC19,  // Performance-monitoring counter
-    HPMCOUNTER26    = 0xC1A,  // Performance-monitoring counter
-    HPMCOUNTER27    = 0xC1B,  // Performance-monitoring counter
-    HPMCOUNTER28    = 0xC1C,  // Performance-monitoring counter
-    HPMCOUNTER29    = 0xC1D,  // Performance-monitoring counter
-    HPMCOUNTER30    = 0xC1E,  // Performance-monitoring counter
-    HPMCOUNTER31    = 0xC1F,  // Performance-monitoring counter
-    CYCLEH          = 0xC80,  // Upper 32 bits of CYCLE, RV32I only
-    TIMEH           = 0xC81,  // Upper 32 bits of TIME, RV32I only
-    INSTRETH        = 0xC82,  // Upper 32 bits of INSTRET, RV32I only
-    HPMCOUNTER3H    = 0xC83,  // Upper 32 bits of HPMCOUNTER3, RV32I only
-    HPMCOUNTER4H    = 0xC84,  // Upper 32 bits of HPMCOUNTER4, RV32I only
-    HPMCOUNTER5H    = 0xC85,  // Upper 32 bits of HPMCOUNTER5, RV32I only
-    HPMCOUNTER6H    = 0xC86,  // Upper 32 bits of HPMCOUNTER6, RV32I only
-    HPMCOUNTER7H    = 0xC87,  // Upper 32 bits of HPMCOUNTER7, RV32I only
-    HPMCOUNTER8H    = 0xC88,  // Upper 32 bits of HPMCOUNTER8, RV32I only
-    HPMCOUNTER9H    = 0xC89,  // Upper 32 bits of HPMCOUNTER9, RV32I only
-    HPMCOUNTER10H   = 0xC8A,  // Upper 32 bits of HPMCOUNTER10, RV32I only
-    HPMCOUNTER11H   = 0xC8B,  // Upper 32 bits of HPMCOUNTER11, RV32I only
-    HPMCOUNTER12H   = 0xC8C,  // Upper 32 bits of HPMCOUNTER12, RV32I only
-    HPMCOUNTER13H   = 0xC8D,  // Upper 32 bits of HPMCOUNTER13, RV32I only
-    HPMCOUNTER14H   = 0xC8E,  // Upper 32 bits of HPMCOUNTER14, RV32I only
-    HPMCOUNTER15H   = 0xC8F,  // Upper 32 bits of HPMCOUNTER15, RV32I only
-    HPMCOUNTER16H   = 0xC90,  // Upper 32 bits of HPMCOUNTER16, RV32I only
-    HPMCOUNTER17H   = 0xC91,  // Upper 32 bits of HPMCOUNTER17, RV32I only
-    HPMCOUNTER18H   = 0xC92,  // Upper 32 bits of HPMCOUNTER18, RV32I only
-    HPMCOUNTER19H   = 0xC93,  // Upper 32 bits of HPMCOUNTER19, RV32I only
-    HPMCOUNTER20H   = 0xC94,  // Upper 32 bits of HPMCOUNTER20, RV32I only
-    HPMCOUNTER21H   = 0xC95,  // Upper 32 bits of HPMCOUNTER21, RV32I only
-    HPMCOUNTER22H   = 0xC96,  // Upper 32 bits of HPMCOUNTER22, RV32I only
-    HPMCOUNTER23H   = 0xC97,  // Upper 32 bits of HPMCOUNTER23, RV32I only
-    HPMCOUNTER24H   = 0xC98,  // Upper 32 bits of HPMCOUNTER24, RV32I only
-    HPMCOUNTER25H   = 0xC99,  // Upper 32 bits of HPMCOUNTER25, RV32I only
-    HPMCOUNTER26H   = 0xC9A,  // Upper 32 bits of HPMCOUNTER26, RV32I only
-    HPMCOUNTER27H   = 0xC9B,  // Upper 32 bits of HPMCOUNTER27, RV32I only
-    HPMCOUNTER28H   = 0xC9C,  // Upper 32 bits of HPMCOUNTER28, RV32I only
-    HPMCOUNTER29H   = 0xC9D,  // Upper 32 bits of HPMCOUNTER29, RV32I only
-    HPMCOUNTER30H   = 0xC9E,  // Upper 32 bits of HPMCOUNTER30, RV32I only
-    HPMCOUNTER31H   = 0xC9F,  // Upper 32 bits of HPMCOUNTER31, RV32I only
+    CYCLE           = UBVEC!(12, 0xC00),  // Cycle counter for RDCYCLE instruction
+    TIME            = UBVEC!(12, 0xC01),  // Timer for RDTIME instruction
+    INSTRET         = UBVEC!(12, 0xC02),  // Instructions-retired counter for RDINSTRET instruction
+    HPMCOUNTER3     = UBVEC!(12, 0xC03),  // Performance-monitoring counter
+    HPMCOUNTER4     = UBVEC!(12, 0xC04),  // Performance-monitoring counter
+    HPMCOUNTER5     = UBVEC!(12, 0xC05),  // Performance-monitoring counter
+    HPMCOUNTER6     = UBVEC!(12, 0xC06),  // Performance-monitoring counter
+    HPMCOUNTER7     = UBVEC!(12, 0xC07),  // Performance-monitoring counter
+    HPMCOUNTER8     = UBVEC!(12, 0xC08),  // Performance-monitoring counter
+    HPMCOUNTER9     = UBVEC!(12, 0xC09),  // Performance-monitoring counter
+    HPMCOUNTER10    = UBVEC!(12, 0xC0A),  // Performance-monitoring counter
+    HPMCOUNTER11    = UBVEC!(12, 0xC0B),  // Performance-monitoring counter
+    HPMCOUNTER12    = UBVEC!(12, 0xC0C),  // Performance-monitoring counter
+    HPMCOUNTER13    = UBVEC!(12, 0xC0D),  // Performance-monitoring counter
+    HPMCOUNTER14    = UBVEC!(12, 0xC0E),  // Performance-monitoring counter
+    HPMCOUNTER15    = UBVEC!(12, 0xC0F),  // Performance-monitoring counter
+    HPMCOUNTER16    = UBVEC!(12, 0xC10),  // Performance-monitoring counter
+    HPMCOUNTER17    = UBVEC!(12, 0xC11),  // Performance-monitoring counter
+    HPMCOUNTER18    = UBVEC!(12, 0xC12),  // Performance-monitoring counter
+    HPMCOUNTER19    = UBVEC!(12, 0xC13),  // Performance-monitoring counter
+    HPMCOUNTER20    = UBVEC!(12, 0xC14),  // Performance-monitoring counter
+    HPMCOUNTER21    = UBVEC!(12, 0xC15),  // Performance-monitoring counter
+    HPMCOUNTER22    = UBVEC!(12, 0xC16),  // Performance-monitoring counter
+    HPMCOUNTER23    = UBVEC!(12, 0xC17),  // Performance-monitoring counter
+    HPMCOUNTER24    = UBVEC!(12, 0xC18),  // Performance-monitoring counter
+    HPMCOUNTER25    = UBVEC!(12, 0xC19),  // Performance-monitoring counter
+    HPMCOUNTER26    = UBVEC!(12, 0xC1A),  // Performance-monitoring counter
+    HPMCOUNTER27    = UBVEC!(12, 0xC1B),  // Performance-monitoring counter
+    HPMCOUNTER28    = UBVEC!(12, 0xC1C),  // Performance-monitoring counter
+    HPMCOUNTER29    = UBVEC!(12, 0xC1D),  // Performance-monitoring counter
+    HPMCOUNTER30    = UBVEC!(12, 0xC1E),  // Performance-monitoring counter
+    HPMCOUNTER31    = UBVEC!(12, 0xC1F),  // Performance-monitoring counter
+    CYCLEH          = UBVEC!(12, 0xC80),  // Upper 32 bits of CYCLE, RV32I only
+    TIMEH           = UBVEC!(12, 0xC81),  // Upper 32 bits of TIME, RV32I only
+    INSTRETH        = UBVEC!(12, 0xC82),  // Upper 32 bits of INSTRET, RV32I only
+    HPMCOUNTER3H    = UBVEC!(12, 0xC83),  // Upper 32 bits of HPMCOUNTER3, RV32I only
+    HPMCOUNTER4H    = UBVEC!(12, 0xC84),  // Upper 32 bits of HPMCOUNTER4, RV32I only
+    HPMCOUNTER5H    = UBVEC!(12, 0xC85),  // Upper 32 bits of HPMCOUNTER5, RV32I only
+    HPMCOUNTER6H    = UBVEC!(12, 0xC86),  // Upper 32 bits of HPMCOUNTER6, RV32I only
+    HPMCOUNTER7H    = UBVEC!(12, 0xC87),  // Upper 32 bits of HPMCOUNTER7, RV32I only
+    HPMCOUNTER8H    = UBVEC!(12, 0xC88),  // Upper 32 bits of HPMCOUNTER8, RV32I only
+    HPMCOUNTER9H    = UBVEC!(12, 0xC89),  // Upper 32 bits of HPMCOUNTER9, RV32I only
+    HPMCOUNTER10H   = UBVEC!(12, 0xC8A),  // Upper 32 bits of HPMCOUNTER10, RV32I only
+    HPMCOUNTER11H   = UBVEC!(12, 0xC8B),  // Upper 32 bits of HPMCOUNTER11, RV32I only
+    HPMCOUNTER12H   = UBVEC!(12, 0xC8C),  // Upper 32 bits of HPMCOUNTER12, RV32I only
+    HPMCOUNTER13H   = UBVEC!(12, 0xC8D),  // Upper 32 bits of HPMCOUNTER13, RV32I only
+    HPMCOUNTER14H   = UBVEC!(12, 0xC8E),  // Upper 32 bits of HPMCOUNTER14, RV32I only
+    HPMCOUNTER15H   = UBVEC!(12, 0xC8F),  // Upper 32 bits of HPMCOUNTER15, RV32I only
+    HPMCOUNTER16H   = UBVEC!(12, 0xC90),  // Upper 32 bits of HPMCOUNTER16, RV32I only
+    HPMCOUNTER17H   = UBVEC!(12, 0xC91),  // Upper 32 bits of HPMCOUNTER17, RV32I only
+    HPMCOUNTER18H   = UBVEC!(12, 0xC92),  // Upper 32 bits of HPMCOUNTER18, RV32I only
+    HPMCOUNTER19H   = UBVEC!(12, 0xC93),  // Upper 32 bits of HPMCOUNTER19, RV32I only
+    HPMCOUNTER20H   = UBVEC!(12, 0xC94),  // Upper 32 bits of HPMCOUNTER20, RV32I only
+    HPMCOUNTER21H   = UBVEC!(12, 0xC95),  // Upper 32 bits of HPMCOUNTER21, RV32I only
+    HPMCOUNTER22H   = UBVEC!(12, 0xC96),  // Upper 32 bits of HPMCOUNTER22, RV32I only
+    HPMCOUNTER23H   = UBVEC!(12, 0xC97),  // Upper 32 bits of HPMCOUNTER23, RV32I only
+    HPMCOUNTER24H   = UBVEC!(12, 0xC98),  // Upper 32 bits of HPMCOUNTER24, RV32I only
+    HPMCOUNTER25H   = UBVEC!(12, 0xC99),  // Upper 32 bits of HPMCOUNTER25, RV32I only
+    HPMCOUNTER26H   = UBVEC!(12, 0xC9A),  // Upper 32 bits of HPMCOUNTER26, RV32I only
+    HPMCOUNTER27H   = UBVEC!(12, 0xC9B),  // Upper 32 bits of HPMCOUNTER27, RV32I only
+    HPMCOUNTER28H   = UBVEC!(12, 0xC9C),  // Upper 32 bits of HPMCOUNTER28, RV32I only
+    HPMCOUNTER29H   = UBVEC!(12, 0xC9D),  // Upper 32 bits of HPMCOUNTER29, RV32I only
+    HPMCOUNTER30H   = UBVEC!(12, 0xC9E),  // Upper 32 bits of HPMCOUNTER30, RV32I only
+    HPMCOUNTER31H   = UBVEC!(12, 0xC9F),  // Upper 32 bits of HPMCOUNTER31, RV32I only
     // Supervisor mode register
     // Supervisor Trap Setup
-    SSTATUS         = 0x100,  // Supervisor status
-    SEDELEG         = 0x102,  // Supervisor exception delegation register
-    SIDELEG         = 0x103,  // Supervisor interrupt delegation register
-    SIE             = 0x104,  // Supervisor interrupt-enable register
-    STVEC           = 0x105,  // Supervisor trap-handler base address
-    SCOUNTEREN      = 0x106,  // Supervisor counter enable
+    SSTATUS         = UBVEC!(12, 0x100),  // Supervisor status
+    SEDELEG         = UBVEC!(12, 0x102),  // Supervisor exception delegation register
+    SIDELEG         = UBVEC!(12, 0x103),  // Supervisor interrupt delegation register
+    SIE             = UBVEC!(12, 0x104),  // Supervisor interrupt-enable register
+    STVEC           = UBVEC!(12, 0x105),  // Supervisor trap-handler base address
+    SCOUNTEREN      = UBVEC!(12, 0x106),  // Supervisor counter enable
     // Supervisor Configuration
-    SENVCFG         = 0x10A,  // Supervisor environment configuration register
+    SENVCFG         = UBVEC!(12, 0x10A),  // Supervisor environment configuration register
     // Supervisor Trap Handling
-    SSCRATCH        = 0x140,  // Scratch register for supervisor trap handlers
-    SEPC            = 0x141,  // Supervisor exception program counter
-    SCAUSE          = 0x142,  // Supervisor trap cause
-    STVAL           = 0x143,  // Supervisor bad address or instruction
-    SIP             = 0x144,  // Supervisor interrupt pending
+    SSCRATCH        = UBVEC!(12, 0x140),  // Scratch register for supervisor trap handlers
+    SEPC            = UBVEC!(12, 0x141),  // Supervisor exception program counter
+    SCAUSE          = UBVEC!(12, 0x142),  // Supervisor trap cause
+    STVAL           = UBVEC!(12, 0x143),  // Supervisor bad address or instruction
+    SIP             = UBVEC!(12, 0x144),  // Supervisor interrupt pending
     // Supervisor Protection and Translation
-    SATP            = 0x180,  // Supervisor address translation and protection
+    SATP            = UBVEC!(12, 0x180),  // Supervisor address translation and protection
     // Supervisor Debug/Trace Register
-    SCONTEXT        = 0x5A8,  // Supervisor environment configuration register.
+    SCONTEXT        = UBVEC!(12, 0x5A8),  // Supervisor environment configuration register.
     // Hypervisor Trap Setup register
-    HSTATUS         = 0x600,  // Hypervisor status register
-    HEDELEG         = 0x602,  // Hypervisor exception delegation register
-    HIDELEG         = 0x603,  // Hypervisor interrupt delegation register
-    HIE             = 0x604,  // Hypervisor interrupt-enable register
-    HCOUNTEREN      = 0x606,  // Hypervisor counter enable
-    HGEIE           = 0x607,  // Hypervisor guest external interrupt-enable register
+    HSTATUS         = UBVEC!(12, 0x600),  // Hypervisor status register
+    HEDELEG         = UBVEC!(12, 0x602),  // Hypervisor exception delegation register
+    HIDELEG         = UBVEC!(12, 0x603),  // Hypervisor interrupt delegation register
+    HIE             = UBVEC!(12, 0x604),  // Hypervisor interrupt-enable register
+    HCOUNTEREN      = UBVEC!(12, 0x606),  // Hypervisor counter enable
+    HGEIE           = UBVEC!(12, 0x607),  // Hypervisor guest external interrupt-enable register
     // Hypervisor Trap Handling
-    HTVAL           = 0x643,  // Hypervisor bad guest physical address
-    HIP             = 0x644,  // Hypervisor interrupt pending
-    HVIP            = 0x645,  // Hypervisor virtual interrupt pending
-    HTINST          = 0x64A,  // Hypervisor trap instruction (transformed)
-    HGEIP           = 0xE12,  // Hypervisor guest external interrupt pending
+    HTVAL           = UBVEC!(12, 0x643),  // Hypervisor bad guest physical address
+    HIP             = UBVEC!(12, 0x644),  // Hypervisor interrupt pending
+    HVIP            = UBVEC!(12, 0x645),  // Hypervisor virtual interrupt pending
+    HTINST          = UBVEC!(12, 0x64A),  // Hypervisor trap instruction (transformed)
+    HGEIP           = UBVEC!(12, 0xE12),  // Hypervisor guest external interrupt pending
     // Hypervisor configuration
-    HENVCFG         = 0x60A,  // Hypervisor environment configuration register
-    HENVCFGH        = 0x61A,  // Additional hypervisor env. conf. register, RV32 only
+    HENVCFG         = UBVEC!(12, 0x60A),  // Hypervisor environment configuration register
+    HENVCFGH        = UBVEC!(12, 0x61A),  // Additional hypervisor env. conf. register, RV32 only
     // Hypervisor guest address translation and protection
-    HGATP           = 0x680,  // Hypervisor guest address translation and protection
+    HGATP           = UBVEC!(12, 0x680),  // Hypervisor guest address translation and protection
     // Hypervisor Debug/Trace registers
-    HCONTEXT        = 0x6A8,  // Hypervisor-mode context register
+    HCONTEXT        = UBVEC!(12, 0x6A8),  // Hypervisor-mode context register
     // Hypervisor Counter/Timer Virtualization Registers
-    HTIMEDELTA      = 0x605,  // Delta for VS/VU-mode timer
-    HTIMEDELTAH     = 0x615,  // Upper 32 bits of htimedelta, HSXLEN=32 only
+    HTIMEDELTA      = UBVEC!(12, 0x605),  // Delta for VS/VU-mode timer
+    HTIMEDELTAH     = UBVEC!(12, 0x615),  // Upper 32 bits of htimedelta, HSXLEN=32 only
     // Virtual Supervisor Registers
-    VSSTATUS        = 0x200,  // Virtual supervisor status register
-    VSIE            = 0x204,  // Virtual supervisor interrupt-enable register
-    VSTVEC          = 0x205,  // Virtual supervisor trap handler base address
-    VSSCRATCH       = 0x240,  // Virtual supervisor scratch register
-    VSEPC           = 0x241,  // Virtual supervisor exception program counter
-    VSCAUSE         = 0x242,  // Virtual supervisor trap cause
-    VSTVAL          = 0x243,  // Virtual supervisor bad address or instruction
-    VSIP            = 0x244,  // Virtual supervisor interrupt pending
-    VSATP           = 0x280,  // Virtual supervisor address translation and protection
+    VSSTATUS        = UBVEC!(12, 0x200),  // Virtual supervisor status register
+    VSIE            = UBVEC!(12, 0x204),  // Virtual supervisor interrupt-enable register
+    VSTVEC          = UBVEC!(12, 0x205),  // Virtual supervisor trap handler base address
+    VSSCRATCH       = UBVEC!(12, 0x240),  // Virtual supervisor scratch register
+    VSEPC           = UBVEC!(12, 0x241),  // Virtual supervisor exception program counter
+    VSCAUSE         = UBVEC!(12, 0x242),  // Virtual supervisor trap cause
+    VSTVAL          = UBVEC!(12, 0x243),  // Virtual supervisor bad address or instruction
+    VSIP            = UBVEC!(12, 0x244),  // Virtual supervisor interrupt pending
+    VSATP           = UBVEC!(12, 0x280),  // Virtual supervisor address translation and protection
     // Machine mode registers
     // Machine Information Registers
-    MVENDORID       = 0xF11,  // Vendor ID
-    MARCHID         = 0xF12,  // Architecture ID
-    MIMPID          = 0xF13,  // Implementation ID
-    MHARTID         = 0xF14,  // Hardware thread ID
-    MCONFIGPTR      = 0xF15,  // Pointer to configuration data structure
+    MVENDORID       = UBVEC!(12, 0xF11),  // Vendor ID
+    MARCHID         = UBVEC!(12, 0xF12),  // Architecture ID
+    MIMPID          = UBVEC!(12, 0xF13),  // Implementation ID
+    MHARTID         = UBVEC!(12, 0xF14),  // Hardware thread ID
+    MCONFIGPTR      = UBVEC!(12, 0xF15),  // Pointer to configuration data structure
     // Machine Trap Setup
-    MSTATUS         = 0x300,  // Machine status
-    MISA            = 0x301,  // ISA and extensions
-    MEDELEG         = 0x302,  // Machine exception delegation register
-    MIDELEG         = 0x303,  // Machine interrupt delegation register
-    MIE             = 0x304,  // Machine interrupt-enable register
-    MTVEC           = 0x305,  // Machine trap-handler base address
-    MCOUNTEREN      = 0x306,  // Machine counter enable
-    MSTATUSH        = 0x310,  // Additional machine status register, RV32 only
+    MSTATUS         = UBVEC!(12, 0x300),  // Machine status
+    MISA            = UBVEC!(12, 0x301),  // ISA and extensions
+    MEDELEG         = UBVEC!(12, 0x302),  // Machine exception delegation register
+    MIDELEG         = UBVEC!(12, 0x303),  // Machine interrupt delegation register
+    MIE             = UBVEC!(12, 0x304),  // Machine interrupt-enable register
+    MTVEC           = UBVEC!(12, 0x305),  // Machine trap-handler base address
+    MCOUNTEREN      = UBVEC!(12, 0x306),  // Machine counter enable
+    MSTATUSH        = UBVEC!(12, 0x310),  // Additional machine status register, RV32 only
     // Machine Trap Handling
-    MSCRATCH        = 0x340,  // Scratch register for machine trap handlers
-    MEPC            = 0x341,  // Machine exception program counter
-    MCAUSE          = 0x342,  // Machine trap cause
-    MTVAL           = 0x343,  // Machine bad address or instruction
-    MIP             = 0x344,  // Machine interrupt pending
+    MSCRATCH        = UBVEC!(12, 0x340),  // Scratch register for machine trap handlers
+    MEPC            = UBVEC!(12, 0x341),  // Machine exception program counter
+    MCAUSE          = UBVEC!(12, 0x342),  // Machine trap cause
+    MTVAL           = UBVEC!(12, 0x343),  // Machine bad address or instruction
+    MIP             = UBVEC!(12, 0x344),  // Machine interrupt pending
     // Machine Configuration
-    MENVCFG         = 0x30A,  // Machine environment configuration register
-    MENVCFGH        = 0x31A,  // Additional machine env. conf. register, RV32 only
-    MSECCFG         = 0x747,  // Machine security configuration register
-    MSECCFGH        = 0x757,  // Additional machine security conf. register, RV32 only
+    MENVCFG         = UBVEC!(12, 0x30A),  // Machine environment configuration register
+    MENVCFGH        = UBVEC!(12, 0x31A),  // Additional machine env. conf. register, RV32 only
+    MSECCFG         = UBVEC!(12, 0x747),  // Machine security configuration register
+    MSECCFGH        = UBVEC!(12, 0x757),  // Additional machine security conf. register, RV32 only
     // Machine Memory Protection
-    PMPCFG0         = 0x3A0,  // Physical memory protection configuration
-    PMPCFG1         = 0x3A1,  // Physical memory protection configuration, RV32 only
-    PMPCFG2         = 0x3A2,  // Physical memory protection configuration
-    PMPCFG3         = 0x3A3,  // Physical memory protection configuration, RV32 only
-    PMPCFG4         = 0x3A4,  // Physical memory protection configuration
-    PMPCFG5         = 0x3A5,  // Physical memory protection configuration, RV32 only
-    PMPCFG6         = 0x3A6,  // Physical memory protection configuration
-    PMPCFG7         = 0x3A7,  // Physical memory protection configuration, RV32 only
-    PMPCFG8         = 0x3A8,  // Physical memory protection configuration
-    PMPCFG9         = 0x3A9,  // Physical memory protection configuration, RV32 only
-    PMPCFG10        = 0x3AA,  // Physical memory protection configuration
-    PMPCFG11        = 0x3AB,  // Physical memory protection configuration, RV32 only
-    PMPCFG12        = 0x3AC,  // Physical memory protection configuration
-    PMPCFG13        = 0x3AD,  // Physical memory protection configuration, RV32 only
-    PMPCFG14        = 0x3AE,  // Physical memory protection configuration
-    PMPCFG15        = 0x3AF,  // Physical memory protection configuration, RV32 only
-    PMPADDR0        = 0x3B0,  // Physical memory protection address register
-    PMPADDR1        = 0x3B1,  // Physical memory protection address register
-    PMPADDR2        = 0x3B2,  // Physical memory protection address register
-    PMPADDR3        = 0x3B3,  // Physical memory protection address register
-    PMPADDR4        = 0x3B4,  // Physical memory protection address register
-    PMPADDR5        = 0x3B5,  // Physical memory protection address register
-    PMPADDR6        = 0x3B6,  // Physical memory protection address register
-    PMPADDR7        = 0x3B7,  // Physical memory protection address register
-    PMPADDR8        = 0x3B8,  // Physical memory protection address register
-    PMPADDR9        = 0x3B9,  // Physical memory protection address register
-    PMPADDR10       = 0x3BA,  // Physical memory protection address register
-    PMPADDR11       = 0x3BB,  // Physical memory protection address register
-    PMPADDR12       = 0x3BC,  // Physical memory protection address register
-    PMPADDR13       = 0x3BD,  // Physical memory protection address register
-    PMPADDR14       = 0x3BE,  // Physical memory protection address register
-    PMPADDR15       = 0x3BF,  // Physical memory protection address register
-    PMPADDR16       = 0x4C0,  // Physical memory protection address register
-    PMPADDR17       = 0x3C1,  // Physical memory protection address register
-    PMPADDR18       = 0x3C2,  // Physical memory protection address register
-    PMPADDR19       = 0x3C3,  // Physical memory protection address register
-    PMPADDR20       = 0x3C4,  // Physical memory protection address register
-    PMPADDR21       = 0x3C5,  // Physical memory protection address register
-    PMPADDR22       = 0x3C6,  // Physical memory protection address register
-    PMPADDR23       = 0x3C7,  // Physical memory protection address register
-    PMPADDR24       = 0x3C8,  // Physical memory protection address register
-    PMPADDR25       = 0x3C9,  // Physical memory protection address register
-    PMPADDR26       = 0x3CA,  // Physical memory protection address register
-    PMPADDR27       = 0x3CB,  // Physical memory protection address register
-    PMPADDR28       = 0x3CC,  // Physical memory protection address register
-    PMPADDR29       = 0x3CD,  // Physical memory protection address register
-    PMPADDR30       = 0x3CE,  // Physical memory protection address register
-    PMPADDR31       = 0x3CF,  // Physical memory protection address register
-    PMPADDR32       = 0x4D0,  // Physical memory protection address register
-    PMPADDR33       = 0x3D1,  // Physical memory protection address register
-    PMPADDR34       = 0x3D2,  // Physical memory protection address register
-    PMPADDR35       = 0x3D3,  // Physical memory protection address register
-    PMPADDR36       = 0x3D4,  // Physical memory protection address register
-    PMPADDR37       = 0x3D5,  // Physical memory protection address register
-    PMPADDR38       = 0x3D6,  // Physical memory protection address register
-    PMPADDR39       = 0x3D7,  // Physical memory protection address register
-    PMPADDR40       = 0x3D8,  // Physical memory protection address register
-    PMPADDR41       = 0x3D9,  // Physical memory protection address register
-    PMPADDR42       = 0x3DA,  // Physical memory protection address register
-    PMPADDR43       = 0x3DB,  // Physical memory protection address register
-    PMPADDR44       = 0x3DC,  // Physical memory protection address register
-    PMPADDR45       = 0x3DD,  // Physical memory protection address register
-    PMPADDR46       = 0x3DE,  // Physical memory protection address register
-    PMPADDR47       = 0x3DF,  // Physical memory protection address register
-    PMPADDR48       = 0x4E0,  // Physical memory protection address register
-    PMPADDR49       = 0x3E1,  // Physical memory protection address register
-    PMPADDR50       = 0x3E2,  // Physical memory protection address register
-    PMPADDR51       = 0x3E3,  // Physical memory protection address register
-    PMPADDR52       = 0x3E4,  // Physical memory protection address register
-    PMPADDR53       = 0x3E5,  // Physical memory protection address register
-    PMPADDR54       = 0x3E6,  // Physical memory protection address register
-    PMPADDR55       = 0x3E7,  // Physical memory protection address register
-    PMPADDR56       = 0x3E8,  // Physical memory protection address register
-    PMPADDR57       = 0x3E9,  // Physical memory protection address register
-    PMPADDR58       = 0x3EA,  // Physical memory protection address register
-    PMPADDR59       = 0x3EB,  // Physical memory protection address register
-    PMPADDR60       = 0x3EC,  // Physical memory protection address register
-    PMPADDR61       = 0x3ED,  // Physical memory protection address register
-    PMPADDR62       = 0x3EE,  // Physical memory protection address register
-    PMPADDR63       = 0x3EF,  // Physical memory protection address register
-    MCYCLE          = 0xB00,  // Machine cycle counter
-    MINSTRET        = 0xB02,  // Machine instructions-retired counter
-    MHPMCOUNTER3    = 0xB03,  // Machine performance-monitoring counter
-    MHPMCOUNTER4    = 0xB04,  // Machine performance-monitoring counter
-    MHPMCOUNTER5    = 0xB05,  // Machine performance-monitoring counter
-    MHPMCOUNTER6    = 0xB06,  // Machine performance-monitoring counter
-    MHPMCOUNTER7    = 0xB07,  // Machine performance-monitoring counter
-    MHPMCOUNTER8    = 0xB08,  // Machine performance-monitoring counter
-    MHPMCOUNTER9    = 0xB09,  // Machine performance-monitoring counter
-    MHPMCOUNTER10   = 0xB0A,  // Machine performance-monitoring counter
-    MHPMCOUNTER11   = 0xB0B,  // Machine performance-monitoring counter
-    MHPMCOUNTER12   = 0xB0C,  // Machine performance-monitoring counter
-    MHPMCOUNTER13   = 0xB0D,  // Machine performance-monitoring counter
-    MHPMCOUNTER14   = 0xB0E,  // Machine performance-monitoring counter
-    MHPMCOUNTER15   = 0xB0F,  // Machine performance-monitoring counter
-    MHPMCOUNTER16   = 0xB10,  // Machine performance-monitoring counter
-    MHPMCOUNTER17   = 0xB11,  // Machine performance-monitoring counter
-    MHPMCOUNTER18   = 0xB12,  // Machine performance-monitoring counter
-    MHPMCOUNTER19   = 0xB13,  // Machine performance-monitoring counter
-    MHPMCOUNTER20   = 0xB14,  // Machine performance-monitoring counter
-    MHPMCOUNTER21   = 0xB15,  // Machine performance-monitoring counter
-    MHPMCOUNTER22   = 0xB16,  // Machine performance-monitoring counter
-    MHPMCOUNTER23   = 0xB17,  // Machine performance-monitoring counter
-    MHPMCOUNTER24   = 0xB18,  // Machine performance-monitoring counter
-    MHPMCOUNTER25   = 0xB19,  // Machine performance-monitoring counter
-    MHPMCOUNTER26   = 0xB1A,  // Machine performance-monitoring counter
-    MHPMCOUNTER27   = 0xB1B,  // Machine performance-monitoring counter
-    MHPMCOUNTER28   = 0xB1C,  // Machine performance-monitoring counter
-    MHPMCOUNTER29   = 0xB1D,  // Machine performance-monitoring counter
-    MHPMCOUNTER30   = 0xB1E,  // Machine performance-monitoring counter
-    MHPMCOUNTER31   = 0xB1F,  // Machine performance-monitoring counter
-    MCYCLEH         = 0xB80,  // Upper 32 bits of MCYCLE, RV32I only
-    MINSTRETH       = 0xB82,  // Upper 32 bits of MINSTRET, RV32I only
-    MHPMCOUNTER3H   = 0xB83,  // Upper 32 bits of HPMCOUNTER3, RV32I only
-    MHPMCOUNTER4H   = 0xB84,  // Upper 32 bits of HPMCOUNTER4, RV32I only
-    MHPMCOUNTER5H   = 0xB85,  // Upper 32 bits of HPMCOUNTER5, RV32I only
-    MHPMCOUNTER6H   = 0xB86,  // Upper 32 bits of HPMCOUNTER6, RV32I only
-    MHPMCOUNTER7H   = 0xB87,  // Upper 32 bits of HPMCOUNTER7, RV32I only
-    MHPMCOUNTER8H   = 0xB88,  // Upper 32 bits of HPMCOUNTER8, RV32I only
-    MHPMCOUNTER9H   = 0xB89,  // Upper 32 bits of HPMCOUNTER9, RV32I only
-    MHPMCOUNTER10H  = 0xB8A,  // Upper 32 bits of HPMCOUNTER10, RV32I only
-    MHPMCOUNTER11H  = 0xB8B,  // Upper 32 bits of HPMCOUNTER11, RV32I only
-    MHPMCOUNTER12H  = 0xB8C,  // Upper 32 bits of HPMCOUNTER12, RV32I only
-    MHPMCOUNTER13H  = 0xB8D,  // Upper 32 bits of HPMCOUNTER13, RV32I only
-    MHPMCOUNTER14H  = 0xB8E,  // Upper 32 bits of HPMCOUNTER14, RV32I only
-    MHPMCOUNTER15H  = 0xB8F,  // Upper 32 bits of HPMCOUNTER15, RV32I only
-    MHPMCOUNTER16H  = 0xB90,  // Upper 32 bits of HPMCOUNTER16, RV32I only
-    MHPMCOUNTER17H  = 0xB91,  // Upper 32 bits of HPMCOUNTER17, RV32I only
-    MHPMCOUNTER18H  = 0xB92,  // Upper 32 bits of HPMCOUNTER18, RV32I only
-    MHPMCOUNTER19H  = 0xB93,  // Upper 32 bits of HPMCOUNTER19, RV32I only
-    MHPMCOUNTER20H  = 0xB94,  // Upper 32 bits of HPMCOUNTER20, RV32I only
-    MHPMCOUNTER21H  = 0xB95,  // Upper 32 bits of HPMCOUNTER21, RV32I only
-    MHPMCOUNTER22H  = 0xB96,  // Upper 32 bits of HPMCOUNTER22, RV32I only
-    MHPMCOUNTER23H  = 0xB97,  // Upper 32 bits of HPMCOUNTER23, RV32I only
-    MHPMCOUNTER24H  = 0xB98,  // Upper 32 bits of HPMCOUNTER24, RV32I only
-    MHPMCOUNTER25H  = 0xB99,  // Upper 32 bits of HPMCOUNTER25, RV32I only
-    MHPMCOUNTER26H  = 0xB9A,  // Upper 32 bits of HPMCOUNTER26, RV32I only
-    MHPMCOUNTER27H  = 0xB9B,  // Upper 32 bits of HPMCOUNTER27, RV32I only
-    MHPMCOUNTER28H  = 0xB9C,  // Upper 32 bits of HPMCOUNTER28, RV32I only
-    MHPMCOUNTER29H  = 0xB9D,  // Upper 32 bits of HPMCOUNTER29, RV32I only
-    MHPMCOUNTER30H  = 0xB9E,  // Upper 32 bits of HPMCOUNTER30, RV32I only
-    MHPMCOUNTER31H  = 0xB9F,  // Upper 32 bits of HPMCOUNTER31, RV32I only
-    MCOUNTINHIBIT   = 0x320,  // Machine counter-inhibit register
-    MHPMEVENT3      = 0x323,  // Machine performance-monitoring event selector
-    MHPMEVENT4      = 0x324,  // Machine performance-monitoring event selector
-    MHPMEVENT5      = 0x325,  // Machine performance-monitoring event selector
-    MHPMEVENT6      = 0x326,  // Machine performance-monitoring event selector
-    MHPMEVENT7      = 0x327,  // Machine performance-monitoring event selector
-    MHPMEVENT8      = 0x328,  // Machine performance-monitoring event selector
-    MHPMEVENT9      = 0x329,  // Machine performance-monitoring event selector
-    MHPMEVENT10     = 0x32A,  // Machine performance-monitoring event selector
-    MHPMEVENT11     = 0x32B,  // Machine performance-monitoring event selector
-    MHPMEVENT12     = 0x32C,  // Machine performance-monitoring event selector
-    MHPMEVENT13     = 0x32D,  // Machine performance-monitoring event selector
-    MHPMEVENT14     = 0x32E,  // Machine performance-monitoring event selector
-    MHPMEVENT15     = 0x32F,  // Machine performance-monitoring event selector
-    MHPMEVENT16     = 0x330,  // Machine performance-monitoring event selector
-    MHPMEVENT17     = 0x331,  // Machine performance-monitoring event selector
-    MHPMEVENT18     = 0x332,  // Machine performance-monitoring event selector
-    MHPMEVENT19     = 0x333,  // Machine performance-monitoring event selector
-    MHPMEVENT20     = 0x334,  // Machine performance-monitoring event selector
-    MHPMEVENT21     = 0x335,  // Machine performance-monitoring event selector
-    MHPMEVENT22     = 0x336,  // Machine performance-monitoring event selector
-    MHPMEVENT23     = 0x337,  // Machine performance-monitoring event selector
-    MHPMEVENT24     = 0x338,  // Machine performance-monitoring event selector
-    MHPMEVENT25     = 0x339,  // Machine performance-monitoring event selector
-    MHPMEVENT26     = 0x33A,  // Machine performance-monitoring event selector
-    MHPMEVENT27     = 0x33B,  // Machine performance-monitoring event selector
-    MHPMEVENT28     = 0x33C,  // Machine performance-monitoring event selector
-    MHPMEVENT29     = 0x33D,  // Machine performance-monitoring event selector
-    MHPMEVENT30     = 0x33E,  // Machine performance-monitoring event selector
-    MHPMEVENT31     = 0x33F,  // Machine performance-monitoring event selector
+    PMPCFG0         = UBVEC!(12, 0x3A0),  // Physical memory protection configuration
+    PMPCFG1         = UBVEC!(12, 0x3A1),  // Physical memory protection configuration, RV32 only
+    PMPCFG2         = UBVEC!(12, 0x3A2),  // Physical memory protection configuration
+    PMPCFG3         = UBVEC!(12, 0x3A3),  // Physical memory protection configuration, RV32 only
+    PMPCFG4         = UBVEC!(12, 0x3A4),  // Physical memory protection configuration
+    PMPCFG5         = UBVEC!(12, 0x3A5),  // Physical memory protection configuration, RV32 only
+    PMPCFG6         = UBVEC!(12, 0x3A6),  // Physical memory protection configuration
+    PMPCFG7         = UBVEC!(12, 0x3A7),  // Physical memory protection configuration, RV32 only
+    PMPCFG8         = UBVEC!(12, 0x3A8),  // Physical memory protection configuration
+    PMPCFG9         = UBVEC!(12, 0x3A9),  // Physical memory protection configuration, RV32 only
+    PMPCFG10        = UBVEC!(12, 0x3AA),  // Physical memory protection configuration
+    PMPCFG11        = UBVEC!(12, 0x3AB),  // Physical memory protection configuration, RV32 only
+    PMPCFG12        = UBVEC!(12, 0x3AC),  // Physical memory protection configuration
+    PMPCFG13        = UBVEC!(12, 0x3AD),  // Physical memory protection configuration, RV32 only
+    PMPCFG14        = UBVEC!(12, 0x3AE),  // Physical memory protection configuration
+    PMPCFG15        = UBVEC!(12, 0x3AF),  // Physical memory protection configuration, RV32 only
+    PMPADDR0        = UBVEC!(12, 0x3B0),  // Physical memory protection address register
+    PMPADDR1        = UBVEC!(12, 0x3B1),  // Physical memory protection address register
+    PMPADDR2        = UBVEC!(12, 0x3B2),  // Physical memory protection address register
+    PMPADDR3        = UBVEC!(12, 0x3B3),  // Physical memory protection address register
+    PMPADDR4        = UBVEC!(12, 0x3B4),  // Physical memory protection address register
+    PMPADDR5        = UBVEC!(12, 0x3B5),  // Physical memory protection address register
+    PMPADDR6        = UBVEC!(12, 0x3B6),  // Physical memory protection address register
+    PMPADDR7        = UBVEC!(12, 0x3B7),  // Physical memory protection address register
+    PMPADDR8        = UBVEC!(12, 0x3B8),  // Physical memory protection address register
+    PMPADDR9        = UBVEC!(12, 0x3B9),  // Physical memory protection address register
+    PMPADDR10       = UBVEC!(12, 0x3BA),  // Physical memory protection address register
+    PMPADDR11       = UBVEC!(12, 0x3BB),  // Physical memory protection address register
+    PMPADDR12       = UBVEC!(12, 0x3BC),  // Physical memory protection address register
+    PMPADDR13       = UBVEC!(12, 0x3BD),  // Physical memory protection address register
+    PMPADDR14       = UBVEC!(12, 0x3BE),  // Physical memory protection address register
+    PMPADDR15       = UBVEC!(12, 0x3BF),  // Physical memory protection address register
+    PMPADDR16       = UBVEC!(12, 0x4C0),  // Physical memory protection address register
+    PMPADDR17       = UBVEC!(12, 0x3C1),  // Physical memory protection address register
+    PMPADDR18       = UBVEC!(12, 0x3C2),  // Physical memory protection address register
+    PMPADDR19       = UBVEC!(12, 0x3C3),  // Physical memory protection address register
+    PMPADDR20       = UBVEC!(12, 0x3C4),  // Physical memory protection address register
+    PMPADDR21       = UBVEC!(12, 0x3C5),  // Physical memory protection address register
+    PMPADDR22       = UBVEC!(12, 0x3C6),  // Physical memory protection address register
+    PMPADDR23       = UBVEC!(12, 0x3C7),  // Physical memory protection address register
+    PMPADDR24       = UBVEC!(12, 0x3C8),  // Physical memory protection address register
+    PMPADDR25       = UBVEC!(12, 0x3C9),  // Physical memory protection address register
+    PMPADDR26       = UBVEC!(12, 0x3CA),  // Physical memory protection address register
+    PMPADDR27       = UBVEC!(12, 0x3CB),  // Physical memory protection address register
+    PMPADDR28       = UBVEC!(12, 0x3CC),  // Physical memory protection address register
+    PMPADDR29       = UBVEC!(12, 0x3CD),  // Physical memory protection address register
+    PMPADDR30       = UBVEC!(12, 0x3CE),  // Physical memory protection address register
+    PMPADDR31       = UBVEC!(12, 0x3CF),  // Physical memory protection address register
+    PMPADDR32       = UBVEC!(12, 0x4D0),  // Physical memory protection address register
+    PMPADDR33       = UBVEC!(12, 0x3D1),  // Physical memory protection address register
+    PMPADDR34       = UBVEC!(12, 0x3D2),  // Physical memory protection address register
+    PMPADDR35       = UBVEC!(12, 0x3D3),  // Physical memory protection address register
+    PMPADDR36       = UBVEC!(12, 0x3D4),  // Physical memory protection address register
+    PMPADDR37       = UBVEC!(12, 0x3D5),  // Physical memory protection address register
+    PMPADDR38       = UBVEC!(12, 0x3D6),  // Physical memory protection address register
+    PMPADDR39       = UBVEC!(12, 0x3D7),  // Physical memory protection address register
+    PMPADDR40       = UBVEC!(12, 0x3D8),  // Physical memory protection address register
+    PMPADDR41       = UBVEC!(12, 0x3D9),  // Physical memory protection address register
+    PMPADDR42       = UBVEC!(12, 0x3DA),  // Physical memory protection address register
+    PMPADDR43       = UBVEC!(12, 0x3DB),  // Physical memory protection address register
+    PMPADDR44       = UBVEC!(12, 0x3DC),  // Physical memory protection address register
+    PMPADDR45       = UBVEC!(12, 0x3DD),  // Physical memory protection address register
+    PMPADDR46       = UBVEC!(12, 0x3DE),  // Physical memory protection address register
+    PMPADDR47       = UBVEC!(12, 0x3DF),  // Physical memory protection address register
+    PMPADDR48       = UBVEC!(12, 0x4E0),  // Physical memory protection address register
+    PMPADDR49       = UBVEC!(12, 0x3E1),  // Physical memory protection address register
+    PMPADDR50       = UBVEC!(12, 0x3E2),  // Physical memory protection address register
+    PMPADDR51       = UBVEC!(12, 0x3E3),  // Physical memory protection address register
+    PMPADDR52       = UBVEC!(12, 0x3E4),  // Physical memory protection address register
+    PMPADDR53       = UBVEC!(12, 0x3E5),  // Physical memory protection address register
+    PMPADDR54       = UBVEC!(12, 0x3E6),  // Physical memory protection address register
+    PMPADDR55       = UBVEC!(12, 0x3E7),  // Physical memory protection address register
+    PMPADDR56       = UBVEC!(12, 0x3E8),  // Physical memory protection address register
+    PMPADDR57       = UBVEC!(12, 0x3E9),  // Physical memory protection address register
+    PMPADDR58       = UBVEC!(12, 0x3EA),  // Physical memory protection address register
+    PMPADDR59       = UBVEC!(12, 0x3EB),  // Physical memory protection address register
+    PMPADDR60       = UBVEC!(12, 0x3EC),  // Physical memory protection address register
+    PMPADDR61       = UBVEC!(12, 0x3ED),  // Physical memory protection address register
+    PMPADDR62       = UBVEC!(12, 0x3EE),  // Physical memory protection address register
+    PMPADDR63       = UBVEC!(12, 0x3EF),  // Physical memory protection address register
+    MCYCLE          = UBVEC!(12, 0xB00),  // Machine cycle counter
+    MINSTRET        = UBVEC!(12, 0xB02),  // Machine instructions-retired counter
+    MHPMCOUNTER3    = UBVEC!(12, 0xB03),  // Machine performance-monitoring counter
+    MHPMCOUNTER4    = UBVEC!(12, 0xB04),  // Machine performance-monitoring counter
+    MHPMCOUNTER5    = UBVEC!(12, 0xB05),  // Machine performance-monitoring counter
+    MHPMCOUNTER6    = UBVEC!(12, 0xB06),  // Machine performance-monitoring counter
+    MHPMCOUNTER7    = UBVEC!(12, 0xB07),  // Machine performance-monitoring counter
+    MHPMCOUNTER8    = UBVEC!(12, 0xB08),  // Machine performance-monitoring counter
+    MHPMCOUNTER9    = UBVEC!(12, 0xB09),  // Machine performance-monitoring counter
+    MHPMCOUNTER10   = UBVEC!(12, 0xB0A),  // Machine performance-monitoring counter
+    MHPMCOUNTER11   = UBVEC!(12, 0xB0B),  // Machine performance-monitoring counter
+    MHPMCOUNTER12   = UBVEC!(12, 0xB0C),  // Machine performance-monitoring counter
+    MHPMCOUNTER13   = UBVEC!(12, 0xB0D),  // Machine performance-monitoring counter
+    MHPMCOUNTER14   = UBVEC!(12, 0xB0E),  // Machine performance-monitoring counter
+    MHPMCOUNTER15   = UBVEC!(12, 0xB0F),  // Machine performance-monitoring counter
+    MHPMCOUNTER16   = UBVEC!(12, 0xB10),  // Machine performance-monitoring counter
+    MHPMCOUNTER17   = UBVEC!(12, 0xB11),  // Machine performance-monitoring counter
+    MHPMCOUNTER18   = UBVEC!(12, 0xB12),  // Machine performance-monitoring counter
+    MHPMCOUNTER19   = UBVEC!(12, 0xB13),  // Machine performance-monitoring counter
+    MHPMCOUNTER20   = UBVEC!(12, 0xB14),  // Machine performance-monitoring counter
+    MHPMCOUNTER21   = UBVEC!(12, 0xB15),  // Machine performance-monitoring counter
+    MHPMCOUNTER22   = UBVEC!(12, 0xB16),  // Machine performance-monitoring counter
+    MHPMCOUNTER23   = UBVEC!(12, 0xB17),  // Machine performance-monitoring counter
+    MHPMCOUNTER24   = UBVEC!(12, 0xB18),  // Machine performance-monitoring counter
+    MHPMCOUNTER25   = UBVEC!(12, 0xB19),  // Machine performance-monitoring counter
+    MHPMCOUNTER26   = UBVEC!(12, 0xB1A),  // Machine performance-monitoring counter
+    MHPMCOUNTER27   = UBVEC!(12, 0xB1B),  // Machine performance-monitoring counter
+    MHPMCOUNTER28   = UBVEC!(12, 0xB1C),  // Machine performance-monitoring counter
+    MHPMCOUNTER29   = UBVEC!(12, 0xB1D),  // Machine performance-monitoring counter
+    MHPMCOUNTER30   = UBVEC!(12, 0xB1E),  // Machine performance-monitoring counter
+    MHPMCOUNTER31   = UBVEC!(12, 0xB1F),  // Machine performance-monitoring counter
+    MCYCLEH         = UBVEC!(12, 0xB80),  // Upper 32 bits of MCYCLE, RV32I only
+    MINSTRETH       = UBVEC!(12, 0xB82),  // Upper 32 bits of MINSTRET, RV32I only
+    MHPMCOUNTER3H   = UBVEC!(12, 0xB83),  // Upper 32 bits of HPMCOUNTER3, RV32I only
+    MHPMCOUNTER4H   = UBVEC!(12, 0xB84),  // Upper 32 bits of HPMCOUNTER4, RV32I only
+    MHPMCOUNTER5H   = UBVEC!(12, 0xB85),  // Upper 32 bits of HPMCOUNTER5, RV32I only
+    MHPMCOUNTER6H   = UBVEC!(12, 0xB86),  // Upper 32 bits of HPMCOUNTER6, RV32I only
+    MHPMCOUNTER7H   = UBVEC!(12, 0xB87),  // Upper 32 bits of HPMCOUNTER7, RV32I only
+    MHPMCOUNTER8H   = UBVEC!(12, 0xB88),  // Upper 32 bits of HPMCOUNTER8, RV32I only
+    MHPMCOUNTER9H   = UBVEC!(12, 0xB89),  // Upper 32 bits of HPMCOUNTER9, RV32I only
+    MHPMCOUNTER10H  = UBVEC!(12, 0xB8A),  // Upper 32 bits of HPMCOUNTER10, RV32I only
+    MHPMCOUNTER11H  = UBVEC!(12, 0xB8B),  // Upper 32 bits of HPMCOUNTER11, RV32I only
+    MHPMCOUNTER12H  = UBVEC!(12, 0xB8C),  // Upper 32 bits of HPMCOUNTER12, RV32I only
+    MHPMCOUNTER13H  = UBVEC!(12, 0xB8D),  // Upper 32 bits of HPMCOUNTER13, RV32I only
+    MHPMCOUNTER14H  = UBVEC!(12, 0xB8E),  // Upper 32 bits of HPMCOUNTER14, RV32I only
+    MHPMCOUNTER15H  = UBVEC!(12, 0xB8F),  // Upper 32 bits of HPMCOUNTER15, RV32I only
+    MHPMCOUNTER16H  = UBVEC!(12, 0xB90),  // Upper 32 bits of HPMCOUNTER16, RV32I only
+    MHPMCOUNTER17H  = UBVEC!(12, 0xB91),  // Upper 32 bits of HPMCOUNTER17, RV32I only
+    MHPMCOUNTER18H  = UBVEC!(12, 0xB92),  // Upper 32 bits of HPMCOUNTER18, RV32I only
+    MHPMCOUNTER19H  = UBVEC!(12, 0xB93),  // Upper 32 bits of HPMCOUNTER19, RV32I only
+    MHPMCOUNTER20H  = UBVEC!(12, 0xB94),  // Upper 32 bits of HPMCOUNTER20, RV32I only
+    MHPMCOUNTER21H  = UBVEC!(12, 0xB95),  // Upper 32 bits of HPMCOUNTER21, RV32I only
+    MHPMCOUNTER22H  = UBVEC!(12, 0xB96),  // Upper 32 bits of HPMCOUNTER22, RV32I only
+    MHPMCOUNTER23H  = UBVEC!(12, 0xB97),  // Upper 32 bits of HPMCOUNTER23, RV32I only
+    MHPMCOUNTER24H  = UBVEC!(12, 0xB98),  // Upper 32 bits of HPMCOUNTER24, RV32I only
+    MHPMCOUNTER25H  = UBVEC!(12, 0xB99),  // Upper 32 bits of HPMCOUNTER25, RV32I only
+    MHPMCOUNTER26H  = UBVEC!(12, 0xB9A),  // Upper 32 bits of HPMCOUNTER26, RV32I only
+    MHPMCOUNTER27H  = UBVEC!(12, 0xB9B),  // Upper 32 bits of HPMCOUNTER27, RV32I only
+    MHPMCOUNTER28H  = UBVEC!(12, 0xB9C),  // Upper 32 bits of HPMCOUNTER28, RV32I only
+    MHPMCOUNTER29H  = UBVEC!(12, 0xB9D),  // Upper 32 bits of HPMCOUNTER29, RV32I only
+    MHPMCOUNTER30H  = UBVEC!(12, 0xB9E),  // Upper 32 bits of HPMCOUNTER30, RV32I only
+    MHPMCOUNTER31H  = UBVEC!(12, 0xB9F),  // Upper 32 bits of HPMCOUNTER31, RV32I only
+    MCOUNTINHIBIT   = UBVEC!(12, 0x320),  // Machine counter-inhibit register
+    MHPMEVENT3      = UBVEC!(12, 0x323),  // Machine performance-monitoring event selector
+    MHPMEVENT4      = UBVEC!(12, 0x324),  // Machine performance-monitoring event selector
+    MHPMEVENT5      = UBVEC!(12, 0x325),  // Machine performance-monitoring event selector
+    MHPMEVENT6      = UBVEC!(12, 0x326),  // Machine performance-monitoring event selector
+    MHPMEVENT7      = UBVEC!(12, 0x327),  // Machine performance-monitoring event selector
+    MHPMEVENT8      = UBVEC!(12, 0x328),  // Machine performance-monitoring event selector
+    MHPMEVENT9      = UBVEC!(12, 0x329),  // Machine performance-monitoring event selector
+    MHPMEVENT10     = UBVEC!(12, 0x32A),  // Machine performance-monitoring event selector
+    MHPMEVENT11     = UBVEC!(12, 0x32B),  // Machine performance-monitoring event selector
+    MHPMEVENT12     = UBVEC!(12, 0x32C),  // Machine performance-monitoring event selector
+    MHPMEVENT13     = UBVEC!(12, 0x32D),  // Machine performance-monitoring event selector
+    MHPMEVENT14     = UBVEC!(12, 0x32E),  // Machine performance-monitoring event selector
+    MHPMEVENT15     = UBVEC!(12, 0x32F),  // Machine performance-monitoring event selector
+    MHPMEVENT16     = UBVEC!(12, 0x330),  // Machine performance-monitoring event selector
+    MHPMEVENT17     = UBVEC!(12, 0x331),  // Machine performance-monitoring event selector
+    MHPMEVENT18     = UBVEC!(12, 0x332),  // Machine performance-monitoring event selector
+    MHPMEVENT19     = UBVEC!(12, 0x333),  // Machine performance-monitoring event selector
+    MHPMEVENT20     = UBVEC!(12, 0x334),  // Machine performance-monitoring event selector
+    MHPMEVENT21     = UBVEC!(12, 0x335),  // Machine performance-monitoring event selector
+    MHPMEVENT22     = UBVEC!(12, 0x336),  // Machine performance-monitoring event selector
+    MHPMEVENT23     = UBVEC!(12, 0x337),  // Machine performance-monitoring event selector
+    MHPMEVENT24     = UBVEC!(12, 0x338),  // Machine performance-monitoring event selector
+    MHPMEVENT25     = UBVEC!(12, 0x339),  // Machine performance-monitoring event selector
+    MHPMEVENT26     = UBVEC!(12, 0x33A),  // Machine performance-monitoring event selector
+    MHPMEVENT27     = UBVEC!(12, 0x33B),  // Machine performance-monitoring event selector
+    MHPMEVENT28     = UBVEC!(12, 0x33C),  // Machine performance-monitoring event selector
+    MHPMEVENT29     = UBVEC!(12, 0x33D),  // Machine performance-monitoring event selector
+    MHPMEVENT30     = UBVEC!(12, 0x33E),  // Machine performance-monitoring event selector
+    MHPMEVENT31     = UBVEC!(12, 0x33F),  // Machine performance-monitoring event selector
     // Debug/Trace Registers (shared with Debug Mode)
-    TSELECT         = 0x7A0,  // Debug/Trace trigger register select
-    TDATA1          = 0x7A1,  // First Debug/Trace trigger data register
-    TDATA2          = 0x7A2,  // Second Debug/Trace trigger data register
-    TDATA3          = 0x7A3,  // Third Debug/Trace trigger data register
-    TINFO           = 0x7A4,  // Debug trigger info register
-    TCONTROL        = 0x7A5,  // Debug trigger control register
-    MCONTEXT        = 0x7A8,  // Machine mode trigger context register
-    MSCONTEXT       = 0x7AA,  // Supervisor mode trigger context register
+    TSELECT         = UBVEC!(12, 0x7A0),  // Debug/Trace trigger register select
+    TDATA1          = UBVEC!(12, 0x7A1),  // First Debug/Trace trigger data register
+    TDATA2          = UBVEC!(12, 0x7A2),  // Second Debug/Trace trigger data register
+    TDATA3          = UBVEC!(12, 0x7A3),  // Third Debug/Trace trigger data register
+    TINFO           = UBVEC!(12, 0x7A4),  // Debug trigger info register
+    TCONTROL        = UBVEC!(12, 0x7A5),  // Debug trigger control register
+    MCONTEXT        = UBVEC!(12, 0x7A8),  // Machine mode trigger context register
+    MSCONTEXT       = UBVEC!(12, 0x7AA),  // Supervisor mode trigger context register
     // Debug Mode Registers
-    DCSR            = 0x7B0,  // Debug control and status register
-    DPC             = 0x7B1,  // Debug PC
-    DSCRATCH0       = 0x7B2,  // Debug scratch register
-    DSCRATCH1       = 0x7B3,  // Debug scratch register (last one)
-    VSTART          = 0x008,  // Vector start position
-    VXSTAT          = 0x009,  // Fixed point saturate flag
-    VXRM            = 0x00A,  // Fixed point rounding mode
-    VL              = 0xC20,  // Vector length
-    VTYPE           = 0xC21,  // Vector data type register
-    VLENB           = 0xC22   // VLEN/8 (vector register length in bytes)
+    DCSR            = UBVEC!(12, 0x7B0),  // Debug control and status register
+    DPC             = UBVEC!(12, 0x7B1),  // Debug PC
+    DSCRATCH0       = UBVEC!(12, 0x7B2),  // Debug scratch register
+    DSCRATCH1       = UBVEC!(12, 0x7B3),  // Debug scratch register (last one)
+    VSTART          = UBVEC!(12, 0x008),  // Vector start position
+    VXSTAT          = UBVEC!(12, 0x009),  // Fixed point saturate flag
+    VXRM            = UBVEC!(12, 0x00A),  // Fixed point rounding mode
+    VL              = UBVEC!(12, 0xC20),  // Vector length
+    VTYPE           = UBVEC!(12, 0xC21),  // Vector data type register
+    VLENB           = UBVEC!(12, 0xC22),   // VLEN/8 (vector register length in bytes)
 }
 
-enum privileged_reg_fld_t: ubyte {
-  RSVD,       // Reserved field
-  MXL,        // mis.mxl
-  EXTENSION,  // mis.extension
-  MODE,       // satp.mode
-  ASID,       // satp.asid
-  PPN         // satp.ppn
+enum privileged_reg_fld_t: ubvec!5 {
+  RSVD       = UBVEC!(5, 0),  // Reserved field
+  MXL        = UBVEC!(5, 1),  // mis.mxl
+  EXTENSION  = UBVEC!(5, 2),  // mis.extension
+  MODE       = UBVEC!(5, 3),  // satp.mode
+  ASID       = UBVEC!(5, 4),  // satp.asid
+  PPN        = UBVEC!(5, 5)   // satp.ppn
 }
 
-enum privileged_level_t: ubyte {
-  M_LEVEL = 0b11,  // Machine mode
-  S_LEVEL = 0b01,  // Supervisor mode
-  U_LEVEL = 0b00   // User mode
+enum privileged_level_t: ubvec!2 {
+  M_LEVEL = UBVEC!(2, 0b11),  // Machine mode
+  S_LEVEL = UBVEC!(2, 0b01),  // Supervisor mode
+  U_LEVEL = UBVEC!(2, 0b00)   // User mode
 }
 
-enum reg_field_access_t: ubyte {
-  WPRI, // Reserved Writes Preserve Values, Reads Ignore Value
-  WLRL, // Write/Read Only Legal Values
-  WARL  // Write Any Values, Reads Legal Values
+enum reg_field_access_t: ubvec!2 {
+  WPRI = UBVEC!(2, 0b00), // Reserved Writes Preserve Values, Reads Ignore Value
+  WLRL = UBVEC!(2, 0b01), // Write/Read Only Legal Values
+  WARL = UBVEC!(2, 0b10)  // Write Any Values, Reads Legal Values
 }
 
 //Pseudo instructions
@@ -1133,19 +2030,19 @@ enum riscv_pseudo_instr_name_t: ubyte {
 }
 
 // Data pattern of the memory model
-enum data_pattern_t: ubyte {
-  RAND_DATA = 0,
-  ALL_ZERO,
-  INCR_VAL
+enum data_pattern_t: ubvec!2 {
+  RAND_DATA = UBVEC!(2, 0b00),
+  ALL_ZERO  = UBVEC!(2, 0b01),
+  INCR_VAL  = UBVEC!(2, 0b10)
 }
 
-enum pte_permission_t: ubyte {
-  NEXT_LEVEL_PAGE   = 0b000, // Pointer to next level of page table.
-  READ_ONLY_PAGE    = 0b001, // Read-only page.
-  READ_WRITE_PAGE   = 0b011, // Read-write page.
-  EXECUTE_ONLY_PAGE = 0b100, // Execute-only page.
-  READ_EXECUTE_PAGE = 0b101, // Read-execute page.
-  R_W_EXECUTE_PAGE  = 0b111  // Read-write-execute page
+enum pte_permission_t: ubvec!3 {
+  NEXT_LEVEL_PAGE   = UBVEC!(3, 0b000), // Pointer to next level of page table.
+  READ_ONLY_PAGE    = UBVEC!(3, 0b001), // Read-only page.
+  READ_WRITE_PAGE   = UBVEC!(3, 0b011), // Read-write page.
+  EXECUTE_ONLY_PAGE = UBVEC!(3, 0b100), // Execute-only page.
+  READ_EXECUTE_PAGE = UBVEC!(3, 0b101), // Read-execute page.
+  R_W_EXECUTE_PAGE  = UBVEC!(3, 0b111)  // Read-write-execute page
 }
 
 enum interrupt_cause_t: ubyte {
@@ -1206,21 +2103,32 @@ enum  misa_ext_t: int {
   MISA_EXT_Z
 }
 
-enum hazard_e: ubyte {
-  NO_HAZARD,
-  RAW_HAZARD,
-  WAR_HAZARD,
-  WAW_HAZARD
+enum hazard_e: ubvec!2 {
+  NO_HAZARD   = UBVEC!(2, 0b00),
+  RAW_HAZARD  = UBVEC!(2, 0b01),
+  WAR_HAZARD  = UBVEC!(2, 0b10),
+  WAW_HAZARD  = UBVEC!(2, 0b11)
 }
 
+riscv_csr_t[] default_include_csr_write = [privileged_reg_t.MSCRATCH];
+
 // `include "riscv_core_setting.sv"
 
+// ePMP machine security configuration
+struct mseccfg_reg_t {
+  @UVM_DEFAULT {
+    @rand bool rlb;
+    @rand bool mmwp;
+    @rand bool mml;
+  }
+}
+
 // PMP address matching mode
-enum pmp_addr_mode_t: ubyte {
-  OFF   = 0b00,
-  TOR   = 0b01,
-  NA4   = 0b10,
-  NAPOT = 0b11
+enum pmp_addr_mode_t: ubvec!2 {
+  OFF   = UBVEC!(2, 0b00),
+  TOR   = UBVEC!(2, 0b01),
+  NA4   = UBVEC!(2, 0b10),
+  NAPOT = UBVEC!(2, 0b11)
 }
 
 //   // PMP configuration register layout
@@ -1250,10 +2158,12 @@ struct pmp_cfg_reg_t {
   @rand bool                   r;
   // RV32: the pmpaddr is the top 32 bits of a 34 bit PMP address
   // RV64: the pmpaddr is the top 54 bits of a 56 bit PMP address
-  ubvec!XLEN    addr;
+  @rand ubvec!XLEN    addr;
   // The offset from the address of <main> - automatically populated by the
   // PMP generation routine.
   @rand ubvec!XLEN    offset;
+  // The size of the region in case of NAPOT and overlap in case of TOR.
+  @rand int addr_mode;
 }
 
 
@@ -1283,11 +2193,11 @@ struct vtype_t {
 }
 
 
-enum vxrm_t: ubyte {
-  RoundToNearestUp,
-  RoundToNearestEven,
-  RoundDown,
-  RoundToOdd
+enum vxrm_t: ubvec!2 {
+  RoundToNearestUp    = UBVEC!(2, 0b00),
+  RoundToNearestEven  = UBVEC!(2, 0b01),
+  RoundDown           = UBVEC!(2, 0b10),
+  RoundToOdd          = UBVEC!(2, 0b11)
 }
 
 enum  b_ext_group_t: int {
@@ -1332,6 +2242,8 @@ template SPACES(uint spaces) {
   else enum SPACES = SPACES!(spaces-1) ~ " ";
 }
 
+enum string INDENT = SPACES!LABEL_STR_LEN;
+
 string spaces_string(uint len) {
   import std.algorithm: fill;
   char[] str = new char[len];
@@ -1339,16 +2251,14 @@ string spaces_string(uint len) {
   return cast(string) str;
 }
 
-enum string indent = SPACES!LABEL_STR_LEN;
 
 // Format the string to a fixed length
 string format_string(string str, int len = 10) {
   if (len < str.length) return str;
   else {
     static string spaces;
-    if (spaces.length == 0) spaces = spaces_string(len);
-    string formatted_str = str ~ spaces[0..len-str.length];
-    return formatted_str;
+    if (spaces.length < len) spaces = spaces_string(len);
+    return str ~ spaces[0..len-str.length];
   }
 }
 
@@ -1392,18 +2302,18 @@ void push_gpr_to_kernel_stack(privileged_reg_t status,
 
   string store_instr = (XLEN == 32) ? "sw" : "sd";
   if (canFind(implemented_csr, scratch)) {
-    // Use kernal stack for handling exceptions
-    // Save the user mode stack pointer to the scratch register
-    instr ~= format("csrrw x%0d, 0x%0x, x%0d", sp, scratch, sp);
-    // Move TP to SP
+    // Push USP from gpr.SP onto the kernel stack
+    instr ~= format("addi x%0d, x%0d, -4", tp, tp);
+    instr ~= format("%0s  x%0d, (x%0d)", store_instr, sp, tp);
+    // Move KSP to gpr.SP
     instr ~= format("add x%0d, x%0d, zero", sp, tp);
   }
   // If MPRV is set and MPP is S/U mode, it means the address translation and memory protection
   // for load/store instruction is the same as the mode indicated by MPP. In this case, we
   // need to use the virtual address to access the kernel stack.
   if ((status == privileged_reg_t.MSTATUS) && (SATP_MODE != satp_mode_t.BARE)) {
-    // We temporarily use tp to check mstatus to avoid changing other GPR. The value of sp has
-    // been saved to xScratch and can be restored later.
+    // We temporarily use tp to check mstatus to avoid changing other GPR.
+    // (The value of sp has been pushed to the kernel stack, so can be recovered later)
     if (mprv) {
       instr ~= format("csrr x%0d, 0x%0x // MSTATUS", tp, status);
       instr ~= format("srli x%0d, x%0d, 11", tp, tp);  // Move MPP to bit 0
@@ -1414,14 +2324,18 @@ void push_gpr_to_kernel_stack(privileged_reg_t status,
       // Use virtual address for stack pointer
       instr ~= format("slli x%0d, x%0d, %0d", sp, sp, XLEN - MAX_USED_VADDR_BITS);
       instr ~= format("srli x%0d, x%0d, %0d", sp, sp, XLEN - MAX_USED_VADDR_BITS);
+      instr ~= "1: nop";
     }
   }
-  // Reserve space from kernel stack to save all 32 GPR except for x0
-  instr ~= format("1: addi x%0d, x%0d, -%0d", sp, sp, 31 * (XLEN/8));
-  // Push all GPRs to kernel stack
+  // Push all GPRs (except for x0) to kernel stack
+  // (gpr.SP currently holds the KSP)
+  instr ~= format("addi x%0d, x%0d, -%0d", sp, sp, 32 * (XLEN/8));
   for (int i = 1; i < 32; i++) {
     instr ~= format("%0s  x%0d, %0d(x%0d)", store_instr, i, i * (XLEN/8), sp);
   }
+  // Move KSP back to gpr.TP
+  // (this is needed if we again take a interrupt (nested) before restoring our USP)
+  instr ~= format("add x%0d, x%0d, zero", tp, sp);
 }
 
 // Pop general purpose register from stack, this is needed before returning to user program
@@ -1435,17 +2349,19 @@ void pop_gpr_from_kernel_stack(privileged_reg_t status,
   import std.string: format;
 
   string load_instr = (XLEN == 32) ? "lw" : "ld";
-  // Pop user mode GPRs from kernel stack
+  // Move KSP to gpr.SP
+  instr ~= format("add x%0d, x%0d, zero", sp, tp);
+  // Pop GPRs from kernel stack
   for (int i = 1; i < 32; i++) {
     instr ~= format("%0s  x%0d, %0d(x%0d)", load_instr, i, i * (XLEN/8), sp);
   }
-  // Restore kernel stack pointer
-  instr ~= format("addi x%0d, x%0d, %0d", sp, sp, 31 * (XLEN/8));
+  instr ~= format("addi x%0d, x%0d, %0d", sp, sp, 32 * (XLEN/8));
   if (canFind(implemented_csr, scratch)) {
-    // Move SP to TP
+    // Move KSP back to gpr.TP
     instr ~= format("add x%0d, x%0d, zero", tp, sp);
-    // Restore user mode stack pointer
-    instr ~= format("csrrw x%0d, 0x%0x, x%0d", sp, scratch, sp);
+    // Pop USP from the kernel stack, move back to gpr.SP
+    instr ~= format("%0s  x%0d, (x%0d)", load_instr, sp, tp);
+    instr ~= format("addi x%0d, x%0d, 4", tp, tp);
   }
 }
 
@@ -1457,6 +2373,14 @@ void get_int_arg_value(string cmdline_str, ref int val) {
   }
 }
 
+void get_uint_arg_value(string cmdline_str, ref uint val) {
+  import std.conv: to;
+  string s;
+  if (uvm_cmdline_processor.get_inst().get_arg_value(cmdline_str, s)) {
+    val = s.to!uint;
+  }
+}
+
 
 // Get a bool argument from comand line
 void get_bool_arg_value(string cmdline_str, ref bool val) {
@@ -1479,8 +2403,10 @@ void get_hex_arg_value(string cmdline_str, ref int val) {
 
 class cmdline_enum_processor(T)
 {
-  static void get_array_values(string cmdline_str, ref T[] vals) {
+  static void get_array_values(string cmdline_str, bool allow_raw_vals, ref T[] vals) {
     import std.format: format;
+    import std.conv: parse;
+    import std.traits: OriginalType;
     string s;
     uvm_cmdline_processor.get_inst().get_arg_value(cmdline_str, s);
     if (s != "") {
@@ -1490,7 +2416,22 @@ class cmdline_enum_processor(T)
       vals.length = cmdline_list.length;
       foreach (i, str; cmdline_list) {
 	import std.string: toUpper;
-	if (uvm_enum_wrapper!T.from_name(toUpper(str), value)) {
+	if (allow_raw_vals && str[0..2] == "0x") {
+	  // SV version declares a logic vec and then uses atohex
+	  // atohex always returns an int though -- so let us use int
+	  // enum C = bits!T;
+	  // ulvec!C raw_val;
+	  string valstr = str[2..$].dup;
+	  int raw_val = parse!(int, string)(valstr, 16);
+	  static if (isBitVector!T) {
+	    ubvec!32 raw_bvec = raw_val.toubvec!32;
+	    vals[i] = cast(T) raw_bvec; // cast to enum
+	  }
+	  else {
+	    vals[i] = cast(T) raw_val; // cast to enum
+	  }
+	}
+	else if (uvm_enum_wrapper!T.from_name(toUpper(str), value)) {
 	  vals[i] = value;
 	}
 	else {
@@ -1537,3 +2478,4 @@ void get_val(string str, out bvec!XLEN val, bool hex = 0) {
   uvm_info("riscv_instr_pkg", format("imm:%0s -> 0x%0x/%0d", str, val,
 				     cast(bvec!XLEN) val), UVM_FULL);
 }
+
diff --git a/euvm/riscv/gen/riscv_instr_registry.d b/euvm/riscv/gen/riscv_instr_registry.d
index a0bd5010..df591f4d 100644
--- a/euvm/riscv/gen/riscv_instr_registry.d
+++ b/euvm/riscv/gen/riscv_instr_registry.d
@@ -29,9 +29,13 @@ import riscv.gen.target: unsupported_instr, supported_isa,
 
 import std.format: format;
 import std.algorithm: canFind, remove;
+import std.algorithm.sorting: sort;
 import std.traits: EnumMembers;
 
 import esdl.base.rand: urandom;
+import esdl.experimental.allocator.tcallocator: TCallocator;
+import std.container.array: Array;
+import esdl.data.vector: Vector;
 
 import uvm;
 
@@ -44,6 +48,7 @@ class riscv_instr_registry: uvm_object
 
   // Instruction list
   riscv_instr_name_t[]                          instr_names;
+  riscv_instr_name_t[]                          instr_names_sorted;
 
   // Categorized instruction list
   riscv_instr_name_t[][riscv_instr_group_t]     instr_group;
@@ -51,11 +56,8 @@ class riscv_instr_registry: uvm_object
   riscv_instr_name_t[]                          basic_instr;
   riscv_instr[riscv_instr_name_t]               instr_template;
 
-  // Privileged CSR filter
-  privileged_reg_t[]                            exclude_reg;
-  privileged_reg_t[]                            include_reg;
-
   riscv_instr_gen_config                        cfg;
+  static TCallocator!(1024*1024)                tcallocator;
 
   this (string name="") {
     super(name);
@@ -96,6 +98,8 @@ class riscv_instr_registry: uvm_object
       if (!cfg.enable_sfence && instr_name == riscv_instr_name_t.SFENCE_VMA) continue;
       if (cfg.no_fence && (instr_name.inside(riscv_instr_name_t.FENCE,
 					     riscv_instr_name_t.FENCE_I,
+					     riscv_instr_name_t.FENCE_TSO,
+					     riscv_instr_name_t.PAUSE,
 					     riscv_instr_name_t.SFENCE_VMA))) continue;
       if (canFind(supported_isa, instr_inst.group) &&
           !(cfg.disable_compressed_instr &&
@@ -115,30 +119,8 @@ class riscv_instr_registry: uvm_object
       }
     }
     build_basic_instruction_list(cfg);
-    create_csr_filter(cfg);
-  }
-
-  void create_csr_filter(riscv_instr_gen_config cfg) {
-    include_reg.length = 0;
-    exclude_reg.length = 0;
-    if (cfg.enable_illegal_csr_instruction) {
-      exclude_reg = implemented_csr;
-    }
-    else if (cfg.enable_access_invalid_csr_level) {
-      include_reg = cfg.invalid_priv_mode_csrs;
-    }
-    else {
-      // Use scratch register to avoid the side effect of modifying other privileged mode CSR.
-      if (cfg.init_privileged_mode == privileged_mode_t.MACHINE_MODE) {
-	include_reg = [privileged_reg_t.MSCRATCH];
-      }
-      else if (cfg.init_privileged_mode == privileged_mode_t.SUPERVISOR_MODE) {
-	include_reg = [privileged_reg_t.SSCRATCH];
-      }
-      else {
-	include_reg = [privileged_reg_t.USCRATCH];
-      }
-    }
+    instr_names_sorted = instr_names.dup;
+    instr_names_sorted.sort();
   }
 
   riscv_instr create_instr(riscv_instr_name_t instr_name, string instr_class_name) {
@@ -173,6 +155,9 @@ class riscv_instr_registry: uvm_object
 	}
       }
     }
+    if (cfg.no_ecall == 0) {
+      basic_instr ~= riscv_instr_name_t.ECALL;
+    }
     if (cfg.no_dret == 0) {
       basic_instr ~= riscv_instr_name_t.DRET;
     }
@@ -222,9 +207,15 @@ class riscv_instr_registry: uvm_object
     ulong  idx;
     riscv_instr_name_t name;
     // riscv_instr_name_t name;
-    riscv_instr_name_t[] allowed_instr;
-    riscv_instr_name_t[] disallowed_instr;
-    riscv_instr_category_t[] allowed_categories;
+
+    static Vector!(riscv_instr_name_t, "allowed_instr") allowed_instr;
+    static Vector!(riscv_instr_name_t, "disallowed_instr") disallowed_instr;
+    static Vector!(riscv_instr_category_t, "allowed_categories") allowed_categories;
+
+    allowed_instr.length = 0;
+    disallowed_instr.length = 0;
+    allowed_categories.length = 0;
+    
     foreach (icatg; include_category) {
       allowed_instr ~= instr_category[icatg];
     }
@@ -258,9 +249,8 @@ class riscv_instr_registry: uvm_object
       import std.algorithm.sorting: sort;
       import std.algorithm.setops: setIntersection, setDifference;
       import std.array: array;
-
-      riscv_instr_name_t[] instr_set = instr_names.dup;
-      instr_set.sort();
+      
+      riscv_instr_name_t[] instr_set = instr_names_sorted;
 
       riscv_instr_name_t[] include_set = instr_set;
       riscv_instr_name_t[] allowed_set = instr_set;
@@ -271,20 +261,22 @@ class riscv_instr_registry: uvm_object
       }
 
       if (allowed_instr.length > 0) {
-	allowed_set = allowed_instr;
+	allowed_set = allowed_instr[];
 	allowed_set.sort();
       }
 
-      riscv_instr_name_t[] inter_set =
-	setDifference(setIntersection(instr_set, include_set, allowed_set),
-		      disallowed_instr.sort()).array();
+      static Vector!(riscv_instr_name_t, "instr_set") inter_set;
+      inter_set.length = 0;
+      inter_set ~= setDifference(setIntersection(instr_set, include_set, allowed_set),
+				 disallowed_instr[].sort());
 
       idx = urandom(0, inter_set.length);
 
       name = inter_set[idx];
     }
     // Shallow copy for all relevant fields, avoid using create() to improve performance
-    auto instr = instr_template[name].dup;
+    auto instr = instr_template[name].dup(tcallocator);
+    // auto instr = instr_template[name].dup();
     instr.m_cfg = cfg;
     return instr;
   }
@@ -312,7 +304,8 @@ class riscv_instr_registry: uvm_object
     ulong idx = urandom( 0, load_store_instr.length);
     riscv_instr_name_t name = load_store_instr[idx];
     // Shallow copy for all relevant fields, avoid using create() to improve performance
-    auto instr = instr_template[name].dup;
+    auto instr = instr_template[name].dup(tcallocator);
+    // auto instr = instr_template[name].dup();
     instr.m_cfg = cfg;
     return instr;
   }
@@ -322,7 +315,8 @@ class riscv_instr_registry: uvm_object
       uvm_fatal("riscv_instr", format("Cannot get instr %0s", name));
     }
     // Shallow copy for all relevant fields, avoid using create() to improve performance
-    auto instr = instr_template[name].dup;
+    auto instr = instr_template[name].dup(tcallocator);
+    // auto instr = instr_template[name].dup();
     instr.m_cfg = cfg;
     return instr;
   }
diff --git a/euvm/riscv/gen/riscv_instr_sequence.d b/euvm/riscv/gen/riscv_instr_sequence.d
index 04c8a025..c7ffdbec 100644
--- a/euvm/riscv/gen/riscv_instr_sequence.d
+++ b/euvm/riscv/gen/riscv_instr_sequence.d
@@ -36,7 +36,7 @@
 module riscv.gen.riscv_instr_sequence;
 
 import riscv.gen.riscv_instr_pkg: riscv_instr_category_t, riscv_instr_name_t,
-  format_string, riscv_reg_t, indent, LABEL_STR_LEN;
+  riscv_reg_t, INDENT, LABEL_STR_LEN;
 import riscv.gen.target: support_pmp, XLEN;
 
 import riscv.gen.riscv_instr_gen_config: riscv_instr_gen_config;
@@ -49,6 +49,7 @@ import std.format: format;
 import std.algorithm.searching: canFind;
 
 import esdl.data.queue: Queue;
+import esdl.data.charbuf: ScratchPad;
 import esdl.rand: randomize, randomize_with;
 import esdl.base.rand: urandom, shuffle;
 
@@ -67,9 +68,11 @@ class riscv_instr_sequence:  uvm_sequence!(uvm_sequence_item,uvm_sequence_item)
   bool                     is_debug_program;     // Indicates whether sequence is debug program
   string                   label_name;           // Label of the sequence (program name)
   riscv_instr_gen_config   cfg;                  // Configuration class handle
-  Queue!string             instr_string_list; // Save the instruction list in string format
+  Queue!string             instr_string_list;    // Save the instruction list in string format
+  
   int                      program_stack_len;    // Stack space allocated for this program
-  riscv_instr_stream[]     directed_instr;     // List of all directed instruction stream
+  riscv_instr_stream[]     directed_instr;       // List of all directed instruction stream
+  ScratchPad!("InstrPad")  scratch_pad;
   riscv_illegal_instr      illegal_instr;        // Illegal instruction generator
   int                      illegal_instr_pct;    // Percentage of illegal instruction
   int                      hint_instr_pct;       // Percentage of HINT instruction
@@ -80,7 +83,7 @@ class riscv_instr_sequence:  uvm_sequence!(uvm_sequence_item,uvm_sequence_item)
     super(name);
     if(!uvm_config_db!(riscv_instr_gen_config).get(null, "*", "instr_cfg", cfg))
       uvm_fatal(get_full_name(), "Cannot get instr_gen_cfg");
-    instr_stream = riscv_prog_instr_stream.type_id.create("instr_stream");
+    instr_stream = riscv_prog_instr_stream.type_id.create(name ~ "/instr_stream");
     instr_stack_enter = riscv_push_stack_instr.type_id.create("instr_stack_enter");
     instr_stack_exit  = riscv_pop_stack_instr.type_id.create("instr_stack_exit");
     illegal_instr = riscv_illegal_instr.type_id.create("illegal_instr");
@@ -127,7 +130,8 @@ class riscv_instr_sequence:  uvm_sequence!(uvm_sequence_item,uvm_sequence_item)
     instr_stack_enter.cfg = cfg;
     instr_stack_enter.push_start_label = label_name ~ "_stack_p";
     instr_stack_enter.gen_push_stack_instr(program_stack_len, allow_branch);
-    instr_stream.prepend_instr_list(instr_stack_enter.instr_list);
+    // this is now done in merge_directed_instr_list
+    // instr_stream.prepend_instr_list(instr_stack_enter.instr_list);
   }
 
   // Recover the saved GPR from the stack
@@ -135,7 +139,8 @@ class riscv_instr_sequence:  uvm_sequence!(uvm_sequence_item,uvm_sequence_item)
   void gen_stack_exit_instr() {
     instr_stack_exit.cfg = cfg;
     instr_stack_exit.gen_pop_stack_instr(program_stack_len, instr_stack_enter.saved_regs);
-    instr_stream.append_instr_list(instr_stack_exit.instr_list);
+    // this is now done in merge_directed_instr_list
+    // instr_stream.append_instr_list(instr_stack_exit.instr_list);
   }
 
   //----------------------------------------------------------------------------------------------
@@ -156,6 +161,7 @@ class riscv_instr_sequence:  uvm_sequence!(uvm_sequence_item,uvm_sequence_item)
   //
   //----------------------------------------------------------------------------------------------
   void post_process_instr() {
+    import std.format: sformat;
     // int i;
     int label_idx;
     int branch_cnt;
@@ -165,7 +171,11 @@ class riscv_instr_sequence:  uvm_sequence!(uvm_sequence_item,uvm_sequence_item)
     // foreach (instr; directed_instr) {
     //   instr_stream.insert_instr_stream(instr.instr_list);
     // }
-    instr_stream.mixin_directed_instr_list(directed_instr);
+    // instr_stream.merge_directed_instr_list(directed_instr);
+    if (is_main_program) instr_stream.merge_directed_instr_list(directed_instr);
+    else
+      instr_stream.merge_directed_instr_list(directed_instr, instr_stack_enter.instr_list.toArray(),
+					     instr_stack_exit.instr_list.toArray());
     // Assign an index for all instructions, these indexes won't change even a new instruction
     // is injected in the post process.
     foreach (i, instr; instr_stream.instr_list) {
@@ -225,7 +235,7 @@ class riscv_instr_sequence:  uvm_sequence!(uvm_sequence_item,uvm_sequence_item)
 		 format("Processing branch instruction[%0d]:%0s # %0d -> %0d",
 			i, instr.convert2asm(),
 			instr.idx, branch_target_label), UVM_HIGH);
-        instr.imm_str = format("%0df", branch_target_label);
+        instr.imm_str = cast(string) sformat!("%0df")(instr.imm_str_buf(), branch_target_label);
         // Below calculation is only needed for generating the instruction stream in binary format
         for (size_t j = i + 1; j < instr_stream.instr_list.length; j++) {
           branch_byte_offset = (instr_stream.instr_list[j-1].is_compressed) ?
@@ -271,7 +281,9 @@ class riscv_instr_sequence:  uvm_sequence!(uvm_sequence_item,uvm_sequence_item)
     jump_instr.idx = idx;
     jump_instr.use_jalr = is_main_program;
     jump_instr.randomize();
-    instr_stream.insert_instr_stream(jump_instr.instr_list);
+    directed_instr ~= jump_instr;
+    // Now done as part of merge_directed_instr_list
+    // instr_stream.insert_instr_stream(jump_instr.instr_list);
     uvm_info(get_full_name(), format("%0s -> %0s...done",
 				     jump_instr.jump.instr_name, target_label), UVM_LOW);
   }
@@ -280,40 +292,60 @@ class riscv_instr_sequence:  uvm_sequence!(uvm_sequence_item,uvm_sequence_item)
   // Label is attached to the instruction if available, otherwise attach proper space to make
   // the code indent consistent.
   void generate_instr_stream(bool no_label = false) {
-    string prefix, str;
+    import std.format:sformat;
+    string prefix;
     int i;
+    enum string FMT = "%-" ~ LABEL_STR_LEN.stringof ~ "s";
     instr_string_list = [];
+    // If PMP is supported, need to align <main> to a 4-byte boundary.
+    // TODO(udi) - this might interfere with multi-hart programs,
+    //             may need to specifically match hart0.
+    if (support_pmp && !uvm_re_match(uvm_glob_to_re("*main*"), label_name)) {
+      instr_string_list ~= ".align 2";
+    }
+
+    uvm_trace("GEN INSTR STRINGS", "START", UVM_NONE);
     for (i = 0; i < instr_stream.instr_list.length; i++) {
+      char[] buf = scratch_pad.getBuf(256);
+      char[32] label_buf;
       if (i == 0) {
         if (no_label) {
-          prefix = format_string(" ", LABEL_STR_LEN);
+          prefix = cast(string) sformat!FMT(buf, " ");
 	}
 	else {
-          prefix = format_string(format("%0s:", label_name), LABEL_STR_LEN);
+          prefix = cast(string)
+	    sformat!FMT(buf, sformat!("%s:")(label_buf, label_name));
 	}
         instr_stream.instr_list[i].has_label = true;
       }
       else {
-        if(instr_stream.instr_list[i].has_label) {
-          prefix = format_string(format("%0s:", instr_stream.instr_list[i].label),
-				 LABEL_STR_LEN);
+        if (instr_stream.instr_list[i].has_label) {
+          prefix = cast(string)
+	    sformat!FMT(buf, sformat!("%0s:")(label_buf,
+					      instr_stream.instr_list[i].label));
         }
 	else {
-          prefix = format_string(" ", LABEL_STR_LEN);
+          prefix = cast(string) sformat!FMT(buf, " ");
         }
       }
-      str = prefix ~ instr_stream.instr_list[i].convert2asm();
-      instr_string_list ~= str;
+      char[] instr_str =
+	instr_stream.instr_list[i].convert2asm(buf[prefix.length..$]);
+      
+      char[] str = buf[0..prefix.length+instr_str.length];
+      scratch_pad.register(str);
+      instr_string_list ~= cast(string) str;
     }
+    uvm_trace("GEN INSTR STRINGS", "END", UVM_NONE);
     // If PMP is supported, need to align <main> to a 4-byte boundary.
     // TODO(udi) - this might interfere with multi-hart programs,
     //             may need to specifically match hart0.
-    if (support_pmp && !uvm_re_match(uvm_glob_to_re("*main*"), label_name)) {
-      instr_string_list.pushFront(".align 2");
-    }
+    // **** done in the beginning of the function now ****
+    // if (support_pmp && !uvm_re_match(uvm_glob_to_re("*main*"), label_name)) {
+    //   instr_string_list.pushFront(".align 2");
+    // }
     insert_illegal_hint_instr();
-    prefix = format_string(format("%0d:", i), LABEL_STR_LEN);
-    if(!is_main_program) {
+    prefix = format!FMT(format("%0d:", i));
+    if (!is_main_program) {
       generate_return_routine(prefix);
     }
   }
@@ -372,7 +404,7 @@ class riscv_instr_sequence:  uvm_sequence!(uvm_sequence_item,uvm_sequence_item)
       for(int i = 0; i != bin_instr_cnt; ++i) {
         // DV_CHECK_RANDOMIZE_WITH_FATAL(,
 	illegal_instr.randomize_with! q{ exception != illegal_instr_type_e.kHintInstr;} ();
-        str = indent ~ format(".4byte 0x%s # %0s",
+        str = INDENT ~ format(".4byte 0x%s # %0s",
 			      illegal_instr.get_bin_str(), illegal_instr.comment);
 	idx = urandom(0, cast(uint) instr_string_list.length+1);
         instr_string_list.insert(idx, str);
@@ -385,7 +417,7 @@ class riscv_instr_sequence:  uvm_sequence!(uvm_sequence_item,uvm_sequence_item)
       for(int i = 0; i != bin_instr_cnt; ++i) {
 	//DV_CHECK_RANDOMIZE_WITH_FATAL(illegal_instr,
 	illegal_instr.randomize_with! q{exception == illegal_instr_type_e.kHintInstr;}();
-        str = indent ~ format(".2byte 0x%s # %0s",
+        str = INDENT ~ format(".2byte 0x%s # %0s",
 			      illegal_instr.get_bin_str(), illegal_instr.comment);
         idx = urandom(0, cast(uint) instr_string_list.length+1);
         instr_string_list.insert(idx, str);
diff --git a/euvm/riscv/gen/riscv_instr_stream.d b/euvm/riscv/gen/riscv_instr_stream.d
index 244b8b6f..873a79ea 100644
--- a/euvm/riscv/gen/riscv_instr_stream.d
+++ b/euvm/riscv/gen/riscv_instr_stream.d
@@ -34,11 +34,13 @@ import riscv.gen.target: XLEN;
 
 import std.format: format;
 import std.algorithm: canFind, sort;
+import core.memory: GC;
 
 import esdl.rand: rand, constraint, randomize, randomize_with;
 import esdl.base.rand: urandom;
 import esdl.data.queue: Queue;
 import esdl.data.bvec: ubvec;
+import esdl.base.core: fork, Fork;
 
 import uvm;
 
@@ -106,112 +108,6 @@ class riscv_instr_stream: uvm_object
     instr_list.insert(idx, instr);
   }
 
-  void insert_instr_map(Queue!riscv_instr new_instr, int idx = -1, bool replace = false) {
-    assert (replace == false);
-  }
-
-  // Insert an instruction to the existing instruction stream at the given index
-  // When index is -1, the instruction is injected at a random location
-  // When replace is 1, the original instruction at the inserted position will be replaced
-  void insert_instr_stream(Queue!riscv_instr new_instr, int idx = -1, bool replace = false) {
-    int current_instr_cnt = cast(int) instr_list.length;
-    int new_instr_cnt = cast(int) new_instr.length;
-    if (current_instr_cnt == 0) {
-      instr_list ~= new_instr;
-      return;
-    }
-    if (idx == -1) {
-      idx = cast(int) urandom(0, current_instr_cnt);
-      for (int i=0; i < 10 ; i++) {
-	if (instr_list[idx].atomic) break;
-	idx = cast(int) urandom(0, current_instr_cnt);
-      }
-      if (instr_list[idx].atomic) {
-	foreach (k, instr; instr_list) {
-	  if (! instr.atomic) {
-	    idx = cast(int) k;
-	    break;
-	  }
-	}
-	if (instr_list[idx].atomic) {
-	  uvm_fatal(get_full_name, format("Cannot inject the instruction"));
-	}
-      }
-    }
-    else if((idx > current_instr_cnt) || (idx < 0)) {
-      uvm_error(get_full_name(), format("Cannot insert instr stream at idx %0d", idx));
-    }
-    //When replace is 1, the original instruction at this index will be removed. The label of the
-    //original instruction will be copied to the head of inserted instruction stream.
-    if (replace) {
-      new_instr[0].label = instr_list[idx].label;
-      new_instr[0].has_label = instr_list[idx].has_label;
-      foreach (i, instr; new_instr) {
-	instr_list[i+idx] = instr;
-      }
-    }
-    else {
-      if (idx == 0) {
-	instr_list.pushFront(new_instr[]);
-      }
-      else {
-        instr_list.insert(idx, new_instr[]);
-      }
-    }
-  }
-
-  void insert_instr_stream(riscv_instr[] new_instr, int idx = -1, bool replace = false) {
-    int current_instr_cnt = cast(int) instr_list.length;
-    int new_instr_cnt = cast(int) new_instr.length;
-    if (current_instr_cnt == 0) {
-      instr_list ~= new_instr;
-      return;
-    }
-    if (idx == -1) {
-      idx = cast(int) urandom(0, current_instr_cnt);
-      for (int i=0; i < 10 ; i++) {
-	if (instr_list[idx].atomic) break;
-	idx = cast(int) urandom(0, current_instr_cnt);
-      }
-      if (instr_list[idx].atomic) {
-	foreach (k, instr; instr_list) {
-	  if (! instr.atomic) {
-	    idx = cast(int) k;
-	    break;
-	  }
-	}
-	if (instr_list[idx].atomic) {
-	  uvm_fatal(get_full_name, format("Cannot inject the instruction"));
-	}
-      }
-    }
-    else if((idx > current_instr_cnt) || (idx < 0)) {
-      uvm_error(get_full_name(), format("Cannot insert instr stream at idx %0d", idx));
-    }
-    //When replace is 1, the original instruction at this index will be removed. The label of the
-    //original instruction will be copied to the head of inserted instruction stream.
-    if (replace) {
-      new_instr[0].label = instr_list[idx].label;
-      new_instr[0].has_label = instr_list[idx].has_label;
-      if (idx == 0) {
-	instr_list.removeFront();
-	instr_list.pushFront(new_instr);
-      }
-      else {
-	instr_list.remove(idx);
-	instr_list.insert(idx, new_instr);
-      }
-     }
-    else {
-      if (idx == 0) {
-	instr_list.pushFront(new_instr);
-      }
-      else {
-        instr_list.insert(idx, new_instr);
-      }
-    }
-  }
-
   void append_instr(riscv_instr instr) {
     instr_list ~= instr;
   }
@@ -233,7 +129,7 @@ class riscv_instr_stream: uvm_object
   // new instruction stream with the first and last instruction from the input instruction stream.
   void mix_instr_stream(riscv_instr[] new_instr, bool contained = false) {
     int current_instr_cnt = cast(int) instr_list.length;
-    int[] insert_instr_position;
+    static int[] insert_instr_position;
     int new_instr_cnt = cast(int) new_instr.length;
     insert_instr_position.length = new_instr_cnt;
     foreach (ref position; insert_instr_position) {
@@ -256,7 +152,7 @@ class riscv_instr_stream: uvm_object
   void mix_instr_stream(Queue!riscv_instr new_instr, bool contained = false) {
     import std.range: enumerate;
     int current_instr_cnt = cast(int) instr_list.length;
-    int[] insert_instr_position;
+    static int[] insert_instr_position;
     int new_instr_cnt = cast(int) new_instr.length;
     insert_instr_position.length = new_instr_cnt;
     foreach (ref position; insert_instr_position) {
@@ -371,17 +267,46 @@ class riscv_rand_instr_stream: riscv_instr_stream
 
   void gen_instr(bool no_branch = false, bool no_load_store = true,
 		 bool is_debug_program = false) {
+    GC.disable();
     setup_allowed_instr(no_branch, no_load_store);
     assert (instr_list.length != 0);
-    foreach (ref instr; instr_list) {
-      randomize_instr(instr, is_debug_program);
-    }
-    // Do not allow branch instruction as the last instruction because there's no
-    // forward branch target
+    uvm_trace("GEN INSTR", "START", UVM_NONE);
+    if (instr_list.length <= cfg.par_instr_threshold ||
+	cfg.par_num_threads == 1) {
+      foreach (ref instr; instr_list) {
+	randomize_instr(instr, is_debug_program);
+      }
+    }
+    else {	// parallelise with cfg.par_num_threads
+      Fork[] forks;
+      size_t instr_count = instr_list.length;
+      size_t instr_grp_length = instr_count / cfg.par_num_threads;
+      for (size_t i=0; i!=cfg.par_num_threads; ++i) {
+	size_t start_idx = i * instr_grp_length;
+	size_t end_idx = (i + 1) * instr_grp_length;
+	// last group
+	if (i == cfg.par_num_threads - 1) end_idx = instr_count;
+	// capture start_idx and end_idx and fork
+	Fork new_fork = (size_t start, size_t end) {
+	  return fork({
+	      for (size_t i=start; i!=end; ++i) {
+		randomize_instr(instr_list[i], is_debug_program);
+	      }
+	    });
+	} (start_idx, end_idx);
+	new_fork.set_thread_affinity(forks.length);
+	forks ~= new_fork;
+      }
+      foreach (f; forks) f.join();
+    }
+    uvm_trace("GEN INSTR", "END", UVM_NONE);
+    // Do not allow branch instruction as the last instruction because
+    // there's no forward branch target
     while (instr_list[$-1].category == riscv_instr_category_t.BRANCH) {
       instr_list.length = instr_list.length - 1;
       if (instr_list.length == 0) break;
     }
+    GC.enable();
   }
 
   void randomize_instr(out riscv_instr instr,
@@ -411,57 +336,93 @@ class riscv_rand_instr_stream: riscv_instr_stream
   void randomize_gpr(riscv_instr instr) {
     assert (cfg !is null);
     instr.m_cfg = cfg;
-    instr.randomize_with! q{
-      if ($0.length > 0) {
-        if (has_rs1) {
+
+    if (avail_regs.length > 0) {
+      instr.randomize_with! q{
+	if (has_rs1) {
 	  rs1 inside [$0];
 	}
-        if (has_rs2) {
-          rs2 inside [$0];
-        }
-        if (has_rd) {
-          rd  inside [$0];
-        }
-      }
-      foreach (rrd; $1) {
+	if (has_rs2) {
+	  rs2 inside [$0];
+	}
 	if (has_rd) {
-	  rd != rrd;
+	  rd  inside [$0];
+	  rd !inside [$1];
+	  rd !inside [$2];
 	}
 	if (instr_format == riscv_instr_format_t.CB_FORMAT) {
-          rs1 != rrd;
+	  rs1 !inside [$1];
+	  rs1 !inside [$2];
 	}
-      }
-      foreach (rreg; $2) {
-        if (has_rd) {
-          rd != rreg;
-        }
-        if (instr_format == riscv_instr_format_t.CB_FORMAT) {
-          rs1 != rreg;
-        }
-      }
-    } (avail_regs, reserved_rd, cfg.reserved_regs);
+      } (avail_regs, reserved_rd, cfg.reserved_regs);
+    }
+
+    else {
+      instr.randomize_with! q{
+	if (has_rd) {
+	  rd !inside [$0];
+	  rd !inside [$1];
+	}
+	if (instr_format == riscv_instr_format_t.CB_FORMAT) {
+	  rs1 !inside [$0];
+	  rs1 !inside [$1];
+	}
+      } (reserved_rd, cfg.reserved_regs);
+    }
+      
+      
+    // instr.randomize_with! q{
+    // 	if ($0.length > 0) {
+    // 	  if (has_rs1) {
+    // 	    rs1 inside [$0];
+    // 	  }
+    // 	  if (has_rs2) {
+    // 	    rs2 inside [$0];
+    // 	  }
+    // 	  if (has_rd) {
+    // 	    rd  inside [$0];
+    // 	  }
+    // 	}
+    // foreach (rrd; $1) {
+    // 	if (has_rd) {
+    // 	  rd != rrd;
+    // 	}
+    // 	if (instr_format == riscv_instr_format_t.CB_FORMAT) {
+    //     rs1 != rrd;
+    // 	}
+    // }
+    // foreach (rreg; $2) {
+    //   if (has_rd) {
+    //     rd != rreg;
+    //   }
+    //   if (instr_format == riscv_instr_format_t.CB_FORMAT) {
+    //     rs1 != rreg;
+    //   }
+    // }
+    // } (avail_regs, reserved_rd, cfg.reserved_regs);
     // TODO: Add constraint for CSR, floating point register
   }
 
 
   riscv_instr get_init_gpr_instr(riscv_reg_t gpr, ubvec!XLEN val) {
+    import std.format: sformat;
     riscv_pseudo_instr li_instr;
     li_instr = riscv_pseudo_instr.type_id.create("li_instr");
     li_instr.randomize_with! q{
       pseudo_instr_name == riscv_pseudo_instr_name_t.LI;
       rd == $0;
     } (gpr);
-    li_instr.imm_str = format("0x%0x", val);
+    li_instr.imm_str = cast(string) sformat!("0x%0x")(li_instr.imm_str_buf(), val);
     return li_instr;
   }
 
   void  add_init_vector_gpr_instr(riscv_vreg_t gpr, ubvec!XLEN val) {
     riscv_vector_instr instr
-      = cast(riscv_vector_instr) cfg.instr_registry.get_instr(riscv_instr_name_t.VMV);
+      = cast(riscv_vector_instr) cfg.instr_registry.get_instr(riscv_instr_name_t.VMV_V_X);
     instr.m_cfg = cfg;
     instr.avoid_reserved_vregs_c.constraint_mode(false);
     instr.randomize_with! q{
-      va_variant == va_variant_t.VX;
+      // va_variant == va_variant_t.VX;
       vd == $0;
       rs1 == $1;
     } (gpr, cfg.gpr[0]);
@@ -477,7 +438,7 @@ class riscv_prog_instr_stream: riscv_rand_instr_stream
 
   riscv_instr_stream[] dir_instr_list;
 
-  // used in mixin_directed_instr_list
+  // used in merge_directed_instr_list
   uint[] dir_n;
 
   this(string name = "riscv_prog_instr_stream") {
@@ -487,7 +448,7 @@ class riscv_prog_instr_stream: riscv_rand_instr_stream
   // Insert an instruction to the existing instruction stream at the given index
   // When index is -1, the instruction is injected at a random location
   // When replace is 1, the original instruction at the inserted position will be replaced
-  override void insert_instr_stream(Queue!riscv_instr new_instr, int idx = -1, bool replace = false) {
+  void insert_instr_stream(Queue!riscv_instr new_instr, int idx = -1, bool replace = false) {
     int current_instr_cnt = cast(int) instr_list.length;
     int new_instr_cnt = cast(int) new_instr.length;
     if (current_instr_cnt == 0) {
@@ -534,7 +495,7 @@ class riscv_prog_instr_stream: riscv_rand_instr_stream
     }
   }
 
-  override void insert_instr_stream(riscv_instr[] new_instr, int idx = -1, bool replace = false) {
+  void insert_instr_stream(riscv_instr[] new_instr, int idx = -1, bool replace = false) {
     int current_instr_cnt = cast(int) instr_list.length;
     int new_instr_cnt = cast(int) new_instr.length;
     if (current_instr_cnt == 0) {
@@ -581,7 +542,9 @@ class riscv_prog_instr_stream: riscv_rand_instr_stream
     }
   }
 
-  void mixin_directed_instr_list(riscv_instr_stream[] dir_list) {
+  void merge_directed_instr_list(riscv_instr_stream[] dir_list,
+				 riscv_instr[] first_instrs = [],
+				 riscv_instr[] last_instrs = []) {
     riscv_instr[]        mixed_list;
 
     uint instr_count = cast(uint) instr_list.length;
@@ -591,6 +554,8 @@ class riscv_prog_instr_stream: riscv_rand_instr_stream
 
     this.dir_instr_list = dir_list;
 
+    mixed_count += first_instrs.length;
+
     foreach (size_t dir_idx, dir_instr; dir_instr_list) {
       mixed_count += dir_instr.instr_list.length;
       uint rnd_idx = urandom(0, instr_count);
@@ -612,10 +577,16 @@ class riscv_prog_instr_stream: riscv_rand_instr_stream
       }
     }
 
+    mixed_count += last_instrs.length;
+
     mixed_list.length = mixed_count;
 
-    uint n = 0;
+    size_t n = first_instrs.length;
+    mixed_list[0..n] = first_instrs;
+    
     foreach (i, instr; instr_list) {
+      // make sure that we are not inserting inside another directed stream
+      assert (! instr.atomic, "Cannot inject the instruction");
       uint next_dir = dir_n[i];
       while (next_dir != 0) {
 	uint next = dir_instr_list[next_dir-1].next_stream;
@@ -626,6 +597,10 @@ class riscv_prog_instr_stream: riscv_rand_instr_stream
       }
       mixed_list[n++] = instr;
     }
+
+    mixed_list[n..$] = last_instrs;
+    n += last_instrs.length;
+    
     assert (mixed_count == n);
 
     instr_list = mixed_list;
diff --git a/euvm/riscv/gen/riscv_load_store_instr_lib.d b/euvm/riscv/gen/riscv_load_store_instr_lib.d
index 4694ce4d..08181c76 100644
--- a/euvm/riscv/gen/riscv_load_store_instr_lib.d
+++ b/euvm/riscv/gen/riscv_load_store_instr_lib.d
@@ -32,7 +32,7 @@ import riscv.gen.riscv_directed_instr_lib: riscv_mem_access_stream;
 import std.format: format;
 import std.algorithm.searching: canFind, minElement, maxElement;
 
-import esdl.rand: rand, constraint, randomize_with;
+import esdl.rand: rand, constraint, randomize_with, constraint_override;
 import esdl.base.rand: urandom;
 import esdl.data.queue: Queue;
 import esdl.data.bvec: ubvec, toubvec;
@@ -145,6 +145,7 @@ class riscv_load_store_base_instr_stream : riscv_mem_access_stream
 
   // Generate each load/store instruction
   void gen_load_store_instr() {
+    import std.format: sformat;
     bool enable_compressed_load_store;
     riscv_instr instr;
     randomize_avail_regs();
@@ -236,7 +237,7 @@ class riscv_load_store_base_instr_stream : riscv_mem_access_stream
       instr.has_imm = false;
       randomize_gpr(instr);
       instr.rs1 = rs1_reg;
-      instr.imm_str = format("%0d", offset[i]);  // $signed(offset[i]));
+      instr.imm_str = cast(string) sformat!("%0d")(instr.imm_str_buf(), offset[i]);  // $signed(offset[i]));
       instr.process_load_store = 0;
       append_instr(instr);
       load_store_instr ~= instr;
@@ -479,6 +480,7 @@ class riscv_mem_region_stress_test: riscv_multi_page_load_store_instr_stream
     super(name);
   }
 
+  @constraint_override
   constraint! q{
     num_of_instr_stream inside [2..5];
     foreach (i, id; data_page_id) {
@@ -526,6 +528,8 @@ class riscv_load_store_rand_addr_instr_stream : riscv_load_store_base_instr_stre
   }
 
   override void add_rs1_init_la_instr(riscv_reg_t gpr, int id, int base = 0) {
+    import std.format: sformat;
+
     Queue!riscv_instr instr;
     riscv_pseudo_instr li_instr;
     riscv_instr store_instr;
@@ -542,7 +546,7 @@ class riscv_load_store_rand_addr_instr_stream : riscv_load_store_base_instr_stre
       rd inside [$0];
       rd != $1;
     } (cfg.gpr, gpr);
-    li_instr.imm_str = format("0x%0x", addr_offset);
+    li_instr.imm_str = cast(string) sformat!("0x%0x")(li_instr.imm_str_buf(), addr_offset);
     // Add offset to the base address
     add_instr = cfg.instr_registry.get_instr(riscv_instr_name_t.ADD);
     //`DV_CHECK_RANDOMIZE_WITH_FATAL(add_instr,
@@ -564,10 +568,11 @@ class riscv_load_store_rand_addr_instr_stream : riscv_load_store_base_instr_stre
     // Initialize the location which used by load instruction later
     foreach (i, lsinstr; load_store_instr) {
       if (lsinstr.category == riscv_instr_category_t.LOAD) {
+	import esdl.data.bvec: to;
         riscv_instr store;
         store = riscv_instr.type_id.create("store");
         store.copy(store_instr);
-        store.rs2 = cast(riscv_reg_t) ((cast(int) i) % 32);
+        store.rs2 = ((cast(int) i) % 32).to!riscv_reg_t;
         store.imm_str = lsinstr.imm_str;
         // TODO: C_FLDSP is in both rv32 and rv64 ISA
 	switch (lsinstr.instr_name) {
@@ -670,11 +675,11 @@ class riscv_vector_load_store_instr_stream : riscv_mem_access_stream
     add_mixed_instr(num_mixed_instr);
     add_rs1_init_la_instr(rs1_reg, data_page_id, base);
     if (address_mode == address_mode_e.STRIDED) {
-      this.append_instr(get_init_gpr_instr(rs2_reg, toubvec!64(stride_byte_offset)));
+      this.append_instr(get_init_gpr_instr(rs2_reg, toubvec!XLEN(stride_byte_offset)));
     }
     else if (address_mode == address_mode_e.INDEXED) {
       // TODO: Support different index address for each element
-      add_init_vector_gpr_instr(vs2_reg, toubvec!64(index_addr));
+      add_init_vector_gpr_instr(vs2_reg, toubvec!XLEN(index_addr));
     }
     super.post_randomize();
   }
@@ -734,30 +739,32 @@ class riscv_vector_load_store_instr_stream : riscv_mem_access_stream
   void build_allowed_instr() {
     switch (address_mode) {
     case address_mode_e.UNIT_STRIDED:
-      allowed_instr = [riscv_instr_name_t.VLE_V, riscv_instr_name_t.VSE_V] ~ allowed_instr;
-      if (cfg.vector_cfg.enable_fault_only_first_load) {
-	allowed_instr = [riscv_instr_name_t.VLEFF_V] ~ allowed_instr;
-      }
-      if (cfg.vector_cfg.enable_zvlsseg) {
-	allowed_instr = [riscv_instr_name_t.VLSEGE_V, riscv_instr_name_t.VSSEGE_V] ~ allowed_instr;
-	if (cfg.vector_cfg.enable_fault_only_first_load) {
-	  allowed_instr = [riscv_instr_name_t.VLSEGEFF_V] ~ allowed_instr;
-	}
-      }
+      // allowed_instr = [// riscv_instr_name_t.VLE_V, // mismatch with riscv-opcodes
+      // 		       // riscv_instr_name_t.VSE_V  // mismatch with riscv-opcodes
+      // 		       ] ~ allowed_instr;
+      // if (cfg.vector_cfg.enable_fault_only_first_load) {
+      // 	allowed_instr = [riscv_instr_name_t.VLEFF_V] ~ allowed_instr;
+      // }
+      // if (cfg.vector_cfg.enable_zvlsseg) {
+      // 	allowed_instr = [riscv_instr_name_t.VLSEGE_V, riscv_instr_name_t.VSSEGE_V] ~ allowed_instr;
+      // 	if (cfg.vector_cfg.enable_fault_only_first_load) {
+      // 	  allowed_instr = [riscv_instr_name_t.VLSEGEFF_V] ~ allowed_instr;
+      // 	}
+      // }
       break;
     case address_mode_e.STRIDED:
-      allowed_instr = [riscv_instr_name_t.VLSE_V, riscv_instr_name_t.VSSE_V] ~ allowed_instr;
-      if (cfg.vector_cfg.enable_zvlsseg) {
-	allowed_instr = [riscv_instr_name_t.VLSSEGE_V, riscv_instr_name_t.VSSSEGE_V] ~ allowed_instr;
-      }
-      break;
-    case address_mode_e.INDEXED:
-      allowed_instr = [riscv_instr_name_t.VLXEI_V, riscv_instr_name_t.VSXEI_V,
-		       riscv_instr_name_t.VSUXEI_V] ~ allowed_instr;
-      if (cfg.vector_cfg.enable_zvlsseg) {
-	allowed_instr = [riscv_instr_name_t.VLXSEGEI_V, riscv_instr_name_t.VSXSEGEI_V,
-			 riscv_instr_name_t.VSUXSEGEI_V] ~ allowed_instr;
-      }
+    //   allowed_instr = [riscv_instr_name_t.VLSE_V, riscv_instr_name_t.VSSE_V] ~ allowed_instr;
+    //   if (cfg.vector_cfg.enable_zvlsseg) {
+    // 	allowed_instr = [riscv_instr_name_t.VLSSEGE_V, riscv_instr_name_t.VSSSEGE_V] ~ allowed_instr;
+    //   }
+    //   break;
+    // case address_mode_e.INDEXED:
+    //   allowed_instr = [riscv_instr_name_t.VLXEI_V, riscv_instr_name_t.VSXEI_V,
+    // 		       riscv_instr_name_t.VSUXEI_V] ~ allowed_instr;
+    //   if (cfg.vector_cfg.enable_zvlsseg) {
+    // 	allowed_instr = [riscv_instr_name_t.VLXSEGEI_V, riscv_instr_name_t.VSXSEGEI_V,
+    // 			 riscv_instr_name_t.VSUXSEGEI_V] ~ allowed_instr;
+    //   }
       break;
     default: break;
     }
diff --git a/euvm/riscv/gen/riscv_opcodes_pkg.d b/euvm/riscv/gen/riscv_opcodes_pkg.d
new file mode 100644
index 00000000..76b2f24f
--- /dev/null
+++ b/euvm/riscv/gen/riscv_opcodes_pkg.d
@@ -0,0 +1,16477 @@
+module riscv.gen.riscv_opcodes_pkg;
+
+enum riscv_instr_name_t: short {
+    ADD,
+    ADD16,
+    ADD32,
+    ADD8,
+    ADD_UW,
+    ADDI,
+    ADDIW,
+    ADDW,
+    AMOADD_D,
+    AMOADD_W,
+    AMOAND_D,
+    AMOAND_W,
+    AMOMAX_D,
+    AMOMAX_W,
+    AMOMAXU_D,
+    AMOMAXU_W,
+    AMOMIN_D,
+    AMOMIN_W,
+    AMOMINU_D,
+    AMOMINU_W,
+    AMOOR_D,
+    AMOOR_W,
+    AMOSWAP_D,
+    AMOSWAP_W,
+    AMOXOR_D,
+    AMOXOR_W,
+    AND,
+    ANDI,
+    ANDN,
+    AUIPC,
+    AVE,
+    BCLR,
+    BCLRI,
+    BCOMPRESS,
+    BCOMPRESSW,
+    BDECOMPRESS,
+    BDECOMPRESSW,
+    BEQ,
+    BEXT,
+    BEXTI,
+    BFP,
+    BFPW,
+    BGE,
+    BGEU,
+    BINV,
+    BINVI,
+    BLT,
+    BLTU,
+    BMATFLIP,
+    BMATOR,
+    BMATXOR,
+    BNE,
+    BSET,
+    BSETI,
+    C_ADD,
+    C_ADDI,
+    C_ADDI16SP,
+    C_ADDI4SPN,
+    C_ADDIW,
+    C_ADDW,
+    C_AND,
+    C_ANDI,
+    C_BEQZ,
+    C_BNEZ,
+    C_EBREAK,
+    C_FLD,
+    C_FLDSP,
+    C_FLW,
+    C_FLWSP,
+    C_FSD,
+    C_FSDSP,
+    C_FSW,
+    C_FSWSP,
+    C_J,
+    C_JAL,
+    C_JALR,
+    C_JR,
+    C_LD,
+    C_LDSP,
+    C_LI,
+    C_LQ,
+    C_LQSP,
+    C_LUI,
+    C_LW,
+    C_LWSP,
+    C_MV,
+    C_NOP,
+    C_OR,
+    C_SD,
+    C_SDSP,
+    C_SLLI,
+    C_SLLI64,
+    C_SQ,
+    C_SQSP,
+    C_SRAI,
+    C_SRAI64,
+    C_SRLI,
+    C_SRLI64,
+    C_SUB,
+    C_SUBW,
+    C_SW,
+    C_SWSP,
+    C_XOR,
+    CLMUL,
+    CLMULH,
+    CLMULR,
+    CLROV,
+    CLRS16,
+    CLRS32,
+    CLRS8,
+    CLZ,
+    CLZ16,
+    CLZ32,
+    CLZ8,
+    CLZW,
+    CMIX,
+    CMOV,
+    CMPEQ16,
+    CMPEQ8,
+    CPOP,
+    CPOPW,
+    CRAS16,
+    CRAS32,
+    CRC32_B,
+    CRC32_D,
+    CRC32_H,
+    CRC32_W,
+    CRC32C_B,
+    CRC32C_D,
+    CRC32C_H,
+    CRC32C_W,
+    CRSA16,
+    CRSA32,
+    CSRRC,
+    CSRRCI,
+    CSRRS,
+    CSRRSI,
+    CSRRW,
+    CSRRWI,
+    CTZ,
+    CTZW,
+    DIV,
+    DIVU,
+    DIVUW,
+    DIVW,
+    DRET,
+    EBREAK,
+    ECALL,
+    FADD_D,
+    FADD_S,
+    FCLASS_D,
+    FCLASS_S,
+    FCVT_D_L,
+    FCVT_D_LU,
+    FCVT_D_S,
+    FCVT_D_W,
+    FCVT_D_WU,
+    FCVT_L_D,
+    FCVT_L_S,
+    FCVT_LU_D,
+    FCVT_LU_S,
+    FCVT_S_D,
+    FCVT_S_L,
+    FCVT_S_LU,
+    FCVT_S_W,
+    FCVT_S_WU,
+    FCVT_W_D,
+    FCVT_W_S,
+    FCVT_WU_D,
+    FCVT_WU_S,
+    FDIV_D,
+    FDIV_S,
+    FENCE,
+    FENCE_I,
+    FENCE_TSO,
+    FEQ_D,
+    FEQ_S,
+    FLD,
+    FLE_D,
+    FLE_S,
+    FLT_D,
+    FLT_S,
+    FLW,
+    FMADD_D,
+    FMADD_S,
+    FMAX_D,
+    FMAX_S,
+    FMIN_D,
+    FMIN_S,
+    FMSUB_D,
+    FMSUB_S,
+    FMUL_D,
+    FMUL_S,
+    FMV_D_X,
+    FMV_S_X,
+    FMV_W_X,
+    FMV_X_D,
+    FMV_X_S,
+    FMV_X_W,
+    FNMADD_D,
+    FNMADD_S,
+    FNMSUB_D,
+    FNMSUB_S,
+    FRCSR,
+    FRFLAGS,
+    FRRM,
+    FSCSR,
+    FSD,
+    FSFLAGS,
+    FSFLAGSI,
+    FSGNJ_D,
+    FSGNJ_S,
+    FSGNJN_D,
+    FSGNJN_S,
+    FSGNJX_D,
+    FSGNJX_S,
+    FSL,
+    FSLW,
+    FSQRT_D,
+    FSQRT_S,
+    FSR,
+    FSRI,
+    FSRIW,
+    FSRM,
+    FSRMI,
+    FSRW,
+    FSUB_D,
+    FSUB_S,
+    FSW,
+    GORC,
+    GORCI,
+    GORCIW,
+    GORCW,
+    GREV,
+    GREVI,
+    GREVIW,
+    GREVW,
+    INSB,
+    JAL,
+    JALR,
+    KABS16,
+    KABS32,
+    KABS8,
+    KABSW,
+    KADD16,
+    KADD32,
+    KADD8,
+    KADDH,
+    KADDW,
+    KCRAS16,
+    KCRAS32,
+    KCRSA16,
+    KCRSA32,
+    KDMABB,
+    KDMABB16,
+    KDMABT,
+    KDMABT16,
+    KDMATT,
+    KDMATT16,
+    KDMBB,
+    KDMBB16,
+    KDMBT,
+    KDMBT16,
+    KDMTT,
+    KDMTT16,
+    KHM16,
+    KHM8,
+    KHMBB,
+    KHMBB16,
+    KHMBT,
+    KHMBT16,
+    KHMTT,
+    KHMTT16,
+    KHMX16,
+    KHMX8,
+    KMABB,
+    KMABB32,
+    KMABT,
+    KMABT32,
+    KMADA,
+    KMADRS,
+    KMADRS32,
+    KMADS,
+    KMADS32,
+    KMATT,
+    KMATT32,
+    KMAXDA,
+    KMAXDA32,
+    KMAXDS,
+    KMAXDS32,
+    KMDA,
+    KMDA32,
+    KMMAC,
+    KMMAC_U,
+    KMMAWB,
+    KMMAWB2,
+    KMMAWB2_U,
+    KMMAWB_U,
+    KMMAWT,
+    KMMAWT2,
+    KMMAWT2_U,
+    KMMAWT_U,
+    KMMSB,
+    KMMSB_U,
+    KMMWB2,
+    KMMWB2_U,
+    KMMWT2,
+    KMMWT2_U,
+    KMSDA,
+    KMSDA32,
+    KMSXDA,
+    KMSXDA32,
+    KMXDA,
+    KMXDA32,
+    KSLL16,
+    KSLL32,
+    KSLL8,
+    KSLLI16,
+    KSLLI32,
+    KSLLI8,
+    KSLLIW,
+    KSLLW,
+    KSLRA16,
+    KSLRA16_U,
+    KSLRA32,
+    KSLRA32_U,
+    KSLRA8,
+    KSLRA8_U,
+    KSLRAW,
+    KSLRAW_U,
+    KSTAS16,
+    KSTAS32,
+    KSTSA16,
+    KSTSA32,
+    KSUB16,
+    KSUB32,
+    KSUB8,
+    KSUBH,
+    KSUBW,
+    KWMMUL,
+    KWMMUL_U,
+    LB,
+    LBU,
+    LD,
+    LH,
+    LHU,
+    LR_D,
+    LR_W,
+    LUI,
+    LW,
+    LWU,
+    MADDR32,
+    MAX,
+    MAXU,
+    MIN,
+    MINU,
+    MRET,
+    MSUBR32,
+    MUL,
+    MULH,
+    MULHSU,
+    MULHU,
+    MULW,
+    NOP,
+    OR,
+    ORC_B,
+    ORI,
+    ORN,
+    PACK,
+    PACKH,
+    PACKU,
+    PACKUW,
+    PACKW,
+    PAUSE,
+    PBSAD,
+    PBSADA,
+    PKBB16,
+    PKBT16,
+    PKBT32,
+    PKTB16,
+    PKTB32,
+    PKTT16,
+    RADD16,
+    RADD32,
+    RADD8,
+    RADDW,
+    RCRAS16,
+    RCRAS32,
+    RCRSA16,
+    RCRSA32,
+    RDCYCLE,
+    RDCYCLEH,
+    RDINSTRET,
+    RDINSTRETH,
+    RDOV,
+    RDTIME,
+    RDTIMEH,
+    REM,
+    REMU,
+    REMUW,
+    REMW,
+    REV8,
+    ROL,
+    ROLW,
+    ROR,
+    RORI,
+    RORIW,
+    RORW,
+    RSTAS16,
+    RSTAS32,
+    RSTSA16,
+    RSTSA32,
+    RSUB16,
+    RSUB32,
+    RSUB8,
+    RSUBW,
+    SB,
+    SBREAK,
+    SC_D,
+    SC_W,
+    SCALL,
+    SCLIP16,
+    SCLIP32,
+    SCLIP8,
+    SCMPLE16,
+    SCMPLE8,
+    SCMPLT16,
+    SCMPLT8,
+    SD,
+    SEXT_B,
+    SEXT_H,
+    SFENCE_VMA,
+    SH,
+    SH1ADD,
+    SH1ADD_UW,
+    SH2ADD,
+    SH2ADD_UW,
+    SH3ADD,
+    SH3ADD_UW,
+    SHFL,
+    SHFLI,
+    SHFLW,
+    SLL,
+    SLL16,
+    SLL32,
+    SLL8,
+    SLLI,
+    SLLI16,
+    SLLI32,
+    SLLI8,
+    SLLI_UW,
+    SLLIW,
+    SLLW,
+    SLO,
+    SLOI,
+    SLOIW,
+    SLOW,
+    SLT,
+    SLTI,
+    SLTIU,
+    SLTU,
+    SMAQA,
+    SMAQA_SU,
+    SMAX16,
+    SMAX32,
+    SMAX8,
+    SMBB16,
+    SMBT16,
+    SMBT32,
+    SMDRS,
+    SMDRS32,
+    SMDS,
+    SMDS32,
+    SMIN16,
+    SMIN32,
+    SMIN8,
+    SMMUL,
+    SMMUL_U,
+    SMMWB,
+    SMMWB_U,
+    SMMWT,
+    SMMWT_U,
+    SMTT16,
+    SMTT32,
+    SMXDS,
+    SMXDS32,
+    SRA,
+    SRA16,
+    SRA16_U,
+    SRA32,
+    SRA32_U,
+    SRA8,
+    SRA8_U,
+    SRA_U,
+    SRAI,
+    SRAI16,
+    SRAI16_U,
+    SRAI32,
+    SRAI32_U,
+    SRAI8,
+    SRAI8_U,
+    SRAI_U,
+    SRAIW,
+    SRAIW_U,
+    SRAW,
+    SRET,
+    SRL,
+    SRL16,
+    SRL16_U,
+    SRL32,
+    SRL32_U,
+    SRL8,
+    SRL8_U,
+    SRLI,
+    SRLI16,
+    SRLI16_U,
+    SRLI32,
+    SRLI32_U,
+    SRLI8,
+    SRLI8_U,
+    SRLIW,
+    SRLW,
+    SRO,
+    SROI,
+    SROIW,
+    SROW,
+    STAS16,
+    STAS32,
+    STSA16,
+    STSA32,
+    SUB,
+    SUB16,
+    SUB32,
+    SUB8,
+    SUBW,
+    SUNPKD810,
+    SUNPKD820,
+    SUNPKD830,
+    SUNPKD831,
+    SUNPKD832,
+    SW,
+    UCLIP16,
+    UCLIP32,
+    UCLIP8,
+    UCMPLE16,
+    UCMPLE8,
+    UCMPLT16,
+    UCMPLT8,
+    UKADD16,
+    UKADD32,
+    UKADD8,
+    UKADDH,
+    UKADDW,
+    UKCRAS16,
+    UKCRAS32,
+    UKCRSA16,
+    UKCRSA32,
+    UKSTAS16,
+    UKSTAS32,
+    UKSTSA16,
+    UKSTSA32,
+    UKSUB16,
+    UKSUB32,
+    UKSUB8,
+    UKSUBH,
+    UKSUBW,
+    UMAQA,
+    UMAX16,
+    UMAX32,
+    UMAX8,
+    UMIN16,
+    UMIN32,
+    UMIN8,
+    UNSHFL,
+    UNSHFLI,
+    UNSHFLW,
+    UNZIP16,
+    UNZIP8,
+    URADD16,
+    URADD32,
+    URADD8,
+    URADDW,
+    URCRAS16,
+    URCRAS32,
+    URCRSA16,
+    URCRSA32,
+    URSTAS16,
+    URSTAS32,
+    URSTSA16,
+    URSTSA32,
+    URSUB16,
+    URSUB32,
+    URSUB8,
+    URSUBW,
+    VAADD_VV,
+    VAADD_VX,
+    VAADDU_VV,
+    VAADDU_VX,
+    VADC_VIM,
+    VADC_VVM,
+    VADC_VXM,
+    VADD_VI,
+    VADD_VV,
+    VADD_VX,
+    VAESDF_VS,
+    VAESDF_VV,
+    VAESDM_VS,
+    VAESDM_VV,
+    VAESEF_VS,
+    VAESEF_VV,
+    VAESEM_VS,
+    VAESEM_VV,
+    VAESKF1_VI,
+    VAESKF2_VI,
+    VAESZ_VS,
+    VAND_VI,
+    VAND_VV,
+    VAND_VX,
+    VANDN_VV,
+    VANDN_VX,
+    VASUB_VV,
+    VASUB_VX,
+    VASUBU_VV,
+    VASUBU_VX,
+    VBREV8_V,
+    VBREV_V,
+    VCLMUL_VV,
+    VCLMUL_VX,
+    VCLMULH_VV,
+    VCLMULH_VX,
+    VCLZ_V,
+    VCOMPRESS_VM,
+    VCPOP_M,
+    VCPOP_V,
+    VCTZ_V,
+    VDIV_VV,
+    VDIV_VX,
+    VDIVU_VV,
+    VDIVU_VX,
+    VFADD_VF,
+    VFADD_VV,
+    VFCLASS_V,
+    VFCVT_F_X_V,
+    VFCVT_F_XU_V,
+    VFCVT_RTZ_X_F_V,
+    VFCVT_RTZ_XU_F_V,
+    VFCVT_X_F_V,
+    VFCVT_XU_F_V,
+    VFDIV_VF,
+    VFDIV_VV,
+    VFIRST_M,
+    VFMACC_VF,
+    VFMACC_VV,
+    VFMADD_VF,
+    VFMADD_VV,
+    VFMAX_VF,
+    VFMAX_VV,
+    VFMERGE_VFM,
+    VFMIN_VF,
+    VFMIN_VV,
+    VFMSAC_VF,
+    VFMSAC_VV,
+    VFMSUB_VF,
+    VFMSUB_VV,
+    VFMUL_VF,
+    VFMUL_VV,
+    VFMV_F_S,
+    VFMV_S_F,
+    VFMV_V_F,
+    VFNCVT_F_F_W,
+    VFNCVT_F_X_W,
+    VFNCVT_F_XU_W,
+    VFNCVT_ROD_F_F_W,
+    VFNCVT_RTZ_X_F_W,
+    VFNCVT_RTZ_XU_F_W,
+    VFNCVT_X_F_W,
+    VFNCVT_XU_F_W,
+    VFNMACC_VF,
+    VFNMACC_VV,
+    VFNMADD_VF,
+    VFNMADD_VV,
+    VFNMSAC_VF,
+    VFNMSAC_VV,
+    VFNMSUB_VF,
+    VFNMSUB_VV,
+    VFRDIV_VF,
+    VFREC7_V,
+    VFREDMAX_VS,
+    VFREDMIN_VS,
+    VFREDOSUM_VS,
+    VFREDSUM_VS,
+    VFREDUSUM_VS,
+    VFRSQRT7_V,
+    VFRSUB_VF,
+    VFSGNJ_VF,
+    VFSGNJ_VV,
+    VFSGNJN_VF,
+    VFSGNJN_VV,
+    VFSGNJX_VF,
+    VFSGNJX_VV,
+    VFSLIDE1DOWN_VF,
+    VFSLIDE1UP_VF,
+    VFSQRT_V,
+    VFSUB_VF,
+    VFSUB_VV,
+    VFWADD_VF,
+    VFWADD_VV,
+    VFWADD_WF,
+    VFWADD_WV,
+    VFWCVT_F_F_V,
+    VFWCVT_F_X_V,
+    VFWCVT_F_XU_V,
+    VFWCVT_RTZ_X_F_V,
+    VFWCVT_RTZ_XU_F_V,
+    VFWCVT_X_F_V,
+    VFWCVT_XU_F_V,
+    VFWMACC_VF,
+    VFWMACC_VV,
+    VFWMSAC_VF,
+    VFWMSAC_VV,
+    VFWMUL_VF,
+    VFWMUL_VV,
+    VFWNMACC_VF,
+    VFWNMACC_VV,
+    VFWNMSAC_VF,
+    VFWNMSAC_VV,
+    VFWREDOSUM_VS,
+    VFWREDSUM_VS,
+    VFWREDUSUM_VS,
+    VFWSUB_VF,
+    VFWSUB_VV,
+    VFWSUB_WF,
+    VFWSUB_WV,
+    VGHSH_VV,
+    VGMUL_VV,
+    VID_V,
+    VIOTA_M,
+    VL1R_V,
+    VL1RE16_V,
+    VL1RE32_V,
+    VL1RE64_V,
+    VL1RE8_V,
+    VL2R_V,
+    VL2RE16_V,
+    VL2RE32_V,
+    VL2RE64_V,
+    VL2RE8_V,
+    VL4R_V,
+    VL4RE16_V,
+    VL4RE32_V,
+    VL4RE64_V,
+    VL4RE8_V,
+    VL8R_V,
+    VL8RE16_V,
+    VL8RE32_V,
+    VL8RE64_V,
+    VL8RE8_V,
+    VLE1024_V,
+    VLE1024FF_V,
+    VLE128_V,
+    VLE128FF_V,
+    VLE16_V,
+    VLE16FF_V,
+    VLE1_V,
+    VLE256_V,
+    VLE256FF_V,
+    VLE32_V,
+    VLE32FF_V,
+    VLE512_V,
+    VLE512FF_V,
+    VLE64_V,
+    VLE64FF_V,
+    VLE8_V,
+    VLE8FF_V,
+    VLM_V,
+    VLOXEI1024_V,
+    VLOXEI128_V,
+    VLOXEI16_V,
+    VLOXEI256_V,
+    VLOXEI32_V,
+    VLOXEI512_V,
+    VLOXEI64_V,
+    VLOXEI8_V,
+    VLSE1024_V,
+    VLSE128_V,
+    VLSE16_V,
+    VLSE256_V,
+    VLSE32_V,
+    VLSE512_V,
+    VLSE64_V,
+    VLSE8_V,
+    VLUXEI1024_V,
+    VLUXEI128_V,
+    VLUXEI16_V,
+    VLUXEI256_V,
+    VLUXEI32_V,
+    VLUXEI512_V,
+    VLUXEI64_V,
+    VLUXEI8_V,
+    VMACC_VV,
+    VMACC_VX,
+    VMADC_VI,
+    VMADC_VIM,
+    VMADC_VV,
+    VMADC_VVM,
+    VMADC_VX,
+    VMADC_VXM,
+    VMADD_VV,
+    VMADD_VX,
+    VMAND_MM,
+    VMANDN_MM,
+    VMANDNOT_MM,
+    VMAX_VV,
+    VMAX_VX,
+    VMAXU_VV,
+    VMAXU_VX,
+    VMERGE_VIM,
+    VMERGE_VVM,
+    VMERGE_VXM,
+    VMFEQ_VF,
+    VMFEQ_VV,
+    VMFGE_VF,
+    VMFGT_VF,
+    VMFLE_VF,
+    VMFLE_VV,
+    VMFLT_VF,
+    VMFLT_VV,
+    VMFNE_VF,
+    VMFNE_VV,
+    VMIN_VV,
+    VMIN_VX,
+    VMINU_VV,
+    VMINU_VX,
+    VMNAND_MM,
+    VMNOR_MM,
+    VMOR_MM,
+    VMORN_MM,
+    VMORNOT_MM,
+    VMSBC_VV,
+    VMSBC_VVM,
+    VMSBC_VX,
+    VMSBC_VXM,
+    VMSBF_M,
+    VMSEQ_VI,
+    VMSEQ_VV,
+    VMSEQ_VX,
+    VMSGT_VI,
+    VMSGT_VX,
+    VMSGTU_VI,
+    VMSGTU_VX,
+    VMSIF_M,
+    VMSLE_VI,
+    VMSLE_VV,
+    VMSLE_VX,
+    VMSLEU_VI,
+    VMSLEU_VV,
+    VMSLEU_VX,
+    VMSLT_VV,
+    VMSLT_VX,
+    VMSLTU_VV,
+    VMSLTU_VX,
+    VMSNE_VI,
+    VMSNE_VV,
+    VMSNE_VX,
+    VMSOF_M,
+    VMUL_VV,
+    VMUL_VX,
+    VMULH_VV,
+    VMULH_VX,
+    VMULHSU_VV,
+    VMULHSU_VX,
+    VMULHU_VV,
+    VMULHU_VX,
+    VMV1R_V,
+    VMV2R_V,
+    VMV4R_V,
+    VMV8R_V,
+    VMV_S_X,
+    VMV_V_I,
+    VMV_V_V,
+    VMV_V_X,
+    VMV_X_S,
+    VMXNOR_MM,
+    VMXOR_MM,
+    VNCLIP_WI,
+    VNCLIP_WV,
+    VNCLIP_WX,
+    VNCLIPU_WI,
+    VNCLIPU_WV,
+    VNCLIPU_WX,
+    VNMSAC_VV,
+    VNMSAC_VX,
+    VNMSUB_VV,
+    VNMSUB_VX,
+    VNSRA_WI,
+    VNSRA_WV,
+    VNSRA_WX,
+    VNSRL_WI,
+    VNSRL_WV,
+    VNSRL_WX,
+    VOR_VI,
+    VOR_VV,
+    VOR_VX,
+    VPOPC_M,
+    VREDAND_VS,
+    VREDMAX_VS,
+    VREDMAXU_VS,
+    VREDMIN_VS,
+    VREDMINU_VS,
+    VREDOR_VS,
+    VREDSUM_VS,
+    VREDXOR_VS,
+    VREM_VV,
+    VREM_VX,
+    VREMU_VV,
+    VREMU_VX,
+    VREV8_V,
+    VRGATHER_VI,
+    VRGATHER_VV,
+    VRGATHER_VX,
+    VRGATHEREI16_VV,
+    VROL_VV,
+    VROL_VX,
+    VROR_VI,
+    VROR_VV,
+    VROR_VX,
+    VRSUB_VI,
+    VRSUB_VX,
+    VS1R_V,
+    VS2R_V,
+    VS4R_V,
+    VS8R_V,
+    VSADD_VI,
+    VSADD_VV,
+    VSADD_VX,
+    VSADDU_VI,
+    VSADDU_VV,
+    VSADDU_VX,
+    VSBC_VVM,
+    VSBC_VXM,
+    VSE1024_V,
+    VSE128_V,
+    VSE16_V,
+    VSE1_V,
+    VSE256_V,
+    VSE32_V,
+    VSE512_V,
+    VSE64_V,
+    VSE8_V,
+    VSETIVLI,
+    VSETVL,
+    VSETVLI,
+    VSEXT_VF2,
+    VSEXT_VF4,
+    VSEXT_VF8,
+    VSHA2CH_VV,
+    VSHA2CL_VV,
+    VSHA2MS_VV,
+    VSLIDE1DOWN_VX,
+    VSLIDE1UP_VX,
+    VSLIDEDOWN_VI,
+    VSLIDEDOWN_VX,
+    VSLIDEUP_VI,
+    VSLIDEUP_VX,
+    VSLL_VI,
+    VSLL_VV,
+    VSLL_VX,
+    VSM3C_VI,
+    VSM3ME_VV,
+    VSM4K_VI,
+    VSM4R_VS,
+    VSM4R_VV,
+    VSM_V,
+    VSMUL_VV,
+    VSMUL_VX,
+    VSOXEI1024_V,
+    VSOXEI128_V,
+    VSOXEI16_V,
+    VSOXEI256_V,
+    VSOXEI32_V,
+    VSOXEI512_V,
+    VSOXEI64_V,
+    VSOXEI8_V,
+    VSRA_VI,
+    VSRA_VV,
+    VSRA_VX,
+    VSRL_VI,
+    VSRL_VV,
+    VSRL_VX,
+    VSSE1024_V,
+    VSSE128_V,
+    VSSE16_V,
+    VSSE256_V,
+    VSSE32_V,
+    VSSE512_V,
+    VSSE64_V,
+    VSSE8_V,
+    VSSRA_VI,
+    VSSRA_VV,
+    VSSRA_VX,
+    VSSRL_VI,
+    VSSRL_VV,
+    VSSRL_VX,
+    VSSUB_VV,
+    VSSUB_VX,
+    VSSUBU_VV,
+    VSSUBU_VX,
+    VSUB_VV,
+    VSUB_VX,
+    VSUXEI1024_V,
+    VSUXEI128_V,
+    VSUXEI16_V,
+    VSUXEI256_V,
+    VSUXEI32_V,
+    VSUXEI512_V,
+    VSUXEI64_V,
+    VSUXEI8_V,
+    VWADD_VV,
+    VWADD_VX,
+    VWADD_WV,
+    VWADD_WX,
+    VWADDU_VV,
+    VWADDU_VX,
+    VWADDU_WV,
+    VWADDU_WX,
+    VWMACC_VV,
+    VWMACC_VX,
+    VWMACCSU_VV,
+    VWMACCSU_VX,
+    VWMACCU_VV,
+    VWMACCU_VX,
+    VWMACCUS_VX,
+    VWMUL_VV,
+    VWMUL_VX,
+    VWMULSU_VV,
+    VWMULSU_VX,
+    VWMULU_VV,
+    VWMULU_VX,
+    VWREDSUM_VS,
+    VWREDSUMU_VS,
+    VWSLL_VI,
+    VWSLL_VV,
+    VWSLL_VX,
+    VWSUB_VV,
+    VWSUB_VX,
+    VWSUB_WV,
+    VWSUB_WX,
+    VWSUBU_VV,
+    VWSUBU_VX,
+    VWSUBU_WV,
+    VWSUBU_WX,
+    VXOR_VI,
+    VXOR_VV,
+    VXOR_VX,
+    VZEXT_VF2,
+    VZEXT_VF4,
+    VZEXT_VF8,
+    WFI,
+    XNOR,
+    XOR,
+    XORI,
+    XPERM16,
+    XPERM32,
+    XPERM4,
+    XPERM8,
+    ZEXT_H,
+    ZUNPKD810,
+    ZUNPKD820,
+    ZUNPKD830,
+    ZUNPKD831,
+    ZUNPKD832,
+    INVALID_INSTR
+}
+
+
+  enum riscv_opcodes_imm_t: byte {
+    imm20,
+    jimm20,
+    imm12,
+    imm12hi,
+    bimm12hi,
+    imm12lo,
+    bimm12lo,
+    imm2,
+    imm3,
+    imm4,
+    imm5,
+    imm6,
+    zimm
+  }
+
+  enum riscv_opcodes_v_imm_t: byte {
+    simm5,
+    zimm5,
+    zimm10,
+    zimm11,
+    zimm6hi,
+    zimm6lo
+  }
+
+  enum riscv_opcodes_c_imm_t: byte {
+    c_nzuimm10,
+    c_uimm7lo,
+    c_uimm7hi,
+    c_uimm8lo,
+    c_uimm8hi,
+    c_uimm9lo,
+    c_uimm9hi,
+    c_nzimm6lo,
+    c_nzimm6hi,
+    c_imm6lo,
+    c_imm6hi,
+    c_nzimm10hi,
+    c_nzimm10lo,
+    c_nzimm18hi,
+    c_nzimm18lo,
+    c_imm12,
+    c_bimm9lo,
+    c_bimm9hi,
+    c_nzuimm5,
+    c_nzuimm6lo,
+    c_nzuimm6hi,
+    c_uimm8splo,
+    c_uimm8sphi,
+    c_uimm8sp_s,
+    c_uimm10splo,
+    c_uimm10sphi,
+    c_uimm9splo,
+    c_uimm9sphi,
+    c_uimm10sp_s,
+    c_uimm9sp_s,
+    c_uimm2,
+    c_uimm1,
+    c_spimm
+  }
+
+  enum riscv_opcodes_var_t: byte {
+    rd,
+    rt,
+    rs1,
+    rs2,
+    rs3,
+    aqrl,
+    aq,
+    rl,
+    fm,
+    pred,
+    succ,
+    rm,
+    funct3,
+    funct2,
+    csr,
+    shamtq,
+    shamtw,
+    shamtw4,
+    shamtd,
+    bs,
+    rnum,
+    rc,
+    opcode,
+    funct7
+  }
+
+  enum riscv_opcodes_v_var_t: byte {
+    vd,
+    vs3,
+    vs1,
+    vs2,
+    vm,
+    wd,
+    amoop,
+    nf
+  }
+ 
+  enum riscv_opcodes_c_var_t: byte {
+    c_rlist,
+    c_index,
+    rs1_p,
+    rs2_p,
+    rd_p,
+    rd_rs1_n0,
+    rd_rs1_p,
+    rd_rs1,
+    rd_n2,
+    rd_n0,
+    rs1_n0,
+    c_rs2_n0,
+    c_rs1_n0,
+    c_rs2,
+    c_sreg1,
+    c_sreg2
+  }
+
+
+enum riscv_extention_t: short {
+  rv_s,
+  rv_system,
+  rv_sdext,
+  rv_i,
+  rv32_i,
+  rv64_i,
+  rv_c,
+  rv32_c,
+  rv_c_d,
+  rv64_c,
+  rv128_c,
+  rv_zba,
+  rv64_zba,
+  rv_zbb,
+  rv64_zbb,
+  rv_zbc,
+  rv_zbe,
+  rv64_zbe,
+  rv_zbf,
+  rv64_zbf,
+  rv64_zbm,
+  rv_zbp,
+  rv64_zbp,
+  rv_zbr,
+  rv64_zbr,
+  rv_zbs,
+  rv64_zbs,
+  rv_zbt,
+  rv64_zbt,
+  rv64_zks,
+  rv_b,
+  rv64_b,
+  rv_m,
+  rv64_m,
+  rv_f,
+  rv32_c_f,
+  rv64_f,
+  rv_d,
+  rv32_c_d,
+  rv64_d,
+  rv_a,
+  rv64_a,
+  rv_v,
+  rv_v_aliases,
+  rv_zicsr,
+  rv_zifencei,
+  rv_zvknha,
+  rv_zvknhb,
+  rv_zpn,
+  rv32_zpn,
+  rv64_zpn,
+  rv_zvkg,
+  rv_zvkn,
+  rv_zvks
+};
+	struct riscv_instr_var_params_s {
+	  riscv_instr_var_t _arg;
+	  ubyte             _lsb;
+	  ubyte             _msb;
+	}
+	
+	struct riscv_instr_param_s {
+	  riscv_instr_name_t _name;
+	  riscv_instr_name_t _orig_name;
+	  uint _mask;
+	  uint _match;
+	  riscv_instr_var_t[] _var_list;
+	  riscv_extention_t[] _ext_list;
+	  ulong _imms;
+	  ulong _c_imms;
+	  ulong _v_imms;
+	  ulong _vars;
+	  ulong _c_vars;
+	  ulong _v_vars;
+	}
+
+      
+enum riscv_instr_var_t: short {
+  rd,
+  rt,
+  rs1,
+  rs2,
+  rs3,
+  aqrl,
+  aq,
+  rl,
+  fm,
+  pred,
+  succ,
+  rm,
+  funct3,
+  funct2,
+  imm20,
+  jimm20,
+  imm12,
+  csr,
+  imm12hi,
+  bimm12hi,
+  imm12lo,
+  bimm12lo,
+  zimm,
+  shamtq,
+  shamtw,
+  shamtw4,
+  shamtd,
+  bs,
+  rnum,
+  rc,
+  imm2,
+  imm3,
+  imm4,
+  imm5,
+  imm6,
+  opcode,
+  funct7,
+  vd,
+  vs3,
+  vs1,
+  vs2,
+  vm,
+  wd,
+  amoop,
+  nf,
+  simm5,
+  zimm5,
+  zimm10,
+  zimm11,
+  zimm6hi,
+  zimm6lo,
+  c_nzuimm10,
+  c_uimm7lo,
+  c_uimm7hi,
+  c_uimm8lo,
+  c_uimm8hi,
+  c_uimm9lo,
+  c_uimm9hi,
+  c_nzimm6lo,
+  c_nzimm6hi,
+  c_imm6lo,
+  c_imm6hi,
+  c_nzimm10hi,
+  c_nzimm10lo,
+  c_nzimm18hi,
+  c_nzimm18lo,
+  c_imm12,
+  c_bimm9lo,
+  c_bimm9hi,
+  c_nzuimm5,
+  c_nzuimm6lo,
+  c_nzuimm6hi,
+  c_uimm8splo,
+  c_uimm8sphi,
+  c_uimm8sp_s,
+  c_uimm10splo,
+  c_uimm10sphi,
+  c_uimm9splo,
+  c_uimm9sphi,
+  c_uimm10sp_s,
+  c_uimm9sp_s,
+  c_uimm2,
+  c_uimm1,
+  c_rlist,
+  c_spimm,
+  c_index,
+  rs1_p,
+  rs2_p,
+  rd_p,
+  rd_rs1_n0,
+  rd_rs1_p,
+  rd_rs1,
+  rd_n2,
+  rd_n0,
+  rs1_n0,
+  c_rs2_n0,
+  c_rs1_n0,
+  c_rs2,
+  c_sreg1,
+  c_sreg2,
+}
+
+enum riscv_instr_var_params_s[] riscv_instr_var_params = [
+  riscv_instr_var_params_s(riscv_instr_var_t.rd, 7, 12),
+  riscv_instr_var_params_s(riscv_instr_var_t.rt, 15, 20),
+  riscv_instr_var_params_s(riscv_instr_var_t.rs1, 15, 20),
+  riscv_instr_var_params_s(riscv_instr_var_t.rs2, 20, 25),
+  riscv_instr_var_params_s(riscv_instr_var_t.rs3, 27, 32),
+  riscv_instr_var_params_s(riscv_instr_var_t.aqrl, 25, 27),
+  riscv_instr_var_params_s(riscv_instr_var_t.aq, 26, 27),
+  riscv_instr_var_params_s(riscv_instr_var_t.rl, 25, 26),
+  riscv_instr_var_params_s(riscv_instr_var_t.fm, 28, 32),
+  riscv_instr_var_params_s(riscv_instr_var_t.pred, 24, 28),
+  riscv_instr_var_params_s(riscv_instr_var_t.succ, 20, 24),
+  riscv_instr_var_params_s(riscv_instr_var_t.rm, 12, 15),
+  riscv_instr_var_params_s(riscv_instr_var_t.funct3, 12, 15),
+  riscv_instr_var_params_s(riscv_instr_var_t.funct2, 25, 27),
+  riscv_instr_var_params_s(riscv_instr_var_t.imm20, 12, 32),
+  riscv_instr_var_params_s(riscv_instr_var_t.jimm20, 12, 32),
+  riscv_instr_var_params_s(riscv_instr_var_t.imm12, 20, 32),
+  riscv_instr_var_params_s(riscv_instr_var_t.csr, 20, 32),
+  riscv_instr_var_params_s(riscv_instr_var_t.imm12hi, 25, 32),
+  riscv_instr_var_params_s(riscv_instr_var_t.bimm12hi, 25, 32),
+  riscv_instr_var_params_s(riscv_instr_var_t.imm12lo, 7, 12),
+  riscv_instr_var_params_s(riscv_instr_var_t.bimm12lo, 7, 12),
+  riscv_instr_var_params_s(riscv_instr_var_t.zimm, 15, 20),
+  riscv_instr_var_params_s(riscv_instr_var_t.shamtq, 20, 27),
+  riscv_instr_var_params_s(riscv_instr_var_t.shamtw, 20, 25),
+  riscv_instr_var_params_s(riscv_instr_var_t.shamtw4, 20, 24),
+  riscv_instr_var_params_s(riscv_instr_var_t.shamtd, 20, 26),
+  riscv_instr_var_params_s(riscv_instr_var_t.bs, 30, 32),
+  riscv_instr_var_params_s(riscv_instr_var_t.rnum, 20, 24),
+  riscv_instr_var_params_s(riscv_instr_var_t.rc, 25, 30),
+  riscv_instr_var_params_s(riscv_instr_var_t.imm2, 20, 22),
+  riscv_instr_var_params_s(riscv_instr_var_t.imm3, 20, 23),
+  riscv_instr_var_params_s(riscv_instr_var_t.imm4, 20, 24),
+  riscv_instr_var_params_s(riscv_instr_var_t.imm5, 20, 25),
+  riscv_instr_var_params_s(riscv_instr_var_t.imm6, 20, 26),
+  riscv_instr_var_params_s(riscv_instr_var_t.opcode, 0, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.funct7, 25, 32),
+  riscv_instr_var_params_s(riscv_instr_var_t.vd, 7, 12),
+  riscv_instr_var_params_s(riscv_instr_var_t.vs3, 7, 12),
+  riscv_instr_var_params_s(riscv_instr_var_t.vs1, 15, 20),
+  riscv_instr_var_params_s(riscv_instr_var_t.vs2, 20, 25),
+  riscv_instr_var_params_s(riscv_instr_var_t.vm, 25, 26),
+  riscv_instr_var_params_s(riscv_instr_var_t.wd, 26, 27),
+  riscv_instr_var_params_s(riscv_instr_var_t.amoop, 27, 32),
+  riscv_instr_var_params_s(riscv_instr_var_t.nf, 29, 32),
+  riscv_instr_var_params_s(riscv_instr_var_t.simm5, 15, 20),
+  riscv_instr_var_params_s(riscv_instr_var_t.zimm5, 15, 20),
+  riscv_instr_var_params_s(riscv_instr_var_t.zimm10, 20, 30),
+  riscv_instr_var_params_s(riscv_instr_var_t.zimm11, 20, 31),
+  riscv_instr_var_params_s(riscv_instr_var_t.zimm6hi, 26, 27),
+  riscv_instr_var_params_s(riscv_instr_var_t.zimm6lo, 15, 20),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_nzuimm10, 5, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm7lo, 5, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm7hi, 10, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm8lo, 5, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm8hi, 10, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm9lo, 5, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm9hi, 10, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_nzimm6lo, 2, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_nzimm6hi, 12, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_imm6lo, 2, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_imm6hi, 12, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_nzimm10hi, 12, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_nzimm10lo, 2, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_nzimm18hi, 12, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_nzimm18lo, 2, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_imm12, 2, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_bimm9lo, 2, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_bimm9hi, 10, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_nzuimm5, 2, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_nzuimm6lo, 2, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_nzuimm6hi, 12, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm8splo, 2, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm8sphi, 12, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm8sp_s, 7, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm10splo, 2, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm10sphi, 12, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm9splo, 2, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm9sphi, 12, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm10sp_s, 7, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm9sp_s, 7, 13),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm2, 5, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_uimm1, 5, 6),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_rlist, 4, 8),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_spimm, 2, 4),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_index, 2, 10),
+  riscv_instr_var_params_s(riscv_instr_var_t.rs1_p, 7, 10),
+  riscv_instr_var_params_s(riscv_instr_var_t.rs2_p, 2, 5),
+  riscv_instr_var_params_s(riscv_instr_var_t.rd_p, 2, 5),
+  riscv_instr_var_params_s(riscv_instr_var_t.rd_rs1_n0, 7, 12),
+  riscv_instr_var_params_s(riscv_instr_var_t.rd_rs1_p, 7, 10),
+  riscv_instr_var_params_s(riscv_instr_var_t.rd_rs1, 7, 12),
+  riscv_instr_var_params_s(riscv_instr_var_t.rd_n2, 7, 12),
+  riscv_instr_var_params_s(riscv_instr_var_t.rd_n0, 7, 12),
+  riscv_instr_var_params_s(riscv_instr_var_t.rs1_n0, 7, 12),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_rs2_n0, 2, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_rs1_n0, 7, 12),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_rs2, 2, 7),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_sreg1, 7, 10),
+  riscv_instr_var_params_s(riscv_instr_var_t.c_sreg2, 2, 5),
+];
+
+enum riscv_instr_params = 
+  [  riscv_instr_param_s(
+     riscv_instr_name_t.ADD, // instr_name
+     riscv_instr_name_t.ADD, // orig_name
+     0xfe00707f, // mask
+     0x33, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ADD
+  riscv_instr_param_s(
+     riscv_instr_name_t.ADD16, // instr_name
+     riscv_instr_name_t.ADD16, // orig_name
+     0xfe00707f, // mask
+     0x40000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ADD16
+  riscv_instr_param_s(
+     riscv_instr_name_t.ADD32, // instr_name
+     riscv_instr_name_t.ADD32, // orig_name
+     0xfe00707f, // mask
+     0x40002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ADD32
+  riscv_instr_param_s(
+     riscv_instr_name_t.ADD8, // instr_name
+     riscv_instr_name_t.ADD8, // orig_name
+     0xfe00707f, // mask
+     0x48000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ADD8
+  riscv_instr_param_s(
+     riscv_instr_name_t.ADD_UW, // instr_name
+     riscv_instr_name_t.ADD_UW, // orig_name
+     0xfe00707f, // mask
+     0x800003b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zba], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ADD_UW
+  riscv_instr_param_s(
+     riscv_instr_name_t.ADDI, // instr_name
+     riscv_instr_name_t.ADDI, // orig_name
+     0x707f, // mask
+     0x13, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ADDI
+  riscv_instr_param_s(
+     riscv_instr_name_t.ADDIW, // instr_name
+     riscv_instr_name_t.ADDIW, // orig_name
+     0x707f, // mask
+     0x1b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ADDIW
+  riscv_instr_param_s(
+     riscv_instr_name_t.ADDW, // instr_name
+     riscv_instr_name_t.ADDW, // orig_name
+     0xfe00707f, // mask
+     0x3b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ADDW
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOADD_D, // instr_name
+     riscv_instr_name_t.AMOADD_D, // orig_name
+     0xf800707f, // mask
+     0x302f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv64_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOADD_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOADD_W, // instr_name
+     riscv_instr_name_t.AMOADD_W, // orig_name
+     0xf800707f, // mask
+     0x202f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOADD_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOAND_D, // instr_name
+     riscv_instr_name_t.AMOAND_D, // orig_name
+     0xf800707f, // mask
+     0x6000302f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv64_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOAND_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOAND_W, // instr_name
+     riscv_instr_name_t.AMOAND_W, // orig_name
+     0xf800707f, // mask
+     0x6000202f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOAND_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOMAX_D, // instr_name
+     riscv_instr_name_t.AMOMAX_D, // orig_name
+     0xf800707f, // mask
+     0xa000302f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv64_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOMAX_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOMAX_W, // instr_name
+     riscv_instr_name_t.AMOMAX_W, // orig_name
+     0xf800707f, // mask
+     0xa000202f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOMAX_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOMAXU_D, // instr_name
+     riscv_instr_name_t.AMOMAXU_D, // orig_name
+     0xf800707f, // mask
+     0xe000302f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv64_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOMAXU_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOMAXU_W, // instr_name
+     riscv_instr_name_t.AMOMAXU_W, // orig_name
+     0xf800707f, // mask
+     0xe000202f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOMAXU_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOMIN_D, // instr_name
+     riscv_instr_name_t.AMOMIN_D, // orig_name
+     0xf800707f, // mask
+     0x8000302f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv64_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOMIN_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOMIN_W, // instr_name
+     riscv_instr_name_t.AMOMIN_W, // orig_name
+     0xf800707f, // mask
+     0x8000202f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOMIN_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOMINU_D, // instr_name
+     riscv_instr_name_t.AMOMINU_D, // orig_name
+     0xf800707f, // mask
+     0xc000302f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv64_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOMINU_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOMINU_W, // instr_name
+     riscv_instr_name_t.AMOMINU_W, // orig_name
+     0xf800707f, // mask
+     0xc000202f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOMINU_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOOR_D, // instr_name
+     riscv_instr_name_t.AMOOR_D, // orig_name
+     0xf800707f, // mask
+     0x4000302f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv64_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOOR_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOOR_W, // instr_name
+     riscv_instr_name_t.AMOOR_W, // orig_name
+     0xf800707f, // mask
+     0x4000202f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOOR_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOSWAP_D, // instr_name
+     riscv_instr_name_t.AMOSWAP_D, // orig_name
+     0xf800707f, // mask
+     0x800302f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv64_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOSWAP_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOSWAP_W, // instr_name
+     riscv_instr_name_t.AMOSWAP_W, // orig_name
+     0xf800707f, // mask
+     0x800202f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOSWAP_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOXOR_D, // instr_name
+     riscv_instr_name_t.AMOXOR_D, // orig_name
+     0xf800707f, // mask
+     0x2000302f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv64_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOXOR_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.AMOXOR_W, // instr_name
+     riscv_instr_name_t.AMOXOR_W, // orig_name
+     0xf800707f, // mask
+     0x2000202f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AMOXOR_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.AND, // instr_name
+     riscv_instr_name_t.AND, // orig_name
+     0xfe00707f, // mask
+     0x7033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AND
+  riscv_instr_param_s(
+     riscv_instr_name_t.ANDI, // instr_name
+     riscv_instr_name_t.ANDI, // orig_name
+     0x707f, // mask
+     0x7013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ANDI
+  riscv_instr_param_s(
+     riscv_instr_name_t.ANDN, // instr_name
+     riscv_instr_name_t.ANDN, // orig_name
+     0xfe00707f, // mask
+     0x40007033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbb, riscv_extention_t.rv_zbp, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ANDN
+  riscv_instr_param_s(
+     riscv_instr_name_t.AUIPC, // instr_name
+     riscv_instr_name_t.AUIPC, // orig_name
+     0x7f, // mask
+     0x17, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.imm20], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b1, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AUIPC
+  riscv_instr_param_s(
+     riscv_instr_name_t.AVE, // instr_name
+     riscv_instr_name_t.AVE, // orig_name
+     0xfe00707f, // mask
+     0xe0000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // AVE
+  riscv_instr_param_s(
+     riscv_instr_name_t.BCLR, // instr_name
+     riscv_instr_name_t.BCLR, // orig_name
+     0xfe00707f, // mask
+     0x48001033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbs], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BCLR
+  riscv_instr_param_s(
+     riscv_instr_name_t.BCLRI, // instr_name
+     riscv_instr_name_t.BCLRI, // orig_name
+     0xfc00707f, // mask
+     0x48001013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv64_zbs], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BCLRI
+  riscv_instr_param_s(
+     riscv_instr_name_t.BCOMPRESS, // instr_name
+     riscv_instr_name_t.BCOMPRESS, // orig_name
+     0xfe00707f, // mask
+     0x8006033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbe], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BCOMPRESS
+  riscv_instr_param_s(
+     riscv_instr_name_t.BCOMPRESSW, // instr_name
+     riscv_instr_name_t.BCOMPRESSW, // orig_name
+     0xfe00707f, // mask
+     0x800603b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbe], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BCOMPRESSW
+  riscv_instr_param_s(
+     riscv_instr_name_t.BDECOMPRESS, // instr_name
+     riscv_instr_name_t.BDECOMPRESS, // orig_name
+     0xfe00707f, // mask
+     0x48006033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbe], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BDECOMPRESS
+  riscv_instr_param_s(
+     riscv_instr_name_t.BDECOMPRESSW, // instr_name
+     riscv_instr_name_t.BDECOMPRESSW, // orig_name
+     0xfe00707f, // mask
+     0x4800603b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbe], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BDECOMPRESSW
+  riscv_instr_param_s(
+     riscv_instr_name_t.BEQ, // instr_name
+     riscv_instr_name_t.BEQ, // orig_name
+     0x707f, // mask
+     0x63, // match
+     [riscv_instr_var_t.bimm12hi, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.bimm12lo], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b1010000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BEQ
+  riscv_instr_param_s(
+     riscv_instr_name_t.BEXT, // instr_name
+     riscv_instr_name_t.BEXT, // orig_name
+     0xfe00707f, // mask
+     0x48005033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbs], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BEXT
+  riscv_instr_param_s(
+     riscv_instr_name_t.BEXTI, // instr_name
+     riscv_instr_name_t.BEXTI, // orig_name
+     0xfc00707f, // mask
+     0x48005013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv64_zbs], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BEXTI
+  riscv_instr_param_s(
+     riscv_instr_name_t.BFP, // instr_name
+     riscv_instr_name_t.BFP, // orig_name
+     0xfe00707f, // mask
+     0x48007033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbf], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BFP
+  riscv_instr_param_s(
+     riscv_instr_name_t.BFPW, // instr_name
+     riscv_instr_name_t.BFPW, // orig_name
+     0xfe00707f, // mask
+     0x4800703b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbf], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BFPW
+  riscv_instr_param_s(
+     riscv_instr_name_t.BGE, // instr_name
+     riscv_instr_name_t.BGE, // orig_name
+     0x707f, // mask
+     0x5063, // match
+     [riscv_instr_var_t.bimm12hi, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.bimm12lo], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b1010000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BGE
+  riscv_instr_param_s(
+     riscv_instr_name_t.BGEU, // instr_name
+     riscv_instr_name_t.BGEU, // orig_name
+     0x707f, // mask
+     0x7063, // match
+     [riscv_instr_var_t.bimm12hi, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.bimm12lo], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b1010000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BGEU
+  riscv_instr_param_s(
+     riscv_instr_name_t.BINV, // instr_name
+     riscv_instr_name_t.BINV, // orig_name
+     0xfe00707f, // mask
+     0x68001033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbs], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BINV
+  riscv_instr_param_s(
+     riscv_instr_name_t.BINVI, // instr_name
+     riscv_instr_name_t.BINVI, // orig_name
+     0xfc00707f, // mask
+     0x68001013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv64_zbs], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BINVI
+  riscv_instr_param_s(
+     riscv_instr_name_t.BLT, // instr_name
+     riscv_instr_name_t.BLT, // orig_name
+     0x707f, // mask
+     0x4063, // match
+     [riscv_instr_var_t.bimm12hi, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.bimm12lo], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b1010000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BLT
+  riscv_instr_param_s(
+     riscv_instr_name_t.BLTU, // instr_name
+     riscv_instr_name_t.BLTU, // orig_name
+     0x707f, // mask
+     0x6063, // match
+     [riscv_instr_var_t.bimm12hi, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.bimm12lo], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b1010000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BLTU
+  riscv_instr_param_s(
+     riscv_instr_name_t.BMATFLIP, // instr_name
+     riscv_instr_name_t.BMATFLIP, // orig_name
+     0xfff0707f, // mask
+     0x60301013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv64_zbm], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BMATFLIP
+  riscv_instr_param_s(
+     riscv_instr_name_t.BMATOR, // instr_name
+     riscv_instr_name_t.BMATOR, // orig_name
+     0xfe00707f, // mask
+     0x8003033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbm], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BMATOR
+  riscv_instr_param_s(
+     riscv_instr_name_t.BMATXOR, // instr_name
+     riscv_instr_name_t.BMATXOR, // orig_name
+     0xfe00707f, // mask
+     0x48003033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbm], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BMATXOR
+  riscv_instr_param_s(
+     riscv_instr_name_t.BNE, // instr_name
+     riscv_instr_name_t.BNE, // orig_name
+     0x707f, // mask
+     0x1063, // match
+     [riscv_instr_var_t.bimm12hi, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.bimm12lo], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b1010000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BNE
+  riscv_instr_param_s(
+     riscv_instr_name_t.BSET, // instr_name
+     riscv_instr_name_t.BSET, // orig_name
+     0xfe00707f, // mask
+     0x28001033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbs], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BSET
+  riscv_instr_param_s(
+     riscv_instr_name_t.BSETI, // instr_name
+     riscv_instr_name_t.BSETI, // orig_name
+     0xfc00707f, // mask
+     0x28001013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv64_zbs], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // BSETI
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_ADD, // instr_name
+     riscv_instr_name_t.C_ADD, // orig_name
+     0xf003, // mask
+     0x9002, // match
+     [riscv_instr_var_t.rd_rs1, riscv_instr_var_t.c_rs2_n0], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b100010000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_ADD
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_ADDI, // instr_name
+     riscv_instr_name_t.C_ADDI, // orig_name
+     0xe003, // mask
+     0x1, // match
+     [riscv_instr_var_t.rd_rs1_n0, riscv_instr_var_t.c_nzimm6lo, riscv_instr_var_t.c_nzimm6hi], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b110000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b100000, // _c_vars
+     0b0, // _v_vars
+   ), // C_ADDI
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_ADDI16SP, // instr_name
+     riscv_instr_name_t.C_ADDI16SP, // orig_name
+     0xef83, // mask
+     0x6101, // match
+     [riscv_instr_var_t.c_nzimm10hi, riscv_instr_var_t.c_nzimm10lo], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b1100000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // C_ADDI16SP
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_ADDI4SPN, // instr_name
+     riscv_instr_name_t.C_ADDI4SPN, // orig_name
+     0xe003, // mask
+     0x0, // match
+     [riscv_instr_var_t.rd_p, riscv_instr_var_t.c_nzuimm10], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b1, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b10000, // _c_vars
+     0b0, // _v_vars
+   ), // C_ADDI4SPN
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_ADDIW, // instr_name
+     riscv_instr_name_t.C_ADDIW, // orig_name
+     0xe003, // mask
+     0x2001, // match
+     [riscv_instr_var_t.rd_rs1_n0, riscv_instr_var_t.c_imm6lo, riscv_instr_var_t.c_imm6hi], // variables
+     [riscv_extention_t.rv64_c, riscv_extention_t.rv128_c], // extentions
+     0b0, // _imms
+     0b11000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b100000, // _c_vars
+     0b0, // _v_vars
+   ), // C_ADDIW
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_ADDW, // instr_name
+     riscv_instr_name_t.C_ADDW, // orig_name
+     0xfc63, // mask
+     0x9c21, // match
+     [riscv_instr_var_t.rd_rs1_p, riscv_instr_var_t.rs2_p], // variables
+     [riscv_extention_t.rv64_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1001000, // _c_vars
+     0b0, // _v_vars
+   ), // C_ADDW
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_AND, // instr_name
+     riscv_instr_name_t.C_AND, // orig_name
+     0xfc63, // mask
+     0x8c61, // match
+     [riscv_instr_var_t.rd_rs1_p, riscv_instr_var_t.rs2_p], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1001000, // _c_vars
+     0b0, // _v_vars
+   ), // C_AND
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_ANDI, // instr_name
+     riscv_instr_name_t.C_ANDI, // orig_name
+     0xec03, // mask
+     0x8801, // match
+     [riscv_instr_var_t.rd_rs1_p, riscv_instr_var_t.c_imm6hi, riscv_instr_var_t.c_imm6lo], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b11000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_ANDI
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_BEQZ, // instr_name
+     riscv_instr_name_t.C_BEQZ, // orig_name
+     0xe003, // mask
+     0xc001, // match
+     [riscv_instr_var_t.rs1_p, riscv_instr_var_t.c_bimm9lo, riscv_instr_var_t.c_bimm9hi], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b110000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b100, // _c_vars
+     0b0, // _v_vars
+   ), // C_BEQZ
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_BNEZ, // instr_name
+     riscv_instr_name_t.C_BNEZ, // orig_name
+     0xe003, // mask
+     0xe001, // match
+     [riscv_instr_var_t.rs1_p, riscv_instr_var_t.c_bimm9lo, riscv_instr_var_t.c_bimm9hi], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b110000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b100, // _c_vars
+     0b0, // _v_vars
+   ), // C_BNEZ
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_EBREAK, // instr_name
+     riscv_instr_name_t.C_EBREAK, // orig_name
+     0xffff, // mask
+     0x9002, // match
+     [], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // C_EBREAK
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_FLD, // instr_name
+     riscv_instr_name_t.C_FLD, // orig_name
+     0xe003, // mask
+     0x2000, // match
+     [riscv_instr_var_t.rd_p, riscv_instr_var_t.rs1_p, riscv_instr_var_t.c_uimm8lo, riscv_instr_var_t.c_uimm8hi], // variables
+     [riscv_extention_t.rv_c_d], // extentions
+     0b0, // _imms
+     0b11000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b10100, // _c_vars
+     0b0, // _v_vars
+   ), // C_FLD
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_FLDSP, // instr_name
+     riscv_instr_name_t.C_FLDSP, // orig_name
+     0xe003, // mask
+     0x2002, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.c_uimm9sphi, riscv_instr_var_t.c_uimm9splo], // variables
+     [riscv_extention_t.rv_c_d], // extentions
+     0b0, // _imms
+     0b1100000000000000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // C_FLDSP
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_FLW, // instr_name
+     riscv_instr_name_t.C_FLW, // orig_name
+     0xe003, // mask
+     0x6000, // match
+     [riscv_instr_var_t.rd_p, riscv_instr_var_t.rs1_p, riscv_instr_var_t.c_uimm7lo, riscv_instr_var_t.c_uimm7hi], // variables
+     [riscv_extention_t.rv32_c_f], // extentions
+     0b0, // _imms
+     0b110, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b10100, // _c_vars
+     0b0, // _v_vars
+   ), // C_FLW
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_FLWSP, // instr_name
+     riscv_instr_name_t.C_FLWSP, // orig_name
+     0xe003, // mask
+     0x6002, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.c_uimm8sphi, riscv_instr_var_t.c_uimm8splo], // variables
+     [riscv_extention_t.rv32_c_f], // extentions
+     0b0, // _imms
+     0b11000000000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // C_FLWSP
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_FSD, // instr_name
+     riscv_instr_name_t.C_FSD, // orig_name
+     0xe003, // mask
+     0xa000, // match
+     [riscv_instr_var_t.rs1_p, riscv_instr_var_t.rs2_p, riscv_instr_var_t.c_uimm8lo, riscv_instr_var_t.c_uimm8hi], // variables
+     [riscv_extention_t.rv_c_d], // extentions
+     0b0, // _imms
+     0b11000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1100, // _c_vars
+     0b0, // _v_vars
+   ), // C_FSD
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_FSDSP, // instr_name
+     riscv_instr_name_t.C_FSDSP, // orig_name
+     0xe003, // mask
+     0xa002, // match
+     [riscv_instr_var_t.c_rs2, riscv_instr_var_t.c_uimm9sp_s], // variables
+     [riscv_extention_t.rv_c_d], // extentions
+     0b0, // _imms
+     0b100000000000000000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b10000000000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_FSDSP
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_FSW, // instr_name
+     riscv_instr_name_t.C_FSW, // orig_name
+     0xe003, // mask
+     0xe000, // match
+     [riscv_instr_var_t.rs1_p, riscv_instr_var_t.rs2_p, riscv_instr_var_t.c_uimm7lo, riscv_instr_var_t.c_uimm7hi], // variables
+     [riscv_extention_t.rv32_c_f], // extentions
+     0b0, // _imms
+     0b110, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1100, // _c_vars
+     0b0, // _v_vars
+   ), // C_FSW
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_FSWSP, // instr_name
+     riscv_instr_name_t.C_FSWSP, // orig_name
+     0xe003, // mask
+     0xe002, // match
+     [riscv_instr_var_t.c_rs2, riscv_instr_var_t.c_uimm8sp_s], // variables
+     [riscv_extention_t.rv32_c_f], // extentions
+     0b0, // _imms
+     0b100000000000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b10000000000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_FSWSP
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_J, // instr_name
+     riscv_instr_name_t.C_J, // orig_name
+     0xe003, // mask
+     0xa001, // match
+     [riscv_instr_var_t.c_imm12], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b1000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // C_J
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_JAL, // instr_name
+     riscv_instr_name_t.C_JAL, // orig_name
+     0xe003, // mask
+     0x2001, // match
+     [riscv_instr_var_t.c_imm12], // variables
+     [riscv_extention_t.rv32_c], // extentions
+     0b0, // _imms
+     0b1000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // C_JAL
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_JALR, // instr_name
+     riscv_instr_name_t.C_JALR, // orig_name
+     0xf07f, // mask
+     0x9002, // match
+     [riscv_instr_var_t.c_rs1_n0], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1000000000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_JALR
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_JR, // instr_name
+     riscv_instr_name_t.C_JR, // orig_name
+     0xf07f, // mask
+     0x8002, // match
+     [riscv_instr_var_t.rs1_n0], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b10000000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_JR
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_LD, // instr_name
+     riscv_instr_name_t.C_LD, // orig_name
+     0xe003, // mask
+     0x6000, // match
+     [riscv_instr_var_t.rd_p, riscv_instr_var_t.rs1_p, riscv_instr_var_t.c_uimm8lo, riscv_instr_var_t.c_uimm8hi], // variables
+     [riscv_extention_t.rv64_c, riscv_extention_t.rv128_c], // extentions
+     0b0, // _imms
+     0b11000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b10100, // _c_vars
+     0b0, // _v_vars
+   ), // C_LD
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_LDSP, // instr_name
+     riscv_instr_name_t.C_LDSP, // orig_name
+     0xe003, // mask
+     0x6002, // match
+     [riscv_instr_var_t.rd_n0, riscv_instr_var_t.c_uimm9sphi, riscv_instr_var_t.c_uimm9splo], // variables
+     [riscv_extention_t.rv64_c, riscv_extention_t.rv128_c], // extentions
+     0b0, // _imms
+     0b1100000000000000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1000000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_LDSP
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_LI, // instr_name
+     riscv_instr_name_t.C_LI, // orig_name
+     0xe003, // mask
+     0x4001, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.c_imm6lo, riscv_instr_var_t.c_imm6hi], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b11000000000, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // C_LI
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_LQ, // instr_name
+     riscv_instr_name_t.C_LQ, // orig_name
+     0xe003, // mask
+     0x2000, // match
+     [riscv_instr_var_t.rd_p, riscv_instr_var_t.rs1_p, riscv_instr_var_t.c_uimm9lo, riscv_instr_var_t.c_uimm9hi], // variables
+     [riscv_extention_t.rv128_c], // extentions
+     0b0, // _imms
+     0b1100000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b10100, // _c_vars
+     0b0, // _v_vars
+   ), // C_LQ
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_LQSP, // instr_name
+     riscv_instr_name_t.C_LQSP, // orig_name
+     0xe003, // mask
+     0x2002, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.c_uimm10sphi, riscv_instr_var_t.c_uimm10splo], // variables
+     [riscv_extention_t.rv128_c], // extentions
+     0b0, // _imms
+     0b11000000000000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // C_LQSP
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_LUI, // instr_name
+     riscv_instr_name_t.C_LUI, // orig_name
+     0xe003, // mask
+     0x6001, // match
+     [riscv_instr_var_t.rd_n2, riscv_instr_var_t.c_nzimm18hi, riscv_instr_var_t.c_nzimm18lo], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b110000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b100000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_LUI
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_LW, // instr_name
+     riscv_instr_name_t.C_LW, // orig_name
+     0xe003, // mask
+     0x4000, // match
+     [riscv_instr_var_t.rd_p, riscv_instr_var_t.rs1_p, riscv_instr_var_t.c_uimm7lo, riscv_instr_var_t.c_uimm7hi], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b110, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b10100, // _c_vars
+     0b0, // _v_vars
+   ), // C_LW
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_LWSP, // instr_name
+     riscv_instr_name_t.C_LWSP, // orig_name
+     0xe003, // mask
+     0x4002, // match
+     [riscv_instr_var_t.rd_n0, riscv_instr_var_t.c_uimm8sphi, riscv_instr_var_t.c_uimm8splo], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b11000000000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1000000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_LWSP
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_MV, // instr_name
+     riscv_instr_name_t.C_MV, // orig_name
+     0xf003, // mask
+     0x8002, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.c_rs2_n0], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b100000000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_MV
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_NOP, // instr_name
+     riscv_instr_name_t.C_NOP, // orig_name
+     0xef83, // mask
+     0x1, // match
+     [riscv_instr_var_t.c_nzimm6hi, riscv_instr_var_t.c_nzimm6lo], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b110000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // C_NOP
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_OR, // instr_name
+     riscv_instr_name_t.C_OR, // orig_name
+     0xfc63, // mask
+     0x8c41, // match
+     [riscv_instr_var_t.rd_rs1_p, riscv_instr_var_t.rs2_p], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1001000, // _c_vars
+     0b0, // _v_vars
+   ), // C_OR
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SD, // instr_name
+     riscv_instr_name_t.C_SD, // orig_name
+     0xe003, // mask
+     0xe000, // match
+     [riscv_instr_var_t.rs1_p, riscv_instr_var_t.rs2_p, riscv_instr_var_t.c_uimm8hi, riscv_instr_var_t.c_uimm8lo], // variables
+     [riscv_extention_t.rv64_c, riscv_extention_t.rv128_c], // extentions
+     0b0, // _imms
+     0b11000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1100, // _c_vars
+     0b0, // _v_vars
+   ), // C_SD
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SDSP, // instr_name
+     riscv_instr_name_t.C_SDSP, // orig_name
+     0xe003, // mask
+     0xe002, // match
+     [riscv_instr_var_t.c_rs2, riscv_instr_var_t.c_uimm9sp_s], // variables
+     [riscv_extention_t.rv64_c, riscv_extention_t.rv128_c], // extentions
+     0b0, // _imms
+     0b100000000000000000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b10000000000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_SDSP
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SLLI, // instr_name
+     riscv_instr_name_t.C_SLLI, // orig_name
+     0xe003, // mask
+     0x2, // match
+     [riscv_instr_var_t.rd_rs1_n0, riscv_instr_var_t.c_nzuimm6hi, riscv_instr_var_t.c_nzuimm6lo], // variables
+     [riscv_extention_t.rv64_c], // extentions
+     0b0, // _imms
+     0b110000000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b100000, // _c_vars
+     0b0, // _v_vars
+   ), // C_SLLI
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SLLI64, // instr_name
+     riscv_instr_name_t.C_SLLI64, // orig_name
+     0xf07f, // mask
+     0x8002, // match
+     [riscv_instr_var_t.rd_rs1_n0], // variables
+     [riscv_extention_t.rv128_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b100000, // _c_vars
+     0b0, // _v_vars
+   ), // C_SLLI64
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SQ, // instr_name
+     riscv_instr_name_t.C_SQ, // orig_name
+     0xe003, // mask
+     0xa000, // match
+     [riscv_instr_var_t.rs1_p, riscv_instr_var_t.rs2_p, riscv_instr_var_t.c_uimm9hi, riscv_instr_var_t.c_uimm9lo], // variables
+     [riscv_extention_t.rv128_c], // extentions
+     0b0, // _imms
+     0b1100000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1100, // _c_vars
+     0b0, // _v_vars
+   ), // C_SQ
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SQSP, // instr_name
+     riscv_instr_name_t.C_SQSP, // orig_name
+     0xe003, // mask
+     0xa002, // match
+     [riscv_instr_var_t.c_rs2, riscv_instr_var_t.c_uimm10sp_s], // variables
+     [riscv_extention_t.rv128_c], // extentions
+     0b0, // _imms
+     0b10000000000000000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b10000000000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_SQSP
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SRAI, // instr_name
+     riscv_instr_name_t.C_SRAI, // orig_name
+     0xec03, // mask
+     0x8401, // match
+     [riscv_instr_var_t.rd_rs1_p, riscv_instr_var_t.c_nzuimm6lo, riscv_instr_var_t.c_nzuimm6hi], // variables
+     [riscv_extention_t.rv64_c], // extentions
+     0b0, // _imms
+     0b110000000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_SRAI
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SRAI64, // instr_name
+     riscv_instr_name_t.C_SRAI64, // orig_name
+     0xfc7f, // mask
+     0x8401, // match
+     [riscv_instr_var_t.rd_rs1_p], // variables
+     [riscv_extention_t.rv128_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_SRAI64
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SRLI, // instr_name
+     riscv_instr_name_t.C_SRLI, // orig_name
+     0xec03, // mask
+     0x8001, // match
+     [riscv_instr_var_t.rd_rs1_p, riscv_instr_var_t.c_nzuimm6lo, riscv_instr_var_t.c_nzuimm6hi], // variables
+     [riscv_extention_t.rv64_c], // extentions
+     0b0, // _imms
+     0b110000000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_SRLI
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SRLI64, // instr_name
+     riscv_instr_name_t.C_SRLI64, // orig_name
+     0xfc7f, // mask
+     0x8001, // match
+     [riscv_instr_var_t.rd_rs1_p], // variables
+     [riscv_extention_t.rv128_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_SRLI64
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SUB, // instr_name
+     riscv_instr_name_t.C_SUB, // orig_name
+     0xfc63, // mask
+     0x8c01, // match
+     [riscv_instr_var_t.rd_rs1_p, riscv_instr_var_t.rs2_p], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1001000, // _c_vars
+     0b0, // _v_vars
+   ), // C_SUB
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SUBW, // instr_name
+     riscv_instr_name_t.C_SUBW, // orig_name
+     0xfc63, // mask
+     0x9c01, // match
+     [riscv_instr_var_t.rd_rs1_p, riscv_instr_var_t.rs2_p], // variables
+     [riscv_extention_t.rv64_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1001000, // _c_vars
+     0b0, // _v_vars
+   ), // C_SUBW
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SW, // instr_name
+     riscv_instr_name_t.C_SW, // orig_name
+     0xe003, // mask
+     0xc000, // match
+     [riscv_instr_var_t.rs1_p, riscv_instr_var_t.rs2_p, riscv_instr_var_t.c_uimm7lo, riscv_instr_var_t.c_uimm7hi], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b110, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1100, // _c_vars
+     0b0, // _v_vars
+   ), // C_SW
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_SWSP, // instr_name
+     riscv_instr_name_t.C_SWSP, // orig_name
+     0xe003, // mask
+     0xc002, // match
+     [riscv_instr_var_t.c_rs2, riscv_instr_var_t.c_uimm8sp_s], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b100000000000000000000000, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b10000000000000, // _c_vars
+     0b0, // _v_vars
+   ), // C_SWSP
+  riscv_instr_param_s(
+     riscv_instr_name_t.C_XOR, // instr_name
+     riscv_instr_name_t.C_XOR, // orig_name
+     0xfc63, // mask
+     0x8c21, // match
+     [riscv_instr_var_t.rd_rs1_p, riscv_instr_var_t.rs2_p], // variables
+     [riscv_extention_t.rv_c], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b1001000, // _c_vars
+     0b0, // _v_vars
+   ), // C_XOR
+  riscv_instr_param_s(
+     riscv_instr_name_t.CLMUL, // instr_name
+     riscv_instr_name_t.CLMUL, // orig_name
+     0xfe00707f, // mask
+     0xa001033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbc, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CLMUL
+  riscv_instr_param_s(
+     riscv_instr_name_t.CLMULH, // instr_name
+     riscv_instr_name_t.CLMULH, // orig_name
+     0xfe00707f, // mask
+     0xa003033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbc, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CLMULH
+  riscv_instr_param_s(
+     riscv_instr_name_t.CLMULR, // instr_name
+     riscv_instr_name_t.CLMULR, // orig_name
+     0xfe00707f, // mask
+     0xa002033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbc], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CLMULR
+  riscv_instr_param_s(
+     riscv_instr_name_t.CLROV, // instr_name
+     riscv_instr_name_t.CSRRCI, // orig_name
+     0xfffff07f, // mask
+     0x90f073, // match
+     [riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CLROV
+  riscv_instr_param_s(
+     riscv_instr_name_t.CLRS16, // instr_name
+     riscv_instr_name_t.CLRS16, // orig_name
+     0xfff0707f, // mask
+     0xae800077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CLRS16
+  riscv_instr_param_s(
+     riscv_instr_name_t.CLRS32, // instr_name
+     riscv_instr_name_t.CLRS32, // orig_name
+     0xfff0707f, // mask
+     0xaf800077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CLRS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.CLRS8, // instr_name
+     riscv_instr_name_t.CLRS8, // orig_name
+     0xfff0707f, // mask
+     0xae000077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CLRS8
+  riscv_instr_param_s(
+     riscv_instr_name_t.CLZ, // instr_name
+     riscv_instr_name_t.CLZ, // orig_name
+     0xfff0707f, // mask
+     0x60001013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zbb, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CLZ
+  riscv_instr_param_s(
+     riscv_instr_name_t.CLZ16, // instr_name
+     riscv_instr_name_t.CLZ16, // orig_name
+     0xfff0707f, // mask
+     0xae900077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CLZ16
+  riscv_instr_param_s(
+     riscv_instr_name_t.CLZ32, // instr_name
+     riscv_instr_name_t.CLZ32, // orig_name
+     0xfff0707f, // mask
+     0xaf900077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CLZ32
+  riscv_instr_param_s(
+     riscv_instr_name_t.CLZ8, // instr_name
+     riscv_instr_name_t.CLZ8, // orig_name
+     0xfff0707f, // mask
+     0xae100077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CLZ8
+  riscv_instr_param_s(
+     riscv_instr_name_t.CLZW, // instr_name
+     riscv_instr_name_t.CLZW, // orig_name
+     0xfff0707f, // mask
+     0x6000101b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv64_zbb], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CLZW
+  riscv_instr_param_s(
+     riscv_instr_name_t.CMIX, // instr_name
+     riscv_instr_name_t.CMIX, // orig_name
+     0x600707f, // mask
+     0x6001033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3], // variables
+     [riscv_extention_t.rv_zbt, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CMIX
+  riscv_instr_param_s(
+     riscv_instr_name_t.CMOV, // instr_name
+     riscv_instr_name_t.CMOV, // orig_name
+     0x600707f, // mask
+     0x6005033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3], // variables
+     [riscv_extention_t.rv_zbt], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CMOV
+  riscv_instr_param_s(
+     riscv_instr_name_t.CMPEQ16, // instr_name
+     riscv_instr_name_t.CMPEQ16, // orig_name
+     0xfe00707f, // mask
+     0x4c000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CMPEQ16
+  riscv_instr_param_s(
+     riscv_instr_name_t.CMPEQ8, // instr_name
+     riscv_instr_name_t.CMPEQ8, // orig_name
+     0xfe00707f, // mask
+     0x4e000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CMPEQ8
+  riscv_instr_param_s(
+     riscv_instr_name_t.CPOP, // instr_name
+     riscv_instr_name_t.CPOP, // orig_name
+     0xfff0707f, // mask
+     0x60201013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zbb], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CPOP
+  riscv_instr_param_s(
+     riscv_instr_name_t.CPOPW, // instr_name
+     riscv_instr_name_t.CPOPW, // orig_name
+     0xfff0707f, // mask
+     0x6020101b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv64_zbb], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CPOPW
+  riscv_instr_param_s(
+     riscv_instr_name_t.CRAS16, // instr_name
+     riscv_instr_name_t.CRAS16, // orig_name
+     0xfe00707f, // mask
+     0x44000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CRAS16
+  riscv_instr_param_s(
+     riscv_instr_name_t.CRAS32, // instr_name
+     riscv_instr_name_t.CRAS32, // orig_name
+     0xfe00707f, // mask
+     0x44002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CRAS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.CRC32_B, // instr_name
+     riscv_instr_name_t.CRC32_B, // orig_name
+     0xfff0707f, // mask
+     0x61001013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zbr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CRC32_B
+  riscv_instr_param_s(
+     riscv_instr_name_t.CRC32_D, // instr_name
+     riscv_instr_name_t.CRC32_D, // orig_name
+     0xfff0707f, // mask
+     0x61301013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv64_zbr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CRC32_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.CRC32_H, // instr_name
+     riscv_instr_name_t.CRC32_H, // orig_name
+     0xfff0707f, // mask
+     0x61101013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zbr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CRC32_H
+  riscv_instr_param_s(
+     riscv_instr_name_t.CRC32_W, // instr_name
+     riscv_instr_name_t.CRC32_W, // orig_name
+     0xfff0707f, // mask
+     0x61201013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zbr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CRC32_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.CRC32C_B, // instr_name
+     riscv_instr_name_t.CRC32C_B, // orig_name
+     0xfff0707f, // mask
+     0x61801013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zbr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CRC32C_B
+  riscv_instr_param_s(
+     riscv_instr_name_t.CRC32C_D, // instr_name
+     riscv_instr_name_t.CRC32C_D, // orig_name
+     0xfff0707f, // mask
+     0x61b01013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv64_zbr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CRC32C_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.CRC32C_H, // instr_name
+     riscv_instr_name_t.CRC32C_H, // orig_name
+     0xfff0707f, // mask
+     0x61901013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zbr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CRC32C_H
+  riscv_instr_param_s(
+     riscv_instr_name_t.CRC32C_W, // instr_name
+     riscv_instr_name_t.CRC32C_W, // orig_name
+     0xfff0707f, // mask
+     0x61a01013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zbr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CRC32C_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.CRSA16, // instr_name
+     riscv_instr_name_t.CRSA16, // orig_name
+     0xfe00707f, // mask
+     0x46000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CRSA16
+  riscv_instr_param_s(
+     riscv_instr_name_t.CRSA32, // instr_name
+     riscv_instr_name_t.CRSA32, // orig_name
+     0xfe00707f, // mask
+     0x46002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CRSA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.CSRRC, // instr_name
+     riscv_instr_name_t.CSRRC, // orig_name
+     0x707f, // mask
+     0x3073, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.csr], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CSRRC
+  riscv_instr_param_s(
+     riscv_instr_name_t.CSRRCI, // instr_name
+     riscv_instr_name_t.CSRRCI, // orig_name
+     0x707f, // mask
+     0x7073, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.csr, riscv_instr_var_t.zimm], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b1000000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000000001, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CSRRCI
+  riscv_instr_param_s(
+     riscv_instr_name_t.CSRRS, // instr_name
+     riscv_instr_name_t.CSRRS, // orig_name
+     0x707f, // mask
+     0x2073, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.csr], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CSRRS
+  riscv_instr_param_s(
+     riscv_instr_name_t.CSRRSI, // instr_name
+     riscv_instr_name_t.CSRRSI, // orig_name
+     0x707f, // mask
+     0x6073, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.csr, riscv_instr_var_t.zimm], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b1000000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000000001, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CSRRSI
+  riscv_instr_param_s(
+     riscv_instr_name_t.CSRRW, // instr_name
+     riscv_instr_name_t.CSRRW, // orig_name
+     0x707f, // mask
+     0x1073, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.csr], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CSRRW
+  riscv_instr_param_s(
+     riscv_instr_name_t.CSRRWI, // instr_name
+     riscv_instr_name_t.CSRRWI, // orig_name
+     0x707f, // mask
+     0x5073, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.csr, riscv_instr_var_t.zimm], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b1000000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000000001, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CSRRWI
+  riscv_instr_param_s(
+     riscv_instr_name_t.CTZ, // instr_name
+     riscv_instr_name_t.CTZ, // orig_name
+     0xfff0707f, // mask
+     0x60101013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zbb], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CTZ
+  riscv_instr_param_s(
+     riscv_instr_name_t.CTZW, // instr_name
+     riscv_instr_name_t.CTZW, // orig_name
+     0xfff0707f, // mask
+     0x6010101b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv64_zbb], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // CTZW
+  riscv_instr_param_s(
+     riscv_instr_name_t.DIV, // instr_name
+     riscv_instr_name_t.DIV, // orig_name
+     0xfe00707f, // mask
+     0x2004033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_m], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // DIV
+  riscv_instr_param_s(
+     riscv_instr_name_t.DIVU, // instr_name
+     riscv_instr_name_t.DIVU, // orig_name
+     0xfe00707f, // mask
+     0x2005033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_m], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // DIVU
+  riscv_instr_param_s(
+     riscv_instr_name_t.DIVUW, // instr_name
+     riscv_instr_name_t.DIVUW, // orig_name
+     0xfe00707f, // mask
+     0x200503b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_m], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // DIVUW
+  riscv_instr_param_s(
+     riscv_instr_name_t.DIVW, // instr_name
+     riscv_instr_name_t.DIVW, // orig_name
+     0xfe00707f, // mask
+     0x200403b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_m], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // DIVW
+  riscv_instr_param_s(
+     riscv_instr_name_t.DRET, // instr_name
+     riscv_instr_name_t.DRET, // orig_name
+     0xffffffff, // mask
+     0x7b200073, // match
+     [], // variables
+     [riscv_extention_t.rv_sdext], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // DRET
+  riscv_instr_param_s(
+     riscv_instr_name_t.EBREAK, // instr_name
+     riscv_instr_name_t.EBREAK, // orig_name
+     0xffffffff, // mask
+     0x100073, // match
+     [], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // EBREAK
+  riscv_instr_param_s(
+     riscv_instr_name_t.ECALL, // instr_name
+     riscv_instr_name_t.ECALL, // orig_name
+     0xffffffff, // mask
+     0x73, // match
+     [], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ECALL
+  riscv_instr_param_s(
+     riscv_instr_name_t.FADD_D, // instr_name
+     riscv_instr_name_t.FADD_D, // orig_name
+     0xfe00007f, // mask
+     0x2000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FADD_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FADD_S, // instr_name
+     riscv_instr_name_t.FADD_S, // orig_name
+     0xfe00007f, // mask
+     0x53, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FADD_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCLASS_D, // instr_name
+     riscv_instr_name_t.FCLASS_D, // orig_name
+     0xfff0707f, // mask
+     0xe2001053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCLASS_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCLASS_S, // instr_name
+     riscv_instr_name_t.FCLASS_S, // orig_name
+     0xfff0707f, // mask
+     0xe0001053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCLASS_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_D_L, // instr_name
+     riscv_instr_name_t.FCVT_D_L, // orig_name
+     0xfff0007f, // mask
+     0xd2200053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv64_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_D_L
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_D_LU, // instr_name
+     riscv_instr_name_t.FCVT_D_LU, // orig_name
+     0xfff0007f, // mask
+     0xd2300053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv64_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_D_LU
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_D_S, // instr_name
+     riscv_instr_name_t.FCVT_D_S, // orig_name
+     0xfff0007f, // mask
+     0x42000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_D_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_D_W, // instr_name
+     riscv_instr_name_t.FCVT_D_W, // orig_name
+     0xfff0007f, // mask
+     0xd2000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_D_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_D_WU, // instr_name
+     riscv_instr_name_t.FCVT_D_WU, // orig_name
+     0xfff0007f, // mask
+     0xd2100053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_D_WU
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_L_D, // instr_name
+     riscv_instr_name_t.FCVT_L_D, // orig_name
+     0xfff0007f, // mask
+     0xc2200053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv64_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_L_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_L_S, // instr_name
+     riscv_instr_name_t.FCVT_L_S, // orig_name
+     0xfff0007f, // mask
+     0xc0200053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv64_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_L_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_LU_D, // instr_name
+     riscv_instr_name_t.FCVT_LU_D, // orig_name
+     0xfff0007f, // mask
+     0xc2300053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv64_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_LU_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_LU_S, // instr_name
+     riscv_instr_name_t.FCVT_LU_S, // orig_name
+     0xfff0007f, // mask
+     0xc0300053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv64_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_LU_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_S_D, // instr_name
+     riscv_instr_name_t.FCVT_S_D, // orig_name
+     0xfff0007f, // mask
+     0x40100053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_S_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_S_L, // instr_name
+     riscv_instr_name_t.FCVT_S_L, // orig_name
+     0xfff0007f, // mask
+     0xd0200053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv64_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_S_L
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_S_LU, // instr_name
+     riscv_instr_name_t.FCVT_S_LU, // orig_name
+     0xfff0007f, // mask
+     0xd0300053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv64_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_S_LU
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_S_W, // instr_name
+     riscv_instr_name_t.FCVT_S_W, // orig_name
+     0xfff0007f, // mask
+     0xd0000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_S_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_S_WU, // instr_name
+     riscv_instr_name_t.FCVT_S_WU, // orig_name
+     0xfff0007f, // mask
+     0xd0100053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_S_WU
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_W_D, // instr_name
+     riscv_instr_name_t.FCVT_W_D, // orig_name
+     0xfff0007f, // mask
+     0xc2000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_W_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_W_S, // instr_name
+     riscv_instr_name_t.FCVT_W_S, // orig_name
+     0xfff0007f, // mask
+     0xc0000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_W_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_WU_D, // instr_name
+     riscv_instr_name_t.FCVT_WU_D, // orig_name
+     0xfff0007f, // mask
+     0xc2100053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_WU_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FCVT_WU_S, // instr_name
+     riscv_instr_name_t.FCVT_WU_S, // orig_name
+     0xfff0007f, // mask
+     0xc0100053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FCVT_WU_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FDIV_D, // instr_name
+     riscv_instr_name_t.FDIV_D, // orig_name
+     0xfe00007f, // mask
+     0x1a000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FDIV_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FDIV_S, // instr_name
+     riscv_instr_name_t.FDIV_S, // orig_name
+     0xfe00007f, // mask
+     0x18000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FDIV_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FENCE, // instr_name
+     riscv_instr_name_t.FENCE, // orig_name
+     0x707f, // mask
+     0xf, // match
+     [riscv_instr_var_t.fm, riscv_instr_var_t.pred, riscv_instr_var_t.succ, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11100000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FENCE
+  riscv_instr_param_s(
+     riscv_instr_name_t.FENCE_I, // instr_name
+     riscv_instr_name_t.FENCE_I, // orig_name
+     0x707f, // mask
+     0x100f, // match
+     [riscv_instr_var_t.imm12, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zifencei], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FENCE_I
+  riscv_instr_param_s(
+     riscv_instr_name_t.FENCE_TSO, // instr_name
+     riscv_instr_name_t.FENCE, // orig_name
+     0xfff0707f, // mask
+     0x8330000f, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FENCE_TSO
+  riscv_instr_param_s(
+     riscv_instr_name_t.FEQ_D, // instr_name
+     riscv_instr_name_t.FEQ_D, // orig_name
+     0xfe00707f, // mask
+     0xa2002053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FEQ_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FEQ_S, // instr_name
+     riscv_instr_name_t.FEQ_S, // orig_name
+     0xfe00707f, // mask
+     0xa0002053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FEQ_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FLD, // instr_name
+     riscv_instr_name_t.FLD, // orig_name
+     0x707f, // mask
+     0x3007, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FLD
+  riscv_instr_param_s(
+     riscv_instr_name_t.FLE_D, // instr_name
+     riscv_instr_name_t.FLE_D, // orig_name
+     0xfe00707f, // mask
+     0xa2000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FLE_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FLE_S, // instr_name
+     riscv_instr_name_t.FLE_S, // orig_name
+     0xfe00707f, // mask
+     0xa0000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FLE_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FLT_D, // instr_name
+     riscv_instr_name_t.FLT_D, // orig_name
+     0xfe00707f, // mask
+     0xa2001053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FLT_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FLT_S, // instr_name
+     riscv_instr_name_t.FLT_S, // orig_name
+     0xfe00707f, // mask
+     0xa0001053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FLT_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FLW, // instr_name
+     riscv_instr_name_t.FLW, // orig_name
+     0x707f, // mask
+     0x2007, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FLW
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMADD_D, // instr_name
+     riscv_instr_name_t.FMADD_D, // orig_name
+     0x600007f, // mask
+     0x2000043, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000011101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMADD_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMADD_S, // instr_name
+     riscv_instr_name_t.FMADD_S, // orig_name
+     0x600007f, // mask
+     0x43, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000011101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMADD_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMAX_D, // instr_name
+     riscv_instr_name_t.FMAX_D, // orig_name
+     0xfe00707f, // mask
+     0x2a001053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMAX_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMAX_S, // instr_name
+     riscv_instr_name_t.FMAX_S, // orig_name
+     0xfe00707f, // mask
+     0x28001053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMAX_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMIN_D, // instr_name
+     riscv_instr_name_t.FMIN_D, // orig_name
+     0xfe00707f, // mask
+     0x2a000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMIN_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMIN_S, // instr_name
+     riscv_instr_name_t.FMIN_S, // orig_name
+     0xfe00707f, // mask
+     0x28000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMIN_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMSUB_D, // instr_name
+     riscv_instr_name_t.FMSUB_D, // orig_name
+     0x600007f, // mask
+     0x2000047, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000011101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMSUB_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMSUB_S, // instr_name
+     riscv_instr_name_t.FMSUB_S, // orig_name
+     0x600007f, // mask
+     0x47, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000011101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMSUB_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMUL_D, // instr_name
+     riscv_instr_name_t.FMUL_D, // orig_name
+     0xfe00007f, // mask
+     0x12000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMUL_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMUL_S, // instr_name
+     riscv_instr_name_t.FMUL_S, // orig_name
+     0xfe00007f, // mask
+     0x10000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMUL_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMV_D_X, // instr_name
+     riscv_instr_name_t.FMV_D_X, // orig_name
+     0xfff0707f, // mask
+     0xf2000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv64_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMV_D_X
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMV_S_X, // instr_name
+     riscv_instr_name_t.FMV_W_X, // orig_name
+     0xfff0707f, // mask
+     0xf0000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMV_S_X
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMV_W_X, // instr_name
+     riscv_instr_name_t.FMV_W_X, // orig_name
+     0xfff0707f, // mask
+     0xf0000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMV_W_X
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMV_X_D, // instr_name
+     riscv_instr_name_t.FMV_X_D, // orig_name
+     0xfff0707f, // mask
+     0xe2000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv64_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMV_X_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMV_X_S, // instr_name
+     riscv_instr_name_t.FMV_X_W, // orig_name
+     0xfff0707f, // mask
+     0xe0000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMV_X_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FMV_X_W, // instr_name
+     riscv_instr_name_t.FMV_X_W, // orig_name
+     0xfff0707f, // mask
+     0xe0000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FMV_X_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.FNMADD_D, // instr_name
+     riscv_instr_name_t.FNMADD_D, // orig_name
+     0x600007f, // mask
+     0x200004f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000011101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FNMADD_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FNMADD_S, // instr_name
+     riscv_instr_name_t.FNMADD_S, // orig_name
+     0x600007f, // mask
+     0x4f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000011101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FNMADD_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FNMSUB_D, // instr_name
+     riscv_instr_name_t.FNMSUB_D, // orig_name
+     0x600007f, // mask
+     0x200004b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000011101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FNMSUB_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FNMSUB_S, // instr_name
+     riscv_instr_name_t.FNMSUB_S, // orig_name
+     0x600007f, // mask
+     0x4b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000011101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FNMSUB_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FRCSR, // instr_name
+     riscv_instr_name_t.CSRRS, // orig_name
+     0xfffff07f, // mask
+     0x302073, // match
+     [riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FRCSR
+  riscv_instr_param_s(
+     riscv_instr_name_t.FRFLAGS, // instr_name
+     riscv_instr_name_t.CSRRS, // orig_name
+     0xfffff07f, // mask
+     0x102073, // match
+     [riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FRFLAGS
+  riscv_instr_param_s(
+     riscv_instr_name_t.FRRM, // instr_name
+     riscv_instr_name_t.CSRRS, // orig_name
+     0xfffff07f, // mask
+     0x202073, // match
+     [riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FRRM
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSCSR, // instr_name
+     riscv_instr_name_t.CSRRW, // orig_name
+     0xfff0707f, // mask
+     0x301073, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSCSR
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSD, // instr_name
+     riscv_instr_name_t.FSD, // orig_name
+     0x707f, // mask
+     0x3027, // match
+     [riscv_instr_var_t.imm12hi, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.imm12lo], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b101000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSD
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSFLAGS, // instr_name
+     riscv_instr_name_t.CSRRW, // orig_name
+     0xfff0707f, // mask
+     0x101073, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSFLAGS
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSFLAGSI, // instr_name
+     riscv_instr_name_t.CSRRWI, // orig_name
+     0xfff0707f, // mask
+     0x105073, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.zimm], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b1000000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSFLAGSI
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSGNJ_D, // instr_name
+     riscv_instr_name_t.FSGNJ_D, // orig_name
+     0xfe00707f, // mask
+     0x22000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSGNJ_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSGNJ_S, // instr_name
+     riscv_instr_name_t.FSGNJ_S, // orig_name
+     0xfe00707f, // mask
+     0x20000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSGNJ_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSGNJN_D, // instr_name
+     riscv_instr_name_t.FSGNJN_D, // orig_name
+     0xfe00707f, // mask
+     0x22001053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSGNJN_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSGNJN_S, // instr_name
+     riscv_instr_name_t.FSGNJN_S, // orig_name
+     0xfe00707f, // mask
+     0x20001053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSGNJN_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSGNJX_D, // instr_name
+     riscv_instr_name_t.FSGNJX_D, // orig_name
+     0xfe00707f, // mask
+     0x22002053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSGNJX_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSGNJX_S, // instr_name
+     riscv_instr_name_t.FSGNJX_S, // orig_name
+     0xfe00707f, // mask
+     0x20002053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSGNJX_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSL, // instr_name
+     riscv_instr_name_t.FSL, // orig_name
+     0x600707f, // mask
+     0x4001033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3], // variables
+     [riscv_extention_t.rv_zbt], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSL
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSLW, // instr_name
+     riscv_instr_name_t.FSLW, // orig_name
+     0x600707f, // mask
+     0x400103b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3], // variables
+     [riscv_extention_t.rv64_zbt], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSLW
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSQRT_D, // instr_name
+     riscv_instr_name_t.FSQRT_D, // orig_name
+     0xfff0007f, // mask
+     0x5a000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSQRT_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSQRT_S, // instr_name
+     riscv_instr_name_t.FSQRT_S, // orig_name
+     0xfff0007f, // mask
+     0x58000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSQRT_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSR, // instr_name
+     riscv_instr_name_t.FSR, // orig_name
+     0x600707f, // mask
+     0x4005033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3], // variables
+     [riscv_extention_t.rv_zbt, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSR
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSRI, // instr_name
+     riscv_instr_name_t.FSRI, // orig_name
+     0x400707f, // mask
+     0x4005013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs3, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv64_zbt], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000010101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSRI
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSRIW, // instr_name
+     riscv_instr_name_t.FSRIW, // orig_name
+     0x600707f, // mask
+     0x400501b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs3, riscv_instr_var_t.shamtw], // variables
+     [riscv_extention_t.rv64_zbt], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b10000000000010101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSRIW
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSRM, // instr_name
+     riscv_instr_name_t.CSRRW, // orig_name
+     0xfff0707f, // mask
+     0x201073, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSRM
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSRMI, // instr_name
+     riscv_instr_name_t.CSRRWI, // orig_name
+     0xfff0707f, // mask
+     0x205073, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.zimm], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b1000000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSRMI
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSRW, // instr_name
+     riscv_instr_name_t.FSRW, // orig_name
+     0x600707f, // mask
+     0x400503b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rs3], // variables
+     [riscv_extention_t.rv64_zbt, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSRW
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSUB_D, // instr_name
+     riscv_instr_name_t.FSUB_D, // orig_name
+     0xfe00007f, // mask
+     0xa000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_d], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSUB_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSUB_S, // instr_name
+     riscv_instr_name_t.FSUB_S, // orig_name
+     0xfe00007f, // mask
+     0x8000053, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.rm], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100000001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSUB_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.FSW, // instr_name
+     riscv_instr_name_t.FSW, // orig_name
+     0x707f, // mask
+     0x2027, // match
+     [riscv_instr_var_t.imm12hi, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.imm12lo], // variables
+     [riscv_extention_t.rv_f], // extentions
+     0b101000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // FSW
+  riscv_instr_param_s(
+     riscv_instr_name_t.GORC, // instr_name
+     riscv_instr_name_t.GORC, // orig_name
+     0xfe00707f, // mask
+     0x28005033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // GORC
+  riscv_instr_param_s(
+     riscv_instr_name_t.GORCI, // instr_name
+     riscv_instr_name_t.GORCI, // orig_name
+     0xfc00707f, // mask
+     0x28005013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv64_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // GORCI
+  riscv_instr_param_s(
+     riscv_instr_name_t.GORCIW, // instr_name
+     riscv_instr_name_t.GORCIW, // orig_name
+     0xfe00707f, // mask
+     0x2800501b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtw], // variables
+     [riscv_extention_t.rv64_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b10000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // GORCIW
+  riscv_instr_param_s(
+     riscv_instr_name_t.GORCW, // instr_name
+     riscv_instr_name_t.GORCW, // orig_name
+     0xfe00707f, // mask
+     0x2800503b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // GORCW
+  riscv_instr_param_s(
+     riscv_instr_name_t.GREV, // instr_name
+     riscv_instr_name_t.GREV, // orig_name
+     0xfe00707f, // mask
+     0x68005033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // GREV
+  riscv_instr_param_s(
+     riscv_instr_name_t.GREVI, // instr_name
+     riscv_instr_name_t.GREVI, // orig_name
+     0xfc00707f, // mask
+     0x68005013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv64_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // GREVI
+  riscv_instr_param_s(
+     riscv_instr_name_t.GREVIW, // instr_name
+     riscv_instr_name_t.GREVIW, // orig_name
+     0xfe00707f, // mask
+     0x6800501b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtw], // variables
+     [riscv_extention_t.rv64_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b10000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // GREVIW
+  riscv_instr_param_s(
+     riscv_instr_name_t.GREVW, // instr_name
+     riscv_instr_name_t.GREVW, // orig_name
+     0xfe00707f, // mask
+     0x6800503b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // GREVW
+  riscv_instr_param_s(
+     riscv_instr_name_t.INSB, // instr_name
+     riscv_instr_name_t.INSB, // orig_name
+     0xff80707f, // mask
+     0xac000077, // match
+     [riscv_instr_var_t.imm3, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b100000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // INSB
+  riscv_instr_param_s(
+     riscv_instr_name_t.JAL, // instr_name
+     riscv_instr_name_t.JAL, // orig_name
+     0x7f, // mask
+     0x6f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.jimm20], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b10, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // JAL
+  riscv_instr_param_s(
+     riscv_instr_name_t.JALR, // instr_name
+     riscv_instr_name_t.JALR, // orig_name
+     0x707f, // mask
+     0x67, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // JALR
+  riscv_instr_param_s(
+     riscv_instr_name_t.KABS16, // instr_name
+     riscv_instr_name_t.KABS16, // orig_name
+     0xfff0707f, // mask
+     0xad100077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KABS16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KABS32, // instr_name
+     riscv_instr_name_t.KABS32, // orig_name
+     0xfff0707f, // mask
+     0xad200077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KABS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KABS8, // instr_name
+     riscv_instr_name_t.KABS8, // orig_name
+     0xfff0707f, // mask
+     0xad000077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KABS8
+  riscv_instr_param_s(
+     riscv_instr_name_t.KABSW, // instr_name
+     riscv_instr_name_t.KABSW, // orig_name
+     0xfff0707f, // mask
+     0xad400077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KABSW
+  riscv_instr_param_s(
+     riscv_instr_name_t.KADD16, // instr_name
+     riscv_instr_name_t.KADD16, // orig_name
+     0xfe00707f, // mask
+     0x10000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KADD16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KADD32, // instr_name
+     riscv_instr_name_t.KADD32, // orig_name
+     0xfe00707f, // mask
+     0x10002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KADD32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KADD8, // instr_name
+     riscv_instr_name_t.KADD8, // orig_name
+     0xfe00707f, // mask
+     0x18000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KADD8
+  riscv_instr_param_s(
+     riscv_instr_name_t.KADDH, // instr_name
+     riscv_instr_name_t.KADDH, // orig_name
+     0xfe00707f, // mask
+     0x4001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KADDH
+  riscv_instr_param_s(
+     riscv_instr_name_t.KADDW, // instr_name
+     riscv_instr_name_t.KADDW, // orig_name
+     0xfe00707f, // mask
+     0x1077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KADDW
+  riscv_instr_param_s(
+     riscv_instr_name_t.KCRAS16, // instr_name
+     riscv_instr_name_t.KCRAS16, // orig_name
+     0xfe00707f, // mask
+     0x14000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KCRAS16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KCRAS32, // instr_name
+     riscv_instr_name_t.KCRAS32, // orig_name
+     0xfe00707f, // mask
+     0x14002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KCRAS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KCRSA16, // instr_name
+     riscv_instr_name_t.KCRSA16, // orig_name
+     0xfe00707f, // mask
+     0x16000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KCRSA16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KCRSA32, // instr_name
+     riscv_instr_name_t.KCRSA32, // orig_name
+     0xfe00707f, // mask
+     0x16002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KCRSA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KDMABB, // instr_name
+     riscv_instr_name_t.KDMABB, // orig_name
+     0xfe00707f, // mask
+     0xd2001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KDMABB
+  riscv_instr_param_s(
+     riscv_instr_name_t.KDMABB16, // instr_name
+     riscv_instr_name_t.KDMABB16, // orig_name
+     0xfe00707f, // mask
+     0xd8001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KDMABB16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KDMABT, // instr_name
+     riscv_instr_name_t.KDMABT, // orig_name
+     0xfe00707f, // mask
+     0xe2001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KDMABT
+  riscv_instr_param_s(
+     riscv_instr_name_t.KDMABT16, // instr_name
+     riscv_instr_name_t.KDMABT16, // orig_name
+     0xfe00707f, // mask
+     0xe8001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KDMABT16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KDMATT, // instr_name
+     riscv_instr_name_t.KDMATT, // orig_name
+     0xfe00707f, // mask
+     0xf2001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KDMATT
+  riscv_instr_param_s(
+     riscv_instr_name_t.KDMATT16, // instr_name
+     riscv_instr_name_t.KDMATT16, // orig_name
+     0xfe00707f, // mask
+     0xf8001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KDMATT16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KDMBB, // instr_name
+     riscv_instr_name_t.KDMBB, // orig_name
+     0xfe00707f, // mask
+     0xa001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KDMBB
+  riscv_instr_param_s(
+     riscv_instr_name_t.KDMBB16, // instr_name
+     riscv_instr_name_t.KDMBB16, // orig_name
+     0xfe00707f, // mask
+     0xda001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KDMBB16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KDMBT, // instr_name
+     riscv_instr_name_t.KDMBT, // orig_name
+     0xfe00707f, // mask
+     0x1a001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KDMBT
+  riscv_instr_param_s(
+     riscv_instr_name_t.KDMBT16, // instr_name
+     riscv_instr_name_t.KDMBT16, // orig_name
+     0xfe00707f, // mask
+     0xea001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KDMBT16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KDMTT, // instr_name
+     riscv_instr_name_t.KDMTT, // orig_name
+     0xfe00707f, // mask
+     0x2a001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KDMTT
+  riscv_instr_param_s(
+     riscv_instr_name_t.KDMTT16, // instr_name
+     riscv_instr_name_t.KDMTT16, // orig_name
+     0xfe00707f, // mask
+     0xfa001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KDMTT16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KHM16, // instr_name
+     riscv_instr_name_t.KHM16, // orig_name
+     0xfe00707f, // mask
+     0x86000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KHM16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KHM8, // instr_name
+     riscv_instr_name_t.KHM8, // orig_name
+     0xfe00707f, // mask
+     0x8e000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KHM8
+  riscv_instr_param_s(
+     riscv_instr_name_t.KHMBB, // instr_name
+     riscv_instr_name_t.KHMBB, // orig_name
+     0xfe00707f, // mask
+     0xc001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KHMBB
+  riscv_instr_param_s(
+     riscv_instr_name_t.KHMBB16, // instr_name
+     riscv_instr_name_t.KHMBB16, // orig_name
+     0xfe00707f, // mask
+     0xdc001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KHMBB16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KHMBT, // instr_name
+     riscv_instr_name_t.KHMBT, // orig_name
+     0xfe00707f, // mask
+     0x1c001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KHMBT
+  riscv_instr_param_s(
+     riscv_instr_name_t.KHMBT16, // instr_name
+     riscv_instr_name_t.KHMBT16, // orig_name
+     0xfe00707f, // mask
+     0xec001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KHMBT16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KHMTT, // instr_name
+     riscv_instr_name_t.KHMTT, // orig_name
+     0xfe00707f, // mask
+     0x2c001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KHMTT
+  riscv_instr_param_s(
+     riscv_instr_name_t.KHMTT16, // instr_name
+     riscv_instr_name_t.KHMTT16, // orig_name
+     0xfe00707f, // mask
+     0xfc001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KHMTT16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KHMX16, // instr_name
+     riscv_instr_name_t.KHMX16, // orig_name
+     0xfe00707f, // mask
+     0x96000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KHMX16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KHMX8, // instr_name
+     riscv_instr_name_t.KHMX8, // orig_name
+     0xfe00707f, // mask
+     0x9e000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KHMX8
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMABB, // instr_name
+     riscv_instr_name_t.KMABB, // orig_name
+     0xfe00707f, // mask
+     0x5a001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMABB
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMABB32, // instr_name
+     riscv_instr_name_t.KMABB32, // orig_name
+     0xfe00707f, // mask
+     0x5a002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMABB32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMABT, // instr_name
+     riscv_instr_name_t.KMABT, // orig_name
+     0xfe00707f, // mask
+     0x6a001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMABT
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMABT32, // instr_name
+     riscv_instr_name_t.KMABT32, // orig_name
+     0xfe00707f, // mask
+     0x6a002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMABT32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMADA, // instr_name
+     riscv_instr_name_t.KMADA, // orig_name
+     0xfe00707f, // mask
+     0x48001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMADA
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMADRS, // instr_name
+     riscv_instr_name_t.KMADRS, // orig_name
+     0xfe00707f, // mask
+     0x6c001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMADRS
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMADRS32, // instr_name
+     riscv_instr_name_t.KMADRS32, // orig_name
+     0xfe00707f, // mask
+     0x6c002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMADRS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMADS, // instr_name
+     riscv_instr_name_t.KMADS, // orig_name
+     0xfe00707f, // mask
+     0x5c001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMADS
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMADS32, // instr_name
+     riscv_instr_name_t.KMADS32, // orig_name
+     0xfe00707f, // mask
+     0x5c002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMADS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMATT, // instr_name
+     riscv_instr_name_t.KMATT, // orig_name
+     0xfe00707f, // mask
+     0x7a001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMATT
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMATT32, // instr_name
+     riscv_instr_name_t.KMATT32, // orig_name
+     0xfe00707f, // mask
+     0x7a002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMATT32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMAXDA, // instr_name
+     riscv_instr_name_t.KMAXDA, // orig_name
+     0xfe00707f, // mask
+     0x4a001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMAXDA
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMAXDA32, // instr_name
+     riscv_instr_name_t.KMAXDA32, // orig_name
+     0xfe00707f, // mask
+     0x4a002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMAXDA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMAXDS, // instr_name
+     riscv_instr_name_t.KMAXDS, // orig_name
+     0xfe00707f, // mask
+     0x7c001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMAXDS
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMAXDS32, // instr_name
+     riscv_instr_name_t.KMAXDS32, // orig_name
+     0xfe00707f, // mask
+     0x7c002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMAXDS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMDA, // instr_name
+     riscv_instr_name_t.KMDA, // orig_name
+     0xfe00707f, // mask
+     0x38001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMDA
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMDA32, // instr_name
+     riscv_instr_name_t.KMDA32, // orig_name
+     0xfe00707f, // mask
+     0x38002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMDA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMAC, // instr_name
+     riscv_instr_name_t.KMMAC, // orig_name
+     0xfe00707f, // mask
+     0x60001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMAC
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMAC_U, // instr_name
+     riscv_instr_name_t.KMMAC_U, // orig_name
+     0xfe00707f, // mask
+     0x70001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMAC_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMAWB, // instr_name
+     riscv_instr_name_t.KMMAWB, // orig_name
+     0xfe00707f, // mask
+     0x46001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMAWB
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMAWB2, // instr_name
+     riscv_instr_name_t.KMMAWB2, // orig_name
+     0xfe00707f, // mask
+     0xce001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMAWB2
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMAWB2_U, // instr_name
+     riscv_instr_name_t.KMMAWB2_U, // orig_name
+     0xfe00707f, // mask
+     0xde001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMAWB2_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMAWB_U, // instr_name
+     riscv_instr_name_t.KMMAWB_U, // orig_name
+     0xfe00707f, // mask
+     0x56001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMAWB_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMAWT, // instr_name
+     riscv_instr_name_t.KMMAWT, // orig_name
+     0xfe00707f, // mask
+     0x66001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMAWT
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMAWT2, // instr_name
+     riscv_instr_name_t.KMMAWT2, // orig_name
+     0xfe00707f, // mask
+     0xee001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMAWT2
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMAWT2_U, // instr_name
+     riscv_instr_name_t.KMMAWT2_U, // orig_name
+     0xfe00707f, // mask
+     0xfe001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMAWT2_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMAWT_U, // instr_name
+     riscv_instr_name_t.KMMAWT_U, // orig_name
+     0xfe00707f, // mask
+     0x76001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMAWT_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMSB, // instr_name
+     riscv_instr_name_t.KMMSB, // orig_name
+     0xfe00707f, // mask
+     0x42001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMSB
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMSB_U, // instr_name
+     riscv_instr_name_t.KMMSB_U, // orig_name
+     0xfe00707f, // mask
+     0x52001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMSB_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMWB2, // instr_name
+     riscv_instr_name_t.KMMWB2, // orig_name
+     0xfe00707f, // mask
+     0x8e001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMWB2
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMWB2_U, // instr_name
+     riscv_instr_name_t.KMMWB2_U, // orig_name
+     0xfe00707f, // mask
+     0x9e001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMWB2_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMWT2, // instr_name
+     riscv_instr_name_t.KMMWT2, // orig_name
+     0xfe00707f, // mask
+     0xae001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMWT2
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMMWT2_U, // instr_name
+     riscv_instr_name_t.KMMWT2_U, // orig_name
+     0xfe00707f, // mask
+     0xbe001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMMWT2_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMSDA, // instr_name
+     riscv_instr_name_t.KMSDA, // orig_name
+     0xfe00707f, // mask
+     0x4c001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMSDA
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMSDA32, // instr_name
+     riscv_instr_name_t.KMSDA32, // orig_name
+     0xfe00707f, // mask
+     0x4c002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMSDA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMSXDA, // instr_name
+     riscv_instr_name_t.KMSXDA, // orig_name
+     0xfe00707f, // mask
+     0x4e001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMSXDA
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMSXDA32, // instr_name
+     riscv_instr_name_t.KMSXDA32, // orig_name
+     0xfe00707f, // mask
+     0x4e002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMSXDA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMXDA, // instr_name
+     riscv_instr_name_t.KMXDA, // orig_name
+     0xfe00707f, // mask
+     0x3a001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMXDA
+  riscv_instr_param_s(
+     riscv_instr_name_t.KMXDA32, // instr_name
+     riscv_instr_name_t.KMXDA32, // orig_name
+     0xfe00707f, // mask
+     0x3a002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KMXDA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLL16, // instr_name
+     riscv_instr_name_t.KSLL16, // orig_name
+     0xfe00707f, // mask
+     0x64000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLL16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLL32, // instr_name
+     riscv_instr_name_t.KSLL32, // orig_name
+     0xfe00707f, // mask
+     0x64002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLL32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLL8, // instr_name
+     riscv_instr_name_t.KSLL8, // orig_name
+     0xfe00707f, // mask
+     0x6c000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLL8
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLLI16, // instr_name
+     riscv_instr_name_t.KSLLI16, // orig_name
+     0xff00707f, // mask
+     0x75000077, // match
+     [riscv_instr_var_t.imm4, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b1000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLLI16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLLI32, // instr_name
+     riscv_instr_name_t.KSLLI32, // orig_name
+     0xfe00707f, // mask
+     0x84002077, // match
+     [riscv_instr_var_t.imm5, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b10000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLLI32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLLI8, // instr_name
+     riscv_instr_name_t.KSLLI8, // orig_name
+     0xff80707f, // mask
+     0x7c800077, // match
+     [riscv_instr_var_t.imm3, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b100000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLLI8
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLLIW, // instr_name
+     riscv_instr_name_t.KSLLIW, // orig_name
+     0xfe00707f, // mask
+     0x36001077, // match
+     [riscv_instr_var_t.imm5, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b10000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLLIW
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLLW, // instr_name
+     riscv_instr_name_t.KSLLW, // orig_name
+     0xfe00707f, // mask
+     0x26001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLLW
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLRA16, // instr_name
+     riscv_instr_name_t.KSLRA16, // orig_name
+     0xfe00707f, // mask
+     0x56000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLRA16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLRA16_U, // instr_name
+     riscv_instr_name_t.KSLRA16_U, // orig_name
+     0xfe00707f, // mask
+     0x66000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLRA16_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLRA32, // instr_name
+     riscv_instr_name_t.KSLRA32, // orig_name
+     0xfe00707f, // mask
+     0x56002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLRA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLRA32_U, // instr_name
+     riscv_instr_name_t.KSLRA32_U, // orig_name
+     0xfe00707f, // mask
+     0x66002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLRA32_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLRA8, // instr_name
+     riscv_instr_name_t.KSLRA8, // orig_name
+     0xfe00707f, // mask
+     0x5e000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLRA8
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLRA8_U, // instr_name
+     riscv_instr_name_t.KSLRA8_U, // orig_name
+     0xfe00707f, // mask
+     0x6e000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLRA8_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLRAW, // instr_name
+     riscv_instr_name_t.KSLRAW, // orig_name
+     0xfe00707f, // mask
+     0x6e001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLRAW
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSLRAW_U, // instr_name
+     riscv_instr_name_t.KSLRAW_U, // orig_name
+     0xfe00707f, // mask
+     0x7e001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSLRAW_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSTAS16, // instr_name
+     riscv_instr_name_t.KSTAS16, // orig_name
+     0xfe00707f, // mask
+     0xc4002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSTAS16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSTAS32, // instr_name
+     riscv_instr_name_t.KSTAS32, // orig_name
+     0xfe00707f, // mask
+     0xc0002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSTAS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSTSA16, // instr_name
+     riscv_instr_name_t.KSTSA16, // orig_name
+     0xfe00707f, // mask
+     0xc6002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSTSA16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSTSA32, // instr_name
+     riscv_instr_name_t.KSTSA32, // orig_name
+     0xfe00707f, // mask
+     0xc2002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSTSA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSUB16, // instr_name
+     riscv_instr_name_t.KSUB16, // orig_name
+     0xfe00707f, // mask
+     0x12000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSUB16
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSUB32, // instr_name
+     riscv_instr_name_t.KSUB32, // orig_name
+     0xfe00707f, // mask
+     0x12002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSUB32
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSUB8, // instr_name
+     riscv_instr_name_t.KSUB8, // orig_name
+     0xfe00707f, // mask
+     0x1a000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSUB8
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSUBH, // instr_name
+     riscv_instr_name_t.KSUBH, // orig_name
+     0xfe00707f, // mask
+     0x6001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSUBH
+  riscv_instr_param_s(
+     riscv_instr_name_t.KSUBW, // instr_name
+     riscv_instr_name_t.KSUBW, // orig_name
+     0xfe00707f, // mask
+     0x2001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KSUBW
+  riscv_instr_param_s(
+     riscv_instr_name_t.KWMMUL, // instr_name
+     riscv_instr_name_t.KWMMUL, // orig_name
+     0xfe00707f, // mask
+     0x62001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KWMMUL
+  riscv_instr_param_s(
+     riscv_instr_name_t.KWMMUL_U, // instr_name
+     riscv_instr_name_t.KWMMUL_U, // orig_name
+     0xfe00707f, // mask
+     0x72001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // KWMMUL_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.LB, // instr_name
+     riscv_instr_name_t.LB, // orig_name
+     0x707f, // mask
+     0x3, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // LB
+  riscv_instr_param_s(
+     riscv_instr_name_t.LBU, // instr_name
+     riscv_instr_name_t.LBU, // orig_name
+     0x707f, // mask
+     0x4003, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // LBU
+  riscv_instr_param_s(
+     riscv_instr_name_t.LD, // instr_name
+     riscv_instr_name_t.LD, // orig_name
+     0x707f, // mask
+     0x3003, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // LD
+  riscv_instr_param_s(
+     riscv_instr_name_t.LH, // instr_name
+     riscv_instr_name_t.LH, // orig_name
+     0x707f, // mask
+     0x1003, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // LH
+  riscv_instr_param_s(
+     riscv_instr_name_t.LHU, // instr_name
+     riscv_instr_name_t.LHU, // orig_name
+     0x707f, // mask
+     0x5003, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // LHU
+  riscv_instr_param_s(
+     riscv_instr_name_t.LR_D, // instr_name
+     riscv_instr_name_t.LR_D, // orig_name
+     0xf9f0707f, // mask
+     0x1000302f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv64_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // LR_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.LR_W, // instr_name
+     riscv_instr_name_t.LR_W, // orig_name
+     0xf9f0707f, // mask
+     0x1000202f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // LR_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.LUI, // instr_name
+     riscv_instr_name_t.LUI, // orig_name
+     0x7f, // mask
+     0x37, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.imm20], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b1, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // LUI
+  riscv_instr_param_s(
+     riscv_instr_name_t.LW, // instr_name
+     riscv_instr_name_t.LW, // orig_name
+     0x707f, // mask
+     0x2003, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // LW
+  riscv_instr_param_s(
+     riscv_instr_name_t.LWU, // instr_name
+     riscv_instr_name_t.LWU, // orig_name
+     0x707f, // mask
+     0x6003, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // LWU
+  riscv_instr_param_s(
+     riscv_instr_name_t.MADDR32, // instr_name
+     riscv_instr_name_t.MADDR32, // orig_name
+     0xfe00707f, // mask
+     0xc4001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // MADDR32
+  riscv_instr_param_s(
+     riscv_instr_name_t.MAX, // instr_name
+     riscv_instr_name_t.MAX, // orig_name
+     0xfe00707f, // mask
+     0xa006033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbb, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // MAX
+  riscv_instr_param_s(
+     riscv_instr_name_t.MAXU, // instr_name
+     riscv_instr_name_t.MAXU, // orig_name
+     0xfe00707f, // mask
+     0xa007033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbb], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // MAXU
+  riscv_instr_param_s(
+     riscv_instr_name_t.MIN, // instr_name
+     riscv_instr_name_t.MIN, // orig_name
+     0xfe00707f, // mask
+     0xa004033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbb, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // MIN
+  riscv_instr_param_s(
+     riscv_instr_name_t.MINU, // instr_name
+     riscv_instr_name_t.MINU, // orig_name
+     0xfe00707f, // mask
+     0xa005033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbb], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // MINU
+  riscv_instr_param_s(
+     riscv_instr_name_t.MRET, // instr_name
+     riscv_instr_name_t.MRET, // orig_name
+     0xffffffff, // mask
+     0x30200073, // match
+     [], // variables
+     [riscv_extention_t.rv_system], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // MRET
+  riscv_instr_param_s(
+     riscv_instr_name_t.MSUBR32, // instr_name
+     riscv_instr_name_t.MSUBR32, // orig_name
+     0xfe00707f, // mask
+     0xc6001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // MSUBR32
+  riscv_instr_param_s(
+     riscv_instr_name_t.MUL, // instr_name
+     riscv_instr_name_t.MUL, // orig_name
+     0xfe00707f, // mask
+     0x2000033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_m], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // MUL
+  riscv_instr_param_s(
+     riscv_instr_name_t.MULH, // instr_name
+     riscv_instr_name_t.MULH, // orig_name
+     0xfe00707f, // mask
+     0x2001033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_m, riscv_extention_t.rv32_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // MULH
+  riscv_instr_param_s(
+     riscv_instr_name_t.MULHSU, // instr_name
+     riscv_instr_name_t.MULHSU, // orig_name
+     0xfe00707f, // mask
+     0x2002033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_m], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // MULHSU
+  riscv_instr_param_s(
+     riscv_instr_name_t.MULHU, // instr_name
+     riscv_instr_name_t.MULHU, // orig_name
+     0xfe00707f, // mask
+     0x2003033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_m], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // MULHU
+  riscv_instr_param_s(
+     riscv_instr_name_t.MULW, // instr_name
+     riscv_instr_name_t.MULW, // orig_name
+     0xfe00707f, // mask
+     0x200003b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_m], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // MULW
+  riscv_instr_param_s(
+     riscv_instr_name_t.NOP, // instr_name
+     riscv_instr_name_t.ADDI, // orig_name
+     0xffffffff, // mask
+     0x13, // match
+     [], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // NOP
+  riscv_instr_param_s(
+     riscv_instr_name_t.OR, // instr_name
+     riscv_instr_name_t.OR, // orig_name
+     0xfe00707f, // mask
+     0x6033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // OR
+  riscv_instr_param_s(
+     riscv_instr_name_t.ORC_B, // instr_name
+     riscv_instr_name_t.GORCI, // orig_name
+     0xfff0707f, // mask
+     0x28705013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zbb], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ORC_B
+  riscv_instr_param_s(
+     riscv_instr_name_t.ORI, // instr_name
+     riscv_instr_name_t.ORI, // orig_name
+     0x707f, // mask
+     0x6013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ORI
+  riscv_instr_param_s(
+     riscv_instr_name_t.ORN, // instr_name
+     riscv_instr_name_t.ORN, // orig_name
+     0xfe00707f, // mask
+     0x40006033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbb, riscv_extention_t.rv_zbp, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ORN
+  riscv_instr_param_s(
+     riscv_instr_name_t.PACK, // instr_name
+     riscv_instr_name_t.PACK, // orig_name
+     0xfe00707f, // mask
+     0x8004033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbe, riscv_extention_t.rv_zbp, riscv_extention_t.rv_zbf, riscv_extention_t.rv64_zbm, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PACK
+  riscv_instr_param_s(
+     riscv_instr_name_t.PACKH, // instr_name
+     riscv_instr_name_t.PACKH, // orig_name
+     0xfe00707f, // mask
+     0x8007033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbe, riscv_extention_t.rv_zbp, riscv_extention_t.rv_zbf, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PACKH
+  riscv_instr_param_s(
+     riscv_instr_name_t.PACKU, // instr_name
+     riscv_instr_name_t.PACKU, // orig_name
+     0xfe00707f, // mask
+     0x48004033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbp, riscv_extention_t.rv64_zbm], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PACKU
+  riscv_instr_param_s(
+     riscv_instr_name_t.PACKUW, // instr_name
+     riscv_instr_name_t.PACKUW, // orig_name
+     0xfe00707f, // mask
+     0x4800403b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PACKUW
+  riscv_instr_param_s(
+     riscv_instr_name_t.PACKW, // instr_name
+     riscv_instr_name_t.PACKW, // orig_name
+     0xfe00707f, // mask
+     0x800403b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbe, riscv_extention_t.rv64_zbp, riscv_extention_t.rv64_zbf, riscv_extention_t.rv64_zks, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PACKW
+  riscv_instr_param_s(
+     riscv_instr_name_t.PAUSE, // instr_name
+     riscv_instr_name_t.FENCE, // orig_name
+     0xffffffff, // mask
+     0x100000f, // match
+     [], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PAUSE
+  riscv_instr_param_s(
+     riscv_instr_name_t.PBSAD, // instr_name
+     riscv_instr_name_t.PBSAD, // orig_name
+     0xfe00707f, // mask
+     0xfc000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PBSAD
+  riscv_instr_param_s(
+     riscv_instr_name_t.PBSADA, // instr_name
+     riscv_instr_name_t.PBSADA, // orig_name
+     0xfe00707f, // mask
+     0xfe000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PBSADA
+  riscv_instr_param_s(
+     riscv_instr_name_t.PKBB16, // instr_name
+     riscv_instr_name_t.PKBB16, // orig_name
+     0xfe00707f, // mask
+     0xe001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PKBB16
+  riscv_instr_param_s(
+     riscv_instr_name_t.PKBT16, // instr_name
+     riscv_instr_name_t.PKBT16, // orig_name
+     0xfe00707f, // mask
+     0x1e001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PKBT16
+  riscv_instr_param_s(
+     riscv_instr_name_t.PKBT32, // instr_name
+     riscv_instr_name_t.PKBT32, // orig_name
+     0xfe00707f, // mask
+     0x1e002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PKBT32
+  riscv_instr_param_s(
+     riscv_instr_name_t.PKTB16, // instr_name
+     riscv_instr_name_t.PKTB16, // orig_name
+     0xfe00707f, // mask
+     0x3e001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PKTB16
+  riscv_instr_param_s(
+     riscv_instr_name_t.PKTB32, // instr_name
+     riscv_instr_name_t.PKTB32, // orig_name
+     0xfe00707f, // mask
+     0x3e002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PKTB32
+  riscv_instr_param_s(
+     riscv_instr_name_t.PKTT16, // instr_name
+     riscv_instr_name_t.PKTT16, // orig_name
+     0xfe00707f, // mask
+     0x2e001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // PKTT16
+  riscv_instr_param_s(
+     riscv_instr_name_t.RADD16, // instr_name
+     riscv_instr_name_t.RADD16, // orig_name
+     0xfe00707f, // mask
+     0x77, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RADD16
+  riscv_instr_param_s(
+     riscv_instr_name_t.RADD32, // instr_name
+     riscv_instr_name_t.RADD32, // orig_name
+     0xfe00707f, // mask
+     0x2077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RADD32
+  riscv_instr_param_s(
+     riscv_instr_name_t.RADD8, // instr_name
+     riscv_instr_name_t.RADD8, // orig_name
+     0xfe00707f, // mask
+     0x8000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RADD8
+  riscv_instr_param_s(
+     riscv_instr_name_t.RADDW, // instr_name
+     riscv_instr_name_t.RADDW, // orig_name
+     0xfe00707f, // mask
+     0x20001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RADDW
+  riscv_instr_param_s(
+     riscv_instr_name_t.RCRAS16, // instr_name
+     riscv_instr_name_t.RCRAS16, // orig_name
+     0xfe00707f, // mask
+     0x4000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RCRAS16
+  riscv_instr_param_s(
+     riscv_instr_name_t.RCRAS32, // instr_name
+     riscv_instr_name_t.RCRAS32, // orig_name
+     0xfe00707f, // mask
+     0x4002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RCRAS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.RCRSA16, // instr_name
+     riscv_instr_name_t.RCRSA16, // orig_name
+     0xfe00707f, // mask
+     0x6000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RCRSA16
+  riscv_instr_param_s(
+     riscv_instr_name_t.RCRSA32, // instr_name
+     riscv_instr_name_t.RCRSA32, // orig_name
+     0xfe00707f, // mask
+     0x6002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RCRSA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.RDCYCLE, // instr_name
+     riscv_instr_name_t.CSRRS, // orig_name
+     0xfffff07f, // mask
+     0xc0002073, // match
+     [riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RDCYCLE
+  riscv_instr_param_s(
+     riscv_instr_name_t.RDCYCLEH, // instr_name
+     riscv_instr_name_t.CSRRS, // orig_name
+     0xfffff07f, // mask
+     0xc8002073, // match
+     [riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RDCYCLEH
+  riscv_instr_param_s(
+     riscv_instr_name_t.RDINSTRET, // instr_name
+     riscv_instr_name_t.CSRRS, // orig_name
+     0xfffff07f, // mask
+     0xc0202073, // match
+     [riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RDINSTRET
+  riscv_instr_param_s(
+     riscv_instr_name_t.RDINSTRETH, // instr_name
+     riscv_instr_name_t.CSRRS, // orig_name
+     0xfffff07f, // mask
+     0xc8202073, // match
+     [riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RDINSTRETH
+  riscv_instr_param_s(
+     riscv_instr_name_t.RDOV, // instr_name
+     riscv_instr_name_t.CSRRS, // orig_name
+     0xfffff07f, // mask
+     0x902073, // match
+     [riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RDOV
+  riscv_instr_param_s(
+     riscv_instr_name_t.RDTIME, // instr_name
+     riscv_instr_name_t.CSRRS, // orig_name
+     0xfffff07f, // mask
+     0xc0102073, // match
+     [riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RDTIME
+  riscv_instr_param_s(
+     riscv_instr_name_t.RDTIMEH, // instr_name
+     riscv_instr_name_t.CSRRS, // orig_name
+     0xfffff07f, // mask
+     0xc8102073, // match
+     [riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zicsr], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RDTIMEH
+  riscv_instr_param_s(
+     riscv_instr_name_t.REM, // instr_name
+     riscv_instr_name_t.REM, // orig_name
+     0xfe00707f, // mask
+     0x2006033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_m], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // REM
+  riscv_instr_param_s(
+     riscv_instr_name_t.REMU, // instr_name
+     riscv_instr_name_t.REMU, // orig_name
+     0xfe00707f, // mask
+     0x2007033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_m], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // REMU
+  riscv_instr_param_s(
+     riscv_instr_name_t.REMUW, // instr_name
+     riscv_instr_name_t.REMUW, // orig_name
+     0xfe00707f, // mask
+     0x200703b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_m], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // REMUW
+  riscv_instr_param_s(
+     riscv_instr_name_t.REMW, // instr_name
+     riscv_instr_name_t.REMW, // orig_name
+     0xfe00707f, // mask
+     0x200603b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_m], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // REMW
+  riscv_instr_param_s(
+     riscv_instr_name_t.REV8, // instr_name
+     riscv_instr_name_t.GREVI, // orig_name
+     0xfff0707f, // mask
+     0x6b805013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv64_zks], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // REV8
+  riscv_instr_param_s(
+     riscv_instr_name_t.ROL, // instr_name
+     riscv_instr_name_t.ROL, // orig_name
+     0xfe00707f, // mask
+     0x60001033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbb, riscv_extention_t.rv_zbp, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ROL
+  riscv_instr_param_s(
+     riscv_instr_name_t.ROLW, // instr_name
+     riscv_instr_name_t.ROLW, // orig_name
+     0xfe00707f, // mask
+     0x6000103b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbb, riscv_extention_t.rv64_zbp, riscv_extention_t.rv64_zks, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ROLW
+  riscv_instr_param_s(
+     riscv_instr_name_t.ROR, // instr_name
+     riscv_instr_name_t.ROR, // orig_name
+     0xfe00707f, // mask
+     0x60005033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbb, riscv_extention_t.rv_zbp, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ROR
+  riscv_instr_param_s(
+     riscv_instr_name_t.RORI, // instr_name
+     riscv_instr_name_t.RORI, // orig_name
+     0xfc00707f, // mask
+     0x60005013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv64_zbb, riscv_extention_t.rv64_zbp, riscv_extention_t.rv64_zks, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RORI
+  riscv_instr_param_s(
+     riscv_instr_name_t.RORIW, // instr_name
+     riscv_instr_name_t.RORIW, // orig_name
+     0xfe00707f, // mask
+     0x6000501b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtw], // variables
+     [riscv_extention_t.rv64_zbb, riscv_extention_t.rv64_zbp, riscv_extention_t.rv64_zks, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b10000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RORIW
+  riscv_instr_param_s(
+     riscv_instr_name_t.RORW, // instr_name
+     riscv_instr_name_t.RORW, // orig_name
+     0xfe00707f, // mask
+     0x6000503b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbb, riscv_extention_t.rv64_zbp, riscv_extention_t.rv64_zks, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RORW
+  riscv_instr_param_s(
+     riscv_instr_name_t.RSTAS16, // instr_name
+     riscv_instr_name_t.RSTAS16, // orig_name
+     0xfe00707f, // mask
+     0xb4002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RSTAS16
+  riscv_instr_param_s(
+     riscv_instr_name_t.RSTAS32, // instr_name
+     riscv_instr_name_t.RSTAS32, // orig_name
+     0xfe00707f, // mask
+     0xb0002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RSTAS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.RSTSA16, // instr_name
+     riscv_instr_name_t.VSHA2MS_VV, // orig_name
+     0xfe00707f, // mask
+     0xb6002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RSTSA16
+  riscv_instr_param_s(
+     riscv_instr_name_t.RSTSA32, // instr_name
+     riscv_instr_name_t.VGHSH_VV, // orig_name
+     0xfe00707f, // mask
+     0xb2002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RSTSA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.RSUB16, // instr_name
+     riscv_instr_name_t.RSUB16, // orig_name
+     0xfe00707f, // mask
+     0x2000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RSUB16
+  riscv_instr_param_s(
+     riscv_instr_name_t.RSUB32, // instr_name
+     riscv_instr_name_t.RSUB32, // orig_name
+     0xfe00707f, // mask
+     0x2002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RSUB32
+  riscv_instr_param_s(
+     riscv_instr_name_t.RSUB8, // instr_name
+     riscv_instr_name_t.RSUB8, // orig_name
+     0xfe00707f, // mask
+     0xa000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RSUB8
+  riscv_instr_param_s(
+     riscv_instr_name_t.RSUBW, // instr_name
+     riscv_instr_name_t.RSUBW, // orig_name
+     0xfe00707f, // mask
+     0x22001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // RSUBW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SB, // instr_name
+     riscv_instr_name_t.SB, // orig_name
+     0x707f, // mask
+     0x23, // match
+     [riscv_instr_var_t.imm12hi, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.imm12lo], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b101000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SB
+  riscv_instr_param_s(
+     riscv_instr_name_t.SBREAK, // instr_name
+     riscv_instr_name_t.EBREAK, // orig_name
+     0xffffffff, // mask
+     0x100073, // match
+     [], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SBREAK
+  riscv_instr_param_s(
+     riscv_instr_name_t.SC_D, // instr_name
+     riscv_instr_name_t.SC_D, // orig_name
+     0xf800707f, // mask
+     0x1800302f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv64_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SC_D
+  riscv_instr_param_s(
+     riscv_instr_name_t.SC_W, // instr_name
+     riscv_instr_name_t.SC_W, // orig_name
+     0xf800707f, // mask
+     0x1800202f, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.aq, riscv_instr_var_t.rl], // variables
+     [riscv_extention_t.rv_a], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b11001101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SC_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.SCALL, // instr_name
+     riscv_instr_name_t.ECALL, // orig_name
+     0xffffffff, // mask
+     0x73, // match
+     [], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SCALL
+  riscv_instr_param_s(
+     riscv_instr_name_t.SCLIP16, // instr_name
+     riscv_instr_name_t.SCLIP16, // orig_name
+     0xff00707f, // mask
+     0x84000077, // match
+     [riscv_instr_var_t.imm4, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b1000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SCLIP16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SCLIP32, // instr_name
+     riscv_instr_name_t.SCLIP32, // orig_name
+     0xfe00707f, // mask
+     0xe4000077, // match
+     [riscv_instr_var_t.imm5, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b10000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SCLIP32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SCLIP8, // instr_name
+     riscv_instr_name_t.SCLIP8, // orig_name
+     0xff80707f, // mask
+     0x8c000077, // match
+     [riscv_instr_var_t.imm3, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b100000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SCLIP8
+  riscv_instr_param_s(
+     riscv_instr_name_t.SCMPLE16, // instr_name
+     riscv_instr_name_t.SCMPLE16, // orig_name
+     0xfe00707f, // mask
+     0x1c000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SCMPLE16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SCMPLE8, // instr_name
+     riscv_instr_name_t.SCMPLE8, // orig_name
+     0xfe00707f, // mask
+     0x1e000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SCMPLE8
+  riscv_instr_param_s(
+     riscv_instr_name_t.SCMPLT16, // instr_name
+     riscv_instr_name_t.SCMPLT16, // orig_name
+     0xfe00707f, // mask
+     0xc000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SCMPLT16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SCMPLT8, // instr_name
+     riscv_instr_name_t.SCMPLT8, // orig_name
+     0xfe00707f, // mask
+     0xe000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SCMPLT8
+  riscv_instr_param_s(
+     riscv_instr_name_t.SD, // instr_name
+     riscv_instr_name_t.SD, // orig_name
+     0x707f, // mask
+     0x3023, // match
+     [riscv_instr_var_t.imm12hi, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.imm12lo], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b101000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SD
+  riscv_instr_param_s(
+     riscv_instr_name_t.SEXT_B, // instr_name
+     riscv_instr_name_t.SEXT_B, // orig_name
+     0xfff0707f, // mask
+     0x60401013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zbb], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SEXT_B
+  riscv_instr_param_s(
+     riscv_instr_name_t.SEXT_H, // instr_name
+     riscv_instr_name_t.SEXT_H, // orig_name
+     0xfff0707f, // mask
+     0x60501013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv_zbb], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SEXT_H
+  riscv_instr_param_s(
+     riscv_instr_name_t.SFENCE_VMA, // instr_name
+     riscv_instr_name_t.SFENCE_VMA, // orig_name
+     0xfe007fff, // mask
+     0x12000073, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_s], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SFENCE_VMA
+  riscv_instr_param_s(
+     riscv_instr_name_t.SH, // instr_name
+     riscv_instr_name_t.SH, // orig_name
+     0x707f, // mask
+     0x1023, // match
+     [riscv_instr_var_t.imm12hi, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.imm12lo], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b101000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SH
+  riscv_instr_param_s(
+     riscv_instr_name_t.SH1ADD, // instr_name
+     riscv_instr_name_t.SH1ADD, // orig_name
+     0xfe00707f, // mask
+     0x20002033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zba], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SH1ADD
+  riscv_instr_param_s(
+     riscv_instr_name_t.SH1ADD_UW, // instr_name
+     riscv_instr_name_t.SH1ADD_UW, // orig_name
+     0xfe00707f, // mask
+     0x2000203b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zba], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SH1ADD_UW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SH2ADD, // instr_name
+     riscv_instr_name_t.SH2ADD, // orig_name
+     0xfe00707f, // mask
+     0x20004033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zba], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SH2ADD
+  riscv_instr_param_s(
+     riscv_instr_name_t.SH2ADD_UW, // instr_name
+     riscv_instr_name_t.SH2ADD_UW, // orig_name
+     0xfe00707f, // mask
+     0x2000403b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zba], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SH2ADD_UW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SH3ADD, // instr_name
+     riscv_instr_name_t.SH3ADD, // orig_name
+     0xfe00707f, // mask
+     0x20006033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zba], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SH3ADD
+  riscv_instr_param_s(
+     riscv_instr_name_t.SH3ADD_UW, // instr_name
+     riscv_instr_name_t.SH3ADD_UW, // orig_name
+     0xfe00707f, // mask
+     0x2000603b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zba], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SH3ADD_UW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SHFL, // instr_name
+     riscv_instr_name_t.SHFL, // orig_name
+     0xfe00707f, // mask
+     0x8001033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SHFL
+  riscv_instr_param_s(
+     riscv_instr_name_t.SHFLI, // instr_name
+     riscv_instr_name_t.SHFLI, // orig_name
+     0xfe00707f, // mask
+     0x8001013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtw], // variables
+     [riscv_extention_t.rv64_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b10000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SHFLI
+  riscv_instr_param_s(
+     riscv_instr_name_t.SHFLW, // instr_name
+     riscv_instr_name_t.SHFLW, // orig_name
+     0xfe00707f, // mask
+     0x800103b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SHFLW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLL, // instr_name
+     riscv_instr_name_t.SLL, // orig_name
+     0xfe00707f, // mask
+     0x1033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLL
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLL16, // instr_name
+     riscv_instr_name_t.SLL16, // orig_name
+     0xfe00707f, // mask
+     0x54000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLL16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLL32, // instr_name
+     riscv_instr_name_t.SLL32, // orig_name
+     0xfe00707f, // mask
+     0x54002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLL32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLL8, // instr_name
+     riscv_instr_name_t.SLL8, // orig_name
+     0xfe00707f, // mask
+     0x5c000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLL8
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLLI, // instr_name
+     riscv_instr_name_t.SLLI, // orig_name
+     0xfc00707f, // mask
+     0x1013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLLI
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLLI16, // instr_name
+     riscv_instr_name_t.SLLI16, // orig_name
+     0xff00707f, // mask
+     0x74000077, // match
+     [riscv_instr_var_t.imm4, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b1000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLLI16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLLI32, // instr_name
+     riscv_instr_name_t.SLLI32, // orig_name
+     0xfe00707f, // mask
+     0x74002077, // match
+     [riscv_instr_var_t.imm5, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b10000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLLI32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLLI8, // instr_name
+     riscv_instr_name_t.SLLI8, // orig_name
+     0xff80707f, // mask
+     0x7c000077, // match
+     [riscv_instr_var_t.imm3, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b100000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLLI8
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLLI_UW, // instr_name
+     riscv_instr_name_t.SLLI_UW, // orig_name
+     0xfc00707f, // mask
+     0x800101b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv64_zba], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLLI_UW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLLIW, // instr_name
+     riscv_instr_name_t.SLLIW, // orig_name
+     0xfe00707f, // mask
+     0x101b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtw], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b10000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLLIW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLLW, // instr_name
+     riscv_instr_name_t.SLLW, // orig_name
+     0xfe00707f, // mask
+     0x103b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLLW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLO, // instr_name
+     riscv_instr_name_t.SLO, // orig_name
+     0xfe00707f, // mask
+     0x20001033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_b], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLO
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLOI, // instr_name
+     riscv_instr_name_t.SLOI, // orig_name
+     0xfc00707f, // mask
+     0x20001013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv_b], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLOI
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLOIW, // instr_name
+     riscv_instr_name_t.SLOIW, // orig_name
+     0xfe00707f, // mask
+     0x2000101b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtw], // variables
+     [riscv_extention_t.rv64_b], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b10000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLOIW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLOW, // instr_name
+     riscv_instr_name_t.SLOW, // orig_name
+     0xfe00707f, // mask
+     0x2000103b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_b], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLOW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLT, // instr_name
+     riscv_instr_name_t.SLT, // orig_name
+     0xfe00707f, // mask
+     0x2033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLT
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLTI, // instr_name
+     riscv_instr_name_t.SLTI, // orig_name
+     0x707f, // mask
+     0x2013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLTI
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLTIU, // instr_name
+     riscv_instr_name_t.SLTIU, // orig_name
+     0x707f, // mask
+     0x3013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLTIU
+  riscv_instr_param_s(
+     riscv_instr_name_t.SLTU, // instr_name
+     riscv_instr_name_t.SLTU, // orig_name
+     0xfe00707f, // mask
+     0x3033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SLTU
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMAQA, // instr_name
+     riscv_instr_name_t.SMAQA, // orig_name
+     0xfe00707f, // mask
+     0xc8000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMAQA
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMAQA_SU, // instr_name
+     riscv_instr_name_t.SMAQA_SU, // orig_name
+     0xfe00707f, // mask
+     0xca000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMAQA_SU
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMAX16, // instr_name
+     riscv_instr_name_t.SMAX16, // orig_name
+     0xfe00707f, // mask
+     0x82000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMAX16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMAX32, // instr_name
+     riscv_instr_name_t.SMAX32, // orig_name
+     0xfe00707f, // mask
+     0x92002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMAX32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMAX8, // instr_name
+     riscv_instr_name_t.SMAX8, // orig_name
+     0xfe00707f, // mask
+     0x8a000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMAX8
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMBB16, // instr_name
+     riscv_instr_name_t.SMBB16, // orig_name
+     0xfe00707f, // mask
+     0x8001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMBB16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMBT16, // instr_name
+     riscv_instr_name_t.SMBT16, // orig_name
+     0xfe00707f, // mask
+     0x18001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMBT16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMBT32, // instr_name
+     riscv_instr_name_t.SMBT32, // orig_name
+     0xfe00707f, // mask
+     0x18002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMBT32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMDRS, // instr_name
+     riscv_instr_name_t.SMDRS, // orig_name
+     0xfe00707f, // mask
+     0x68001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMDRS
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMDRS32, // instr_name
+     riscv_instr_name_t.SMDRS32, // orig_name
+     0xfe00707f, // mask
+     0x68002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMDRS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMDS, // instr_name
+     riscv_instr_name_t.SMDS, // orig_name
+     0xfe00707f, // mask
+     0x58001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMDS
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMDS32, // instr_name
+     riscv_instr_name_t.SMDS32, // orig_name
+     0xfe00707f, // mask
+     0x58002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMDS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMIN16, // instr_name
+     riscv_instr_name_t.SMIN16, // orig_name
+     0xfe00707f, // mask
+     0x80000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMIN16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMIN32, // instr_name
+     riscv_instr_name_t.SMIN32, // orig_name
+     0xfe00707f, // mask
+     0x90002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMIN32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMIN8, // instr_name
+     riscv_instr_name_t.SMIN8, // orig_name
+     0xfe00707f, // mask
+     0x88000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMIN8
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMMUL, // instr_name
+     riscv_instr_name_t.SMMUL, // orig_name
+     0xfe00707f, // mask
+     0x40001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMMUL
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMMUL_U, // instr_name
+     riscv_instr_name_t.SMMUL_U, // orig_name
+     0xfe00707f, // mask
+     0x50001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMMUL_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMMWB, // instr_name
+     riscv_instr_name_t.SMMWB, // orig_name
+     0xfe00707f, // mask
+     0x44001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMMWB
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMMWB_U, // instr_name
+     riscv_instr_name_t.SMMWB_U, // orig_name
+     0xfe00707f, // mask
+     0x54001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMMWB_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMMWT, // instr_name
+     riscv_instr_name_t.SMMWT, // orig_name
+     0xfe00707f, // mask
+     0x64001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMMWT
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMMWT_U, // instr_name
+     riscv_instr_name_t.SMMWT_U, // orig_name
+     0xfe00707f, // mask
+     0x74001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMMWT_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMTT16, // instr_name
+     riscv_instr_name_t.SMTT16, // orig_name
+     0xfe00707f, // mask
+     0x28001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMTT16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMTT32, // instr_name
+     riscv_instr_name_t.SMTT32, // orig_name
+     0xfe00707f, // mask
+     0x28002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMTT32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMXDS, // instr_name
+     riscv_instr_name_t.SMXDS, // orig_name
+     0xfe00707f, // mask
+     0x78001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMXDS
+  riscv_instr_param_s(
+     riscv_instr_name_t.SMXDS32, // instr_name
+     riscv_instr_name_t.SMXDS32, // orig_name
+     0xfe00707f, // mask
+     0x78002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SMXDS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRA, // instr_name
+     riscv_instr_name_t.SRA, // orig_name
+     0xfe00707f, // mask
+     0x40005033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRA
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRA16, // instr_name
+     riscv_instr_name_t.SRA16, // orig_name
+     0xfe00707f, // mask
+     0x50000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRA16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRA16_U, // instr_name
+     riscv_instr_name_t.SRA16_U, // orig_name
+     0xfe00707f, // mask
+     0x60000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRA16_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRA32, // instr_name
+     riscv_instr_name_t.SRA32, // orig_name
+     0xfe00707f, // mask
+     0x50002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRA32_U, // instr_name
+     riscv_instr_name_t.SRA32_U, // orig_name
+     0xfe00707f, // mask
+     0x60002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRA32_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRA8, // instr_name
+     riscv_instr_name_t.SRA8, // orig_name
+     0xfe00707f, // mask
+     0x58000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRA8
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRA8_U, // instr_name
+     riscv_instr_name_t.SRA8_U, // orig_name
+     0xfe00707f, // mask
+     0x68000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRA8_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRA_U, // instr_name
+     riscv_instr_name_t.SRA_U, // orig_name
+     0xfe00707f, // mask
+     0x24001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRA_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRAI, // instr_name
+     riscv_instr_name_t.SRAI, // orig_name
+     0xfc00707f, // mask
+     0x40005013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRAI
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRAI16, // instr_name
+     riscv_instr_name_t.SRAI16, // orig_name
+     0xff00707f, // mask
+     0x70000077, // match
+     [riscv_instr_var_t.imm4, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b1000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRAI16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRAI16_U, // instr_name
+     riscv_instr_name_t.SRAI16_U, // orig_name
+     0xff00707f, // mask
+     0x71000077, // match
+     [riscv_instr_var_t.imm4, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b1000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRAI16_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRAI32, // instr_name
+     riscv_instr_name_t.SRAI32, // orig_name
+     0xfe00707f, // mask
+     0x70002077, // match
+     [riscv_instr_var_t.imm5, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b10000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRAI32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRAI32_U, // instr_name
+     riscv_instr_name_t.SRAI32_U, // orig_name
+     0xfe00707f, // mask
+     0x80002077, // match
+     [riscv_instr_var_t.imm5, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b10000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRAI32_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRAI8, // instr_name
+     riscv_instr_name_t.SRAI8, // orig_name
+     0xff80707f, // mask
+     0x78000077, // match
+     [riscv_instr_var_t.imm3, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b100000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRAI8
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRAI8_U, // instr_name
+     riscv_instr_name_t.SRAI8_U, // orig_name
+     0xff80707f, // mask
+     0x78800077, // match
+     [riscv_instr_var_t.imm3, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b100000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRAI8_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRAI_U, // instr_name
+     riscv_instr_name_t.SRAI_U, // orig_name
+     0xfc00707f, // mask
+     0xd4001077, // match
+     [riscv_instr_var_t.imm6, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b100000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRAI_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRAIW, // instr_name
+     riscv_instr_name_t.SRAIW, // orig_name
+     0xfe00707f, // mask
+     0x4000501b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtw], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b10000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRAIW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRAIW_U, // instr_name
+     riscv_instr_name_t.SRAIW_U, // orig_name
+     0xfe00707f, // mask
+     0x34001077, // match
+     [riscv_instr_var_t.imm5, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b10000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRAIW_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRAW, // instr_name
+     riscv_instr_name_t.SRAW, // orig_name
+     0xfe00707f, // mask
+     0x4000503b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRAW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRET, // instr_name
+     riscv_instr_name_t.SRET, // orig_name
+     0xffffffff, // mask
+     0x10200073, // match
+     [], // variables
+     [riscv_extention_t.rv_s], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRET
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRL, // instr_name
+     riscv_instr_name_t.SRL, // orig_name
+     0xfe00707f, // mask
+     0x5033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRL
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRL16, // instr_name
+     riscv_instr_name_t.SRL16, // orig_name
+     0xfe00707f, // mask
+     0x52000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRL16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRL16_U, // instr_name
+     riscv_instr_name_t.SRL16_U, // orig_name
+     0xfe00707f, // mask
+     0x62000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRL16_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRL32, // instr_name
+     riscv_instr_name_t.SRL32, // orig_name
+     0xfe00707f, // mask
+     0x52002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRL32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRL32_U, // instr_name
+     riscv_instr_name_t.SRL32_U, // orig_name
+     0xfe00707f, // mask
+     0x62002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRL32_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRL8, // instr_name
+     riscv_instr_name_t.SRL8, // orig_name
+     0xfe00707f, // mask
+     0x5a000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRL8
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRL8_U, // instr_name
+     riscv_instr_name_t.SRL8_U, // orig_name
+     0xfe00707f, // mask
+     0x6a000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRL8_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRLI, // instr_name
+     riscv_instr_name_t.SRLI, // orig_name
+     0xfc00707f, // mask
+     0x5013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRLI
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRLI16, // instr_name
+     riscv_instr_name_t.SRLI16, // orig_name
+     0xff00707f, // mask
+     0x72000077, // match
+     [riscv_instr_var_t.imm4, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b1000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRLI16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRLI16_U, // instr_name
+     riscv_instr_name_t.SRLI16_U, // orig_name
+     0xff00707f, // mask
+     0x73000077, // match
+     [riscv_instr_var_t.imm4, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b1000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRLI16_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRLI32, // instr_name
+     riscv_instr_name_t.SRLI32, // orig_name
+     0xfe00707f, // mask
+     0x72002077, // match
+     [riscv_instr_var_t.imm5, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b10000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRLI32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRLI32_U, // instr_name
+     riscv_instr_name_t.VSM3ME_VV, // orig_name
+     0xfe00707f, // mask
+     0x82002077, // match
+     [riscv_instr_var_t.imm5, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b10000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRLI32_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRLI8, // instr_name
+     riscv_instr_name_t.SRLI8, // orig_name
+     0xff80707f, // mask
+     0x7a000077, // match
+     [riscv_instr_var_t.imm3, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b100000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRLI8
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRLI8_U, // instr_name
+     riscv_instr_name_t.SRLI8_U, // orig_name
+     0xff80707f, // mask
+     0x7a800077, // match
+     [riscv_instr_var_t.imm3, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b100000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRLI8_U
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRLIW, // instr_name
+     riscv_instr_name_t.SRLIW, // orig_name
+     0xfe00707f, // mask
+     0x501b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtw], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b10000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRLIW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRLW, // instr_name
+     riscv_instr_name_t.SRLW, // orig_name
+     0xfe00707f, // mask
+     0x503b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRLW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SRO, // instr_name
+     riscv_instr_name_t.SRO, // orig_name
+     0xfe00707f, // mask
+     0x20005033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_b], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SRO
+  riscv_instr_param_s(
+     riscv_instr_name_t.SROI, // instr_name
+     riscv_instr_name_t.SROI, // orig_name
+     0xfc00707f, // mask
+     0x20005013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtd], // variables
+     [riscv_extention_t.rv_b], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1000000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SROI
+  riscv_instr_param_s(
+     riscv_instr_name_t.SROIW, // instr_name
+     riscv_instr_name_t.SROIW, // orig_name
+     0xfe00707f, // mask
+     0x2000501b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtw], // variables
+     [riscv_extention_t.rv64_b], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b10000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SROIW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SROW, // instr_name
+     riscv_instr_name_t.SROW, // orig_name
+     0xfe00707f, // mask
+     0x2000503b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_b], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SROW
+  riscv_instr_param_s(
+     riscv_instr_name_t.STAS16, // instr_name
+     riscv_instr_name_t.STAS16, // orig_name
+     0xfe00707f, // mask
+     0xf4002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // STAS16
+  riscv_instr_param_s(
+     riscv_instr_name_t.STAS32, // instr_name
+     riscv_instr_name_t.STAS32, // orig_name
+     0xfe00707f, // mask
+     0xf0002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // STAS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.STSA16, // instr_name
+     riscv_instr_name_t.STSA16, // orig_name
+     0xfe00707f, // mask
+     0xf6002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // STSA16
+  riscv_instr_param_s(
+     riscv_instr_name_t.STSA32, // instr_name
+     riscv_instr_name_t.STSA32, // orig_name
+     0xfe00707f, // mask
+     0xf2002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // STSA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SUB, // instr_name
+     riscv_instr_name_t.SUB, // orig_name
+     0xfe00707f, // mask
+     0x40000033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SUB
+  riscv_instr_param_s(
+     riscv_instr_name_t.SUB16, // instr_name
+     riscv_instr_name_t.SUB16, // orig_name
+     0xfe00707f, // mask
+     0x42000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SUB16
+  riscv_instr_param_s(
+     riscv_instr_name_t.SUB32, // instr_name
+     riscv_instr_name_t.SUB32, // orig_name
+     0xfe00707f, // mask
+     0x42002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SUB32
+  riscv_instr_param_s(
+     riscv_instr_name_t.SUB8, // instr_name
+     riscv_instr_name_t.SUB8, // orig_name
+     0xfe00707f, // mask
+     0x4a000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SUB8
+  riscv_instr_param_s(
+     riscv_instr_name_t.SUBW, // instr_name
+     riscv_instr_name_t.SUBW, // orig_name
+     0xfe00707f, // mask
+     0x4000003b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SUBW
+  riscv_instr_param_s(
+     riscv_instr_name_t.SUNPKD810, // instr_name
+     riscv_instr_name_t.SUNPKD810, // orig_name
+     0xfff0707f, // mask
+     0xac800077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SUNPKD810
+  riscv_instr_param_s(
+     riscv_instr_name_t.SUNPKD820, // instr_name
+     riscv_instr_name_t.SUNPKD820, // orig_name
+     0xfff0707f, // mask
+     0xac900077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SUNPKD820
+  riscv_instr_param_s(
+     riscv_instr_name_t.SUNPKD830, // instr_name
+     riscv_instr_name_t.SUNPKD830, // orig_name
+     0xfff0707f, // mask
+     0xaca00077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SUNPKD830
+  riscv_instr_param_s(
+     riscv_instr_name_t.SUNPKD831, // instr_name
+     riscv_instr_name_t.SUNPKD831, // orig_name
+     0xfff0707f, // mask
+     0xacb00077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SUNPKD831
+  riscv_instr_param_s(
+     riscv_instr_name_t.SUNPKD832, // instr_name
+     riscv_instr_name_t.SUNPKD832, // orig_name
+     0xfff0707f, // mask
+     0xad300077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SUNPKD832
+  riscv_instr_param_s(
+     riscv_instr_name_t.SW, // instr_name
+     riscv_instr_name_t.SW, // orig_name
+     0x707f, // mask
+     0x2023, // match
+     [riscv_instr_var_t.imm12hi, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2, riscv_instr_var_t.imm12lo], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b101000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // SW
+  riscv_instr_param_s(
+     riscv_instr_name_t.UCLIP16, // instr_name
+     riscv_instr_name_t.UCLIP16, // orig_name
+     0xff00707f, // mask
+     0x85000077, // match
+     [riscv_instr_var_t.imm4, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b1000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UCLIP16
+  riscv_instr_param_s(
+     riscv_instr_name_t.UCLIP32, // instr_name
+     riscv_instr_name_t.UCLIP32, // orig_name
+     0xfe00707f, // mask
+     0xf4000077, // match
+     [riscv_instr_var_t.imm5, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b10000000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UCLIP32
+  riscv_instr_param_s(
+     riscv_instr_name_t.UCLIP8, // instr_name
+     riscv_instr_name_t.UCLIP8, // orig_name
+     0xff80707f, // mask
+     0x8d000077, // match
+     [riscv_instr_var_t.imm3, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b100000000, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UCLIP8
+  riscv_instr_param_s(
+     riscv_instr_name_t.UCMPLE16, // instr_name
+     riscv_instr_name_t.UCMPLE16, // orig_name
+     0xfe00707f, // mask
+     0x3c000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UCMPLE16
+  riscv_instr_param_s(
+     riscv_instr_name_t.UCMPLE8, // instr_name
+     riscv_instr_name_t.UCMPLE8, // orig_name
+     0xfe00707f, // mask
+     0x3e000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UCMPLE8
+  riscv_instr_param_s(
+     riscv_instr_name_t.UCMPLT16, // instr_name
+     riscv_instr_name_t.UCMPLT16, // orig_name
+     0xfe00707f, // mask
+     0x2c000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UCMPLT16
+  riscv_instr_param_s(
+     riscv_instr_name_t.UCMPLT8, // instr_name
+     riscv_instr_name_t.UCMPLT8, // orig_name
+     0xfe00707f, // mask
+     0x2e000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UCMPLT8
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKADD16, // instr_name
+     riscv_instr_name_t.UKADD16, // orig_name
+     0xfe00707f, // mask
+     0x30000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKADD16
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKADD32, // instr_name
+     riscv_instr_name_t.UKADD32, // orig_name
+     0xfe00707f, // mask
+     0x30002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKADD32
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKADD8, // instr_name
+     riscv_instr_name_t.UKADD8, // orig_name
+     0xfe00707f, // mask
+     0x38000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKADD8
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKADDH, // instr_name
+     riscv_instr_name_t.UKADDH, // orig_name
+     0xfe00707f, // mask
+     0x14001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKADDH
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKADDW, // instr_name
+     riscv_instr_name_t.UKADDW, // orig_name
+     0xfe00707f, // mask
+     0x10001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKADDW
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKCRAS16, // instr_name
+     riscv_instr_name_t.UKCRAS16, // orig_name
+     0xfe00707f, // mask
+     0x34000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKCRAS16
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKCRAS32, // instr_name
+     riscv_instr_name_t.UKCRAS32, // orig_name
+     0xfe00707f, // mask
+     0x34002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKCRAS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKCRSA16, // instr_name
+     riscv_instr_name_t.UKCRSA16, // orig_name
+     0xfe00707f, // mask
+     0x36000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKCRSA16
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKCRSA32, // instr_name
+     riscv_instr_name_t.UKCRSA32, // orig_name
+     0xfe00707f, // mask
+     0x36002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKCRSA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKSTAS16, // instr_name
+     riscv_instr_name_t.UKSTAS16, // orig_name
+     0xfe00707f, // mask
+     0xe4002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKSTAS16
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKSTAS32, // instr_name
+     riscv_instr_name_t.UKSTAS32, // orig_name
+     0xfe00707f, // mask
+     0xe0002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKSTAS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKSTSA16, // instr_name
+     riscv_instr_name_t.UKSTSA16, // orig_name
+     0xfe00707f, // mask
+     0xe6002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKSTSA16
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKSTSA32, // instr_name
+     riscv_instr_name_t.UKSTSA32, // orig_name
+     0xfe00707f, // mask
+     0xe2002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKSTSA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKSUB16, // instr_name
+     riscv_instr_name_t.UKSUB16, // orig_name
+     0xfe00707f, // mask
+     0x32000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKSUB16
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKSUB32, // instr_name
+     riscv_instr_name_t.UKSUB32, // orig_name
+     0xfe00707f, // mask
+     0x32002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKSUB32
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKSUB8, // instr_name
+     riscv_instr_name_t.UKSUB8, // orig_name
+     0xfe00707f, // mask
+     0x3a000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKSUB8
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKSUBH, // instr_name
+     riscv_instr_name_t.UKSUBH, // orig_name
+     0xfe00707f, // mask
+     0x16001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKSUBH
+  riscv_instr_param_s(
+     riscv_instr_name_t.UKSUBW, // instr_name
+     riscv_instr_name_t.UKSUBW, // orig_name
+     0xfe00707f, // mask
+     0x12001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UKSUBW
+  riscv_instr_param_s(
+     riscv_instr_name_t.UMAQA, // instr_name
+     riscv_instr_name_t.UMAQA, // orig_name
+     0xfe00707f, // mask
+     0xcc000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UMAQA
+  riscv_instr_param_s(
+     riscv_instr_name_t.UMAX16, // instr_name
+     riscv_instr_name_t.UMAX16, // orig_name
+     0xfe00707f, // mask
+     0x92000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UMAX16
+  riscv_instr_param_s(
+     riscv_instr_name_t.UMAX32, // instr_name
+     riscv_instr_name_t.VAESDF_VV, // orig_name
+     0xfe00707f, // mask
+     0xa2002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UMAX32
+  riscv_instr_param_s(
+     riscv_instr_name_t.UMAX8, // instr_name
+     riscv_instr_name_t.UMAX8, // orig_name
+     0xfe00707f, // mask
+     0x9a000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UMAX8
+  riscv_instr_param_s(
+     riscv_instr_name_t.UMIN16, // instr_name
+     riscv_instr_name_t.UMIN16, // orig_name
+     0xfe00707f, // mask
+     0x90000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UMIN16
+  riscv_instr_param_s(
+     riscv_instr_name_t.UMIN32, // instr_name
+     riscv_instr_name_t.UMIN32, // orig_name
+     0xfe00707f, // mask
+     0xa0002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UMIN32
+  riscv_instr_param_s(
+     riscv_instr_name_t.UMIN8, // instr_name
+     riscv_instr_name_t.UMIN8, // orig_name
+     0xfe00707f, // mask
+     0x98000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UMIN8
+  riscv_instr_param_s(
+     riscv_instr_name_t.UNSHFL, // instr_name
+     riscv_instr_name_t.UNSHFL, // orig_name
+     0xfe00707f, // mask
+     0x8005033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UNSHFL
+  riscv_instr_param_s(
+     riscv_instr_name_t.UNSHFLI, // instr_name
+     riscv_instr_name_t.UNSHFLI, // orig_name
+     0xfe00707f, // mask
+     0x8005013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.shamtw], // variables
+     [riscv_extention_t.rv64_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b10000000000000101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UNSHFLI
+  riscv_instr_param_s(
+     riscv_instr_name_t.UNSHFLW, // instr_name
+     riscv_instr_name_t.UNSHFLW, // orig_name
+     0xfe00707f, // mask
+     0x800503b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UNSHFLW
+  riscv_instr_param_s(
+     riscv_instr_name_t.UNZIP16, // instr_name
+     riscv_instr_name_t.UNSHFLI, // orig_name
+     0xfff0707f, // mask
+     0x9005013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv64_zbm], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UNZIP16
+  riscv_instr_param_s(
+     riscv_instr_name_t.UNZIP8, // instr_name
+     riscv_instr_name_t.UNSHFLI, // orig_name
+     0xfff0707f, // mask
+     0x9805013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv64_zbm], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // UNZIP8
+  riscv_instr_param_s(
+     riscv_instr_name_t.URADD16, // instr_name
+     riscv_instr_name_t.URADD16, // orig_name
+     0xfe00707f, // mask
+     0x20000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URADD16
+  riscv_instr_param_s(
+     riscv_instr_name_t.URADD32, // instr_name
+     riscv_instr_name_t.URADD32, // orig_name
+     0xfe00707f, // mask
+     0x20002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URADD32
+  riscv_instr_param_s(
+     riscv_instr_name_t.URADD8, // instr_name
+     riscv_instr_name_t.URADD8, // orig_name
+     0xfe00707f, // mask
+     0x28000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URADD8
+  riscv_instr_param_s(
+     riscv_instr_name_t.URADDW, // instr_name
+     riscv_instr_name_t.URADDW, // orig_name
+     0xfe00707f, // mask
+     0x30001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URADDW
+  riscv_instr_param_s(
+     riscv_instr_name_t.URCRAS16, // instr_name
+     riscv_instr_name_t.URCRAS16, // orig_name
+     0xfe00707f, // mask
+     0x24000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URCRAS16
+  riscv_instr_param_s(
+     riscv_instr_name_t.URCRAS32, // instr_name
+     riscv_instr_name_t.URCRAS32, // orig_name
+     0xfe00707f, // mask
+     0x24002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URCRAS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.URCRSA16, // instr_name
+     riscv_instr_name_t.URCRSA16, // orig_name
+     0xfe00707f, // mask
+     0x26000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URCRSA16
+  riscv_instr_param_s(
+     riscv_instr_name_t.URCRSA32, // instr_name
+     riscv_instr_name_t.URCRSA32, // orig_name
+     0xfe00707f, // mask
+     0x26002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URCRSA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.URSTAS16, // instr_name
+     riscv_instr_name_t.URSTAS16, // orig_name
+     0xfe00707f, // mask
+     0xd4002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URSTAS16
+  riscv_instr_param_s(
+     riscv_instr_name_t.URSTAS32, // instr_name
+     riscv_instr_name_t.URSTAS32, // orig_name
+     0xfe00707f, // mask
+     0xd0002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URSTAS32
+  riscv_instr_param_s(
+     riscv_instr_name_t.URSTSA16, // instr_name
+     riscv_instr_name_t.URSTSA16, // orig_name
+     0xfe00707f, // mask
+     0xd6002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URSTSA16
+  riscv_instr_param_s(
+     riscv_instr_name_t.URSTSA32, // instr_name
+     riscv_instr_name_t.URSTSA32, // orig_name
+     0xfe00707f, // mask
+     0xd2002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URSTSA32
+  riscv_instr_param_s(
+     riscv_instr_name_t.URSUB16, // instr_name
+     riscv_instr_name_t.URSUB16, // orig_name
+     0xfe00707f, // mask
+     0x22000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URSUB16
+  riscv_instr_param_s(
+     riscv_instr_name_t.URSUB32, // instr_name
+     riscv_instr_name_t.URSUB32, // orig_name
+     0xfe00707f, // mask
+     0x22002077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv64_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URSUB32
+  riscv_instr_param_s(
+     riscv_instr_name_t.URSUB8, // instr_name
+     riscv_instr_name_t.URSUB8, // orig_name
+     0xfe00707f, // mask
+     0x2a000077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URSUB8
+  riscv_instr_param_s(
+     riscv_instr_name_t.URSUBW, // instr_name
+     riscv_instr_name_t.URSUBW, // orig_name
+     0xfe00707f, // mask
+     0x32001077, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // URSUBW
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAADD_VV, // instr_name
+     riscv_instr_name_t.VAADD_VV, // orig_name
+     0xfc00707f, // mask
+     0x24002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VAADD_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAADD_VX, // instr_name
+     riscv_instr_name_t.VAADD_VX, // orig_name
+     0xfc00707f, // mask
+     0x24006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VAADD_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAADDU_VV, // instr_name
+     riscv_instr_name_t.VAADDU_VV, // orig_name
+     0xfc00707f, // mask
+     0x20002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VAADDU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAADDU_VX, // instr_name
+     riscv_instr_name_t.VAADDU_VX, // orig_name
+     0xfc00707f, // mask
+     0x20006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VAADDU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VADC_VIM, // instr_name
+     riscv_instr_name_t.VADC_VIM, // orig_name
+     0xfe00707f, // mask
+     0x40003057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VADC_VIM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VADC_VVM, // instr_name
+     riscv_instr_name_t.VADC_VVM, // orig_name
+     0xfe00707f, // mask
+     0x40000057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VADC_VVM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VADC_VXM, // instr_name
+     riscv_instr_name_t.VADC_VXM, // orig_name
+     0xfe00707f, // mask
+     0x40004057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VADC_VXM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VADD_VI, // instr_name
+     riscv_instr_name_t.VADD_VI, // orig_name
+     0xfc00707f, // mask
+     0x3057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VADD_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VADD_VV, // instr_name
+     riscv_instr_name_t.VADD_VV, // orig_name
+     0xfc00707f, // mask
+     0x57, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VADD_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VADD_VX, // instr_name
+     riscv_instr_name_t.VADD_VX, // orig_name
+     0xfc00707f, // mask
+     0x4057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VADD_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAESDF_VS, // instr_name
+     riscv_instr_name_t.VAESDF_VS, // orig_name
+     0xfe0ff07f, // mask
+     0xa600a077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VAESDF_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAESDF_VV, // instr_name
+     riscv_instr_name_t.VAESDF_VV, // orig_name
+     0xfe0ff07f, // mask
+     0xa200a077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VAESDF_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAESDM_VS, // instr_name
+     riscv_instr_name_t.VAESDM_VS, // orig_name
+     0xfe0ff07f, // mask
+     0xa6002077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VAESDM_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAESDM_VV, // instr_name
+     riscv_instr_name_t.VAESDM_VV, // orig_name
+     0xfe0ff07f, // mask
+     0xa2002077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VAESDM_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAESEF_VS, // instr_name
+     riscv_instr_name_t.VAESEF_VS, // orig_name
+     0xfe0ff07f, // mask
+     0xa601a077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VAESEF_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAESEF_VV, // instr_name
+     riscv_instr_name_t.VAESEF_VV, // orig_name
+     0xfe0ff07f, // mask
+     0xa201a077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VAESEF_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAESEM_VS, // instr_name
+     riscv_instr_name_t.VAESEM_VS, // orig_name
+     0xfe0ff07f, // mask
+     0xa6012077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VAESEM_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAESEM_VV, // instr_name
+     riscv_instr_name_t.VAESEM_VV, // orig_name
+     0xfe0ff07f, // mask
+     0xa2012077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VAESEM_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAESKF1_VI, // instr_name
+     riscv_instr_name_t.VAESKF1_VI, // orig_name
+     0xfe00707f, // mask
+     0x8a002077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.zimm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b10, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VAESKF1_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAESKF2_VI, // instr_name
+     riscv_instr_name_t.VAESKF2_VI, // orig_name
+     0xfe00707f, // mask
+     0xaa002077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.zimm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b10, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VAESKF2_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAESZ_VS, // instr_name
+     riscv_instr_name_t.VAESZ_VS, // orig_name
+     0xfe0ff07f, // mask
+     0xa603a077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VAESZ_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAND_VI, // instr_name
+     riscv_instr_name_t.VAND_VI, // orig_name
+     0xfc00707f, // mask
+     0x24003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VAND_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAND_VV, // instr_name
+     riscv_instr_name_t.VAND_VV, // orig_name
+     0xfc00707f, // mask
+     0x24000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VAND_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VAND_VX, // instr_name
+     riscv_instr_name_t.VAND_VX, // orig_name
+     0xfc00707f, // mask
+     0x24004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VAND_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VANDN_VV, // instr_name
+     riscv_instr_name_t.VANDN_VV, // orig_name
+     0xfc00707f, // mask
+     0x4000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VANDN_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VANDN_VX, // instr_name
+     riscv_instr_name_t.VANDN_VX, // orig_name
+     0xfc00707f, // mask
+     0x4004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VANDN_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VASUB_VV, // instr_name
+     riscv_instr_name_t.VASUB_VV, // orig_name
+     0xfc00707f, // mask
+     0x2c002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VASUB_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VASUB_VX, // instr_name
+     riscv_instr_name_t.VASUB_VX, // orig_name
+     0xfc00707f, // mask
+     0x2c006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VASUB_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VASUBU_VV, // instr_name
+     riscv_instr_name_t.VASUBU_VV, // orig_name
+     0xfc00707f, // mask
+     0x28002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VASUBU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VASUBU_VX, // instr_name
+     riscv_instr_name_t.VASUBU_VX, // orig_name
+     0xfc00707f, // mask
+     0x28006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VASUBU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VBREV8_V, // instr_name
+     riscv_instr_name_t.VBREV8_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48042057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VBREV8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VBREV_V, // instr_name
+     riscv_instr_name_t.VBREV_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48052057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VBREV_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VCLMUL_VV, // instr_name
+     riscv_instr_name_t.VCLMUL_VV, // orig_name
+     0xfc00707f, // mask
+     0x30002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VCLMUL_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VCLMUL_VX, // instr_name
+     riscv_instr_name_t.VCLMUL_VX, // orig_name
+     0xfc00707f, // mask
+     0x30006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VCLMUL_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VCLMULH_VV, // instr_name
+     riscv_instr_name_t.VCLMULH_VV, // orig_name
+     0xfc00707f, // mask
+     0x34002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VCLMULH_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VCLMULH_VX, // instr_name
+     riscv_instr_name_t.VCLMULH_VX, // orig_name
+     0xfc00707f, // mask
+     0x34006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VCLMULH_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VCLZ_V, // instr_name
+     riscv_instr_name_t.VCLZ_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48062057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VCLZ_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VCOMPRESS_VM, // instr_name
+     riscv_instr_name_t.VCOMPRESS_VM, // orig_name
+     0xfe00707f, // mask
+     0x5e002057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VCOMPRESS_VM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VCPOP_M, // instr_name
+     riscv_instr_name_t.VCPOP_M, // orig_name
+     0xfc0ff07f, // mask
+     0x40082057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b11000, // _v_vars
+   ), // VCPOP_M
+  riscv_instr_param_s(
+     riscv_instr_name_t.VCPOP_V, // instr_name
+     riscv_instr_name_t.VCPOP_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48072057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VCPOP_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VCTZ_V, // instr_name
+     riscv_instr_name_t.VCTZ_V, // orig_name
+     0xfc0ff07f, // mask
+     0x4806a057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VCTZ_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VDIV_VV, // instr_name
+     riscv_instr_name_t.VDIV_VV, // orig_name
+     0xfc00707f, // mask
+     0x84002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VDIV_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VDIV_VX, // instr_name
+     riscv_instr_name_t.VDIV_VX, // orig_name
+     0xfc00707f, // mask
+     0x84006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VDIV_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VDIVU_VV, // instr_name
+     riscv_instr_name_t.VDIVU_VV, // orig_name
+     0xfc00707f, // mask
+     0x80002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VDIVU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VDIVU_VX, // instr_name
+     riscv_instr_name_t.VDIVU_VX, // orig_name
+     0xfc00707f, // mask
+     0x80006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VDIVU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFADD_VF, // instr_name
+     riscv_instr_name_t.VFADD_VF, // orig_name
+     0xfc00707f, // mask
+     0x5057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFADD_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFADD_VV, // instr_name
+     riscv_instr_name_t.VFADD_VV, // orig_name
+     0xfc00707f, // mask
+     0x1057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFADD_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFCLASS_V, // instr_name
+     riscv_instr_name_t.VFCLASS_V, // orig_name
+     0xfc0ff07f, // mask
+     0x4c081057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFCLASS_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFCVT_F_X_V, // instr_name
+     riscv_instr_name_t.VFCVT_F_X_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48019057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFCVT_F_X_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFCVT_F_XU_V, // instr_name
+     riscv_instr_name_t.VFCVT_F_XU_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48011057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFCVT_F_XU_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFCVT_RTZ_X_F_V, // instr_name
+     riscv_instr_name_t.VFCVT_RTZ_X_F_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48039057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFCVT_RTZ_X_F_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFCVT_RTZ_XU_F_V, // instr_name
+     riscv_instr_name_t.VFCVT_RTZ_XU_F_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48031057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFCVT_RTZ_XU_F_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFCVT_X_F_V, // instr_name
+     riscv_instr_name_t.VFCVT_X_F_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48009057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFCVT_X_F_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFCVT_XU_F_V, // instr_name
+     riscv_instr_name_t.VFCVT_XU_F_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFCVT_XU_F_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFDIV_VF, // instr_name
+     riscv_instr_name_t.VFDIV_VF, // orig_name
+     0xfc00707f, // mask
+     0x80005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFDIV_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFDIV_VV, // instr_name
+     riscv_instr_name_t.VFDIV_VV, // orig_name
+     0xfc00707f, // mask
+     0x80001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFDIV_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFIRST_M, // instr_name
+     riscv_instr_name_t.VFIRST_M, // orig_name
+     0xfc0ff07f, // mask
+     0x4008a057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b11000, // _v_vars
+   ), // VFIRST_M
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMACC_VF, // instr_name
+     riscv_instr_name_t.VFMACC_VF, // orig_name
+     0xfc00707f, // mask
+     0xb0005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFMACC_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMACC_VV, // instr_name
+     riscv_instr_name_t.VFMACC_VV, // orig_name
+     0xfc00707f, // mask
+     0xb0001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFMACC_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMADD_VF, // instr_name
+     riscv_instr_name_t.VFMADD_VF, // orig_name
+     0xfc00707f, // mask
+     0xa0005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFMADD_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMADD_VV, // instr_name
+     riscv_instr_name_t.VFMADD_VV, // orig_name
+     0xfc00707f, // mask
+     0xa0001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFMADD_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMAX_VF, // instr_name
+     riscv_instr_name_t.VFMAX_VF, // orig_name
+     0xfc00707f, // mask
+     0x18005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFMAX_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMAX_VV, // instr_name
+     riscv_instr_name_t.VFMAX_VV, // orig_name
+     0xfc00707f, // mask
+     0x18001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFMAX_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMERGE_VFM, // instr_name
+     riscv_instr_name_t.VFMERGE_VFM, // orig_name
+     0xfe00707f, // mask
+     0x5c005057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VFMERGE_VFM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMIN_VF, // instr_name
+     riscv_instr_name_t.VFMIN_VF, // orig_name
+     0xfc00707f, // mask
+     0x10005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFMIN_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMIN_VV, // instr_name
+     riscv_instr_name_t.VFMIN_VV, // orig_name
+     0xfc00707f, // mask
+     0x10001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFMIN_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMSAC_VF, // instr_name
+     riscv_instr_name_t.VFMSAC_VF, // orig_name
+     0xfc00707f, // mask
+     0xb8005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFMSAC_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMSAC_VV, // instr_name
+     riscv_instr_name_t.VFMSAC_VV, // orig_name
+     0xfc00707f, // mask
+     0xb8001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFMSAC_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMSUB_VF, // instr_name
+     riscv_instr_name_t.VFMSUB_VF, // orig_name
+     0xfc00707f, // mask
+     0xa8005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFMSUB_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMSUB_VV, // instr_name
+     riscv_instr_name_t.VFMSUB_VV, // orig_name
+     0xfc00707f, // mask
+     0xa8001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFMSUB_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMUL_VF, // instr_name
+     riscv_instr_name_t.VFMUL_VF, // orig_name
+     0xfc00707f, // mask
+     0x90005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFMUL_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMUL_VV, // instr_name
+     riscv_instr_name_t.VFMUL_VV, // orig_name
+     0xfc00707f, // mask
+     0x90001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFMUL_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMV_F_S, // instr_name
+     riscv_instr_name_t.VFMV_F_S, // orig_name
+     0xfe0ff07f, // mask
+     0x42001057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b1000, // _v_vars
+   ), // VFMV_F_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMV_S_F, // instr_name
+     riscv_instr_name_t.VFMV_S_F, // orig_name
+     0xfff0707f, // mask
+     0x42005057, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VFMV_S_F
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFMV_V_F, // instr_name
+     riscv_instr_name_t.VFMV_V_F, // orig_name
+     0xfff0707f, // mask
+     0x5e005057, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VFMV_V_F
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNCVT_F_F_W, // instr_name
+     riscv_instr_name_t.VFNCVT_F_F_W, // orig_name
+     0xfc0ff07f, // mask
+     0x480a1057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFNCVT_F_F_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNCVT_F_X_W, // instr_name
+     riscv_instr_name_t.VFNCVT_F_X_W, // orig_name
+     0xfc0ff07f, // mask
+     0x48099057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFNCVT_F_X_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNCVT_F_XU_W, // instr_name
+     riscv_instr_name_t.VFNCVT_F_XU_W, // orig_name
+     0xfc0ff07f, // mask
+     0x48091057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFNCVT_F_XU_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNCVT_ROD_F_F_W, // instr_name
+     riscv_instr_name_t.VFNCVT_ROD_F_F_W, // orig_name
+     0xfc0ff07f, // mask
+     0x480a9057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFNCVT_ROD_F_F_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNCVT_RTZ_X_F_W, // instr_name
+     riscv_instr_name_t.VFNCVT_RTZ_X_F_W, // orig_name
+     0xfc0ff07f, // mask
+     0x480b9057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFNCVT_RTZ_X_F_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNCVT_RTZ_XU_F_W, // instr_name
+     riscv_instr_name_t.VFNCVT_RTZ_XU_F_W, // orig_name
+     0xfc0ff07f, // mask
+     0x480b1057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFNCVT_RTZ_XU_F_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNCVT_X_F_W, // instr_name
+     riscv_instr_name_t.VFNCVT_X_F_W, // orig_name
+     0xfc0ff07f, // mask
+     0x48089057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFNCVT_X_F_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNCVT_XU_F_W, // instr_name
+     riscv_instr_name_t.VFNCVT_XU_F_W, // orig_name
+     0xfc0ff07f, // mask
+     0x48081057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFNCVT_XU_F_W
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNMACC_VF, // instr_name
+     riscv_instr_name_t.VFNMACC_VF, // orig_name
+     0xfc00707f, // mask
+     0xb4005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFNMACC_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNMACC_VV, // instr_name
+     riscv_instr_name_t.VFNMACC_VV, // orig_name
+     0xfc00707f, // mask
+     0xb4001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFNMACC_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNMADD_VF, // instr_name
+     riscv_instr_name_t.VFNMADD_VF, // orig_name
+     0xfc00707f, // mask
+     0xa4005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFNMADD_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNMADD_VV, // instr_name
+     riscv_instr_name_t.VFNMADD_VV, // orig_name
+     0xfc00707f, // mask
+     0xa4001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFNMADD_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNMSAC_VF, // instr_name
+     riscv_instr_name_t.VFNMSAC_VF, // orig_name
+     0xfc00707f, // mask
+     0xbc005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFNMSAC_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNMSAC_VV, // instr_name
+     riscv_instr_name_t.VFNMSAC_VV, // orig_name
+     0xfc00707f, // mask
+     0xbc001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFNMSAC_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNMSUB_VF, // instr_name
+     riscv_instr_name_t.VFNMSUB_VF, // orig_name
+     0xfc00707f, // mask
+     0xac005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFNMSUB_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFNMSUB_VV, // instr_name
+     riscv_instr_name_t.VFNMSUB_VV, // orig_name
+     0xfc00707f, // mask
+     0xac001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFNMSUB_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFRDIV_VF, // instr_name
+     riscv_instr_name_t.VFRDIV_VF, // orig_name
+     0xfc00707f, // mask
+     0x84005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFRDIV_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFREC7_V, // instr_name
+     riscv_instr_name_t.VFREC7_V, // orig_name
+     0xfc0ff07f, // mask
+     0x4c029057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFREC7_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFREDMAX_VS, // instr_name
+     riscv_instr_name_t.VFREDMAX_VS, // orig_name
+     0xfc00707f, // mask
+     0x1c001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFREDMAX_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFREDMIN_VS, // instr_name
+     riscv_instr_name_t.VFREDMIN_VS, // orig_name
+     0xfc00707f, // mask
+     0x14001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFREDMIN_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFREDOSUM_VS, // instr_name
+     riscv_instr_name_t.VFREDOSUM_VS, // orig_name
+     0xfc00707f, // mask
+     0xc001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFREDOSUM_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFREDSUM_VS, // instr_name
+     riscv_instr_name_t.VFREDUSUM_VS, // orig_name
+     0xfc00707f, // mask
+     0x4001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v_aliases], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFREDSUM_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFREDUSUM_VS, // instr_name
+     riscv_instr_name_t.VFREDUSUM_VS, // orig_name
+     0xfc00707f, // mask
+     0x4001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFREDUSUM_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFRSQRT7_V, // instr_name
+     riscv_instr_name_t.VFRSQRT7_V, // orig_name
+     0xfc0ff07f, // mask
+     0x4c021057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFRSQRT7_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFRSUB_VF, // instr_name
+     riscv_instr_name_t.VFRSUB_VF, // orig_name
+     0xfc00707f, // mask
+     0x9c005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFRSUB_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFSGNJ_VF, // instr_name
+     riscv_instr_name_t.VFSGNJ_VF, // orig_name
+     0xfc00707f, // mask
+     0x20005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFSGNJ_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFSGNJ_VV, // instr_name
+     riscv_instr_name_t.VFSGNJ_VV, // orig_name
+     0xfc00707f, // mask
+     0x20001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFSGNJ_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFSGNJN_VF, // instr_name
+     riscv_instr_name_t.VFSGNJN_VF, // orig_name
+     0xfc00707f, // mask
+     0x24005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFSGNJN_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFSGNJN_VV, // instr_name
+     riscv_instr_name_t.VFSGNJN_VV, // orig_name
+     0xfc00707f, // mask
+     0x24001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFSGNJN_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFSGNJX_VF, // instr_name
+     riscv_instr_name_t.VFSGNJX_VF, // orig_name
+     0xfc00707f, // mask
+     0x28005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFSGNJX_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFSGNJX_VV, // instr_name
+     riscv_instr_name_t.VFSGNJX_VV, // orig_name
+     0xfc00707f, // mask
+     0x28001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFSGNJX_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFSLIDE1DOWN_VF, // instr_name
+     riscv_instr_name_t.VFSLIDE1DOWN_VF, // orig_name
+     0xfc00707f, // mask
+     0x3c005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFSLIDE1DOWN_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFSLIDE1UP_VF, // instr_name
+     riscv_instr_name_t.VFSLIDE1UP_VF, // orig_name
+     0xfc00707f, // mask
+     0x38005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFSLIDE1UP_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFSQRT_V, // instr_name
+     riscv_instr_name_t.VFSQRT_V, // orig_name
+     0xfc0ff07f, // mask
+     0x4c001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFSQRT_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFSUB_VF, // instr_name
+     riscv_instr_name_t.VFSUB_VF, // orig_name
+     0xfc00707f, // mask
+     0x8005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFSUB_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFSUB_VV, // instr_name
+     riscv_instr_name_t.VFSUB_VV, // orig_name
+     0xfc00707f, // mask
+     0x8001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFSUB_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWADD_VF, // instr_name
+     riscv_instr_name_t.VFWADD_VF, // orig_name
+     0xfc00707f, // mask
+     0xc0005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWADD_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWADD_VV, // instr_name
+     riscv_instr_name_t.VFWADD_VV, // orig_name
+     0xfc00707f, // mask
+     0xc0001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFWADD_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWADD_WF, // instr_name
+     riscv_instr_name_t.VFWADD_WF, // orig_name
+     0xfc00707f, // mask
+     0xd0005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWADD_WF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWADD_WV, // instr_name
+     riscv_instr_name_t.VFWADD_WV, // orig_name
+     0xfc00707f, // mask
+     0xd0001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFWADD_WV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWCVT_F_F_V, // instr_name
+     riscv_instr_name_t.VFWCVT_F_F_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48061057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWCVT_F_F_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWCVT_F_X_V, // instr_name
+     riscv_instr_name_t.VFWCVT_F_X_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48059057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWCVT_F_X_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWCVT_F_XU_V, // instr_name
+     riscv_instr_name_t.VFWCVT_F_XU_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48051057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWCVT_F_XU_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWCVT_RTZ_X_F_V, // instr_name
+     riscv_instr_name_t.VFWCVT_RTZ_X_F_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48079057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWCVT_RTZ_X_F_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWCVT_RTZ_XU_F_V, // instr_name
+     riscv_instr_name_t.VFWCVT_RTZ_XU_F_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48071057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWCVT_RTZ_XU_F_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWCVT_X_F_V, // instr_name
+     riscv_instr_name_t.VFWCVT_X_F_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48049057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWCVT_X_F_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWCVT_XU_F_V, // instr_name
+     riscv_instr_name_t.VFWCVT_XU_F_V, // orig_name
+     0xfc0ff07f, // mask
+     0x48041057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWCVT_XU_F_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWMACC_VF, // instr_name
+     riscv_instr_name_t.VFWMACC_VF, // orig_name
+     0xfc00707f, // mask
+     0xf0005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWMACC_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWMACC_VV, // instr_name
+     riscv_instr_name_t.VFWMACC_VV, // orig_name
+     0xfc00707f, // mask
+     0xf0001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFWMACC_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWMSAC_VF, // instr_name
+     riscv_instr_name_t.VFWMSAC_VF, // orig_name
+     0xfc00707f, // mask
+     0xf8005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWMSAC_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWMSAC_VV, // instr_name
+     riscv_instr_name_t.VFWMSAC_VV, // orig_name
+     0xfc00707f, // mask
+     0xf8001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFWMSAC_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWMUL_VF, // instr_name
+     riscv_instr_name_t.VFWMUL_VF, // orig_name
+     0xfc00707f, // mask
+     0xe0005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWMUL_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWMUL_VV, // instr_name
+     riscv_instr_name_t.VFWMUL_VV, // orig_name
+     0xfc00707f, // mask
+     0xe0001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFWMUL_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWNMACC_VF, // instr_name
+     riscv_instr_name_t.VFWNMACC_VF, // orig_name
+     0xfc00707f, // mask
+     0xf4005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWNMACC_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWNMACC_VV, // instr_name
+     riscv_instr_name_t.VFWNMACC_VV, // orig_name
+     0xfc00707f, // mask
+     0xf4001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFWNMACC_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWNMSAC_VF, // instr_name
+     riscv_instr_name_t.VFWNMSAC_VF, // orig_name
+     0xfc00707f, // mask
+     0xfc005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWNMSAC_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWNMSAC_VV, // instr_name
+     riscv_instr_name_t.VFWNMSAC_VV, // orig_name
+     0xfc00707f, // mask
+     0xfc001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFWNMSAC_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWREDOSUM_VS, // instr_name
+     riscv_instr_name_t.VFWREDOSUM_VS, // orig_name
+     0xfc00707f, // mask
+     0xcc001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFWREDOSUM_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWREDSUM_VS, // instr_name
+     riscv_instr_name_t.VFWREDUSUM_VS, // orig_name
+     0xfc00707f, // mask
+     0xc4001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v_aliases], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFWREDSUM_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWREDUSUM_VS, // instr_name
+     riscv_instr_name_t.VFWREDUSUM_VS, // orig_name
+     0xfc00707f, // mask
+     0xc4001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFWREDUSUM_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWSUB_VF, // instr_name
+     riscv_instr_name_t.VFWSUB_VF, // orig_name
+     0xfc00707f, // mask
+     0xc8005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWSUB_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWSUB_VV, // instr_name
+     riscv_instr_name_t.VFWSUB_VV, // orig_name
+     0xfc00707f, // mask
+     0xc8001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFWSUB_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWSUB_WF, // instr_name
+     riscv_instr_name_t.VFWSUB_WF, // orig_name
+     0xfc00707f, // mask
+     0xd8005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VFWSUB_WF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VFWSUB_WV, // instr_name
+     riscv_instr_name_t.VFWSUB_WV, // orig_name
+     0xfc00707f, // mask
+     0xd8001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VFWSUB_WV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VGHSH_VV, // instr_name
+     riscv_instr_name_t.VGHSH_VV, // orig_name
+     0xfe00707f, // mask
+     0xb2002077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvkg], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VGHSH_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VGMUL_VV, // instr_name
+     riscv_instr_name_t.VGMUL_VV, // orig_name
+     0xfe0ff07f, // mask
+     0xa208a077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvkg], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VGMUL_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VID_V, // instr_name
+     riscv_instr_name_t.VID_V, // orig_name
+     0xfdfff07f, // mask
+     0x5008a057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b10001, // _v_vars
+   ), // VID_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VIOTA_M, // instr_name
+     riscv_instr_name_t.VIOTA_M, // orig_name
+     0xfc0ff07f, // mask
+     0x50082057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VIOTA_M
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL1R_V, // instr_name
+     riscv_instr_name_t.VL1RE8_V, // orig_name
+     0xfff0707f, // mask
+     0x2800007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v_aliases], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL1R_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL1RE16_V, // instr_name
+     riscv_instr_name_t.VL1RE16_V, // orig_name
+     0xfff0707f, // mask
+     0x2805007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL1RE16_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL1RE32_V, // instr_name
+     riscv_instr_name_t.VL1RE32_V, // orig_name
+     0xfff0707f, // mask
+     0x2806007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL1RE32_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL1RE64_V, // instr_name
+     riscv_instr_name_t.VL1RE64_V, // orig_name
+     0xfff0707f, // mask
+     0x2807007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL1RE64_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL1RE8_V, // instr_name
+     riscv_instr_name_t.VL1RE8_V, // orig_name
+     0xfff0707f, // mask
+     0x2800007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL1RE8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL2R_V, // instr_name
+     riscv_instr_name_t.VL2RE8_V, // orig_name
+     0xfff0707f, // mask
+     0x22800007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v_aliases], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL2R_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL2RE16_V, // instr_name
+     riscv_instr_name_t.VL2RE16_V, // orig_name
+     0xfff0707f, // mask
+     0x22805007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL2RE16_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL2RE32_V, // instr_name
+     riscv_instr_name_t.VL2RE32_V, // orig_name
+     0xfff0707f, // mask
+     0x22806007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL2RE32_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL2RE64_V, // instr_name
+     riscv_instr_name_t.VL2RE64_V, // orig_name
+     0xfff0707f, // mask
+     0x22807007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL2RE64_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL2RE8_V, // instr_name
+     riscv_instr_name_t.VL2RE8_V, // orig_name
+     0xfff0707f, // mask
+     0x22800007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL2RE8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL4R_V, // instr_name
+     riscv_instr_name_t.VL4RE8_V, // orig_name
+     0xfff0707f, // mask
+     0x62800007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v_aliases], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL4R_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL4RE16_V, // instr_name
+     riscv_instr_name_t.VL4RE16_V, // orig_name
+     0xfff0707f, // mask
+     0x62805007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL4RE16_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL4RE32_V, // instr_name
+     riscv_instr_name_t.VL4RE32_V, // orig_name
+     0xfff0707f, // mask
+     0x62806007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL4RE32_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL4RE64_V, // instr_name
+     riscv_instr_name_t.VL4RE64_V, // orig_name
+     0xfff0707f, // mask
+     0x62807007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL4RE64_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL4RE8_V, // instr_name
+     riscv_instr_name_t.VL4RE8_V, // orig_name
+     0xfff0707f, // mask
+     0x62800007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL4RE8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL8R_V, // instr_name
+     riscv_instr_name_t.VL8RE8_V, // orig_name
+     0xfff0707f, // mask
+     0xe2800007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v_aliases], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL8R_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL8RE16_V, // instr_name
+     riscv_instr_name_t.VL8RE16_V, // orig_name
+     0xfff0707f, // mask
+     0xe2805007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL8RE16_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL8RE32_V, // instr_name
+     riscv_instr_name_t.VL8RE32_V, // orig_name
+     0xfff0707f, // mask
+     0xe2806007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL8RE32_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL8RE64_V, // instr_name
+     riscv_instr_name_t.VL8RE64_V, // orig_name
+     0xfff0707f, // mask
+     0xe2807007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL8RE64_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VL8RE8_V, // instr_name
+     riscv_instr_name_t.VL8RE8_V, // orig_name
+     0xfff0707f, // mask
+     0xe2800007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VL8RE8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE1024_V, // instr_name
+     riscv_instr_name_t.VLE1024_V, // orig_name
+     0x1df0707f, // mask
+     0x10007007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE1024_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE1024FF_V, // instr_name
+     riscv_instr_name_t.VLE1024FF_V, // orig_name
+     0x1df0707f, // mask
+     0x11007007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE1024FF_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE128_V, // instr_name
+     riscv_instr_name_t.VLE128_V, // orig_name
+     0x1df0707f, // mask
+     0x10000007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE128_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE128FF_V, // instr_name
+     riscv_instr_name_t.VLE128FF_V, // orig_name
+     0x1df0707f, // mask
+     0x11000007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE128FF_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE16_V, // instr_name
+     riscv_instr_name_t.VLE16_V, // orig_name
+     0x1df0707f, // mask
+     0x5007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE16_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE16FF_V, // instr_name
+     riscv_instr_name_t.VLE16FF_V, // orig_name
+     0x1df0707f, // mask
+     0x1005007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE16FF_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE1_V, // instr_name
+     riscv_instr_name_t.VLM_V, // orig_name
+     0xfff0707f, // mask
+     0x2b00007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v_aliases], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VLE1_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE256_V, // instr_name
+     riscv_instr_name_t.VLE256_V, // orig_name
+     0x1df0707f, // mask
+     0x10005007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE256_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE256FF_V, // instr_name
+     riscv_instr_name_t.VLE256FF_V, // orig_name
+     0x1df0707f, // mask
+     0x11005007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE256FF_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE32_V, // instr_name
+     riscv_instr_name_t.VLE32_V, // orig_name
+     0x1df0707f, // mask
+     0x6007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE32_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE32FF_V, // instr_name
+     riscv_instr_name_t.VLE32FF_V, // orig_name
+     0x1df0707f, // mask
+     0x1006007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE32FF_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE512_V, // instr_name
+     riscv_instr_name_t.VLE512_V, // orig_name
+     0x1df0707f, // mask
+     0x10006007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE512_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE512FF_V, // instr_name
+     riscv_instr_name_t.VLE512FF_V, // orig_name
+     0x1df0707f, // mask
+     0x11006007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE512FF_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE64_V, // instr_name
+     riscv_instr_name_t.VLE64_V, // orig_name
+     0x1df0707f, // mask
+     0x7007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE64_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE64FF_V, // instr_name
+     riscv_instr_name_t.VLE64FF_V, // orig_name
+     0x1df0707f, // mask
+     0x1007007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE64FF_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE8_V, // instr_name
+     riscv_instr_name_t.VLE8_V, // orig_name
+     0x1df0707f, // mask
+     0x7, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLE8FF_V, // instr_name
+     riscv_instr_name_t.VLE8FF_V, // orig_name
+     0x1df0707f, // mask
+     0x1000007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLE8FF_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLM_V, // instr_name
+     riscv_instr_name_t.VLM_V, // orig_name
+     0xfff0707f, // mask
+     0x2b00007, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VLM_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLOXEI1024_V, // instr_name
+     riscv_instr_name_t.VLOXEI1024_V, // orig_name
+     0x1c00707f, // mask
+     0x1c007007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLOXEI1024_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLOXEI128_V, // instr_name
+     riscv_instr_name_t.VLOXEI128_V, // orig_name
+     0x1c00707f, // mask
+     0x1c000007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLOXEI128_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLOXEI16_V, // instr_name
+     riscv_instr_name_t.VLOXEI16_V, // orig_name
+     0x1c00707f, // mask
+     0xc005007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLOXEI16_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLOXEI256_V, // instr_name
+     riscv_instr_name_t.VLOXEI256_V, // orig_name
+     0x1c00707f, // mask
+     0x1c005007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLOXEI256_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLOXEI32_V, // instr_name
+     riscv_instr_name_t.VLOXEI32_V, // orig_name
+     0x1c00707f, // mask
+     0xc006007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLOXEI32_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLOXEI512_V, // instr_name
+     riscv_instr_name_t.VLOXEI512_V, // orig_name
+     0x1c00707f, // mask
+     0x1c006007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLOXEI512_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLOXEI64_V, // instr_name
+     riscv_instr_name_t.VLOXEI64_V, // orig_name
+     0x1c00707f, // mask
+     0xc007007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLOXEI64_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLOXEI8_V, // instr_name
+     riscv_instr_name_t.VLOXEI8_V, // orig_name
+     0x1c00707f, // mask
+     0xc000007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLOXEI8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLSE1024_V, // instr_name
+     riscv_instr_name_t.VLSE1024_V, // orig_name
+     0x1c00707f, // mask
+     0x18007007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLSE1024_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLSE128_V, // instr_name
+     riscv_instr_name_t.VLSE128_V, // orig_name
+     0x1c00707f, // mask
+     0x18000007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLSE128_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLSE16_V, // instr_name
+     riscv_instr_name_t.VLSE16_V, // orig_name
+     0x1c00707f, // mask
+     0x8005007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLSE16_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLSE256_V, // instr_name
+     riscv_instr_name_t.VLSE256_V, // orig_name
+     0x1c00707f, // mask
+     0x18005007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLSE256_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLSE32_V, // instr_name
+     riscv_instr_name_t.VLSE32_V, // orig_name
+     0x1c00707f, // mask
+     0x8006007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLSE32_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLSE512_V, // instr_name
+     riscv_instr_name_t.VLSE512_V, // orig_name
+     0x1c00707f, // mask
+     0x18006007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLSE512_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLSE64_V, // instr_name
+     riscv_instr_name_t.VLSE64_V, // orig_name
+     0x1c00707f, // mask
+     0x8007007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLSE64_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLSE8_V, // instr_name
+     riscv_instr_name_t.VLSE8_V, // orig_name
+     0x1c00707f, // mask
+     0x8000007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010001, // _v_vars
+   ), // VLSE8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLUXEI1024_V, // instr_name
+     riscv_instr_name_t.VLUXEI1024_V, // orig_name
+     0x1c00707f, // mask
+     0x14007007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLUXEI1024_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLUXEI128_V, // instr_name
+     riscv_instr_name_t.VLUXEI128_V, // orig_name
+     0x1c00707f, // mask
+     0x14000007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLUXEI128_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLUXEI16_V, // instr_name
+     riscv_instr_name_t.VLUXEI16_V, // orig_name
+     0x1c00707f, // mask
+     0x4005007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLUXEI16_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLUXEI256_V, // instr_name
+     riscv_instr_name_t.VLUXEI256_V, // orig_name
+     0x1c00707f, // mask
+     0x14005007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLUXEI256_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLUXEI32_V, // instr_name
+     riscv_instr_name_t.VLUXEI32_V, // orig_name
+     0x1c00707f, // mask
+     0x4006007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLUXEI32_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLUXEI512_V, // instr_name
+     riscv_instr_name_t.VLUXEI512_V, // orig_name
+     0x1c00707f, // mask
+     0x14006007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLUXEI512_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLUXEI64_V, // instr_name
+     riscv_instr_name_t.VLUXEI64_V, // orig_name
+     0x1c00707f, // mask
+     0x4007007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLUXEI64_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VLUXEI8_V, // instr_name
+     riscv_instr_name_t.VLUXEI8_V, // orig_name
+     0x1c00707f, // mask
+     0x4000007, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011001, // _v_vars
+   ), // VLUXEI8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMACC_VV, // instr_name
+     riscv_instr_name_t.VMACC_VV, // orig_name
+     0xfc00707f, // mask
+     0xb4002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMACC_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMACC_VX, // instr_name
+     riscv_instr_name_t.VMACC_VX, // orig_name
+     0xfc00707f, // mask
+     0xb4006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMACC_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMADC_VI, // instr_name
+     riscv_instr_name_t.VMADC_VI, // orig_name
+     0xfe00707f, // mask
+     0x46003057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VMADC_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMADC_VIM, // instr_name
+     riscv_instr_name_t.VMADC_VIM, // orig_name
+     0xfe00707f, // mask
+     0x44003057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VMADC_VIM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMADC_VV, // instr_name
+     riscv_instr_name_t.VMADC_VV, // orig_name
+     0xfe00707f, // mask
+     0x46000057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VMADC_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMADC_VVM, // instr_name
+     riscv_instr_name_t.VMADC_VVM, // orig_name
+     0xfe00707f, // mask
+     0x44000057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VMADC_VVM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMADC_VX, // instr_name
+     riscv_instr_name_t.VMADC_VX, // orig_name
+     0xfe00707f, // mask
+     0x46004057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VMADC_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMADC_VXM, // instr_name
+     riscv_instr_name_t.VMADC_VXM, // orig_name
+     0xfe00707f, // mask
+     0x44004057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VMADC_VXM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMADD_VV, // instr_name
+     riscv_instr_name_t.VMADD_VV, // orig_name
+     0xfc00707f, // mask
+     0xa4002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMADD_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMADD_VX, // instr_name
+     riscv_instr_name_t.VMADD_VX, // orig_name
+     0xfc00707f, // mask
+     0xa4006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMADD_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMAND_MM, // instr_name
+     riscv_instr_name_t.VMAND_MM, // orig_name
+     0xfe00707f, // mask
+     0x66002057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VMAND_MM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMANDN_MM, // instr_name
+     riscv_instr_name_t.VMANDN_MM, // orig_name
+     0xfe00707f, // mask
+     0x62002057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VMANDN_MM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMANDNOT_MM, // instr_name
+     riscv_instr_name_t.VMANDN_MM, // orig_name
+     0xfc00707f, // mask
+     0x60002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v_aliases], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMANDNOT_MM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMAX_VV, // instr_name
+     riscv_instr_name_t.VMAX_VV, // orig_name
+     0xfc00707f, // mask
+     0x1c000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMAX_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMAX_VX, // instr_name
+     riscv_instr_name_t.VMAX_VX, // orig_name
+     0xfc00707f, // mask
+     0x1c004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMAX_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMAXU_VV, // instr_name
+     riscv_instr_name_t.VMAXU_VV, // orig_name
+     0xfc00707f, // mask
+     0x18000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMAXU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMAXU_VX, // instr_name
+     riscv_instr_name_t.VMAXU_VX, // orig_name
+     0xfc00707f, // mask
+     0x18004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMAXU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMERGE_VIM, // instr_name
+     riscv_instr_name_t.VMERGE_VIM, // orig_name
+     0xfe00707f, // mask
+     0x5c003057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VMERGE_VIM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMERGE_VVM, // instr_name
+     riscv_instr_name_t.VMERGE_VVM, // orig_name
+     0xfe00707f, // mask
+     0x5c000057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VMERGE_VVM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMERGE_VXM, // instr_name
+     riscv_instr_name_t.VMERGE_VXM, // orig_name
+     0xfe00707f, // mask
+     0x5c004057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VMERGE_VXM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMFEQ_VF, // instr_name
+     riscv_instr_name_t.VMFEQ_VF, // orig_name
+     0xfc00707f, // mask
+     0x60005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMFEQ_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMFEQ_VV, // instr_name
+     riscv_instr_name_t.VMFEQ_VV, // orig_name
+     0xfc00707f, // mask
+     0x60001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMFEQ_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMFGE_VF, // instr_name
+     riscv_instr_name_t.VMFGE_VF, // orig_name
+     0xfc00707f, // mask
+     0x7c005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMFGE_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMFGT_VF, // instr_name
+     riscv_instr_name_t.VMFGT_VF, // orig_name
+     0xfc00707f, // mask
+     0x74005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMFGT_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMFLE_VF, // instr_name
+     riscv_instr_name_t.VMFLE_VF, // orig_name
+     0xfc00707f, // mask
+     0x64005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMFLE_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMFLE_VV, // instr_name
+     riscv_instr_name_t.VMFLE_VV, // orig_name
+     0xfc00707f, // mask
+     0x64001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMFLE_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMFLT_VF, // instr_name
+     riscv_instr_name_t.VMFLT_VF, // orig_name
+     0xfc00707f, // mask
+     0x6c005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMFLT_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMFLT_VV, // instr_name
+     riscv_instr_name_t.VMFLT_VV, // orig_name
+     0xfc00707f, // mask
+     0x6c001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMFLT_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMFNE_VF, // instr_name
+     riscv_instr_name_t.VMFNE_VF, // orig_name
+     0xfc00707f, // mask
+     0x70005057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMFNE_VF
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMFNE_VV, // instr_name
+     riscv_instr_name_t.VMFNE_VV, // orig_name
+     0xfc00707f, // mask
+     0x70001057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMFNE_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMIN_VV, // instr_name
+     riscv_instr_name_t.VMIN_VV, // orig_name
+     0xfc00707f, // mask
+     0x14000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMIN_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMIN_VX, // instr_name
+     riscv_instr_name_t.VMIN_VX, // orig_name
+     0xfc00707f, // mask
+     0x14004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMIN_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMINU_VV, // instr_name
+     riscv_instr_name_t.VMINU_VV, // orig_name
+     0xfc00707f, // mask
+     0x10000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMINU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMINU_VX, // instr_name
+     riscv_instr_name_t.VMINU_VX, // orig_name
+     0xfc00707f, // mask
+     0x10004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMINU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMNAND_MM, // instr_name
+     riscv_instr_name_t.VMNAND_MM, // orig_name
+     0xfe00707f, // mask
+     0x76002057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VMNAND_MM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMNOR_MM, // instr_name
+     riscv_instr_name_t.VMNOR_MM, // orig_name
+     0xfe00707f, // mask
+     0x7a002057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VMNOR_MM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMOR_MM, // instr_name
+     riscv_instr_name_t.VMOR_MM, // orig_name
+     0xfe00707f, // mask
+     0x6a002057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VMOR_MM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMORN_MM, // instr_name
+     riscv_instr_name_t.VMORN_MM, // orig_name
+     0xfe00707f, // mask
+     0x72002057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VMORN_MM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMORNOT_MM, // instr_name
+     riscv_instr_name_t.VMORN_MM, // orig_name
+     0xfc00707f, // mask
+     0x70002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v_aliases], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMORNOT_MM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSBC_VV, // instr_name
+     riscv_instr_name_t.VMSBC_VV, // orig_name
+     0xfe00707f, // mask
+     0x4e000057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VMSBC_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSBC_VVM, // instr_name
+     riscv_instr_name_t.VMSBC_VVM, // orig_name
+     0xfe00707f, // mask
+     0x4c000057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VMSBC_VVM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSBC_VX, // instr_name
+     riscv_instr_name_t.VMSBC_VX, // orig_name
+     0xfe00707f, // mask
+     0x4e004057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VMSBC_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSBC_VXM, // instr_name
+     riscv_instr_name_t.VMSBC_VXM, // orig_name
+     0xfe00707f, // mask
+     0x4c004057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VMSBC_VXM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSBF_M, // instr_name
+     riscv_instr_name_t.VMSBF_M, // orig_name
+     0xfc0ff07f, // mask
+     0x5000a057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSBF_M
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSEQ_VI, // instr_name
+     riscv_instr_name_t.VMSEQ_VI, // orig_name
+     0xfc00707f, // mask
+     0x60003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSEQ_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSEQ_VV, // instr_name
+     riscv_instr_name_t.VMSEQ_VV, // orig_name
+     0xfc00707f, // mask
+     0x60000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMSEQ_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSEQ_VX, // instr_name
+     riscv_instr_name_t.VMSEQ_VX, // orig_name
+     0xfc00707f, // mask
+     0x60004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSEQ_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSGT_VI, // instr_name
+     riscv_instr_name_t.VMSGT_VI, // orig_name
+     0xfc00707f, // mask
+     0x7c003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSGT_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSGT_VX, // instr_name
+     riscv_instr_name_t.VMSGT_VX, // orig_name
+     0xfc00707f, // mask
+     0x7c004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSGT_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSGTU_VI, // instr_name
+     riscv_instr_name_t.VMSGTU_VI, // orig_name
+     0xfc00707f, // mask
+     0x78003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSGTU_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSGTU_VX, // instr_name
+     riscv_instr_name_t.VMSGTU_VX, // orig_name
+     0xfc00707f, // mask
+     0x78004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSGTU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSIF_M, // instr_name
+     riscv_instr_name_t.VMSIF_M, // orig_name
+     0xfc0ff07f, // mask
+     0x5001a057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSIF_M
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSLE_VI, // instr_name
+     riscv_instr_name_t.VMSLE_VI, // orig_name
+     0xfc00707f, // mask
+     0x74003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSLE_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSLE_VV, // instr_name
+     riscv_instr_name_t.VMSLE_VV, // orig_name
+     0xfc00707f, // mask
+     0x74000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMSLE_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSLE_VX, // instr_name
+     riscv_instr_name_t.VMSLE_VX, // orig_name
+     0xfc00707f, // mask
+     0x74004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSLE_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSLEU_VI, // instr_name
+     riscv_instr_name_t.VMSLEU_VI, // orig_name
+     0xfc00707f, // mask
+     0x70003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSLEU_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSLEU_VV, // instr_name
+     riscv_instr_name_t.VMSLEU_VV, // orig_name
+     0xfc00707f, // mask
+     0x70000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMSLEU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSLEU_VX, // instr_name
+     riscv_instr_name_t.VMSLEU_VX, // orig_name
+     0xfc00707f, // mask
+     0x70004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSLEU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSLT_VV, // instr_name
+     riscv_instr_name_t.VMSLT_VV, // orig_name
+     0xfc00707f, // mask
+     0x6c000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMSLT_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSLT_VX, // instr_name
+     riscv_instr_name_t.VMSLT_VX, // orig_name
+     0xfc00707f, // mask
+     0x6c004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSLT_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSLTU_VV, // instr_name
+     riscv_instr_name_t.VMSLTU_VV, // orig_name
+     0xfc00707f, // mask
+     0x68000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMSLTU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSLTU_VX, // instr_name
+     riscv_instr_name_t.VMSLTU_VX, // orig_name
+     0xfc00707f, // mask
+     0x68004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSLTU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSNE_VI, // instr_name
+     riscv_instr_name_t.VMSNE_VI, // orig_name
+     0xfc00707f, // mask
+     0x64003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSNE_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSNE_VV, // instr_name
+     riscv_instr_name_t.VMSNE_VV, // orig_name
+     0xfc00707f, // mask
+     0x64000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMSNE_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSNE_VX, // instr_name
+     riscv_instr_name_t.VMSNE_VX, // orig_name
+     0xfc00707f, // mask
+     0x64004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSNE_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMSOF_M, // instr_name
+     riscv_instr_name_t.VMSOF_M, // orig_name
+     0xfc0ff07f, // mask
+     0x50012057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMSOF_M
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMUL_VV, // instr_name
+     riscv_instr_name_t.VMUL_VV, // orig_name
+     0xfc00707f, // mask
+     0x94002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMUL_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMUL_VX, // instr_name
+     riscv_instr_name_t.VMUL_VX, // orig_name
+     0xfc00707f, // mask
+     0x94006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMUL_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMULH_VV, // instr_name
+     riscv_instr_name_t.VMULH_VV, // orig_name
+     0xfc00707f, // mask
+     0x9c002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMULH_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMULH_VX, // instr_name
+     riscv_instr_name_t.VMULH_VX, // orig_name
+     0xfc00707f, // mask
+     0x9c006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMULH_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMULHSU_VV, // instr_name
+     riscv_instr_name_t.VMULHSU_VV, // orig_name
+     0xfc00707f, // mask
+     0x98002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMULHSU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMULHSU_VX, // instr_name
+     riscv_instr_name_t.VMULHSU_VX, // orig_name
+     0xfc00707f, // mask
+     0x98006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMULHSU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMULHU_VV, // instr_name
+     riscv_instr_name_t.VMULHU_VV, // orig_name
+     0xfc00707f, // mask
+     0x90002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VMULHU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMULHU_VX, // instr_name
+     riscv_instr_name_t.VMULHU_VX, // orig_name
+     0xfc00707f, // mask
+     0x90006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VMULHU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMV1R_V, // instr_name
+     riscv_instr_name_t.VMV1R_V, // orig_name
+     0xfe0ff07f, // mask
+     0x9e003057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VMV1R_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMV2R_V, // instr_name
+     riscv_instr_name_t.VMV2R_V, // orig_name
+     0xfe0ff07f, // mask
+     0x9e00b057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VMV2R_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMV4R_V, // instr_name
+     riscv_instr_name_t.VMV4R_V, // orig_name
+     0xfe0ff07f, // mask
+     0x9e01b057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VMV4R_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMV8R_V, // instr_name
+     riscv_instr_name_t.VMV8R_V, // orig_name
+     0xfe0ff07f, // mask
+     0x9e03b057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VMV8R_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMV_S_X, // instr_name
+     riscv_instr_name_t.VMV_S_X, // orig_name
+     0xfff0707f, // mask
+     0x42006057, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VMV_S_X
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMV_V_I, // instr_name
+     riscv_instr_name_t.VMV_V_I, // orig_name
+     0xfff0707f, // mask
+     0x5e003057, // match
+     [riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VMV_V_I
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMV_V_V, // instr_name
+     riscv_instr_name_t.VMV_V_V, // orig_name
+     0xfff0707f, // mask
+     0x5e000057, // match
+     [riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b101, // _v_vars
+   ), // VMV_V_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMV_V_X, // instr_name
+     riscv_instr_name_t.VMV_V_X, // orig_name
+     0xfff0707f, // mask
+     0x5e004057, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1, // _v_vars
+   ), // VMV_V_X
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMV_X_S, // instr_name
+     riscv_instr_name_t.VMV_X_S, // orig_name
+     0xfe0ff07f, // mask
+     0x42002057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b1000, // _v_vars
+   ), // VMV_X_S
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMXNOR_MM, // instr_name
+     riscv_instr_name_t.VMXNOR_MM, // orig_name
+     0xfe00707f, // mask
+     0x7e002057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VMXNOR_MM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VMXOR_MM, // instr_name
+     riscv_instr_name_t.VMXOR_MM, // orig_name
+     0xfe00707f, // mask
+     0x6e002057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VMXOR_MM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNCLIP_WI, // instr_name
+     riscv_instr_name_t.VNCLIP_WI, // orig_name
+     0xfc00707f, // mask
+     0xbc003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VNCLIP_WI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNCLIP_WV, // instr_name
+     riscv_instr_name_t.VNCLIP_WV, // orig_name
+     0xfc00707f, // mask
+     0xbc000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VNCLIP_WV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNCLIP_WX, // instr_name
+     riscv_instr_name_t.VNCLIP_WX, // orig_name
+     0xfc00707f, // mask
+     0xbc004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VNCLIP_WX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNCLIPU_WI, // instr_name
+     riscv_instr_name_t.VNCLIPU_WI, // orig_name
+     0xfc00707f, // mask
+     0xb8003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VNCLIPU_WI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNCLIPU_WV, // instr_name
+     riscv_instr_name_t.VNCLIPU_WV, // orig_name
+     0xfc00707f, // mask
+     0xb8000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VNCLIPU_WV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNCLIPU_WX, // instr_name
+     riscv_instr_name_t.VNCLIPU_WX, // orig_name
+     0xfc00707f, // mask
+     0xb8004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VNCLIPU_WX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNMSAC_VV, // instr_name
+     riscv_instr_name_t.VNMSAC_VV, // orig_name
+     0xfc00707f, // mask
+     0xbc002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VNMSAC_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNMSAC_VX, // instr_name
+     riscv_instr_name_t.VNMSAC_VX, // orig_name
+     0xfc00707f, // mask
+     0xbc006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VNMSAC_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNMSUB_VV, // instr_name
+     riscv_instr_name_t.VNMSUB_VV, // orig_name
+     0xfc00707f, // mask
+     0xac002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VNMSUB_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNMSUB_VX, // instr_name
+     riscv_instr_name_t.VNMSUB_VX, // orig_name
+     0xfc00707f, // mask
+     0xac006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VNMSUB_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNSRA_WI, // instr_name
+     riscv_instr_name_t.VNSRA_WI, // orig_name
+     0xfc00707f, // mask
+     0xb4003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VNSRA_WI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNSRA_WV, // instr_name
+     riscv_instr_name_t.VNSRA_WV, // orig_name
+     0xfc00707f, // mask
+     0xb4000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VNSRA_WV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNSRA_WX, // instr_name
+     riscv_instr_name_t.VNSRA_WX, // orig_name
+     0xfc00707f, // mask
+     0xb4004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VNSRA_WX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNSRL_WI, // instr_name
+     riscv_instr_name_t.VNSRL_WI, // orig_name
+     0xfc00707f, // mask
+     0xb0003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VNSRL_WI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNSRL_WV, // instr_name
+     riscv_instr_name_t.VNSRL_WV, // orig_name
+     0xfc00707f, // mask
+     0xb0000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VNSRL_WV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VNSRL_WX, // instr_name
+     riscv_instr_name_t.VNSRL_WX, // orig_name
+     0xfc00707f, // mask
+     0xb0004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VNSRL_WX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VOR_VI, // instr_name
+     riscv_instr_name_t.VOR_VI, // orig_name
+     0xfc00707f, // mask
+     0x28003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VOR_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VOR_VV, // instr_name
+     riscv_instr_name_t.VOR_VV, // orig_name
+     0xfc00707f, // mask
+     0x28000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VOR_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VOR_VX, // instr_name
+     riscv_instr_name_t.VOR_VX, // orig_name
+     0xfc00707f, // mask
+     0x28004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VOR_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VPOPC_M, // instr_name
+     riscv_instr_name_t.VCPOP_M, // orig_name
+     0xfc0ff07f, // mask
+     0x40082057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_v_aliases], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b11000, // _v_vars
+   ), // VPOPC_M
+  riscv_instr_param_s(
+     riscv_instr_name_t.VREDAND_VS, // instr_name
+     riscv_instr_name_t.VREDAND_VS, // orig_name
+     0xfc00707f, // mask
+     0x4002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VREDAND_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VREDMAX_VS, // instr_name
+     riscv_instr_name_t.VREDMAX_VS, // orig_name
+     0xfc00707f, // mask
+     0x1c002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VREDMAX_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VREDMAXU_VS, // instr_name
+     riscv_instr_name_t.VREDMAXU_VS, // orig_name
+     0xfc00707f, // mask
+     0x18002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VREDMAXU_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VREDMIN_VS, // instr_name
+     riscv_instr_name_t.VREDMIN_VS, // orig_name
+     0xfc00707f, // mask
+     0x14002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VREDMIN_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VREDMINU_VS, // instr_name
+     riscv_instr_name_t.VREDMINU_VS, // orig_name
+     0xfc00707f, // mask
+     0x10002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VREDMINU_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VREDOR_VS, // instr_name
+     riscv_instr_name_t.VREDOR_VS, // orig_name
+     0xfc00707f, // mask
+     0x8002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VREDOR_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VREDSUM_VS, // instr_name
+     riscv_instr_name_t.VREDSUM_VS, // orig_name
+     0xfc00707f, // mask
+     0x2057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VREDSUM_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VREDXOR_VS, // instr_name
+     riscv_instr_name_t.VREDXOR_VS, // orig_name
+     0xfc00707f, // mask
+     0xc002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VREDXOR_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VREM_VV, // instr_name
+     riscv_instr_name_t.VREM_VV, // orig_name
+     0xfc00707f, // mask
+     0x8c002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VREM_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VREM_VX, // instr_name
+     riscv_instr_name_t.VREM_VX, // orig_name
+     0xfc00707f, // mask
+     0x8c006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VREM_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VREMU_VV, // instr_name
+     riscv_instr_name_t.VREMU_VV, // orig_name
+     0xfc00707f, // mask
+     0x88002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VREMU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VREMU_VX, // instr_name
+     riscv_instr_name_t.VREMU_VX, // orig_name
+     0xfc00707f, // mask
+     0x88006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VREMU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VREV8_V, // instr_name
+     riscv_instr_name_t.VREV8_V, // orig_name
+     0xfc0ff07f, // mask
+     0x4804a057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VREV8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VRGATHER_VI, // instr_name
+     riscv_instr_name_t.VRGATHER_VI, // orig_name
+     0xfc00707f, // mask
+     0x30003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VRGATHER_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VRGATHER_VV, // instr_name
+     riscv_instr_name_t.VRGATHER_VV, // orig_name
+     0xfc00707f, // mask
+     0x30000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VRGATHER_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VRGATHER_VX, // instr_name
+     riscv_instr_name_t.VRGATHER_VX, // orig_name
+     0xfc00707f, // mask
+     0x30004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VRGATHER_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VRGATHEREI16_VV, // instr_name
+     riscv_instr_name_t.VRGATHEREI16_VV, // orig_name
+     0xfc00707f, // mask
+     0x38000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VRGATHEREI16_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VROL_VV, // instr_name
+     riscv_instr_name_t.VROL_VV, // orig_name
+     0xfc00707f, // mask
+     0x54000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VROL_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VROL_VX, // instr_name
+     riscv_instr_name_t.VROL_VX, // orig_name
+     0xfc00707f, // mask
+     0x54004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VROL_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VROR_VI, // instr_name
+     riscv_instr_name_t.VROR_VI, // orig_name
+     0xf800707f, // mask
+     0x50003057, // match
+     [riscv_instr_var_t.zimm6hi, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.zimm6lo, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b110000, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VROR_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VROR_VV, // instr_name
+     riscv_instr_name_t.VROR_VV, // orig_name
+     0xfc00707f, // mask
+     0x50000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VROR_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VROR_VX, // instr_name
+     riscv_instr_name_t.VROR_VX, // orig_name
+     0xfc00707f, // mask
+     0x50004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VROR_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VRSUB_VI, // instr_name
+     riscv_instr_name_t.VRSUB_VI, // orig_name
+     0xfc00707f, // mask
+     0xc003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VRSUB_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VRSUB_VX, // instr_name
+     riscv_instr_name_t.VRSUB_VX, // orig_name
+     0xfc00707f, // mask
+     0xc004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VRSUB_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VS1R_V, // instr_name
+     riscv_instr_name_t.VS1R_V, // orig_name
+     0xfff0707f, // mask
+     0x2800027, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10, // _v_vars
+   ), // VS1R_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VS2R_V, // instr_name
+     riscv_instr_name_t.VS2R_V, // orig_name
+     0xfff0707f, // mask
+     0x22800027, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10, // _v_vars
+   ), // VS2R_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VS4R_V, // instr_name
+     riscv_instr_name_t.VS4R_V, // orig_name
+     0xfff0707f, // mask
+     0x62800027, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10, // _v_vars
+   ), // VS4R_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VS8R_V, // instr_name
+     riscv_instr_name_t.VS8R_V, // orig_name
+     0xfff0707f, // mask
+     0xe2800027, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10, // _v_vars
+   ), // VS8R_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSADD_VI, // instr_name
+     riscv_instr_name_t.VSADD_VI, // orig_name
+     0xfc00707f, // mask
+     0x84003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSADD_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSADD_VV, // instr_name
+     riscv_instr_name_t.VSADD_VV, // orig_name
+     0xfc00707f, // mask
+     0x84000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VSADD_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSADD_VX, // instr_name
+     riscv_instr_name_t.VSADD_VX, // orig_name
+     0xfc00707f, // mask
+     0x84004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSADD_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSADDU_VI, // instr_name
+     riscv_instr_name_t.VSADDU_VI, // orig_name
+     0xfc00707f, // mask
+     0x80003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSADDU_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSADDU_VV, // instr_name
+     riscv_instr_name_t.VSADDU_VV, // orig_name
+     0xfc00707f, // mask
+     0x80000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VSADDU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSADDU_VX, // instr_name
+     riscv_instr_name_t.VSADDU_VX, // orig_name
+     0xfc00707f, // mask
+     0x80004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSADDU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSBC_VVM, // instr_name
+     riscv_instr_name_t.VSBC_VVM, // orig_name
+     0xfe00707f, // mask
+     0x48000057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VSBC_VVM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSBC_VXM, // instr_name
+     riscv_instr_name_t.VSBC_VXM, // orig_name
+     0xfe00707f, // mask
+     0x48004057, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VSBC_VXM
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSE1024_V, // instr_name
+     riscv_instr_name_t.VSE1024_V, // orig_name
+     0x1df0707f, // mask
+     0x10007027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSE1024_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSE128_V, // instr_name
+     riscv_instr_name_t.VSE128_V, // orig_name
+     0x1df0707f, // mask
+     0x10000027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSE128_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSE16_V, // instr_name
+     riscv_instr_name_t.VSE16_V, // orig_name
+     0x1df0707f, // mask
+     0x5027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSE16_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSE1_V, // instr_name
+     riscv_instr_name_t.VSM_V, // orig_name
+     0xfff0707f, // mask
+     0x2b00027, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v_aliases], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10, // _v_vars
+   ), // VSE1_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSE256_V, // instr_name
+     riscv_instr_name_t.VSE256_V, // orig_name
+     0x1df0707f, // mask
+     0x10005027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSE256_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSE32_V, // instr_name
+     riscv_instr_name_t.VSE32_V, // orig_name
+     0x1df0707f, // mask
+     0x6027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSE32_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSE512_V, // instr_name
+     riscv_instr_name_t.VSE512_V, // orig_name
+     0x1df0707f, // mask
+     0x10006027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSE512_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSE64_V, // instr_name
+     riscv_instr_name_t.VSE64_V, // orig_name
+     0x1df0707f, // mask
+     0x7027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSE64_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSE8_V, // instr_name
+     riscv_instr_name_t.VSE8_V, // orig_name
+     0x1df0707f, // mask
+     0x27, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSE8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSETIVLI, // instr_name
+     riscv_instr_name_t.VSETIVLI, // orig_name
+     0xc000707f, // mask
+     0xc0007057, // match
+     [riscv_instr_var_t.zimm10, riscv_instr_var_t.zimm, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b1000000000000, // _imms
+     0b0, // _c_imms
+     0b100, // _v_imms
+     0b1, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // VSETIVLI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSETVL, // instr_name
+     riscv_instr_name_t.VSETVL, // orig_name
+     0xfe00707f, // mask
+     0x80007057, // match
+     [riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // VSETVL
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSETVLI, // instr_name
+     riscv_instr_name_t.VSETVLI, // orig_name
+     0x8000707f, // mask
+     0x7057, // match
+     [riscv_instr_var_t.zimm11, riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1000, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // VSETVLI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSEXT_VF2, // instr_name
+     riscv_instr_name_t.VSEXT_VF2, // orig_name
+     0xfc0ff07f, // mask
+     0x4803a057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSEXT_VF2
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSEXT_VF4, // instr_name
+     riscv_instr_name_t.VSEXT_VF4, // orig_name
+     0xfc0ff07f, // mask
+     0x4802a057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSEXT_VF4
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSEXT_VF8, // instr_name
+     riscv_instr_name_t.VSEXT_VF8, // orig_name
+     0xfc0ff07f, // mask
+     0x4801a057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSEXT_VF8
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSHA2CH_VV, // instr_name
+     riscv_instr_name_t.VSHA2CH_VV, // orig_name
+     0xfe00707f, // mask
+     0xba002077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvknha, riscv_extention_t.rv_zvknhb, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VSHA2CH_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSHA2CL_VV, // instr_name
+     riscv_instr_name_t.VSHA2CL_VV, // orig_name
+     0xfe00707f, // mask
+     0xbe002077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvknha, riscv_extention_t.rv_zvknhb, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VSHA2CL_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSHA2MS_VV, // instr_name
+     riscv_instr_name_t.VSHA2MS_VV, // orig_name
+     0xfe00707f, // mask
+     0xb6002077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvknha, riscv_extention_t.rv_zvknhb, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VSHA2MS_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSLIDE1DOWN_VX, // instr_name
+     riscv_instr_name_t.VSLIDE1DOWN_VX, // orig_name
+     0xfc00707f, // mask
+     0x3c006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSLIDE1DOWN_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSLIDE1UP_VX, // instr_name
+     riscv_instr_name_t.VSLIDE1UP_VX, // orig_name
+     0xfc00707f, // mask
+     0x38006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSLIDE1UP_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSLIDEDOWN_VI, // instr_name
+     riscv_instr_name_t.VSLIDEDOWN_VI, // orig_name
+     0xfc00707f, // mask
+     0x3c003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSLIDEDOWN_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSLIDEDOWN_VX, // instr_name
+     riscv_instr_name_t.VSLIDEDOWN_VX, // orig_name
+     0xfc00707f, // mask
+     0x3c004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSLIDEDOWN_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSLIDEUP_VI, // instr_name
+     riscv_instr_name_t.VSLIDEUP_VI, // orig_name
+     0xfc00707f, // mask
+     0x38003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSLIDEUP_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSLIDEUP_VX, // instr_name
+     riscv_instr_name_t.VSLIDEUP_VX, // orig_name
+     0xfc00707f, // mask
+     0x38004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSLIDEUP_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSLL_VI, // instr_name
+     riscv_instr_name_t.VSLL_VI, // orig_name
+     0xfc00707f, // mask
+     0x94003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSLL_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSLL_VV, // instr_name
+     riscv_instr_name_t.VSLL_VV, // orig_name
+     0xfc00707f, // mask
+     0x94000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VSLL_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSLL_VX, // instr_name
+     riscv_instr_name_t.VSLL_VX, // orig_name
+     0xfc00707f, // mask
+     0x94004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSLL_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSM3C_VI, // instr_name
+     riscv_instr_name_t.VSM3C_VI, // orig_name
+     0xfe00707f, // mask
+     0xae002077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.zimm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b10, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VSM3C_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSM3ME_VV, // instr_name
+     riscv_instr_name_t.VSM3ME_VV, // orig_name
+     0xfe00707f, // mask
+     0x82002077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1101, // _v_vars
+   ), // VSM3ME_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSM4K_VI, // instr_name
+     riscv_instr_name_t.VSM4K_VI, // orig_name
+     0xfe00707f, // mask
+     0x86002077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.zimm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b10, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VSM4K_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSM4R_VS, // instr_name
+     riscv_instr_name_t.VSM4R_VS, // orig_name
+     0xfe0ff07f, // mask
+     0xa6082077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VSM4R_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSM4R_VV, // instr_name
+     riscv_instr_name_t.VSM4R_VV, // orig_name
+     0xfe0ff07f, // mask
+     0xa2082077, // match
+     [riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b1001, // _v_vars
+   ), // VSM4R_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSM_V, // instr_name
+     riscv_instr_name_t.VSM_V, // orig_name
+     0xfff0707f, // mask
+     0x2b00027, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10, // _v_vars
+   ), // VSM_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSMUL_VV, // instr_name
+     riscv_instr_name_t.VSMUL_VV, // orig_name
+     0xfc00707f, // mask
+     0x9c000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VSMUL_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSMUL_VX, // instr_name
+     riscv_instr_name_t.VSMUL_VX, // orig_name
+     0xfc00707f, // mask
+     0x9c004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSMUL_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSOXEI1024_V, // instr_name
+     riscv_instr_name_t.VSOXEI1024_V, // orig_name
+     0x1c00707f, // mask
+     0x1c007027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSOXEI1024_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSOXEI128_V, // instr_name
+     riscv_instr_name_t.VSOXEI128_V, // orig_name
+     0x1c00707f, // mask
+     0x1c000027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSOXEI128_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSOXEI16_V, // instr_name
+     riscv_instr_name_t.VSOXEI16_V, // orig_name
+     0x1c00707f, // mask
+     0xc005027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSOXEI16_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSOXEI256_V, // instr_name
+     riscv_instr_name_t.VSOXEI256_V, // orig_name
+     0x1c00707f, // mask
+     0x1c005027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSOXEI256_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSOXEI32_V, // instr_name
+     riscv_instr_name_t.VSOXEI32_V, // orig_name
+     0x1c00707f, // mask
+     0xc006027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSOXEI32_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSOXEI512_V, // instr_name
+     riscv_instr_name_t.VSOXEI512_V, // orig_name
+     0x1c00707f, // mask
+     0x1c006027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSOXEI512_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSOXEI64_V, // instr_name
+     riscv_instr_name_t.VSOXEI64_V, // orig_name
+     0x1c00707f, // mask
+     0xc007027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSOXEI64_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSOXEI8_V, // instr_name
+     riscv_instr_name_t.VSOXEI8_V, // orig_name
+     0x1c00707f, // mask
+     0xc000027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSOXEI8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSRA_VI, // instr_name
+     riscv_instr_name_t.VSRA_VI, // orig_name
+     0xfc00707f, // mask
+     0xa4003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSRA_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSRA_VV, // instr_name
+     riscv_instr_name_t.VSRA_VV, // orig_name
+     0xfc00707f, // mask
+     0xa4000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VSRA_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSRA_VX, // instr_name
+     riscv_instr_name_t.VSRA_VX, // orig_name
+     0xfc00707f, // mask
+     0xa4004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSRA_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSRL_VI, // instr_name
+     riscv_instr_name_t.VSRL_VI, // orig_name
+     0xfc00707f, // mask
+     0xa0003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSRL_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSRL_VV, // instr_name
+     riscv_instr_name_t.VSRL_VV, // orig_name
+     0xfc00707f, // mask
+     0xa0000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VSRL_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSRL_VX, // instr_name
+     riscv_instr_name_t.VSRL_VX, // orig_name
+     0xfc00707f, // mask
+     0xa0004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSRL_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSE1024_V, // instr_name
+     riscv_instr_name_t.VSSE1024_V, // orig_name
+     0x1c00707f, // mask
+     0x18007027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSSE1024_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSE128_V, // instr_name
+     riscv_instr_name_t.VSSE128_V, // orig_name
+     0x1c00707f, // mask
+     0x18000027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSSE128_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSE16_V, // instr_name
+     riscv_instr_name_t.VSSE16_V, // orig_name
+     0x1c00707f, // mask
+     0x8005027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSSE16_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSE256_V, // instr_name
+     riscv_instr_name_t.VSSE256_V, // orig_name
+     0x1c00707f, // mask
+     0x18005027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSSE256_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSE32_V, // instr_name
+     riscv_instr_name_t.VSSE32_V, // orig_name
+     0x1c00707f, // mask
+     0x8006027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSSE32_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSE512_V, // instr_name
+     riscv_instr_name_t.VSSE512_V, // orig_name
+     0x1c00707f, // mask
+     0x18006027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSSE512_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSE64_V, // instr_name
+     riscv_instr_name_t.VSSE64_V, // orig_name
+     0x1c00707f, // mask
+     0x8007027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSSE64_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSE8_V, // instr_name
+     riscv_instr_name_t.VSSE8_V, // orig_name
+     0x1c00707f, // mask
+     0x8000027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.rs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1100, // _vars
+     0b0, // _c_vars
+     0b10010010, // _v_vars
+   ), // VSSE8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSRA_VI, // instr_name
+     riscv_instr_name_t.VSSRA_VI, // orig_name
+     0xfc00707f, // mask
+     0xac003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSSRA_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSRA_VV, // instr_name
+     riscv_instr_name_t.VSSRA_VV, // orig_name
+     0xfc00707f, // mask
+     0xac000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VSSRA_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSRA_VX, // instr_name
+     riscv_instr_name_t.VSSRA_VX, // orig_name
+     0xfc00707f, // mask
+     0xac004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSSRA_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSRL_VI, // instr_name
+     riscv_instr_name_t.VSSRL_VI, // orig_name
+     0xfc00707f, // mask
+     0xa8003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSSRL_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSRL_VV, // instr_name
+     riscv_instr_name_t.VSSRL_VV, // orig_name
+     0xfc00707f, // mask
+     0xa8000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VSSRL_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSRL_VX, // instr_name
+     riscv_instr_name_t.VSSRL_VX, // orig_name
+     0xfc00707f, // mask
+     0xa8004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSSRL_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSUB_VV, // instr_name
+     riscv_instr_name_t.VSSUB_VV, // orig_name
+     0xfc00707f, // mask
+     0x8c000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VSSUB_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSUB_VX, // instr_name
+     riscv_instr_name_t.VSSUB_VX, // orig_name
+     0xfc00707f, // mask
+     0x8c004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSSUB_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSUBU_VV, // instr_name
+     riscv_instr_name_t.VSSUBU_VV, // orig_name
+     0xfc00707f, // mask
+     0x88000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VSSUBU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSSUBU_VX, // instr_name
+     riscv_instr_name_t.VSSUBU_VX, // orig_name
+     0xfc00707f, // mask
+     0x88004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSSUBU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSUB_VV, // instr_name
+     riscv_instr_name_t.VSUB_VV, // orig_name
+     0xfc00707f, // mask
+     0x8000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VSUB_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSUB_VX, // instr_name
+     riscv_instr_name_t.VSUB_VX, // orig_name
+     0xfc00707f, // mask
+     0x8004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VSUB_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSUXEI1024_V, // instr_name
+     riscv_instr_name_t.VSUXEI1024_V, // orig_name
+     0x1c00707f, // mask
+     0x14007027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSUXEI1024_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSUXEI128_V, // instr_name
+     riscv_instr_name_t.VSUXEI128_V, // orig_name
+     0x1c00707f, // mask
+     0x14000027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSUXEI128_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSUXEI16_V, // instr_name
+     riscv_instr_name_t.VSUXEI16_V, // orig_name
+     0x1c00707f, // mask
+     0x4005027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSUXEI16_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSUXEI256_V, // instr_name
+     riscv_instr_name_t.VSUXEI256_V, // orig_name
+     0x1c00707f, // mask
+     0x14005027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSUXEI256_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSUXEI32_V, // instr_name
+     riscv_instr_name_t.VSUXEI32_V, // orig_name
+     0x1c00707f, // mask
+     0x4006027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSUXEI32_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSUXEI512_V, // instr_name
+     riscv_instr_name_t.VSUXEI512_V, // orig_name
+     0x1c00707f, // mask
+     0x14006027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSUXEI512_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSUXEI64_V, // instr_name
+     riscv_instr_name_t.VSUXEI64_V, // orig_name
+     0x1c00707f, // mask
+     0x4007027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSUXEI64_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VSUXEI8_V, // instr_name
+     riscv_instr_name_t.VSUXEI8_V, // orig_name
+     0x1c00707f, // mask
+     0x4000027, // match
+     [riscv_instr_var_t.nf, riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vs3], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b10011010, // _v_vars
+   ), // VSUXEI8_V
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWADD_VV, // instr_name
+     riscv_instr_name_t.VWADD_VV, // orig_name
+     0xfc00707f, // mask
+     0xc4002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWADD_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWADD_VX, // instr_name
+     riscv_instr_name_t.VWADD_VX, // orig_name
+     0xfc00707f, // mask
+     0xc4006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWADD_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWADD_WV, // instr_name
+     riscv_instr_name_t.VWADD_WV, // orig_name
+     0xfc00707f, // mask
+     0xd4002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWADD_WV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWADD_WX, // instr_name
+     riscv_instr_name_t.VWADD_WX, // orig_name
+     0xfc00707f, // mask
+     0xd4006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWADD_WX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWADDU_VV, // instr_name
+     riscv_instr_name_t.VWADDU_VV, // orig_name
+     0xfc00707f, // mask
+     0xc0002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWADDU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWADDU_VX, // instr_name
+     riscv_instr_name_t.VWADDU_VX, // orig_name
+     0xfc00707f, // mask
+     0xc0006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWADDU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWADDU_WV, // instr_name
+     riscv_instr_name_t.VWADDU_WV, // orig_name
+     0xfc00707f, // mask
+     0xd0002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWADDU_WV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWADDU_WX, // instr_name
+     riscv_instr_name_t.VWADDU_WX, // orig_name
+     0xfc00707f, // mask
+     0xd0006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWADDU_WX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWMACC_VV, // instr_name
+     riscv_instr_name_t.VWMACC_VV, // orig_name
+     0xfc00707f, // mask
+     0xf4002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWMACC_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWMACC_VX, // instr_name
+     riscv_instr_name_t.VWMACC_VX, // orig_name
+     0xfc00707f, // mask
+     0xf4006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWMACC_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWMACCSU_VV, // instr_name
+     riscv_instr_name_t.VWMACCSU_VV, // orig_name
+     0xfc00707f, // mask
+     0xfc002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWMACCSU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWMACCSU_VX, // instr_name
+     riscv_instr_name_t.VWMACCSU_VX, // orig_name
+     0xfc00707f, // mask
+     0xfc006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWMACCSU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWMACCU_VV, // instr_name
+     riscv_instr_name_t.VWMACCU_VV, // orig_name
+     0xfc00707f, // mask
+     0xf0002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWMACCU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWMACCU_VX, // instr_name
+     riscv_instr_name_t.VWMACCU_VX, // orig_name
+     0xfc00707f, // mask
+     0xf0006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWMACCU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWMACCUS_VX, // instr_name
+     riscv_instr_name_t.VWMACCUS_VX, // orig_name
+     0xfc00707f, // mask
+     0xf8006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWMACCUS_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWMUL_VV, // instr_name
+     riscv_instr_name_t.VWMUL_VV, // orig_name
+     0xfc00707f, // mask
+     0xec002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWMUL_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWMUL_VX, // instr_name
+     riscv_instr_name_t.VWMUL_VX, // orig_name
+     0xfc00707f, // mask
+     0xec006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWMUL_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWMULSU_VV, // instr_name
+     riscv_instr_name_t.VWMULSU_VV, // orig_name
+     0xfc00707f, // mask
+     0xe8002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWMULSU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWMULSU_VX, // instr_name
+     riscv_instr_name_t.VWMULSU_VX, // orig_name
+     0xfc00707f, // mask
+     0xe8006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWMULSU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWMULU_VV, // instr_name
+     riscv_instr_name_t.VWMULU_VV, // orig_name
+     0xfc00707f, // mask
+     0xe0002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWMULU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWMULU_VX, // instr_name
+     riscv_instr_name_t.VWMULU_VX, // orig_name
+     0xfc00707f, // mask
+     0xe0006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWMULU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWREDSUM_VS, // instr_name
+     riscv_instr_name_t.VWREDSUM_VS, // orig_name
+     0xfc00707f, // mask
+     0xc4000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWREDSUM_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWREDSUMU_VS, // instr_name
+     riscv_instr_name_t.VWREDSUMU_VS, // orig_name
+     0xfc00707f, // mask
+     0xc0000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWREDSUMU_VS
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWSLL_VI, // instr_name
+     riscv_instr_name_t.VWSLL_VI, // orig_name
+     0xfc00707f, // mask
+     0xd4003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.zimm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b10, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWSLL_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWSLL_VV, // instr_name
+     riscv_instr_name_t.VWSLL_VV, // orig_name
+     0xfc00707f, // mask
+     0xd4000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWSLL_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWSLL_VX, // instr_name
+     riscv_instr_name_t.VWSLL_VX, // orig_name
+     0xfc00707f, // mask
+     0xd4004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_zvks, riscv_extention_t.rv_zvkn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWSLL_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWSUB_VV, // instr_name
+     riscv_instr_name_t.VWSUB_VV, // orig_name
+     0xfc00707f, // mask
+     0xcc002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWSUB_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWSUB_VX, // instr_name
+     riscv_instr_name_t.VWSUB_VX, // orig_name
+     0xfc00707f, // mask
+     0xcc006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWSUB_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWSUB_WV, // instr_name
+     riscv_instr_name_t.VWSUB_WV, // orig_name
+     0xfc00707f, // mask
+     0xdc002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWSUB_WV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWSUB_WX, // instr_name
+     riscv_instr_name_t.VWSUB_WX, // orig_name
+     0xfc00707f, // mask
+     0xdc006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWSUB_WX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWSUBU_VV, // instr_name
+     riscv_instr_name_t.VWSUBU_VV, // orig_name
+     0xfc00707f, // mask
+     0xc8002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWSUBU_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWSUBU_VX, // instr_name
+     riscv_instr_name_t.VWSUBU_VX, // orig_name
+     0xfc00707f, // mask
+     0xc8006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWSUBU_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWSUBU_WV, // instr_name
+     riscv_instr_name_t.VWSUBU_WV, // orig_name
+     0xfc00707f, // mask
+     0xd8002057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VWSUBU_WV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VWSUBU_WX, // instr_name
+     riscv_instr_name_t.VWSUBU_WX, // orig_name
+     0xfc00707f, // mask
+     0xd8006057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VWSUBU_WX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VXOR_VI, // instr_name
+     riscv_instr_name_t.VXOR_VI, // orig_name
+     0xfc00707f, // mask
+     0x2c003057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.simm5, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b1, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VXOR_VI
+  riscv_instr_param_s(
+     riscv_instr_name_t.VXOR_VV, // instr_name
+     riscv_instr_name_t.VXOR_VV, // orig_name
+     0xfc00707f, // mask
+     0x2c000057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11101, // _v_vars
+   ), // VXOR_VV
+  riscv_instr_param_s(
+     riscv_instr_name_t.VXOR_VX, // instr_name
+     riscv_instr_name_t.VXOR_VX, // orig_name
+     0xfc00707f, // mask
+     0x2c004057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.rs1, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b100, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VXOR_VX
+  riscv_instr_param_s(
+     riscv_instr_name_t.VZEXT_VF2, // instr_name
+     riscv_instr_name_t.VZEXT_VF2, // orig_name
+     0xfc0ff07f, // mask
+     0x48032057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VZEXT_VF2
+  riscv_instr_param_s(
+     riscv_instr_name_t.VZEXT_VF4, // instr_name
+     riscv_instr_name_t.VZEXT_VF4, // orig_name
+     0xfc0ff07f, // mask
+     0x48022057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VZEXT_VF4
+  riscv_instr_param_s(
+     riscv_instr_name_t.VZEXT_VF8, // instr_name
+     riscv_instr_name_t.VZEXT_VF8, // orig_name
+     0xfc0ff07f, // mask
+     0x48012057, // match
+     [riscv_instr_var_t.vm, riscv_instr_var_t.vs2, riscv_instr_var_t.vd], // variables
+     [riscv_extention_t.rv_v], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b11001, // _v_vars
+   ), // VZEXT_VF8
+  riscv_instr_param_s(
+     riscv_instr_name_t.WFI, // instr_name
+     riscv_instr_name_t.WFI, // orig_name
+     0xffffffff, // mask
+     0x10500073, // match
+     [], // variables
+     [riscv_extention_t.rv_system], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b0, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // WFI
+  riscv_instr_param_s(
+     riscv_instr_name_t.XNOR, // instr_name
+     riscv_instr_name_t.XNOR, // orig_name
+     0xfe00707f, // mask
+     0x40004033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbb, riscv_extention_t.rv_zbp, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // XNOR
+  riscv_instr_param_s(
+     riscv_instr_name_t.XOR, // instr_name
+     riscv_instr_name_t.XOR, // orig_name
+     0xfe00707f, // mask
+     0x4033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // XOR
+  riscv_instr_param_s(
+     riscv_instr_name_t.XORI, // instr_name
+     riscv_instr_name_t.XORI, // orig_name
+     0x707f, // mask
+     0x4013, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.imm12], // variables
+     [riscv_extention_t.rv_i], // extentions
+     0b100, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // XORI
+  riscv_instr_param_s(
+     riscv_instr_name_t.XPERM16, // instr_name
+     riscv_instr_name_t.XPERM16, // orig_name
+     0xfe00707f, // mask
+     0x28006033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // XPERM16
+  riscv_instr_param_s(
+     riscv_instr_name_t.XPERM32, // instr_name
+     riscv_instr_name_t.XPERM32, // orig_name
+     0xfe00707f, // mask
+     0x28000033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv64_zbp], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // XPERM32
+  riscv_instr_param_s(
+     riscv_instr_name_t.XPERM4, // instr_name
+     riscv_instr_name_t.XPERM4, // orig_name
+     0xfe00707f, // mask
+     0x28002033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbp, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // XPERM4
+  riscv_instr_param_s(
+     riscv_instr_name_t.XPERM8, // instr_name
+     riscv_instr_name_t.XPERM8, // orig_name
+     0xfe00707f, // mask
+     0x28004033, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1, riscv_instr_var_t.rs2], // variables
+     [riscv_extention_t.rv_zbp, ], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b1101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // XPERM8
+  riscv_instr_param_s(
+     riscv_instr_name_t.ZEXT_H, // instr_name
+     riscv_instr_name_t.PACKW, // orig_name
+     0xfff0707f, // mask
+     0x800403b, // match
+     [riscv_instr_var_t.rd, riscv_instr_var_t.rs1], // variables
+     [riscv_extention_t.rv64_zbb], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ZEXT_H
+  riscv_instr_param_s(
+     riscv_instr_name_t.ZUNPKD810, // instr_name
+     riscv_instr_name_t.ZUNPKD810, // orig_name
+     0xfff0707f, // mask
+     0xacc00077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ZUNPKD810
+  riscv_instr_param_s(
+     riscv_instr_name_t.ZUNPKD820, // instr_name
+     riscv_instr_name_t.ZUNPKD820, // orig_name
+     0xfff0707f, // mask
+     0xacd00077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ZUNPKD820
+  riscv_instr_param_s(
+     riscv_instr_name_t.ZUNPKD830, // instr_name
+     riscv_instr_name_t.ZUNPKD830, // orig_name
+     0xfff0707f, // mask
+     0xace00077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ZUNPKD830
+  riscv_instr_param_s(
+     riscv_instr_name_t.ZUNPKD831, // instr_name
+     riscv_instr_name_t.ZUNPKD831, // orig_name
+     0xfff0707f, // mask
+     0xacf00077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ZUNPKD831
+  riscv_instr_param_s(
+     riscv_instr_name_t.ZUNPKD832, // instr_name
+     riscv_instr_name_t.ZUNPKD832, // orig_name
+     0xfff0707f, // mask
+     0xad700077, // match
+     [riscv_instr_var_t.rs1, riscv_instr_var_t.rd], // variables
+     [riscv_extention_t.rv_zpn], // extentions
+     0b0, // _imms
+     0b0, // _c_imms
+     0b0, // _v_imms
+     0b101, // _vars
+     0b0, // _c_vars
+     0b0, // _v_vars
+   ), // ZUNPKD832
+];
diff --git a/euvm/riscv/gen/riscv_opcodes_yaml.d b/euvm/riscv/gen/riscv_opcodes_yaml.d
new file mode 100644
index 00000000..53d52de7
--- /dev/null
+++ b/euvm/riscv/gen/riscv_opcodes_yaml.d
@@ -0,0 +1,633 @@
+import dyaml;
+
+import std.algorithm: canFind;
+import std.format: format;
+import std.stdio: write, writeln, writef, writefln, stderr;
+
+string[] riscv_dv_handled_extentions = ["rv_s",
+					"rv_system",
+					"rv_sdext",
+					"rv_i",
+					"rv32_i",
+					"rv64_i",
+					"rv_c",
+					"rv32_c",
+					"rv_c_d",
+					"rv64_c",
+					"rv128_c",
+					"rv_zba",
+					"rv64_zba",
+					"rv_zbb",
+					"rv64_zbb",
+					"rv_zbc",
+					"rv_zbe",
+					"rv64_zbe",
+					"rv_zbf",
+					"rv64_zbf",
+					"rv64_zbm",
+					"rv_zbp",
+					"rv64_zbp",
+					"rv_zbr",
+					"rv64_zbr",
+					"rv_zbs",
+					"rv64_zbs",
+					"rv_zbt",
+					"rv64_zbt",
+					"rv64_zks",
+					"rv_b",
+					"rv64_b",
+					"rv_m",
+					"rv64_m",
+					"rv_f",
+					"rv32_c_f",
+					"rv64_f",
+					"rv_d",
+					"rv32_c_d",
+					"rv64_d",
+					"rv_a",
+					"rv64_a",
+					"rv_v",
+					"rv_v_aliases",
+					"rv_zicsr",
+					"rv_zifencei",
+					"rv_zvknha",
+					"rv_zvknhb",
+					"rv_zpn",
+					"rv32_zpn",
+					"rv64_zpn",
+					"rv_zvkg",
+					"rv_zvkn",
+					"rv_zvks"
+					];
+
+string[] riscv_dv_handled_instrs;
+
+struct riscv_opcodes_args_params_s {
+  string               _arg;
+  ubyte                _msb;
+  ubyte                _lsb;
+}
+
+riscv_opcodes_args_params_s[] riscv_opcodes_args_params =
+  [
+   riscv_opcodes_args_params_s("rd", 11, 7),
+   riscv_opcodes_args_params_s("rt", 19, 15),
+   riscv_opcodes_args_params_s("rs1", 19, 15),
+   riscv_opcodes_args_params_s("rs2", 24, 20),
+   riscv_opcodes_args_params_s("rs3", 31, 27),
+   riscv_opcodes_args_params_s("aqrl", 26, 25),
+   riscv_opcodes_args_params_s("aq", 26, 26),
+   riscv_opcodes_args_params_s("rl", 25, 25),
+   riscv_opcodes_args_params_s("fm", 31, 28),
+   riscv_opcodes_args_params_s("pred", 27, 24),
+   riscv_opcodes_args_params_s("succ", 23, 20),
+   riscv_opcodes_args_params_s("rm", 14, 12),
+   riscv_opcodes_args_params_s("funct3", 14, 12),
+   riscv_opcodes_args_params_s("funct2", 26, 25),
+   riscv_opcodes_args_params_s("imm20", 31, 12),
+   riscv_opcodes_args_params_s("jimm20", 31, 12),
+   riscv_opcodes_args_params_s("imm12", 31, 20),
+   riscv_opcodes_args_params_s("csr", 31, 20),
+   riscv_opcodes_args_params_s("imm12hi", 31, 25),
+   riscv_opcodes_args_params_s("bimm12hi", 31, 25),
+   riscv_opcodes_args_params_s("imm12lo", 11, 7),
+   riscv_opcodes_args_params_s("bimm12lo", 11, 7),
+   riscv_opcodes_args_params_s("zimm", 19, 15),
+   riscv_opcodes_args_params_s("shamtq", 26, 20),
+   riscv_opcodes_args_params_s("shamtw", 24, 20),
+   riscv_opcodes_args_params_s("shamtw4", 23, 20),
+   riscv_opcodes_args_params_s("shamtd", 25, 20),
+   riscv_opcodes_args_params_s("bs", 31, 30),
+   riscv_opcodes_args_params_s("rnum", 23, 20),
+   riscv_opcodes_args_params_s("rc", 29, 25),
+   riscv_opcodes_args_params_s("imm2", 21, 20),
+   riscv_opcodes_args_params_s("imm3", 22, 20),
+   riscv_opcodes_args_params_s("imm4", 23, 20),
+   riscv_opcodes_args_params_s("imm5", 24, 20),
+   riscv_opcodes_args_params_s("imm6", 25, 20),
+   riscv_opcodes_args_params_s("opcode", 6,0),
+   riscv_opcodes_args_params_s("funct7", 31,25),
+
+   //  for vectors
+   riscv_opcodes_args_params_s("vd", 11, 7),
+   riscv_opcodes_args_params_s("vs3", 11, 7),
+   riscv_opcodes_args_params_s("vs1", 19, 15),
+   riscv_opcodes_args_params_s("vs2", 24, 20),
+   riscv_opcodes_args_params_s("vm", 25, 25),
+   riscv_opcodes_args_params_s("wd", 26, 26),
+   riscv_opcodes_args_params_s("amoop", 31, 27),
+   riscv_opcodes_args_params_s("nf", 31, 29),
+   riscv_opcodes_args_params_s("simm5", 19, 15),
+   riscv_opcodes_args_params_s("zimm5", 19, 15),
+   riscv_opcodes_args_params_s("zimm10", 29, 20),
+   riscv_opcodes_args_params_s("zimm11", 30, 20),
+   riscv_opcodes_args_params_s("zimm6hi", 26, 26),
+   riscv_opcodes_args_params_s("zimm6lo", 19, 15),
+
+
+   // compressed immediates and fields
+   riscv_opcodes_args_params_s("c_nzuimm10", 12, 5),
+   riscv_opcodes_args_params_s("c_uimm7lo", 6, 5),
+   riscv_opcodes_args_params_s("c_uimm7hi", 12, 10),
+   riscv_opcodes_args_params_s("c_uimm8lo", 6, 5),
+   riscv_opcodes_args_params_s("c_uimm8hi", 12, 10),
+   riscv_opcodes_args_params_s("c_uimm9lo", 6, 5),
+   riscv_opcodes_args_params_s("c_uimm9hi", 12, 10),
+   riscv_opcodes_args_params_s("c_nzimm6lo", 6, 2),
+   riscv_opcodes_args_params_s("c_nzimm6hi", 12, 12),
+   riscv_opcodes_args_params_s("c_imm6lo", 6, 2),
+   riscv_opcodes_args_params_s("c_imm6hi", 12, 12),
+   riscv_opcodes_args_params_s("c_nzimm10hi", 12, 12),
+   riscv_opcodes_args_params_s("c_nzimm10lo", 6, 2),
+   riscv_opcodes_args_params_s("c_nzimm18hi", 12, 12),
+   riscv_opcodes_args_params_s("c_nzimm18lo", 6, 2),
+   riscv_opcodes_args_params_s("c_imm12", 12, 2),
+   riscv_opcodes_args_params_s("c_bimm9lo", 6, 2),
+   riscv_opcodes_args_params_s("c_bimm9hi", 12, 10),
+   riscv_opcodes_args_params_s("c_nzuimm5", 6, 2),
+   riscv_opcodes_args_params_s("c_nzuimm6lo", 6, 2),
+   riscv_opcodes_args_params_s("c_nzuimm6hi", 12, 12),
+   riscv_opcodes_args_params_s("c_uimm8splo", 6, 2),
+   riscv_opcodes_args_params_s("c_uimm8sphi", 12, 12),
+   riscv_opcodes_args_params_s("c_uimm8sp_s", 12, 7),
+   riscv_opcodes_args_params_s("c_uimm10splo", 6, 2),
+   riscv_opcodes_args_params_s("c_uimm10sphi", 12, 12),
+   riscv_opcodes_args_params_s("c_uimm9splo", 6, 2),
+   riscv_opcodes_args_params_s("c_uimm9sphi", 12, 12),
+   riscv_opcodes_args_params_s("c_uimm10sp_s", 12, 7),
+   riscv_opcodes_args_params_s("c_uimm9sp_s", 12, 7),
+   riscv_opcodes_args_params_s("c_uimm2", 6, 5),
+   riscv_opcodes_args_params_s("c_uimm1", 5, 5),
+   riscv_opcodes_args_params_s("c_rlist", 7, 4),
+   riscv_opcodes_args_params_s("c_spimm", 3, 2),
+   riscv_opcodes_args_params_s("c_index", 9, 2),
+
+   riscv_opcodes_args_params_s("rs1_p", 9, 7),
+   riscv_opcodes_args_params_s("rs2_p", 4, 2),
+   riscv_opcodes_args_params_s("rd_p", 4, 2),
+   riscv_opcodes_args_params_s("rd_rs1_n0", 11, 7),
+   riscv_opcodes_args_params_s("rd_rs1_p", 9, 7),
+   riscv_opcodes_args_params_s("rd_rs1", 11, 7),
+   riscv_opcodes_args_params_s("rd_n2", 11, 7),
+   riscv_opcodes_args_params_s("rd_n0", 11, 7),
+   riscv_opcodes_args_params_s("rs1_n0", 11, 7),
+   riscv_opcodes_args_params_s("c_rs2_n0", 6, 2),
+   riscv_opcodes_args_params_s("c_rs1_n0", 11, 7),
+   riscv_opcodes_args_params_s("c_rs2", 6, 2),
+   riscv_opcodes_args_params_s("c_sreg1", 9, 7),
+   riscv_opcodes_args_params_s("c_sreg2", 4, 2),
+   ];
+	
+enum string riscv_opcodes_types = q{
+
+  enum riscv_opcodes_imm_t: byte {
+    imm20,
+    jimm20,
+    imm12,
+    imm12hi,
+    bimm12hi,
+    imm12lo,
+    bimm12lo,
+    imm2,
+    imm3,
+    imm4,
+    imm5,
+    imm6,
+    zimm
+  }
+
+  enum riscv_opcodes_v_imm_t: byte {
+    simm5,
+    zimm5,
+    zimm10,
+    zimm11,
+    zimm6hi,
+    zimm6lo
+  }
+
+  enum riscv_opcodes_c_imm_t: byte {
+    c_nzuimm10,
+    c_uimm7lo,
+    c_uimm7hi,
+    c_uimm8lo,
+    c_uimm8hi,
+    c_uimm9lo,
+    c_uimm9hi,
+    c_nzimm6lo,
+    c_nzimm6hi,
+    c_imm6lo,
+    c_imm6hi,
+    c_nzimm10hi,
+    c_nzimm10lo,
+    c_nzimm18hi,
+    c_nzimm18lo,
+    c_imm12,
+    c_bimm9lo,
+    c_bimm9hi,
+    c_nzuimm5,
+    c_nzuimm6lo,
+    c_nzuimm6hi,
+    c_uimm8splo,
+    c_uimm8sphi,
+    c_uimm8sp_s,
+    c_uimm10splo,
+    c_uimm10sphi,
+    c_uimm9splo,
+    c_uimm9sphi,
+    c_uimm10sp_s,
+    c_uimm9sp_s,
+    c_uimm2,
+    c_uimm1,
+    c_spimm
+  }
+
+  enum riscv_opcodes_var_t: byte {
+    rd,
+    rt,
+    rs1,
+    rs2,
+    rs3,
+    aqrl,
+    aq,
+    rl,
+    fm,
+    pred,
+    succ,
+    rm,
+    funct3,
+    funct2,
+    csr,
+    shamtq,
+    shamtw,
+    shamtw4,
+    shamtd,
+    bs,
+    rnum,
+    rc,
+    opcode,
+    funct7
+  }
+
+  enum riscv_opcodes_v_var_t: byte {
+    vd,
+    vs3,
+    vs1,
+    vs2,
+    vm,
+    wd,
+    amoop,
+    nf
+  }
+ 
+  enum riscv_opcodes_c_var_t: byte {
+    c_rlist,
+    c_index,
+    rs1_p,
+    rs2_p,
+    rd_p,
+    rd_rs1_n0,
+    rd_rs1_p,
+    rd_rs1,
+    rd_n2,
+    rd_n0,
+    rs1_n0,
+    c_rs2_n0,
+    c_rs1_n0,
+    c_rs2,
+    c_sreg1,
+    c_sreg2
+  }
+
+};
+
+mixin(riscv_opcodes_types);
+  
+class Opcodes
+{
+  Node yaml_root;
+
+  // string instr_variables;
+  // string instr_extentions;
+  string instr_params;
+
+  this(string yaml) {
+    import std.traits: EnumMembers;
+    yaml_root = Loader.fromFile(yaml).load();
+
+  }
+
+  string[] var_arg_list;
+
+  // check if all instructions in given extentions are present in the enum riscv_instr_name_t
+  bool check_ext(string[] extns) {
+    import std.string: toLower, toUpper;
+    foreach (op_instr; yaml_root.mapping()) {
+      auto iextns = op_instr.value["extension"];
+      for (int i=0; i!=iextns.length;i+=1) {
+	auto iext = iextns[i].get!string();
+	if (extns.canFind(iext)) {
+	  string instrN = op_instr.key.get!string().toUpper;
+	  if (instrN.length > 5 && instrN[$-5..$] == "_RV32" ||
+	      instrN.length > 5 && instrN[$-5..$] == "_RV64") {
+	    stderr.writefln("Checking on instruction: %s, %s",
+			    instrN, iextns.length);
+	  }
+	}
+      }
+    }
+    return true;
+  }
+  
+  void parse_opcode_yaml() {
+    import std.stdio;
+    import std.traits: EnumMembers;
+
+    string instrName;
+    
+    instr_params = "\n  [";
+
+    foreach (instr; yaml_root.mapping()) {
+      import std.string: toLower, toUpper;
+
+      bool isListedExtn = false;
+
+      foreach (Node extn; instr.value["extension"]) {
+	auto extnStr = extn.get!string();
+	if (riscv_dv_handled_extentions.canFind(extnStr)) {
+	  isListedExtn = true;
+	  continue;
+	}
+      }
+
+      if (! isListedExtn) continue;
+
+      instrName = instr.key.get!string().toUpper();
+
+      if ((instrName.length > 5 &&
+	   (instrName[$-5..$] == "_RV32" || instrName[$-5..$] == "_RV64")) ||
+	  (instrName.length > 6 && instrName[$-6..$] == "_RV128")) {
+	stderr.writeln("Ignoring Istruction: ", instrName);
+	continue;
+      }
+      
+      riscv_dv_handled_instrs ~= instrName;
+      // writeln("Parsing instruction: ", instr.key.get!string());
+
+      // if (j != 0) instr_params ~= "   ";
+
+      string dv_instr = instr.key.get!string().toUpper();
+
+      instr_params ~= "  riscv_instr_param_s(\n     riscv_instr_name_t." ~ dv_instr ~ ", // instr_name\n     ";
+
+      if (dv_instr == "invalid_instr") {
+	instr_params ~= "riscv_instr_name_t." ~ dv_instr ~ ", // orig_name\n     ";
+	instr_params ~= "0xFFFFFFFF, // mask\n     ";
+	instr_params ~= "0x00000000, // match\n     ";
+	instr_params ~= "[], // _var_list\n     ";
+	instr_params ~= "[], // _ext_list\n     ";
+	instr_params ~= "0x0, // _imms\n     ";
+	instr_params ~= "0x0, // _c_imms\n     ";
+	instr_params ~= "0x0, // _v_imms\n     ";
+	instr_params ~= "0x0, // _vars\n     ";
+	instr_params ~= "0x0, // _c_vars\n     ";
+	instr_params ~= "0x0, // _v_vars\n   ";
+      }
+      else {
+	auto instrData = instr.value;
+	auto mask = instrData["mask"];
+
+	if ("orig_inst" in instrData) {
+	  import std.string: toUpper;
+	  auto orig_inst = instrData["orig_inst"];
+	  instr_params ~= "riscv_instr_name_t." ~
+	    orig_inst.get!string().toUpper() ~ ", // orig_name\n     ";
+	}
+	else {
+	  instr_params ~= "riscv_instr_name_t." ~ dv_instr ~ ", // orig_name\n     ";
+	}
+
+	  
+	// pragma(msg, typeof(mask));
+	instr_params ~= mask.get!string() ~ ", // mask\n     ";
+
+	auto match = instrData["match"];
+	// pragma(msg, typeof(match));
+	instr_params ~= match.get!string() ~ ", // match\n     ";
+
+	auto variable_fields = instrData["variable_fields"];
+
+	instr_params ~= ("[");
+	for (int i=0; i != variable_fields.length; i += 1) {
+	  auto field = variable_fields[i];
+	  string vf = field.get!string();
+	  if (! var_arg_list.canFind(vf)) var_arg_list ~= vf;
+	  instr_params ~= "riscv_instr_var_t." ~ vf;
+	  if (i != variable_fields.length - 1) instr_params ~= ", ";
+	}
+	instr_params ~= ("], // variables\n     ");      
+
+	auto extension = instrData["extension"];
+	// pragma(msg, typeof(extension));
+
+	instr_params ~= ("[");
+	for (int i=0; i != extension.length; i += 1) {
+	  auto field = extension[i];
+	  string ext = field.get!string();
+	  if (riscv_dv_handled_extentions.canFind(ext)) {
+	    instr_params ~= "riscv_extention_t." ~ ext;
+	    if (i != extension.length - 1) instr_params ~= ", ";
+	  }
+	}
+	instr_params ~= ("], // extentions\n     ");      
+
+	ulong imm_bits;
+	for (int i=0; i != variable_fields.length; i += 1) {
+	  auto field = variable_fields[i];
+	  string vf = field.get!string();
+	  foreach (imm; EnumMembers!riscv_opcodes_imm_t) {
+	    if (vf == imm.stringof["riscv_opcodes_imm_t".length+1..$])
+	      imm_bits |= 0x1UL << imm;
+	  }
+	}
+	instr_params ~= format("0b%0b, // _imms\n     ", imm_bits);
+
+	ulong c_imm_bits;
+	for (int i=0; i != variable_fields.length; i += 1) {
+	  auto field = variable_fields[i];
+	  string vf = field.get!string();
+	  foreach (c_imm; EnumMembers!riscv_opcodes_c_imm_t) {
+	    if (vf == c_imm.stringof["riscv_opcodes_c_imm_t".length+1..$])
+	      c_imm_bits |= 0x1UL << c_imm;
+	  }
+	}
+	instr_params ~= format("0b%0b, // _c_imms\n     ", c_imm_bits);
+      
+	ulong v_imm_bits;
+	for (int i=0; i != variable_fields.length; i += 1) {
+	  auto field = variable_fields[i];
+	  string vf = field.get!string();
+	  foreach (v_imm; EnumMembers!riscv_opcodes_v_imm_t) {
+	    if (vf == v_imm.stringof["riscv_opcodes_v_imm_t".length+1..$])
+	      v_imm_bits |= 0x1UL << v_imm;
+	  }
+	}
+	instr_params ~= format("0b%0b, // _v_imms\n     ", v_imm_bits);
+      
+	ulong var_bits;
+	for (int i=0; i != variable_fields.length; i += 1) {
+	  auto field = variable_fields[i];
+	  string vf = field.get!string();
+	  foreach (var; EnumMembers!riscv_opcodes_var_t) {
+	    if (vf == var.stringof["riscv_opcodes_var_t".length+1..$])
+	      var_bits |= 0x1UL << var;
+	  }
+	}
+	instr_params ~= format("0b%0b, // _vars\n     ", var_bits);
+      
+	ulong c_var_bits;
+	for (int i=0; i != variable_fields.length; i += 1) {
+	  auto field = variable_fields[i];
+	  string vf = field.get!string();
+	  foreach (c_var; EnumMembers!riscv_opcodes_c_var_t) {
+	    if (vf == c_var.stringof["riscv_opcodes_c_var_t".length+1..$])
+	      c_var_bits |= 0x1UL << c_var;
+	  }
+	}
+	instr_params ~= format("0b%0b, // _c_vars\n     ", c_var_bits);
+
+	ulong v_var_bits;
+	for (int i=0; i != variable_fields.length; i += 1) {
+	  auto field = variable_fields[i];
+	  string vf = field.get!string();
+	  foreach (v_var; EnumMembers!riscv_opcodes_v_var_t) {
+	    if (vf == v_var.stringof["riscv_opcodes_v_var_t".length+1..$])
+	      v_var_bits |= 0x1UL << v_var;
+	  }
+	}
+	instr_params ~= format("0b%0b, // _v_vars\n   ", v_var_bits);
+	
+      }
+      
+      // if (j == EnumMembers!riscv_instr_name_t.length - 1) {
+      // 	instr_params ~= ") // " ~ dv_instr;
+      // 	instr_params ~= "\n];\n";
+      // }
+      // else {
+      instr_params ~= "), // " ~ dv_instr;
+      instr_params ~= "\n";
+      // }
+    }
+    instr_params ~= "];";
+  }
+
+
+  void print() {
+    import std.traits: EnumMembers;
+  
+    writeln("module riscv.gen.riscv_opcodes_pkg;\n");
+    // writeln("import riscv.gen.riscv_instr_pkg;");
+
+    parse_opcode_yaml();
+
+    writeln("enum riscv_instr_name_t: short {");
+    foreach (instr; riscv_dv_handled_instrs) {
+      writeln("    ", instr, ",");
+    }
+    writeln("    INVALID_INSTR\n}");
+
+    
+    writeln(riscv_opcodes_types);
+    
+    writeln("enum riscv_extention_t: short {");
+    foreach (i, ext; riscv_dv_handled_extentions) {
+      write("  " ~ ext);
+      if (i != riscv_dv_handled_extentions.length - 1) writeln(",");
+    }
+
+    write("\n};");
+
+    writeln(q{
+	struct riscv_instr_var_params_s {
+	  riscv_instr_var_t _arg;
+	  ubyte             _lsb;
+	  ubyte             _msb;
+	}
+	
+	struct riscv_instr_param_s {
+	  riscv_instr_name_t _name;
+	  riscv_instr_name_t _orig_name;
+	  uint _mask;
+	  uint _match;
+	  riscv_instr_var_t[] _var_list;
+	  riscv_extention_t[] _ext_list;
+	  ulong _imms;
+	  ulong _c_imms;
+	  ulong _v_imms;
+	  ulong _vars;
+	  ulong _c_vars;
+	  ulong _v_vars;
+	}
+
+      });
+
+    
+    writeln("enum riscv_instr_var_t: short {");
+    foreach (arg; riscv_opcodes_args_params) {
+      // if (var_arg_list.canFind(arg._arg)) {
+      writefln("  %s,", arg._arg);
+      // }
+    }
+    writeln("}\n");
+    
+    writeln("enum riscv_instr_var_params_s[] riscv_instr_var_params = [");
+    foreach (arg; riscv_opcodes_args_params) {
+      // if (var_arg_list.canFind(arg._arg)) {
+      writefln("  riscv_instr_var_params_s(riscv_instr_var_t.%s, %s, %s),",
+	       arg._arg, arg._lsb, arg._msb + 1);
+      // }
+    }
+    writeln("];\n");
+    
+
+    // writeln("enum riscv_opcodes_args_list = create_args_table();");
+    // writefln("enum riscv_instr_opcodes = %s", instr_opcodes);
+    // writefln("enum riscv_instr_variables = %s", instr_variables);
+    // writefln("enum riscv_instr_extentions = %s", instr_extentions);
+    writefln("enum riscv_instr_params = %s", instr_params);
+  }
+}
+
+
+void main() {
+  auto opcodeData = new Opcodes("riscv-opcodes.yaml");
+  opcodeData.check_ext(riscv_dv_handled_extentions);
+  opcodeData.print();
+}
+
+// string instr_assign(Node yaml_root) {
+//   import std.stdio;
+//   import std.traits: EnumMembers;
+//   string str;
+
+//   foreach (instr_name; EnumMembers!riscv_instr_name_t) {
+//     import std.string: toLower;
+//     string dv_instr = instr_name.stringof[19..$].toLower();
+//     if (dv_instr != "nop" && dv_instr != "invalid_instr") {
+//       auto instr = yaml_root[dv_instr];
+//       str ~= "table[" ~ instr_name.stringof ~ "] = ";
+//       // write(dv_instr, " ");
+//       auto variable_fields = instr["variable_fields"];
+//       // pragma(msg, typeof(variable_fields));
+
+//       str ~= ("[");
+//       for (int i=0; i != variable_fields.length; i += 1) {
+// 	auto field = variable_fields[i];
+// 	string vf = field.get!string();
+// 	str ~= "riscv_instr_var_t." ~ vf;
+// 	if (i != variable_fields.length - 1) str ~= ", ";
+//       }
+//       str ~= ("];\n");      
+//     }
+//   }
+//   return str;
+// }
diff --git a/euvm/riscv/gen/riscv_page_table_entry.d b/euvm/riscv/gen/riscv_page_table_entry.d
index cc1ae5de..da2b1f67 100644
--- a/euvm/riscv/gen/riscv_page_table_entry.d
+++ b/euvm/riscv/gen/riscv_page_table_entry.d
@@ -27,7 +27,7 @@ import riscv.gen.riscv_instr_pkg: pte_permission_t, satp_mode_t;
 import riscv.gen.target: XLEN;
 import std.format: format;
 
-import esdl.data.bvec: ubvec;
+import esdl.data.bvec: ubvec, toubvec;
 import esdl.rand: constraint, rand;
 
 import uvm;
diff --git a/euvm/riscv/gen/riscv_page_table_list.d b/euvm/riscv/gen/riscv_page_table_list.d
index 2e118705..f15b1c73 100644
--- a/euvm/riscv/gen/riscv_page_table_list.d
+++ b/euvm/riscv/gen/riscv_page_table_list.d
@@ -212,6 +212,9 @@ class riscv_page_table_list(satp_mode_t MODE = satp_mode_t.SV39) : uvm_object
     valid_data_leaf_pte = cast (riscv_page_table_entry!(MODE)) valid_leaf_pte.clone;
     illegal_pte.turn_off_default_constraint();
     valid_link_pte.xwr = pte_permission_t.NEXT_LEVEL_PAGE;
+    valid_link_pte.a = false;
+    valid_link_pte.d = false;
+    valid_link_pte.u = false;
     valid_link_pte.pack_entry();
     // Set data page to read/write, but not executable
     valid_data_leaf_pte.xwr = pte_permission_t.READ_WRITE_PAGE;
diff --git a/euvm/riscv/gen/riscv_pmp_cfg.d b/euvm/riscv/gen/riscv_pmp_cfg.d
index 4dcaa71e..91400479 100644
--- a/euvm/riscv/gen/riscv_pmp_cfg.d
+++ b/euvm/riscv/gen/riscv_pmp_cfg.d
@@ -19,12 +19,12 @@ module riscv.gen.riscv_pmp_cfg;
 
 import riscv.gen.riscv_instr_pkg: pmp_cfg_reg_t, pmp_addr_mode_t,
   privileged_reg_t, riscv_reg_t, exception_cause_t, get_int_arg_value,
-  get_bool_arg_value, get_hex_arg_value;
+  get_bool_arg_value, get_hex_arg_value, mseccfg_reg_t;
 
-import riscv.gen.target: XLEN;
+import riscv.gen.target: XLEN, support_epmp;
 import std.format: format;
 
-import esdl.data.bvec: ubvec, toubvec, tobvec, clog2;
+import esdl.data.bvec: ubvec, toubvec, tobvec, clog2, UBVEC;
 import esdl.rand: rand, constraint;
 
 import uvm;
@@ -46,7 +46,7 @@ class riscv_pmp_cfg: uvm_object {
   bool pmp_randomize = false;
 
   // allow pmp randomization to cause address range overlap
-  @rand bool pmp_allow_addr_overlap = false;
+  bool pmp_allow_illegal_tor = false;
 
   // By default, after returning from a PMP exception, we return to the exact same instruction that
   // resulted in a PMP exception to begin with, creating an infinite loop of taking an exception.
@@ -56,13 +56,33 @@ class riscv_pmp_cfg: uvm_object {
   // allowing all access restrictions to be enforced.
   bool enable_pmp_exception_handler = true;
 
+  // Don't generate the usual PMP setup section, instead generate a setup that provides a single
+  // region allowing full access to all of memory from both U mode and M mode.
+  bool suppress_pmp_setup = false;
+
   // Setting this bit to 1'b1 enables generation of the directed stream of instructions to test
   // write accesses to all supported pmpaddr[i] CSRs.
   bool enable_write_pmp_csr;
 
+  // ePMP machine security configuration - RLB, MMWP, MML
+  @UVM_DEFAULT
+  @rand mseccfg_reg_t mseccfg = mseccfg_reg_t(true, false, false);
+
+  // allow regions that start above 32-bit address space when XLEN == 32
+  @rand bool allow_high_addrs;
+
+  // percentage of configs that will allow high address regions. Set low by default as for cores
+  // where physical addresses do not go beyond 32 bits high regions don't do anything interesting
+  // (though you want some to ensure they're handled correctly).
+  int high_addr_proportion = 10;
+
   // pmp CSR configurations
   @rand pmp_cfg_reg_t[]  pmp_cfg;
 
+  // Hints used during PMP generation
+  bool[] pmp_cfg_addr_valid;
+  bool[] pmp_cfg_already_configured;
+
   // This value is the address offset between the minimum and maximum pmpaddr
   // CSR values.
   // As pmpaddr0 will be set to the address of the <main> label, the address stored
@@ -71,6 +91,11 @@ class riscv_pmp_cfg: uvm_object {
   // Can be manually configured from the command line.
   @UVM_DEFAULT ubvec!(XLEN) pmp_max_offset = ubvec!(XLEN).max();
 
+  // Value to hold the end signature address to that signals the end to the test environment.
+  // Currently the design assumes that the end signature is address is equal to the signature
+  // address minus 4 Bytes.
+  ubvec!XLEN end_signature_addr;
+
   // used to parse addr_mode configuration from cmdline
   alias addr_mode_wrapper = uvm_enum_wrapper!(pmp_addr_mode_t);
   pmp_addr_mode_t addr_mode;
@@ -92,21 +117,43 @@ class riscv_pmp_cfg: uvm_object {
 
   constraint! q{
     foreach (cfg; pmp_cfg) {
-      !(cfg.w && !cfg.r);
+      solve mseccfg.mml before cfg.w;
+      solve mseccfg.mml before cfg.r;
+      !(!mseccfg.mml && cfg.w && !cfg.r);
     }
   } xwr_c;
 
+  constraint! q{
+    allow_high_addrs dist [ false := 100 - high_addr_proportion,
+			    true  := high_addr_proportion];
+    if (XLEN == 64) {
+      allow_high_addrs == true;
+    }
+  } allow_high_addrs_c;
+
+
+
+  constraint! q{
+    foreach (cfg; pmp_cfg) {
+      cfg.addr_mode >= 0;
+      if (allow_high_addrs) {
+        cfg.addr_mode <= XLEN;
+      }
+      else {
+        cfg.addr_mode <= XLEN - 3;
+      }
+    }
+  } address_modes_c;
+
   constraint! q{
     foreach (cfg; pmp_cfg) {
-      (pmp_granularity == 0) ->	(cfg.a != pmp_addr_mode_t.NAPOT);
       (pmp_granularity >= 1) -> (cfg.a != pmp_addr_mode_t.NA4);
     }
   } grain_addr_mode_c;
 
   constraint! q{
     foreach (i, cfg; pmp_cfg) {
-      // Offset of pmp_cfg[0] does not matter, since it will be set to <main>,
-      // so we do not constrain it here, as it will be overridden during generation
+      // Offset of pmp_cfg[0] is always set to 0 from main.
       if (i != 0) {
         cfg.offset inside [1 : pmp_max_offset];
       }
@@ -116,22 +163,58 @@ class riscv_pmp_cfg: uvm_object {
     }
   }  addr_range_c;
 
+  constraint! q{
+    foreach (cfg; pmp_cfg) {
+      solve allow_high_addrs before cfg.addr;
+      solve allow_high_addrs before cfg.addr_mode;
+      solve cfg.a before cfg.addr;
+      solve cfg.addr_mode before cfg.addr;
+    }
+  }  modes_before_addr_c;
+
+
   constraint! q{
     foreach (i, cfg; pmp_cfg) {
-      if (!pmp_allow_addr_overlap && i > 0) {
-        cfg.offset > pmp_cfg[i-1].offset;
+      // In case illegal TOR regions are disallowed always add the constraint, otherwise make the
+      // remove the constraint for 1 in every XLEN entries.
+      if (i > 0 && cfg.a == pmp_addr_mode_t.TOR && (!pmp_allow_illegal_tor || cfg.addr_mode > 0)) {
+        cfg.addr > pmp_cfg[i-1].addr;
+      }
+
+      if (!allow_high_addrs) {
+        cfg.addr[29..32] == 0;
       }
     }
-  }  addr_overlapping_c;
+  } addr_legal_tor_c;
 
-  // Privileged spec states that in TOR mode, offset[i-1] < offset[i]
   constraint! q{
     foreach (cfg; pmp_cfg) {
-      if (cfg.a == pmp_addr_mode_t.TOR) {
-        pmp_allow_addr_overlap == false;
+      // In case NAPOT is selected make sure that we randomly select a region mode and force the
+      // address to match that mode.
+      if (cfg.a == pmp_addr_mode_t.NAPOT) {
+	// Make sure the bottom addr_mode - 1 bits are set to 1.
+	(cfg.addr & ((1 << cfg.addr_mode) - 1)) == ((1 << cfg.addr_mode) - 1);
+	if (cfg.addr_mode < XLEN) {
+	  // Unless the largest region is selected make sure the bit just before the ones is set to 0.
+	  (cfg.addr & (1 << cfg.addr_mode)) == 0;
+       }
+
+        if (!allow_high_addrs) {
+          cfg.addr[29..32] == 0;
+        }
       }
     }
-  }  tor_addr_overlap_c;
+  } addr_napot_mode_c;
+
+  constraint! q{
+    foreach (cfg; pmp_cfg) {
+      if (cfg.a == pmp_addr_mode_t.NA4) {
+        if (!allow_high_addrs) {
+          cfg.addr[29..32] == 0;
+        }
+      }
+    }
+  } addr_na4_mode_c;
 
   this(string name = "") {
     string s;
@@ -145,15 +228,19 @@ class riscv_pmp_cfg: uvm_object {
     }
     get_int_arg_value("+pmp_granularity=", pmp_granularity);
     get_bool_arg_value("+pmp_randomize=", pmp_randomize);
-    get_bool_arg_value("+pmp_allow_addr_overlap=", pmp_allow_addr_overlap);
+    get_bool_arg_value("+pmp_allow_illegal_tor=", pmp_allow_illegal_tor);
+    get_bool_arg_value("+suppress_pmp_setup=", suppress_pmp_setup);
     get_bool_arg_value("+enable_write_pmp_csr=", enable_write_pmp_csr);
     get_hex_arg_value("+pmp_max_offset=", pmp_max_offset_int);
     pmp_max_offset = toubvec!XLEN(pmp_max_offset_int);
-    uvm_info(get_full_name(), format("pmp max offset: 0x%0x", pmp_max_offset), UVM_LOW);
+    uvm_info(get_full_name(), format("pmp max offset: 0x%08x", pmp_max_offset), UVM_LOW);
     pmp_cfg.length = pmp_num_regions;
+    pmp_cfg_addr_valid.length = pmp_num_regions;
+    pmp_cfg_already_configured.length = pmp_num_regions;
   }
 
-  void initialize(bool require_signature_addr) {
+  void initialize(ubvec!XLEN signature_addr) {
+    end_signature_addr = signature_addr - 0x04;
     if (!pmp_randomize) {
       set_defaults();
       setup_pmp();
@@ -170,14 +257,19 @@ class riscv_pmp_cfg: uvm_object {
   }
 
   void set_defaults() {
-    uvm_info(get_full_name(), format("MAX OFFSET: 0x%0x", pmp_max_offset), UVM_LOW);
+    uvm_info(get_full_name(), format("MAX OFFSET: 0x%08x", pmp_max_offset), UVM_LOW);
+    mseccfg.mml  = false;
+    mseccfg.mmwp = false;
+    mseccfg.rlb  = true;
     foreach (i, cfg; pmp_cfg) {
-      cfg.l      = false;
-      cfg.a      = pmp_addr_mode_t.TOR;
-      cfg.x      = true;
-      cfg.w      = true;
-      cfg.r      = true;
-      cfg.offset = assign_default_addr_offset(pmp_num_regions, cast(int) i);
+      cfg.l                         = false;
+      cfg.a                         = pmp_addr_mode_t.TOR;
+      cfg.x                         = true;
+      cfg.w                         = true;
+      cfg.r                         = true;
+      cfg.offset                    = assign_default_addr_offset(pmp_num_regions, cast(int) i);
+      pmp_cfg_addr_valid[i]         = false;
+      pmp_cfg_already_configured[i] = false;
     }
   }
 
@@ -194,25 +286,66 @@ class riscv_pmp_cfg: uvm_object {
     return offset;
   }
 
+  struct parse_pmp_config_t { pmp_cfg_reg_t pmp_cfg_reg; bool addr_valid; }
+
   void setup_pmp() {
     string arg_name;
-    string pmp_region;
+    string arg_value;
+    parse_pmp_config_t tmp_value;
+    if (uvm_cmdline_processor.get_inst().get_arg_value("+mseccfg=", arg_value)) {
+      mseccfg = parse_mseccfg(arg_value, mseccfg);
+    }
     foreach (i, ref cfg; pmp_cfg) {
       arg_name = format("+pmp_region_%0d=", i);
-      if (uvm_cmdline_processor.get_inst().get_arg_value(arg_name, pmp_region)) {
-        cfg = parse_pmp_config(pmp_region, cfg);
+      if (uvm_cmdline_processor.get_inst().get_arg_value(arg_name, arg_value)) {
+        tmp_value = parse_pmp_config(arg_value, cfg);
+        cfg = tmp_value.pmp_cfg_reg;
+        pmp_cfg_addr_valid[i] = tmp_value.addr_valid;
         uvm_info(get_full_name(), format("Configured pmp_cfg[%0d] from command line: %p",
 					 i , cfg), UVM_LOW);
       }
     }
   }
 
-  pmp_cfg_reg_t parse_pmp_config(string pmp_region, pmp_cfg_reg_t ref_pmp_cfg) {
+  mseccfg_reg_t parse_mseccfg(string mseccfg, mseccfg_reg_t ref_mseccfg) {
+    import std.format: format;
+    import std.conv: to;
+
+    string field_type;
+    string field_val;
+    mseccfg_reg_t mseccfg_reg = ref_mseccfg;
+    string[] fields = uvm_string_split(mseccfg, ',');
+    foreach (field; fields) {
+      string[] field_vals = uvm_string_split(field, ':');
+      field_type = field_vals[0];
+      field_val = field_vals[1];
+      switch (field_type) {
+      case "MML":
+	mseccfg_reg.mml = field_val.to!(bool);
+	break;
+      case "MMWP":
+	mseccfg_reg.mmwp = field_val.to!(bool);
+	break;
+      case "RLB":
+	mseccfg_reg.rlb = field_val.to!(bool);
+	break;
+      default: {
+	uvm_fatal(get_full_name(), format("%s, Invalid MSECCFG field name!", field_val));
+      }
+      }
+    }
+    return mseccfg_reg;
+  }
+
+
+parse_pmp_config_t parse_pmp_config(string pmp_region, pmp_cfg_reg_t ref_pmp_cfg) {
     string [] fields;
     string [] field_vals;
     string field_type;
     string field_val;
-    pmp_cfg_reg_t pmp_cfg_reg = ref_pmp_cfg;
+    parse_pmp_config_t return_value;
+    return_value.pmp_cfg_reg = ref_pmp_cfg;
+    return_value.addr_valid = false;
     uvm_string_split(pmp_region, ',', fields);
     foreach (i, ref field; fields) {
       import std.conv: to;
@@ -224,30 +357,32 @@ class riscv_pmp_cfg: uvm_object {
 
       switch (field_type) {
       case "L" :
-	pmp_cfg_reg.l = field_val.to!bool;
+	return_value.pmp_cfg_reg.l = field_val.to!bool;
 	break;
       case "A":
 	bool ch_mode = addr_mode_wrapper.from_name(field_val, addr_mode);
 	if(!ch_mode) uvm_error(get_full_name(), format("Check failed : %s", field_val));
-	pmp_cfg_reg.a = addr_mode;
+	return_value.pmp_cfg_reg.a = addr_mode;
 	break;
       case "X":
-	pmp_cfg_reg.x = field_val.to!bool;
+	return_value.pmp_cfg_reg.x = field_val.to!bool;
 	break;
       case "W":
-	pmp_cfg_reg.w = field_val.to!bool;
+	return_value.pmp_cfg_reg.w = field_val.to!bool;
 	break;
       case  "R":
-	pmp_cfg_reg.r = field_val.to!bool;
+	return_value.pmp_cfg_reg.r = field_val.to!bool;
 	break;
       case "ADDR":
 	// Don't have to convert address to "PMP format" here,
 	// since it must be masked off in hardware
 	static if (XLEN == 32) {
-	  pmp_cfg_reg.addr = format_addr(toubvec!XLEN(field_val.to!uint(16)));
+	  return_value.addr_valid = true;
+	  return_value.pmp_cfg_reg.addr       = format_addr(toubvec!XLEN(field_val.to!uint(16)));
 	}
 	else static if (XLEN == 64) {
-	  pmp_cfg_reg.addr = format_addr(toubvec!XLEN(field_val.to!ulong(16)));
+	  return_value.addr_valid = true;
+	  return_value.pmp_cfg_reg.addr       = format_addr(toubvec!XLEN(field_val.to!ulong(16)));
 	}
 	else {
 	  uvm_fatal(get_full_name(), format("Unsupported XLEN %0s", XLEN));
@@ -258,7 +393,7 @@ class riscv_pmp_cfg: uvm_object {
       }
     }
 
-    return pmp_cfg_reg;
+    return return_value;
   }
 
   ubvec!XLEN format_addr(ubvec!XLEN addr) {
@@ -287,11 +422,20 @@ class riscv_pmp_cfg: uvm_object {
     return addr;
   }
 
-  ubvec!1  booltobit( bool x) {
+  ubvec!1 booltobit( bool x) {
     if ( x == true)
-      return 0b1.toubvec!1;
+      return UBVEC!(1, 1);
     else
-      return 0b0.toubvec!1;
+      return UBVEC!(1, 0);
+  }
+
+  // Generates code to setup a single PMP region allowing full access to all memory
+  void gen_pmp_enable_all(riscv_reg_t scratch_reg, ref string[] instr) {
+    // Setup region 0 to NAPOT covering the whole 32-bit address space, with RWX permissions and no
+    // lock.
+    instr ~= format("li x%0d, 0x1fffffff", scratch_reg);
+    instr ~= format("csrw 0x%0x, x%0d", privileged_reg_t.PMPADDR0, scratch_reg);
+    instr ~= format("csrw 0x%0x, 0x1f", privileged_reg_t.PMPCFG0);
   }
 
   // This function parses the pmp_cfg[] array to generate the actual instructions to set up
@@ -299,94 +443,295 @@ class riscv_pmp_cfg: uvm_object {
   // Since either 4 (in rv32) or 8 (in rv64) PMP configuration registers fit into one physical
   // CSR, this function waits until it has reached this maximum to write to the physical CSR to
   // save some extraneous instructions from being performed.
+  //
+  // The general flow of this function:
+  // - If randomization, generate code region, otherwise select region 0.
+  // - Set address of code region before setting MSECCFG.
+  // - If  MML, initially set MSECCFG to MML=0, MMWP=0, RLB=1.
+  // - If  MML, set the config of code region to LXWR=1100 and TOR.
+  // - If MMWP, set the config of code region to LXWR=0100 and TOR.
+  // - If MML or MMWP, set requested MSECCFG with RLB hardcoded to 1.
+  // - Don't override code region config if corresponding `+pmp_region_` is passed.
+  // - If MML, set default code region config to shared execute.
+  // - If MML or MMWP, set stack and signature regions to shared read/write.
+  // - Set requested MSECCFG (including RLB).
+  // - Set all other addresses and configs.
   void gen_pmp_instr(riscv_reg_t[2] scratch_reg, ref string[] instr) {
+    import std.format: format;
+    import esdl.base.rand: urandom;
+    
     ubvec!XLEN   pmp_word;
     ubvec!XLEN   cfg_bitmask;
     ubvec!8       cfg_byte;
     int pmp_id;
-    foreach (i, ref cfg; pmp_cfg) {
+    string arg_value;
+
+    int code_entry, stack_entry, sig_entry;
+    pmp_cfg_reg_t tmp_pmp_cfg;
+
+    if (support_epmp) {
+      // In case of MML or MMWP we need to set code region to executable before setting MSECCFG.
+      if (mseccfg.mml || mseccfg.mmwp) {
+        // Writing MSECCFG with RLB set to 1 to stop the config with L enabled from locking
+        // everything before configuration is done.
+        uvm_info(get_full_name(), format("MSECCFG: MML 0, MMWP 0, RLB 1"), UVM_LOW);
+        cfg_byte = 0b00000100; // {1'b1, 1'b0, 1'b0};
+        instr ~= format("csrwi 0x%0x, %0d", privileged_reg_t.MSECCFG, cfg_byte);
+
+        if (pmp_randomize) {
+          // Randomly select a PMP region to contain the code for permitting execution and two
+          // extra regions to contain the stack and the signature address.
+	  code_entry = urandom(0, pmp_num_regions - 2);
+	  // Randomly select a PMP region to contain the code for permitting execution.
+          // In case of full randomization we actually want the code region to cover main as well.
+          pmp_cfg[code_entry].offset = pmp_max_offset;
+	  stack_entry = code_entry + 1;
+	  sig_entry = code_entry + 2;
+        }
+	else {
+          code_entry = 0;
+	  stack_entry = pmp_num_regions - 2;
+	  sig_entry = pmp_num_regions - 1;
+          // This is the default offset.
+          pmp_cfg[code_entry].offset = assign_default_addr_offset(pmp_num_regions, code_entry);
+	  pmp_cfg[pmp_num_regions - 3].offset = pmp_max_offset;
+        }
 
-      // TODO(udinator) condense this calculations if possible
-      pmp_id = cast(int) (i/cfg_per_csr);
-      if (i == 0) {
-	cfg_byte = tobvec!0b0 ~ cfg.zero ~ tobvec!2(pmp_addr_mode_t.TOR) ~ tobvec!3(0b111);
-      }
-      else {
-	bool l, w, r, x;
-	l = cfg.l;
-	//a = cfg.a;
-	x = cfg.x;
-	w = cfg.w;
-	r = cfg.r;
-	cfg_byte = booltobit(l) ~ cfg.zero ~ tobvec!2(cfg.a)
-	  ~ booltobit(x) ~ booltobit(w) ~ booltobit(r);
+        if (code_entry > 0) {
+          // Load _start into PMP address of previous entry to complete TOR region.
+          instr ~= format("la x%0d, _start", scratch_reg[0]);
+          instr ~= format("srli x%0d, x%0d, 2", scratch_reg[0], scratch_reg[0]);
+          instr ~= format("csrw 0x%0x, x%0d", base_pmp_addr + code_entry - 1,
+			  scratch_reg[0]);
+          uvm_info(get_full_name(), format("Address of pmp_addr_%d is _start",
+					   code_entry - 1), UVM_LOW);
+          pmp_cfg_already_configured[code_entry - 1] = true;
+        }
+
+        // Load the address of the kernel_instr_end into PMP code entry.
+        instr ~= format("la x%0d, kernel_instr_end", scratch_reg[0]);
+        instr ~= format("srli x%0d, x%0d, 2", scratch_reg[0], scratch_reg[0]);
+        instr ~= format("csrw 0x%0x, x%0d", base_pmp_addr + code_entry, scratch_reg[0]);
+        uvm_info(get_full_name(), format("Address of pmp_addr_%d is kernel_instr_end", code_entry),
+		 UVM_LOW);
+        pmp_cfg_already_configured[code_entry] = true;
+
+        if (mseccfg.mml) {
+          // This value is different from below (M-mode execute only) because we need code region
+          // to be executable in both M-mode and U-mode, since RISCV-DV switches priviledge before
+          // <main> but after <pmp_setup>. We choose to allow M-mode reads to allows checking
+          // whether instructions are compressed in the trap handler in order to recover from load
+          // and store access faults.
+          tmp_pmp_cfg.l = true;
+          tmp_pmp_cfg.a = pmp_addr_mode_t.TOR;
+          tmp_pmp_cfg.x = true;
+          tmp_pmp_cfg.w = true;
+          tmp_pmp_cfg.r = false;
+          // This configuration needs to be executable in M-mode both before and after writing to
+          // MSECCFG. It will deny execution for U-Mode, but this is necessary because RWX=111 in
+          // MML means read only, and RW=01 is not allowed before MML is enabled.
+          // cfg_byte = {tmp_pmp_cfg.l, tmp_pmp_cfg.zero, tmp_pmp_cfg.a, 1'b1,
+          //             1'b0, tmp_pmp_cfg.r};
+	  cfg_byte[0] = tmp_pmp_cfg.r;
+	  cfg_byte[1] = false;
+	  cfg_byte[2] = tmp_pmp_cfg.x;
+	  cfg_byte[3..5] = tmp_pmp_cfg.a;
+	  cfg_byte[5..7] = tmp_pmp_cfg.zero;
+	  cfg_byte[7] = tmp_pmp_cfg.l;
+	}
+	else {
+          // We must set pmp code region to executable before enabling MMWP.
+          tmp_pmp_cfg.l = false;
+          tmp_pmp_cfg.a = pmp_addr_mode_t.TOR;
+          tmp_pmp_cfg.x = true;
+          tmp_pmp_cfg.w = false;
+          tmp_pmp_cfg.r = false;
+
+          // cfg_byte      = {tmp_pmp_cfg.l, tmp_pmp_cfg.zero, tmp_pmp_cfg.a,
+          //                  tmp_pmp_cfg.x, tmp_pmp_cfg.w,    tmp_pmp_cfg.r};
+	  cfg_byte[0] = tmp_pmp_cfg.r;
+	  cfg_byte[1] = tmp_pmp_cfg.w;
+	  cfg_byte[2] = tmp_pmp_cfg.x;
+	  cfg_byte[3..5] = tmp_pmp_cfg.a;
+	  cfg_byte[5..7] = tmp_pmp_cfg.zero;
+	  cfg_byte[7] = tmp_pmp_cfg.l;
+	}
+        // In case the randomly selected code entry is not also configured in the arguments,
+        // overwrite it in pmp_cfg.
+        // The pmp_config has value LXWR = 1010, which means it is executable in both M and U mode.
+        if (! uvm_cmdline_processor.get_inst().get_arg_value(format("+pmp_region_%0d=", code_entry),
+				arg_value)) {
+          pmp_cfg[code_entry].l      = tmp_pmp_cfg.l;
+          pmp_cfg[code_entry].a      = tmp_pmp_cfg.a;
+          pmp_cfg[code_entry].x      = tmp_pmp_cfg.x;
+          pmp_cfg[code_entry].w      = tmp_pmp_cfg.w;
+          pmp_cfg[code_entry].r      = tmp_pmp_cfg.r;
+	}
+
+        if (code_entry > 0) {
+	  // Disable all configs before the code entry because PMP regions can be initialized with
+	  // any value and we need to make sure that the code entry is the first valid entry during
+	  // PMP setup.
+	  cfg_bitmask = 0;
+	  instr ~= format("li x%0d, 0x%0x", scratch_reg[0], cfg_bitmask);
+	  for (int i = 0; i < (code_entry / cfg_per_csr); i++) {
+	    instr ~= format("csrw 0x%0x, x%0d", base_pmpcfg_addr + i, scratch_reg[0]);
+	  }
+	}
+	  // Enable the selected config on region code_entry.
+	cfg_bitmask = cfg_byte << ((code_entry % cfg_per_csr) * 8);
+        uvm_info(get_full_name(), format("temporary code config: 0x%08x", cfg_bitmask), UVM_DEBUG);
+        instr ~= format("li x%0d, 0x%0x", scratch_reg[0], cfg_bitmask);
+        instr ~= format("csrw 0x%0x, x%0d", base_pmpcfg_addr + (code_entry/cfg_per_csr),
+			scratch_reg[0]);
+
+        // Load the address of the kernel_stack_end into PMP stack entry.
+        instr ~= format("la x%0d, kernel_stack_end", scratch_reg[0]);
+	// Add 4 to also include the final address of the kernel stack.
+	instr ~= format("addi x%0d, x%0d, 4", scratch_reg[0], scratch_reg[0]);
+        instr ~= format("srli x%0d, x%0d, 2", scratch_reg[0], scratch_reg[0]);
+        instr ~= format("csrw 0x%0x, x%0d", base_pmp_addr + stack_entry,
+			scratch_reg[0]);
+        uvm_info(get_full_name(), format("Address of pmp_addr_%d is kernel_stack_end", stack_entry),
+		 UVM_LOW);
+        pmp_cfg_already_configured[stack_entry] = true;
+        // In case the randomly selected stack_entry is not also specified in the arguments,
+        // overwrite it in pmp_cfg. We use this for the stack entry.
+        if (! uvm_cmdline_processor.get_inst().get_arg_value(format("+pmp_region_%0d=", stack_entry), arg_value)) {
+          if (mseccfg.mml) {
+            // Marking the pmp stack region as shared write/read region before starting main.
+            pmp_cfg[stack_entry].l = false;
+            pmp_cfg[stack_entry].a = pmp_addr_mode_t.TOR;
+            pmp_cfg[stack_entry].x = true;
+            pmp_cfg[stack_entry].w = true;
+            pmp_cfg[stack_entry].r = false;
+          }
+	  else {
+            // We must set PMP stack region to write/read before starting main. X=0 to be consistent
+            // with MML mode.
+            pmp_cfg[stack_entry].l = false;
+            pmp_cfg[stack_entry].a = pmp_addr_mode_t.TOR;
+            pmp_cfg[stack_entry].x = false;
+            pmp_cfg[stack_entry].w = true;
+            pmp_cfg[stack_entry].r = true;
+          }
+        }
+        // Load the signature address into PMP signature entry. This assumes the
+        // end_signature_addr = signature_addr - 4. And that both are 4 Bytes.
+        instr ~= format("li x%0d, 0x%0x", scratch_reg[0], end_signature_addr);
+        instr ~= format("srli x%0d, x%0d, 2", scratch_reg[0], scratch_reg[0]);
+        instr ~= format("csrw 0x%0x, x%0d", base_pmp_addr + sig_entry,
+			scratch_reg[0]);
+        uvm_info(get_full_name(), format("Address of pmp_addr_%0d is signature_addr", sig_entry),
+		 UVM_LOW);
+        pmp_cfg_already_configured[sig_entry] = true;
+        // In case the randomly selected sig_entry is not also specified in the arguments,
+        // overwrite it in pmp_cfg. This is used for the signature address.
+        if (! uvm_cmdline_processor.get_inst().get_arg_value(format("+pmp_region_%0d=", sig_entry), arg_value)) {
+          if (mseccfg.mml) {
+            // Marking the PMP signature region as shared write/read region before starting main.
+            pmp_cfg[sig_entry].l = false;
+            pmp_cfg[sig_entry].a = pmp_addr_mode_t.NAPOT;
+            pmp_cfg[sig_entry].x = true;
+            pmp_cfg[sig_entry].w = true;
+            pmp_cfg[sig_entry].r = false;
+          }
+	  else {
+            // We must set PMP signature region to write/read before starting main. X=0 to be
+            // consistent with MML mode.
+            pmp_cfg[sig_entry].l = false;
+            pmp_cfg[sig_entry].a = pmp_addr_mode_t.NAPOT;
+            pmp_cfg[sig_entry].x = false;
+            pmp_cfg[sig_entry].w = true;
+            pmp_cfg[sig_entry].r = true;
+          }
+        }
       }
-      uvm_info(get_full_name(), format("cfg_byte: 0x%0x", cfg_byte), UVM_DEBUG);
-      // First write to the appropriate pmpaddr CSR
+
+      // Writing MSECCFG with RLB still set to 1 otherwise we cannot complete configuration.
+      uvm_info(get_full_name(), format("MSECCFG: MML %0x, MMWP %0x, RLB 1", mseccfg.mml, mseccfg.mmwp),
+	       UVM_LOW);
+      cfg_byte = booltobit(true) ~ mseccfg.mmwp ~ mseccfg.mml;
+      instr ~= format("csrwi 0x%0x, %0d", privileged_reg_t.MSECCFG, cfg_byte);
+    }
+
+    foreach (i, ref cfg; pmp_cfg) {
+      pmp_id = cast(int) (i/cfg_per_csr);
+      cfg_byte[0] = pmp_cfg[i].r;
+      cfg_byte[1] = pmp_cfg[i].w;
+      cfg_byte[2] = pmp_cfg[i].x;
+      cfg_byte[3..5] = pmp_cfg[i].a;
+      cfg_byte[5..7] = pmp_cfg[i].zero;
+      cfg_byte[7] = pmp_cfg[i].l;
+      uvm_info(get_full_name(), format("cfg_byte: 0x%02x", cfg_byte), UVM_LOW);
+      // First write to the appropriate pmpaddr CSR.
       cfg_bitmask = cfg_byte << ((i % cfg_per_csr) * 8);
-      uvm_info(get_full_name(), format("cfg_bitmask: 0x%0x", cfg_bitmask), UVM_DEBUG);
+      uvm_info(get_full_name(), format("cfg_bitmask: 0x%08x", cfg_bitmask), UVM_DEBUG);
       pmp_word = pmp_word | cfg_bitmask;
-      uvm_info(get_full_name(), format("pmp_word: 0x%0x", pmp_word), UVM_DEBUG);
+      uvm_info(get_full_name(), format("pmp_word: 0x%08x", pmp_word), UVM_DEBUG);
       cfg_bitmask = 0;
 
-      if (i == 0)  {
-        // load the address of the <main> section into pmpaddr0
-        instr ~= format("la x%0d, main", scratch_reg[0]);
-        instr ~= format("srli x%0d, x%0d, 2", scratch_reg[0], scratch_reg[0]);
-        instr ~= format("csrw 0x%0x, x%0d", base_pmp_addr + i, scratch_reg[0]);
-        uvm_info(get_full_name(), "Loaded the address of <main> section into pmpaddr0", UVM_LOW);
-      }
-      else {
-        // If an actual address has been set from the command line, use this address,
-        // otherwise use the default offset+<main> address
-        //
-        // TODO(udinator) - The practice of passing in a max offset from the command line
-        //  is somewhat unintuitive, and is just an initial step. Eventually a max address
-        //  should be passed in from the command line and this routine do all of the
-        //  calculations to split the address range formed by [<main> : pmp_max_addr].
-        //  This will likely require a complex assembly routine - the code below is a very simple
-        //  first step towards this goal, allowing users to specify a PMP memory address
-        //  from the command line instead of having to calculate an offset themselves.
-        if (cfg.addr != 0) {
-	  instr ~= format("li x%0d, 0x%0x", scratch_reg[0], cfg.addr);
-	  instr ~= format("csrw 0x%0x, x%0d", base_pmp_addr + i, scratch_reg[0]);
-	  uvm_info(get_full_name(),
-		   format("Address 0x%0x loaded into pmpaddr[%d] CSR", base_pmp_addr + i, i),
+      // If an actual address has been set from the command line, use this address,
+      // otherwise use the default <main> + offset.
+      //
+      // TODO(udinator) - The practice of passing in a max offset from the command line
+      //  is somewhat unintuitive, and is just an initial step. Eventually a max address
+      //  should be passed in from the command line and this routine do all of the
+      //  calculations to split the address range formed by [<main> : pmp_max_addr].
+      //  This will likely require a complex assembly routine - the code below is a very simple
+      //  first step towards this goal, allowing users to specify a PMP memory address
+      //  from the command line instead of having to calculate an offset themselves.
+      //
+      // Only set the address if it has not already been configured in the above routine.
+      if (pmp_cfg_already_configured[i] == false || pmp_cfg_addr_valid[i]) {
+        if (pmp_cfg_addr_valid[i] || pmp_randomize) {
+          // In case an address was supplied by the test or full randomize is enabled.
+          instr ~= format("li x%0d, 0x%0x", scratch_reg[0], pmp_cfg[i].addr);
+          instr ~= format("csrw 0x%0x, x%0d", base_pmp_addr + i, scratch_reg[0]);
+          uvm_info(get_full_name(), format("Value 0x%08x loaded into pmpaddr[%d] CSR, corresponding to address 0x%0x", pmp_cfg[i].addr, i, pmp_cfg[i].addr << 2),
 		   UVM_LOW);
 	}
 	else {
-          // Add the offset to the base address to get the other pmpaddr values
+          // Add the offset to the base address to get the other pmpaddr values.
           instr ~= format("la x%0d, main", scratch_reg[0]);
-          instr ~= format("li x%0d, 0x%0x", scratch_reg[1], cfg.offset);
+	  instr ~= format("li x%0d, 0x%0x", scratch_reg[1], pmp_cfg[i].offset);
           instr ~= format("add x%0d, x%0d, x%0d",
-				scratch_reg[0], scratch_reg[0], scratch_reg[1]);
+			  scratch_reg[0], scratch_reg[0], scratch_reg[1]);
           instr ~= format("srli x%0d, x%0d, 2", scratch_reg[0], scratch_reg[0]);
-	  instr ~= format("csrw 0x%0x, x%0d", base_pmp_addr + i, scratch_reg[0]);
-	  uvm_info(get_full_name(), format("Offset of pmp_addr_%d from pmpaddr0: 0x%0x",
-					   i, cfg.offset), UVM_LOW);
+          instr ~= format("csrw 0x%0x, x%0d", base_pmp_addr + i, scratch_reg[0]);
+          uvm_info(get_full_name(), format("Offset of pmp_addr_%d from main: 0x%08x", i,
+					   pmp_cfg[i].offset), UVM_LOW);
         }
       }
 
       // Now, check if we have to write to the appropriate pmpcfg CSR.
-      // Short circuit if we reach the end of the list
+      // Short circuit if we reach the end of the list.
       if (i == pmp_cfg.length - 1) {
 
         instr ~= format("li x%0d, 0x%0x", scratch_reg[0], pmp_word);
-        instr ~= format("csrw 0x%0x, x%0d",
-			base_pmpcfg_addr + pmp_id,
+        instr ~= format("csrw 0x%0x, x%0d", base_pmpcfg_addr + pmp_id,
 			scratch_reg[0]);
-        return;
+        break;
       }
       else if ((i + 1) % cfg_per_csr == 0) {
-        // if we've filled up pmp_word, write to the corresponding CSR
+        // if we've filled up pmp_word, write to the corresponding CSR.
         instr ~= format("li x%0d, 0x%0x", scratch_reg[0], pmp_word);
-        instr ~= format("csrw 0x%0x, x%0d",
-			base_pmpcfg_addr + pmp_id,
+        instr ~= format("csrw 0x%0x, x%0d", base_pmpcfg_addr + pmp_id,
 			scratch_reg[0]);
         pmp_word = 0;
       }
     }
-  }
+
+    // Unsetting RLB if that was requested.
+    if (support_epmp && !mseccfg.rlb) {
+      uvm_info(get_full_name(), format("MSECCFG: MML %0x, MMWP %0x, RLB %0x",
+				       mseccfg.mml, mseccfg.mmwp,
+				       mseccfg.rlb), UVM_LOW);
+      cfg_byte = booltobit(mseccfg.rlb) ~
+	booltobit(mseccfg.mmwp) ~ booltobit(mseccfg.mml);
+      instr ~= format("csrwi 0x%0x, %0d", privileged_reg_t.MSECCFG, cfg_byte);
+    }
+ }
 
   // This function creates a special PMP exception routine that is generated within the
   // instr_fault, load_fault, and store_fault exception routines to prevent infinite loops.
@@ -403,25 +748,25 @@ class riscv_pmp_cfg: uvm_object {
   void gen_pmp_exception_routine(riscv_reg_t[] scratch_reg,
 				 exception_cause_t fault_type,
 				 ref string[] instr) {
-    assert (scratch_reg.length == 6);
-    // mscratch       : loop counter
+    assert (scratch_reg.length == 7);
     // scratch_reg[0] : temporary storage
     // scratch_reg[1] : &pmpaddr[i]
     // scratch_reg[2] : &pmpcfg[i]
     // scratch_reg[3] : 8-bit configuration fields
     // scratch_reg[4] : 2-bit pmpcfg[i].A address matching mode
     // scratch_reg[5] : holds the previous pmpaddr[i] value (necessary for TOR matching)
+    // scratch_reg[6] : loop counter
     instr ~=
-      //////////////////////////////////////////////////
-      // Initialize loop counter and save to mscratch //
-      //////////////////////////////////////////////////
+      ////////////////////////////////////////////////////////
+      // Initialize loop counter and save to scratch_reg[6] //
+      ////////////////////////////////////////////////////////
       [format("li x%0d, 0", scratch_reg[0]),
-       format("csrw 0x%0x, x%0d", privileged_reg_t.MSCRATCH, scratch_reg[0]),
+       format("mv x%0d, x%0d", scratch_reg[6], scratch_reg[0]),
        format("li x%0d, 0", scratch_reg[5]),
       ////////////////////////////////////////////////////
       // calculate next pmpaddr and pmpcfg CSRs to read //
       ////////////////////////////////////////////////////
-       format("0: csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MSCRATCH),
+       format("0: mv x%0d, x%0d", scratch_reg[0], scratch_reg[6]),
        format("mv x%0d, x%0d", scratch_reg[4], scratch_reg[0])];
 
     // Generate a sequence of loads and branches that will compare the loop index to every
@@ -450,14 +795,13 @@ class riscv_pmp_cfg: uvm_object {
       // get correct 8-bit configuration fields //
       ////////////////////////////////////////////
       [format("17: li x%0d, %0d", scratch_reg[3], cfg_per_csr),
-       format("csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MSCRATCH),
        // calculate offset to left-shift pmpcfg[i] (scratch_reg[2]),
        // use scratch_reg[4] as temporary storage
        //
        // First calculate (loop_counter % cfg_per_csr)
        format("slli x%0d, x%0d, %0d", scratch_reg[0], scratch_reg[0],
 	      XLEN - clog2(cfg_per_csr)),
-       format("srli x%0d, x%0d, %0d", scratch_reg[0], scratch_reg[0],
+       format("srli x%0d, x%0d, %0d", scratch_reg[0], scratch_reg[6],
 	      XLEN - clog2(cfg_per_csr)),
        // Calculate (cfg_per_csr - modded_loop_counter - 1) to determine how many 8bit slots to
        // the left this needs to be shifted
@@ -491,34 +835,49 @@ class riscv_pmp_cfg: uvm_object {
        format("beq x%0d, x%0d, 21f", scratch_reg[4], scratch_reg[0]),
        // pmpcfg[i].A == NA4
        format("li x%0d, 2", scratch_reg[0]),
-       format("beq x%0d, x%0d, 25f", scratch_reg[4], scratch_reg[0]),
+       format("beq x%0d, x%0d, 24f", scratch_reg[4], scratch_reg[0]),
        // pmpcfg[i].A == NAPOT
        format("li x%0d, 3", scratch_reg[0]),
-       format("beq x%0d, x%0d, 27f", scratch_reg[4], scratch_reg[0]),
+       format("beq x%0d, x%0d, 25f", scratch_reg[4], scratch_reg[0]),
        // Error check, if no address modes match, something has gone wrong
        format("la x%0d, test_done", scratch_reg[0]),
        format("jalr x0, x%0d, 0", scratch_reg[0]),
        /////////////////////////////////////////////////////////////////
        // increment loop counter and branch back to beginning of loop //
        /////////////////////////////////////////////////////////////////
-       format("18: csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MSCRATCH),
+       format("18: mv x%0d, x%0d", scratch_reg[0], scratch_reg[6]),
        // load pmpaddr[i] into scratch_reg[5] to store for iteration [i+1]
        format("mv x%0d, x%0d", scratch_reg[5], scratch_reg[1]),
        // increment loop counter by 1
        format("addi x%0d, x%0d, 1", scratch_reg[0], scratch_reg[0]),
-       // store loop counter to MSCRATCH
-       format("csrw 0x%0x, x%0d", privileged_reg_t.MSCRATCH, scratch_reg[0]),
+       // store loop counter to scratch_reg[6]
+       format("mv x%0d, x%0d", scratch_reg[6], scratch_reg[0]),
        // load number of pmp regions - loop limit
        format("li x%0d, %0d", scratch_reg[1], pmp_num_regions),
        // if counter < pmp_num_regions => branch to beginning of loop,
        // otherwise jump to the end of the loop
        format("ble x%0d, x%0d, 19f", scratch_reg[1], scratch_reg[0]),
-       format("j 0b"),
-       // If we reach here, it means that no PMP entry has matched the request.
-       // We must immediately jump to <test_done> since the CPU is taking a PMP exception,
-       // but this routine is unable to find a matching PMP region for the faulting access -
-       // there is a bug somewhere.
-       format("19: la x%0d, test_done", scratch_reg[0]),
+       format("j 0b")
+       ];
+
+    // If we reach here, it means that no PMP entry has matched the request.
+    // We must immediately jump to <test_done> since the CPU is taking a PMP exception,
+    // but this routine is unable to find a matching PMP region for the faulting access -
+    // there is a bug somewhere.
+    // In case of MMWP mode this is expected behavior, we should try to continue.
+    if (support_epmp) {
+      instr ~=
+	[format("19: csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MSECCFG),
+	 format("andi x%0d, x%0d, 2", scratch_reg[0], scratch_reg[0]),
+	 format("bnez x%0d, 27f", scratch_reg[0])
+	 ];
+    }
+    else {
+      instr ~=
+	[format("19: nop")];
+    }
+    instr ~= 
+      [format("la x%0d, test_done", scratch_reg[0]),
        format("jalr x0, x%0d, 0", scratch_reg[0])];
 
     /////////////////////////////////////////////////
@@ -537,7 +896,7 @@ class riscv_pmp_cfg: uvm_object {
 
     // Sub-section to handle address matching mode TOR.
     instr ~=
-      [format("21: csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MSCRATCH),
+      [format("21: mv x%0d, x%0d", scratch_reg[0], scratch_reg[6]),
        format("csrr x%0d, 0x%0x", scratch_reg[4], privileged_reg_t.MTVAL),
        format("srli x%0d, x%0d, 2", scratch_reg[4], scratch_reg[4]),
        // If loop_counter==0, compare fault_addr to 0
@@ -549,18 +908,12 @@ class riscv_pmp_cfg: uvm_object {
        format("22: bgtu x%0d, x%0d, 18b", scratch_reg[5], scratch_reg[4]),
        // If fault_addr >= pmpaddr[i] : continue looping
        format("23: bleu x%0d, x%0d, 18b", scratch_reg[1], scratch_reg[4]),
-       // If we get here, there is a TOR match, if the entry is locked jump to
-       // <test_done>, otherwise modify access bits and return
-       format("andi x%0d, x%0d, 128", scratch_reg[4], scratch_reg[3]),
-       format("beqz x%0d, 24f", scratch_reg[4]),
-       format("la x%0d, test_done", scratch_reg[0]),
-       format("jalr x0, x%0d, 0", scratch_reg[0]),
-       format("24: j 29f")];
+       format("j 26f")];
 
     // Sub-section to handle address matching mode NA4.
     // TODO(udinator) : add rv64 support
     instr ~=
-      [format("25: csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MTVAL),
+      [format("24: csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MTVAL),
        format("srli x%0d, x%0d, 2", scratch_reg[0], scratch_reg[0]),
        // Zero out pmpaddr[i][31:30]
        format("slli x%0d, x%0d, 2", scratch_reg[4], scratch_reg[1]),
@@ -568,17 +921,11 @@ class riscv_pmp_cfg: uvm_object {
        // If fault_addr[31:2] != pmpaddr[i][29:0] => there is a mismatch,
        // so continue looping
        format("bne x%0d, x%0d, 18b", scratch_reg[0], scratch_reg[4]),
-       // If we get here, there is an NA4 address match, jump to <test_done> if the
-       // entry is locked, otherwise modify access bits
-       format("andi x%0d, x%0d, 128", scratch_reg[4], scratch_reg[3]),
-       format("beqz x%0d, 26f", scratch_reg[4]),
-       format("la x%0d, test_done", scratch_reg[0]),
-       format("jalr x0, x%0d, 0", scratch_reg[0]),
-       format("26: j 29f")];
+       format("j 26f")];
 
     // Sub-section to handle address matching mode NAPOT.
     instr ~=
-      [format("27: csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MTVAL),
+      [format("25: csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MTVAL),
        // get fault_addr[31:2]
        format("srli x%0d, x%0d, 2", scratch_reg[0], scratch_reg[0]),
        // mask the bottom pmp_granularity bits of fault_addr
@@ -592,35 +939,117 @@ class riscv_pmp_cfg: uvm_object {
        format("slli x%0d, x%0d, %0d", scratch_reg[4], scratch_reg[4], pmp_granularity),
        // If masked_fault_addr != masked_pmpaddr[i] : mismatch, so continue looping
        format("bne x%0d, x%0d, 18b", scratch_reg[0], scratch_reg[4]),
-       // If we get here there is an NAPOT address match, jump to <test_done> if
-       // the entry is locked, otherwise modify access bits
+       format("j 26f")];
+
+    // Sub-section that is common to the address modes deciding what to do what to do when hitting
+    // a locked region
+    if (support_epmp) {
+      instr ~=
+	[
+	 // If we get here there is an address match.
+	 // First check whether we are in MML mode.
+	 format("26: csrr x%0d, 0x%0x", scratch_reg[4], privileged_reg_t.MSECCFG),
+	 format("andi x%0d, x%0d, 1", scratch_reg[4], scratch_reg[4]),
+	 format("bnez x%0d, 27f", scratch_reg[4])
+	 ];
+    }
+    else {
+      instr ~=
+	[format("26: nop")];
+    }
+    instr ~=
+      [
+       // Then check whether the lock bit is set.
        format("andi x%0d, x%0d, 128", scratch_reg[4], scratch_reg[3]),
-       format("beqz x%0d, 29f", scratch_reg[4]),
-       format("la x%0d, test_done", scratch_reg[0]),
-       format("jalr x0, x%0d, 0", scratch_reg[0]),
-       format("28: j 29f")];
+       format("bnez x%0d, 27f", scratch_reg[4]),
+       format("j 29f")];
 
 
     // This case statement creates a bitmask that enables the correct access permissions
     // and ORs it with the 8-bit configuration fields.
     switch  (fault_type) {
     case  exception_cause_t.INSTRUCTION_ACCESS_FAULT:
-      instr ~= format("29: ori x%0d, x%0d, 4", scratch_reg[3], scratch_reg[3]);
+      instr ~= 
+	[ // If MML or locked just quit the test.
+	  format("27: la x%0d, test_done", scratch_reg[0]),
+	  format("jalr x0, x%0d, 0", scratch_reg[0]),
+	  // If neither is true then try to modify the PMP permission bits.
+	  // The X bit is bit 2, and 1 << 2 = 2.
+	  format("29: ori x%0d, x%0d, 4", scratch_reg[3], scratch_reg[3])
+	  ];
       break;
     case  exception_cause_t.STORE_AMO_ACCESS_FAULT:
-      // The combination of W:1 and R:0 is reserved, so if we are enabling write
-      // permissions, also enable read permissions to adhere to the spec.
-      instr ~= format("29: ori x%0d, x%0d, 3", scratch_reg[3], scratch_reg[3]);
+      instr ~=
+	[ // If MML or locked try to load the instruction and see if it is compressed so
+	  // the MEPC can be advanced appropriately.
+	  format("27: csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MEPC),
+	  // This might cause a load access fault, which we much handle in the load trap
+	  // handler.
+	  format("lw x%0d, 0(x%0d)", scratch_reg[0], scratch_reg[0]),
+	  // Non-compressed instructions have two least significant bits set to one.
+	  format("li x%0d, 3", scratch_reg[4]),
+	  format("and x%0d, x%0d, x%0d", scratch_reg[0], scratch_reg[0], scratch_reg[4]),
+	  // Check whether instruction is compressed.
+	  format("beq x%0d, x%0d, 28f", scratch_reg[0], scratch_reg[4]),
+	  format("csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MEPC),
+	  // Increase MEPC by 2 in case instruction is compressed.
+	  format("addi x%0d, x%0d, 2", scratch_reg[0], scratch_reg[0]),
+	  format("csrw 0x%0x, x%0d", privileged_reg_t.MEPC, scratch_reg[0]),
+	  format("j 34f"),
+	  format("28: csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MEPC),
+	  // Increase MEPC by 4 in case instruction is compressed.
+	  format("addi x%0d, x%0d, 4", scratch_reg[0], scratch_reg[0]),
+	  format("csrw 0x%0x, x%0d", privileged_reg_t.MEPC, scratch_reg[0]),
+	  format("j 34f"),
+	  // If neither is true then try to modify the PMP permission bits.
+	  // The combination of W:1 and R:0 is reserved, so if we are enabling write
+	  // permissions, also enable read permissions to adhere to the spec.
+	  format("29: ori x%0d, x%0d, 3", scratch_reg[3], scratch_reg[3])
+	  ];
       break;
     case exception_cause_t.LOAD_ACCESS_FAULT:
-      instr ~= format("29: ori x%0d, x%0d, 1", scratch_reg[3], scratch_reg[3]);
+      instr ~=
+	[ // If MML or locked try to load the instruction and see if it is compressed so
+	  // the MEPC can be advanced appropriately.
+	  format("27: csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MEPC),
+	  // We must first check whether the access fault was in the trap handler in case
+	  // we previously tried to load an instruction in a PMP entry that did not have
+	  // read permissions.
+	  format("la x%0d, main", scratch_reg[4]),
+	  format("bge x%0d, x%0d, 40f", scratch_reg[0], scratch_reg[4]),
+	  // In case MEPC is before main, then the load access fault probably happened in a
+	  // trap handler and we should just quit the test.
+	  format("la x%0d, test_done", scratch_reg[0]),
+	  format("jalr x0, x%0d, 0", scratch_reg[0]),
+	  // This might cause a load access fault, which we much handle in the load trap
+	  // handler.
+	  format("40: lw x%0d, 0(x%0d)", scratch_reg[0], scratch_reg[0]),
+	  // Non-compressed instructions have two least significant bits set to one.
+	  format("li x%0d, 3", scratch_reg[4]),
+	  format("and x%0d, x%0d, x%0d", scratch_reg[0], scratch_reg[0], scratch_reg[4]),
+	  // Check whether instruction is compressed.
+	  format("beq x%0d, x%0d, 28f", scratch_reg[0], scratch_reg[4]),
+	  format("csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MEPC),
+	  // Increase MEPC by 2 in case instruction is compressed.
+	  format("addi x%0d, x%0d, 2", scratch_reg[0], scratch_reg[0]),
+	  format("csrw 0x%0x, x%0d", privileged_reg_t.MEPC, scratch_reg[0]),
+	  format("j 34f"),
+	  format("28: csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MEPC),
+	  // Increase MEPC by 4 in case instruction is compressed.
+	  format("addi x%0d, x%0d, 4", scratch_reg[0], scratch_reg[0]),
+	  format("csrw 0x%0x, x%0d", privileged_reg_t.MEPC, scratch_reg[0]),
+	  format("j 34f"),
+	  // If neither is true then try to modify the PMP permission bits.
+	  // The R bit is bit 0, and 1 << 0 = 1.
+	  format("29: ori x%0d, x%0d, 1", scratch_reg[3], scratch_reg[3])
+	  ];
       break;
     default:
       uvm_fatal(get_full_name(), "Invalid PMP fault type");
       break;
     }
     instr ~=
-      [format("csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MSCRATCH),
+      [
        // Calculate (loop_counter % cfg_per_csr) to find the index of the correct
        // entry in pmpcfg[i].
        //
@@ -629,7 +1058,7 @@ class riscv_pmp_cfg: uvm_object {
        format("li x%0d, %0d", scratch_reg[4], XLEN - clog2(cfg_per_csr)),
        // Now leftshift and rightshift loop_counter by this amount to clear all the upper
        // bits
-       format("sll x%0d, x%0d, x%0d", scratch_reg[0], scratch_reg[0], scratch_reg[4]),
+       format("sll x%0d, x%0d, x%0d", scratch_reg[0], scratch_reg[6], scratch_reg[4]),
        format("srl x%0d, x%0d, x%0d", scratch_reg[0], scratch_reg[0], scratch_reg[4]),
        // Multiply the index by 8 to get the shift amount.
        format("slli x%0d, x%0d, 3", scratch_reg[4], scratch_reg[0]),
@@ -638,7 +1067,7 @@ class riscv_pmp_cfg: uvm_object {
        // OR pmpcfg[i] with the updated configuration byte
        format("or x%0d, x%0d, x%0d", scratch_reg[2], scratch_reg[2], scratch_reg[3]),
        // Divide the loop counter by cfg_per_csr to determine which pmpcfg CSR to write to.
-       format("csrr x%0d, 0x%0x", scratch_reg[0], privileged_reg_t.MSCRATCH),
+       format("mv x%0d, x%0d", scratch_reg[0], scratch_reg[6]),
        format("srli x%0d, x%0d, %0d", scratch_reg[0], scratch_reg[0], clog2(cfg_per_csr)),
        // Write the updated pmpcfg[i] to the CSR bank and exit the handler.
        //
@@ -715,7 +1144,7 @@ class riscv_pmp_cfg: uvm_object {
 
       for (size_t j=0; j!=XLEN/8; ++j) {
 	pmp_val[j*8+7] = false;
-	ubvec!XLEN mask = ~ (toubvec!XLEN(0b11));
+	ubvec!XLEN mask = ~ UBVEC!(XLEN, 0b11);
 	ubvec!XLEN bits;
 	uint r;
 
@@ -739,7 +1168,13 @@ class riscv_pmp_cfg: uvm_object {
       // If we're writing to the pmpcfg CSR that contains region0 config information,
       // ensure that the "safe" region remains fully accessible.
       if (pmpcfg_addr == base_pmpcfg_addr) {
-	pmp_val[0..8] = cast(ubyte) 0x0f;
+	if (mseccfg.mml) {
+          // In case of MML make this a shared code region with LXWR='b1010.
+          pmp_val[0..8] = 0x8a;
+	}
+	else {
+          pmp_val[0..8] = 0x0f;
+        }
       }
       instr ~= format("li x%0d, 0x%0x", scratch_reg[0], pmp_val);
       // Write the randomized address to pmpcfg[i].
diff --git a/euvm/riscv/gen/riscv_privil_reg.d b/euvm/riscv/gen/riscv_privil_reg.d
index ae54813b..b42e2125 100644
--- a/euvm/riscv/gen/riscv_privil_reg.d
+++ b/euvm/riscv/gen/riscv_privil_reg.d
@@ -287,6 +287,20 @@ class riscv_privil_reg: riscv_reg!(privileged_reg_t)
       privil_level = privileged_level_t.M_LEVEL;
       add_field("VALUE",  XLEN,  reg_field_access_t.WARL);
       break;
+      // Machine security configuration
+    case privileged_reg_t.MSECCFG:
+      privil_level = privileged_level_t.M_LEVEL;
+      add_field("MML", 1, reg_field_access_t.WARL); // RW1S
+      add_field("MMWP", 1, reg_field_access_t.WARL); // RW1S
+      add_field("RLB", 1, reg_field_access_t.WARL); // RW0C
+      break;
+      // Machine security configuration, RV32 only
+    case privileged_reg_t.MSECCFGH:
+      privil_level = privileged_level_t.M_LEVEL;
+      if (XLEN!=32) {
+	uvm_fatal(get_full_name(), "CSR MSECCFGH only exists in RV32.");
+      }
+      break;
       // Physical Memory Protection Configuration Register
     case privileged_reg_t.PMPCFG0:
       privil_level = privileged_level_t.M_LEVEL;
diff --git a/euvm/riscv/gen/riscv_privileged_common_seq.d b/euvm/riscv/gen/riscv_privileged_common_seq.d
index 8b41a916..0ad6a0d6 100644
--- a/euvm/riscv/gen/riscv_privileged_common_seq.d
+++ b/euvm/riscv/gen/riscv_privileged_common_seq.d
@@ -20,7 +20,7 @@
 module riscv.gen.riscv_privileged_common_seq;
 
 import riscv.gen.riscv_instr_pkg: privileged_mode_t, privileged_reg_t,
-  format_string, indent, satp_mode_t, hart_prefix, LABEL_STR_LEN;
+  INDENT, satp_mode_t, hart_prefix, LABEL_STR_LEN;
 import riscv.gen.target: supported_privileged_mode, support_umode_trap,
   implemented_csr, XLEN, SATP_MODE;
 import riscv.gen.riscv_instr_gen_config: riscv_instr_gen_config;
@@ -31,17 +31,18 @@ import std.format: format;
 import std.string: toLower;
 
 import esdl.data.queue: Queue;
-import esdl.data.bvec: ubvec, toubvec;
-import esdl.rand: randomize;
+import esdl.data.bvec: ubvec, UBVEC;
+import esdl.rand: randomize, rand;
 
 import uvm;
 
-class riscv_privileged_common_seq : uvm_sequence!(uvm_sequence_item,uvm_sequence_item)
+class riscv_privileged_common_seq: uvm_sequence!(uvm_sequence_item,uvm_sequence_item)
 {
 
   riscv_instr_gen_config  cfg;
   int                     hart;
   riscv_privil_reg        mstatus;
+  @rand bool              mstatus_mie;
   riscv_privil_reg        mie;
   riscv_privil_reg        sstatus;
   riscv_privil_reg        sie;
@@ -57,8 +58,9 @@ class riscv_privileged_common_seq : uvm_sequence!(uvm_sequence_item,uvm_sequence
   void enter_privileged_mode(in privileged_mode_t mode,
 			     out Queue!string instrs) {
     import std.conv: to;
-    string label = format_string(format("%0sinit_%0s:",
-					hart_prefix(hart), mode), LABEL_STR_LEN);
+    enum string FMT = "%-" ~ LABEL_STR_LEN.stringof ~ "s";
+    string label = format!FMT(format("%0sinit_%0s:",
+				     hart_prefix(hart), mode));
     string[] ret_instr = ["mret"];
     riscv_privil_reg[] regs;
     label = label.toLower();
@@ -76,7 +78,7 @@ class riscv_privileged_common_seq : uvm_sequence!(uvm_sequence_item,uvm_sequence
     // Use mret/sret to switch to the target privileged mode
     instrs ~= ret_instr[0];
     foreach (instr; instrs) {
-      instr = indent ~ instr;
+      instr = INDENT ~ instr;
     }
     instrs.pushFront(label);
   }
@@ -84,8 +86,9 @@ class riscv_privileged_common_seq : uvm_sequence!(uvm_sequence_item,uvm_sequence
   void enter_privileged_mode(in privileged_mode_t mode,
 			     out string[] instrs) {
     import std.conv: to;
-    string label = format_string(format("%0sinit_%0s:",
-					hart_prefix(hart), mode), LABEL_STR_LEN);
+    enum string FMT = "%-" ~ LABEL_STR_LEN.stringof ~ "s";
+    string label = format!FMT(format("%0sinit_%0s:",
+				     hart_prefix(hart), mode));
     string[] ret_instr = ["mret"];
     riscv_privil_reg[] regs;
     label = label.toLower();
@@ -105,7 +108,7 @@ class riscv_privileged_common_seq : uvm_sequence!(uvm_sequence_item,uvm_sequence
     instrs ~= ret_instr[0];
     foreach (i, ref instr; instrs) {
       if (i != 0)		// skip indent for label
-	instr = indent ~ instr;
+	instr = INDENT ~ instr;
     }
     // instrs.pushFront(label); // do it upfront
   }
@@ -123,16 +126,16 @@ class riscv_privileged_common_seq : uvm_sequence!(uvm_sequence_item,uvm_sequence
     mstatus.set_field("TW", cfg.set_mstatus_tw);
     mstatus.set_field("FS", cfg.mstatus_fs);
     mstatus.set_field("VS", cfg.mstatus_vs);
-    if (!(canFind(supported_privileged_mode, privileged_mode_t.SUPERVISOR_MODE) && (XLEN != 32))) {
-      mstatus.set_field("SXL", toubvec!2(0b00));
+    if (!(canFind(supported_privileged_mode, privileged_mode_t.SUPERVISOR_MODE)) && (XLEN != 32)) {
+      mstatus.set_field("SXL", UBVEC!(2, 0b00));
     }
     else if (XLEN == 64) {
-      mstatus.set_field("SXL", toubvec!2(0b10));
+      mstatus.set_field("SXL", UBVEC!(2, 0b10));
     }
-    if (!(canFind(supported_privileged_mode, privileged_mode_t.USER_MODE) && (XLEN != 32))) {
-      mstatus.set_field("UXL", toubvec!2(0b00));
+    if (!(canFind(supported_privileged_mode, privileged_mode_t.USER_MODE)) && (XLEN != 32)) {
+      mstatus.set_field("UXL", UBVEC!(2, 0b00));
     } else if (XLEN == 64) {
-      mstatus.set_field("UXL", toubvec!2(0b10));
+      mstatus.set_field("UXL", UBVEC!(2, 0b10));
     }
     mstatus.set_field("XS", 0);
     mstatus.set_field("SD", 0);
@@ -141,8 +144,15 @@ class riscv_privileged_common_seq : uvm_sequence!(uvm_sequence_item,uvm_sequence
     mstatus.set_field("MPP", mode);
     mstatus.set_field("SPP", 0);
     // Enable interrupt
-    mstatus.set_field("MPIE", cfg.enable_interrupt);
-    mstatus.set_field("MIE", cfg.enable_interrupt);
+    // Only machine mode requires mstatus.MIE to be 1 for enabling interrupt
+    if (mode == privileged_mode_t.MACHINE_MODE) {
+      mstatus.set_field("MPIE", cfg.enable_interrupt);
+    }
+    else {
+      mstatus.set_field("MPIE", cfg.enable_interrupt & mstatus_mie);
+    }
+    // MIE is set when returning with mret, avoids trapping before returning
+    mstatus.set_field("MIE", 0);
     mstatus.set_field("SPIE", cfg.enable_interrupt);
     mstatus.set_field("SIE",  cfg.enable_interrupt);
     mstatus.set_field("UPIE", cfg.enable_interrupt);
@@ -181,7 +191,7 @@ class riscv_privileged_common_seq : uvm_sequence!(uvm_sequence_item,uvm_sequence
     sstatus.set_field("UPIE", cfg.enable_interrupt);
     sstatus.set_field("UIE", support_umode_trap);
     if(XLEN==64) {
-      sstatus.set_field("UXL", toubvec!2(0b10));
+      sstatus.set_field("UXL", UBVEC!(2, 0b10));
     }
     sstatus.set_field("FS", cfg.mstatus_fs);
     sstatus.set_field("XS", 0);
diff --git a/euvm/riscv/gen/riscv_pseudo_instr.d b/euvm/riscv/gen/riscv_pseudo_instr.d
index 7ef13cd3..18dd7c0e 100644
--- a/euvm/riscv/gen/riscv_pseudo_instr.d
+++ b/euvm/riscv/gen/riscv_pseudo_instr.d
@@ -19,7 +19,7 @@
 module riscv.gen.riscv_pseudo_instr;
 
 import riscv.gen.riscv_instr_pkg: riscv_pseudo_instr_name_t, riscv_instr_format_t,
-  riscv_instr_category_t, riscv_instr_group_t, format_string, MAX_INSTR_STR_LEN;
+  riscv_instr_category_t, riscv_instr_group_t, MAX_INSTR_STR_LEN;
 import riscv.gen.isa.riscv_instr: riscv_instr;
 
 import std.format: format;
@@ -60,12 +60,35 @@ class riscv_pseudo_instr: riscv_instr
 
   // Convert the instruction to assembly code
   override string convert2asm(string prefix = "") {
-    string asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN);
-    // instr rd,imm
-    asm_str = format("%0s%0s, %0s", asm_str, rd, get_imm());
-    if (comment != "")
-      asm_str ~= " #"~comment;
-    return asm_str.toLower();
+    if (comment.length == 0) {
+      enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s%0s, %0s";
+      string asm_str = format!FMT(get_instr_name(), rd, get_imm());
+      return asm_str.toLower();
+    }
+    else {
+      enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s%0s, %0s #%s";
+      string asm_str = format!FMT(get_instr_name(), rd, get_imm(), comment);
+      return asm_str.toLower();
+    }
+  }
+
+  override char[] convert2asm(char[] buf, string prefix = "") {
+    import std.format: sformat;
+    import std.string: toLower, toLowerInPlace;
+    char[32] instr_buf;
+    
+    if (comment.length == 0) {
+      enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s%0s, %0s";
+      char[] asm_str = sformat!FMT(buf, get_instr_name(instr_buf), rd, get_imm());
+      asm_str.toLowerInPlace();
+      return asm_str;
+    }
+    else {
+      enum string FMT = "%-" ~ MAX_INSTR_STR_LEN.stringof ~ "s%0s, %0s #%s";
+      char[] asm_str = sformat!FMT(buf, get_instr_name(instr_buf), rd, get_imm(), comment);
+      asm_str.toLowerInPlace();
+      return asm_str;
+    }
   }
 
   override string get_instr_name() {
@@ -73,4 +96,10 @@ class riscv_pseudo_instr: riscv_instr
     return pseudo_instr_name.to!string();
   }
 
+  override char[] get_instr_name(char[] buf) {
+    import std.format: sformat;
+    char[] str_instr_name = sformat!("%s")(buf, pseudo_instr_name);
+    return str_instr_name;
+  }
+
 }
diff --git a/euvm/riscv/gen/riscv_reg.d b/euvm/riscv/gen/riscv_reg.d
index 96699ddf..1562102d 100644
--- a/euvm/riscv/gen/riscv_reg.d
+++ b/euvm/riscv/gen/riscv_reg.d
@@ -24,7 +24,7 @@
 module riscv.gen.riscv_reg;
 
 
-import esdl.data.bvec: ubvec, toubvec;
+import esdl.data.bvec: ubvec;
 import riscv.gen.riscv_instr_pkg: reg_field_access_t, privileged_reg_t,
   privileged_level_t, riscv_csr_t;
 import riscv.gen.target: XLEN;
@@ -88,7 +88,7 @@ class riscv_reg(REG_T): uvm_object
 
   void init_reg(REG_T reg_name) {
     this.reg_name = reg_name;
-    offset = toubvec!12(reg_name);
+    offset = cast (riscv_csr_t) (reg_name);
   }
 
   ubvec!XLEN get_val() {
diff --git a/euvm/riscv/gen/riscv_vector_cfg.d b/euvm/riscv/gen/riscv_vector_cfg.d
index 51a35751..aa0d7157 100644
--- a/euvm/riscv/gen/riscv_vector_cfg.d
+++ b/euvm/riscv/gen/riscv_vector_cfg.d
@@ -107,7 +107,7 @@ class riscv_vector_cfg : uvm_object
      if (vec_quad_widening) {
        vtype.vlmul < 4 || (vtype.fractional_lmul == true);
      }
-   } vlmul_c ;
+   } vlmul_c;
 
    constraint! q{
      vtype.vsew inside [8, 16, 32, 64, 128];
diff --git a/euvm/riscv/gen/target/ml/riscv_core_setting.d b/euvm/riscv/gen/target/ml/riscv_core_setting.d
index ec34a61a..f4d10de8 100644
--- a/euvm/riscv/gen/target/ml/riscv_core_setting.d
+++ b/euvm/riscv/gen/target/ml/riscv_core_setting.d
@@ -50,6 +50,9 @@ int max_interrupt_vector_num = 16;
 // Physical memory protection support
 enum bool support_pmp = false;
 
+// Enhanced physical memory protection support
+enum bool support_epmp = false;
+
 // Debug mode support
 enum bool support_debug_mode = false;
 
diff --git a/euvm/riscv/gen/target/multi_harts/riscv_core_setting.d b/euvm/riscv/gen/target/multi_harts/riscv_core_setting.d
index acd5f5d1..61950c82 100644
--- a/euvm/riscv/gen/target/multi_harts/riscv_core_setting.d
+++ b/euvm/riscv/gen/target/multi_harts/riscv_core_setting.d
@@ -45,11 +45,14 @@ mtvec_mode_t[] supported_interrupt_mode  = [mtvec_mode_t.DIRECT, mtvec_mode_t.VE
 
 // The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is
 // supported
-int max_interrupt_vector_num = 16;
+enum int max_interrupt_vector_num = 16;
 
 // Physical memory protection support
 enum bool support_pmp = false;
 
+// Enhanced physical memory protection support
+enum bool support_epmp = false;
+
 // Debug mode support
 enum bool support_debug_mode = false;
 
diff --git a/euvm/riscv/gen/target/package.d b/euvm/riscv/gen/target/package.d
index c0518960..3617ec1b 100644
--- a/euvm/riscv/gen/target/package.d
+++ b/euvm/riscv/gen/target/package.d
@@ -44,6 +44,10 @@ version(RV32IMCB) {
    pragma (msg, "Using target: RV32IMC");
    public import riscv.gen.target.rv32imc.riscv_core_setting;
  }
+ else version(RV64IMP) {
+   pragma (msg, "Using target: RV64IMP");
+   public import riscv.gen.target.rv64imp.riscv_core_setting;
+ }
  else {
    pragma (msg, "Using Default target: RV64IMC");
    public import riscv.gen.target.rv64imc.riscv_core_setting;
diff --git a/euvm/riscv/gen/target/rv32i/riscv_core_setting.d b/euvm/riscv/gen/target/rv32i/riscv_core_setting.d
index d41147de..d32fb3ff 100644
--- a/euvm/riscv/gen/target/rv32i/riscv_core_setting.d
+++ b/euvm/riscv/gen/target/rv32i/riscv_core_setting.d
@@ -46,11 +46,14 @@ mtvec_mode_t[] supported_interrupt_mode  = [mtvec_mode_t.DIRECT, mtvec_mode_t.VE
 
 // The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is
 // supported
-int max_interrupt_vector_num = 16;
+enum int max_interrupt_vector_num = 16;
 
 // Physical memory protection support
 enum bool support_pmp = false;
 
+// Enhanced physical memory protection support
+enum bool support_epmp = false;
+
 // Debug mode support
 enum bool support_debug_mode = false;
 
@@ -132,7 +135,6 @@ enum interrupt_cause_t[] implemented_interrupt = [ interrupt_cause_t.M_SOFTWARE_
 						   ];
 
 enum exception_cause_t[] implemented_exception = [
-
 						  exception_cause_t.INSTRUCTION_ACCESS_FAULT,
 						  exception_cause_t.ILLEGAL_INSTRUCTION,
 						  exception_cause_t.BREAKPOINT,
diff --git a/euvm/riscv/gen/target/rv32imafdc/riscv_core_setting.d b/euvm/riscv/gen/target/rv32imafdc/riscv_core_setting.d
index 68c2e437..a14cb53e 100644
--- a/euvm/riscv/gen/target/rv32imafdc/riscv_core_setting.d
+++ b/euvm/riscv/gen/target/rv32imafdc/riscv_core_setting.d
@@ -53,11 +53,14 @@ mtvec_mode_t[] supported_interrupt_mode = [mtvec_mode_t.DIRECT, mtvec_mode_t.VEC
 
 // The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is
 // supported
-int max_interrupt_vector_num = 16;
+enum int max_interrupt_vector_num = 16;
 
 // Physical memory protection support
 enum bool support_pmp = false;
 
+// Enhanced physical memory protection support
+enum bool support_epmp = false;
+
 // Debug mode support
 enum bool support_debug_mode = false;
 
diff --git a/euvm/riscv/gen/target/rv32imc/riscv_core_setting.d b/euvm/riscv/gen/target/rv32imc/riscv_core_setting.d
index 626aed61..0cd13d57 100644
--- a/euvm/riscv/gen/target/rv32imc/riscv_core_setting.d
+++ b/euvm/riscv/gen/target/rv32imc/riscv_core_setting.d
@@ -48,11 +48,14 @@ mtvec_mode_t[] supported_interrupt_mode  = [mtvec_mode_t.DIRECT, mtvec_mode_t.VE
 
 // The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is
 // supported
-int max_interrupt_vector_num = 16;
+enum int max_interrupt_vector_num = 16;
 
 // Physical memory protection support
 enum bool support_pmp = false;
 
+// Enhanced physical memory protection support
+enum bool support_epmp = false;
+
 // Debug mode support
 enum bool support_debug_mode = false;
 
@@ -134,7 +137,6 @@ enum interrupt_cause_t[] implemented_interrupt = [ interrupt_cause_t.M_SOFTWARE_
 						   ];
 
 enum exception_cause_t[] implemented_exception = [
-
 						  exception_cause_t.INSTRUCTION_ACCESS_FAULT,
 						  exception_cause_t.ILLEGAL_INSTRUCTION,
 						  exception_cause_t.BREAKPOINT,
diff --git a/euvm/riscv/gen/target/rv32imc_sv32/riscv_core_setting.d b/euvm/riscv/gen/target/rv32imc_sv32/riscv_core_setting.d
index 76444932..f9e9720a 100644
--- a/euvm/riscv/gen/target/rv32imc_sv32/riscv_core_setting.d
+++ b/euvm/riscv/gen/target/rv32imc_sv32/riscv_core_setting.d
@@ -48,11 +48,14 @@ mtvec_mode_t[] supported_interrupt_mode  = [mtvec_mode_t.DIRECT, mtvec_mode_t.VE
 
 // The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is
 // supported
-int max_interrupt_vector_num = 16;
+enum int max_interrupt_vector_num = 16;
 
 // Physical memory protection support
 enum bool support_pmp = false;
 
+// Enhanced physical memory protection support
+enum bool support_epmp = false;
+
 // Debug mode support
 enum bool support_debug_mode = false;
 
diff --git a/euvm/riscv/gen/target/rv32imcb/riscv_core_setting.d b/euvm/riscv/gen/target/rv32imcb/riscv_core_setting.d
index b94ecd64..964411c9 100644
--- a/euvm/riscv/gen/target/rv32imcb/riscv_core_setting.d
+++ b/euvm/riscv/gen/target/rv32imcb/riscv_core_setting.d
@@ -49,11 +49,14 @@ mtvec_mode_t[] supported_interrupt_mode  = [mtvec_mode_t.DIRECT, mtvec_mode_t.VE
 
 // The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is
 // supported
-int max_interrupt_vector_num = 16;
+enum int max_interrupt_vector_num = 16;
 
 // Physical memory protection support
 enum bool support_pmp = false;
 
+// Enhanced physical memory protection support
+enum bool support_epmp = false;
+
 // Debug mode support
 enum bool support_debug_mode = false;
 
@@ -135,7 +138,6 @@ enum interrupt_cause_t[] implemented_interrupt = [ interrupt_cause_t.M_SOFTWARE_
 						   ];
 
 enum exception_cause_t[] implemented_exception = [
-
 						  exception_cause_t.INSTRUCTION_ACCESS_FAULT,
 						  exception_cause_t.ILLEGAL_INSTRUCTION,
 						  exception_cause_t.BREAKPOINT,
diff --git a/euvm/riscv/gen/target/rv64gc/riscv_core_setting.d b/euvm/riscv/gen/target/rv64gc/riscv_core_setting.d
index 50a8843b..cbca0c64 100644
--- a/euvm/riscv/gen/target/rv64gc/riscv_core_setting.d
+++ b/euvm/riscv/gen/target/rv64gc/riscv_core_setting.d
@@ -62,6 +62,9 @@ enum int max_interrupt_vector_num = 16;
 // Physical memory protection support
 enum bool support_pmp = false;
 
+// Enhanced physical memory protection support
+enum bool support_epmp = false;
+
 // Debug mode support
 enum bool support_debug_mode = false;
 
diff --git a/euvm/riscv/gen/target/rv64gcv/riscv_core_setting.d b/euvm/riscv/gen/target/rv64gcv/riscv_core_setting.d
index bebcb588..775c9c1e 100644
--- a/euvm/riscv/gen/target/rv64gcv/riscv_core_setting.d
+++ b/euvm/riscv/gen/target/rv64gcv/riscv_core_setting.d
@@ -63,6 +63,9 @@ enum int max_interrupt_vector_num = 16;
 // Physical memory protection support
 enum bool support_pmp = false;
 
+// Enhanced physical memory protection support
+enum bool support_epmp = false;
+
 // Debug mode support
 enum bool support_debug_mode = false;
 
diff --git a/euvm/riscv/gen/target/rv64imafdc/riscv_core_setting.d b/euvm/riscv/gen/target/rv64imafdc/riscv_core_setting.d
new file mode 100644
index 00000000..f56cef9a
--- /dev/null
+++ b/euvm/riscv/gen/target/rv64imafdc/riscv_core_setting.d
@@ -0,0 +1,197 @@
+/*
+ * Copyright 2019 Google LLC
+ * Copyright 2022 Coverify Systems Technology
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//-----------------------------------------------------------------------------
+// Processor feature configuration
+//-----------------------------------------------------------------------------
+// XLEN
+
+module riscv.gen.target.rv64imafdc.riscv_core_setting;
+
+import riscv.gen.riscv_instr_pkg: satp_mode_t, privileged_mode_t,
+  riscv_instr_name_t, mtvec_mode_t, interrupt_cause_t,
+  exception_cause_t, riscv_instr_group_t, privileged_reg_t;
+import esdl: ubvec, flog2;
+
+enum int XLEN = 64;
+
+// Parameter for SATP mode, set to BARE if address translation is not supported
+enum satp_mode_t SATP_MODE = satp_mode_t.SV39;
+
+// Supported Privileged mode
+privileged_mode_t[] supported_privileged_mode = [privileged_mode_t.USER_MODE,
+						 privileged_mode_t.SUPERVISOR_MODE,
+						 privileged_mode_t.MACHINE_MODE];
+
+// Unsupported instructions
+riscv_instr_name_t[] unsupported_instr = [];
+
+// ISA supported by the processor
+riscv_instr_group_t[] supported_isa = [riscv_instr_group_t.RV32I,
+				       riscv_instr_group_t.RV32M,
+				       riscv_instr_group_t.RV64I,
+				       riscv_instr_group_t.RV64M,
+				       riscv_instr_group_t.RV32C,
+				       riscv_instr_group_t.RV64C,
+				       riscv_instr_group_t.RV32A,
+				       riscv_instr_group_t.RV64A,
+				       riscv_instr_group_t.RV32F,
+				       riscv_instr_group_t.RV64F,
+				       riscv_instr_group_t.RV32D,
+				       riscv_instr_group_t.RV64D,
+				       riscv_instr_group_t.RV32X];
+
+// Interrupt mode support
+mtvec_mode_t[] supported_interrupt_mode = [mtvec_mode_t.DIRECT,
+					   mtvec_mode_t.VECTORED];
+
+// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is
+// supported
+enum int max_interrupt_vector_num = 16;
+
+// Physical memory protection support
+enum bool support_pmp = false;
+
+// Enhanced physical memory protection support
+enum bool support_epmp = false;
+
+// Debug mode support
+enum bool support_debug_mode = false;
+
+// Support delegate trap to user mode
+enum bool support_umode_trap = false;
+
+// Support sfence.vma instruction
+enum bool support_sfence = true;
+
+// Support unaligned load/store
+enum bool support_unaligned_load_store = true;
+
+// GPR setting
+enum int NUM_FLOAT_GPR = 32;
+enum int NUM_GPR = 32;
+enum int NUM_VEC_GPR = 32;
+// ----------------------------------------------------------------------------
+// Vector extension configuration
+// ----------------------------------------------------------------------------
+
+// Parameter for vector extension
+enum int VECTOR_EXTENSION_ENABLE = 0;
+
+enum int VLEN = 512;
+
+// Maximum size of a single vector element
+enum int ELEN = 32;
+
+// Minimum size of a sub-element, which must be at most 8-bits.
+enum int SELEN = 8;
+
+// Maximum size of a single vector element (encoded in vsew format)
+enum int VELEN = flog2(ELEN) - 3;
+
+static assert (VELEN == 2);
+
+// Maxium LMUL supported by the core
+enum int MAX_LMUL = 8;
+
+// ----------------------------------------------------------------------------
+// Multi-harts configuration
+// ----------------------------------------------------------------------------
+
+// Number of harts
+enum int NUM_HARTS = 1;
+
+// ----------------------------------------------------------------------------
+// Previleged CSR implementation
+// ----------------------------------------------------------------------------
+
+// Implemented previlieged CSR list
+enum privileged_reg_t[] implemented_csr = [
+    // User mode CSR
+    privileged_reg_t.USTATUS,    // User status
+    privileged_reg_t.UIE,        // User interrupt-enable register
+    privileged_reg_t.UTVEC,      // User trap-handler base address
+    privileged_reg_t.USCRATCH,   // Scratch register for user trap handlers
+    privileged_reg_t.UEPC,       // User exception program counter
+    privileged_reg_t.UCAUSE,     // User trap cause
+    privileged_reg_t.UTVAL,      // User bad address or instruction
+    privileged_reg_t.UIP,        // User interrupt pending
+    // Supervisor mode CSR
+    privileged_reg_t.SSTATUS,    // Supervisor status
+    privileged_reg_t.SEDELEG,    // Supervisor exception delegation register
+    privileged_reg_t.SIDELEG,    // Supervisor interrupt delegation register
+    privileged_reg_t.SIE,        // Supervisor interrupt-enable register
+    privileged_reg_t.STVEC,      // Supervisor trap-handler base address
+    privileged_reg_t.SCOUNTEREN, // Supervisor counter enable
+    privileged_reg_t.SSCRATCH,   // Scratch register for supervisor trap handlers
+    privileged_reg_t.SEPC,       // Supervisor exception program counter
+    privileged_reg_t.SCAUSE,     // Supervisor trap cause
+    privileged_reg_t.STVAL,      // Supervisor bad address or instruction
+    privileged_reg_t.SIP,        // Supervisor interrupt pending
+    privileged_reg_t.SATP,       // Supervisor address translation and protection
+    // Machine mode mode CSR
+    privileged_reg_t.MVENDORID,  // Vendor ID
+    privileged_reg_t.MARCHID,    // Architecture ID
+    privileged_reg_t.MIMPID,     // Implementation ID
+    privileged_reg_t.MHARTID,    // Hardware thread ID
+    privileged_reg_t.MSTATUS,    // Machine status
+    privileged_reg_t.MISA,       // ISA and extensions
+    privileged_reg_t.MEDELEG,    // Machine exception delegation register
+    privileged_reg_t.MIDELEG,    // Machine interrupt delegation register
+    privileged_reg_t.MIE,        // Machine interrupt-enable register
+    privileged_reg_t.MTVEC,      // Machine trap-handler base address
+    privileged_reg_t.MCOUNTEREN, // Machine counter enable
+    privileged_reg_t.MSCRATCH,   // Scratch register for machine trap handlers
+    privileged_reg_t.MEPC,       // Machine exception program counter
+    privileged_reg_t.MCAUSE,     // Machine trap cause
+    privileged_reg_t.MTVAL,      // Machine bad address or instruction
+    privileged_reg_t.MIP,        // Machine interrupt pending
+    // Floating point CSR
+    privileged_reg_t.FCSR        // Floating point control and status
+];
+
+// Implementation-specific custom CSRs
+ubvec!12[] custom_csr = [];
+
+// ----------------------------------------------------------------------------
+// Supported interrupt/exception setting, used for functional coverage
+// ----------------------------------------------------------------------------
+
+enum interrupt_cause_t[] implemented_interrupt = [interrupt_cause_t.U_SOFTWARE_INTR,
+						  interrupt_cause_t.S_SOFTWARE_INTR,
+						  interrupt_cause_t.M_SOFTWARE_INTR,
+						  interrupt_cause_t.U_TIMER_INTR,
+						  interrupt_cause_t.S_TIMER_INTR,
+						  interrupt_cause_t.M_TIMER_INTR,
+						  interrupt_cause_t.U_EXTERNAL_INTR,
+						  interrupt_cause_t.S_EXTERNAL_INTR,
+						  interrupt_cause_t.M_EXTERNAL_INTR];
+
+enum exception_cause_t[] implemented_exception = [exception_cause_t.INSTRUCTION_ACCESS_FAULT,
+						  exception_cause_t.ILLEGAL_INSTRUCTION,
+						  exception_cause_t.BREAKPOINT,
+						  exception_cause_t.LOAD_ADDRESS_MISALIGNED,
+						  exception_cause_t.LOAD_ACCESS_FAULT,
+						  exception_cause_t.STORE_AMO_ADDRESS_MISALIGNED,
+						  exception_cause_t.STORE_AMO_ACCESS_FAULT,
+						  exception_cause_t.ECALL_UMODE,
+						  exception_cause_t.ECALL_SMODE,
+						  exception_cause_t.ECALL_MMODE,
+						  exception_cause_t.INSTRUCTION_PAGE_FAULT,
+						  exception_cause_t.LOAD_PAGE_FAULT,
+						  exception_cause_t.STORE_AMO_PAGE_FAULT
+						  ];
diff --git a/euvm/riscv/gen/target/rv64imc/riscv_core_setting.d b/euvm/riscv/gen/target/rv64imc/riscv_core_setting.d
index 89cb7dc1..75058dab 100644
--- a/euvm/riscv/gen/target/rv64imc/riscv_core_setting.d
+++ b/euvm/riscv/gen/target/rv64imc/riscv_core_setting.d
@@ -57,6 +57,9 @@ enum int max_interrupt_vector_num = 16;
 // Physical memory protection support
 enum bool support_pmp = false;
 
+// Enhanced physical memory protection support
+enum bool support_epmp = false;
+
 // Debug mode support
 enum bool support_debug_mode = false;
 
diff --git a/euvm/riscv/gen/target/rv64imcb/riscv_core_setting.d b/euvm/riscv/gen/target/rv64imcb/riscv_core_setting.d
index 895a4efb..84c7d69b 100644
--- a/euvm/riscv/gen/target/rv64imcb/riscv_core_setting.d
+++ b/euvm/riscv/gen/target/rv64imcb/riscv_core_setting.d
@@ -59,6 +59,9 @@ enum int max_interrupt_vector_num = 16;
 // Physical memory protection support
 enum bool support_pmp = false;
 
+// Enhanced physical memory protection support
+enum bool support_epmp = false;
+
 // Debug mode support
 enum bool support_debug_mode = false;
 
diff --git a/euvm/riscv/gen/target/rv64imp/riscv_core_setting.d b/euvm/riscv/gen/target/rv64imp/riscv_core_setting.d
new file mode 100644
index 00000000..c82e0bea
--- /dev/null
+++ b/euvm/riscv/gen/target/rv64imp/riscv_core_setting.d
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2019 Google LLC
+ * Copyright 2022 Coverify Systems Technology
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//-----------------------------------------------------------------------------
+// Processor feature configuration
+//-----------------------------------------------------------------------------
+// XLEN
+
+module riscv.gen.target.rv64imp.riscv_core_setting;
+
+import riscv.gen.riscv_instr_pkg: satp_mode_t, privileged_mode_t,
+  riscv_instr_name_t, mtvec_mode_t, interrupt_cause_t,
+  exception_cause_t, riscv_instr_group_t, privileged_reg_t;
+import esdl: ubvec, flog2;
+
+enum int XLEN = 64;
+
+// Parameter for SATP mode, set to BARE if address translation is not supported
+enum satp_mode_t SATP_MODE = satp_mode_t.BARE;
+
+// Supported Privileged mode
+privileged_mode_t[] supported_privileged_mode = [privileged_mode_t.MACHINE_MODE];
+
+// Unsupported instructions
+riscv_instr_name_t[] unsupported_instr = [];
+
+// ISA supported by the processor
+riscv_instr_group_t[] supported_isa = [riscv_instr_group_t.RV32I,
+				       riscv_instr_group_t.RV32M,
+				       riscv_instr_group_t.RV64I,
+				       riscv_instr_group_t.RV64M,
+				       riscv_instr_group_t.RVZPN,
+				       riscv_instr_group_t.RV64ZPN];
+
+// Interrupt mode support
+mtvec_mode_t[] supported_interrupt_mode = [mtvec_mode_t.DIRECT,
+					   mtvec_mode_t.VECTORED];
+
+// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is
+// supported
+enum int max_interrupt_vector_num = 16;
+
+// Physical memory protection support
+enum bool support_pmp = false;
+
+// Enhanced physical memory protection support
+enum bool support_epmp = false;
+
+// Debug mode support
+enum bool support_debug_mode = false;
+
+// Support delegate trap to user mode
+enum bool support_umode_trap = false;
+
+// Support sfence.vma instruction
+enum bool support_sfence = false;
+
+// Support unaligned load/store
+enum bool support_unaligned_load_store = true;
+
+// GPR setting
+enum int NUM_FLOAT_GPR = 32;
+enum int NUM_GPR = 32;
+enum int NUM_VEC_GPR = 32;
+// ----------------------------------------------------------------------------
+// Vector extension configuration
+// ----------------------------------------------------------------------------
+
+// Parameter for vector extension
+enum int VECTOR_EXTENSION_ENABLE = 0;
+
+enum int VLEN = 512;
+
+// Maximum size of a single vector element
+enum int ELEN = 32;
+
+// Minimum size of a sub-element, which must be at most 8-bits.
+enum int SELEN = 8;
+
+// Maximum size of a single vector element (encoded in vsew format)
+enum int VELEN = flog2(ELEN) - 3;
+
+static assert (VELEN == 2);
+
+// Maxium LMUL supported by the core
+enum int MAX_LMUL = 8;
+
+// ----------------------------------------------------------------------------
+// Multi-harts configuration
+// ----------------------------------------------------------------------------
+
+// Number of harts
+enum int NUM_HARTS = 1;
+
+// ----------------------------------------------------------------------------
+// Previleged CSR implementation
+// ----------------------------------------------------------------------------
+
+// Implemented previlieged CSR list
+enum privileged_reg_t[] implemented_csr = [
+					   // Machine mode mode CSR
+					   privileged_reg_t.MVENDORID,  // Vendor ID
+					   privileged_reg_t.MARCHID,    // Architecture ID
+					   privileged_reg_t.MIMPID,     // Implementation ID
+					   privileged_reg_t.MHARTID,    // Hardware thread ID
+					   privileged_reg_t.MSTATUS,    // Machine status
+					   privileged_reg_t.MISA,       // ISA and extensions
+					   privileged_reg_t.MIE,        // Machine interrupt-enable register
+					   privileged_reg_t.MTVEC,      // Machine trap-handler base address
+					   privileged_reg_t.MCOUNTEREN, // Machine counter enable
+					   privileged_reg_t.MSCRATCH,   // Scratch register for machine trap handlers
+					   privileged_reg_t.MEPC,       // Machine exception program counter
+					   privileged_reg_t.MCAUSE,     // Machine trap cause
+					   privileged_reg_t.MTVAL,      // Machine bad address or instruction
+					   privileged_reg_t.MIP         // Machine interrupt pending
+					   ];
+
+// Implementation-specific custom CSRs
+ubvec!12[] custom_csr = [];
+
+// ----------------------------------------------------------------------------
+// Supported interrupt/exception setting, used for functional coverage
+// ----------------------------------------------------------------------------
+
+enum interrupt_cause_t[] implemented_interrupt = [interrupt_cause_t.M_SOFTWARE_INTR,
+						  interrupt_cause_t.M_TIMER_INTR,
+						  interrupt_cause_t.M_EXTERNAL_INTR];
+
+enum exception_cause_t[] implemented_exception = [exception_cause_t.INSTRUCTION_ACCESS_FAULT,
+						  exception_cause_t.ILLEGAL_INSTRUCTION,
+						  exception_cause_t.BREAKPOINT,
+						  exception_cause_t.LOAD_ADDRESS_MISALIGNED,
+						  exception_cause_t.LOAD_ACCESS_FAULT,
+						  exception_cause_t.ECALL_MMODE];
diff --git a/euvm/riscv/test/riscv_instr_base_test.d b/euvm/riscv/test/riscv_instr_base_test.d
index 7710e402..765d1787 100644
--- a/euvm/riscv/test/riscv_instr_base_test.d
+++ b/euvm/riscv/test/riscv_instr_base_test.d
@@ -63,7 +63,7 @@ class riscv_instr_base_test: uvm_test
     uvm_info(get_full_name(), "Create configuration instance...done", UVM_LOW);
     uvm_info(get_full_name(), cfg.sprint(), UVM_LOW);
     uvm_config_db!(riscv_instr_gen_config).set(null, "*", "instr_cfg", cfg);
-    if(cfg.asm_test_suffix != "")
+    if (cfg.asm_test_suffix != "")
       asm_file_name = asm_file_name ~ "." ~ cfg.asm_test_suffix;
     // Override the default riscv instruction sequence
     if (cmd.plusArgs("instr_seq=%s", instr_seq)) {
@@ -104,7 +104,8 @@ class riscv_instr_base_test: uvm_test
     for (int i = 0; i < cfg.num_of_tests; i++) {
       string test_name;
       randomize_cfg();
-      // registry.create_instr_list(cfg);
+      cfg.instr_registry.create_instr_list(cfg);
+      cfg.csr_cfg.create_csr_filter(cfg);
       asm_gen = riscv_asm_program_gen.type_id.create("asm_gen", null, get_full_name());
       asm_gen.cfg = cfg;
       asm_gen.get_directed_instr_stream();
diff --git a/euvm/riscv/test/riscv_instr_gen.d b/euvm/riscv/test/riscv_instr_gen.d
index a5e60e87..dfcdd0d5 100644
--- a/euvm/riscv/test/riscv_instr_gen.d
+++ b/euvm/riscv/test/riscv_instr_gen.d
@@ -16,6 +16,7 @@
 
 import uvm;
 import esdl;
+// import esdl.rand.meta: printStats;
 
 int main(string[] args) {
   import std.stdio: writeln;
@@ -32,7 +33,7 @@ int main(string[] args) {
 
   if (! cmdl.plusArgs("thread_index=" ~ "%d", thread_index))
     thread_index = 0;
-  if (! cmdl.plusArgs("thread_count=" ~ "%d", thread_count))
+  if (! cmdl.plusArgs("par_num_threads=" ~ "%d", thread_count))
     thread_count = 1;
 
   auto testbench = new uvm_testbench;
@@ -40,7 +41,6 @@ int main(string[] args) {
   testbench.multicore(thread_index, thread_count);
   testbench.elaborate("test", args);
   testbench.set_seed(random_seed);
-  testbench.set_async_mode();
 
   return testbench.start();
 }
diff --git a/euvm/riscv/test/riscv_instr_test.d b/euvm/riscv/test/riscv_instr_test.d
index 656a22f3..de7e1bf4 100644
--- a/euvm/riscv/test/riscv_instr_test.d
+++ b/euvm/riscv/test/riscv_instr_test.d
@@ -39,8 +39,8 @@ class riscv_instr_test: riscv_instr_base_test
     super(name, parent);
   }
 
-  override void build_phase(uvm_phase phase)
-  {  super.build_phase(phase);
+  override void build_phase(uvm_phase phase) {
+    super.build_phase(phase);
     coreservice = uvm_coreservice_t.get();
     factory = coreservice.get_factory();
     uvm_info(get_full_name(), "Create configuration instance", UVM_LOW);
@@ -48,7 +48,7 @@ class riscv_instr_test: riscv_instr_base_test
     uvm_info(get_full_name(), "Create configuration instance...done", UVM_LOW);
     uvm_info(get_full_name(), cfg.sprint(), UVM_LOW);
     uvm_config_db!(riscv_instr_gen_config).set(null, "*", "instr_cfg", cfg);
-    if(cfg.asm_test_suffix != "")
+    if (cfg.asm_test_suffix != "")
       asm_file_name = asm_file_name ~ "." ~ cfg.asm_test_suffix;
     if (support_debug_mode) {
       factory.set_inst_override_by_name("riscv_asm_program_gen",
@@ -56,40 +56,41 @@ class riscv_instr_test: riscv_instr_base_test
                                         get_full_name() ~ ".asm_gen.debug_rom");
     }
   }
-  override void run_phase(uvm_phase phase)
-  {
+  override void run_phase(uvm_phase phase) {
     riscv_instr instr;
     riscv_instr_name_t instr_name;
     string test_name = format("%0s_0.S", asm_file_name);
     auto fd = File(test_name,"w");
     uvm_info(get_full_name(), "Creating instruction list", UVM_LOW);
     cfg.instr_registry.create_instr_list(cfg);
+    cfg.csr_cfg.create_csr_filter(cfg);
     uvm_info(get_full_name(), "Randomizing instruction list now...", UVM_LOW);
 
     //10000.repeat();
-    for(int i = 0; i<100000; i++)
-      {
-	instr = cfg.instr_registry.get_rand_instr();
-	instr.randomize();
-	fd.writeln(instr.convert2asm());
-      }
+    for (int i = 0; i<10000; i++) {
+      instr = cfg.instr_registry.get_rand_instr();
+      instr.randomize();
+      fd.writeln(instr.convert2asm());
+    }
     //repeat (10000);
-    instr = cfg.instr_registry.get_rand_instr([riscv_instr_category_t.LOAD, riscv_instr_category_t.STORE]);
-    instr.randomize();
-    fd.writeln(instr.convert2asm());
-
+    for (int i = 0; i<10000; i++) {
+      instr = cfg.instr_registry.get_rand_instr([riscv_instr_category_t.LOAD, riscv_instr_category_t.STORE]);
+      instr.randomize();
+      fd.writeln(instr.convert2asm());
+    }
     // repeat (10000);
-    instr = cfg.instr_registry.get_rand_instr(([riscv_instr_category_t.LOAD, riscv_instr_category_t.STORE , riscv_instr_category_t.BRANCH]),
-					      ([riscv_instr_group_t.RV32I, riscv_instr_group_t.RV32M]));
-    instr.randomize();
-    fd.writeln(instr.convert2asm());
-
-    uvm_info(get_full_name(), format("%0s is generated", test_name), UVM_LOW);
-
+    for (int i = 0; i<10000; i++) {
+      instr = cfg.instr_registry.get_rand_instr(([riscv_instr_category_t.LOAD, riscv_instr_category_t.STORE,
+						  riscv_instr_category_t.BRANCH]),
+						([riscv_instr_group_t.RV32I, riscv_instr_group_t.RV32M]));
+      instr.randomize();
+      fd.writeln(instr.convert2asm());
+    }
+   
+    uvm_info(get_full_name(), format("%0s is generated", test_name), UVM_LOW); 
   }
 
-  override void randomize_cfg()
-  {
+  override void randomize_cfg() {
     cfg.randomize();
     uvm_info(get_full_name(), format("riscv_instr_gen_config is randomized:\n%0s",
 				     cfg.sprint()), UVM_LOW);
diff --git a/scripts/lib.py b/scripts/lib.py
index 9acf6dcf..872752f0 100644
--- a/scripts/lib.py
+++ b/scripts/lib.py
@@ -109,6 +109,7 @@ def run_cmd(cmd, timeout_s=999, exit_on_error=1, check_return_code=True,
                               executable='/bin/bash',
                               universal_newlines=True,
                               start_new_session=True,
+                              env=os.environ,
                               stdout=subprocess.PIPE,
                               stderr=subprocess.STDOUT)
     except subprocess.CalledProcessError:
diff --git a/yaml/simulator.yaml b/yaml/simulator.yaml
index 01f8b1ac..76dd6f1e 100644
--- a/yaml/simulator.yaml
+++ b/yaml/simulator.yaml
@@ -22,6 +22,7 @@
       - "vcs -file <cwd>/vcs.compile.option.f
               +incdir+<setting>
               +incdir+<user_extension>
+             +vcs+lic+wait
              -f <cwd>/files.f -full64
              -l <out>/compile.log
              -LDFLAGS '-Wl,--no-as-needed'