From 5bef59a8cfafdadf43b75eb59714a9134d9b53ff Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Sat, 25 Nov 2023 16:47:25 +0800 Subject: [PATCH] add vectorUseDCache parameter --- src/main/scala/tile/BaseTile.scala | 2 +- src/main/scala/tile/Core.scala | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 1fb447317b..448050a0d5 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -93,7 +93,7 @@ trait HasNonDiplomaticTileParameters { // TODO make HellaCacheIO diplomatic and remove this brittle collection of hacks // Core PTW DTIM coprocessors - def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + (tileParams.core.useVector && tileParams.core.vectorUseDCache).toInt // TODO merge with isaString in CSR.scala def isaDTS: String = { diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala index 259560f8b1..8c9018da50 100644 --- a/src/main/scala/tile/Core.scala +++ b/src/main/scala/tile/Core.scala @@ -23,6 +23,7 @@ trait CoreParams { val useAtomicsOnlyForIO: Boolean val useCompressed: Boolean val useVector: Boolean = false + val vectorUseDCache: Boolean = false val useRVE: Boolean val useConditionalZero: Boolean val mulDiv: Option[MulDivParams]