From df66c19e873fbc74214082f512a1cbb7a15087e7 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Fri, 24 Nov 2023 01:32:54 +0800 Subject: [PATCH 1/3] remove vMemDataBits check --- src/main/scala/tile/Core.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala index f6981892dca..259560f8b1e 100644 --- a/src/main/scala/tile/Core.scala +++ b/src/main/scala/tile/Core.scala @@ -113,7 +113,6 @@ trait HasCoreParameters extends HasTileParameters { if (usingVector) { require(isPow2(vLen), s"vLen ($vLen) must be a power of 2") require(eLen >= 32 && vLen % eLen == 0, s"eLen must divide vLen ($vLen) and be no less than 32") - require(vMemDataBits >= eLen && vLen % vMemDataBits == 0, s"vMemDataBits ($vMemDataBits) must divide vLen ($vLen) and be no less than eLen ($eLen)") } lazy val hartIdLen: Int = p(MaxHartIdBits) From 74dd9b19d0bc911670f8e7a50178bd946c3200cf Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Fri, 24 Nov 2023 01:41:12 +0800 Subject: [PATCH 2/3] remove vector on dcache port --- src/main/scala/tile/BaseTile.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 4182752d77c..1fb447317b8 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -93,7 +93,7 @@ trait HasNonDiplomaticTileParameters { // TODO make HellaCacheIO diplomatic and remove this brittle collection of hacks // Core PTW DTIM coprocessors - def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + tileParams.core.useVector.toInt + def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size // TODO merge with isaString in CSR.scala def isaDTS: String = { From 5bef59a8cfafdadf43b75eb59714a9134d9b53ff Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Sat, 25 Nov 2023 16:47:25 +0800 Subject: [PATCH 3/3] add vectorUseDCache parameter --- src/main/scala/tile/BaseTile.scala | 2 +- src/main/scala/tile/Core.scala | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 1fb447317b8..448050a0d50 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -93,7 +93,7 @@ trait HasNonDiplomaticTileParameters { // TODO make HellaCacheIO diplomatic and remove this brittle collection of hacks // Core PTW DTIM coprocessors - def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + (tileParams.core.useVector && tileParams.core.vectorUseDCache).toInt // TODO merge with isaString in CSR.scala def isaDTS: String = { diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala index 259560f8b1e..8c9018da50a 100644 --- a/src/main/scala/tile/Core.scala +++ b/src/main/scala/tile/Core.scala @@ -23,6 +23,7 @@ trait CoreParams { val useAtomicsOnlyForIO: Boolean val useCompressed: Boolean val useVector: Boolean = false + val vectorUseDCache: Boolean = false val useRVE: Boolean val useConditionalZero: Boolean val mulDiv: Option[MulDivParams]