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verible-verilog-syntax crashing #2181
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Thanks for the report. [one-liner to reproduce] bazel run -c dbg verilog/tools/syntax:verible-verilog-syntax -- - <<EOF
module m();
id_0var_0 (var_3), var_1, var_2;
endmodule
EOF |
The problem seems to be happening in the rule for instantiation_base
: instantiation_type non_anonymous_gate_instance_or_register_variable_list
{ $$ = MakeInstantiationBase($1, $2); }
| reference call_base ',' gate_instance_or_register_variable_list
{$$ = MakeInstantiationBase(ReinterpretReferenceAsDataTypePackedDimensions($1), ExtendNode($4,$3,$2)); }
| reference_or_call_base
{$$ = MakeTaggedNode(N::kFunctionCall,$1); }
; The second case is matched due to the comma appearing after the call ( Why is this second case of the rule needed at all? I can't think of any situation where it would be needed for valid syntax. When I tried commenting it out, all of Verible's tests have passed and verible-verilog-syntax correctly identified the syntax error in the input given by @joaovam:
|
Just briefly looking at this, I recall that we don't have great support for anonymous instances, and this second grammar case may have been a haklf-baked attempt to support a single declaration that mixes anonymous with named instances (I'm not even sure if this is valid). |
So sounds like this faulty production might be good to comment out with a @rafasumi can you prepare a Pull Request ? Might be worthwhile checking that running |
Sure, I'll work on it! |
The verible-verilog-syntax crashes when trying to analyze the following input:
the crash output is the following:
The expected behavior would be to exit the program, identifying a syntax error near id_0 without crashing.
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