Render CompDecl in VHDL decl function (copy #2819)

[mergify]

Instead of rendering them in inst_. I noticed that while creating a primitive that when I used a combination of compInBlock and instDecl Empty that the entire block declaration and its declarative part were elided; leaving only the portmap.

So before this change, the following primitive declaration:

  = do
    plusFloatInstName <- Id.makeBasic "plusFloat_inst"

    let
      compInps =
        [ ("clk", N.Bit)
        , ("arg1", DSL.ety a)
        , ("arg2", DSL.ety b) ]
      compOuts =
        [ ("dout", DSL.ety result) ]

      plusFloatName = "plusFloat"

    DSL.declaration "plusFloat_inst_block" $ do
      DSL.compInBlock "plusFloat" compInps compOuts

      let
        inps =
          [ ("clk", clk )
          , ("arg1", a)
          , ("arg2", b)
          ]

        outs =
          [ ("dout", result)
          ]

      DSL.instDecl Empty (Id.unsafeMake plusFloatName) plusFloatInstName
        [] inps outs

would get translated to:

    plusFloat_inst : plusFloat
      port map
        ( clk  => clk
        , arg1 => y
        , arg2 => z
        , dout => \c$app_arg\ );

instead of the expected:

  plusFloat_inst_block : block
    component plusFloat port
      ( clk : in std_logic
      ; arg1 : in std_logic_vector(31 downto 0)
      ; arg2 : in std_logic_vector(31 downto 0)
      ; dout : out std_logic_vector(31 downto 0) );
    end component;
  begin
    plusFloat_inst : plusFloat
      port map
        ( clk  => clk
        , arg1 => y
        , arg2 => z
        , dout => \c$app_arg\ );


  end block;

Still TODO:

• Check copyright notices are up to date in edited files

---

This is an automatic copy of pull request #2819 done by [Mergify](https://mergify.com).

[DigitalBrains1]

Should we perhaps add a short Changelog message? (This will need another PR on master with another backport to not confuse us when we release the next version of Clash.)

[christiaanb]

Adding a changelog entry is tracked as: #2838