From 49807bc00adfadd5e40e5cd61cedd1223802e8bf Mon Sep 17 00:00:00 2001 From: Egor Chesakov Date: Tue, 2 Nov 2021 20:47:26 -0700 Subject: [PATCH] Remove dead code in src/coreclr/jit (#61129) --- src/coreclr/jit/codegen.h | 81 ------- src/coreclr/jit/codegenarm.cpp | 6 +- src/coreclr/jit/codegenarmarch.cpp | 2 +- src/coreclr/jit/codegencommon.cpp | 2 - src/coreclr/jit/codegeninterface.h | 1 - src/coreclr/jit/codegenxarch.cpp | 8 +- src/coreclr/jit/emitarm.cpp | 2 +- src/coreclr/jit/instr.cpp | 344 +---------------------------- 8 files changed, 11 insertions(+), 435 deletions(-) diff --git a/src/coreclr/jit/codegen.h b/src/coreclr/jit/codegen.h index 8473b573dc765..c6b789f86f3cb 100644 --- a/src/coreclr/jit/codegen.h +++ b/src/coreclr/jit/codegen.h @@ -1338,8 +1338,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ public: - void instInit(); - void instGen(instruction ins); void inst_JMP(emitJumpKind jmp, BasicBlock* tgtBlock); @@ -1384,10 +1382,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX instruction ins, regNumber reg, target_ssize_t val, emitAttr size, insFlags flags = INS_FLAGS_DONT_CARE); void inst_ST_RV(instruction ins, TempDsc* tmp, unsigned ofs, regNumber reg, var_types type); - void inst_ST_IV(instruction ins, TempDsc* tmp, unsigned ofs, int val, var_types type); - - void inst_SA_RV(instruction ins, unsigned ofs, regNumber reg, var_types type); - void inst_SA_IV(instruction ins, unsigned ofs, int val, var_types type); void inst_FS_ST(instruction ins, emitAttr size, TempDsc* tmp, unsigned ofs); @@ -1402,54 +1396,28 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX emitAttr size = EA_UNKNOWN, insFlags flags = INS_FLAGS_DONT_CARE); - void inst_FS_TT(instruction ins, GenTree* tree); - void inst_RV_SH(instruction ins, emitAttr size, regNumber reg, unsigned val, insFlags flags = INS_FLAGS_DONT_CARE); - void inst_TT_SH(instruction ins, GenTree* tree, unsigned val, unsigned offs = 0); - - void inst_RV_CL(instruction ins, regNumber reg, var_types type = TYP_I_IMPL); - - void inst_TT_CL(instruction ins, GenTree* tree, unsigned offs = 0); - #if defined(TARGET_XARCH) void inst_RV_RV_IV(instruction ins, emitAttr size, regNumber reg1, regNumber reg2, unsigned ival); void inst_RV_TT_IV(instruction ins, emitAttr attr, regNumber reg1, GenTree* rmOp, int ival); void inst_RV_RV_TT(instruction ins, emitAttr size, regNumber targetReg, regNumber op1Reg, GenTree* op2, bool isRMW); #endif - void inst_RV_RR(instruction ins, emitAttr size, regNumber reg1, regNumber reg2); - - void inst_RV_ST(instruction ins, emitAttr size, regNumber reg, GenTree* tree); - - void inst_mov_RV_ST(regNumber reg, GenTree* tree); - void inst_set_SV_var(GenTree* tree); #ifdef TARGET_ARM bool arm_Valid_Imm_For_Instr(instruction ins, target_ssize_t imm, insFlags flags); - bool arm_Valid_Disp_For_LdSt(target_ssize_t disp, var_types type); - bool arm_Valid_Imm_For_Alu(target_ssize_t imm); - bool arm_Valid_Imm_For_Mov(target_ssize_t imm); - bool arm_Valid_Imm_For_Small_Mov(regNumber reg, target_ssize_t imm, insFlags flags); bool arm_Valid_Imm_For_Add(target_ssize_t imm, insFlags flag); bool arm_Valid_Imm_For_Add_SP(target_ssize_t imm); - bool arm_Valid_Imm_For_BL(ssize_t addr); - - bool ins_Writes_Dest(instruction ins); #endif - bool isMoveIns(instruction ins); instruction ins_Move_Extend(var_types srcType, bool srcInReg); instruction ins_Copy(var_types dstType); instruction ins_Copy(regNumber srcReg, var_types dstType); - static instruction ins_FloatStore(var_types type = TYP_DOUBLE); - static instruction ins_FloatCopy(var_types type = TYP_DOUBLE); instruction ins_FloatConv(var_types to, var_types from); - instruction ins_FloatCompare(var_types type); instruction ins_MathOp(genTreeOps oper, var_types type); - instruction ins_FloatSqrt(var_types type); void instGen_Return(unsigned stkArgSize); @@ -1469,16 +1437,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX insFlags flags = INS_FLAGS_DONT_CARE DEBUGARG(size_t targetHandle = 0) DEBUGARG(GenTreeFlags gtFlags = GTF_EMPTY)); - void instGen_Compare_Reg_To_Zero(emitAttr size, regNumber reg); - - void instGen_Compare_Reg_To_Reg(emitAttr size, regNumber reg1, regNumber reg2); - - void instGen_Compare_Reg_To_Imm(emitAttr size, regNumber reg, target_ssize_t imm); - - void instGen_Load_Reg_From_Lcl(var_types srcType, regNumber dstReg, int varNum, int offs); - - void instGen_Store_Reg_Into_Lcl(var_types dstType, regNumber srcReg, int varNum, int offs); - #ifdef TARGET_XARCH instruction genMapShiftInsToShiftByConstantIns(instruction ins, int shiftByValue); #endif // TARGET_XARCH @@ -1528,45 +1486,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX void inst_SETCC(GenCondition condition, var_types type, regNumber dstReg); }; -/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -XX XX -XX Instruction XX -XX Inline functions XX -XX XX -XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -*/ - -#ifdef TARGET_XARCH -/***************************************************************************** - * - * Generate a floating-point instruction that has one operand given by - * a tree (which has been made addressable). - */ - -inline void CodeGen::inst_FS_TT(instruction ins, GenTree* tree) -{ - assert(instIsFP(ins)); - - assert(varTypeIsFloating(tree->gtType)); - - inst_TT(ins, tree, 0); -} -#endif - -/***************************************************************************** - * - * Generate a "shift reg, cl" instruction. - */ - -inline void CodeGen::inst_RV_CL(instruction ins, regNumber reg, var_types type) -{ - inst_RV(ins, reg, type); -} - -/*****************************************************************************/ - // A simple phase that just invokes a method on the codegen instance // class CodeGenPhase final : public Phase diff --git a/src/coreclr/jit/codegenarm.cpp b/src/coreclr/jit/codegenarm.cpp index e206073b739b2..23beb66352978 100644 --- a/src/coreclr/jit/codegenarm.cpp +++ b/src/coreclr/jit/codegenarm.cpp @@ -182,7 +182,7 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr size, { // TODO-CrossBitness: we wouldn't need the cast below if we had CodeGen::instGen_Set_Reg_To_Reloc_Imm. const int val32 = (int)imm; - if (arm_Valid_Imm_For_Mov(val32)) + if (validImmForMov(val32)) { GetEmitter()->emitIns_R_I(INS_mov, size, reg, val32, flags); } @@ -191,7 +191,7 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr size, const int imm_lo16 = val32 & 0xffff; const int imm_hi16 = (val32 >> 16) & 0xffff; - assert(arm_Valid_Imm_For_Mov(imm_lo16)); + assert(validImmForMov(imm_lo16)); assert(imm_hi16 != 0); GetEmitter()->emitIns_R_I(INS_movw, size, reg, imm_lo16); @@ -1606,7 +1606,7 @@ void CodeGen::genEmitHelperCall(unsigned helper, int argSize, emitAttr retSize, addr = compiler->compGetHelperFtn((CorInfoHelpFunc)helper, (void**)&pAddr); } - if (!addr || !arm_Valid_Imm_For_BL((ssize_t)addr)) + if (!addr || !validImmForBL((ssize_t)addr)) { if (callTargetReg == REG_NA) { diff --git a/src/coreclr/jit/codegenarmarch.cpp b/src/coreclr/jit/codegenarmarch.cpp index 01b28767db5dd..469a145f12dbc 100644 --- a/src/coreclr/jit/codegenarmarch.cpp +++ b/src/coreclr/jit/codegenarmarch.cpp @@ -2582,7 +2582,7 @@ void CodeGen::genCallInstruction(GenTreeCall* call) // Non-virtual direct call to known addresses #ifdef TARGET_ARM - if (!arm_Valid_Imm_For_BL((ssize_t)addr)) + if (!validImmForBL((ssize_t)addr)) { regNumber tmpReg = call->GetSingleTempReg(); instGen_Set_Reg_To_Imm(EA_HANDLE_CNS_RELOC, tmpReg, (ssize_t)addr); diff --git a/src/coreclr/jit/codegencommon.cpp b/src/coreclr/jit/codegencommon.cpp index ba11b8e485e17..8c788286f292d 100644 --- a/src/coreclr/jit/codegencommon.cpp +++ b/src/coreclr/jit/codegencommon.cpp @@ -100,8 +100,6 @@ CodeGen::CodeGen(Compiler* theCompiler) : CodeGenInterface(theCompiler) regSet.tmpInit(); - instInit(); - #ifdef LATE_DISASM getDisAssembler().disInit(compiler); #endif diff --git a/src/coreclr/jit/codegeninterface.h b/src/coreclr/jit/codegeninterface.h index 82519973d1ea8..f276a492da33d 100644 --- a/src/coreclr/jit/codegeninterface.h +++ b/src/coreclr/jit/codegeninterface.h @@ -310,7 +310,6 @@ class CodeGenInterface instruction ins_Load(var_types srcType, bool aligned = false); instruction ins_Store(var_types dstType, bool aligned = false); instruction ins_StoreFromSrc(regNumber srcReg, var_types dstType, bool aligned = false); - static instruction ins_FloatLoad(var_types type = TYP_DOUBLE); // Methods for spilling - used by RegSet void spillReg(var_types type, TempDsc* tmp, regNumber reg); diff --git a/src/coreclr/jit/codegenxarch.cpp b/src/coreclr/jit/codegenxarch.cpp index 61a6042885a6a..128de7c9fcd5b 100644 --- a/src/coreclr/jit/codegenxarch.cpp +++ b/src/coreclr/jit/codegenxarch.cpp @@ -4260,7 +4260,7 @@ void CodeGen::genCodeForShift(GenTree* tree) noway_assert(operandReg != REG_RCX); inst_Mov(targetType, tree->GetRegNum(), operandReg, /* canSkip */ true); - inst_RV_CL(ins, tree->GetRegNum(), targetType); + inst_RV(ins, tree->GetRegNum(), targetType); } genProduceReg(tree); @@ -6083,7 +6083,7 @@ void CodeGen::genCompareFloat(GenTree* treeNode) std::swap(op1, op2); } - ins = ins_FloatCompare(op1Type); + ins = (op1Type == TYP_FLOAT) ? INS_ucomiss : INS_ucomisd; cmpAttr = emitTypeSize(op1Type); GetEmitter()->emitInsBinary(ins, cmpAttr, op1, op2); @@ -7201,7 +7201,9 @@ void CodeGen::genIntrinsic(GenTree* treeNode) assert(srcNode->TypeGet() == treeNode->TypeGet()); genConsumeOperands(treeNode->AsOp()); - GetEmitter()->emitInsBinary(ins_FloatSqrt(treeNode->TypeGet()), emitTypeSize(treeNode), treeNode, srcNode); + + const instruction ins = (treeNode->TypeGet() == TYP_FLOAT) ? INS_sqrtss : INS_sqrtsd; + GetEmitter()->emitInsBinary(ins, emitTypeSize(treeNode), treeNode, srcNode); break; } diff --git a/src/coreclr/jit/emitarm.cpp b/src/coreclr/jit/emitarm.cpp index 30c6f7e219ae9..7ed8421074192 100644 --- a/src/coreclr/jit/emitarm.cpp +++ b/src/coreclr/jit/emitarm.cpp @@ -4801,7 +4801,7 @@ void emitter::emitIns_Call(EmitCallType callType, assert(callType == EC_FUNC_TOKEN); // if addr is nullptr then this call is treated as a recursive call. - assert(addr == nullptr || codeGen->arm_Valid_Imm_For_BL((ssize_t)addr)); + assert(addr == nullptr || codeGen->validImmForBL((ssize_t)addr)); if (isJump) { diff --git a/src/coreclr/jit/instr.cpp b/src/coreclr/jit/instr.cpp index 39f885d925fdf..06ee07c405b6b 100644 --- a/src/coreclr/jit/instr.cpp +++ b/src/coreclr/jit/instr.cpp @@ -145,11 +145,6 @@ const char* CodeGen::genInsDisplayName(emitter::instrDesc* id) /*****************************************************************************/ #endif // DEBUG -/*****************************************************************************/ - -void CodeGen::instInit() -{ -} /***************************************************************************** * @@ -993,46 +988,6 @@ void CodeGen::inst_RV_SH( #endif // TARGET* } -/***************************************************************************** - * - * Generate a "shift [r/m], icon" instruction. - */ - -void CodeGen::inst_TT_SH(instruction ins, GenTree* tree, unsigned val, unsigned offs) -{ -#ifdef TARGET_XARCH - if (val == 0) - { - // Shift by 0 - why are you wasting our precious time???? - return; - } - - ins = genMapShiftInsToShiftByConstantIns(ins, val); - if (val == 1) - { - inst_TT(ins, tree, offs, 0, emitTypeSize(tree->TypeGet())); - } - else - { - inst_TT(ins, tree, offs, val, emitTypeSize(tree->TypeGet())); - } -#endif // TARGET_XARCH - -#ifdef TARGET_ARM - inst_TT(ins, tree, offs, val, emitTypeSize(tree->TypeGet())); -#endif -} - -/***************************************************************************** - * - * Generate a "shift [addr], cl" instruction. - */ - -void CodeGen::inst_TT_CL(instruction ins, GenTree* tree, unsigned offs) -{ - inst_TT(ins, tree, offs, 0, emitTypeSize(tree->TypeGet())); -} - /***************************************************************************** * * Generate an instruction of the form "op reg1, reg2, icon". @@ -1329,23 +1284,6 @@ void CodeGen::inst_RV_RV_TT( } #endif // TARGET_XARCH -/***************************************************************************** - * - * Generate an instruction with two registers, the second one being a byte - * or word register (i.e. this is something like "movzx eax, cl"). - */ - -void CodeGen::inst_RV_RR(instruction ins, emitAttr size, regNumber reg1, regNumber reg2) -{ - assert(size == EA_1BYTE || size == EA_2BYTE); -#ifdef TARGET_XARCH - assert(ins == INS_movsx || ins == INS_movzx); - assert(size != EA_1BYTE || (genRegMask(reg2) & RBM_BYTE_REGS)); -#endif - - GetEmitter()->emitIns_R_R(ins, size, reg1, reg2); -} - /***************************************************************************** * * The following should all end up inline in compiler.hpp at some point. @@ -1356,66 +1294,6 @@ void CodeGen::inst_ST_RV(instruction ins, TempDsc* tmp, unsigned ofs, regNumber GetEmitter()->emitIns_S_R(ins, emitActualTypeSize(type), reg, tmp->tdTempNum(), ofs); } -void CodeGen::inst_ST_IV(instruction ins, TempDsc* tmp, unsigned ofs, int val, var_types type) -{ - GetEmitter()->emitIns_S_I(ins, emitActualTypeSize(type), tmp->tdTempNum(), ofs, val); -} - -#if FEATURE_FIXED_OUT_ARGS -/***************************************************************************** - * - * Generate an instruction that references the outgoing argument space - * like "str r3, [sp+0x04]" - */ - -void CodeGen::inst_SA_RV(instruction ins, unsigned ofs, regNumber reg, var_types type) -{ - assert(ofs < compiler->lvaOutgoingArgSpaceSize); - - GetEmitter()->emitIns_S_R(ins, emitActualTypeSize(type), reg, compiler->lvaOutgoingArgSpaceVar, ofs); -} - -void CodeGen::inst_SA_IV(instruction ins, unsigned ofs, int val, var_types type) -{ - assert(ofs < compiler->lvaOutgoingArgSpaceSize); - - GetEmitter()->emitIns_S_I(ins, emitActualTypeSize(type), compiler->lvaOutgoingArgSpaceVar, ofs, val); -} -#endif // FEATURE_FIXED_OUT_ARGS - -/***************************************************************************** - * - * Generate an instruction with one register and one operand that is byte - * or short (e.g. something like "movzx eax, byte ptr [edx]"). - */ - -void CodeGen::inst_RV_ST(instruction ins, emitAttr size, regNumber reg, GenTree* tree) -{ - assert(size == EA_1BYTE || size == EA_2BYTE); - - inst_RV_TT(ins, reg, tree, 0, size); -} - -void CodeGen::inst_mov_RV_ST(regNumber reg, GenTree* tree) -{ - /* Figure out the size of the value being loaded */ - - emitAttr size = EA_ATTR(genTypeSize(tree->gtType)); - instruction loadIns = ins_Move_Extend(tree->TypeGet(), false); - - if (size < EA_4BYTE) - { - /* Generate the "movsx/movzx" opcode */ - - inst_RV_ST(loadIns, size, reg, tree); - } - else - { - /* Compute op1 into the target register */ - - inst_RV_TT(loadIns, reg, tree); - } -} #ifdef TARGET_XARCH void CodeGen::inst_FS_ST(instruction ins, emitAttr size, TempDsc* tmp, unsigned ofs) { @@ -1517,38 +1395,22 @@ bool CodeGenInterface::validDispForLdSt(target_ssize_t disp, var_types type) return false; } } -bool CodeGen::arm_Valid_Disp_For_LdSt(target_ssize_t disp, var_types type) -{ - return validDispForLdSt(disp, type); -} bool CodeGenInterface::validImmForAlu(target_ssize_t imm) { return emitter::emitIns_valid_imm_for_alu(imm); } -bool CodeGen::arm_Valid_Imm_For_Alu(target_ssize_t imm) -{ - return validImmForAlu(imm); -} bool CodeGenInterface::validImmForMov(target_ssize_t imm) { return emitter::emitIns_valid_imm_for_mov(imm); } -bool CodeGen::arm_Valid_Imm_For_Mov(target_ssize_t imm) -{ - return validImmForMov(imm); -} - -bool CodeGen::arm_Valid_Imm_For_Small_Mov(regNumber reg, target_ssize_t imm, insFlags flags) -{ - return emitter::emitIns_valid_imm_for_small_mov(reg, imm, flags); -} bool CodeGenInterface::validImmForAdd(target_ssize_t imm, insFlags flags) { return emitter::emitIns_valid_imm_for_add(imm, flags); } + bool CodeGen::arm_Valid_Imm_For_Add(target_ssize_t imm, insFlags flags) { return emitter::emitIns_valid_imm_for_add(imm, flags); @@ -1568,28 +1430,7 @@ bool CodeGenInterface::validImmForBL(ssize_t addr) (!compiler->info.compMatchedVM && compiler->opts.jitFlags->IsSet(JitFlags::JIT_FLAG_PREJIT)) || (compiler->eeGetRelocTypeHint((void*)addr) == IMAGE_REL_BASED_THUMB_BRANCH24); } -bool CodeGen::arm_Valid_Imm_For_BL(ssize_t addr) -{ - return validImmForBL(addr); -} - -// Returns true if this instruction writes to a destination register -// -bool CodeGen::ins_Writes_Dest(instruction ins) -{ - switch (ins) - { - case INS_cmp: - case INS_cmn: - case INS_tst: - case INS_teq: - return false; - - default: - return true; - } -} #endif // TARGET_ARM #if defined(TARGET_ARM64) @@ -2093,35 +1934,6 @@ instruction CodeGenInterface::ins_StoreFromSrc(regNumber srcReg, var_types dstTy #if defined(TARGET_XARCH) -bool CodeGen::isMoveIns(instruction ins) -{ - return (ins == INS_mov); -} - -instruction CodeGenInterface::ins_FloatLoad(var_types type) -{ - // Do Not use this routine in RyuJIT backend. Instead use ins_Load()/ins_Store() - unreached(); -} - -// everything is just an addressing mode variation on x64 -instruction CodeGen::ins_FloatStore(var_types type) -{ - // Do Not use this routine in RyuJIT backend. Instead use ins_Store() - unreached(); -} - -instruction CodeGen::ins_FloatCopy(var_types type) -{ - // Do Not use this routine in RyuJIT backend. Instead use ins_Load(). - unreached(); -} - -instruction CodeGen::ins_FloatCompare(var_types type) -{ - return (type == TYP_FLOAT) ? INS_ucomiss : INS_ucomisd; -} - instruction CodeGen::ins_MathOp(genTreeOps oper, var_types type) { switch (oper) @@ -2139,27 +1951,6 @@ instruction CodeGen::ins_MathOp(genTreeOps oper, var_types type) } } -instruction CodeGen::ins_FloatSqrt(var_types type) -{ - instruction ins = INS_invalid; - - if (type == TYP_DOUBLE) - { - ins = INS_sqrtsd; - } - else if (type == TYP_FLOAT) - { - ins = INS_sqrtss; - } - else - { - assert(!"ins_FloatSqrt: Unsupported type"); - unreached(); - } - - return ins; -} - // Conversions to or from floating point values instruction CodeGen::ins_FloatConv(var_types to, var_types from) { @@ -2220,39 +2011,6 @@ instruction CodeGen::ins_FloatConv(var_types to, var_types from) #elif defined(TARGET_ARM) -bool CodeGen::isMoveIns(instruction ins) -{ - return (ins == INS_vmov) || (ins == INS_mov); -} - -instruction CodeGenInterface::ins_FloatLoad(var_types type) -{ - assert(type == TYP_DOUBLE || type == TYP_FLOAT); - return INS_vldr; -} -instruction CodeGen::ins_FloatStore(var_types type) -{ - assert(type == TYP_DOUBLE || type == TYP_FLOAT); - return INS_vstr; -} -instruction CodeGen::ins_FloatCopy(var_types type) -{ - assert(type == TYP_DOUBLE || type == TYP_FLOAT); - return INS_vmov; -} - -instruction CodeGen::ins_FloatCompare(var_types type) -{ - // Not used and not implemented - unreached(); -} - -instruction CodeGen::ins_FloatSqrt(var_types type) -{ - // Not used and not implemented - unreached(); -} - instruction CodeGen::ins_MathOp(genTreeOps oper, var_types type) { switch (oper) @@ -2402,106 +2160,6 @@ void CodeGen::instGen_Set_Reg_To_Zero(emitAttr size, regNumber reg, insFlags fla regSet.verifyRegUsed(reg); } -/***************************************************************************** - * - * Machine independent way to set the flags based on - * comparing a register with zero - */ -void CodeGen::instGen_Compare_Reg_To_Zero(emitAttr size, regNumber reg) -{ -#if defined(TARGET_XARCH) - GetEmitter()->emitIns_R_R(INS_test, size, reg, reg); -#elif defined(TARGET_ARMARCH) - GetEmitter()->emitIns_R_I(INS_cmp, size, reg, 0); -#else -#error "Unknown TARGET" -#endif -} - -/***************************************************************************** - * - * Machine independent way to set the flags based upon - * comparing a register with another register - */ -void CodeGen::instGen_Compare_Reg_To_Reg(emitAttr size, regNumber reg1, regNumber reg2) -{ -#if defined(TARGET_XARCH) || defined(TARGET_ARMARCH) - GetEmitter()->emitIns_R_R(INS_cmp, size, reg1, reg2); -#else -#error "Unknown TARGET" -#endif -} - -/***************************************************************************** - * - * Machine independent way to set the flags based upon - * comparing a register with an immediate - */ -void CodeGen::instGen_Compare_Reg_To_Imm(emitAttr size, regNumber reg, target_ssize_t imm) -{ - if (imm == 0) - { - instGen_Compare_Reg_To_Zero(size, reg); - } - else - { -#if defined(TARGET_XARCH) -#if defined(TARGET_AMD64) - if ((EA_SIZE(size) == EA_8BYTE) && (((int)imm != (ssize_t)imm) || EA_IS_CNS_RELOC(size))) - { - assert(!"Invalid immediate for instGen_Compare_Reg_To_Imm"); - } - else -#endif // TARGET_AMD64 - { - GetEmitter()->emitIns_R_I(INS_cmp, size, reg, imm); - } -#elif defined(TARGET_ARM) - if (arm_Valid_Imm_For_Alu(imm) || arm_Valid_Imm_For_Alu(-imm)) - { - GetEmitter()->emitIns_R_I(INS_cmp, size, reg, imm); - } - else // We need a scratch register - { - assert(!"Invalid immediate for instGen_Compare_Reg_To_Imm"); - } -#elif defined(TARGET_ARM64) - if (true) // TODO-ARM64-NYI: arm_Valid_Imm_For_Alu(imm) || arm_Valid_Imm_For_Alu(-imm)) - { - GetEmitter()->emitIns_R_I(INS_cmp, size, reg, imm); - } - else // We need a scratch register - { - assert(!"Invalid immediate for instGen_Compare_Reg_To_Imm"); - } -#else -#error "Unknown TARGET" -#endif - } -} - -/***************************************************************************** - * - * Machine independent way to move a stack based local variable into a register - */ -void CodeGen::instGen_Load_Reg_From_Lcl(var_types srcType, regNumber dstReg, int varNum, int offs) -{ - emitAttr size = emitTypeSize(srcType); - - GetEmitter()->emitIns_R_S(ins_Load(srcType), size, dstReg, varNum, offs); -} - -/***************************************************************************** - * - * Machine independent way to move a register into a stack based local variable - */ -void CodeGen::instGen_Store_Reg_Into_Lcl(var_types dstType, regNumber srcReg, int varNum, int offs) -{ - emitAttr size = emitTypeSize(dstType); - - GetEmitter()->emitIns_S_R(ins_Store(dstType), size, srcReg, varNum, offs); -} - /*****************************************************************************/ /*****************************************************************************/ /*****************************************************************************/