From 833aaba5f38a66756e721914e889db32bfacec48 Mon Sep 17 00:00:00 2001 From: Egor Chesakov Date: Tue, 4 Aug 2020 14:55:26 -0700 Subject: [PATCH] Set tgtPrefOp1 for intrinsics with SIMD-to-SIMD move semantics in lsraarm64.cpp --- src/coreclr/src/jit/lsraarm64.cpp | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/src/coreclr/src/jit/lsraarm64.cpp b/src/coreclr/src/jit/lsraarm64.cpp index bdb626d7d98d4..2138b782c53e4 100644 --- a/src/coreclr/src/jit/lsraarm64.cpp +++ b/src/coreclr/src/jit/lsraarm64.cpp @@ -1050,9 +1050,24 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree) if (intrin.op1 != nullptr) { - // If we have an RMW intrinsic, we want to preference op1Reg to the target if - // op1 is not contained. - if (isRMW) + bool simdRegToSimdRegMove = false; + + if ((intrin.id == NI_Vector64_CreateScalarUnsafe) || (intrin.id == NI_Vector128_CreateScalarUnsafe)) + { + simdRegToSimdRegMove = varTypeIsFloating(intrin.op1); + } + else if (intrin.id == NI_AdvSimd_Arm64_DuplicateToVector64) + { + simdRegToSimdRegMove = (intrin.op1->TypeGet() == TYP_DOUBLE); + } + else if ((intrin.id == NI_Vector64_ToScalar) || (intrin.id == NI_Vector128_ToScalar)) + { + simdRegToSimdRegMove = varTypeIsFloating(intrinsicTree); + } + + // If we have an RMW intrinsic or an intrinsic with simple move semantic between two SIMD registers, + // we want to preference op1Reg to the target if op1 is not contained. + if (isRMW || simdRegToSimdRegMove) { tgtPrefOp1 = !intrin.op1->isContained(); }