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Assertion failed 'genIsValidDoubleReg(regRec->regNum)' #53322

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BruceForstall opened this issue May 26, 2021 · 3 comments · Fixed by #53412
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Assertion failed 'genIsValidDoubleReg(regRec->regNum)' #53322

BruceForstall opened this issue May 26, 2021 · 3 comments · Fixed by #53412
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arch-arm32 area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI blocking-outerloop Blocking the 'runtime-coreclr outerloop' and 'runtime-libraries-coreclr outerloop' runs os-linux Linux OS (any supported distro)
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@BruceForstall
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Test: JIT/SIMD/VectorConvert_ro_Target_32Bit/VectorConvert_ro_Target_32Bit.sh

Linux/arm
JitStress2 + JitStressRegs1/JitStressRegs8

Assert failure(PID 928 [0x000003a0], Thread: 928 [0x03a0]): Assertion failed 'genIsValidDoubleReg(regRec->regNum)' in 'VectorConvertTest:VectorConvertDoubleSingle(System.Numerics.Vector1[Double],System.Numerics.Vector1[Double]):int' during 'LSRA build intervals' (IL size 477)

File: /__w/1/s/src/coreclr/jit/lsra.cpp Line: 3827
Image: /root/helix/work/correlation/corerun
/root/helix/work/workitem/JIT/SIMD/VectorConvert_ro_Target_32Bit/VectorConvert_ro_Target_32Bit.sh: line 379:   928 Aborted                 (core dumped) $LAUNCHER $ExePath "${CLRTestExecutionArguments[@]}"

Return code:      1
Raw output file:      /root/helix/work/workitem/JIT/SIMD/Reports/JIT.SIMD/VectorConvert_ro_Target_32Bit/VectorConvert_ro_Target_32Bit.output.txt
Raw output:
BEGIN EXECUTION
/root/helix/work/correlation/corerun VectorConvert_ro_Target_32Bit.dll ''
Gathering state for process 928 corerun
Writing minidump with heap to file /home/helixbot/dotnetbuild/dumps/coredump.928.dmp
Written 51810304 bytes (12649 pages) to core file
Dump successfully written
Expected: 100
Actual: 134
END EXECUTION - FAILED
Test Harness Exitcode is : 1
To run the test:

set CORE_ROOT=/root/helix/work/correlation
/root/helix/work/workitem/JIT/SIMD/VectorConvert_ro_Target_32Bit/VectorConvert_ro_Target_32Bit.sh
Expected: True
Actual:   False

fwiw, the failure occurred after this LSRA change: #52832

@kunalspathak PTAL
cc @dotnet/jit-contrib

@BruceForstall BruceForstall added arch-arm32 os-linux Linux OS (any supported distro) area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI blocking-outerloop Blocking the 'runtime-coreclr outerloop' and 'runtime-libraries-coreclr outerloop' runs labels May 26, 2021
@BruceForstall BruceForstall added this to the 6.0.0 milestone May 26, 2021
@dotnet-issue-labeler dotnet-issue-labeler bot added the untriaged New issue has not been triaged by the area owner label May 26, 2021
@BruceForstall BruceForstall removed the untriaged New issue has not been triaged by the area owner label May 26, 2021
@VincentBu
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Failed again in runtime-coreclr crossgen2 20210525.1

Failed test:

CoreCLR Linux arm Checked jitstress2_jitstressregs8 @ (Ubuntu.1804.Arm32.Open)[email protected]/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440

- JIT/SIMD/VectorConvert_ro_Target_32Bit/VectorConvert_ro_Target_32Bit.sh

Error message:

Assert failure(PID 928 [0x000003a0], Thread: 928 [0x03a0]): Assertion failed 'genIsValidDoubleReg(regRec->regNum)' in 'VectorConvertTest:VectorConvertDoubleSingle(System.Numerics.Vector1[Double],System.Numerics.Vector1[Double]):int' during 'LSRA build intervals' (IL size 477)

File: /__w/1/s/src/coreclr/jit/lsra.cpp Line: 3827
Image: /root/helix/work/correlation/corerun
/root/helix/work/workitem/JIT/SIMD/VectorConvert_ro_Target_32Bit/VectorConvert_ro_Target_32Bit.sh: line 379:   928 Aborted                 (core dumped) $LAUNCHER $ExePath "${CLRTestExecutionArguments[@]}"

Return code:      1
Raw output file:      /root/helix/work/workitem/JIT/SIMD/Reports/JIT.SIMD/VectorConvert_ro_Target_32Bit/VectorConvert_ro_Target_32Bit.output.txt
Raw output:
BEGIN EXECUTION
/root/helix/work/correlation/corerun VectorConvert_ro_Target_32Bit.dll ''
Gathering state for process 928 corerun
Writing minidump with heap to file /home/helixbot/dotnetbuild/dumps/coredump.928.dmp
Written 51810304 bytes (12649 pages) to core file
Dump successfully written
Expected: 100
Actual: 134
END EXECUTION - FAILED
Test Harness Exitcode is : 1
To run the test:

set CORE_ROOT=/root/helix/work/correlation
/root/helix/work/workitem/JIT/SIMD/VectorConvert_ro_Target_32Bit/VectorConvert_ro_Target_32Bit.sh
Expected: True
Actual:   False


Stack trace
   at JIT_SIMD._VectorConvert_ro_Target_32Bit_VectorConvert_ro_Target_32Bit_._VectorConvert_ro_Target_32Bit_VectorConvert_ro_Target_32Bit_sh()

@VincentBu
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Historical failures of this test:

Queued OS Arch Pipeline
2021-05-23T19:06:29.367Z ubuntu.1804.armarch.open arm runtime-coreclr jitstress2-jitstressregs Checked-jitstress2_jitstressregs8
2021-05-23T18:56:04.817Z ubuntu.1804.armarch.open arm runtime-coreclr jitstress2-jitstressregs Checked-jitstress2_jitstressregs1
2021-05-22T18:54:55.641Z ubuntu.1804.armarch.open arm runtime-coreclr jitstress2-jitstressregs Checked-jitstress2_jitstressregs8
2021-05-22T18:44:21.444Z ubuntu.1804.armarch.open arm runtime-coreclr jitstress2-jitstressregs Checked-jitstress2_jitstressregs1

@sandreenko
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@VincentBu it is great to see the history, was it hard to fetch?

@ghost ghost added the in-pr There is an active PR which will close this issue when it is merged label May 28, 2021
@ghost ghost removed the in-pr There is an active PR which will close this issue when it is merged label May 28, 2021
@ghost ghost locked as resolved and limited conversation to collaborators Jun 27, 2021
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arch-arm32 area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI blocking-outerloop Blocking the 'runtime-coreclr outerloop' and 'runtime-libraries-coreclr outerloop' runs os-linux Linux OS (any supported distro)
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