Arm64: Consider using "DC ZVA" instruction

[kunalspathak]

We should consider using DC ZVA instruction in the runtime so it can be directly used by GC or other places where memset is needed. “DC ZVA” seems effective and takes memory system into write streaming mode which avoids doing a linefill the L1 cache during scenarios like memset. Last year, we merged the work to use “DC ZVA” for zero init the frame. I was hoping to see the memset implementation to be similar to the one suggested in Arm64 optimizing guide.

Some other refence: ARM-software/tf-issues#408

category:implementation
theme:intrinsics
skill-level:expert
cost:medium
impact:small

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[kunalspathak]

@a74nh

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Issue Details

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We should consider using DC ZVA instruction in the runtime so it can be directly used by GC or other places where memset is needed. “DC ZVA” seems effective and takes memory system into write streaming mode which avoids doing a linefill the L1 cache during scenarios like memset. Last year, we merged the work to use “DC ZVA” for zero init the frame. I was hoping to see the memset implementation to be similar to the one suggested in Arm64 optimizing guide.

Some other refence: ARM-software/tf-issues#408

Author:	kunalspathak
Assignees:	-
Labels:	area-CodeGen-coreclr, untriaged
Milestone:	-

[kunalspathak]

Moving to future.

[kunalspathak]

Note that in JIT, we already use this instruction for zero init the frame.

runtime/src/coreclr/jit/codegenarm64.cpp

Line 2034 in 3fded0b

GetEmitter()->emitIns_R(INS_dczva, EA_PTRSIZE, addrReg);

[a74nh]

Looking back through the various discussions and related pull requests, ZVA is already used in a number of places and in elsewhere it was dropped due to lack of performance impact.

AIUI, this issue is only concerned with where coreclr today calls out to memset().

On Linux, memset should already be fairly optimal. See https://github.com/bminor/glibc/blob/master/sysdeps/aarch64/memset.S
If the the size is big enough, and setting to 0, and zva exists on the hardware (via checking system register using mrs), then it uses zva.
A quick check on Ubuntu 22.04.2 confirmed it ended up using zva.

I'm not sure what happens on Windows. If it doesn't use zva and there are no plans for it to do so, then maybe it makes sense too add an implementation inside coreclr.