From eeac76831e3526fa63fb74ecdc0f4c3c9ebcc888 Mon Sep 17 00:00:00 2001 From: EgorBo Date: Wed, 6 Oct 2021 22:11:37 +0300 Subject: [PATCH 1/5] enable for arm64 --- src/coreclr/jit/codegencommon.cpp | 12 ++++++------ src/coreclr/jit/gentree.cpp | 25 ++----------------------- 2 files changed, 8 insertions(+), 29 deletions(-) diff --git a/src/coreclr/jit/codegencommon.cpp b/src/coreclr/jit/codegencommon.cpp index 15fac8b26ae0f..3773ac1245267 100644 --- a/src/coreclr/jit/codegencommon.cpp +++ b/src/coreclr/jit/codegencommon.cpp @@ -1441,7 +1441,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr, cns += op2->AsIntConCommon()->IconValue(); -#if defined(TARGET_ARMARCH) +#if defined(TARGET_ARM) if (cns == 0) #endif { @@ -1461,7 +1461,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr, goto AGAIN; -#if SCALED_ADDR_MODES && !defined(TARGET_ARMARCH) +#if SCALED_ADDR_MODES && !defined(TARGET_ARM) // TODO-ARM64-CQ, TODO-ARM-CQ: For now we don't try to create a scaled index. case GT_MUL: if (op1->gtOverflow()) @@ -1505,7 +1505,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr, switch (op1->gtOper) { -#if !defined(TARGET_ARMARCH) +#if !defined(TARGET_ARM) // TODO-ARM64-CQ, TODO-ARM-CQ: For now we don't try to create a scaled index. case GT_ADD: @@ -1568,7 +1568,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr, break; #endif // SCALED_ADDR_MODES -#endif // !TARGET_ARMARCH +#endif // !TARGET_ARM case GT_NOP: @@ -1587,7 +1587,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr, noway_assert(op2); switch (op2->gtOper) { -#if !defined(TARGET_ARMARCH) +#if !defined(TARGET_ARM) // TODO-ARM64-CQ, TODO-ARM-CQ: For now we don't try to create a scaled index. case GT_ADD: @@ -1646,7 +1646,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr, break; #endif // SCALED_ADDR_MODES -#endif // !TARGET_ARMARCH +#endif // !TARGET_ARM case GT_NOP: diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp index 36d530e526456..0c3ea101763f4 100644 --- a/src/coreclr/jit/gentree.cpp +++ b/src/coreclr/jit/gentree.cpp @@ -3030,7 +3030,7 @@ bool Compiler::gtMarkAddrMode(GenTree* addr, int* pCostEx, int* pCostSz, var_typ // nodes with GTF_ADDRMODE_NO_CSE and calculate a more accurate cost. addr->gtFlags |= GTF_ADDRMODE_NO_CSE; -#ifdef TARGET_XARCH +#if defined(TARGET_XARCH) || defined(TARGET_ARM64) // addrmodeCount is the count of items that we used to form // an addressing mode. The maximum value is 4 when we have // all of these: { base, idx, cns, mul } @@ -3161,27 +3161,6 @@ bool Compiler::gtMarkAddrMode(GenTree* addr, int* pCostEx, int* pCostSz, var_typ } } } -#elif defined TARGET_ARM64 - if (base) - { - *pCostEx += base->GetCostEx(); - *pCostSz += base->GetCostSz(); - } - - if (idx) - { - *pCostEx += idx->GetCostEx(); - *pCostSz += idx->GetCostSz(); - } - - if (cns != 0) - { - if (cns >= (4096 * genTypeSize(type))) - { - *pCostEx += 1; - *pCostSz += 4; - } - } #else #error "Unknown TARGET" #endif @@ -3224,7 +3203,7 @@ bool Compiler::gtMarkAddrMode(GenTree* addr, int* pCostEx, int* pCostSz, var_typ // we have already found either a non-ADD op1 or a non-constant op2. gtWalkOp(&op1, &op2, nullptr, true); -#if defined(TARGET_XARCH) +#if defined(TARGET_XARCH) || defined(TARGET_ARM) // For XARCH we will fold GT_ADDs in the op2 position into the addressing mode, so we call // gtWalkOp on both operands of the original GT_ADD. // This is not done for ARMARCH. Though the stated reason is that we don't try to create a From 4264e34ea133bc35fda563355d7c161ce9ae78ce Mon Sep 17 00:00:00 2001 From: EgorBo Date: Wed, 6 Oct 2021 22:40:28 +0300 Subject: [PATCH 2/5] fix small issue --- src/coreclr/jit/gentree.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp index 0c3ea101763f4..1ef2cd4efc5f4 100644 --- a/src/coreclr/jit/gentree.cpp +++ b/src/coreclr/jit/gentree.cpp @@ -3203,7 +3203,7 @@ bool Compiler::gtMarkAddrMode(GenTree* addr, int* pCostEx, int* pCostSz, var_typ // we have already found either a non-ADD op1 or a non-constant op2. gtWalkOp(&op1, &op2, nullptr, true); -#if defined(TARGET_XARCH) || defined(TARGET_ARM) +#if defined(TARGET_XARCH) || defined(TARGET_ARM64) // For XARCH we will fold GT_ADDs in the op2 position into the addressing mode, so we call // gtWalkOp on both operands of the original GT_ADD. // This is not done for ARMARCH. Though the stated reason is that we don't try to create a From f144181a6fe55df9d69286655506dfd69474c281 Mon Sep 17 00:00:00 2001 From: Egor Bogatov Date: Wed, 6 Oct 2021 23:26:57 +0300 Subject: [PATCH 3/5] Update codegencommon.cpp --- src/coreclr/jit/codegencommon.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/coreclr/jit/codegencommon.cpp b/src/coreclr/jit/codegencommon.cpp index 3773ac1245267..980125617abeb 100644 --- a/src/coreclr/jit/codegencommon.cpp +++ b/src/coreclr/jit/codegencommon.cpp @@ -1666,9 +1666,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr, rv1 = op1; rv2 = op2; -#ifdef TARGET_ARM64 assert(cns == 0); -#endif FOUND_AM: From b1ae6b09f8c0c4a81e7d7a71dfb8caee3cdca169 Mon Sep 17 00:00:00 2001 From: Egor Bogatov Date: Wed, 6 Oct 2021 23:27:47 +0300 Subject: [PATCH 4/5] Update codegencommon.cpp --- src/coreclr/jit/codegencommon.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/src/coreclr/jit/codegencommon.cpp b/src/coreclr/jit/codegencommon.cpp index 980125617abeb..146cfefe1d8fa 100644 --- a/src/coreclr/jit/codegencommon.cpp +++ b/src/coreclr/jit/codegencommon.cpp @@ -1666,7 +1666,6 @@ bool CodeGen::genCreateAddrMode(GenTree* addr, rv1 = op1; rv2 = op2; - assert(cns == 0); FOUND_AM: From 5e54adc862f3d2b936721f4b03a7b72483489a95 Mon Sep 17 00:00:00 2001 From: EgorBo Date: Thu, 7 Oct 2021 15:23:08 +0300 Subject: [PATCH 5/5] add ldr/str to r-r-r-i --- src/coreclr/jit/emitarm64.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 98d6dc0fb4d23..1642a709d5c7a 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -6459,6 +6459,11 @@ void emitter::emitIns_R_R_R_I(instruction ins, /* Figure out the encoding format of the instruction */ switch (ins) { + case INS_ldr: + case INS_str: + fmt = IF_LS_3A; + break; + case INS_extr: assert(insOptsNone(opt)); assert(isValidGeneralDatasize(size));