From 6a4db11246790373eeac71b5b9d20afe5bf96d37 Mon Sep 17 00:00:00 2001 From: EgorBo Date: Mon, 15 Nov 2021 22:48:53 +0300 Subject: [PATCH 1/3] Make 0.0 containable for fcmp --- src/coreclr/jit/codegenarm64.cpp | 3 +-- src/coreclr/jit/lowerarmarch.cpp | 12 ++++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 7a5e9122fcc38..7831b66ecaae6 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -3571,7 +3571,6 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree) var_types op2Type = genActualType(op2->TypeGet()); assert(!op1->isUsedFromMemory()); - assert(!op2->isUsedFromMemory()); genConsumeOperands(tree); @@ -3585,7 +3584,7 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree) assert(!op1->isContained()); assert(op1Type == op2Type); - if (op2->IsIntegralConst(0)) + if (op2->IsFPZero()) { assert(op2->isContained()); emit->emitIns_R_F(INS_fcmp, cmpSize, op1->GetRegNum(), 0.0); diff --git a/src/coreclr/jit/lowerarmarch.cpp b/src/coreclr/jit/lowerarmarch.cpp index bc6459eb0da0a..a3c43551e255b 100644 --- a/src/coreclr/jit/lowerarmarch.cpp +++ b/src/coreclr/jit/lowerarmarch.cpp @@ -55,6 +55,18 @@ bool Lowering::IsContainableImmed(GenTree* parentNode, GenTree* childNode) const { if (!varTypeIsFloating(parentNode->TypeGet())) { +#ifdef TARGET_ARM64 + if (parentNode->OperIsRelop() && childNode->IsCnsFltOrDbl() && childNode->IsFPZero()) + { + // Contain 0.0 constant in fcmp on arm64 + // TODO: Enable for arm too (vcmp) + + // We currently don't emit these for floating points + assert(!parentNode->OperIs(GT_TEST_EQ, GT_TEST_NE)); + return true; + } +#endif + // Make sure we have an actual immediate if (!childNode->IsCnsIntOrI()) return false; From ba786f55427de969a67545828e92e1a8947fc559 Mon Sep 17 00:00:00 2001 From: EgorBo Date: Mon, 15 Nov 2021 22:55:01 +0300 Subject: [PATCH 2/3] update comment --- src/coreclr/jit/lowerarmarch.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/coreclr/jit/lowerarmarch.cpp b/src/coreclr/jit/lowerarmarch.cpp index a3c43551e255b..3df2e633413a6 100644 --- a/src/coreclr/jit/lowerarmarch.cpp +++ b/src/coreclr/jit/lowerarmarch.cpp @@ -48,9 +48,6 @@ bool Lowering::IsCallTargetInRange(void* addr) // True if the immediate can be folded into an instruction, // for example small enough and non-relocatable. // -// TODO-CQ: we can contain a floating point 0.0 constant in a compare instruction -// (vcmp on arm, fcmp on arm64). -// bool Lowering::IsContainableImmed(GenTree* parentNode, GenTree* childNode) const { if (!varTypeIsFloating(parentNode->TypeGet())) From 1fdbe79523c807c55cf4e6472ff76f01fb78c2e6 Mon Sep 17 00:00:00 2001 From: EgorBo Date: Mon, 15 Nov 2021 23:07:08 +0300 Subject: [PATCH 3/3] Address feedback --- src/coreclr/jit/lowerarmarch.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/coreclr/jit/lowerarmarch.cpp b/src/coreclr/jit/lowerarmarch.cpp index 3df2e633413a6..b524efa4790b8 100644 --- a/src/coreclr/jit/lowerarmarch.cpp +++ b/src/coreclr/jit/lowerarmarch.cpp @@ -53,7 +53,7 @@ bool Lowering::IsContainableImmed(GenTree* parentNode, GenTree* childNode) const if (!varTypeIsFloating(parentNode->TypeGet())) { #ifdef TARGET_ARM64 - if (parentNode->OperIsRelop() && childNode->IsCnsFltOrDbl() && childNode->IsFPZero()) + if (parentNode->OperIsRelop() && childNode->IsFPZero()) { // Contain 0.0 constant in fcmp on arm64 // TODO: Enable for arm too (vcmp)