Update x86 DWARF registers maps #1633
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common/src/registers/MachRegister.C
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| case 1043: return Dyninst::x86::cr0; | ||
| case 1044: return Dyninst::x86::cr2; | ||
| case 1045: return Dyninst::x86::cr4; | ||
| case 1046: return Dyninst::x86::cr6; | ||
| case 1047: return Dyninst::x86::dr0; | ||
| case 1048: return Dyninst::x86::dr2; | ||
| case 1049: return Dyninst::x86::dr4; | ||
| case 1050: return Dyninst::x86::dr6; | ||
| case 1051: return Dyninst::x86::ymm0; | ||
| case 1052: return Dyninst::x86::ymm2; | ||
| case 1053: return Dyninst::x86::ymm4; | ||
| case 1054: return Dyninst::x86::ymm6; | ||
| case 1055: return Dyninst::x86::zmm0; | ||
| case 1056: return Dyninst::x86::zmm2; | ||
| case 1057: return Dyninst::x86::zmm4; | ||
| case 1058: return Dyninst::x86::zmm6; | ||
| case 1059: return Dyninst::x86::k0; | ||
| case 1060: return Dyninst::x86::k2; | ||
| case 1061: return Dyninst::x86::k4; | ||
| case 1062: return Dyninst::x86::k6; | ||
| case 1063: return Dyninst::x86::oeax; | ||
| case 1064: return Dyninst::x86::gsbase; | ||
| case 1065: return Dyninst::x86::tr1; | ||
| case 1066: return Dyninst::x86::tr3; | ||
| case 1067: return Dyninst::x86::tr5; | ||
| case 1068: return Dyninst::x86::tr7; |
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Is there a reason that the odd cr, dr, ymm, zmm, and k registers are missing, along with the even tr registers?
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Because the perl script I was using to generate these had a huge bug in it that I didn't notice. Fixed now.
common/src/registers/MachRegister.C
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| case 1102: return Dyninst::x86_64::tr0; | ||
| case 1103: return Dyninst::x86_64::tr2; | ||
| case 1104: return Dyninst::x86_64::tr4; | ||
| case 1105: return Dyninst::x86_64::tr6; |
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why are the odd tr registers missing?
| case 127: return Dyninst::InvalidReg; | ||
| case 128: return Dyninst::InvalidReg; | ||
| case 129: return Dyninst::InvalidReg; | ||
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The Oct 2023 ABI doc maps 130-145 to r16-r31 (the new registered defined by APX). These can likely be ignored for now.
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Yup. Capstone doesn't support AMX yet because it's based on LLVM 15 which has very poor support for them. The next release of Capstone will be based on at least LLVM 17 which has full support. I'll probably add the TMM registers soon just to have them.
I will add the missing control registers in a separate PR after this is merged.