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Ethernet connectivity #7

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gkasprow opened this issue Oct 24, 2018 · 0 comments
Open

Ethernet connectivity #7

gkasprow opened this issue Oct 24, 2018 · 0 comments
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@gkasprow
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AFCZ gigabit switch configuration

Routing of RMII lines:

Net name ZynQ MIO checked PORT 88E6321

ETH RGMII 1: GEM0 ok PORT2
RGMII1_TXD0, MIO27 ok P2_IND0
RGMII1_TXD1, MIO28 ok P2_IND1
RGMII1_TXD2, MIO29 ok P2_IND2
RGMII1_TXD3, MIO30 ok P2_IND3
RGMII1_TX_CTL, MIO31 ok P2_INDV
RGMII1_TX_CLK, MIO26 ok P2_INCLK
RGMII1_RXD0, MIO33 ok P2_OUTD0
RGMII1_RXD1, MIO34 ok P2_OUTD1
RGMII1_RXD2, MIO35 ok P2_OUTD2
RGMII1_RXD3, MIO36 ok P2_OUTD3
RGMII1_RX_CTL, MIO37 ok P2_OUTEN
RGMII1_RX_CLK MIO32 ok P2_OUTCLK

ETH RGMII 2: GEM3 PORT6
RGMII2_TXD0, MIO65 ok P6_IND0
RGMII2_TXD1, MIO66 ok P6_IND1
RGMII2_TXD2, MIO67 ok P6_IND2
RGMII2_TXD3, MIO68 ok P6_IND3
RGMII2_TX_CTL, MIO69 ok P6_INDV
RGMII2_TX_CLK, MIO64 ok P6_INCLK
RGMII2_RXD0, MIO71 ok P6_OUTD0
RGMII2_RXD1, MIO72 ok P6_OUTD1
RGMII2_RXD2, MIO73 ok P6_OUTD2
RGMII2_RXD3, MIO74 ok P6_OUTD3
RGMII2_RX_CTL, MIO75 ok P6_OUTEN
RGMII2_RX_CLK, MIO70 ok P6_OUTCLK
RGMII2_MDC, MIO76 ok MDC_CPU
RGMII2_MDIO MIO77 ok MDIO_CPU

88E6321 configuration

line state
Port 6: GEM3, RGMII2

0x7 RGMII
P6_MODE0 H
P6_MODE1 H
P6_MODE2 H

0 = 1.8V
P6_VDDOS1 L
P6_VDDOS0 L

Port 5: MMC MII
0x2 - MII MAC
0X1 - MII PHY
P5_MODE0 L
P5_MODE1 H
P5_MODE2 L

10 = 3.3V
P5_VDDOS1 H
P5_VDDOS0 L

ADDR0n floating
ADDR1n H
ADDR2n H
ADDR3n H
ADDR4n H

AMC:
P0_SMODE H : 1000BASEX or SGMII
P1_SMODE H : 1000BASEX or SGMII

EEE_WP L

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