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design review #2

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18 of 22 tasks
gkasprow opened this issue Jun 28, 2024 · 3 comments
Open
18 of 22 tasks

design review #2

gkasprow opened this issue Jun 28, 2024 · 3 comments

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@gkasprow
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gkasprow commented Jun 28, 2024

SCH:

PCB:

  • place the power unit status header somewhere here
    image
  • add pinout of I2C and UART headers
  • add board name and WUT logo, date and revision
@gkasprow
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gkasprow commented Jun 28, 2024

PCB:

  • follow datasheet of SOM with vias tenting; copy the footprint from K700-178 design
    image

image

  • replace SOM and other libs with CERN symbols and footprints
  • use single footprint instead of primitives for SOM!

@gkasprow
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gkasprow commented Jun 28, 2024

  • use one of supported OpenOCD jtag adapters, for the moment Xilinx JTAG connector is used; maybe switch to the pin header used on Ka-Ro boards

image

@gkasprow
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gkasprow commented Jul 9, 2024

there is conflict with enclosure
image
The 2.54 connectors are too high, the RJ45 will hit the wall
Use lower profile connectors, for the moment elevated ones are used with no reason

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