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there is conflict with enclosure
The 2.54 connectors are too high, the RJ45 will hit the wall
Use lower profile connectors, for the moment elevated ones are used with no reason
SCH:
add .gitignore
add IDC connector with power supply status
that thing won't work: the MCP has open drain, connect button to its output, VDD to 3V3 and passive network is not needed
the power supply chip already generates PG signal that can be used to reset the SOM as in the original design
such thing is hard to read, just route individual GPIOs without harnesses
for the moment P1V1 wakes up first with 1V8, then 2V5 and 3V3. It violates the PHY sequence requirements #3
connect SFP I2C to SoM. We need to report the optical power and configure SFP between SGMII/1000base-x mode
use WUT schematic template everywhere:
add 33Ohm series termination resistors at the RGMII output lines that go to the FPGA #6
add series 1k resistors between FPGA and SoM to prevent from latchup
add 1A thermal fuse on USB port; during plug insertion the buck may restart and may cause to restart other channels. #11
there are no strapping pins (PHY config) on schematic; is this done on purpose? #5
pls add voltage detection circuit that will report loss of one of redundant supplies ; do NOT connect P5V0 rail to this connector! #7
USB port lacks 5V power; SOM does not generate 5V power! re-arrange the power supply chip and let the PHY generate one of the voltages internally #10
use native SOM GPIO numbers; for the moment we have twice GPIO0...3; route the GPIOs as single wires; add FPGA GPIOs as text comment.
use P3V3 from SPEC-A7 connector to enable MPM converter
we need R20 and R22 to talk to SFP #4
pls add SD card connector, we will need it for development purposes; USB may be occupied with SPEC USB debug port
spelling Consol -> Console
PCB:
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