From 583137eaf3a8c8fa5ca6e32ddec92f45b741ab75 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 10 Jul 2024 16:21:11 +0200 Subject: [PATCH] phy/1000basex: Use pll.config["d"] to compute TX_PROGDIV_CFG/RX_PROGDIV_CFG to fix behavior with 200MHz ref_clk_freq. --- liteeth/phy/ku_1000basex.py | 10 ++++++++-- liteeth/phy/usp_gth_1000basex.py | 10 ++++++++-- liteeth/phy/usp_gty_1000basex.py | 10 ++++++++-- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/liteeth/phy/ku_1000basex.py b/liteeth/phy/ku_1000basex.py index 080d16cc..cfe91fdc 100644 --- a/liteeth/phy/ku_1000basex.py +++ b/liteeth/phy/ku_1000basex.py @@ -356,7 +356,10 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e p_RX_FABINT_USRCLK_FLOP = 0b0, p_RX_INT_DATAWIDTH = 0, p_RX_PMA_POWER_SAVE = 0b0, - p_RX_PROGDIV_CFG = {1.25e9 : 20.0, 3.125e9 : 10.0}[self.linerate], + p_RX_PROGDIV_CFG = { + 1.25e9 : 20.0*pll.config["d"]/4, + 3.125e9 : 10.0*pll.config["d"]/4, + }[self.linerate], p_RX_SAMPLE_PERIOD = 0b111, p_RX_SIG_VALID_DLY = 11, p_RX_SUM_DFETAPREP_EN = 0b0, @@ -455,7 +458,10 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e p_TX_PMADATA_OPT = 0b0, p_TX_PMA_POWER_SAVE = 0b0, p_TX_PROGCLK_SEL = "CPLL", - p_TX_PROGDIV_CFG = {1.25e9 : 20.0, 3.125e9 : 10.0}[self.linerate], + p_TX_PROGDIV_CFG = { + 1.25e9 : 20.0*pll.config["d"]/4, + 3.125e9 : 10.0*pll.config["d"]/4, + }[self.linerate], p_TX_QPI_STATUS_EN = 0b0, p_TX_RXDETECT_CFG = 0b00000000110010, p_TX_RXDETECT_REF = 0b100, diff --git a/liteeth/phy/usp_gth_1000basex.py b/liteeth/phy/usp_gth_1000basex.py index 68160f6c..1d811249 100644 --- a/liteeth/phy/usp_gth_1000basex.py +++ b/liteeth/phy/usp_gth_1000basex.py @@ -400,7 +400,10 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e p_RX_INT_DATAWIDTH = 0, p_RX_PMA_POWER_SAVE = 0b0, p_RX_PMA_RSV0 = 0b0000000000000000, - p_RX_PROGDIV_CFG = {1.25e9 : 20.0, 3.125e9 : 10.0}[self.linerate], + p_RX_PROGDIV_CFG = { + 1.25e9 : 20.0*pll.config["d"]/4, + 3.125e9 : 10.0*pll.config["d"]/4, + }[self.linerate], p_RX_PROGDIV_RATE = 0b0000000000000001, p_RX_RESLOAD_CTRL = 0b0000, p_RX_RESLOAD_OVRD = 0b0, @@ -513,7 +516,10 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e p_TX_PMA_RSV0 = 0b0000000000001000, p_TX_PREDRV_CTRL = 2, p_TX_PROGCLK_SEL = "PREPI", - p_TX_PROGDIV_CFG = {1.25e9 : 20.0, 3.125e9 : 10.0}[self.linerate], + p_TX_PROGDIV_CFG = { + 1.25e9 : 20.0*pll.config["d"]/4, + 3.125e9 : 10.0*pll.config["d"]/4, + }[self.linerate], p_TX_PROGDIV_RATE = 0b0000000000000001, p_TX_QPI_STATUS_EN = 0b0, p_TX_RXDETECT_CFG = 0b00000000110010, diff --git a/liteeth/phy/usp_gty_1000basex.py b/liteeth/phy/usp_gty_1000basex.py index 24e54769..4bb16b48 100644 --- a/liteeth/phy/usp_gty_1000basex.py +++ b/liteeth/phy/usp_gty_1000basex.py @@ -418,7 +418,10 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e p_RX_INT_DATAWIDTH = 0, p_RX_PMA_POWER_SAVE = 0b0, p_RX_PMA_RSV0 = 0b0000000000101111, - p_RX_PROGDIV_CFG = {1.25e9 : 20.0, 3.125e9 : 10.0}[self.linerate], + p_RX_PROGDIV_CFG = { + 1.25e9 : 20.0*pll.config["d"]/4, + 3.125e9 : 10.0*pll.config["d"]/4, + }[self.linerate], p_RX_PROGDIV_RATE = 0b0000000000000001, p_RX_RESLOAD_CTRL = 0b0000, p_RX_RESLOAD_OVRD = 0b0, @@ -530,7 +533,10 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, refclk_freq=200e p_TX_PMA_RSV0 = 0b0000000000000000, p_TX_PMA_RSV1 = 0b0000000000000000, p_TX_PROGCLK_SEL = "CPLL", - p_TX_PROGDIV_CFG = {1.25e9 : 20.0, 3.125e9 : 10.0}[self.linerate], + p_TX_PROGDIV_CFG = { + 1.25e9 : 20.0*pll.config["d"]/4, + 3.125e9 : 10.0*pll.config["d"]/4, + }[self.linerate], p_TX_PROGDIV_RATE = 0b0000000000000001, p_TX_RXDETECT_CFG = 0b00000000110010, p_TX_RXDETECT_REF = 5,