From f35f05cd7946b4e166091df69ee714488a2ae016 Mon Sep 17 00:00:00 2001 From: Juraj Sadel Date: Mon, 19 Aug 2024 14:23:30 +0200 Subject: [PATCH] Patch typo in debug assist register name and used patched esp-pacs --- esp-hal/Cargo.toml | 14 +++++++------- esp-hal/src/debugger.rs | 21 +++++---------------- 2 files changed, 12 insertions(+), 23 deletions(-) diff --git a/esp-hal/Cargo.toml b/esp-hal/Cargo.toml index 11a516cfa89..f6e653c0174 100644 --- a/esp-hal/Cargo.toml +++ b/esp-hal/Cargo.toml @@ -53,13 +53,13 @@ xtensa-lx = { version = "0.9.0", optional = true } # IMPORTANT: # Each supported device MUST have its PAC included below along with a # corresponding feature. -esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } -esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } -esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } -esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } -esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } -esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } -esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } +esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true } +esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true } +esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true } +esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true } +esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true } +esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true } +esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true } [target.'cfg(target_arch = "riscv32")'.dependencies] esp-riscv-rt = { version = "0.9.0", path = "../esp-riscv-rt" } diff --git a/esp-hal/src/debugger.rs b/esp-hal/src/debugger.rs index 4c970f82693..3e4ab7043e8 100644 --- a/esp-hal/src/debugger.rs +++ b/esp-hal/src/debugger.rs @@ -11,22 +11,11 @@ pub fn debugger_connected() -> bool { { use crate::peripherals::ASSIST_DEBUG; let assist_debug = unsafe { &*ASSIST_DEBUG::ptr() }; - #[cfg(feature = "esp32c2")] - { - assist_debug - .core_0_debug_mode() - .read() - .core_0_debug_module_active() - .bit_is_set() - } - #[cfg(not(feature = "esp32c2"))] - { - assist_debug - .c0re_0_debug_mode() - .read() - .core_0_debug_module_active() - .bit_is_set() - } + assist_debug + .core_0_debug_mode() + .read() + .core_0_debug_module_active() + .bit_is_set() } #[cfg(not(any(xtensa, riscv)))]