diff --git a/esp-hal-common/Cargo.toml b/esp-hal-common/Cargo.toml index 4c275c22c7d..73cd09fd66a 100644 --- a/esp-hal-common/Cargo.toml +++ b/esp-hal-common/Cargo.toml @@ -20,7 +20,7 @@ embedded-hal-nb = { version = "=1.0.0-alpha.1", optional = true } fugit = "0.3.6" lock_api = { version = "0.4.9", optional = true } nb = "1.0.0" -paste = "=1.0.8" +paste = "1.0.9" procmacros = { version = "0.1.0", package = "esp-hal-procmacros", path = "../esp-hal-procmacros" } void = { version = "1.0.2", default-features = false } embedded-dma = "0.2.0" @@ -34,7 +34,7 @@ embassy-time = { version = "0.1.0", features = ["nightly"], optional = tru # RISC-V riscv = { version = "0.10.0", optional = true } -riscv-atomic-emulation-trap = { version = "0.2.0", optional = true } +riscv-atomic-emulation-trap = { version = "0.3.0", optional = true } # Xtensa xtensa-lx = { version = "0.7.0", optional = true } diff --git a/esp-hal-common/src/analog/adc/esp32.rs b/esp-hal-common/src/analog/adc/esp32.rs index b1c6a415f4f..976bcbb82af 100644 --- a/esp-hal-common/src/analog/adc/esp32.rs +++ b/esp-hal-common/src/analog/adc/esp32.rs @@ -414,3 +414,59 @@ macro_rules! impl_adc_interface { } pub use impl_adc_interface; + +pub mod implementation { + //! Analog to digital (ADC) conversion support. + //! + //! This module provides functions for reading analog values from two + //! analog to digital converters available on the ESP32: `ADC1` and `ADC2`. + //! + //! The following pins can be configured for analog readout: + //! + //! | Channel | ADC1 | ADC2 | + //! |---------|----------------------|---------------| + //! | 0 | GPIO36 (SENSOR_VP) | GPIO4 | + //! | 1 | GPIO37 (SENSOR_CAPP) | GPIO0 | + //! | 2 | GPIO38 (SENSOR_CAPN) | GPIO2 | + //! | 3 | GPIO39 (SENSOR_VN) | GPIO15 (MTDO) | + //! | 4 | GPIO33 (32K_XP) | GPIO13 (MTCK) | + //! | 5 | GPIO32 (32K_XN) | GPIO12 (MTDI) | + //! | 6 | GPIO34 (VDET_1) | GPIO14 (MTMS) | + //! | 7 | GPIO35 (VDET_2) | GPIO27 | + //! | 8 | | GPIO25 | + //! | 9 | | GPIO26 | + + use embedded_hal::adc::Channel; + + use super::impl_adc_interface; + pub use crate::analog::{adc::*, ADC1, ADC2}; + use crate::gpio::*; + + impl_adc_interface! { + ADC1 [ + (Gpio36, 0), // Alt. name: SENSOR_VP + (Gpio37, 1), // Alt. name: SENSOR_CAPP + (Gpio38, 2), // Alt. name: SENSOR_CAPN + (Gpio39, 3), // Alt. name: SENSOR_VN + (Gpio33, 4), // Alt. name: 32K_XP + (Gpio32, 5), // Alt. name: 32K_XN + (Gpio34, 6), // Alt. name: VDET_1 + (Gpio35, 7), // Alt. name: VDET_2 + ] + } + + impl_adc_interface! { + ADC2 [ + (Gpio4, 0), + (Gpio0, 1), + (Gpio2, 2), + (Gpio15, 3), // Alt. name: MTDO + (Gpio13, 4), // Alt. name: MTCK + (Gpio12, 5), // Alt. name: MTDI + (Gpio14, 6), // Alt. name: MTMS + (Gpio27, 7), + (Gpio25, 8), + (Gpio26, 9), + ] + } +} diff --git a/esp-hal-common/src/analog/adc/riscv.rs b/esp-hal-common/src/analog/adc/riscv.rs index 7ccb7a3ab0d..a21c8f8376b 100644 --- a/esp-hal-common/src/analog/adc/riscv.rs +++ b/esp-hal-common/src/analog/adc/riscv.rs @@ -285,3 +285,58 @@ macro_rules! impl_adc_interface { } pub use impl_adc_interface; + +#[cfg(esp32c3)] +pub mod implementation { + //! Analog to digital (ADC) conversion support. + //! + //! This module provides functions for reading analog values from two + //! analog to digital converters available on the ESP32-C3: `ADC1` and + //! `ADC2`. + + use embedded_hal::adc::Channel; + + use super::impl_adc_interface; + pub use crate::analog::{adc::*, ADC1, ADC2}; + use crate::gpio::*; + + impl_adc_interface! { + ADC1 [ + (Gpio0, 0), + (Gpio1, 1), + (Gpio2, 2), + (Gpio3, 3), + (Gpio4, 4), + ] + } + + impl_adc_interface! { + ADC2 [ + (Gpio5, 4), + ] + } +} + +#[cfg(esp32c2)] +pub mod implementation { + //! Analog to digital (ADC) conversion support. + //! + //! This module provides functions for reading analog values from the + //! analog to digital converter available on the ESP32-C2: `ADC1`. + + use embedded_hal::adc::Channel; + + use super::impl_adc_interface; + pub use crate::analog::{adc::*, ADC1}; + use crate::gpio::*; + + impl_adc_interface! { + ADC1 [ + (Gpio0, 0), + (Gpio1, 1), + (Gpio2, 2), + (Gpio3, 3), + (Gpio4, 4), + ] + } +} diff --git a/esp-hal-common/src/analog/adc/xtensa.rs b/esp-hal-common/src/analog/adc/xtensa.rs index 5ef812d8198..0bf5e72cc72 100644 --- a/esp-hal-common/src/analog/adc/xtensa.rs +++ b/esp-hal-common/src/analog/adc/xtensa.rs @@ -161,11 +161,7 @@ impl RegisterAccess for ADC1 { fn read_done_sar() -> bool { let sensors = unsafe { &*SENS::ptr() }; - sensors. - sar_meas1_ctrl2. - read(). - meas1_done_sar(). - bit_is_set() + sensors.sar_meas1_ctrl2.read().meas1_done_sar().bit_is_set() } fn read_data_sar() -> u16 { @@ -242,11 +238,7 @@ impl RegisterAccess for ADC2 { fn read_done_sar() -> bool { let sensors = unsafe { &*SENS::ptr() }; - sensors. - sar_meas2_ctrl2. - read(). - meas2_done_sar(). - bit_is_set() + sensors.sar_meas2_ctrl2.read().meas2_done_sar().bit_is_set() } fn read_data_sar() -> u16 { @@ -413,3 +405,93 @@ macro_rules! impl_adc_interface { } pub use impl_adc_interface; + +#[cfg(esp32s3)] +pub mod implementation { + //! Analog to digital (ADC) conversion support. + //! + //! This module provides functions for reading analog values from two + //! analog to digital converters available on the ESP32-S3: `ADC1` and + //! `ADC2`. + + use embedded_hal::adc::Channel; + + use super::impl_adc_interface; + pub use crate::analog::{adc::*, ADC1, ADC2}; + use crate::gpio::*; + + impl_adc_interface! { + ADC1 [ + (Gpio1, 0), + (Gpio2, 1), + (Gpio3, 2), + (Gpio4, 3), + (Gpio5, 4), + (Gpio6, 5), + (Gpio7, 6), + (Gpio8, 7), + (Gpio9, 8), + (Gpio10,9), + ] + } + + impl_adc_interface! { + ADC2 [ + (Gpio11, 0), + (Gpio12, 1), + (Gpio13, 2), + (Gpio14, 3), + (Gpio15, 4), + (Gpio16, 5), + (Gpio17, 6), + (Gpio18, 7), + (Gpio19, 8), + (Gpio20, 9), + ] + } +} + +#[cfg(esp32s2)] +pub mod implementation { + //! Analog to digital (ADC) conversion support. + //! + //! This module provides functions for reading analog values from two + //! analog to digital converters available on the ESP32-S2: `ADC1` and + //! `ADC2`. + + use embedded_hal::adc::Channel; + + use super::impl_adc_interface; + pub use crate::analog::{adc::*, ADC1, ADC2}; + use crate::gpio::*; + + impl_adc_interface! { + ADC1 [ + (Gpio1, 0), + (Gpio2, 1), + (Gpio3, 2), + (Gpio4, 3), + (Gpio5, 4), + (Gpio6, 5), + (Gpio7, 6), + (Gpio8, 7), + (Gpio9, 8), + (Gpio10,9), + ] + } + + impl_adc_interface! { + ADC2 [ + (Gpio11, 0), + (Gpio12, 1), + (Gpio13, 2), + (Gpio14, 3), + (Gpio15, 4), + (Gpio16, 5), + (Gpio17, 6), + (Gpio18, 7), + (Gpio19, 8), + (Gpio20, 9), + ] + } +} diff --git a/esp-hal-common/src/analog/dac.rs b/esp-hal-common/src/analog/dac.rs index 134fc787c9a..11b70509c16 100644 --- a/esp-hal-common/src/analog/dac.rs +++ b/esp-hal-common/src/analog/dac.rs @@ -88,8 +88,8 @@ macro_rules! impl_dac { use crate::gpio; $( - paste! { - pub use esp_hal_common::analog::dac::[]; + paste::paste! { + pub use $crate::analog::dac::[]; /// DAC channel pub struct [] { @@ -101,8 +101,8 @@ macro_rules! impl_dac { impl [] { /// Constructs a new DAC instance pub fn dac( - _dac: esp_hal_common::analog::[], - _pin: gpio::$gpio, + _dac: $crate::analog::[], + _pin: gpio::$gpio<$crate::Analog>, ) -> Result { let dac = Self { _private: PhantomData, @@ -125,3 +125,33 @@ macro_rules! impl_dac { } pub use impl_dac; + +#[cfg(esp32)] +pub mod implementation { + //! Digital to analog (DAC) conversion. + //! + //! This module provides functions for controling two digital to + //! analog converters, available on ESP32: `DAC1` and `DAC2`. + //! + //! The DAC1 is available on the GPIO pin 25, and DAC2 on pin 26. + + pub use super::*; + use crate::impl_dac; + + impl_dac!(1 => Gpio25, 2 => Gpio26,); +} + +#[cfg(esp32s2)] +pub mod implementation { + //! Digital to analog (DAC) conversion. + //! + //! This module provides functions for controling two digital to + //! analog converters, available on ESP32: `DAC1` and `DAC2`. + //! + //! The DAC1 is available on the GPIO pin 17, and DAC2 on pin 18. + + pub use super::*; + use crate::impl_dac; + + impl_dac!(1 => Gpio17, 2 => Gpio18,); +} diff --git a/esp-hal-common/src/gpio.rs b/esp-hal-common/src/gpio.rs index cae2f804d86..77cad104536 100644 --- a/esp-hal-common/src/gpio.rs +++ b/esp-hal-common/src/gpio.rs @@ -1,14 +1,15 @@ -//! GPIO Types +//! General Purpose I/Os //! -//! Various traits and enums to work with GPIO +//! To get access to the pins, you first need to convert them into a HAL +//! designed struct from the pac struct `GPIO` and `IO_MUX` using `IO::new`. +//! +//! ```no_run +//! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); +//! let mut led = io.pins.gpio5.into_push_pull_output(); +//! ``` use core::marker::PhantomData; -#[doc(hidden)] -pub use paste::paste; - -use crate::pac::GPIO; - #[doc(hidden)] #[cfg_attr(esp32, path = "gpio/esp32.rs")] #[cfg_attr(esp32c2, path = "gpio/esp32c2.rs")] @@ -17,6 +18,21 @@ use crate::pac::GPIO; #[cfg_attr(esp32s3, path = "gpio/esp32s3.rs")] pub mod types; +use core::convert::Infallible; + +pub use crate::types::*; +use crate::{ + pac::{GPIO, IO_MUX}, + types::{ + get_io_mux_reg, + gpio_intr_enable, + OutputSignalType, + GPIO_FUNCTION, + INPUT_SIGNAL_MAX, + OUTPUT_SIGNAL_MAX, + }, +}; + #[derive(Copy, Clone)] pub enum Event { RisingEdge = 1, @@ -60,10 +76,13 @@ pub struct Alternate { _mode: PhantomData, } +#[doc(hidden)] pub struct AF0; +#[doc(hidden)] pub struct AF1; +#[doc(hidden)] pub struct AF2; pub enum DriveStrength { @@ -273,144 +292,169 @@ where } #[doc(hidden)] -pub struct Bank0GpioRegisterAccess {} +pub struct Bank0GpioRegisterAccess; + #[doc(hidden)] -pub struct Bank1GpioRegisterAccess {} +pub struct Bank1GpioRegisterAccess; #[doc(hidden)] pub trait BankGpioRegisterAccess { - fn write_out_en_clear(word: u32); + fn write_out_en_clear(&self, word: u32); + + fn write_out_en_set(&self, word: u32); + + fn read_input(&self) -> u32; + + fn read_output(&self) -> u32; + + fn write_interrupt_status_clear(&self, word: u32); + + fn write_output_set(&self, word: u32); + + fn write_output_clear(&self, word: u32); - fn write_out_en_set(word: u32); + fn set_output_signal(&self, gpio_num: u8, signal: u32) { + let gpio = unsafe { &*crate::pac::GPIO::PTR }; + gpio.func_out_sel_cfg[gpio_num as usize] + .modify(|_, w| unsafe { w.out_sel().bits(signal as OutputSignalType) }); + } - fn read_input() -> u32; + fn configure_out_sel(&self, gpio_num: u8, signal: u32, invert: bool, oen: bool, oen_inv: bool) { + let gpio = unsafe { &*crate::pac::GPIO::PTR }; + gpio.func_out_sel_cfg[gpio_num as usize].modify(|_, w| unsafe { + w.out_sel() + .bits(signal as OutputSignalType) + .inv_sel() + .bit(invert) + .oen_sel() + .bit(oen) + .oen_inv_sel() + .bit(oen_inv) + }); + } - fn read_output() -> u32; + fn set_signal_to_level(&self, signal: u32, high: bool) { + let gpio = unsafe { &*crate::pac::GPIO::PTR }; + gpio.func_in_sel_cfg[signal as usize].modify(|_, w| unsafe { + w.sel() + .set_bit() + .in_inv_sel() + .bit(false) + .in_sel() + .bits(if high { ONE_INPUT } else { ZERO_INPUT }) + }); + } - fn write_interrupt_status_clear(word: u32); + fn clear_func_in_sel(&self, signal: u32) { + let gpio = unsafe { &*crate::pac::GPIO::PTR }; + gpio.func_in_sel_cfg[signal as usize].modify(|_, w| w.sel().clear_bit()); + } - fn write_output_set(word: u32); + fn set_int_enable( + &self, + gpio_num: u8, + int_ena: u32, + int_type: u8, + wake_up_from_light_sleep: bool, + ) { + let gpio = unsafe { &*crate::pac::GPIO::PTR }; + gpio.pin[gpio_num as usize].modify(|_, w| unsafe { + w.int_ena() + .bits(int_ena as u8) + .int_type() + .bits(int_type as u8) + .wakeup_enable() + .bit(wake_up_from_light_sleep) + }); + } - fn write_output_clear(word: u32); + fn set_open_drain(&self, gpio_num: u8, open_drain: bool) { + let gpio = unsafe { &*crate::pac::GPIO::PTR }; + gpio.pin[gpio_num as usize].modify(|_, w| w.pad_driver().bit(open_drain)); + } } impl BankGpioRegisterAccess for Bank0GpioRegisterAccess { - fn write_out_en_clear(word: u32) { + fn write_out_en_clear(&self, word: u32) { unsafe { &*GPIO::PTR } .enable_w1tc .write(|w| unsafe { w.bits(word) }); } - fn write_out_en_set(word: u32) { + fn write_out_en_set(&self, word: u32) { unsafe { &*GPIO::PTR } .enable_w1ts .write(|w| unsafe { w.bits(word) }); } - fn read_input() -> u32 { + fn read_input(&self) -> u32 { unsafe { &*GPIO::PTR }.in_.read().bits() } - fn read_output() -> u32 { + fn read_output(&self) -> u32 { unsafe { &*GPIO::PTR }.out.read().bits() } - fn write_interrupt_status_clear(word: u32) { + fn write_interrupt_status_clear(&self, word: u32) { unsafe { &*GPIO::PTR } .status_w1tc .write(|w| unsafe { w.bits(word) }); } - fn write_output_set(word: u32) { + fn write_output_set(&self, word: u32) { unsafe { &*GPIO::PTR } .out_w1ts .write(|w| unsafe { w.bits(word) }); } - fn write_output_clear(word: u32) { + fn write_output_clear(&self, word: u32) { unsafe { &*GPIO::PTR } .out_w1tc .write(|w| unsafe { w.bits(word) }); } } -#[doc(hidden)] #[cfg(not(any(esp32c2, esp32c3)))] impl BankGpioRegisterAccess for Bank1GpioRegisterAccess { - fn write_out_en_clear(word: u32) { + fn write_out_en_clear(&self, word: u32) { unsafe { &*GPIO::PTR } .enable1_w1tc .write(|w| unsafe { w.bits(word) }); } - fn write_out_en_set(word: u32) { + fn write_out_en_set(&self, word: u32) { unsafe { &*GPIO::PTR } .enable1_w1ts .write(|w| unsafe { w.bits(word) }); } - fn read_input() -> u32 { + fn read_input(&self) -> u32 { unsafe { &*GPIO::PTR }.in1.read().bits() } - fn read_output() -> u32 { + fn read_output(&self) -> u32 { unsafe { &*GPIO::PTR }.out1.read().bits() } - fn write_interrupt_status_clear(word: u32) { + fn write_interrupt_status_clear(&self, word: u32) { unsafe { &*GPIO::PTR } .status1_w1tc .write(|w| unsafe { w.bits(word) }); } - fn write_output_set(word: u32) { + fn write_output_set(&self, word: u32) { unsafe { &*GPIO::PTR } .out1_w1ts .write(|w| unsafe { w.bits(word) }); } - fn write_output_clear(word: u32) { + fn write_output_clear(&self, word: u32) { unsafe { &*GPIO::PTR } .out1_w1tc .write(|w| unsafe { w.bits(word) }); } } -#[doc(hidden)] -pub trait GpioRegisters -where - RegisterAccess: BankGpioRegisterAccess, -{ - fn write_out_en_clear(&self, word: u32) { - RegisterAccess::write_out_en_clear(word); - } - - fn write_out_en_set(&self, word: u32) { - RegisterAccess::write_out_en_set(word); - } - - fn read_input(&self) -> u32 { - RegisterAccess::read_input() - } - - fn read_output(&self) -> u32 { - RegisterAccess::read_output() - } - - fn write_interrupt_status_clear(&self, word: u32) { - RegisterAccess::write_interrupt_status_clear(word); - } - - fn write_output_clear(&self, word: u32) { - RegisterAccess::write_output_clear(word) - } - - fn write_output_set(&self, word: u32) { - RegisterAccess::write_output_set(word) - } -} - -#[doc(hidden)] pub fn connect_low_to_peripheral(signal: InputSignal) { unsafe { &*GPIO::PTR }.func_in_sel_cfg[signal as usize].modify(|_, w| unsafe { w.sel() @@ -422,7 +466,6 @@ pub fn connect_low_to_peripheral(signal: InputSignal) { }); } -#[doc(hidden)] pub fn connect_high_to_peripheral(signal: InputSignal) { unsafe { &*GPIO::PTR }.func_in_sel_cfg[signal as usize].modify(|_, w| unsafe { w.sel() @@ -434,767 +477,883 @@ pub fn connect_high_to_peripheral(signal: InputSignal) { }); } -// Only for ESP32 in order to workaround errata 3.6 #[doc(hidden)] -#[macro_export] -macro_rules! impl_errata36 { - (None, $pull_down:expr, $pull_up:expr) => { - // NONE - }; +pub trait PinType {} - (pad_dac1, $pull_down:expr, $pull_up:expr) => { - use crate::pac::RTCIO; - let rtcio = unsafe { &*RTCIO::PTR }; - rtcio.pad_dac1.modify(|r, w| unsafe { - w.bits(r.bits()) - .pdac1_rue() - .bit($pull_up) - .pdac1_rde() - .bit($pull_down) - }); - }; +#[doc(hidden)] +pub trait IsOutputPin: PinType {} - (pad_dac2, $pull_down:expr, $pull_up:expr) => { - use crate::pac::RTCIO; - let rtcio = unsafe { &*RTCIO::PTR }; - rtcio.pad_dac2.modify(|r, w| unsafe { - w.bits(r.bits()) - .pdac2_rue() - .bit($pull_up) - .pdac2_rde() - .bit($pull_down) - }); - }; +#[doc(hidden)] +pub trait IsInputPin: PinType {} - (xtal_32k_n, $pull_down:expr, $pull_up:expr) => { - use crate::pac::RTCIO; - let rtcio = unsafe { &*RTCIO::PTR }; - rtcio.xtal_32k_pad.modify(|r, w| unsafe { - w.bits(r.bits()) - .x32n_rue() - .bit($pull_up) - .x32n_rde() - .bit($pull_down) - }); - }; +#[doc(hidden)] +pub trait IsAnalogPin: PinType {} - (xtal_32k_p, $pull_down:expr, $pull_up:expr) => { - use crate::pac::RTCIO; - let rtcio = unsafe { &*RTCIO::PTR }; - rtcio.xtal_32k_pad.modify(|r, w| unsafe { - w.bits(r.bits()) - .x32p_rue() - .bit($pull_up) - .x32p_rde() - .bit($pull_down) - }); - }; +#[doc(hidden)] +pub struct InputOutputPinType; - ($errata36:ident, $pull_down:expr, $pull_up:expr) => { - use crate::pac::RTCIO; - let rtcio = unsafe { &*RTCIO::PTR }; - rtcio - .$errata36 - .modify(|r, w| unsafe { w.bits(r.bits()).rue().bit($pull_up).rde().bit($pull_down) }); - }; -} +#[doc(hidden)] +pub struct InputOnlyPinType; #[doc(hidden)] -#[macro_export] -macro_rules! impl_input { - ( - $gpio_function:ident, - $input_signal:ty, - $pxi:ident: - ( - $pin_num:expr, $iomux_reg:expr, $bit:expr, - $errata36:ident - ) - $( ,( $( $af_signal:ident : $af:ident ),* ))? - ) => { - impl embedded_hal::digital::v2::InputPin for $pxi> { - type Error = Infallible; +pub struct InputOutputAnalogPinType; - fn is_high(&self) -> Result { - Ok(self.read_input() & (1 << $bit) != 0) - } +#[doc(hidden)] +pub struct InputOnlyAnalogPinType; - fn is_low(&self) -> Result { - Ok(!self.is_high()?) - } - } +impl PinType for InputOutputPinType {} +impl IsOutputPin for InputOutputPinType {} +impl IsInputPin for InputOutputPinType {} - impl embedded_hal::digital::v2::InputPin for $pxi> { - type Error = Infallible; +impl PinType for InputOnlyPinType {} +impl IsInputPin for InputOnlyPinType {} - fn is_high(&self) -> Result { - Ok(self.read_input() & (1 << $bit) != 0) - } +impl PinType for InputOutputAnalogPinType {} +impl IsOutputPin for InputOutputAnalogPinType {} +impl IsInputPin for InputOutputAnalogPinType {} +impl IsAnalogPin for InputOutputAnalogPinType {} - fn is_low(&self) -> Result { - Ok(!self.is_high()?) - } - } +impl PinType for InputOnlyAnalogPinType {} +impl IsInputPin for InputOnlyAnalogPinType {} +impl IsAnalogPin for InputOnlyAnalogPinType {} - #[cfg(feature = "eh1")] - impl embedded_hal_1::digital::ErrorType for $pxi> { - type Error = Infallible; - } +pub struct GpioPin +where + RA: BankGpioRegisterAccess, + PINTYPE: PinType, +{ + _mode: PhantomData, + _pintype: PhantomData, + reg_access: RA, + af_input_signals: [Option; 6], + af_output_signals: [Option; 6], +} - #[cfg(feature = "eh1")] - impl embedded_hal_1::digital::InputPin for $pxi> { - fn is_high(&self) -> Result { - Ok(self.read_input() & (1 << $bit) != 0) - } +impl embedded_hal::digital::v2::InputPin + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: PinType, +{ + type Error = Infallible; + fn is_high(&self) -> Result { + Ok(self.reg_access.read_input() & (1 << (GPIONUM % 32)) != 0) + } + fn is_low(&self) -> Result { + Ok(!self.is_high()?) + } +} - fn is_low(&self) -> Result { - Ok(!self.is_high()?) - } - } +impl embedded_hal::digital::v2::InputPin + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: PinType, +{ + type Error = Infallible; + fn is_high(&self) -> Result { + Ok(self.reg_access.read_input() & (1 << (GPIONUM % 32)) != 0) + } + fn is_low(&self) -> Result { + Ok(!self.is_high()?) + } +} - impl $pxi { - fn init_input(&self, pull_down: bool, pull_up: bool) { - let gpio = unsafe { &*GPIO::PTR }; - let iomux = unsafe { &*IO_MUX::PTR }; - - self.write_out_en_clear(1 << $bit); - - gpio.func_out_sel_cfg[$pin_num] - .modify(|_, w| unsafe { w.out_sel().bits(OutputSignal::GPIO as OutputSignalType) }); - - impl_errata36!($errata36, pull_down, pull_up); - - paste! { - iomux.$iomux_reg.modify(|_, w| unsafe { - w.mcu_sel() - .bits(AlternateFunction::$gpio_function as u8) - .fun_ie() - .set_bit() - .fun_wpd() - .bit(pull_down) - .fun_wpu() - .bit(pull_up) - .slp_sel() - .clear_bit() - }); - } - } +#[cfg(feature = "eh1")] +impl embedded_hal_1::digital::ErrorType + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: PinType, +{ + type Error = Infallible; +} - pub fn into_floating_input(self) -> $pxi> { - self.init_input(false, false); - $pxi { _mode: PhantomData } - } - } +#[cfg(feature = "eh1")] +impl embedded_hal_1::digital::InputPin + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: PinType, +{ + fn is_high(&self) -> Result { + Ok(self.reg_access.read_input() & (1 << (GPIONUM % 32)) != 0) + } + fn is_low(&self) -> Result { + Ok(!self.is_high()?) + } +} - impl InputPin for $pxi { - fn set_to_input(&mut self) -> &mut Self { - self.init_input(false, false); - self - } +impl GpioPin +where + RA: BankGpioRegisterAccess, + PINTYPE: PinType, +{ + fn init_input(&self, pull_down: bool, pull_up: bool) { + let gpio = unsafe { &*GPIO::PTR }; + + self.reg_access.write_out_en_clear(1 << (GPIONUM % 32)); + gpio.func_out_sel_cfg[GPIONUM as usize] + .modify(|_, w| unsafe { w.out_sel().bits(OutputSignal::GPIO as OutputSignalType) }); + + #[cfg(esp32)] + types::errata36(GPIONUM, pull_up, pull_down); + + get_io_mux_reg(GPIONUM).modify(|_, w| unsafe { + w.mcu_sel() + .bits(GPIO_FUNCTION as u8) + .fun_ie() + .set_bit() + .fun_wpd() + .bit(pull_down) + .fun_wpu() + .bit(pull_up) + .slp_sel() + .clear_bit() + }); + } - fn enable_input(&mut self, on: bool) -> &mut Self { - paste!{ - unsafe { &*IO_MUX::PTR } - .$iomux_reg - .modify(|_, w| w.fun_ie().bit(on)); - } - self - } + pub fn into_floating_input(self) -> GpioPin, RA, PINTYPE, GPIONUM> { + self.init_input(false, false); + GpioPin { + _mode: PhantomData, + _pintype: PhantomData, + reg_access: self.reg_access, + af_input_signals: self.af_input_signals, + af_output_signals: self.af_output_signals, + } + } - fn enable_input_in_sleep_mode(&mut self, on: bool) -> &mut Self { - paste! { - unsafe { &*IO_MUX::PTR } - .$iomux_reg - .modify(|_, w| w.mcu_ie().bit(on)); - } - self - } + pub fn into_pull_up_input(self) -> GpioPin, RA, PINTYPE, GPIONUM> { + self.init_input(false, true); + GpioPin { + _mode: PhantomData, + _pintype: PhantomData, + reg_access: self.reg_access, + af_input_signals: self.af_input_signals, + af_output_signals: self.af_output_signals, + } + } - fn is_input_high(&self) -> bool { - self.read_input() & (1 << $bit) != 0 - } + pub fn into_pull_down_input(self) -> GpioPin, RA, PINTYPE, GPIONUM> { + self.init_input(true, false); + GpioPin { + _mode: PhantomData, + _pintype: PhantomData, + reg_access: self.reg_access, + af_input_signals: self.af_input_signals, + af_output_signals: self.af_output_signals, + } + } +} - fn connect_input_to_peripheral_with_options( - &mut self, - signal: InputSignal, - invert: bool, - force_via_gpio_mux: bool, - ) -> &mut Self { - let af = if force_via_gpio_mux { - AlternateFunction::$gpio_function - } else { - match signal { - $( $( - InputSignal::$af_signal => AlternateFunction::$af, - )* )? - _ => AlternateFunction::$gpio_function +impl InputPin for GpioPin +where + RA: BankGpioRegisterAccess, + PINTYPE: PinType, +{ + fn set_to_input(&mut self) -> &mut Self { + self.init_input(false, false); + self + } + fn enable_input(&mut self, on: bool) -> &mut Self { + get_io_mux_reg(GPIONUM).modify(|_, w| w.fun_ie().bit(on)); + self + } + fn enable_input_in_sleep_mode(&mut self, on: bool) -> &mut Self { + get_io_mux_reg(GPIONUM).modify(|_, w| w.mcu_ie().bit(on)); + self + } + fn is_input_high(&self) -> bool { + self.reg_access.read_input() & (1 << (GPIONUM % 32)) != 0 + } + fn connect_input_to_peripheral_with_options( + &mut self, + signal: InputSignal, + invert: bool, + force_via_gpio_mux: bool, + ) -> &mut Self { + let af = if force_via_gpio_mux { + GPIO_FUNCTION + } else { + let mut res = GPIO_FUNCTION; + for (i, input_signal) in self.af_input_signals.iter().enumerate() { + if let Some(input_signal) = input_signal { + if *input_signal == signal { + res = match i { + 0 => AlternateFunction::Function0, + 1 => AlternateFunction::Function1, + 2 => AlternateFunction::Function2, + 3 => AlternateFunction::Function3, + 4 => AlternateFunction::Function4, + 5 => AlternateFunction::Function5, + _ => unreachable!(), + }; + break; } - }; - - if af == AlternateFunction::$gpio_function && signal as usize > INPUT_SIGNAL_MAX as usize { - panic!("Cannot connect GPIO to this peripheral"); - } - - self.set_alternate_function(af); - - if (signal as usize) <= INPUT_SIGNAL_MAX as usize { - unsafe { &*GPIO::PTR }.func_in_sel_cfg[signal as usize].modify(|_, w| unsafe { - w.sel() - .set_bit() - .in_inv_sel() - .bit(invert) - .in_sel() - .bits($pin_num) - }); } - self } + res + }; + if af == GPIO_FUNCTION && signal as usize > INPUT_SIGNAL_MAX as usize { + panic!("Cannot connect GPIO to this peripheral"); + } + self.set_alternate_function(af); + if (signal as usize) <= INPUT_SIGNAL_MAX as usize { + unsafe { &*GPIO::PTR }.func_in_sel_cfg[signal as usize].modify(|_, w| unsafe { + w.sel() + .set_bit() + .in_inv_sel() + .bit(invert) + .in_sel() + .bits(GPIONUM) + }); + } + self + } - fn disconnect_input_from_peripheral(&mut self, signal: InputSignal) -> &mut Self { - // Reset this GPIO to plain GPIO - self.set_alternate_function(AlternateFunction::$gpio_function); - - unsafe { &*GPIO::PTR }.func_in_sel_cfg[signal as usize].modify(|_, w| unsafe { - w.sel().clear_bit() - }); + fn disconnect_input_from_peripheral(&mut self, signal: InputSignal) -> &mut Self { + self.set_alternate_function(GPIO_FUNCTION); - self - } - } + unsafe { &*GPIO::PTR }.func_in_sel_cfg[signal as usize].modify(|_, w| w.sel().clear_bit()); + self + } +} - impl Pin for $pxi { - fn number(&self) -> u8 { - $pin_num - } +impl Pin for GpioPin +where + RA: BankGpioRegisterAccess, + PINTYPE: PinType, +{ + fn number(&self) -> u8 { + GPIONUM + } - fn sleep_mode(&mut self, on: bool) -> &mut Self { - paste! { - unsafe { &*IO_MUX::PTR } - .$iomux_reg - .modify(|_, w| w.slp_sel().bit(on)); - } - self - } + fn sleep_mode(&mut self, on: bool) -> &mut Self { + get_io_mux_reg(GPIONUM).modify(|_, w| w.slp_sel().bit(on)); - fn set_alternate_function(&mut self, alternate: AlternateFunction) -> &mut Self { - paste! { - unsafe { &*IO_MUX::PTR } - .$iomux_reg - .modify(|_, w| unsafe { w.mcu_sel().bits(alternate as u8) }); - } - self - } + self + } - fn listen_with_options(&mut self, event: Event, - int_enable: bool, nmi_enable: bool, - wake_up_from_light_sleep: bool - ) { - if wake_up_from_light_sleep { - match event { - Event::AnyEdge | Event::RisingEdge | Event::FallingEdge => { - panic!("Edge triggering is not supported for wake-up from light sleep"); - }, - _ => {} - } - } + fn set_alternate_function(&mut self, alternate: AlternateFunction) -> &mut Self { + get_io_mux_reg(GPIONUM).modify(|_, w| unsafe { w.mcu_sel().bits(alternate as u8) }); + self + } - // a crate using this macro needs to provide gpio_intr_enable - unsafe { - (&*GPIO::PTR).pin[$pin_num].modify(|_, w| - w - .int_ena().bits(crate::gpio_intr_enable(int_enable, nmi_enable)) - .int_type().bits(event as u8) - .wakeup_enable().bit(wake_up_from_light_sleep) - ); + fn listen_with_options( + &mut self, + event: Event, + int_enable: bool, + nmi_enable: bool, + wake_up_from_light_sleep: bool, + ) { + if wake_up_from_light_sleep { + match event { + Event::AnyEdge | Event::RisingEdge | Event::FallingEdge => { + panic!("Edge triggering is not supported for wake-up from light sleep"); } + _ => {} } + } + unsafe { + (&*GPIO::PTR).pin[GPIONUM as usize].modify(|_, w| { + w.int_ena() + .bits(gpio_intr_enable(int_enable, nmi_enable)) + .int_type() + .bits(event as u8) + .wakeup_enable() + .bit(wake_up_from_light_sleep) + }); + } + } - fn unlisten(&mut self) { - unsafe { (&*GPIO::PTR).pin[$pin_num].modify(|_, w| - w.int_ena().bits(0).int_type().bits(0).int_ena().bits(0) ); - } - } + fn unlisten(&mut self) { + unsafe { + (&*GPIO::PTR).pin[GPIONUM as usize] + .modify(|_, w| w.int_ena().bits(0).int_type().bits(0).int_ena().bits(0)); + } + } - fn clear_interrupt(&mut self) { - self.write_interrupt_status_clear(1 << $bit); - } + fn clear_interrupt(&mut self) { + self.reg_access + .write_interrupt_status_clear(1 << (GPIONUM % 32)); + } - fn is_pcore_interrupt_set(&self) -> bool { - (self.pro_cpu_interrupt_status_read() & (1 << $bit)) !=0 - } + fn is_pcore_interrupt_set(&self) -> bool { + (self.pro_cpu_interrupt_status_read() & (1 << (GPIONUM % 32))) != 0 + } - fn is_pcore_non_maskable_interrupt_set(&self) -> bool { - (self.pro_cpu_nmi_status_read() & (1 << $bit)) !=0 - } + fn is_pcore_non_maskable_interrupt_set(&self) -> bool { + (self.pro_cpu_nmi_status_read() & (1 << (GPIONUM % 32))) != 0 + } - fn is_acore_interrupt_set(&self) -> bool { - (self.app_cpu_interrupt_status_read() & (1 << $bit)) !=0 - } + fn is_acore_interrupt_set(&self) -> bool { + (self.app_cpu_interrupt_status_read() & (1 << (GPIONUM % 32))) != 0 + } - fn is_acore_non_maskable_interrupt_set(&self) -> bool { - (self.app_cpu_nmi_status_read() & (1 << $bit)) !=0 - } + fn is_acore_non_maskable_interrupt_set(&self) -> bool { + (self.app_cpu_nmi_status_read() & (1 << (GPIONUM % 32))) != 0 + } - fn enable_hold(&mut self, _on: bool) { - todo!(); - } - } - }; + fn enable_hold(&mut self, _on: bool) { + todo!(); + } } -#[doc(hidden)] -#[macro_export] -macro_rules! impl_output { - ( - $gpio_function:ident, - $output_signal:ty, - $pxi:ident: - ( - $pin_num:expr, $iomux_reg:expr, $bit:expr - ) - $( ,( $( $af_signal:ident: $af:ident ),* ))? - ) => { - impl embedded_hal::digital::v2::OutputPin for $pxi> { - type Error = Infallible; - - fn set_high(&mut self) -> Result<(), Self::Error> { - self.write_output_set(1 << $bit); - Ok(()) - } - - fn set_low(&mut self) -> Result<(), Self::Error> { - self.write_output_clear(1 << $bit); - Ok(()) - } - } +impl embedded_hal::digital::v2::OutputPin + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + type Error = Infallible; + fn set_high(&mut self) -> Result<(), Self::Error> { + self.reg_access.write_output_set(1 << (GPIONUM % 32)); + Ok(()) + } + fn set_low(&mut self) -> Result<(), Self::Error> { + self.reg_access.write_output_clear(1 << (GPIONUM % 32)); + Ok(()) + } +} - impl embedded_hal::digital::v2::StatefulOutputPin for $pxi> { - fn is_set_high(&self) -> Result { - Ok(self.read_output() & (1 << $bit) != 0) - } +impl embedded_hal::digital::v2::StatefulOutputPin + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + fn is_set_high(&self) -> Result { + Ok(self.reg_access.read_output() & (1 << (GPIONUM % 32)) != 0) + } + fn is_set_low(&self) -> Result { + Ok(!self.is_set_high()?) + } +} - fn is_set_low(&self) -> Result { - Ok(!self.is_set_high()?) - } +impl embedded_hal::digital::v2::ToggleableOutputPin + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + type Error = Infallible; + fn toggle(&mut self) -> Result<(), Self::Error> { + use embedded_hal::digital::v2::{OutputPin as _, StatefulOutputPin as _}; + if self.is_set_high()? { + Ok(self.set_low()?) + } else { + Ok(self.set_high()?) } + } +} - impl embedded_hal::digital::v2::ToggleableOutputPin for $pxi> { - type Error = Infallible; - - fn toggle(&mut self) -> Result<(), Self::Error> { - use embedded_hal::digital::v2::{StatefulOutputPin as _, OutputPin as _}; - - if self.is_set_high()? { - Ok(self.set_low()?) - } else { - Ok(self.set_high()?) - } - } - } +#[cfg(feature = "eh1")] +impl embedded_hal_1::digital::ErrorType + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + type Error = Infallible; +} - #[cfg(feature = "eh1")] - impl embedded_hal_1::digital::ErrorType for $pxi> { - type Error = Infallible; - } +#[cfg(feature = "eh1")] +impl embedded_hal_1::digital::OutputPin + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + fn set_low(&mut self) -> Result<(), Self::Error> { + self.reg_access.write_output_clear(1 << (GPIONUM % 32)); + Ok(()) + } + fn set_high(&mut self) -> Result<(), Self::Error> { + self.reg_access.write_output_set(1 << (GPIONUM % 32)); + Ok(()) + } +} - #[cfg(feature = "eh1")] - impl embedded_hal_1::digital::OutputPin for $pxi> { - fn set_low(&mut self) -> Result<(), Self::Error> { - self.write_output_clear(1 << $bit); - Ok(()) - } +#[cfg(feature = "eh1")] +impl embedded_hal_1::digital::StatefulOutputPin + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + fn is_set_high(&self) -> Result { + Ok(self.reg_access.read_output() & (1 << (GPIONUM % 32)) != 0) + } + fn is_set_low(&self) -> Result { + Ok(!self.is_set_high()?) + } +} - fn set_high(&mut self) -> Result<(), Self::Error> { - self.write_output_set(1 << $bit); - Ok(()) - } +#[cfg(feature = "eh1")] +impl embedded_hal_1::digital::ToggleableOutputPin + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + fn toggle(&mut self) -> Result<(), Self::Error> { + use embedded_hal_1::digital::{OutputPin as _, StatefulOutputPin as _}; + if self.is_set_high()? { + Ok(self.set_low()?) + } else { + Ok(self.set_high()?) } + } +} - #[cfg(feature = "eh1")] - impl embedded_hal_1::digital::StatefulOutputPin for $pxi> { - fn is_set_high(&self) -> Result { - Ok(self.read_output() & (1 << $bit) != 0) - } +impl From> + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + fn from( + pin: GpioPin, + ) -> GpioPin, RA, PINTYPE, GPIONUM> { + pin.into_floating_input() + } +} - fn is_set_low(&self) -> Result { - Ok(!self.is_set_high()?) - } - } +impl From> + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + fn from( + pin: GpioPin, + ) -> GpioPin, RA, PINTYPE, GPIONUM> { + pin.into_pull_up_input() + } +} - #[cfg(feature = "eh1")] - impl embedded_hal_1::digital::ToggleableOutputPin for $pxi> { - fn toggle(&mut self) -> Result<(), Self::Error> { - use embedded_hal_1::digital::{StatefulOutputPin as _, OutputPin as _}; +impl From> + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsInputPin, +{ + fn from( + pin: GpioPin, + ) -> GpioPin, RA, PINTYPE, GPIONUM> { + pin.into_pull_down_input() + } +} - if self.is_set_high()? { - Ok(self.set_low()?) - } else { - Ok(self.set_high()?) - } - } - } +impl From> + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + fn from( + pin: GpioPin, + ) -> GpioPin, RA, PINTYPE, GPIONUM> { + pin.into_push_pull_output() + } +} - impl_from!($pxi, Input, into_floating_input); - impl_from!($pxi, Input, into_pull_up_input); - impl_from!($pxi, Input, into_pull_down_input); - impl_from!($pxi, Output, into_push_pull_output); - impl_from!($pxi, Output, into_open_drain_output); - impl_from!($pxi, Alternate, into_alternate_1); - impl_from!($pxi, Alternate, into_alternate_2); - - impl $pxi { - pub fn into_pull_up_input(self) -> $pxi> { - self.init_input(false, true); - $pxi { _mode: PhantomData } - } +impl From> + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + fn from( + pin: GpioPin, + ) -> GpioPin, RA, PINTYPE, GPIONUM> { + pin.into_open_drain_output() + } +} - pub fn into_pull_down_input(self) -> $pxi> { - self.init_input(true, false); - $pxi { _mode: PhantomData } - } +impl From> + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + fn from( + pin: GpioPin, + ) -> GpioPin, RA, PINTYPE, GPIONUM> { + pin.into_alternate_1() + } +} - fn init_output(&self, alternate: AlternateFunction, open_drain: bool) { - let gpio = unsafe { &*GPIO::PTR }; - let iomux = unsafe { &*IO_MUX::PTR }; - - self.write_out_en_set(1 << $bit); - gpio.pin[$pin_num].modify(|_, w| w.pad_driver().bit(open_drain)); - - gpio.func_out_sel_cfg[$pin_num] - .modify(|_, w| unsafe { w.out_sel().bits(OutputSignal::GPIO as OutputSignalType) }); - - paste! { - iomux.$iomux_reg.modify(|_, w| unsafe { - w.mcu_sel() - .bits(alternate as u8) - .fun_ie() - .bit(open_drain) - .fun_wpd() - .clear_bit() - .fun_wpu() - .clear_bit() - .fun_drv() - .bits(DriveStrength::I20mA as u8) - .slp_sel() - .clear_bit() - }); - } - } +impl From> + for GpioPin, RA, PINTYPE, GPIONUM> +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + fn from( + pin: GpioPin, + ) -> GpioPin, RA, PINTYPE, GPIONUM> { + pin.into_alternate_2() + } +} - pub fn into_push_pull_output(self) -> $pxi> { - self.init_output(AlternateFunction::$gpio_function, false); - $pxi { _mode: PhantomData } - } +impl GpioPin +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + fn init_output(&self, alternate: AlternateFunction, open_drain: bool) { + let gpio = unsafe { &*GPIO::PTR }; + + self.reg_access.write_out_en_set(1 << (GPIONUM % 32)); + gpio.pin[GPIONUM as usize].modify(|_, w| w.pad_driver().bit(open_drain)); + + gpio.func_out_sel_cfg[GPIONUM as usize] + .modify(|_, w| unsafe { w.out_sel().bits(OutputSignal::GPIO as OutputSignalType) }); + + get_io_mux_reg(GPIONUM).modify(|_, w| unsafe { + w.mcu_sel() + .bits(alternate as u8) + .fun_ie() + .bit(open_drain) + .fun_wpd() + .clear_bit() + .fun_wpu() + .clear_bit() + .fun_drv() + .bits(DriveStrength::I20mA as u8) + .slp_sel() + .clear_bit() + }); + } - pub fn into_open_drain_output(self) -> $pxi> { - self.init_output(AlternateFunction::$gpio_function, true); - $pxi { _mode: PhantomData } - } + pub fn into_push_pull_output(self) -> GpioPin, RA, PINTYPE, GPIONUM> { + self.init_output(GPIO_FUNCTION, false); + GpioPin { + _mode: PhantomData, + _pintype: PhantomData, + reg_access: self.reg_access, + af_input_signals: self.af_input_signals, + af_output_signals: self.af_output_signals, + } + } - pub fn into_alternate_1(self) -> $pxi> { - self.init_output(AlternateFunction::Function1, false); - $pxi { _mode: PhantomData } - } + pub fn into_open_drain_output(self) -> GpioPin, RA, PINTYPE, GPIONUM> { + self.init_output(GPIO_FUNCTION, true); + GpioPin { + _mode: PhantomData, + _pintype: PhantomData, + reg_access: self.reg_access, + af_input_signals: self.af_input_signals, + af_output_signals: self.af_output_signals, + } + } - pub fn into_alternate_2(self) -> $pxi> { - self.init_output(AlternateFunction::Function2, false); - $pxi { _mode: PhantomData } - } + pub fn into_alternate_1(self) -> GpioPin, RA, PINTYPE, GPIONUM> { + self.init_output(AlternateFunction::Function1, false); + GpioPin { + _mode: PhantomData, + _pintype: PhantomData, + reg_access: self.reg_access, + af_input_signals: self.af_input_signals, + af_output_signals: self.af_output_signals, } + } - impl OutputPin for $pxi { - fn set_to_open_drain_output(&mut self) -> &mut Self { - self.init_output(AlternateFunction::$gpio_function, true); - self - } + pub fn into_alternate_2(self) -> GpioPin, RA, PINTYPE, GPIONUM> { + self.init_output(AlternateFunction::Function2, false); + GpioPin { + _mode: PhantomData, + _pintype: PhantomData, + reg_access: self.reg_access, + af_input_signals: self.af_input_signals, + af_output_signals: self.af_output_signals, + } + } +} - fn set_to_push_pull_output(&mut self) -> &mut Self { - self.init_output(AlternateFunction::$gpio_function, false); - self - } +impl OutputPin for GpioPin +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + fn set_to_open_drain_output(&mut self) -> &mut Self { + self.init_output(GPIO_FUNCTION, true); + self + } - fn enable_output(&mut self, on: bool) -> &mut Self { - if on { - self.write_out_en_set(1 << $bit); - } else { - self.write_out_en_clear(1 << $bit); - } - self - } + fn set_to_push_pull_output(&mut self) -> &mut Self { + self.init_output(GPIO_FUNCTION, false); + self + } - fn set_output_high(&mut self, high: bool) -> &mut Self { - if high { - self.write_output_set(1 << $bit); - } else { - self.write_output_clear(1 << $bit); - } - self - } + fn enable_output(&mut self, on: bool) -> &mut Self { + if on { + self.reg_access.write_out_en_set(1 << (GPIONUM % 32)); + } else { + self.reg_access.write_out_en_clear(1 << (GPIONUM % 32)); + } + self + } - fn set_drive_strength(&mut self, strength: DriveStrength) -> &mut Self { - paste! { - unsafe { &*IO_MUX::PTR } - .$iomux_reg - .modify(|_, w| unsafe { w.fun_drv().bits(strength as u8) }); - } - self - } + fn set_output_high(&mut self, high: bool) -> &mut Self { + if high { + self.reg_access.write_output_set(1 << (GPIONUM % 32)); + } else { + self.reg_access.write_output_clear(1 << (GPIONUM % 32)); + } + self + } - fn enable_open_drain(&mut self, on: bool) -> &mut Self { - unsafe { &*GPIO::PTR }.pin[$pin_num].modify(|_, w| w.pad_driver().bit(on)); - self - } + fn set_drive_strength(&mut self, strength: DriveStrength) -> &mut Self { + get_io_mux_reg(GPIONUM).modify(|_, w| unsafe { w.fun_drv().bits(strength as u8) }); - fn internal_pull_up_in_sleep_mode(&mut self, on: bool) -> &mut Self { - paste! { - unsafe { &*IO_MUX::PTR } - .$iomux_reg - .modify(|_, w| w.mcu_wpu().bit(on)); - } - self - } + self + } - fn internal_pull_down_in_sleep_mode(&mut self, on: bool) -> &mut Self { - paste!{ - unsafe { &*IO_MUX::PTR } - .$iomux_reg - .modify(|_, w| w.mcu_wpd().bit(on)); - } - self - } + fn enable_open_drain(&mut self, on: bool) -> &mut Self { + unsafe { &*GPIO::PTR }.pin[GPIONUM as usize].modify(|_, w| w.pad_driver().bit(on)); + self + } - fn enable_output_in_sleep_mode(&mut self, on: bool) -> &mut Self { - paste! { - unsafe { &*IO_MUX::PTR } - .$iomux_reg - .modify(|_, w| w.mcu_oe().bit(on)); - } - self - } + fn internal_pull_up_in_sleep_mode(&mut self, on: bool) -> &mut Self { + get_io_mux_reg(GPIONUM).modify(|_, w| w.mcu_wpu().bit(on)); + self + } + fn internal_pull_down_in_sleep_mode(&mut self, on: bool) -> &mut Self { + get_io_mux_reg(GPIONUM).modify(|_, w| w.mcu_wpd().bit(on)); + self + } + fn enable_output_in_sleep_mode(&mut self, on: bool) -> &mut Self { + get_io_mux_reg(GPIONUM).modify(|_, w| w.mcu_oe().bit(on)); + self + } - fn connect_peripheral_to_output_with_options( - &mut self, - signal: OutputSignal, - invert: bool, - invert_enable: bool, - enable_from_gpio: bool, - force_via_gpio_mux: bool, - ) -> &mut Self { - let af = if force_via_gpio_mux { - AlternateFunction::$gpio_function - } else { - match signal { - $( $( - OutputSignal::$af_signal => AlternateFunction::$af, - )* )? - _ => AlternateFunction::$gpio_function + fn connect_peripheral_to_output_with_options( + &mut self, + signal: OutputSignal, + invert: bool, + invert_enable: bool, + enable_from_gpio: bool, + force_via_gpio_mux: bool, + ) -> &mut Self { + let af = if force_via_gpio_mux { + GPIO_FUNCTION + } else { + let mut res = GPIO_FUNCTION; + for (i, output_signal) in self.af_output_signals.iter().enumerate() { + if let Some(output_signal) = output_signal { + if *output_signal == signal { + res = match i { + 0 => AlternateFunction::Function0, + 1 => AlternateFunction::Function1, + 2 => AlternateFunction::Function2, + 3 => AlternateFunction::Function3, + 4 => AlternateFunction::Function4, + 5 => AlternateFunction::Function5, + _ => unreachable!(), + }; + break; } - }; - - if af == AlternateFunction::$gpio_function && signal as usize > OUTPUT_SIGNAL_MAX as usize { - panic!("Cannot connect this peripheral to GPIO"); } - - self.set_alternate_function(af); - - let clipped_signal = if signal as usize <= OUTPUT_SIGNAL_MAX as usize { signal as OutputSignalType } else { OUTPUT_SIGNAL_MAX }; - - unsafe { &*GPIO::PTR }.func_out_sel_cfg[$pin_num].modify(|_, w| unsafe { - w - .out_sel().bits(clipped_signal) - .inv_sel().bit(invert) - .oen_sel().bit(enable_from_gpio) - .oen_inv_sel().bit(invert_enable) - }); - - self } + res + }; + if af == GPIO_FUNCTION && signal as usize > OUTPUT_SIGNAL_MAX as usize { + panic!("Cannot connect this peripheral to GPIO"); + } + self.set_alternate_function(af); + let clipped_signal = if signal as usize <= OUTPUT_SIGNAL_MAX as usize { + signal as OutputSignalType + } else { + OUTPUT_SIGNAL_MAX + }; + unsafe { &*GPIO::PTR }.func_out_sel_cfg[GPIONUM as usize].modify(|_, w| unsafe { + w.out_sel() + .bits(clipped_signal) + .inv_sel() + .bit(invert) + .oen_sel() + .bit(enable_from_gpio) + .oen_inv_sel() + .bit(invert_enable) + }); + self + } - fn disconnect_peripheral_from_output( - &mut self, - ) -> &mut Self { - // Reset this GPIO to plain GPIO - self.set_alternate_function(AlternateFunction::$gpio_function); - - unsafe { &*GPIO::PTR }.func_out_sel_cfg[$pin_num].modify(|_, w| unsafe { - w.out_sel().bits(OutputSignal::GPIO as OutputSignalType) - }); - - self - } + fn disconnect_peripheral_from_output(&mut self) -> &mut Self { + self.set_alternate_function(GPIO_FUNCTION); + unsafe { &*GPIO::PTR }.func_out_sel_cfg[GPIONUM as usize] + .modify(|_, w| unsafe { w.out_sel().bits(OutputSignal::GPIO as OutputSignalType) }); + self + } - fn internal_pull_up(&mut self, on: bool) -> &mut Self { - paste!{ - unsafe { &*IO_MUX::PTR }.$iomux_reg.modify(|_, w| w.fun_wpu().bit(on)); - } - self - } + fn internal_pull_up(&mut self, on: bool) -> &mut Self { + get_io_mux_reg(GPIONUM).modify(|_, w| w.fun_wpu().bit(on)); + self + } + fn internal_pull_down(&mut self, on: bool) -> &mut Self { + get_io_mux_reg(GPIONUM).modify(|_, w| w.fun_wpd().bit(on)); + self + } +} - fn internal_pull_down(&mut self, on: bool) -> &mut Self { - paste! { - unsafe { &*IO_MUX::PTR }.$iomux_reg.modify(|_, w| w.fun_wpd().bit(on)); - } - self - } +impl GpioPin +where + RA: BankGpioRegisterAccess, + PINTYPE: IsOutputPin, +{ + pub fn into_analog(self) -> GpioPin { + types::internal_into_analog(GPIONUM); + + GpioPin { + _mode: PhantomData, + _pintype: PhantomData, + reg_access: self.reg_access, + af_input_signals: self.af_input_signals, + af_output_signals: self.af_output_signals, } - }; + } } -#[doc(hidden)] -#[macro_export] -macro_rules! impl_output_wrap { - ( - $gpio_function:ident, - $pxi:ident, $pin_num:expr, $iomux_reg:expr, IO, - $( ,( $( $af_output_signal:ident : $af_output:ident ),* ))? - ) => { - impl_output!( - $gpio_function, - OutputSignal, - $pxi: - ( - $pin_num, $iomux_reg, $pin_num % 32 - ) - $( ,( $( $af_output_signal: $af_output ),* ) )? - ); - }; - - // if it's not an output enabled pin just emit no code here - ( - $gpio_function:ident, - $pxi:ident, $pin_num:expr, $iomux_reg:expr, $type:ident, - $( ,( $( $af_output_signal:ident : $af_output:ident ),* ))? - ) => {}; +pub struct IO { + _io_mux: IO_MUX, + pub pins: types::Pins, +} +impl IO { + pub fn new(gpio: GPIO, io_mux: IO_MUX) -> Self { + let pins = gpio.split(); + let io = IO { + _io_mux: io_mux, + pins, + }; + io + } } -#[doc(hidden)] -#[macro_export] -macro_rules! impl_gpio_register_access { - (Bank0, $pxi:ident) => { - #[doc(hidden)] - impl GpioRegisters for $pxi {} - }; +// while ESP32-S3 is multicore it is more like single core in terms of GPIO +// interrupts +#[cfg(esp32s3)] +impl + InterruptStatusRegisters + for GpioPin +where + RA: BankGpioRegisterAccess, + PINTYPE: PinType, +{ +} - (Bank1, $pxi:ident) => { - #[doc(hidden)] - impl GpioRegisters for $pxi {} - }; +#[cfg(esp32)] +impl + InterruptStatusRegisters + for GpioPin +where + RA: BankGpioRegisterAccess, + PINTYPE: PinType, +{ } -#[doc(hidden)] -#[macro_export] -macro_rules! impl_interrupt_status_register_access { - (SingleCore, $pxi:ident) => { - #[doc(hidden)] - impl InterruptStatusRegisters for $pxi {} - }; +#[cfg(esp32c3)] +impl + InterruptStatusRegisters + for GpioPin +where + RA: BankGpioRegisterAccess, + PINTYPE: PinType, +{ +} - (DualCore, $pxi:ident) => { - #[doc(hidden)] - impl InterruptStatusRegisters for $pxi {} - }; +#[cfg(esp32s2)] +impl + InterruptStatusRegisters + for GpioPin +where + RA: BankGpioRegisterAccess, + PINTYPE: PinType, +{ } -#[doc(hidden)] -#[macro_export] -macro_rules! impl_from { - ($pxi:ident, $mode:ty, $function:ident) => { - impl From<$pxi> for $pxi<$mode> { - fn from(pin: $pxi) -> $pxi<$mode> { - pin.$function() - } - } - }; +#[cfg(esp32c2)] +impl + InterruptStatusRegisters + for GpioPin +where + RA: BankGpioRegisterAccess, + PINTYPE: PinType, +{ } #[doc(hidden)] #[macro_export] macro_rules! gpio { ( - $gpio_function:ident, - $cores:ident, $( - $pxi:ident: - ( - $pname:ident, $pin_num:literal, $iomux_reg:expr, $type:ident, - $rtc:tt, $bank:ident, $errata36:ident - ), - $( - ( $( $af_input_signal:ident: $af_input:ident ),* ), - $( ( $( $af_output_signal:ident: $af_output:ident ),* ), )? - )? + ($gpionum:literal, $bank:literal, $type:ident + $( + ( $( $af_input_num:literal => $af_input_signal:ident )* ) + ( $( $af_output_num:literal => $af_output_signal:ident )* ) + )? + ) )+ ) => { - use core::{convert::Infallible, marker::PhantomData}; - - use crate::pac::{GPIO, IO_MUX}; - - pub struct IO { - io_mux: IO_MUX, - pub pins: Pins, - } - - impl IO { - pub fn new(gpio: GPIO, io_mux: IO_MUX) -> Self { - let pins = gpio.split(); - let io = IO { io_mux, pins }; - - io - } - } - + #[doc(hidden)] pub trait GpioExt { type Parts; - fn split(self) -> Self::Parts; } - impl GpioExt for GPIO { - type Parts = Pins; - - fn split(self) -> Self::Parts { - Pins { - $( - $pname: $pxi { _mode: PhantomData }, - )+ + paste!{ + impl GpioExt for GPIO { + type Parts = Pins; + fn split(self) -> Self::Parts { + Pins { + $( + [< gpio $gpionum >]: { + #[allow(unused_mut)] + let mut input_signals = [None,None,None,None,None,None]; + + #[allow(unused_mut)] + let mut output_signals = [None,None,None,None,None,None]; + + $( + $( + input_signals[ $af_input_num ] = Some( InputSignal::$af_input_signal ); + )* + + $( + output_signals[ $af_output_num ] = Some( OutputSignal::$af_output_signal ); + )* + )? + + GpioPin { + _mode: PhantomData, + _pintype: PhantomData, + reg_access: [< Bank $bank GpioRegisterAccess >] {}, + af_input_signals: input_signals, + af_output_signals: output_signals, + } + }, + )+ + } } } - } - pub struct Pins { + pub struct Pins { + $( + pub [< gpio $gpionum >] : GpioPin], [< $type PinType >], $gpionum>, + )+ + } + $( - pub $pname: $pxi, + pub type [] = GpioPin], [< $type PinType >], $gpionum>; )+ } - - $( - pub struct $pxi { - _mode: PhantomData, - } - - impl_gpio_register_access!($bank, $pxi); - - impl_interrupt_status_register_access!($cores, $pxi); - - impl_input!( - $gpio_function, - InputSignal, - $pxi: - ( - $pin_num, $iomux_reg, $pin_num % 32, - $errata36 - ) - $( ,( $( $af_input_signal: $af_input ),* ) )? - ); - - impl_output_wrap!( - $gpio_function, $pxi, $pin_num, $iomux_reg, $type, - $($( ,( $( $af_output_signal: $af_output ),* ) )? )? - ); - )+ }; } +// Following code enables `into_analog` + #[doc(hidden)] pub fn enable_iomux_clk_gate() { #[cfg(esp32s2)] @@ -1207,63 +1366,121 @@ pub fn enable_iomux_clk_gate() { } } -#[cfg(not(any(esp32c2, esp32c3)))] +#[cfg(not(any(esp32c2, esp32c3, esp32s2)))] #[doc(hidden)] #[macro_export] macro_rules! analog { ( - $($pxi:ident: ($pin_num:expr, $pin_reg:expr, $hold: ident, $mux_sel:ident, - $fun_sel:ident, $fun_ie:ident, $slp_ie:ident, $slp_sel:ident - $(, $rue:ident, $rde:ident, $drv:ident, $slp_oe:ident)?),)+ - ) => { $( - impl $pxi { - pub fn into_analog(mut self) -> $pxi { - $( - use crate::pac::RTCIO; - let rtcio = unsafe{ &*RTCIO::ptr() }; - - $crate::gpio::enable_iomux_clk_gate(); - + ( + $pin_num:expr, $rtc_pin:expr, $pin_reg:expr, + $mux_sel:ident, $fun_sel:ident, $fun_ie:ident $(, $rue:ident, $rde:ident)? + ) + )+ + ) => { + pub(crate) fn internal_into_analog(pin: u8) { + use crate::pac::RTCIO; + let rtcio = unsafe{ &*RTCIO::ptr() }; + $crate::gpio::enable_iomux_clk_gate(); + + match pin { + $( + $pin_num => { // disable input paste! { rtcio.$pin_reg.modify(|_,w| w.$fun_ie().bit(false)); + + // disable output + rtcio.enable_w1tc.write(|w| unsafe { w.enable_w1tc().bits(1 << $rtc_pin) }); + + // disable open drain + rtcio.pin[$rtc_pin].modify(|_,w| w.pad_driver().bit(false)); + + rtcio.$pin_reg.modify(|_,w| { + w.$fun_ie().clear_bit(); + + // Connect pin to analog / RTC module instead of standard GPIO + w.$mux_sel().set_bit(); + + // Select function "RTC function 1" (GPIO) for analog use + unsafe { w.$fun_sel().bits(0b00) } + }); + + // Disable pull-up and pull-down resistors on the pin, if it has them + $( + rtcio.$pin_reg.modify(|_,w| { + w + .$rue().bit(false) + .$rde().bit(false) + }); + )? + } + } + )+ + _ => unreachable!(), + } + } + } +} + +#[cfg(esp32s2)] +#[doc(hidden)] +#[macro_export] +macro_rules! analog { + ( + $( + ( + $pin_num:expr, $rtc_pin:expr, $pin_reg:expr, + $mux_sel:ident, $fun_sel:ident, $fun_ie:ident $(, $rue:ident, $rde:ident)? + ) + )+ + ) => { + pub(crate) fn internal_into_analog(pin: u8) { + use crate::pac::RTCIO; + let rtcio = unsafe{ &*RTCIO::ptr() }; + $crate::gpio::enable_iomux_clk_gate(); + + match pin { + $( + $pin_num => { + + paste!{ + use $crate::gpio::types::[< esp32s2_get_rtc_pad_ $pin_reg>]; + let rtc_pad = [< esp32s2_get_rtc_pad_ $pin_reg>](); } + // disable input + rtc_pad.modify(|_,w| w.$fun_ie().bit(false)); + // disable output - rtcio.enable_w1tc.write(|w| unsafe { w.enable_w1tc().bits(1 << $pin_num) }); + rtcio.enable_w1tc.write(|w| unsafe { w.enable_w1tc().bits(1 << $rtc_pin) }); // disable open drain - rtcio.pin[$pin_num].modify(|_,w| w.pad_driver().bit(false)); + rtcio.pin[$rtc_pin].modify(|_,w| w.pad_driver().bit(false)); - paste! { - rtcio.$pin_reg.modify(|_,w| { - w.$fun_ie().clear_bit(); + rtc_pad.modify(|_,w| { + w.$fun_ie().clear_bit(); - // Connect pin to analog / RTC module instead of standard GPIO - w.$mux_sel().set_bit(); + // Connect pin to analog / RTC module instead of standard GPIO + w.$mux_sel().set_bit(); - // Select function "RTC function 1" (GPIO) for analog use - unsafe { w.$fun_sel().bits(0b00) } - }); - } + // Select function "RTC function 1" (GPIO) for analog use + unsafe { w.$fun_sel().bits(0b00) } + }); // Disable pull-up and pull-down resistors on the pin, if it has them - paste! { - rtcio.$pin_reg.modify(|_,w| { + $( + rtc_pad.modify(|_,w| { w .$rue().bit(false) .$rde().bit(false) }); - } - )? - - $pxi { _mode: PhantomData } - } + )? + } + )+ + _ => unreachable!(), } - - impl_from!($pxi, Analog, into_analog); - )+ + } } } @@ -1272,44 +1489,37 @@ macro_rules! analog { #[macro_export] macro_rules! analog { ( - $($pxi:ident => $pin_num:literal)+ + $($pin_num:literal)+ ) => { - $( - impl $pxi { - pub fn into_analog(mut self) -> $pxi { - use crate::pac::IO_MUX; - use crate::pac::GPIO; - - let io_mux = unsafe{ &*IO_MUX::PTR }; - let gpio = unsafe{ &*GPIO::PTR }; - - io_mux.gpio[$pin_num].modify(|_,w| unsafe { - w.mcu_sel().bits(1) - .fun_ie().clear_bit() - .fun_wpu().clear_bit() - .fun_wpd().clear_bit() - }); - - gpio.enable_w1tc.write(|w| unsafe { w.bits(1 << $pin_num) }); - - $pxi { _mode: PhantomData } - } + pub(crate) fn internal_into_analog(pin: u8) { + use crate::pac::IO_MUX; + use crate::pac::GPIO; + + let io_mux = unsafe{ &*IO_MUX::PTR }; + let gpio = unsafe{ &*GPIO::PTR }; + + match pin { + $( + $pin_num => { + io_mux.gpio[$pin_num].modify(|_,w| unsafe { + w.mcu_sel().bits(1) + .fun_ie().clear_bit() + .fun_wpu().clear_bit() + .fun_wpd().clear_bit() + }); + + gpio.enable_w1tc.write(|w| unsafe { w.bits(1 << $pin_num) }); + } + )+ + _ => unreachable!() } - impl_from!($pxi, Analog, into_analog); - )+ + } } } -pub use analog; -pub use gpio; -pub use impl_errata36; -pub use impl_from; -pub use impl_gpio_register_access; -pub use impl_input; -pub use impl_interrupt_status_register_access; -pub use impl_output; -pub use impl_output_wrap; +pub(crate) use analog; +pub(crate) use gpio; pub use self::types::{InputSignal, OutputSignal}; use self::types::{ONE_INPUT, ZERO_INPUT}; diff --git a/esp-hal-common/src/gpio/esp32.rs b/esp-hal-common/src/gpio/esp32.rs index 00c84cc2b4d..2bf6a174402 100644 --- a/esp-hal-common/src/gpio/esp32.rs +++ b/esp-hal-common/src/gpio/esp32.rs @@ -1,3 +1,18 @@ +use paste::paste; + +use crate::{ + gpio::PhantomData, + pac::GPIO, + AlternateFunction, + Bank0GpioRegisterAccess, + Bank1GpioRegisterAccess, + GpioPin, + InputOnlyAnalogPinType, + InputOutputAnalogPinType, + InputOutputPinType, + Unknown, +}; + pub type OutputSignalType = u16; pub const OUTPUT_SIGNAL_MAX: u16 = 548; pub const INPUT_SIGNAL_MAX: u16 = 539; @@ -5,6 +20,61 @@ pub const INPUT_SIGNAL_MAX: u16 = 539; pub const ONE_INPUT: u8 = 0x38; pub const ZERO_INPUT: u8 = 0x30; +pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function2; + +pub(crate) fn get_io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO0 { + unsafe { + let iomux = &*crate::pac::IO_MUX::PTR; + + match gpio_num { + 0 => core::mem::transmute(&(iomux.gpio0)), + 1 => core::mem::transmute(&(iomux.gpio1)), + 2 => core::mem::transmute(&(iomux.gpio2)), + 3 => core::mem::transmute(&(iomux.gpio3)), + 4 => core::mem::transmute(&(iomux.gpio4)), + 5 => core::mem::transmute(&(iomux.gpio5)), + 6 => core::mem::transmute(&(iomux.gpio6)), + 7 => core::mem::transmute(&(iomux.gpio7)), + 8 => core::mem::transmute(&(iomux.gpio8)), + 9 => core::mem::transmute(&(iomux.gpio9)), + 10 => core::mem::transmute(&(iomux.gpio10)), + 11 => core::mem::transmute(&(iomux.gpio11)), + 12 => core::mem::transmute(&(iomux.gpio12)), + 13 => core::mem::transmute(&(iomux.gpio13)), + 14 => core::mem::transmute(&(iomux.gpio14)), + 15 => core::mem::transmute(&(iomux.gpio15)), + 16 => core::mem::transmute(&(iomux.gpio16)), + 17 => core::mem::transmute(&(iomux.gpio17)), + 18 => core::mem::transmute(&(iomux.gpio18)), + 19 => core::mem::transmute(&(iomux.gpio19)), + 20 => core::mem::transmute(&(iomux.gpio20)), + 21 => core::mem::transmute(&(iomux.gpio21)), + 22 => core::mem::transmute(&(iomux.gpio22)), + 23 => core::mem::transmute(&(iomux.gpio23)), + 24 => core::mem::transmute(&(iomux.gpio24)), + 25 => core::mem::transmute(&(iomux.gpio25)), + 26 => core::mem::transmute(&(iomux.gpio26)), + 27 => core::mem::transmute(&(iomux.gpio27)), + 32 => core::mem::transmute(&(iomux.gpio32)), + 33 => core::mem::transmute(&(iomux.gpio33)), + 34 => core::mem::transmute(&(iomux.gpio34)), + 35 => core::mem::transmute(&(iomux.gpio35)), + 36 => core::mem::transmute(&(iomux.gpio36)), + 37 => core::mem::transmute(&(iomux.gpio37)), + 38 => core::mem::transmute(&(iomux.gpio38)), + 39 => core::mem::transmute(&(iomux.gpio39)), + _ => panic!(), + } + } +} + +pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { + int_enable as u8 + | ((nmi_enable as u8) << 1) + | (int_enable as u8) << 2 + | ((nmi_enable as u8) << 3) +} + /// Peripheral input signals for the GPIO mux #[allow(non_camel_case_types)] #[derive(PartialEq, Copy, Clone)] @@ -497,3 +567,148 @@ pub enum OutputSignal { MTDO, } + +pub(crate) fn errata36(pin_num: u8, pull_up: bool, pull_down: bool) { + use crate::pac::RTCIO; + let rtcio = unsafe { &*RTCIO::PTR }; + + match pin_num { + 0 => { + rtcio + .touch_pad1 + .modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) }); + } + 2 => { + rtcio + .touch_pad2 + .modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) }); + } + 4 => { + rtcio + .touch_pad0 + .modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) }); + } + 12 => { + rtcio + .touch_pad5 + .modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) }); + } + 13 => { + rtcio + .touch_pad4 + .modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) }); + } + 14 => { + rtcio + .touch_pad6 + .modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) }); + } + 15 => { + rtcio + .touch_pad3 + .modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) }); + } + 25 => { + rtcio.pad_dac1.modify(|r, w| unsafe { + w.bits(r.bits()) + .pdac1_rue() + .bit(pull_up) + .pdac1_rde() + .bit(pull_down) + }); + } + 26 => { + rtcio.pad_dac2.modify(|r, w| unsafe { + w.bits(r.bits()) + .pdac2_rue() + .bit(pull_up) + .pdac2_rde() + .bit(pull_down) + }); + } + 27 => { + rtcio + .touch_pad7 + .modify(|r, w| unsafe { w.bits(r.bits()).rue().bit(pull_up).rde().bit(pull_down) }); + } + 32 => { + rtcio.xtal_32k_pad.modify(|r, w| unsafe { + w.bits(r.bits()) + .x32n_rue() + .bit(pull_up) + .x32n_rde() + .bit(pull_down) + }); + } + 33 => { + rtcio.xtal_32k_pad.modify(|r, w| unsafe { + w.bits(r.bits()) + .x32p_rue() + .bit(pull_up) + .x32p_rde() + .bit(pull_down) + }); + } + _ => (), + } +} + +crate::gpio::gpio! { + (0, 0, InputOutputAnalog (5 => EMAC_TX_CLK) (1 => CLK_OUT1)) + (1, 0, InputOutput (5 => EMAC_RXD2) (0 => U0TXD 1 => CLK_OUT3)) + (2, 0, InputOutputAnalog (1 => HSPIWP 3 => HS2_DATA0 4 => SD_DATA0) (3 => HS2_DATA0 4 => SD_DATA0)) + (3, 0, InputOutput (0 => U0RXD) (1 => CLK_OUT2)) + (4, 0, InputOutput (1 => HSPIHD 3 => HS2_DATA1 4 => SD_DATA1 5 => EMAC_TX_ER) (3 => HS2_DATA1 4 => SD_DATA1)) + (5, 0, InputOutput (1 => VSPICS0 3 => HS1_DATA6 5 => EMAC_RX_CLK) (3 => HS1_DATA6)) + (6, 0, InputOutput (4 => U1CTS) (0 => SD_CLK 1 => SPICLK 3 => HS1_CLK)) + (7, 0, InputOutput (0 => SD_DATA0 1 => SPIQ 3 => HS1_DATA0) (0 => SD_DATA0 1 => SPIQ 3 => HS1_DATA0 4 => U2RTS)) + (8, 0, InputOutput (0 => SD_DATA1 1 => SPID 3 => HS1_DATA1 4 => U2CTS) (0 => SD_DATA1 1 => SPID 3 => HS1_DATA1)) + (9, 0, InputOutput (0 => SD_DATA2 1 => SPIHD 3 => HS1_DATA2 4 => U1RXD) (0 => SD_DATA2 1 => SPIHD 3 => HS1_DATA2)) + (10, 0, InputOutput ( 0 => SD_DATA3 1 => SPIWP 3 => HS1_DATA3) (0 => SD_DATA3 1 => SPIWP 3 => HS1_DATA3 4 => U1TXD)) + (11, 0, InputOutput ( 1 => SPICS0) (0 => SD_CMD 1 => SPICS0 3 => HS1_CMD 4 => U1RTS)) + (12, 0, InputOutputAnalog (0 => MTDI 1 => HSPIQ 3 => HS2_DATA2 4 => SD_DATA2) (1 => HSPIQ 3 => HS2_DATA2 4 => SD_DATA2 5 => EMAC_TXD3)) + (13, 0, InputOutputAnalog (0 => MTCK 1 => HSPID 3 => HS2_DATA3 4 => SD_DATA3) (1 => HSPID 3 => HS2_DATA3 4 => SD_DATA3 5 => EMAC_RX_ER)) + (14, 0, InputOutputAnalog (0 => MTMS 1 => HSPICLK) (1 => HSPICLK 3 => HS2_CLK 4 => SD_CLK 5 => EMAC_TXD2)) + (15, 0, InputOutputAnalog (1 => HSPICS0 5 => EMAC_RXD3) (0 => MTDO 1 => HSPICS0 3 => HS2_CMD 4 => SD_CMD)) + (16, 0, InputOutput (3 => HS1_DATA4 4 => U2RXD) (3 => HS1_DATA4 5 => EMAC_CLK_OUT)) + (17, 0, InputOutput (3 => HS1_DATA5) (3 => HS1_DATA5 4 => U2TXD 5 => EMAC_CLK_180)) + (18, 0, InputOutput (1 => VSPICLK 3 => HS1_DATA7) (1 => VSPICLK 3 => HS1_DATA7)) + (19, 0, InputOutput (1 => VSPIQ 3 => U0CTS) (1 => VSPIQ 5 => EMAC_TXD0)) + (20, 0, InputOutput) + (21, 0, InputOutput (1 => VSPIHD) (1 => VSPIHD 5 => EMAC_TX_EN)) + (22, 0, InputOutput (1 => VSPIWP) (1 => VSPIWP 3 => U0RTS 5 => EMAC_TXD1)) + (23, 0, InputOutput (1 => VSPID) (1 => VSPID 3 => HS1_STROBE)) + (24, 0, InputOutput) + (25, 0, InputOutputAnalog (5 => EMAC_RXD0) ()) + (26, 0, InputOutputAnalog (5 => EMAC_RXD1) ()) + (27, 0, InputOutputAnalog (5 => EMAC_RX_DV) ()) + (32, 1, InputOutputAnalog) + (33, 1, InputOutputAnalog) + (34, 1, InputOnlyAnalog) + (35, 1, InputOnlyAnalog) + (36, 1, InputOnlyAnalog) + (37, 1, InputOnlyAnalog) + (38, 1, InputOnlyAnalog) + (39, 1, InputOnlyAnalog) +} + +crate::gpio::analog! { + (36, 0, sensor_pads, sense1_mux_sel, sense1_fun_sel, sense1_fun_ie) + (37, 1, sensor_pads, sense2_mux_sel, sense2_fun_sel, sense2_fun_ie) + (38, 2, sensor_pads, sense3_mux_sel, sense3_fun_sel, sense3_fun_ie) + (39, 3, sensor_pads, sense4_mux_sel, sense4_fun_sel, sense4_fun_ie) + (34, 4, adc_pad, adc1_mux_sel, adc1_fun_sel, adc1_fun_ie) + (35, 5, adc_pad, adc2_mux_sel, adc2_fun_sel, adc1_fun_ie) + (25, 6, pad_dac1, pdac1_mux_sel, pdac1_fun_sel, pdac1_fun_ie, pdac1_rue, pdac1_rde) + (26, 7, pad_dac2, pdac2_mux_sel, pdac2_fun_sel, pdac2_fun_ie, pdac2_rue, pdac2_rde) + (33, 8, xtal_32k_pad, x32n_mux_sel, x32n_fun_sel, x32n_fun_ie, x32n_rue, x32n_rde ) + (32, 9, xtal_32k_pad, x32p_mux_sel, x32p_fun_sel, x32p_fun_ie, x32p_rue, x32p_rde ) + (4, 10, touch_pad0, mux_sel, fun_sel, fun_ie, rue, rde ) + (0, 11, touch_pad1, mux_sel, fun_sel, fun_ie, rue, rde ) + (2, 12, touch_pad2, mux_sel, fun_sel, fun_ie, rue, rde ) + (15, 13, touch_pad3, mux_sel, fun_sel, fun_ie, rue, rde ) + (13, 14, touch_pad4, mux_sel, fun_sel, fun_ie, rue, rde ) + (12, 15, touch_pad5, mux_sel, fun_sel, fun_ie, rue, rde ) + (14, 16, touch_pad6, mux_sel, fun_sel, fun_ie, rue, rde ) + (27, 17, touch_pad7, mux_sel, fun_sel, fun_ie, rue, rde ) +} diff --git a/esp-hal-common/src/gpio/esp32c2.rs b/esp-hal-common/src/gpio/esp32c2.rs index 4b4305ac1ae..745572000e5 100644 --- a/esp-hal-common/src/gpio/esp32c2.rs +++ b/esp-hal-common/src/gpio/esp32c2.rs @@ -1,3 +1,16 @@ +use paste::paste; + +use crate::{ + gpio::PhantomData, + pac::GPIO, + AlternateFunction, + Bank0GpioRegisterAccess, + GpioPin, + InputOutputAnalogPinType, + InputOutputPinType, + Unknown, +}; + pub type OutputSignalType = u8; pub const OUTPUT_SIGNAL_MAX: u8 = 128; pub const INPUT_SIGNAL_MAX: u8 = 100; @@ -5,6 +18,16 @@ pub const INPUT_SIGNAL_MAX: u8 = 100; pub const ONE_INPUT: u8 = 0x1e; pub const ZERO_INPUT: u8 = 0x1f; +pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1; + +pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO { + unsafe { &(&*crate::pac::IO_MUX::PTR).gpio[gpio_num as usize] } +} + +pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { + int_enable as u8 | ((nmi_enable as u8) << 1) +} + /// Peripheral input signals for the GPIO mux #[allow(non_camel_case_types)] #[derive(Clone, Copy, PartialEq)] @@ -111,3 +134,28 @@ pub enum OutputSignal { CLK_OUT3 = 125, GPIO = 128, } + +crate::gpio::gpio! { + (0, 0, InputOutputAnalog) + (1, 0, InputOutputAnalog) + (2, 0, InputOutputAnalog (2 => FSPIQ) (2 => FSPIQ)) + (3, 0, InputOutputAnalog) + (4, 0, InputOutputAnalog (2 => FSPIHD) (2 => FSPIHD)) + (5, 0, InputOutput (2 => FSPIWP) (2 => FSPIWP)) + (6, 0, InputOutput (2 => FSPICLK) (2 => FSPICLK_MUX)) + (7, 0, InputOutput (2 => FSPID) (2 => FSPID)) + (8, 0, InputOutput) + (9, 0, InputOutput) + (10, 0, InputOutput (2 => FSPICS0) (2 => FSPICS0)) + (18, 0, InputOutput) + (19, 0, InputOutput) + (20, 0, InputOutput (0 => U0RXD) ()) +} + +crate::gpio::analog! { + 0 + 1 + 2 + 3 + 4 +} diff --git a/esp-hal-common/src/gpio/esp32c3.rs b/esp-hal-common/src/gpio/esp32c3.rs index 216e4706f00..93b84f249ad 100644 --- a/esp-hal-common/src/gpio/esp32c3.rs +++ b/esp-hal-common/src/gpio/esp32c3.rs @@ -1,3 +1,16 @@ +use paste::paste; + +use crate::{ + gpio::PhantomData, + pac::GPIO, + AlternateFunction, + Bank0GpioRegisterAccess, + GpioPin, + InputOutputAnalogPinType, + InputOutputPinType, + Unknown, +}; + pub type OutputSignalType = u8; pub const OUTPUT_SIGNAL_MAX: u8 = 128; pub const INPUT_SIGNAL_MAX: u8 = 100; @@ -5,6 +18,16 @@ pub const INPUT_SIGNAL_MAX: u8 = 100; pub const ONE_INPUT: u8 = 0x1e; pub const ZERO_INPUT: u8 = 0x1f; +pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1; + +pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO { + unsafe { &(&*crate::pac::IO_MUX::PTR).gpio[gpio_num as usize] } +} + +pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { + int_enable as u8 | ((nmi_enable as u8) << 1) +} + /// Peripheral input signals for the GPIO mux #[allow(non_camel_case_types)] #[derive(Clone, Copy, PartialEq)] @@ -137,3 +160,37 @@ pub enum OutputSignal { USB_JTAG_TRST = 127, GPIO = 128, } + +crate::gpio::gpio! { + (0, 0, InputOutputAnalog) + (1, 0, InputOutputAnalog) + (2, 0, InputOutputAnalog (2 => FSPIQ) (2 => FSPIQ)) + (3, 0, InputOutputAnalog) + (4, 0, InputOutputAnalog (2 => FSPIHD) (0 => USB_JTAG_TMS 2 => FSPIHD)) + (5, 0, InputOutputAnalog (2 => FSPIWP) (0 => USB_JTAG_TDI 2 => FSPIWP)) + (6, 0, InputOutput (2 => FSPICLK) (0 => USB_JTAG_TCK 2 => FSPICLK_MUX)) + (7, 0, InputOutput (2 => FSPID) (0 => USB_JTAG_TDO 2 => FSPID)) + (8, 0, InputOutput) + (9, 0, InputOutput) + (10, 0, InputOutput (2 => FSPICS0) (2 => FSPICS0)) + (11, 0, InputOutput) + (12, 0, InputOutput (0 => SPIHD) (0 => SPIHD)) + (13, 0, InputOutput (0 => SPIWP) (0 => SPIWP)) + (14, 0, InputOutput () (0 => SPICS0)) + (15, 0, InputOutput () (0 => SPICLK_MUX)) + (16, 0, InputOutput (0 => SPID) (0 => SPID)) + (17, 0, InputOutput (0 => SPIQ) (0 => SPIQ)) + (18, 0, InputOutput) + (19, 0, InputOutput) + (20, 0, InputOutput (0 => U0RXD) ()) + (21, 0, InputOutput () (0 => U0TXD)) +} + +crate::gpio::analog! { + 0 + 1 + 2 + 3 + 4 + 5 +} diff --git a/esp-hal-common/src/gpio/esp32s2.rs b/esp-hal-common/src/gpio/esp32s2.rs index 4e11908ba72..90fb87d1dac 100644 --- a/esp-hal-common/src/gpio/esp32s2.rs +++ b/esp-hal-common/src/gpio/esp32s2.rs @@ -1,3 +1,17 @@ +use paste::paste; + +use crate::{ + gpio::PhantomData, + pac::GPIO, + AlternateFunction, + Bank0GpioRegisterAccess, + Bank1GpioRegisterAccess, + GpioPin, + InputOutputAnalogPinType, + InputOutputPinType, + Unknown, +}; + pub type OutputSignalType = u16; pub const OUTPUT_SIGNAL_MAX: u16 = 256; pub const INPUT_SIGNAL_MAX: u16 = 204; @@ -5,6 +19,64 @@ pub const INPUT_SIGNAL_MAX: u16 = 204; pub const ONE_INPUT: u8 = 0x38; pub const ZERO_INPUT: u8 = 0x3c; +pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1; + +pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO0 { + unsafe { + let iomux = &*crate::pac::IO_MUX::PTR; + + match gpio_num { + 0 => core::mem::transmute(&(iomux.gpio0)), + 1 => core::mem::transmute(&(iomux.gpio1)), + 2 => core::mem::transmute(&(iomux.gpio2)), + 3 => core::mem::transmute(&(iomux.gpio3)), + 4 => core::mem::transmute(&(iomux.gpio4)), + 5 => core::mem::transmute(&(iomux.gpio5)), + 6 => core::mem::transmute(&(iomux.gpio6)), + 7 => core::mem::transmute(&(iomux.gpio7)), + 8 => core::mem::transmute(&(iomux.gpio8)), + 9 => core::mem::transmute(&(iomux.gpio9)), + 10 => core::mem::transmute(&(iomux.gpio10)), + 11 => core::mem::transmute(&(iomux.gpio11)), + 12 => core::mem::transmute(&(iomux.gpio12)), + 13 => core::mem::transmute(&(iomux.gpio13)), + 14 => core::mem::transmute(&(iomux.gpio14)), + 15 => core::mem::transmute(&(iomux.gpio15)), + 16 => core::mem::transmute(&(iomux.gpio16)), + 17 => core::mem::transmute(&(iomux.gpio17)), + 18 => core::mem::transmute(&(iomux.gpio18)), + 19 => core::mem::transmute(&(iomux.gpio19)), + 20 => core::mem::transmute(&(iomux.gpio20)), + 21 => core::mem::transmute(&(iomux.gpio21)), + 26 => core::mem::transmute(&(iomux.gpio26)), + 27 => core::mem::transmute(&(iomux.gpio27)), + 32 => core::mem::transmute(&(iomux.gpio32)), + 33 => core::mem::transmute(&(iomux.gpio33)), + 34 => core::mem::transmute(&(iomux.gpio34)), + 35 => core::mem::transmute(&(iomux.gpio35)), + 36 => core::mem::transmute(&(iomux.gpio36)), + 37 => core::mem::transmute(&(iomux.gpio37)), + 38 => core::mem::transmute(&(iomux.gpio38)), + 39 => core::mem::transmute(&(iomux.gpio39)), + 40 => core::mem::transmute(&(iomux.gpio40)), + 41 => core::mem::transmute(&(iomux.gpio41)), + 42 => core::mem::transmute(&(iomux.gpio42)), + 43 => core::mem::transmute(&(iomux.gpio43)), + 44 => core::mem::transmute(&(iomux.gpio44)), + 45 => core::mem::transmute(&(iomux.gpio45)), + 46 => core::mem::transmute(&(iomux.gpio46)), + _ => panic!(), + } + } +} + +pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { + int_enable as u8 + | ((nmi_enable as u8) << 1) + | (int_enable as u8) << 2 + | ((nmi_enable as u8) << 3) +} + /// Peripheral input signals for the GPIO mux #[allow(non_camel_case_types)] #[derive(PartialEq, Copy, Clone)] @@ -168,3 +240,129 @@ pub enum OutputSignal { CLK_I2S = 251, GPIO = 256, } + +crate::gpio::gpio! { + (0, 0, InputOutputAnalog) + (1, 0, InputOutputAnalog) + (2, 0, InputOutputAnalog) + (3, 0, InputOutputAnalog) + (4, 0, InputOutputAnalog) + (5, 0, InputOutputAnalog) + (6, 0, InputOutputAnalog) + (7, 0, InputOutputAnalog) + (8, 0, InputOutputAnalog) + (9, 0, InputOutputAnalog) + (10, 0, InputOutputAnalog) + (11, 0, InputOutputAnalog) + (12, 0, InputOutputAnalog) + (13, 0, InputOutputAnalog) + (14, 0, InputOutputAnalog) + (15, 0, InputOutputAnalog) + (16, 0, InputOutputAnalog) + (17, 0, InputOutputAnalog) + (18, 0, InputOutputAnalog) + (19, 0, InputOutputAnalog) + (20, 0, InputOutputAnalog) + (21, 0, InputOutputAnalog) + + (26, 0, InputOutput) + (27, 0, InputOutput) + (28, 0, InputOutput) + (29, 0, InputOutput) + (30, 0, InputOutput) + (31, 0, InputOutput) + (32, 1, InputOutput) + (33, 1, InputOutput) + (34, 1, InputOutput) + (35, 1, InputOutput) + (36, 1, InputOutput) + (37, 1, InputOutput) + (38, 1, InputOutput) + (39, 1, InputOutput) + (40, 1, InputOutput) + (41, 1, InputOutput) + (42, 1, InputOutput) + (43, 1, InputOutput) + (44, 1, InputOutput) + (45, 1, InputOutput) + (46, 1, InputOutput) +} + +// on ESP32-S2 the touch_pad registers are indexed and the fields are weirdly +// named +macro_rules! impl_get_rtc_pad { + ($pad_name:ident) => { + paste!{ + pub(crate) fn []() -> &'static crate::pac::rtcio::[< $pad_name:upper >] { + use crate::pac::RTCIO; + let rtcio = unsafe{ &*RTCIO::ptr() }; + &rtcio.$pad_name + } + } + }; +} + +macro_rules! impl_get_rtc_pad_indexed { + ($pad_name:ident, $idx:literal) => { + paste!{ + pub(crate) fn []() -> &'static crate::pac::rtcio::[< $pad_name:upper >] { + use crate::pac::RTCIO; + let rtcio = unsafe{ &*RTCIO::ptr() }; + &rtcio.$pad_name[$idx] + } + } + }; +} + +impl_get_rtc_pad_indexed!(touch_pad, 0); +impl_get_rtc_pad_indexed!(touch_pad, 1); +impl_get_rtc_pad_indexed!(touch_pad, 2); +impl_get_rtc_pad_indexed!(touch_pad, 3); +impl_get_rtc_pad_indexed!(touch_pad, 4); +impl_get_rtc_pad_indexed!(touch_pad, 5); +impl_get_rtc_pad_indexed!(touch_pad, 6); +impl_get_rtc_pad_indexed!(touch_pad, 7); +impl_get_rtc_pad_indexed!(touch_pad, 8); +impl_get_rtc_pad_indexed!(touch_pad, 9); +impl_get_rtc_pad_indexed!(touch_pad, 10); +impl_get_rtc_pad_indexed!(touch_pad, 11); +impl_get_rtc_pad_indexed!(touch_pad, 12); +impl_get_rtc_pad_indexed!(touch_pad, 13); +impl_get_rtc_pad_indexed!(touch_pad, 14); +impl_get_rtc_pad!(xtal_32p_pad); +impl_get_rtc_pad!(xtal_32n_pad); +impl_get_rtc_pad!(pad_dac1); +impl_get_rtc_pad!(pad_dac2); +impl_get_rtc_pad!(rtc_pad19); +impl_get_rtc_pad!(rtc_pad20); +impl_get_rtc_pad!(rtc_pad21); + +crate::gpio::analog! { + ( 0, 0, touch_pad0, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + ( 1, 1, touch_pad1, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + ( 2, 2, touch_pad2, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + ( 3, 3, touch_pad3, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + ( 4, 4, touch_pad4, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + ( 5, 5, touch_pad5, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + ( 6, 6, touch_pad6, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + ( 7, 7, touch_pad7, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + ( 8, 8, touch_pad8, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + ( 9, 9, touch_pad9, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + (10, 10, touch_pad10, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + (11, 11, touch_pad11, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + (12, 12, touch_pad12, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + (13, 13, touch_pad13, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + (14, 14, touch_pad14, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_rue, touch_pad0_rde) + (15, 15, xtal_32p_pad, x32p_mux_sel, x32p_fun_sel, x32p_fun_ie, x32p_rue, x32p_rde) + (16, 16, xtal_32n_pad, x32n_mux_sel, x32n_fun_sel, x32n_fun_ie, x32n_rue, x32n_rde) + (17, 17, pad_dac1, pdac1_mux_sel, pdac1_fun_sel, pdac1_fun_ie, pdac1_rue, pdac1_rde) + (18, 18, pad_dac2, pdac2_mux_sel, pdac2_fun_sel, pdac2_fun_ie, pdac2_rue, pdac2_rde) + (19, 19, rtc_pad19, mux_sel, fun_sel, fun_ie, rue, rde) + (20, 20, rtc_pad20, mux_sel, fun_sel, fun_ie, rue, rde) + (21, 21, rtc_pad21, mux_sel, fun_sel, fun_ie, rue, rde) +} + +// implement marker traits on USB pins +impl crate::otg_fs::UsbSel for Gpio18 {} +impl crate::otg_fs::UsbDp for Gpio19 {} +impl crate::otg_fs::UsbDm for Gpio20 {} diff --git a/esp-hal-common/src/gpio/esp32s3.rs b/esp-hal-common/src/gpio/esp32s3.rs index 7c3d3dc6f06..999d7dc0456 100644 --- a/esp-hal-common/src/gpio/esp32s3.rs +++ b/esp-hal-common/src/gpio/esp32s3.rs @@ -1,3 +1,17 @@ +use paste::paste; + +use crate::{ + gpio::PhantomData, + pac::GPIO, + AlternateFunction, + Bank0GpioRegisterAccess, + Bank1GpioRegisterAccess, + GpioPin, + InputOutputAnalogPinType, + InputOutputPinType, + Unknown, +}; + pub type OutputSignalType = u16; pub const OUTPUT_SIGNAL_MAX: u16 = 256; pub const INPUT_SIGNAL_MAX: u16 = 189; @@ -5,6 +19,16 @@ pub const INPUT_SIGNAL_MAX: u16 = 189; pub const ONE_INPUT: u8 = 0x38; pub const ZERO_INPUT: u8 = 0x3c; +pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1; + +pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO { + unsafe { &(&*crate::pac::IO_MUX::PTR).gpio[gpio_num as usize] } +} + +pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { + int_enable as u8 | ((nmi_enable as u8) << 1) +} + /// Peripheral input signals for the GPIO mux #[allow(non_camel_case_types)] #[derive(PartialEq, Copy, Clone)] @@ -217,3 +241,81 @@ pub enum OutputSignal { PCMCLK = 195, GPIO = 256, } + +crate::gpio::gpio! { + (0, 0, InputOutputAnalog) + (1, 0, InputOutputAnalog) + (2, 0, InputOutputAnalog) + (3, 0, InputOutputAnalog) + (4, 0, InputOutputAnalog) + (5, 0, InputOutputAnalog) + (6, 0, InputOutputAnalog) + (7, 0, InputOutputAnalog) + (8, 0, InputOutputAnalog () (3 => SUBSPICS1)) + (9, 0, InputOutputAnalog (3 => SUBSPIHD 4 => FSPIHD) (3 => SUBSPIHD 4 => FSPIHD)) + (10, 0, InputOutputAnalog (2 => FSPIIO4 4 => FSPICS0) (2 => FSPIIO4 3 => SUBSPICS0 4 => FSPICS0)) + (11, 0, InputOutputAnalog (2 => FSPIIO5 3 => SUBSPID 4 => FSPID) (2 => FSPIIO5 3 => SUBSPID 4 => FSPID)) + (12, 0, InputOutputAnalog (2 => FSPIIO6 4 => FSPICLK) (2 => FSPIIO6 3=> SUBSPICLK 4 => FSPICLK)) + (13, 0, InputOutputAnalog (2 => FSPIIO7 3 => SUBSPIQ 4 => FSPIQ) (2 => FSPIIO7 3 => SUBSPIQ 4 => FSPIQ)) + (14, 0, InputOutputAnalog (3 => SUBSPIWP 4 => FSPIWP) (2 => FSPIDQS 3 => SUBSPIWP 4 => FSPIWP)) + (15, 0, InputOutputAnalog () (2 => U0RTS)) + (16, 0, InputOutputAnalog (2 => U0CTS) ()) + (17, 0, InputOutputAnalog () (2 => U1TXD)) + (18, 0, InputOutputAnalog (2 => U1RXD) ()) + (19, 0, InputOutputAnalog () (2 => U1RTS)) + (20, 0, InputOutputAnalog (2 => U1CTS) ()) + (21, 0, InputOutputAnalog) + (26, 0, InputOutput) + (27, 0, InputOutput) + (28, 0, InputOutput) + (29, 0, InputOutput) + (30, 0, InputOutput) + (31, 0, InputOutput) + (32, 1, InputOutput) + (33, 1, InputOutput (2 => FSPIHD 3 => SUBSPIHD) (2 => FSPIHD 3 => SUBSPIHD)) + (34, 1, InputOutput (2 => FSPICS0) (2 => FSPICS0 3 => SUBSPICS0)) + (35, 1, InputOutput (2 => FSPID 3 => SUBSPID) (2 => FSPID 3 => SUBSPID)) + (36, 1, InputOutput (2 => FSPICLK) (2 => FSPICLK 3 => SUBSPICLK)) + (37, 1, InputOutput (2 => FSPIQ 3 => SUBSPIQ 4 => SPIDQS) (2 => FSPIQ 3=> SUBSPIQ 4 => SPIDQS)) + (38, 1, InputOutput (2 => FSPIWP 3 => SUBSPIWP) (3 => FSPIWP 3 => SUBSPIWP)) + (39, 1, InputOutput () (4 => SUBSPICS1)) + (40, 1, InputOutput) + (41, 1, InputOutput) + (42, 1, InputOutput) + (43, 1, InputOutput) + (44, 1, InputOutput) + (45, 1, InputOutput) + (46, 1, InputOutput) + (47, 1, InputOutput) + (48, 1, InputOutput) +} + +crate::gpio::analog! { + ( 0, 0, touch_pad0, mux_sel, fun_sel, fun_ie, rue, rde) + ( 1, 1, touch_pad1, mux_sel, fun_sel, fun_ie, rue, rde) + ( 2, 2, touch_pad2, mux_sel, fun_sel, fun_ie, rue, rde) + ( 3, 3, touch_pad3, mux_sel, fun_sel, fun_ie, rue, rde) + ( 4, 4, touch_pad4, mux_sel, fun_sel, fun_ie, rue, rde) + ( 5, 5, touch_pad5, mux_sel, fun_sel, fun_ie, rue, rde) + ( 6, 6, touch_pad6, mux_sel, fun_sel, fun_ie, rue, rde) + ( 7, 7, touch_pad7, mux_sel, fun_sel, fun_ie, rue, rde) + ( 8, 8, touch_pad8, mux_sel, fun_sel, fun_ie, rue, rde) + ( 9, 9, touch_pad9, mux_sel, fun_sel, fun_ie, rue, rde) + (10, 10, touch_pad10, mux_sel, fun_sel, fun_ie, rue, rde) + (11, 11, touch_pad11, mux_sel, fun_sel, fun_ie, rue, rde) + (12, 12, touch_pad12, mux_sel, fun_sel, fun_ie, rue, rde) + (13, 13, touch_pad13, mux_sel, fun_sel, fun_ie, rue, rde) + (14, 14, touch_pad14, mux_sel, fun_sel, fun_ie, rue, rde) + (15, 15, xtal_32p_pad, x32p_mux_sel, x32p_fun_sel, x32p_fun_ie, x32p_rue, x32p_rde) + (16, 16, xtal_32n_pad, x32n_mux_sel, x32n_fun_sel, x32n_fun_ie, x32n_rue, x32n_rde) + (17, 17, pad_dac1, pdac1_mux_sel,pdac1_fun_sel,pdac1_fun_ie, pdac1_rue, pdac1_rde) + (18, 18, pad_dac2, pdac2_mux_sel,pdac2_fun_sel,pdac2_fun_ie, pdac2_rue, pdac2_rde) + (19, 19, rtc_pad19, mux_sel, fun_sel, fun_ie, rue, rde) + (20, 20, rtc_pad20, mux_sel, fun_sel, fun_ie, rue, rde) + (21, 21, rtc_pad21, mux_sel, fun_sel, fun_ie, rue, rde) +} + +// implement marker traits on USB pins +impl crate::otg_fs::UsbSel for Gpio18 {} +impl crate::otg_fs::UsbDp for Gpio19 {} +impl crate::otg_fs::UsbDm for Gpio20 {} diff --git a/esp32-hal/examples/gpio_interrupt.rs b/esp32-hal/examples/gpio_interrupt.rs index 14611b793eb..4cb400a0d0e 100644 --- a/esp32-hal/examples/gpio_interrupt.rs +++ b/esp32-hal/examples/gpio_interrupt.rs @@ -11,8 +11,7 @@ use core::{borrow::BorrowMut, cell::RefCell}; use critical_section::Mutex; use esp32_hal::{ clock::ClockControl, - gpio::{Gpio0, IO}, - gpio_types::{Event, Input, PullDown}, + gpio::{Gpio0, IO, Event, Input, PullDown,}, interrupt, macros::ram, pac::{self, Peripherals}, diff --git a/esp32-hal/src/adc.rs b/esp32-hal/src/adc.rs deleted file mode 100644 index b2ea46b0339..00000000000 --- a/esp32-hal/src/adc.rs +++ /dev/null @@ -1,53 +0,0 @@ -//! Analog to digital (ADC) conversion support. -//! -//! This module provides functions for reading analog values from two -//! analog to digital converters available on the ESP32: `ADC1` and `ADC2`. -//! -//! The following pins can be configured for analog readout: -//! -//! | Channel | ADC1 | ADC2 | -//! |---------|----------------------|---------------| -//! | 0 | GPIO36 (SENSOR_VP) | GPIO4 | -//! | 1 | GPIO37 (SENSOR_CAPP) | GPIO0 | -//! | 2 | GPIO38 (SENSOR_CAPN) | GPIO2 | -//! | 3 | GPIO39 (SENSOR_VN) | GPIO15 (MTDO) | -//! | 4 | GPIO33 (32K_XP) | GPIO13 (MTCK) | -//! | 5 | GPIO32 (32K_XN) | GPIO12 (MTDI) | -//! | 6 | GPIO34 (VDET_1) | GPIO14 (MTMS) | -//! | 7 | GPIO35 (VDET_2) | GPIO27 | -//! | 8 | | GPIO25 | -//! | 9 | | GPIO26 | - -use embedded_hal::adc::Channel; -use esp_hal_common::analog::adc::impl_adc_interface; -pub use esp_hal_common::analog::{adc::*, ADC1, ADC2}; - -use crate::{gpio::*, gpio_types::Analog}; - -impl_adc_interface! { - ADC1 [ - (Gpio36, 0), // Alt. name: SENSOR_VP - (Gpio37, 1), // Alt. name: SENSOR_CAPP - (Gpio38, 2), // Alt. name: SENSOR_CAPN - (Gpio39, 3), // Alt. name: SENSOR_VN - (Gpio33, 4), // Alt. name: 32K_XP - (Gpio32, 5), // Alt. name: 32K_XN - (Gpio34, 6), // Alt. name: VDET_1 - (Gpio35, 7), // Alt. name: VDET_2 - ] -} - -impl_adc_interface! { - ADC2 [ - (Gpio4, 0), - (Gpio0, 1), - (Gpio2, 2), - (Gpio15, 3), // Alt. name: MTDO - (Gpio13, 4), // Alt. name: MTCK - (Gpio12, 5), // Alt. name: MTDI - (Gpio14, 6), // Alt. name: MTMS - (Gpio27, 7), - (Gpio25, 8), - (Gpio26, 9), - ] -} diff --git a/esp32-hal/src/dac.rs b/esp32-hal/src/dac.rs deleted file mode 100644 index 1dbfce9ca30..00000000000 --- a/esp32-hal/src/dac.rs +++ /dev/null @@ -1,11 +0,0 @@ -//! Digital to analog (DAC) conversion. -//! -//! This module provides functions for controling two digital to -//! analog converters, available on ESP32: `DAC1` and `DAC2`. -//! -//! The DAC1 is available on the GPIO pin 25, and DAC2 on pin 26. - -pub use esp_hal_common::analog::dac::*; -use esp_hal_common::{impl_dac, paste}; - -impl_dac!(1 => Gpio25, 2 => Gpio26,); diff --git a/esp32-hal/src/gpio.rs b/esp32-hal/src/gpio.rs deleted file mode 100644 index 8e47fe68a0e..00000000000 --- a/esp32-hal/src/gpio.rs +++ /dev/null @@ -1,76 +0,0 @@ -//! General Purpose I/Os -//! -//! To get access to the pins, you first need to convert them into a HAL -//! designed struct from the pac struct `GPIO` and `IO_MUX` using `IO::new`. -//! -//! ```no_run -//! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); -//! let mut led = io.pins.gpio5.into_push_pull_output(); -//! ``` - -use esp_hal_common::gpio::{types::*, *}; - -gpio! { - Function2, - DualCore, - - Gpio0: ( gpio0, 0, gpio0, IO, RTC, Bank0, touch_pad1), (EMAC_TX_CLK: Function5), (CLK_OUT1: Function1), - Gpio1: ( gpio1, 1, gpio1, IO, 0, Bank0, None), (EMAC_RXD2: Function5), (U0TXD: Function1, CLK_OUT3: Function1), - Gpio2: ( gpio2, 2, gpio2, IO, RTC, Bank0, touch_pad2), (HSPIWP: Function1, HS2_DATA0: Function3, SD_DATA0: Function4), (HS2_DATA0: Function3, SD_DATA0: Function4), - Gpio3: ( gpio3, 3, gpio3, IO, 0, Bank0, None), (U0RXD: Function0), (CLK_OUT2: Function1), - Gpio4: ( gpio4, 4, gpio4, IO, RTC, Bank0, touch_pad0), (HSPIHD: Function1, HS2_DATA1: Function3, SD_DATA1: Function4, EMAC_TX_ER: Function5), (HS2_DATA1: Function3, SD_DATA1: Function4), - Gpio5: ( gpio5, 5, gpio5, IO, 0, Bank0, None), (VSPICS0: Function1, HS1_DATA6: Function3, EMAC_RX_CLK: Function5), (HS1_DATA6: Function3), - Gpio6: ( gpio6, 6, gpio6, IO, 0, Bank0, None), (U1CTS: Function4), (SD_CLK: Function0, SPICLK: Function1, HS1_CLK: Function3), - Gpio7: ( gpio7, 7, gpio7, IO, 0, Bank0, None), (SD_DATA0: Function0, SPIQ: Function1, HS1_DATA0: Function3), (SD_DATA0: Function0, SPIQ: Function1, HS1_DATA0: Function3, U2RTS: Function4), - Gpio8: ( gpio8, 8, gpio8, IO, 0, Bank0, None), (SD_DATA1: Function0, SPID: Function1, HS1_DATA1: Function3, U2CTS: Function4), (SD_DATA1: Function0, SPID: Function1, HS1_DATA1: Function3), - Gpio9: ( gpio9, 9, gpio9, IO, 0, Bank0, None), (SD_DATA2: Function0, SPIHD: Function1, HS1_DATA2: Function3, U1RXD: Function4), (SD_DATA2: Function0, SPIHD: Function1, HS1_DATA2: Function3), - Gpio10: (gpio10, 10, gpio10, IO, 0, Bank0, None), (SD_DATA3: Function0, SPIWP: Function1, HS1_DATA3: Function3), (SD_DATA3: Function0, SPIWP: Function1, HS1_DATA3: Function3, U1TXD: Function4), - Gpio11: (gpio11, 11, gpio11, IO, 0, Bank0, None), (SPICS0: Function1), (SD_CMD: Function0, SPICS0: Function1, HS1_CMD: Function3, U1RTS: Function4), - Gpio12: (gpio12, 12, gpio12, IO, RTC, Bank0, touch_pad5), (MTDI: Function0, HSPIQ: Function1, HS2_DATA2: Function3, SD_DATA2: Function4), (HSPIQ: Function1, HS2_DATA2: Function3, SD_DATA2: Function4, EMAC_TXD3: Function5), - Gpio13: (gpio13, 13, gpio13, IO, RTC, Bank0, touch_pad4), (MTCK: Function0, HSPID: Function1, HS2_DATA3: Function3, SD_DATA3: Function4), (HSPID: Function1, HS2_DATA3: Function3, SD_DATA3: Function4, EMAC_RX_ER: Function5), - Gpio14: (gpio14, 14, gpio14, IO, RTC, Bank0, touch_pad6), (MTMS: Function0, HSPICLK: Function1), (HSPICLK: Function1, HS2_CLK: Function3, SD_CLK: Function4, EMAC_TXD2: Function5), - Gpio15: (gpio15, 15, gpio15, IO, RTC, Bank0, touch_pad3), (HSPICS0: Function1, EMAC_RXD3: Function5), (MTDO: Function0, HSPICS0: Function1, HS2_CMD: Function3, SD_CMD: Function4), - Gpio16: (gpio16, 16, gpio16, IO, 0, Bank0, None), (HS1_DATA4: Function3, U2RXD: Function4), (HS1_DATA4: Function3, EMAC_CLK_OUT: Function5), - Gpio17: (gpio17, 17, gpio17, IO, 0, Bank0, None), (HS1_DATA5: Function3), (HS1_DATA5: Function3, U2TXD: Function4, EMAC_CLK_180: Function5), - Gpio18: (gpio18, 18, gpio18, IO, 0, Bank0, None), (VSPICLK: Function1, HS1_DATA7: Function3), (VSPICLK: Function1, HS1_DATA7: Function3), - Gpio19: (gpio19, 19, gpio19, IO, 0, Bank0, None), (VSPIQ: Function1, U0CTS: Function3), (VSPIQ: Function1, EMAC_TXD0: Function5), - Gpio20: (gpio20, 20, gpio20, IO, 0, Bank0, None), - Gpio21: (gpio21, 21, gpio21, IO, 0, Bank0, None), (VSPIHD: Function1), (VSPIHD: Function1, EMAC_TX_EN: Function5), - - Gpio22: (gpio22, 22, gpio22, IO, 0, Bank0, None), (VSPIWP: Function1), (VSPIWP: Function1, U0RTS: Function3, EMAC_TXD1: Function5), - Gpio23: (gpio23, 23, gpio23, IO, 0, Bank0, None), (VSPID: Function1), (VSPID: Function1, HS1_STROBE: Function3), - Gpio24: (gpio24, 24, gpio24, IO, 0, Bank0, None), - Gpio25: (gpio25, 25, gpio25, IO, 0, Bank0, pad_dac1), (EMAC_RXD0: Function5), (), - Gpio26: (gpio26, 26, gpio26, IO, 0, Bank0, pad_dac2), (EMAC_RXD1: Function5), (), - Gpio27: (gpio27, 27, gpio27, IO, 0, Bank0, touch_pad7), (EMAC_RX_DV: Function5), (), - - Gpio32: (gpio32, 32, gpio32, IO, 0, Bank1, xtal_32k_n), - Gpio33: (gpio33, 33, gpio33, IO, 0, Bank1, xtal_32k_p), - Gpio34: (gpio34, 34, gpio34, Input, 0, Bank1, None), - Gpio35: (gpio35, 35, gpio35, Input, 0, Bank1, None), - Gpio36: (gpio36, 36, gpio36, Input, 0, Bank1, None), - Gpio37: (gpio37, 37, gpio37, Input, 0, Bank1, None), - Gpio38: (gpio38, 38, gpio38, Input, 0, Bank1, None), - Gpio39: (gpio39, 39, gpio39, Input, 0, Bank1, None), -} - -analog! { - Gpio36: (0, sensor_pads, sense1_hold, sense1_mux_sel, sense1_fun_sel, sense1_fun_ie, sense1_slp_ie, sense1_slp_sel ), - Gpio37: (1, sensor_pads, sense2_hold, sense2_mux_sel, sense2_fun_sel, sense2_fun_ie, sense2_slp_ie, sense2_slp_sel ), - Gpio38: (2, sensor_pads, sense3_hold, sense3_mux_sel, sense3_fun_sel, sense3_fun_ie, sense3_slp_ie, sense3_slp_sel ), - Gpio39: (3, sensor_pads, sense4_hold, sense4_mux_sel, sense4_fun_sel, sense4_fun_ie, sense4_slp_ie, sense4_slp_sel ), - Gpio34: (4, adc_pad, adc1_hold, adc1_mux_sel, adc1_fun_sel, adc1_fun_ie, adc1_slp_ie, adc1_slp_sel ), - Gpio35: (5, adc_pad, adc2_hold, adc2_mux_sel, adc2_fun_sel, adc1_fun_ie, adc1_slp_ie, adc1_slp_sel ), - Gpio25: (6, pad_dac1, pdac1_hold, pdac1_mux_sel, pdac1_fun_sel, pdac1_fun_ie, pdac1_slp_ie, pdac1_slp_sel, pdac1_rue, pdac1_rde, pdac1_drv, pdac1_slp_oe), - Gpio26: (7, pad_dac2, pdac2_hold, pdac2_mux_sel, pdac2_fun_sel, pdac2_fun_ie, pdac2_slp_ie, pdac2_slp_sel, pdac2_rue, pdac2_rde, pdac2_drv, pdac2_slp_oe), - Gpio33: (8, xtal_32k_pad, x32n_hold, x32n_mux_sel, x32n_fun_sel, x32n_fun_ie, x32n_slp_ie, x32n_slp_sel, x32n_rue, x32n_rde, x32n_drv, x32n_slp_oe), - Gpio32: (9, xtal_32k_pad, x32p_hold, x32p_mux_sel, x32p_fun_sel, x32p_fun_ie, x32p_slp_ie, x32p_slp_sel, x32p_rue, x32p_rde, x32p_drv, x32p_slp_oe), - Gpio4: (10, touch_pad0, hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio0: (11, touch_pad1, hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio2: (12, touch_pad2, hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio15: (13, touch_pad3, hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio13: (14, touch_pad4, hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio12: (15, touch_pad5, hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio14: (16, touch_pad6, hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio27: (17, touch_pad7, hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), -} diff --git a/esp32-hal/src/lib.rs b/esp32-hal/src/lib.rs index 70be3d5496a..acda539373a 100644 --- a/esp32-hal/src/lib.rs +++ b/esp32-hal/src/lib.rs @@ -3,12 +3,14 @@ pub use embedded_hal as ehal; #[doc(inline)] pub use esp_hal_common::{ + analog::adc::implementation as adc, + analog::dac::implementation as dac, clock, cpu_control::CpuControl, dma, dma::pdma, efuse, - gpio as gpio_types, + gpio, i2c, i2s, interrupt, @@ -37,10 +39,6 @@ pub use self::gpio::IO; #[cfg(feature = "embassy")] pub use esp_hal_common::embassy; -pub mod adc; -pub mod dac; -pub mod gpio; - /// Common module for analog functions pub mod analog { pub use esp_hal_common::analog::{AvailableAnalog, SensExt}; @@ -95,10 +93,3 @@ pub unsafe extern "C" fn ESP32Reset() -> ! { pub extern "Rust" fn __init_data() -> bool { false } - -fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { - int_enable as u8 - | ((nmi_enable as u8) << 1) - | (int_enable as u8) << 2 - | ((nmi_enable as u8) << 3) -} diff --git a/esp32c2-hal/examples/gpio_interrupt.rs b/esp32c2-hal/examples/gpio_interrupt.rs index fc92b49596f..bf26880202c 100644 --- a/esp32c2-hal/examples/gpio_interrupt.rs +++ b/esp32c2-hal/examples/gpio_interrupt.rs @@ -11,8 +11,7 @@ use core::cell::RefCell; use critical_section::Mutex; use esp32c2_hal::{ clock::ClockControl, - gpio::{Gpio9, IO}, - gpio_types::{Event, Input, PullDown}, + gpio::{Gpio9, IO, Event, Input, PullDown}, interrupt, pac::{self, Peripherals}, prelude::*, diff --git a/esp32c2-hal/src/adc.rs b/esp32c2-hal/src/adc.rs deleted file mode 100644 index 5f232026d59..00000000000 --- a/esp32c2-hal/src/adc.rs +++ /dev/null @@ -1,20 +0,0 @@ -//! Analog to digital (ADC) conversion support. -//! -//! This module provides functions for reading analog values from the -//! analog to digital converter available on the ESP32-C2: `ADC1`. - -use embedded_hal::adc::Channel; -use esp_hal_common::analog::adc::impl_adc_interface; -pub use esp_hal_common::analog::{adc::*, ADC1}; - -use crate::{gpio::*, gpio_types::Analog}; - -impl_adc_interface! { - ADC1 [ - (Gpio0, 0), - (Gpio1, 1), - (Gpio2, 2), - (Gpio3, 3), - (Gpio4, 4), - ] -} diff --git a/esp32c2-hal/src/gpio.rs b/esp32c2-hal/src/gpio.rs deleted file mode 100644 index 476549aa8c9..00000000000 --- a/esp32c2-hal/src/gpio.rs +++ /dev/null @@ -1,38 +0,0 @@ -//! General Purpose I/Os -//! -//! To get access to the pins, you first need to convert them into a HAL -//! designed struct from the pac struct `GPIO` and `IO_MUX` using `IO::new`. -//! -//! ```no_run -//! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); -//! let mut led = io.pins.gpio5.into_push_pull_output(); -//! ``` -use esp_hal_common::gpio::{types::*, *}; - -gpio! { - Function1, - SingleCore, - - Gpio0: ( gpio0, 0, gpio[0], IO, RTC, Bank0, None), - Gpio1: ( gpio1, 1, gpio[1], IO, RTC, Bank0, None), - Gpio2: ( gpio2, 2, gpio[2], IO, RTC, Bank0, None), (FSPIQ: Function2), (FSPIQ: Function2), - Gpio3: ( gpio3, 3, gpio[3], IO, RTC, Bank0, None), - Gpio4: ( gpio4, 4, gpio[4], IO, RTC, Bank0, None), (FSPIHD: Function2), (FSPIHD: Function2), - Gpio5: ( gpio5, 5, gpio[5], IO, RTC, Bank0, None), (FSPIWP: Function2), (FSPIWP: Function2), - Gpio6: ( gpio6, 6, gpio[6], IO, 0, Bank0, None), (FSPICLK: Function2), (FSPICLK_MUX: Function2), - Gpio7: ( gpio7, 7, gpio[7], IO, 0, Bank0, None), (FSPID: Function2), (FSPID: Function2), - Gpio8: ( gpio8, 8, gpio[8], IO, 0, Bank0, None), - Gpio9: ( gpio9, 9, gpio[9], IO, 0, Bank0, None), - Gpio10: (gpio10, 10, gpio[10], IO, 0, Bank0, None), (FSPICS0: Function2), (FSPICS0: Function2), - Gpio18: (gpio18, 18, gpio[18], IO, 0, Bank0, None), - Gpio19: (gpio19, 19, gpio[19], IO, 0, Bank0, None), - Gpio20: (gpio20, 20, gpio[20], IO, 0, Bank0, None), -} - -analog! { - Gpio0 => 0 - Gpio1 => 1 - Gpio2 => 2 - Gpio3 => 3 - Gpio4 => 4 -} diff --git a/esp32c2-hal/src/lib.rs b/esp32c2-hal/src/lib.rs index 38321d7fd39..93a42ef8c92 100644 --- a/esp32c2-hal/src/lib.rs +++ b/esp32c2-hal/src/lib.rs @@ -7,10 +7,11 @@ pub use embedded_hal as ehal; pub use esp_hal_common::embassy; #[doc(inline)] pub use esp_hal_common::{ + analog::adc::implementation as adc, clock, dma::{self, gdma}, efuse, - gpio as gpio_types, + gpio, i2c, interrupt, ledc, @@ -33,9 +34,6 @@ pub use esp_hal_common::{ pub use self::gpio::IO; -pub mod adc; -pub mod gpio; - /// Common module for analog functions pub mod analog { pub use esp_hal_common::analog::{AvailableAnalog, SarAdcExt}; @@ -282,9 +280,5 @@ pub fn mp_hook() -> bool { } } -fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { - int_enable as u8 | ((nmi_enable as u8) << 1) -} - #[no_mangle] extern "C" fn EspDefaultHandler(_interrupt: pac::Interrupt) {} diff --git a/esp32c3-hal/examples/gpio_interrupt.rs b/esp32c3-hal/examples/gpio_interrupt.rs index b0b0f7846ed..12d3bd2f4c8 100644 --- a/esp32c3-hal/examples/gpio_interrupt.rs +++ b/esp32c3-hal/examples/gpio_interrupt.rs @@ -11,8 +11,7 @@ use core::cell::RefCell; use critical_section::Mutex; use esp32c3_hal::{ clock::ClockControl, - gpio::{Gpio9, IO}, - gpio_types::{Event, Input, PullDown}, + gpio::{Gpio9, IO, Event, Input, PullDown}, interrupt, pac::{self, Peripherals}, prelude::*, diff --git a/esp32c3-hal/src/adc.rs b/esp32c3-hal/src/adc.rs deleted file mode 100644 index 4e638b6ffef..00000000000 --- a/esp32c3-hal/src/adc.rs +++ /dev/null @@ -1,26 +0,0 @@ -//! Analog to digital (ADC) conversion support. -//! -//! This module provides functions for reading analog values from two -//! analog to digital converters available on the ESP32-C3: `ADC1` and `ADC2`. - -use embedded_hal::adc::Channel; -use esp_hal_common::analog::adc::impl_adc_interface; -pub use esp_hal_common::analog::{adc::*, ADC1, ADC2}; - -use crate::{gpio::*, gpio_types::Analog}; - -impl_adc_interface! { - ADC1 [ - (Gpio0, 0), - (Gpio1, 1), - (Gpio2, 2), - (Gpio3, 3), - (Gpio4, 4), - ] -} - -impl_adc_interface! { - ADC2 [ - (Gpio5, 4), - ] -} diff --git a/esp32c3-hal/src/gpio.rs b/esp32c3-hal/src/gpio.rs deleted file mode 100644 index 6e6ac1ed14c..00000000000 --- a/esp32c3-hal/src/gpio.rs +++ /dev/null @@ -1,47 +0,0 @@ -//! General Purpose I/Os -//! -//! To get access to the pins, you first need to convert them into a HAL -//! designed struct from the pac struct `GPIO` and `IO_MUX` using `IO::new`. -//! -//! ```no_run -//! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); -//! let mut led = io.pins.gpio5.into_push_pull_output(); -//! ``` -use esp_hal_common::gpio::{types::*, *}; - -gpio! { - Function1, - SingleCore, - - Gpio0: ( gpio0, 0, gpio[0], IO, RTC, Bank0, None), - Gpio1: ( gpio1, 1, gpio[1], IO, RTC, Bank0, None), - Gpio2: ( gpio2, 2, gpio[2], IO, RTC, Bank0, None), (FSPIQ: Function2), (FSPIQ: Function2), - Gpio3: ( gpio3, 3, gpio[3], IO, RTC, Bank0, None), - Gpio4: ( gpio4, 4, gpio[4], IO, RTC, Bank0, None), (FSPIHD: Function2), (USB_JTAG_TMS: Function0, FSPIHD: Function2), - Gpio5: ( gpio5, 5, gpio[5], IO, RTC, Bank0, None), (FSPIWP: Function2), (USB_JTAG_TDI: Function0, FSPIWP: Function2), - Gpio6: ( gpio6, 6, gpio[6], IO, 0, Bank0, None), (FSPICLK: Function2), (USB_JTAG_TCK: Function0, FSPICLK_MUX: Function2), - Gpio7: ( gpio7, 7, gpio[7], IO, 0, Bank0, None), (FSPID: Function2), (USB_JTAG_TDO: Function0, FSPID: Function2), - Gpio8: ( gpio8, 8, gpio[8], IO, 0, Bank0, None), - Gpio9: ( gpio9, 9, gpio[9], IO, 0, Bank0, None), - Gpio10: (gpio10, 10, gpio[10], IO, 0, Bank0, None), (FSPICS0: Function2), (FSPICS0: Function2), - Gpio11: (gpio11, 11, gpio[11], IO, 0, Bank0, None), - Gpio12: (gpio12, 12, gpio[12], IO, 0, Bank0, None), (SPIHD: Function0), (SPIHD: Function0), - Gpio13: (gpio13, 13, gpio[13], IO, 0, Bank0, None), (SPIWP: Function0), (SPIWP: Function0), - Gpio14: (gpio14, 14, gpio[14], IO, 0, Bank0, None), (), (SPICS0: Function0), - Gpio15: (gpio15, 15, gpio[15], IO, 0, Bank0, None), (), (SPICLK_MUX: Function0), - Gpio16: (gpio16, 16, gpio[16], IO, 0, Bank0, None), (SPID: Function0), (SPID: Function0), - Gpio17: (gpio17, 17, gpio[17], IO, 0, Bank0, None), (SPIQ: Function0), (SPIQ: Function0), - Gpio18: (gpio18, 18, gpio[18], IO, 0, Bank0, None), - Gpio19: (gpio19, 19, gpio[19], IO, 0, Bank0, None), - Gpio20: (gpio20, 20, gpio[20], IO, 0, Bank0, None), (U0RXD: Function0), (), - Gpio21: (gpio21, 21, gpio[21], IO, 0, Bank0, None), (), (U0TXD: Function0), -} - -analog! { - Gpio0 => 0 - Gpio1 => 1 - Gpio2 => 2 - Gpio3 => 3 - Gpio4 => 4 - Gpio5 => 4 -} diff --git a/esp32c3-hal/src/lib.rs b/esp32c3-hal/src/lib.rs index cf7f7fbc169..2d139095707 100644 --- a/esp32c3-hal/src/lib.rs +++ b/esp32c3-hal/src/lib.rs @@ -7,11 +7,12 @@ use core::mem::size_of; pub use embedded_hal as ehal; #[doc(inline)] pub use esp_hal_common::{ + analog::adc::implementation as adc, clock, dma, dma::gdma, efuse, - gpio as gpio_types, + gpio, i2c, i2s, interrupt, @@ -45,9 +46,6 @@ use riscv_rt::pre_init; pub use self::gpio::IO; -pub mod adc; -pub mod gpio; - /// Common module for analog functions pub mod analog { pub use esp_hal_common::analog::{AvailableAnalog, SarAdcExt}; @@ -445,9 +443,5 @@ pub fn mp_hook() -> bool { false } -fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { - int_enable as u8 | ((nmi_enable as u8) << 1) -} - #[no_mangle] extern "C" fn EspDefaultHandler(_interrupt: pac::Interrupt) {} diff --git a/esp32s2-hal/examples/gpio_interrupt.rs b/esp32s2-hal/examples/gpio_interrupt.rs index 2ad309fc920..b8b46793c87 100644 --- a/esp32s2-hal/examples/gpio_interrupt.rs +++ b/esp32s2-hal/examples/gpio_interrupt.rs @@ -11,8 +11,7 @@ use core::cell::RefCell; use critical_section::Mutex; use esp32s2_hal::{ clock::ClockControl, - gpio::{Gpio0, IO}, - gpio_types::{Event, Input, PullDown}, + gpio::{Gpio0, IO, Event, Input, PullDown}, interrupt, macros::ram, pac::{self, Peripherals}, diff --git a/esp32s2-hal/src/adc.rs b/esp32s2-hal/src/adc.rs deleted file mode 100644 index f3e77828724..00000000000 --- a/esp32s2-hal/src/adc.rs +++ /dev/null @@ -1,40 +0,0 @@ -//! Analog to digital (ADC) conversion support. -//! -//! This module provides functions for reading analog values from two -//! analog to digital converters available on the ESP32-S2: `ADC1` and `ADC2`. - -use embedded_hal::adc::Channel; -use esp_hal_common::analog::adc::impl_adc_interface; -pub use esp_hal_common::analog::{adc::*, ADC1, ADC2}; - -use crate::{gpio::*, gpio_types::Analog}; - -impl_adc_interface! { - ADC1 [ - (Gpio1, 0), - (Gpio2, 1), - (Gpio3, 2), - (Gpio4, 3), - (Gpio5, 4), - (Gpio6, 5), - (Gpio7, 6), - (Gpio8, 7), - (Gpio9, 8), - (Gpio10,9), - ] -} - -impl_adc_interface! { - ADC2 [ - (Gpio11, 0), - (Gpio12, 1), - (Gpio13, 2), - (Gpio14, 3), - (Gpio15, 4), - (Gpio16, 5), - (Gpio17, 6), - (Gpio18, 7), - (Gpio19, 8), - (Gpio20, 9), - ] -} diff --git a/esp32s2-hal/src/dac.rs b/esp32s2-hal/src/dac.rs deleted file mode 100644 index 5bd90acb916..00000000000 --- a/esp32s2-hal/src/dac.rs +++ /dev/null @@ -1,10 +0,0 @@ -//! Digital to analog (DAC) conversion. -//! -//! This module provides functions for controling two digital to -//! analog converters, available on ESP32-S2: `DAC1` and `DAC2`. -//! -//! The DAC1 is available on the GPIO pin 17, and DAC2 on pin 18. - -use esp_hal_common::{impl_dac, paste}; - -impl_dac!(1 => Gpio17, 2 => Gpio18,); diff --git a/esp32s2-hal/src/gpio.rs b/esp32s2-hal/src/gpio.rs deleted file mode 100644 index e94d80c1e15..00000000000 --- a/esp32s2-hal/src/gpio.rs +++ /dev/null @@ -1,90 +0,0 @@ -//! General Purpose I/Os -//! -//! To get access to the pins, you first need to convert them into a HAL -//! designed struct from the pac struct `GPIO` and `IO_MUX` using `IO::new`. -//! -//! ```no_run -//! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); -//! let mut led = io.pins.gpio5.into_push_pull_output(); -//! ``` - -use esp_hal_common::gpio::{types::*, *}; - -gpio! { - Function1, - SingleCore, - - Gpio0: ( gpio0, 0, gpio0, IO, RTC, Bank0, None), - Gpio1: ( gpio1, 1, gpio1, IO, RTC, Bank0, None), - Gpio2: ( gpio2, 2, gpio2, IO, RTC, Bank0, None), - Gpio3: ( gpio3, 3, gpio3, IO, RTC, Bank0, None), - Gpio4: ( gpio4, 4, gpio4, IO, RTC, Bank0, None), - Gpio5: ( gpio5, 5, gpio5, IO, RTC, Bank0, None), - Gpio6: ( gpio6, 6, gpio6, IO, RTC, Bank0, None), - Gpio7: ( gpio7, 7, gpio7, IO, RTC, Bank0, None), - Gpio8: ( gpio8, 8, gpio8, IO, RTC, Bank0, None), (), (SUBSPICS1: Function3), - Gpio9: ( gpio9, 9, gpio9, IO, RTC, Bank0, None), (SUBSPIHD: Function3, FSPIHD: Function4), (SUBSPIHD: Function3, FSPIHD: Function4), - Gpio10: (gpio10, 10, gpio10, IO, RTC, Bank0, None), (FSPIIO4: Function2, FSPICS0: Function4), (FSPIIO4: Function2, SUBSPICS0: Function3, FSPICS0: Function4), - Gpio11: (gpio11, 11, gpio11, IO, RTC, Bank0, None), (FSPIIO5: Function2, SUBSPID: Function3, FSPID: Function4), (FSPIIO5: Function2, SUBSPID: Function3, FSPID: Function4), - Gpio12: (gpio12, 12, gpio12, IO, RTC, Bank0, None), (FSPICLK: Function4, FSPIIO6: Function2), (FSPIIO6: Function2, SUBSPICLK: Function3, FSPICLK: Function4), - Gpio13: (gpio13, 13, gpio13, IO, RTC, Bank0, None), (FSPIIO7: Function2, SUBSPIQ: Function3, FSPIQ: Function4), (FSPIIO7: Function2, SUBSPIQ: Function3, FSPIQ: Function4), - Gpio14: (gpio14, 14, gpio14, IO, RTC, Bank0, None), (SUBSPIWP: Function3, FSPIWP: Function4), (FSPIDQS: Function2, SUBSPIWP: Function3, FSPIWP: Function4), - Gpio15: (gpio15, 15, gpio15, IO, RTC, Bank0, None), (), (U0RTS: Function2), - Gpio16: (gpio16, 16, gpio16, IO, RTC, Bank0, None), (U0CTS: Function2), (), - Gpio17: (gpio17, 17, gpio17, IO, RTC, Bank0, None), (), (U1TXD: Function2), - Gpio18: (gpio18, 18, gpio18, IO, RTC, Bank0, None), (U1RXD: Function2), (), - Gpio19: (gpio19, 19, gpio19, IO, RTC, Bank0, None), (), (U1RTS: Function2), - Gpio20: (gpio20, 20, gpio20, IO, RTC, Bank0, None), (U1CTS: Function2), (), - Gpio21: (gpio21, 21, gpio21, IO, RTC, Bank0, None), - Gpio26: (gpio26, 26, gpio26, IO, 0, Bank0, None), (), (SPICS1: Function0), - Gpio27: (gpio27, 27, gpio27, IO, 0, Bank0, None), (SPIHD: Function0), (SPIHD: Function0), - Gpio28: (gpio28, 28, gpio28, IO, 0, Bank0, None), (SPIWP: Function0), (SPIWP: Function0), - Gpio29: (gpio29, 29, gpio29, IO, 0, Bank0, None), (), (SPICS0: Function0), - Gpio30: (gpio30, 30, gpio30, IO, 0, Bank0, None), (), (SPICLK: Function0), - Gpio31: (gpio31, 31, gpio31, IO, 0, Bank0, None), (SPIQ: Function0), (SPIQ: Function0), - Gpio32: (gpio32, 32, gpio32, IO, 0, Bank1, None), (SPID: Function0), (SPID: Function0), - Gpio33: (gpio33, 33, gpio33, IO, 0, Bank1, None), (FSPIHD: Function2, SUBSPIHD: Function3, FSPIIO4: Function4), (FSPIHD: Function2, SUBSPIHD: Function3), - Gpio34: (gpio34, 34, gpio34, IO, 0, Bank1, None), (FSPICS0: Function2, FSPIIO5: Function4), (FSPICS0: Function2, SUBSPICS0: Function3), - Gpio35: (gpio35, 35, gpio35, IO, 0, Bank1, None), (FSPID: Function2, SUBSPID: Function3, FSPIIO6: Function4), (FSPID: Function2, SUBSPID: Function3), - Gpio36: (gpio36, 36, gpio36, IO, 0, Bank1, None), (FSPICLK: Function2, FSPIIO7: Function4), (FSPICLK: Function2, SUBSPICLK: Function3), - Gpio37: (gpio37, 37, gpio37, IO, 0, Bank1, None), (FSPIQ: Function2, SUBSPIQ: Function3, SPIDQS: Function4), (FSPIQ: Function2, SUBSPIQ: Function3), - Gpio38: (gpio38, 38, gpio38, IO, 0, Bank1, None), (FSPIWP: Function2, SUBSPIWP: Function3), (FSPIWP: Function2, SUBSPIWP: Function3), - Gpio39: (gpio39, 39, gpio39, IO, 0, Bank1, None), (), (SUBSPICS1: Function3), - Gpio40: (gpio40, 40, gpio40, IO, 0, Bank1, None), - Gpio41: (gpio41, 41, gpio41, IO, 0, Bank1, None), - Gpio42: (gpio42, 42, gpio42, IO, 0, Bank1, None), - Gpio43: (gpio43, 43, gpio43, IO, 0, Bank1, None), (), (U0TXD: Function0), - Gpio44: (gpio44, 44, gpio44, IO, 0, Bank1, None), (U0RXD: Function0), (), - Gpio45: (gpio45, 45, gpio45, IO, 0, Bank1, None), - Gpio46: (gpio46, 46, gpio46, IO,Input, Bank1, None), -} - -analog! { - Gpio0: ( 0, touch_pad[0], touch_pad0_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio1: ( 1, touch_pad[1], touch_pad1_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio2: ( 2, touch_pad[2], touch_pad2_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio3: ( 3, touch_pad[3], touch_pad3_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio4: ( 4, touch_pad[4], touch_pad4_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio5: ( 5, touch_pad[5], touch_pad5_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio6: ( 6, touch_pad[6], touch_pad6_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio7: ( 7, touch_pad[7], touch_pad7_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio8: ( 8, touch_pad[8], touch_pad8_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio9: ( 9, touch_pad[9], touch_pad9_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio10: (10, touch_pad[10], touch_pad10_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio11: (11, touch_pad[11], touch_pad11_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio12: (12, touch_pad[12], touch_pad12_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio13: (13, touch_pad[13], touch_pad13_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio14: (14, touch_pad[14], touch_pad14_hold, touch_pad0_mux_sel, touch_pad0_fun_sel, touch_pad0_fun_ie, touch_pad0_slp_ie, touch_pad0_slp_sel, touch_pad0_rue, touch_pad0_rde, touch_pad0_drv, touch_pad0_slp_oe), - Gpio15: (15, xtal_32p_pad, x32p_hold, x32p_mux_sel, x32p_fun_sel, x32p_fun_ie, x32p_slp_ie, x32p_slp_sel, x32p_rue, x32p_rde, x32p_drv, x32p_slp_oe), - Gpio16: (16, xtal_32n_pad, x32n_hold, x32n_mux_sel, x32n_fun_sel, x32n_fun_ie, x32n_slp_ie, x32n_slp_sel, x32n_rue, x32n_rde, x32n_drv, x32pn_slp_oe), - Gpio17: (17, pad_dac1, pdac1_hold, pdac1_mux_sel, pdac1_fun_sel, pdac1_fun_ie, pdac1_slp_ie, pdac1_slp_sel, pdac1_rue, pdac1_rde, pdac1_drv, pdac1_slp_oe), - Gpio18: (18, pad_dac2, pdac2_hold, pdac2_mux_sel, pdac2_fun_sel, pdac2_fun_ie, pdac2_slp_ie, pdac2_slp_sel, pdac2_rue, pdac2_rde, pdac2_drv, pdac2_slp_oe), - Gpio19: (19, rtc_pad19, rtc_pad19_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio20: (20, rtc_pad20, rtc_pad20_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio21: (21, rtc_pad21, rtc_pad21_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), -} - -// implement marker traits on USB pins -impl esp_hal_common::otg_fs::UsbSel for Gpio18 {} -impl esp_hal_common::otg_fs::UsbDp for Gpio19 {} -impl esp_hal_common::otg_fs::UsbDm for Gpio20 {} diff --git a/esp32s2-hal/src/lib.rs b/esp32s2-hal/src/lib.rs index e806c15fd1a..e4f001b95d8 100644 --- a/esp32s2-hal/src/lib.rs +++ b/esp32s2-hal/src/lib.rs @@ -3,11 +3,13 @@ pub use embedded_hal as ehal; #[doc(inline)] pub use esp_hal_common::{ + analog::adc::implementation as adc, + analog::dac::implementation as dac, clock, dma, dma::pdma, efuse, - gpio as gpio_types, + gpio, i2s, i2c::{self, I2C}, interrupt, @@ -38,10 +40,6 @@ pub use esp_hal_common::embassy; pub use self::gpio::IO; -pub mod adc; -pub mod dac; -pub mod gpio; - /// Common module for analog functions pub mod analog { pub use esp_hal_common::analog::{AvailableAnalog, SensExt}; @@ -96,10 +94,3 @@ pub unsafe extern "C" fn ESP32Reset() -> ! { pub extern "Rust" fn __init_data() -> bool { false } - -fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { - int_enable as u8 - | ((nmi_enable as u8) << 1) - | (int_enable as u8) << 2 - | ((nmi_enable as u8) << 3) -} diff --git a/esp32s3-hal/examples/gpio_interrupt.rs b/esp32s3-hal/examples/gpio_interrupt.rs index 8298d537fd3..a562464726b 100644 --- a/esp32s3-hal/examples/gpio_interrupt.rs +++ b/esp32s3-hal/examples/gpio_interrupt.rs @@ -11,8 +11,7 @@ use core::cell::RefCell; use critical_section::Mutex; use esp32s3_hal::{ clock::ClockControl, - gpio::{Gpio0, IO}, - gpio_types::{Event, Input, PullDown}, + gpio::{Gpio0, IO, Event, Input, PullDown}, interrupt, macros::ram, pac::{self, Peripherals}, diff --git a/esp32s3-hal/src/adc.rs b/esp32s3-hal/src/adc.rs deleted file mode 100644 index 4c34bb2180b..00000000000 --- a/esp32s3-hal/src/adc.rs +++ /dev/null @@ -1,40 +0,0 @@ -//! Analog to digital (ADC) conversion support. -//! -//! This module provides functions for reading analog values from two -//! analog to digital converters available on the ESP32-S3: `ADC1` and `ADC2`. - -use embedded_hal::adc::Channel; -use esp_hal_common::analog::adc::impl_adc_interface; -pub use esp_hal_common::analog::{adc::*, ADC1, ADC2}; - -use crate::{gpio::*, gpio_types::Analog}; - -impl_adc_interface! { - ADC1 [ - (Gpio1, 0), - (Gpio2, 1), - (Gpio3, 2), - (Gpio4, 3), - (Gpio5, 4), - (Gpio6, 5), - (Gpio7, 6), - (Gpio8, 7), - (Gpio9, 8), - (Gpio10,9), - ] -} - -impl_adc_interface! { - ADC2 [ - (Gpio11, 0), - (Gpio12, 1), - (Gpio13, 2), - (Gpio14, 3), - (Gpio15, 4), - (Gpio16, 5), - (Gpio17, 6), - (Gpio18, 7), - (Gpio19, 8), - (Gpio20, 9), - ] -} diff --git a/esp32s3-hal/src/gpio.rs b/esp32s3-hal/src/gpio.rs deleted file mode 100644 index 9ca80ac3bed..00000000000 --- a/esp32s3-hal/src/gpio.rs +++ /dev/null @@ -1,95 +0,0 @@ -//! General Purpose I/Os -//! -//! To get access to the pins, you first need to convert them into a HAL -//! designed struct from the pac struct `GPIO` and `IO_MUX` using `IO::new`. -//! -//! ```no_run -//! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); -//! let mut led = io.pins.gpio5.into_push_pull_output(); -//! ``` - -use esp_hal_common::gpio::{types::*, *}; - -// ESP32S3 is a dual-core chip however pro cpu and app cpu shares the same -// interrupt enable bit see https://github.com/espressif/esp-idf/blob/c04803e88b871a4044da152dfb3699cf47354d18/components/hal/esp32s3/include/hal/gpio_ll.h#L32 -// Treating it as SingleCore in the gpio macro makes this work. -gpio! { - Function1, - SingleCore, - - Gpio0: ( gpio0, 0, gpio[0], IO, RTC, Bank0, None), - Gpio1: ( gpio1, 1, gpio[1], IO, RTC, Bank0, None), - Gpio2: ( gpio2, 2, gpio[2], IO, RTC, Bank0, None), - Gpio3: ( gpio3, 3, gpio[3], IO, RTC, Bank0, None), - Gpio4: ( gpio4, 4, gpio[4], IO, RTC, Bank0, None), - Gpio5: ( gpio5, 5, gpio[5], IO, RTC, Bank0, None), - Gpio6: ( gpio6, 6, gpio[6], IO, RTC, Bank0, None), - Gpio7: ( gpio7, 7, gpio[7], IO, RTC, Bank0, None), - Gpio8: ( gpio8, 8, gpio[8], IO, RTC, Bank0, None), (), (SUBSPICS1: Function3), - Gpio9: ( gpio9, 9, gpio[9], IO, RTC, Bank0, None), (SUBSPIHD: Function3, FSPIHD: Function4), (SUBSPIHD: Function3, FSPIHD: Function4), - Gpio10: (gpio10, 10, gpio[10], IO, RTC, Bank0, None), (FSPIIO4: Function2, FSPICS0: Function4), (FSPIIO4: Function2, SUBSPICS0: Function3, FSPICS0: Function4), - Gpio11: (gpio11, 11, gpio[11], IO, RTC, Bank0, None), (FSPIIO5: Function2, SUBSPID: Function3, FSPID: Function4), (FSPIIO5: Function2, SUBSPID: Function3, FSPID: Function4), - Gpio12: (gpio12, 12, gpio[12], IO, RTC, Bank0, None), (FSPIIO6: Function2, FSPICLK: Function4), (FSPIIO6: Function2, SUBSPICLK: Function3, FSPICLK: Function4), - Gpio13: (gpio13, 13, gpio[13], IO, RTC, Bank0, None), (FSPIIO7: Function2, SUBSPIQ: Function3, FSPIQ: Function4), (FSPIIO7: Function2, SUBSPIQ: Function3, FSPIQ: Function4), - Gpio14: (gpio14, 14, gpio[14], IO, RTC, Bank0, None), (SUBSPIWP: Function3, FSPIWP: Function4), (FSPIDQS: Function2, SUBSPIWP: Function3, FSPIWP: Function4), - Gpio15: (gpio15, 15, gpio[15], IO, RTC, Bank0, None), (), (U0RTS: Function2), - Gpio16: (gpio16, 16, gpio[16], IO, RTC, Bank0, None), (U0CTS: Function2), (), - Gpio17: (gpio17, 17, gpio[17], IO, RTC, Bank0, None), (), (U1TXD: Function2), - Gpio18: (gpio18, 18, gpio[18], IO, RTC, Bank0, None), (U1RXD: Function2), (), - Gpio19: (gpio19, 19, gpio[19], IO, RTC, Bank0, None), (), (U1RTS: Function2), - Gpio20: (gpio20, 20, gpio[20], IO, RTC, Bank0, None), (U1CTS: Function2), (), - Gpio21: (gpio21, 21, gpio[21], IO, RTC, Bank0, None), - Gpio26: (gpio26, 26, gpio[26], IO, 0, Bank0, None), - Gpio27: (gpio27, 27, gpio[27], IO, 0, Bank0, None), - Gpio28: (gpio28, 28, gpio[28], IO, 0, Bank0, None), - Gpio29: (gpio29, 29, gpio[29], IO, 0, Bank0, None), - Gpio30: (gpio30, 30, gpio[30], IO, 0, Bank0, None), - Gpio31: (gpio31, 31, gpio[31], IO, 0, Bank0, None), - Gpio32: (gpio32, 32, gpio[32], IO, 0, Bank1, None), - Gpio33: (gpio33, 33, gpio[33], IO, 0, Bank1, None), (FSPIHD: Function2, SUBSPIHD: Function3), (FSPIHD: Function2, SUBSPIHD: Function3), - Gpio34: (gpio34, 34, gpio[34], IO, 0, Bank1, None), (FSPICS0: Function2), (FSPICS0: Function2, SUBSPICS0: Function3), - Gpio35: (gpio35, 35, gpio[35], IO, 0, Bank1, None), (FSPID: Function2, SUBSPID: Function3), (FSPID: Function2, SUBSPID: Function3), - Gpio36: (gpio36, 36, gpio[36], IO, 0, Bank1, None), (FSPICLK: Function2), (FSPICLK: Function2, SUBSPICLK: Function3), - Gpio37: (gpio37, 37, gpio[37], IO, 0, Bank1, None), (FSPIQ: Function2, SUBSPIQ: Function3, SPIDQS: Function4), (FSPIQ: Function2, SUBSPIQ: Function3, SPIDQS: Function4), - Gpio38: (gpio38, 38, gpio[38], IO, 0, Bank1, None), (FSPIWP: Function2, SUBSPIWP: Function3), (FSPIWP: Function3, SUBSPIWP: Function3), - Gpio39: (gpio39, 39, gpio[39], IO, 0, Bank1, None), (), (SUBSPICS1: Function4), - Gpio40: (gpio40, 40, gpio[40], IO, 0, Bank1, None), - Gpio41: (gpio41, 41, gpio[41], IO, 0, Bank1, None), - Gpio42: (gpio42, 42, gpio[42], IO, 0, Bank1, None), - Gpio43: (gpio43, 43, gpio[43], IO, 0, Bank1, None), - Gpio44: (gpio44, 44, gpio[44], IO, 0, Bank1, None), - Gpio45: (gpio45, 45, gpio[45], IO, 0, Bank1, None), - Gpio46: (gpio46, 46, gpio[46], IO, 0, Bank1, None), - Gpio47: (gpio47, 47, gpio[47], IO, 0, Bank1, None), - Gpio48: (gpio48, 48, gpio[48], IO, 0, Bank1, None), -} - -analog! { - Gpio0: ( 0, touch_pad0, touch_pad0_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio1: ( 1, touch_pad1, touch_pad1_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio2: ( 2, touch_pad2, touch_pad2_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio3: ( 3, touch_pad3, touch_pad3_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio4: ( 4, touch_pad4, touch_pad4_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio5: ( 5, touch_pad5, touch_pad5_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio6: ( 6, touch_pad6, touch_pad6_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio7: ( 7, touch_pad7, touch_pad7_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio8: ( 8, touch_pad8, touch_pad8_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio9: ( 9, touch_pad9, touch_pad9_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio10: (10, touch_pad10, touch_pad10_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio11: (11, touch_pad11, touch_pad11_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio12: (12, touch_pad12, touch_pad12_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio13: (13, touch_pad13, touch_pad13_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio14: (14, touch_pad14, touch_pad14_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio15: (15, xtal_32p_pad, x32p_hold, x32p_mux_sel, x32p_fun_sel, x32p_fun_ie, x32p_slp_ie, x32p_slp_sel, x32p_rue, x32p_rde, x32p_drv, x32p_slp_oe), - Gpio16: (16, xtal_32n_pad, x32n_hold, x32n_mux_sel, x32n_fun_sel, x32n_fun_ie, x32n_slp_ie, x32n_slp_sel, x32n_rue, x32n_rde, x32n_drv, x32pn_slp_oe), - Gpio17: (17, pad_dac1, pdac1_hold, pdac1_mux_sel,pdac1_fun_sel,pdac1_fun_ie, pdac1_slp_ie, pdac1_slp_sel, pdac1_rue, pdac1_rde, pdac1_drv, pdac1_slp_oe), - Gpio18: (18, pad_dac2, pdac2_hold, pdac2_mux_sel,pdac2_fun_sel,pdac2_fun_ie, pdac2_slp_ie, pdac2_slp_sel, pdac2_rue, pdac2_rde, pdac2_drv, pdac2_slp_oe), - Gpio19: (19, rtc_pad19, rtc_pad19_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio20: (20, rtc_pad20, rtc_pad20_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), - Gpio21: (21, rtc_pad21, rtc_pad21_hold, mux_sel, fun_sel, fun_ie, slp_ie, slp_sel, rue, rde, drv, slp_oe), -} - -// implement marker traits on USB pins -impl esp_hal_common::otg_fs::UsbSel for Gpio18 {} -impl esp_hal_common::otg_fs::UsbDp for Gpio19 {} -impl esp_hal_common::otg_fs::UsbDm for Gpio20 {} diff --git a/esp32s3-hal/src/lib.rs b/esp32s3-hal/src/lib.rs index fd161de7632..44baa570288 100644 --- a/esp32s3-hal/src/lib.rs +++ b/esp32s3-hal/src/lib.rs @@ -5,11 +5,12 @@ pub use embedded_hal as ehal; #[doc(inline)] pub use esp_hal_common::{ + analog::adc::implementation as adc, clock, cpu_control::CpuControl, dma::{self, gdma}, efuse, - gpio as gpio_types, + gpio, i2c, i2s, interrupt, @@ -41,9 +42,6 @@ pub use esp_hal_common::embassy; pub use self::gpio::IO; -pub mod adc; -pub mod gpio; - /// Common module for analog functions pub mod analog { pub use esp_hal_common::analog::{AvailableAnalog, SensExt}; @@ -248,7 +246,3 @@ pub extern "Rust" fn __init_data() -> bool { res } - -fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { - int_enable as u8 | ((nmi_enable as u8) << 1) -}