From 5b84c886754e4465a33c6e84ff41ecf32f16b4f2 Mon Sep 17 00:00:00 2001
From: dimi <dimi.polonski@gmail.com>
Date: Wed, 29 Mar 2023 14:20:58 +0200
Subject: [PATCH] add Twai::enable_rx_interrupt and Twai::disable_rx_interrupt

---
 esp-hal-common/src/twai/mod.rs | 36 ++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/esp-hal-common/src/twai/mod.rs b/esp-hal-common/src/twai/mod.rs
index 35a3d0648ed..28ef2d345b6 100644
--- a/esp-hal-common/src/twai/mod.rs
+++ b/esp-hal-common/src/twai/mod.rs
@@ -403,6 +403,42 @@ where
         }
     }
 
+    /// Use in combination with `interrupt::enable`.
+    /// The interrupt is cleared when all pending messages are received.
+    #[cfg(any(esp32c3, esp32s3))]
+    pub fn enable_rx_interrupt(&mut self) {
+        self.peripheral
+            .register_block()
+            .int_ena
+            .modify(|_, w| w.rx_int_ena().set_bit());
+    }
+
+    /// Use in combination with `interrupt::enable`.
+    /// The interrupt is cleared when all pending messages are received.
+    #[cfg(esp32c6)]
+    pub fn enable_rx_interrupt(&mut self) {
+        self.peripheral
+            .register_block()
+            .interrupt_enable
+            .modify(|_, w| w.ext_receive_int_ena().set_bit());
+    }
+
+    #[cfg(any(esp32c3, esp32s3))]
+    pub fn disable_rx_interrupt(&mut self) {
+        self.peripheral
+            .register_block()
+            .int_ena
+            .modify(|_, w| w.rx_int_ena().clear_bit());
+    }
+
+    #[cfg(esp32c6)]
+    pub fn disable_rx_interrupt(&mut self) {
+        self.peripheral
+            .register_block()
+            .interrupt_enable
+            .modify(|_, w| w.ext_receive_int_ena().clear_bit());
+    }
+
     /// Release the message in the buffer. This will decrement the received
     /// message counter and prepare the next message in the FIFO for
     /// reading.