diff --git a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c
index c2f4a3de928..293c16080c1 100644
--- a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c
+++ b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c
@@ -26,11 +26,8 @@ void ulp_riscv_halt(void)
     /* Setting the delay time after RISCV recv `DONE` signal, Ensure that action `RESET` can be executed in time. */
     REG_SET_FIELD(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_2_CLK_DIS, 0x3F);
 
-    /* suspends the ulp operation*/
-    SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE);
-
-    /* Resets the processor */
-    SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
+    /* Suspends the ulp operation and reset the ULP core. Must be the final operation before going to halt. */
+    SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN);
 
     while(1);
 }
diff --git a/components/ulp/ulp_riscv/ulp_riscv.c b/components/ulp/ulp_riscv/ulp_riscv.c
index 0e6bda3dedc..f18360a99b9 100644
--- a/components/ulp/ulp_riscv/ulp_riscv.c
+++ b/components/ulp/ulp_riscv/ulp_riscv.c
@@ -53,8 +53,6 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
 #if CONFIG_IDF_TARGET_ESP32S2
     /* Reset COCPU when power on. */
     SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
-    esp_rom_delay_us(20);
-    CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
 
      /* The coprocessor cpu trap signal doesnt have a stable reset value,
        force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
@@ -75,8 +73,6 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
 #elif CONFIG_IDF_TARGET_ESP32S3
     /* Reset COCPU when power on. */
     SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
-    esp_rom_delay_us(20);
-    CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
 
      /* The coprocessor cpu trap signal doesnt have a stable reset value,
        force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
diff --git a/examples/system/ulp_riscv/i2c/main/bmp180_defs.h b/examples/system/ulp_riscv/i2c/main/bmp180_defs.h
index d8ae173e929..81d7569a000 100644
--- a/examples/system/ulp_riscv/i2c/main/bmp180_defs.h
+++ b/examples/system/ulp_riscv/i2c/main/bmp180_defs.h
@@ -103,8 +103,8 @@ static int32_t bmp180_calculate_real_pressure(int32_t up_data, int32_t ut_data,
 
 /************************************************
  * Temperature and Pressure thresholds (uncompensated) to wake up Main CPU
- * The threshold values have been selected for demp purposes and may not
+ * The threshold values have been selected for demo purposes and may not
  * represent real world use case.
  ************************************************/
-#define EXAMPLE_UT_THRESHOLD    20000
-#define EXAMPLE_UP_THRESHOLD    40000
+#define EXAMPLE_UT_THRESHOLD    25000
+#define EXAMPLE_UP_THRESHOLD    50000
diff --git a/examples/system/ulp_riscv/i2c/main/ulp/main.c b/examples/system/ulp_riscv/i2c/main/ulp/main.c
index ba545ac6ea0..9fc97ca9275 100644
--- a/examples/system/ulp_riscv/i2c/main/ulp/main.c
+++ b/examples/system/ulp_riscv/i2c/main/ulp/main.c
@@ -71,7 +71,7 @@ static void bmp180_read_ut_data(int16_t *ut_data)
     ulp_riscv_i2c_master_write_to_device(&cmd, 1);
 
     /* Wait at least 4.5 milliseconds for the sensor to complete the reading */
-    ulp_riscv_delay_cycles(5 * ULP_RISCV_CYCLES_PER_US * 1000);
+    ulp_riscv_delay_cycles(5 * ULP_RISCV_CYCLES_PER_MS);
 
     /* Read uncompensated temperature data */
     bmp180_read16((uint16_t *)ut_data, BMP180_SENSOR_REG_ADDR_SENSOR_DATA_MSB, BMP180_SENSOR_REG_ADDR_SENSOR_DATA_LSB);
@@ -111,7 +111,7 @@ static void bmp180_read_up_data(int32_t *up_data, oss_mode_t oss_mode)
     ulp_riscv_i2c_master_write_to_device(&cmd, 1);
 
     /* Wait for the required amount of time for the sensor to complete the reading */
-    ulp_riscv_delay_cycles(wait * ULP_RISCV_CYCLES_PER_US * 1000);
+    ulp_riscv_delay_cycles(wait * ULP_RISCV_CYCLES_PER_MS);
 
     /* Read uncompensated temperature data */
 
diff --git a/examples/system/ulp_riscv/i2c/main/ulp_riscv_rtc_i2c_example_main.c b/examples/system/ulp_riscv/i2c/main/ulp_riscv_rtc_i2c_example_main.c
index ba486b7ee8a..35d92db27d3 100644
--- a/examples/system/ulp_riscv/i2c/main/ulp_riscv_rtc_i2c_example_main.c
+++ b/examples/system/ulp_riscv/i2c/main/ulp_riscv_rtc_i2c_example_main.c
@@ -143,7 +143,7 @@ void app_main(void)
     }
 
 
-    /* Add a delay for everything to the printed before heading in to light sleep */
+    /* Add a delay for everything to the printed before heading in to deep sleep */
     vTaskDelay(100);
 
     /* Go back to sleep, only the ULP RISC-V will run */
@@ -342,9 +342,9 @@ static void init_ulp_program(void)
     ESP_ERROR_CHECK(err);
 
     /* The first argument is the period index, which is not used by the ULP-RISC-V timer
-     * The second argument is the period in microseconds, which gives a wakeup time period of: 20ms
+     * The second argument is the period in microseconds, which gives a wakeup time period of: 40ms
      */
-    ulp_set_wakeup_period(0, 20000);
+    ulp_set_wakeup_period(0, 40000);
 
     /* Start the program */
     err = ulp_riscv_run();