CPU: cache cart instructions

[fengb]

Depends on #27

Current CPU implementation is basically:

• address => fetch => decode => op(args)

An alternate approach would be:

• address => [cache miss] => fetch => decode => [fill cache] => indirect(op)(args)
• address => [cache hit] => indirect(op)(args)

This should eliminate a memory fetch thus hopefully speeding up execution.

Notes:

• we need to translate the request address to a physical cart address.
• need separate space for volatile data — first pass should simply reserve 0x8000 and null out whenever that memory location changes