Identation not working properly

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Input

-- sample code here
-- entity name: rng
-- gerador de numero randomico


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY rng is 
  generic (g_SEED : std_logic_vector(7 downto 0) := "00000000");
        
  PORT (  i_CLK       : IN  std_logic;
          i_RST       : IN  std_logic;
          i_EN        : IN  std_logic;            
          o_Q         : OUT std_logic_vector(7 DOWNTO 0)
          );
END rng;

ARCHITECTURE arch OF rng IS
  
  signal w_REG_OUT : std_logic_vector (7 downto 0);  
  signal w_XOR : std_logic;

  component generic_register is 
  generic ( g_DATA_WIDTH : INTEGER := 8);         
  PORT (  
    i_CLK       : IN  std_logic;
    i_CLR       : IN  std_logic;
    i_EN       : IN  std_logic;
    i_A         : IN  std_logic_vector(g_DATA_WIDTH - 1 DOWNTO 0);          
    o_Q         : OUT std_logic_vector(g_DATA_WIDTH - 1 DOWNTO 0)
  );
  END component;
  

BEGIN  
    
  u_REG0 : generic_register 
            generic map (g_DATA_WIDTH => 1)
            port map 
            (
              i_CLK => i_CLK ,
              i_CLR => i_RST ,
              i_EN  => i_EN  ,
              i_A(0)=> w_XOR ,
              o_Q(0)=> w_REG_OUT(0)   
            );

  u_REG1 : generic_register 
            generic map (g_DATA_WIDTH => 1)
            port map 
            (
              i_CLK => i_CLK ,
              i_CLR => i_RST ,
              i_EN  => i_EN  ,
              i_A(0)=> w_REG_OUT(0),
              o_Q(0)=> w_REG_OUT(1)   
            ); 
  u_REG2 : generic_register 
            generic map (g_DATA_WIDTH => 1)
            port map 
            (
              i_CLK => i_CLK ,
              i_CLR => i_RST ,
              i_EN  => i_EN  ,
              i_A(0)=> w_REG_OUT(1),
              o_Q(0)=> w_REG_OUT(2)   
            );
  u_REG3 : generic_register 
            generic map (g_DATA_WIDTH => 1)
            port map 
            (
              i_CLK => i_CLK ,
              i_CLR => i_RST ,
              i_EN  => i_EN  ,
              i_A(0)=> w_REG_OUT(2) ,
              o_Q(0)=> w_REG_OUT(3)   
            );
  u_REG4 : generic_register 
            generic map (g_DATA_WIDTH => 1)
            port map 
            (
              i_CLK => i_CLK ,
              i_CLR => i_RST ,
              i_EN  => i_EN  ,
              i_A(0)=> w_REG_OUT(3),
              o_Q(0)=> w_REG_OUT(4)   
            );
  u_REG5 : generic_register 
            generic map (g_DATA_WIDTH => 1)
            port map 
            (
              i_CLK => i_CLK ,
              i_CLR => i_RST ,
              i_EN  => i_EN  ,
              i_A(0)=> w_REG_OUT(4),
              o_Q(0)=> w_REG_OUT(5)   
            );
  u_REG6 : generic_register 
            generic map (g_DATA_WIDTH => 1)
            port map 
            (
              i_CLK => i_CLK ,
              i_CLR => i_RST ,
              i_EN  => i_EN  ,
              i_A(0)=> w_REG_OUT(5),
              o_Q(0)=> w_REG_OUT(6)   
            );            

  u_REG7 : generic_register 
            generic map (g_DATA_WIDTH => 1)
            port map 
            (
              i_CLK => i_CLK ,
              i_CLR => i_RST ,
              i_EN  => i_EN  ,
              i_A(0)=> w_REG_OUT(6),
              o_Q(0)=> w_REG_OUT(7)   
            );     
  
  -- porta XOR entre segundo, terceiro, quarto e oitavo registradores
  w_XOR <= (w_REG_OUT(1) XOR w_REG_OUT(2)) XOR (w_REG_OUT(3) XOR w_REG_OUT(7));
  
  -- saída
  o_Q <= w_REG_OUT;
  
END arch;

Expected Behavior

Identation of componentes instantiations

-- sample code here
	u_REG0 : generic_register
	  generic map 
          (
            g_DATA_WIDTH => 1
          )
	  port map
	  (
		i_CLK  => i_CLK,
		i_CLR  => i_RST,
		i_EN   => i_EN,
		i_A(0) => w_XOR,
		o_Q(0) => w_REG_OUT(0)
	);

Actual Behavior

-- sample code here
u_REG1 : generic_register
generic
map (g_DATA_WIDTH => 1)
port
map
(
i_CLK => i_CLK,
i_CLR => i_RST,
i_EN => i_EN,
i_A(0) => w_REG_OUT(0),
o_Q(0) => w_REG_OUT(1)
);