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main.lot
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main.lot
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\boolfalse {citerequest}\boolfalse {citetracker}\boolfalse {pagetracker}\boolfalse {backtracker}\relax
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\contentsline {table}{\numberline {5.1}{\ignorespaces I/O number of primary inputs/outputs, $|G|$ number of logic network nodes (gates + fan-outs), $w \times h$ aspect ratio given in tiles, $|WC|$ number wire crossings, $|W|$ number of wires, $t$ in s runtime in seconds, OOM maximum RAM reached, ---no data available\relax }}{61}{table.caption.50}%
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\contentsline {table}{\numberline {5.2}{\ignorespaces I/O number of primary inputs/outputs, $|N|$ number of gates before preprocessing, $|M|$ number of majority gates, $|G|$ number of logic network nodes (gates + fan-outs), $w \times h$ aspect ratio given in tiles, $|WC|$ number wire crossings, $|W|$ number of wires, $t$ in s runtime in seconds, OOM maximum RAM reached, ---no data available\relax }}{63}{table.caption.51}%
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\contentsline {table}{\numberline {5.3}{\ignorespaces I/O number of primary inputs/outputs, $|R|$ number of registers (D-flipflops), $|G|$ number of logic network nodes (gates + fan-outs), $w \times h$ aspect ratio given in tiles, $t$ in s runtime in seconds, OOM maximum RAM reached, ---no data available\relax }}{65}{table.caption.52}%
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