-
Notifications
You must be signed in to change notification settings - Fork 0
/
main.c
1308 lines (1109 loc) · 42.3 KB
/
main.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
Name 1: Jonathan Downing
UTEID 1: jjd2547
*/
/***************************************************************/
/* */
/* LC-3b Simulator - Lab 6 */
/* */
/* EE 460N -- Spring 2013 */
/* The University of Texas at Austin */
/* */
/***************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
/***************************************************************/
/* */
/* Files: ucode Microprogram file */
/* isaprogram LC-3b machine language program file */
/* */
/***************************************************************/
/***************************************************************/
/* These are the functions you'll have to write. */
/***************************************************************/
void FETCH_stage();
void DE_stage();
void AGEX_stage();
void MEM_stage();
void SR_stage();
/***************************************************************/
/* A couple of useful definitions. */
/***************************************************************/
#define TRUE 1
#define FALSE 0
/***************************************************************/
/* Use this to avoid overflowing 16 bits on the bus. */
/***************************************************************/
#define Low16bits(x) ((x) & 0xFFFF)
/***************************************************************/
/* Definition of the control store layout. */
/***************************************************************/
#define CONTROL_STORE_ROWS 64
/***************************************************************/
/* Definition of bit order in control store word. */
/***************************************************************/
/* control signals from the control store */
enum CS_BITS {
SR1_NEEDED,
SR2_NEEDED,
DRMUX,
ADDR1MUX,
ADDR2MUX1, ADDR2MUX0,
LSHF1,
ADDRESSMUX,
SR2MUX,
ALUK1, ALUK0,
ALU_RESULTMUX,
BR_OP,
UNCOND_OP,
TRAP_OP,
BR_STALL,
DCACHE_EN,
DCACHE_RW,
DATA_SIZE,
DR_VALUEMUX1, DR_VALUEMUX0,
LD_REG,
LD_CC,
NUM_CONTROL_STORE_BITS
} CS_BITS;
enum AGEX_CS_BITS {
AGEX_ADDR1MUX,
AGEX_ADDR2MUX1, AGEX_ADDR2MUX0,
AGEX_LSHF1,
AGEX_ADDRESSMUX,
AGEX_SR2MUX,
AGEX_ALUK1, AGEX_ALUK0,
AGEX_ALU_RESULTMUX,
AGEX_BR_OP,
AGEX_UNCOND_OP,
AGEX_TRAP_OP,
AGEX_BR_STALL,
AGEX_DCACHE_EN,
AGEX_DCACHE_RW,
AGEX_DATA_SIZE,
AGEX_DR_VALUEMUX1, AGEX_DR_VALUEMUX0,
AGEX_LD_REG,
AGEX_LD_CC,
NUM_AGEX_CS_BITS
} AGEX_CS_BITS;
enum MEM_CS_BITS {
MEM_BR_OP,
MEM_UNCOND_OP,
MEM_TRAP_OP,
MEM_BR_STALL,
MEM_DCACHE_EN,
MEM_DCACHE_RW,
MEM_DATA_SIZE,
MEM_DR_VALUEMUX1, MEM_DR_VALUEMUX0,
MEM_LD_REG,
MEM_LD_CC,
NUM_MEM_CS_BITS
} MEM_CS_BITS;
enum SR_CS_BITS {
SR_DR_VALUEMUX1, SR_DR_VALUEMUX0,
SR_LD_REG,
SR_LD_CC,
NUM_SR_CS_BITS
} SR_CS_BITS;
/***************************************************************/
/* Functions to get at the control bits. */
/***************************************************************/
int Get_SR1_NEEDED(int *x) { return (x[SR1_NEEDED]); }
int Get_SR2_NEEDED(int *x) { return (x[SR2_NEEDED]); }
int Get_DRMUX(int *x) { return (x[DRMUX]);}
int Get_DE_BR_OP(int *x) { return (x[BR_OP]); }
int Get_ADDR1MUX(int *x) { return (x[AGEX_ADDR1MUX]); }
int Get_ADDR2MUX(int *x) { return ((x[AGEX_ADDR2MUX1] << 1) + x[AGEX_ADDR2MUX0]); }
int Get_LSHF1(int *x) { return (x[AGEX_LSHF1]); }
int Get_ADDRESSMUX(int *x) { return (x[AGEX_ADDRESSMUX]); }
int Get_SR2MUX(int *x) { return (x[AGEX_SR2MUX]); }
int Get_ALUK(int *x) { return ((x[AGEX_ALUK1] << 1) + x[AGEX_ALUK0]); }
int Get_ALU_RESULTMUX(int *x) { return (x[AGEX_ALU_RESULTMUX]); }
int Get_BR_OP(int *x) { return (x[MEM_BR_OP]); }
int Get_UNCOND_OP(int *x) { return (x[MEM_UNCOND_OP]); }
int Get_TRAP_OP(int *x) { return (x[MEM_TRAP_OP]); }
int Get_DCACHE_EN(int *x) { return (x[MEM_DCACHE_EN]); }
int Get_DCACHE_RW(int *x) { return (x[MEM_DCACHE_RW]); }
int Get_DATA_SIZE(int *x) { return (x[MEM_DATA_SIZE]); }
int Get_DR_VALUEMUX1(int *x) { return ((x[SR_DR_VALUEMUX1] << 1 ) + x[SR_DR_VALUEMUX0]); }
int Get_AGEX_LD_REG(int *x) { return (x[AGEX_LD_REG]); }
int Get_AGEX_LD_CC(int *x) { return (x[AGEX_LD_CC]); }
int Get_MEM_LD_REG(int *x) { return (x[MEM_LD_REG]); }
int Get_MEM_LD_CC(int *x) { return (x[MEM_LD_CC]); }
int Get_SR_LD_REG(int *x) { return (x[SR_LD_REG]); }
int Get_SR_LD_CC(int *x) { return (x[SR_LD_CC]); }
int Get_DE_BR_STALL(int *x) { return (x[BR_STALL]); }
int Get_AGEX_BR_STALL(int *x) { return (x[AGEX_BR_STALL]); }
int Get_MEM_BR_STALL(int *x) { return (x[MEM_BR_STALL]); }
/***************************************************************/
/* The control store rom. */
/***************************************************************/
int CONTROL_STORE[CONTROL_STORE_ROWS][NUM_CONTROL_STORE_BITS];
/***************************************************************/
/* Main memory. */
/***************************************************************/
/* MEMORY[A][0] stores the least significant byte of word at word address A
MEMORY[A][1] stores the most significant byte of word at word address A
There are two write enable signals, one for each byte. WE0 is used for
the least significant byte of a word. WE1 is used for the most significant
byte of a word. */
#define WORDS_IN_MEM 0x08000
int MEMORY[WORDS_IN_MEM][2];
/***************************************************************/
/* The LC-3b register file. */
/***************************************************************/
#define LC3b_REGS 8
int REGS[LC3b_REGS];
/***************************************************************/
/* architectural state */
/***************************************************************/
int PC, /* program counter */
N, /* n condition bit */
Z = 1, /* z condition bit */
P; /* p condition bit */
/***************************************************************/
/* LC-3b State info. */
/***************************************************************/
typedef struct PipeState_Entry_Struct{
/* DE latches */
int DE_NPC,
DE_IR,
DE_V,
/* AGEX lateches */
AGEX_NPC,
AGEX_SR1,
AGEX_SR2,
AGEX_CC,
AGEX_IR,
AGEX_DRID,
AGEX_V,
AGEX_CS[NUM_AGEX_CS_BITS],
/* MEM latches */
MEM_NPC,
MEM_ALU_RESULT,
MEM_ADDRESS,
MEM_CC,
MEM_IR,
MEM_DRID,
MEM_V,
MEM_CS[NUM_MEM_CS_BITS],
/* SR latches */
SR_NPC,
SR_DATA,
SR_ALU_RESULT,
SR_ADDRESS,
SR_IR,
SR_DRID,
SR_V,
SR_CS[NUM_SR_CS_BITS];
} PipeState_Entry;
/* data structure for latch */
PipeState_Entry PS, NEW_PS;
/* simulator signal */
int RUN_BIT;
/* Internal stall signals */
int dep_stall,
v_de_br_stall,
v_agex_br_stall,
v_mem_br_stall,
mem_stall,
icache_r;
/***************************************************************/
/* A cycle counter. */
/***************************************************************/
int CYCLE_COUNT;
/***************************************************************/
/* */
/* Procedure : help */
/* */
/* Purpose : Print out a list of commands. */
/* */
/***************************************************************/
void help() {
printf("----------------LC-3bSIM Help-------------------------\n");
printf("go - run program to completion \n");
printf("run n - execute program for n cycles \n");
printf("mdump low high - dump memory from low to high \n");
printf("rdump - dump the architectural state \n");
printf("idump - dump the internal state \n");
printf("? - display this help menu \n");
printf("quit - exit the program \n\n");
}
void print_CS(int *CS, int num)
{
int ii ;
for ( ii = 0 ; ii < num; ii++) {
printf("%d",CS[ii]);
}
printf("\n");
}
/***************************************************************/
/* */
/* Procedure : cycle */
/* */
/* Purpose : Execute a cycle */
/* */
/***************************************************************/
void cycle() {
NEW_PS = PS;
SR_stage();
MEM_stage();
AGEX_stage();
DE_stage();
FETCH_stage();
PS = NEW_PS;
CYCLE_COUNT++;
}
/***************************************************************/
/* */
/* Procedure : run n */
/* */
/* Purpose : Simulate the LC-3b for n cycles. */
/* */
/***************************************************************/
void run(int num_cycles) {
int i;
if (RUN_BIT == FALSE) {
printf("Can't simulate, Simulator is halted\n\n");
return;
}
printf("Simulating for %d cycles...\n\n", num_cycles);
for (i = 0; i < num_cycles; i++) {
if (PC == 0x0000) {
cycle();
RUN_BIT = FALSE;
printf("Simulator halted\n\n");
break;
}
cycle();
}
}
/***************************************************************/
/* */
/* Procedure : go */
/* */
/* Purpose : Simulate the LC-3b until HALTed. */
/* */
/***************************************************************/
void go() {
if ((RUN_BIT == FALSE) || (PC == 0x0000)) {
printf("Can't simulate, Simulator is halted\n\n");
return;
}
printf("Simulating...\n\n");
/* initialization */
while (PC != 0x0000)
cycle();
cycle();
RUN_BIT = FALSE;
printf("Simulator halted\n\n");
}
/***************************************************************/
/* */
/* Procedure : mdump */
/* */
/* Purpose : Dump a region of memory to the output file. */
/* */
/***************************************************************/
void mdump(FILE * dumpsim_file, int start, int stop) {
int address; /* this is a byte address */
printf("\nMemory content [0x%04x..0x%04x] :\n", start, stop);
printf("-------------------------------------\n");
for (address = (start >> 1); address <= (stop >> 1); address++)
printf(" 0x%04x (%d) : 0x%02x%02x\n", address << 1, address << 1, MEMORY[address][1], MEMORY[address][0]);
printf("\n");
/* dump the memory contents into the dumpsim file */
fprintf(dumpsim_file, "\nMemory content [0x%04x..0x%04x] :\n", start, stop);
fprintf(dumpsim_file, "-------------------------------------\n");
for (address = (start >> 1); address <= (stop >> 1); address++)
fprintf(dumpsim_file, " 0x%04x (%d) : 0x%02x%02x\n", address << 1, address << 1, MEMORY[address][1], MEMORY[address][0]);
fprintf(dumpsim_file, "\n");
fflush(dumpsim_file);
}
/***************************************************************/
/* */
/* Procedure : rdump */
/* */
/* Purpose : Dump current architectural state to the */
/* output file. */
/* */
/***************************************************************/
void rdump(FILE * dumpsim_file) {
int k;
printf("\nCurrent architectural state :\n");
printf("-------------------------------------\n");
printf("Cycle Count : %d\n", CYCLE_COUNT);
printf("PC : 0x%04x\n", PC);
printf("CCs: N = %d Z = %d P = %d\n", N, Z, P);
printf("Registers:\n");
for (k = 0; k < LC3b_REGS; k++)
printf("%d: 0x%04x\n", k, (REGS[k] & 0xFFFF));
printf("\n");
/* dump the state information into the dumpsim file */
fprintf(dumpsim_file, "\nCurrent architectural state :\n");
fprintf(dumpsim_file, "-------------------------------------\n");
fprintf(dumpsim_file, "Cycle Count : %d\n", CYCLE_COUNT);
fprintf(dumpsim_file, "PC : 0x%04x\n", PC);
fprintf(dumpsim_file, "CCs: N = %d Z = %d P = %d\n", N, Z, P);
fprintf(dumpsim_file, "Registers:\n");
for (k = 0; k < LC3b_REGS; k++)
fprintf(dumpsim_file, "%d: 0x%04x\n", k, (REGS[k] & 0xFFFF));
fprintf(dumpsim_file, "\n");
fflush(dumpsim_file);
}
/***************************************************************/
/* */
/* Procedure : idump */
/* */
/* Purpose : Dump current internal state to the */
/* output file. */
/* */
/***************************************************************/
void idump(FILE * dumpsim_file) {
int k;
printf("\nCurrent architectural state :\n");
printf("-------------------------------------\n");
printf("Cycle Count : %d\n", CYCLE_COUNT);
printf("PC : 0x%04x\n", PC);
printf("CCs: N = %d Z = %d P = %d\n", N, Z, P);
printf("Registers:\n");
for (k = 0; k < LC3b_REGS; k++)
printf("%d: 0x%04x\n", k, (REGS[k] & 0xFFFF));
printf("\n");
printf("------------- Stall Signals -------------\n");
printf("ICACHE_R : %d\n", icache_r);
printf("DEP_STALL : %d\n", dep_stall);
printf("V_DE_BR_STALL : %d\n", v_de_br_stall);
printf("V_AGEX_BR_STALL : %d\n", v_agex_br_stall);
printf("MEM_STALL : %d\n", mem_stall);
printf("V_MEM_BR_STALL : %d\n", v_mem_br_stall);
printf("\n");
printf("------------- DE Latches --------------\n");
printf("DE_NPC : 0x%04x\n", PS.DE_NPC );
printf("DE_IR : 0x%04x\n", PS.DE_IR );
printf("DE_V : %d\n", PS.DE_V);
printf("\n");
printf("------------- AGEX Latches --------------\n");
printf("AGEX_NPC : 0x%04x\n", PS.AGEX_NPC );
printf("AGEX_SR1 : 0x%04x\n", PS.AGEX_SR1 );
printf("AGEX_SR2 : 0x%04x\n", PS.AGEX_SR2 );
printf("AGEX_CC : %d\n", PS.AGEX_CC );
printf("AGEX_IR : 0x%04x\n", PS.AGEX_IR );
printf("AGEX_DRID : %d\n", PS.AGEX_DRID);
printf("AGEX_CS : ");
for ( k = 0 ; k < NUM_AGEX_CS_BITS; k++) {
printf("%d",PS.AGEX_CS[k]);
}
printf("\n");
printf("AGEX_V : %d\n", PS.AGEX_V);
printf("\n");
printf("------------- MEM Latches --------------\n");
printf("MEM_NPC : 0x%04x\n", PS.MEM_NPC );
printf("MEM_ALU_RESULT : 0x%04x\n", PS.MEM_ALU_RESULT );
printf("MEM_ADDRESS : 0x%04x\n", PS.MEM_ADDRESS );
printf("MEM_CC : %d\n", PS.MEM_CC );
printf("MEM_IR : 0x%04x\n", PS.MEM_IR );
printf("MEM_DRID : %d\n", PS.MEM_DRID);
printf("MEM_CS : ");
for ( k = 0 ; k < NUM_MEM_CS_BITS; k++) {
printf("%d",PS.MEM_CS[k]);
}
printf("\n");
printf("MEM_V : %d\n", PS.MEM_V);
printf("\n");
printf("------------- SR Latches --------------\n");
printf("SR_NPC : 0x%04x\n", PS.SR_NPC );
printf("SR_DATA : 0x%04x\n", PS.SR_DATA );
printf("SR_ALU_RESULT : 0x%04x\n", PS.SR_ALU_RESULT );
printf("SR_ADDRESS : 0x%04x\n", PS.SR_ADDRESS );
printf("SR_IR : 0x%04x\n", PS.SR_IR );
printf("SR_DRID : %d\n", PS.SR_DRID);
printf("SR_CS : ");
for ( k = 0 ; k < NUM_SR_CS_BITS; k++) {
printf("%d",PS.SR_CS[k]);
}
printf("\n");
printf("SR_V : %d\n", PS.SR_V);
printf("\n");
/* dump the state information into the dumpsim file */
fprintf(dumpsim_file, "\nCurrent register/bus values :\n");
fprintf(dumpsim_file,"\nCurrent architectural state :\n");
fprintf(dumpsim_file,"-------------------------------------\n");
fprintf(dumpsim_file,"Cycle Count : %d\n", CYCLE_COUNT);
fprintf(dumpsim_file,"PC : 0x%04x\n", PC);
fprintf(dumpsim_file,"CCs: N = %d Z = %d P = %d\n", N, Z, P);
fprintf(dumpsim_file,"Registers:\n");
for (k = 0; k < LC3b_REGS; k++)
fprintf(dumpsim_file,"%d: 0x%04x\n", k, (REGS[k] & 0xFFFF));
fprintf(dumpsim_file,"\n");
fprintf(dumpsim_file,"------------- Stall Signals -------------\n");
fprintf(dumpsim_file,"ICACHE_R : %d\n", icache_r);
fprintf(dumpsim_file,"DEP_STALL : %d\n", dep_stall);
fprintf(dumpsim_file,"V_DE_BR_STALL : %d\n", v_de_br_stall);
fprintf(dumpsim_file,"V_AGEX_BR_STALL : %d\n", v_agex_br_stall);
fprintf(dumpsim_file,"MEM_STALL : %d\n", mem_stall);
fprintf(dumpsim_file,"V_MEM_BR_STALL : %d\n", v_mem_br_stall);
fprintf(dumpsim_file,"\n");
fprintf(dumpsim_file,"------------- DE Latches --------------\n");
fprintf(dumpsim_file,"DE_NPC : 0x%04x\n", PS.DE_NPC );
fprintf(dumpsim_file,"DE_IR : 0x%04x\n", PS.DE_IR );
fprintf(dumpsim_file,"DE_V : %d\n", PS.DE_V);
fprintf(dumpsim_file,"\n");
fprintf(dumpsim_file,"------------- AGEX Latches --------------\n");
fprintf(dumpsim_file,"AGEX_NPC : 0x%04x\n", PS.AGEX_NPC );
fprintf(dumpsim_file,"AGEX_SR1 : 0x%04x\n", PS.AGEX_SR1 );
fprintf(dumpsim_file,"AGEX_SR2 : 0x%04x\n", PS.AGEX_SR2 );
fprintf(dumpsim_file,"AGEX_CC : %d\n", PS.AGEX_CC );
fprintf(dumpsim_file,"AGEX_IR : 0x%04x\n", PS.AGEX_IR );
fprintf(dumpsim_file,"AGEX_DRID : %d\n", PS.AGEX_DRID);
fprintf(dumpsim_file,"AGEX_CS : ");
for ( k = 0 ; k < NUM_AGEX_CS_BITS; k++) {
fprintf(dumpsim_file,"%d",PS.AGEX_CS[k]);
}
fprintf(dumpsim_file,"\n");
fprintf(dumpsim_file,"AGEX_V : %d\n", PS.AGEX_V);
fprintf(dumpsim_file,"\n");
fprintf(dumpsim_file,"------------- MEM Latches --------------\n");
fprintf(dumpsim_file,"MEM_NPC : 0x%04x\n", PS.MEM_NPC );
fprintf(dumpsim_file,"MEM_ALU_RESULT : 0x%04x\n", PS.MEM_ALU_RESULT );
fprintf(dumpsim_file,"MEM_ADDRESS : 0x%04x\n", PS.MEM_ADDRESS );
fprintf(dumpsim_file,"MEM_CC : %d\n", PS.MEM_CC );
fprintf(dumpsim_file,"MEM_IR : 0x%04x\n", PS.MEM_IR );
fprintf(dumpsim_file,"MEM_DRID : %d\n", PS.MEM_DRID);
fprintf(dumpsim_file,"MEM_CS : ");
for ( k = 0 ; k < NUM_MEM_CS_BITS; k++) {
fprintf(dumpsim_file,"%d",PS.MEM_CS[k]);
}
fprintf(dumpsim_file,"\n");
fprintf(dumpsim_file,"MEM_V : %d\n", PS.MEM_V);
fprintf(dumpsim_file,"\n");
fprintf(dumpsim_file,"------------- SR Latches --------------\n");
fprintf(dumpsim_file,"SR_NPC : 0x%04x\n", PS.SR_NPC );
fprintf(dumpsim_file,"SR_DATA : 0x%04x\n",PS.SR_DATA );
fprintf(dumpsim_file,"SR_ALU_RESULT : 0x%04x\n", PS.SR_ALU_RESULT );
fprintf(dumpsim_file,"SR_ADDRESS : 0x%04x\n", PS.SR_ADDRESS );
fprintf(dumpsim_file,"SR_IR : 0x%04x\n", PS.SR_IR );
fprintf(dumpsim_file,"SR_DRID : %d\n", PS.SR_DRID);
fprintf(dumpsim_file,"SR_CS : ");
for ( k = 0 ; k < NUM_SR_CS_BITS; k++) {
fprintf(dumpsim_file, "%d",PS.SR_CS[k]);
}
fprintf(dumpsim_file,"\n");
fprintf(dumpsim_file,"SR_V : %d\n", PS.SR_V);
fprintf(dumpsim_file,"\n");
fflush(dumpsim_file);
}
/***************************************************************/
/* */
/* Procedure : get_command */
/* */
/* Purpose : Read a command from standard input. */
/* */
/***************************************************************/
void get_command(FILE * dumpsim_file) {
char buffer[20];
int start, stop, cycles;
printf("LC-3b-SIM> ");
scanf("%s", buffer);
printf("\n");
switch(buffer[0]) {
case 'G':
case 'g':
go();
break;
case 'M':
case 'm':
scanf("%i %i", &start, &stop);
mdump(dumpsim_file, start, stop);
break;
case '?':
help();
break;
case 'Q':
case 'q':
printf("Bye.\n");
exit(0);
case 'R':
case 'r':
if (buffer[1] == 'd' || buffer[1] == 'D')
rdump(dumpsim_file);
else {
scanf("%d", &cycles);
run(cycles);
}
break;
case 'I':
case 'i':
idump(dumpsim_file);
break;
default:
printf("Invalid Command\n");
break;
}
}
/***************************************************************/
/* */
/* Procedure : init_control_store */
/* */
/* Purpose : Load microprogram into control store ROM */
/* */
/***************************************************************/
void init_control_store(char *ucode_filename) {
FILE *ucode;
int i, j, index;
char line[200];
printf("Loading Control Store from file: %s\n", ucode_filename);
/* Open the micro-code file. */
if ((ucode = fopen(ucode_filename, "r")) == NULL) {
printf("Error: Can't open micro-code file %s\n", ucode_filename);
exit(-1);
}
/* Read a line for each row in the control store. */
for(i = 0; i < CONTROL_STORE_ROWS; i++) {
if (fscanf(ucode, "%[^\n]\n", line) == EOF) {
printf("Error: Too few lines (%d) in micro-code file: %s\n",
i, ucode_filename);
exit(-1);
}
/* Put in bits one at a time. */
index = 0;
for (j = 0; j < NUM_CONTROL_STORE_BITS; j++) {
/* Needs to find enough bits in line. */
if (line[index] == '\0') {
printf("Error: Too few control bits in micro-code file: %s\nLine: %d\n",
ucode_filename, i);
exit(-1);
}
if (line[index] != '0' && line[index] != '1') {
printf("Error: Unknown value in micro-code file: %s\nLine: %d, Bit: %d\n",
ucode_filename, i, j);
exit(-1);
}
/* Set the bit in the Control Store. */
CONTROL_STORE[i][j] = (line[index] == '0') ? 0:1;
index++;
}
/* Warn about extra bits in line. */
if (line[index] != '\0')
printf("Warning: Extra bit(s) in control store file %s. Line: %d\n",
ucode_filename, i);
}
printf("\n");
}
/***************************************************************/
/* */
/* Procedure : init_memory */
/* */
/* Purpose : Zero out the memory array */
/* */
/***************************************************************/
void init_memory() {
int i;
for (i=0; i < WORDS_IN_MEM; i++) {
MEMORY[i][0] = 0;
MEMORY[i][1] = 0;
}
}
/***************************************************************/
/* */
/* Procedure : init_state */
/* */
/* Purpose : Zero out all latches and registers */
/* */
/***************************************************************/
void init_state() {
memset(&PS, 0 ,sizeof(PipeState_Entry));
memset(&NEW_PS, 0 , sizeof(PipeState_Entry));
dep_stall = 0;
v_de_br_stall = 0;
v_agex_br_stall = 0;
v_mem_br_stall = 0;
mem_stall = 0;
}
/**************************************************************/
/* */
/* Procedure : load_program */
/* */
/* Purpose : Load program and service routines into mem. */
/* */
/**************************************************************/
void load_program(char *program_filename) {
FILE * prog;
int ii, word, program_base;
/* Open program file. */
prog = fopen(program_filename, "r");
if (prog == NULL) {
printf("Error: Can't open program file %s\n", program_filename);
exit(-1);
}
/* Read in the program. */
if (fscanf(prog, "%x\n", &word) != EOF)
program_base = word >> 1 ;
else {
printf("Error: Program file is empty\n");
exit(-1);
}
ii = 0;
while (fscanf(prog, "%x\n", &word) != EOF) {
/* Make sure it fits. */
if (program_base + ii >= WORDS_IN_MEM) {
printf("Error: Program file %s is too long to fit in memory. %x\n",
program_filename, ii);
exit(-1);
}
/* Write the word to memory array. */
MEMORY[program_base + ii][0] = word & 0x00FF;
MEMORY[program_base + ii][1] = (word >> 8) & 0x00FF;
ii++;
}
if (PC == 0) PC = program_base << 1 ;
printf("Read %d words from program into memory.\n\n", ii);
}
/***************************************************************/
/* */
/* Procedure : initialize */
/* */
/* Purpose : Load microprogram and machine language program */
/* and set up initial state of the machine. */
/* */
/***************************************************************/
void initialize(char *ucode_filename, char *program_filename, int num_prog_files) {
int i;
init_control_store(ucode_filename);
init_memory();
for ( i = 0; i < num_prog_files; i++ ) {
load_program(program_filename);
while(*program_filename++ != '\0');
}
init_state();
RUN_BIT = TRUE;
}
/***************************************************************/
/* */
/* dcache_access */
/* */
/***************************************************************/
void dcache_access(int dcache_addr, int *read_word, int write_word, int *dcache_r,
int mem_w0, int mem_w1) {
int addr = dcache_addr >> 1 ;
int random = CYCLE_COUNT % 9;
if (!random) {
*dcache_r = 0;
*read_word = 0xfeed ;
}
else {
*dcache_r = 1;
*read_word = (MEMORY[addr][1] << 8) | (MEMORY[addr][0] & 0x00FF);
if(mem_w0) MEMORY[addr][0] = write_word & 0x00FF;
if(mem_w1) MEMORY[addr][1] = (write_word & 0xFF00) >> 8;
}
}
/***************************************************************/
/* */
/* icache_access */
/* */
/***************************************************************/
void icache_access(int icache_addr, int *read_word, int *icache_r) {
int addr = icache_addr >> 1 ;
int random = CYCLE_COUNT % 13;
if (!random) {
*icache_r = 0;
*read_word = 0xfeed;
}
else {
*icache_r = 1;
*read_word = MEMORY[addr][1] << 8 | MEMORY[addr][0];
}
}
/***************************************************************/
/* */
/* Procedure : main */
/* */
/***************************************************************/
int main(int argc, char *argv[]) {
FILE * dumpsim_file;
/* Error Checking */
if (argc < 3) {
printf("Error: usage: %s <micro_code_file> <program_file_1> <program_file_2> ...\n",
argv[0]);
exit(1);
}
printf("LC-3b Simulator\n\n");
initialize(argv[1], argv[2], argc - 2);
if ( (dumpsim_file = fopen( "dumpsim", "w" )) == NULL ) {
printf("Error: Can't open dumpsim file\n");
exit(-1);
}
while (1)
get_command(dumpsim_file);
}
/***************************************************************/
/* Do not modify the above code.
You are allowed to use the following global variables in your
code. These are defined above.
RUN_BIT
REGS
MEMORY
PC
N
Z
P
dep_stall
v_de_br_stall
v_agex_br_stall
v_mem_br_stall
mem_stall
icache_r
PS
NEW_PS
You may define your own local/global variables and functions.
You may use the functions to get at the control bits defined
above.
Begin your code here */
/***************************************************************/
#define COPY_AGEX_CS_START 3
#define COPY_MEM_CS_START 9
#define COPY_SR_CS_START 7
/* Signals generated by SR stage and needed by previous stages in the
pipeline are declared below. */
int sr_reg_data,
sr_n, sr_z, sr_p,
v_sr_ld_cc,
v_sr_ld_reg,
sr_reg_id;
int mem_pcmux = 0;
int mem_target_pc;
int mem_trap_pc;
int v_mem_ld_cc;
int v_mem_ld_reg;
int v_agex_ld_cc;
int v_agex_ld_reg;
int read_word;
int read_instruction;
int dcache_r;
/************************* SR_stage() *************************/
void SR_stage() {
/* You are given the code for SR_stage to get you started. Look at
the figure for SR stage to see how this code is implemented. */
switch (Get_DR_VALUEMUX1(PS.SR_CS))
{
case 0:
sr_reg_data = PS.SR_ADDRESS ;
break;
case 1:
sr_reg_data = PS.SR_DATA ;
break;
case 2:
sr_reg_data = PS.SR_NPC ;
break;
case 3:
sr_reg_data = PS.SR_ALU_RESULT ;
break;
}
sr_reg_id = PS.SR_DRID;
v_sr_ld_reg = Get_SR_LD_REG(PS.SR_CS) & PS.SR_V;
v_sr_ld_cc = Get_SR_LD_CC(PS.SR_CS) & PS.SR_V ;
/* CC LOGIC */
sr_n = ((sr_reg_data & 0x8000) ? 1 : 0);
sr_z = ((sr_reg_data & 0xFFFF) ? 0 : 1);
sr_p = 0;
if ((!sr_n) && (!sr_z))
sr_p = 1;
}
/************************* MEM_stage() *************************/
void MEM_stage() {
int ii,jj = 0;
/* your code for MEM stage goes here */
if(Get_DCACHE_EN(PS.MEM_CS) && PS.MEM_V){
int we0 = Get_DCACHE_RW(PS.MEM_CS);
int we1 = Get_DCACHE_RW(PS.MEM_CS) && Get_DATA_SIZE(PS.MEM_CS);
dcache_access(PS.MEM_ADDRESS, &read_word, PS.MEM_ALU_RESULT, &dcache_r, we0, we1);
mem_stall = !dcache_r;
}
if(PS.MEM_V){
if(Get_BR_OP(PS.MEM_CS)){
if(PS.MEM_CC == PS.MEM_IR) {
mem_pcmux = 0x01;
v_mem_br_stall = 1;
}
}
else if(Get_UNCOND_OP(PS.MEM_CS)) {
mem_pcmux = 0x01;
v_mem_br_stall = 1;
}
else if(Get_TRAP_OP(PS.MEM_CS)) {
mem_pcmux = 0x02;
v_mem_br_stall = 1;
}
else {
mem_pcmux = 0x00;
v_mem_br_stall = 0;
}
}
v_mem_ld_cc = Get_MEM_LD_CC(PS.MEM_CS) && PS.MEM_V;
v_mem_ld_reg = Get_MEM_LD_REG(PS.MEM_CS) && PS.MEM_V;
NEW_PS.SR_V = !mem_stall && PS.MEM_V;
NEW_PS.SR_ADDRESS = PS.MEM_ADDRESS;
NEW_PS.SR_ALU_RESULT = PS.MEM_ALU_RESULT;
if(Get_DATA_SIZE(PS.MEM_CS))
NEW_PS.SR_DATA = read_word;
else
NEW_PS.SR_DATA = read_word & 0xFF;
NEW_PS.SR_NPC = PS.MEM_NPC;
NEW_PS.SR_IR = PS.MEM_IR;
NEW_PS.SR_DRID = PS.MEM_DRID;
mem_target_pc = PS.MEM_ADDRESS;
mem_trap_pc = NEW_PS.SR_DATA;
/* The code below propagates the control signals from MEM.CS latch
to SR.CS latch. You still need to latch other values into the
other SR latches. */
for (ii=COPY_SR_CS_START; ii < NUM_MEM_CS_BITS; ii++) {
NEW_PS.SR_CS [jj++] = PS.MEM_CS [ii];
}
}