From 0c590abf12554eb9a07e98290b8d3c2715f6947f Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Wed, 10 Jun 2020 03:16:55 +0300 Subject: [PATCH] Update colorlight_5a_75b target: add 5A-75E board support --- litex_boards/targets/colorlight_5a_75b.py | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/litex_boards/targets/colorlight_5a_75b.py b/litex_boards/targets/colorlight_5a_75b.py index 543170476..a6f03d662 100755 --- a/litex_boards/targets/colorlight_5a_75b.py +++ b/litex_boards/targets/colorlight_5a_75b.py @@ -30,6 +30,9 @@ # ./colorlight_5a_75b.py --load # You should see the LiteX BIOS and be able to interact with it. # +# Note that you can also use a 5A-75E board: +# ./colorlight_5a_75b.py --board=5A-75E --revision=7.1 +# # Disclaimer: SoC 2) is still a Proof of Concept with large timings violations on the IP/UDP and # Etherbone stack that need to be optimized. It was initially just used to validate the reversed # pinout but happens to work on hardware... @@ -43,7 +46,7 @@ from litex.build.io import DDROutput -from litex_boards.platforms import colorlight_5a_75b +from litex_boards.platforms import colorlight_5a_75b, colorlight_5a_75e from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -92,8 +95,13 @@ def __init__(self, platform, sys_clk_freq, with_usb_pll=False, with_rst=True): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, revision, with_ethernet=False, with_etherbone=False, sys_clk_freq=60e6, **kwargs): - platform = colorlight_5a_75b.Platform(revision=revision) + def __init__(self, board, revision, with_ethernet=False, with_etherbone=False, sys_clk_freq=60e6, **kwargs): + assert board in ["5A-75B", "5A-75E"] + if board == "5A-75B": + platform = colorlight_5a_75b.Platform(revision=revision) + elif board == "5A-75E": + platform = colorlight_5a_75e.Platform(revision=revision) + if with_etherbone: sys_clk_freq = int(125e6) @@ -138,6 +146,7 @@ def main(): trellis_args(parser) parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--board", default="5A-75B", help="Board type: 5A-75B (default) or 5A-75E") parser.add_argument("--revision", default="7.0", type=str, help="Board revision 7.0 (default) or 6.1") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") @@ -146,7 +155,7 @@ def main(): args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) - soc = BaseSoC(revision=args.revision, + soc = BaseSoC(board=args.board, revision=args.revision, with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, sys_clk_freq = args.sys_clk_freq,