diff --git a/litex_boards/platforms/mist.py b/litex_boards/platforms/mist.py new file mode 100644 index 000000000..db2e35c52 --- /dev/null +++ b/litex_boards/platforms/mist.py @@ -0,0 +1,96 @@ +# +# This file is part of LiteX-Boards. +# +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.generic_platform import * +from litex.build.altera import AlteraPlatform +from litex.build.altera.programmer import USBBlaster + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + ("clk27", 0, Pins("54")), + ("clk27", 0, Pins("54")), + + ("user_led", 0, Pins("7"), + Misc("CURRENT_STRENGTH_NEW 4MA")), + + ("vga", 0, + Subsignal("r", Pins("135 137 141 142 143 144")), + Subsignal("g", Pins("106 110 111 112 113 114")), + Subsignal("b", Pins("115 120 121 125 132 133")), + Subsignal("vsync", Pins("136")), + Subsignal("hsync", Pins("119")), + Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), + ), + + ("audio", 0, + Subsignal("l", Pins("65")), + Subsignal("r", Pins("80")), + Misc("CURRENT_STRENGTH_NEW 4MA"), + ), + + ("serial", 0, + Subsignal("tx", Pins("46")), + Subsignal("rx", Pins("31")), + ), + + ("spi", 0, + Subsignal("do", Pins("105")), + Subsignal("di", Pins("88")), + Subsignal("sck", Pins("126")), + Subsignal("ss2", Pins("127")), + Subsignal("ss3", Pins("91")), + Subsignal("ss4", Pins("90")), + ), + + ("conf_data0", 0, Pins("13")), + + ("sdram_clock", 0, Pins("43"), + Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), IOStandard("3.3-V LVTTL")), + ("sdram", 0, + Subsignal("a", Pins("49 44 42 39 4 6 8 10 11 28 50 30 32")), + Subsignal("dq", Pins("83 79 77 76 72 71 69 68 86 87 98 99 100 101 103 104"), + Misc("FAST_INPUT_REGISTER ON"), Misc("FAST_OUTPUT_ENABLE_REGISTER ON")), + Subsignal("ba", Pins("58 51")), + Subsignal("dm", Pins("67 85")), # DQML, DQMH + Subsignal("ras_n", Pins("60")), + Subsignal("cas_n", Pins("64")), + Subsignal("we_n", Pins("66")), + Subsignal("cs_n", Pins("59")), + Subsignal("cke", Pins("33")), + Misc("FAST_OUTPUT_REGISTER ON"), + Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), + ), +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(AlteraPlatform): + default_clk_name = "clk27" + default_clk_period = 1e9/27e6 + + def __init__(self): + AlteraPlatform.__init__(self, "EP3C25E144C8", _io) + self.add_platform_command("set_global_assignment -name FAMILY \"Cyclone III\"") + self.add_platform_command("set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144") + self.add_platform_command("set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED") + self.add_platform_command("set_global_assignment -name USE_CONFIGURATION_DEVICE OFF") + self.add_platform_command("set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME \"PASSIVE SERIAL\"") + self.add_platform_command("set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP \"AS INPUT TRI-STATED\"") + self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"") + self.add_platform_command("set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION \"USE AS REGULAR IO\"") + self.add_platform_command("set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION \"USE AS REGULAR IO\"") + self.add_platform_command("set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION \"USE AS REGULAR IO\"") + self.add_platform_command("set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION \"USE AS REGULAR IO\"") + self.add_platform_command("set_global_assignment -name STRATIX_DEVICE_IO_STANDARD \"3.3-V LVTTL\"") + + def create_programmer(self): + return USBBlaster() + + def do_finalize(self, fragment): + AlteraPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk27", 0, loose=True), 1e9/27e6) + self.add_period_constraint(self.lookup_request("clk27", 1, loose=True), 1e9/27e6) + diff --git a/litex_boards/targets/mist.py b/litex_boards/targets/mist.py new file mode 100755 index 000000000..b79e6e8a9 --- /dev/null +++ b/litex_boards/targets/mist.py @@ -0,0 +1,121 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# SPDX-License-Identifier: BSD-2-Clause + +import os +import argparse + +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex.build.io import DDROutput + +from litex_boards.platforms import mist + +from litex.soc.cores.clock import CycloneIVPLL +from litex.soc.integration.soc import SoCRegion +from litex.soc.integration.soc_core import * +from litex.soc.integration.soc_sdram import * +from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser + +from litedram.modules import MT48LC16M16 +from litedram.phy import GENSDRPHY + +from litevideo.terminal.core import Terminal + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) + self.clock_domains.cd_vga = ClockDomain(reset_less=True) + + # # # + + # Clk / Rst + clk27 = platform.request("clk27") + + # PLL + self.submodules.pll = pll = CycloneIVPLL(speedgrade="-8") + pll.register_clkin(clk27, 27e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) + pll.create_clkout(self.cd_vga, 25e6) + + # SDRAM clock + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(50e6), with_vga=False, **kwargs): + platform = mist.Platform() + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on MIST", + ident_version = True, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + # SDR SDRAM -------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + self.add_sdram("sdram", + phy = self.sdrphy, + module = MT48LC16M16(sys_clk_freq, "1:1"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x2000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) + + # VGA Terminal ----------------------------------------------------------------------------- + if with_vga: + self.submodules.terminal = terminal = Terminal() + self.bus.add_slave("terminal", self.terminal.bus, region=SoCRegion(origin=0x30000000, size=0x10000)) + vga_pads = platform.request("vga") + self.comb += [ + vga_pads.vsync.eq(terminal.vsync), + vga_pads.hsync.eq(terminal.hsync), + vga_pads.r.eq(terminal.red[2:8]), + vga_pads.g.eq(terminal.green[2:8]), + vga_pads.b.eq(terminal.blue[2:8]) + ] + + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + +# Build -------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on MIST") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + builder_args(parser) + soc_sdram_args(parser) + parser.add_argument("--with-vga", action="store_true", help="Enable VGA support") + args = parser.parse_args() + + soc = BaseSoC(with_vga=args.with_vga, **soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build(run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof")) + +if __name__ == "__main__": + main() + diff --git a/test/test_targets.py b/test/test_targets.py index a4bda1df2..4e9a80685 100644 --- a/test/test_targets.py +++ b/test/test_targets.py @@ -72,6 +72,9 @@ def test_simple(self): # Xilinx Virtex Ultrascale+ platforms.append("vcu118") + # Intel Cyclone3 + platforms.append("mist") + # Intel Cyclone4 platforms.append("de0nano") platforms.append("de2_115")