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LLVM ERROR: Error while trying to spill X9 from class GPR64: Cannot scavenge register without an emergency spill slot! #63358
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@llvm/issue-subscribers-backend-aarch64 |
I've reduced the test case. |
I'd like to work on this issue.. |
One more case. define i32 @f(ptr %A12, ptr %G.9, ptr %G.7, ptr %A, i64 %LGV4, i64 %LGV2, ptr %G, ptr %RP, ptr %G1, i1 %B4, ptr %G.1, ptr %A7, ptr %A5, i1 %C1, ptr %A13, i1 %C8) {
BB:
%A55 = alloca i1, i32 0, align 1
%G8 = getelementptr i16, ptr %A55, i16 256
br label %BB1
BB1: ; preds = %BB1, %BB
%B5 = srem i64 1, %LGV2
store double 1.000000e+00, ptr %A, align 8
store i1 %B4, ptr %G.1, align 1
store i64 %B5, ptr %G8, align 4
store i16 0, ptr %G.7, align 2
store i64 %LGV4, ptr %A12, align 4
store i64 0, ptr %A7, align 4
store i1 false, ptr %G.9, align 1
store i1 %C8, ptr %RP, align 1
store i1 %C1, ptr %A13, align 1
store i8 1, ptr %A5, align 1
store i1 false, ptr %G1, align 1
store i64 0, ptr %G, align 4
br label %BB1
} |
Thanks for reduced testCase.. |
define i32 @f(ptr %G11, ptr %G.5, ptr %A, i1 %C6, ptr %G.4, ptr %A12, ptr %A7, ptr %G.10, ptr %G.9, i64 %LGV4, i64 %LGV2, i64 %L8, ptr %G14, i16 %LGV3, i16 %L5, i16 %L7, i1 %C8) {
BB:
%A57 = alloca i1, i32 0, align 1
%G8 = getelementptr i16, ptr %A57, i16 256
%B16 = urem i16 %LGV3, %L5
%B5 = mul i64 %LGV4, %LGV2
store i64 %B5, ptr %G8, align 4
store i16 %L7, ptr %G14, align 2
store i64 %L8, ptr %G.9, align 4
store i64 %LGV4, ptr %A7, align 4
store i1 true, ptr %G.5, align 1
store float 0.000000e+00, ptr %A, align 4
store i1 %C8, ptr %G.10, align 1
store i16 %B16, ptr %G.4, align 2
store i64 %LGV2, ptr %G11, align 4
store float 0.000000e+00, ptr %A12, align 4
store i1 %C6, ptr %G11, align 1
ret i32 0
} |
Can we close this issue, Failure seems to fix now.. |
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https://godbolt.org/z/on75qaP41
May be related to #63357.
The text was updated successfully, but these errors were encountered: