From c39bc13f60ff9a63eadafe96c7a8705ffabfcfb0 Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Fri, 15 Nov 2024 12:02:15 +0100 Subject: [PATCH 1/8] [hw,pinmux] Gate countermeasures only used for HW strampling Signed-off-by: Robert Schilling --- hw/ip_templates/pinmux/data/pinmux.hjson.tpl | 2 ++ ...sec_cm_testplan.hjson => pinmux_sec_cm_testplan.hjson.tpl} | 2 ++ hw/ip_templates/pinmux/pinmux.core.tpl | 2 ++ ...{pinmux_strap_sampling.sv => pinmux_strap_sampling.sv.tpl} | 4 ++++ 4 files changed, 10 insertions(+) rename hw/ip_templates/pinmux/data/{pinmux_sec_cm_testplan.hjson => pinmux_sec_cm_testplan.hjson.tpl} (98%) rename hw/ip_templates/pinmux/rtl/{pinmux_strap_sampling.sv => pinmux_strap_sampling.sv.tpl} (99%) diff --git a/hw/ip_templates/pinmux/data/pinmux.hjson.tpl b/hw/ip_templates/pinmux/data/pinmux.hjson.tpl index 15516aa4e8d28..00bab6fa8ed0e 100644 --- a/hw/ip_templates/pinmux/data/pinmux.hjson.tpl +++ b/hw/ip_templates/pinmux/data/pinmux.hjson.tpl @@ -399,6 +399,7 @@ { name: "BUS.INTEGRITY", desc: "End-to-end bus integrity scheme." } + % if enable_strap_sampling: { name: "LC_DFT_EN.INTERSIG.MUBI", desc: "The life cycle DFT enable signal is multibit encoded." } @@ -425,6 +426,7 @@ the DFT TAP can only be selected when LC_DFT_EN is asserted. ''' } + % endif ] registers: [ diff --git a/hw/ip_templates/pinmux/data/pinmux_sec_cm_testplan.hjson b/hw/ip_templates/pinmux/data/pinmux_sec_cm_testplan.hjson.tpl similarity index 98% rename from hw/ip_templates/pinmux/data/pinmux_sec_cm_testplan.hjson rename to hw/ip_templates/pinmux/data/pinmux_sec_cm_testplan.hjson.tpl index 61987929469c8..3fbe5a9547ec0 100644 --- a/hw/ip_templates/pinmux/data/pinmux_sec_cm_testplan.hjson +++ b/hw/ip_templates/pinmux/data/pinmux_sec_cm_testplan.hjson.tpl @@ -29,6 +29,7 @@ stage: V2S tests: [] } + % if enable_strap_sampling: { name: sec_cm_lc_dft_en_intersig_mubi desc: "Verify the countermeasure(s) LC_DFT_EN.INTERSIG.MUBI." @@ -65,5 +66,6 @@ stage: V2S tests: [] } + % endif ] } diff --git a/hw/ip_templates/pinmux/pinmux.core.tpl b/hw/ip_templates/pinmux/pinmux.core.tpl index 0552e86fcd710..1653720140fc4 100644 --- a/hw/ip_templates/pinmux/pinmux.core.tpl +++ b/hw/ip_templates/pinmux/pinmux.core.tpl @@ -28,7 +28,9 @@ filesets: - rtl/pinmux_wkup.sv - rtl/pinmux_jtag_buf.sv - rtl/pinmux_jtag_breakout.sv + % if enable_strap_sampling: - rtl/pinmux_strap_sampling.sv + % endif - rtl/pinmux.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/pinmux/rtl/pinmux_strap_sampling.sv b/hw/ip_templates/pinmux/rtl/pinmux_strap_sampling.sv.tpl similarity index 99% rename from hw/ip_templates/pinmux/rtl/pinmux_strap_sampling.sv rename to hw/ip_templates/pinmux/rtl/pinmux_strap_sampling.sv.tpl index 5e86371390854..5ce5c524cc7ac 100644 --- a/hw/ip_templates/pinmux/rtl/pinmux_strap_sampling.sv +++ b/hw/ip_templates/pinmux/rtl/pinmux_strap_sampling.sv.tpl @@ -181,7 +181,9 @@ module pinmux_strap_sampling .lc_en_o(pinmux_hw_debug_en) ); +% if enable_strap_sampling: // SEC_CM: PINMUX_HW_DEBUG_EN.INTERSIG.MUBI +% endif // We send this latched version over to the RV_DM in order to gate the JTAG signals and TAP side. // Note that the bus side will remain gated with the live lc_hw_debug_en value inside RV_DM. assign pinmux_hw_debug_en_o = pinmux_hw_debug_en[HwDebugEnRvDmOut]; @@ -224,7 +226,9 @@ module pinmux_strap_sampling logic [NTapStraps-1:0] tap_strap_d, tap_strap_q; logic [NDFTStraps-1:0] dft_strap_d, dft_strap_q; +% if enable_strap_sampling: // SEC_CM: TAP.MUX.LC_GATED +% endif // The LC strap at index 0 has a slightly different // enable condition than the DFT strap at index 1. assign tap_strap_d[0] = (lc_strap_sample_en) ? in_padring_i[TargetCfg.tap_strap0_idx] : From 09ea55133f5162457435758c4fc788069dde9090 Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Fri, 15 Nov 2024 11:30:19 +0100 Subject: [PATCH 2/8] [darjeeling] Add HJSON files to define Darjeeling Add top_darjeeling.hjson and all xbar.hjson files. Signed-off-by: Robert Schilling --- hw/top_darjeeling/data/top_darjeeling.hjson | 1788 +++++++++++++++++++ hw/top_darjeeling/data/xbar_dbg.hjson | 47 + hw/top_darjeeling/data/xbar_main.hjson | 425 +++++ hw/top_darjeeling/data/xbar_mbx.hjson | 91 + hw/top_darjeeling/data/xbar_peri.hjson | 150 ++ 5 files changed, 2501 insertions(+) create mode 100644 hw/top_darjeeling/data/top_darjeeling.hjson create mode 100644 hw/top_darjeeling/data/xbar_dbg.hjson create mode 100644 hw/top_darjeeling/data/xbar_main.hjson create mode 100644 hw/top_darjeeling/data/xbar_mbx.hjson create mode 100644 hw/top_darjeeling/data/xbar_peri.hjson diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson new file mode 100644 index 0000000000000..6db1371baa1fb --- /dev/null +++ b/hw/top_darjeeling/data/top_darjeeling.hjson @@ -0,0 +1,1788 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// TOP Darjeeling configuration +{ name: "darjeeling", + type: "top", + + ///////////////////////////////////////////////////////////// + // 256 bit seed for compile-time random constants // + // NOTE: REPLACE THIS WITH A NEW VALUE BEFORE THE TAPEOUT // + ///////////////////////////////////////////////////////////// + rnd_cnst_seed: 1017106219537032642877583828875051302543807092889754935647094601236425074047, + + // 32-bit datawidth + datawidth: "32", + + // Power information for the design + power: { + // Power domains supported by the design + // Aon represents domain aon + // 0 represents domain 0 + domains: ["Aon", "0"], + + // Default power domain used for the design + default: "0" + + // Wait for external resets for integrated OpenTitan + wait_for_external_reset: true + }, + + // This is the clock data structure of the design. + // The hier path refers to the clock reference path (struct / port) + // - The top/ext desgination follows the same scheme as inter-module + // The src key indicates the raw clock sources in the design + // The groups key indicates the various clock groupings in the design + clocks: { + + hier_paths: { + top: "clkmgr_aon_clocks.", // top level is a struct + ext: "", // ext is a port of the clock name + lpg: "clkmgr_aon_cg_en.", // top level struct for alert lpg reset enables + }, + + // Clock Source attributes + // name: Name of group. + // aon: Whether the clock is free running all the time. + // If it is, the clock is not hanlded by clkmgr. + // freq: Absolute frequency of clk in Hz + // ref: indicates the clock is used as a reference for measurement. + srcs: [ + { name: "main", aon: "no", freq: "100000000" } + { name: "io", aon: "no", freq: "96000000" } + { name: "usb", aon: "no", freq: "48000000" } + { name: "aon", aon: "yes", freq: "200000", ref: true} + ], + + // Derived clock source attributes + // name: Name of group. + // aon: Whether the clock is free running all the time. + // If it is, the clock is not hanlded by clkmgr. + // freq: Absolute frequency of clk in Hz + // src: From which clock source is the clock derived + // div: Ratio between derived clock and source clock + derived_srcs: [ + { name: "io_div2", aon: "no", div: 2, src: "io", freq: "48000000" } + { name: "io_div4", aon: "no", div: 4, src: "io", freq: "24000000" } + ], + + // Clock Group attributes + // name: name of group. + // + // src: The hierarchical source of the clock + // "ext" - clock is supplied from a port of the top module + // "top" - clock is supplied from a net inside the top module + // + // sw_cg: whether software is allowed to gate the clock + // "no" - software is not allowed to gate clocks + // "yes" - software is allowed to gate clocks + // "hint" - software can provide a hint, and hw controls the rest + // + // unique: whether each module in the group can be separately gated + // if sw_cg is "no", this field has no meaning + // "yes" - each clock is individually controlled + // "no" - the group is controlled as one single unit + // + // The powerup and proc groups are unique. + // The powerup group of clocks do not feed through the clock + // controller as they manage clock controller behavior + // The proc group is not peripheral, and directly hardwired + + groups: [ + // the powerup group is used exclusively by clk/pwr/rstmgr/pinmux + { name: "ast", src:"ext", sw_cg: "no" } + { name: "powerup", src:"top", sw_cg: "no" } + { name: "trans", src:"top", sw_cg: "hint", unique: "yes", } + { name: "infra", src:"top", sw_cg: "no", } + { name: "secure", src:"top", sw_cg: "no" } + { name: "peri", src:"top", sw_cg: "yes", unique: "no" } + { name: "timers", src:"top", sw_cg: "no" } + ], + }, + + // This is the reset data structure of the design. + // The hier path refers to the reset reference path (struct / port) + // - The top/ext desgination follows the same scheme as inter-module + // The node key represents all the known resets in the design + resets: { + // Discrete OpenTitan does not need to wait for external resets + wait_for_external_reset: false, + + hier_paths: { + top: "rstmgr_aon_resets.", // top level is a struct + ext: "", // ext is a port of the clock name + lpg: "rstmgr_aon_rst_en.", // top level struct for alert lpg reset enables + }, + + // Reset node attributes + // name: name of reset. + // + // gen: whether the reset is generated + // true: it is a generated reset inside rstmgr + // false: it is a hardwired design reset inside rstmgr (roots and por) + // For non-generated resets, the parent / domain definitions have no meaning. + // + // type: the reset type [ext, top] + // ext: the reset is coming in from the ports, external to darjeeling + // int: the reset is only used inside rstmgr + // top: the reset is output from rstmgr to top level struct + // + // parent: The parent reset + // If type is "ext", there is no root, since it is external + // + // domains: The power domains of a particular reset + // This is a list of the supported power domains. + // Valid values are Aon and (power domain)0 ~ (power domain)1. + // If no value is supplied, the default is specified by the power configuration. + // + // clk: related clock domain for synchronous release + // If type is "por", there is not related clock, since it is + // likely external or generated from a voltage comparator + // + nodes: [ + { name: "por_aon", gen: false, type: "top", clk: "aon" } + { name: "lc_src", gen: false, type: "int", clk: "io_div4" } + { name: "sys_src", gen: false, type: "int", clk: "io_div4" } + { name: "por", gen: true, type: "top", parent: "por_aon", clk: "main" } + { name: "por_io", gen: true, type: "top", parent: "por_aon", clk: "io" } + { name: "por_io_div2", gen: true , type: "top", parent: "por_aon", clk: "io_div2" } + { name: "por_io_div4", gen: true , type: "top", parent: "por_aon", clk: "io_div4" } + { name: "por_usb", gen: true , type: "top", parent: "por_aon", clk: "usb" } + { name: "lc", gen: true, type: "top", parent: "lc_src", clk: "main" } + { name: "lc_aon", gen: true, type: "top", parent: "lc_src", clk: "aon" } + { name: "lc_io", gen: true, type: "top", parent: "lc_src", clk: "io" } + { name: "lc_io_div2", gen: true, type: "top", parent: "lc_src", clk: "io_div2" } + { name: "lc_io_div4", gen: true, type: "top", parent: "lc_src", clk: "io_div4" } + { name: "lc_usb", gen: true, type: "top", parent: "lc_src", clk: "usb" } + { name: "sys", gen: true, type: "top", parent: "sys_src", clk: "main" } + { name: "sys_io_div4", gen: true, type: "top", parent: "sys_src", clk: "io_div4" } + { name: "spi_device", gen: true, type: "top", parent: "lc_src", clk: "io_div4", sw: true } + { name: "spi_host0", gen: true, type: "top", parent: "lc_src", clk: "io_div4", sw: true } + { name: "i2c0", gen: true, type: "top", parent: "lc_src", clk: "io_div4", sw: true }, + ] + } + + // Number of cores: used in rv_plic and timer + num_cores: "1", + + // `addr_spaces` names the distinct address spaces present in the device. + // All hosts in the same address space share the same base addresses for + // all peripherals, though not every peripheral will be accessible to every + // host in that address space--Access privileges are separate from addresses. + addr_spaces: [ + { name: "hart" + desc: "The main address space, shared between the CPU and DM" + subspaces: [ + { name: "mmio", + desc: ''' + MMIO region excludes any memory that is separate from the module configuration + space, i.e. ROM, main SRAM, and mbx SRAM are excluded but retention SRAM or + spi_device are included. + ''' + nodes: [ + "uart0", + "gpio", + "spi_device", + "i2c0", + "rv_timer", + "otp_ctrl", + "lc_ctrl.regs", + "alert_handler", + "spi_host0", + "pwrmgr_aon", + "rstmgr_aon", + "clkmgr_aon", + "pinmux_aon", + "aon_timer_aon", + "ast" + "sensor_ctrl", + "soc_proxy.core", + "sram_ctrl_ret_aon", + "rv_plic", + "aes", + "hmac", + "otbn", + "keymgr_dpe" + "csrng", + "edn0", + "edn1", + "sram_ctrl_main.regs", + "sram_ctrl_mbox.regs", + "rom_ctrl0.regs", + "rom_ctrl1.regs", + "dma", + "mbx0.core", + "mbx1.core", + "mbx2.core", + "mbx3.core", + "mbx4.core", + "mbx5.core", + "mbx6.core", + "mbx_jtag.core", + "mbx_pcie0.core", + "mbx_pcie1.core", + "rv_core_ibex" + ], + }, + ] + } + { name: "soc_mbx", desc: "SoC address space for mailbox access"}, + { name: "soc_dbg", desc: "SoC address space for debug module interfaces"}, + ] + + // `module` defines the peripherals. + // Details are coming from each modules' config file `ip.hjson` + // TODO: Define parameter here + // attr: There are a few types of modules supported + // normal(default): Normal, non-templated modules that will be instantiated + // templated: These modules are templated and must be run through topgen + // ipgen: These modules are the same as templated but use the new ipgen flow + // reggen_top: These modules are not templated, but need to have reggen run + // because they live exclusively in hw/top_* instead of hw/ip_*. + // These modules are also instantiated in the top level. + // reggen_only: Similar to reggen_top, but are not instantiated in the top level. + module: [ + { name: "uart0", // instance name + type: "uart", // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted) + // and `hw/ip/{type}` + + // clock connections defines the port to top level clock connection + // the ip.hjson will declare the clock port names + // If none are defined at ip.hjson, clk_i is used by default + clock_srcs: {clk_i: "io_div4"}, + clock_group: "peri", + // reset connections defines the port to top level reset connection + // the ip.hjson will declare the reset port names + // If none are defined at ip.hjson, rst_ni is used by default + reset_connections: {rst_ni: "lc_io_div4"}, + base_addr: { + hart: "0x30010000", + }, + }, + { name: "gpio", + type: "gpio", + clock_srcs: {clk_i: "io_div4"}, + clock_group: "peri", + reset_connections: {rst_ni: "lc_io_div4"}, + base_addr: { + hart: "0x30000000", + }, + param_decl: { + GpioAsHwStrapsEn: "1", + GpioAsyncOn: "1" + } + }, + { name: "spi_device", + type: "spi_device", + clock_srcs: {clk_i: "io_div4", scan_clk_i: "io_div2"}, + clock_group: "peri", + reset_connections: {rst_ni: "spi_device"}, + base_addr: { + hart: "0x30310000", + }, + param_decl: { + "SramType": "spi_device_pkg::SramType1r1w" + } + }, + { name: "i2c0", + type: "i2c", + clock_srcs: {clk_i: "io_div4"}, + clock_group: "peri", + reset_connections: {rst_ni: "i2c0"}, + base_addr: { + hart: "0x30080000", + }, + }, + { name: "rv_timer", + type: "rv_timer", + clock_srcs: {clk_i: "io_div4"}, + clock_group: "timers", + reset_connections: {rst_ni: "lc_io_div4"}, + base_addr: { + hart: "0x30100000", + }, + }, + { name: "otp_ctrl", + type: "otp_ctrl", + clock_srcs: {clk_i: "io_div4", clk_edn_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc_io_div4", rst_edn_ni: "lc"}, + base_addrs: { + core: {hart: "0x30130000"}, + prim: {hart: "0x30138000"}, + } + }, + { name: "lc_ctrl", + type: "lc_ctrl", + clock_srcs: {clk_i: "io_div4", clk_kmac_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc_io_div4", rst_kmac_ni: "lc"}, + base_addrs: { + regs: {hart: "0x30140000"}, + dmi: {soc_dbg: "0x00020000"}, + }, + param_decl: { + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED FOR + // PRODUCTION DEVICES. + SecVolatileRawUnlockEn: "top_pkg::SecVolatileRawUnlockEn", + // The following three values get exposed in the life cycle CSRs + // that are also readable via the TAP. + SiliconCreatorId: "16'h 4002", // Darjeeling integration with Rivos + ProductId: "16'h 4000", // Darjeeling + RevisionId: "8'h 01", // First tapeout + // Use TL-UL based DMI + UseDmiInterface: "1" + }, + }, + { name: "alert_handler", + type: "alert_handler", + clock_srcs: {clk_i: "io_div4", clk_edn_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc_io_div4", rst_edn_ni: "lc"}, + base_addr: { + hart: "0x30150000", + }, + attr: "ipgen", + }, + { name: "spi_host0", + type: "spi_host", + clock_srcs: {clk_i: "io_div4"}, + clock_group: "peri", + reset_connections: {rst_ni: "spi_host0"}, + base_addr: { + hart: "0x30300000", + }, + }, + { name: "pwrmgr_aon", + type: "pwrmgr", + // TODO: RS, fix after pwrmgr fix is merged + // param_decl: { + // PwrFsmWaitForExtRst: "1" + // } + clock_group: "powerup", + clock_srcs: { + clk_i: "io_div4", + clk_slow_i: "aon", + clk_lc_i: "io_div4", + clk_esc_i: { + clock: "io_div4", + group: "secure" + } + }, + reset_connections: { + rst_ni: { + name: "por_io_div4", + domain: "Aon" + }, + rst_main_ni: { + name: "por_aon", + domain: "0" + }, + rst_lc_ni: { + name: "lc_io_div4", + domain: "Aon" + }, + rst_esc_ni: { + name: "lc_io_div4", + domain: "Aon" + }, + rst_slow_ni: { + name: "por_aon", + domain: "Aon", + }, + } + domain: ["Aon", "0"], + base_addr: { + hart: "0x30400000", + }, + attr: "ipgen", + + }, + { name: "rstmgr_aon", + type: "rstmgr", + clock_srcs: { + clk_i: { + clock: "io_div4", + group: "powerup" + }, + clk_por_i: "io_div4", clk_aon_i: "aon", clk_main_i: "main", clk_io_i: "io", clk_usb_i: "usb", + clk_io_div2_i: "io_div2", clk_io_div4_i: "io_div4" + }, + clock_group: "powerup", + reset_connections: { + rst_ni: { + name: "lc_io_div4", + domain: "Aon" + }, + rst_por_ni: { + name: "por_io_div4", + domain: "Aon" + }, + } + domain: ["Aon", "0"], + base_addr: { + hart: "0x30410000", + }, + attr: "ipgen", + }, + { name: "clkmgr_aon", + type: "clkmgr", + clock_srcs: { + clk_i: "io_div4", + clk_main_i: { + group: "ast", + clock: "main" + }, + clk_io_i: { + group: "ast", + clock: "io" + }, + clk_usb_i: { + group: "ast", + clock: "usb" + }, + clk_aon_i: { + group: "ast", + clock: "aon" + } + }, + clock_group: "powerup", + reset_connections: {rst_ni: "lc_io_div4", + rst_aon_ni: "lc_aon" + rst_io_ni: "lc_io", + rst_io_div2_ni: "lc_io_div2", + rst_io_div4_ni: "lc_io_div4", + rst_main_ni: "lc", + rst_usb_ni: "lc_usb", + rst_root_ni: "por_io_div4", + rst_root_io_ni: "por_io", + rst_root_io_div2_ni: "por_io_div2", + rst_root_io_div4_ni: "por_io_div4", + rst_root_main_ni: "por", + rst_root_usb_ni: "por_usb", + }, + domain: ["Aon"], + base_addr: { + hart: "0x30420000", + }, + attr: "ipgen", + }, + { name: "pinmux_aon", + type: "pinmux", + clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"}, + clock_group: "powerup", + reset_connections: {rst_ni: "lc_io_div4", + rst_aon_ni: "lc_aon", + rst_sys_ni: "sys_io_div4" + }, + domain: ["Aon"], + base_addr: { + hart: "0x30460000", + }, + attr: "ipgen", + param_decl: { + // TODO: these parameters should be changed + // for the final configuration of Darjeeling. + // TODO: RS Fix that + // UsbWkupModuleEn: "0", + // HwStrapSamplingEn: "0", + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED FOR + // PRODUCTION DEVICES. + SecVolatileRawUnlockEn: "top_pkg::SecVolatileRawUnlockEn", + } + }, + { name: "aon_timer_aon", + type: "aon_timer", + clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"}, + clock_group: "timers", + reset_connections: {rst_ni: "lc_io_div4", rst_aon_ni: "lc_aon"}, + domain: ["Aon"], + base_addr: { + hart: "0x30470000", + }, + }, + { name: "ast", + type: "ast", + clock_srcs: { + clk_ast_tlul_i: { + clock: "io_div4", + group: "infra" + }, + clk_ast_adc_i: { + clock: "aon", + group: "peri" + }, + clk_ast_alert_i: { + clock: "io_div4", + group: "secure" + } + clk_ast_es_i: { + clock: "main", + group: "secure" + } + clk_ast_rng_i: { + clock: "main", + group: "secure" + } + clk_ast_usb_i: { + clock: "usb", + group: "peri" + } + }, + clock_group: "secure", + reset_connections: { + rst_ast_tlul_ni: { + name: "lc_io_div4", + domain: "0", + } + rst_ast_adc_ni: { + name: "lc_aon", + domain: "Aon" + }, + rst_ast_alert_ni: { + name: "lc_io_div4", + domain: "0", + }, + rst_ast_es_ni: { + name: "lc", + domain: "0", + }, + rst_ast_rng_ni: { + name: "lc", + domain: "0", + }, + rst_ast_usb_ni: { + name: "por_usb", + domain: "0" + } + }, + domain: ["Aon", "0"], + base_addr: { + hart: "0x30480000", + }, + attr: "reggen_only", + }, + { name: "sensor_ctrl", + type: "sensor_ctrl", + clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc_io_div4", rst_aon_ni: "lc_aon"}, + domain: ["Aon"], + base_addr: { + hart: "0x30020000", + }, + attr: "reggen_top", + }, + { name: "soc_proxy", + type: "soc_proxy", + clock_srcs: {clk_i: "main", clk_aon_i: "aon"}, + clock_group: "infra", + reset_connections: { + rst_ni: { + name: "lc", + domain: "0", + }, + rst_por_ni: { + name: "por_io_div4", + domain: "Aon", + }, + }, + domain: ["Aon", "0"], + base_addrs: { + core: {hart: "0x22030000"}, + ctn: {hart: "0x40000000"}, + }, + attr: "reggen_top", + memory: { + ctn: { + label: "ctn", + swaccess: "rw", + data_intg_passthru: "true", + exec: "True", + byte_write: "True", + size: "0x40000000", + } + } + }, + { name: "sram_ctrl_ret_aon", + type: "sram_ctrl", + clock_srcs: {clk_i: "io_div4", clk_otp_i: "io_div4"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc_io_div4", rst_otp_ni: "lc_io_div4"} + domain: ["Aon"], + param_decl: { + InstrExec: "0", + } + base_addrs: { + regs: {hart: "0x30500000"}, + ram: {hart: "0x30600000"}, + }, + // Memory regions must be associated with a dedicated + // TL-UL device interface. + memory: { + ram: { + label: "ram_ret_aon", + swaccess: "rw", + data_intg_passthru: "true", + exec: "True", + byte_write: "True", + size: "0x1000" + } + } + }, + { name: "rv_dm", + type: "rv_dm", + clock_srcs: {clk_i: "main", clk_lc_i: "main"}, + clock_group: "infra", + reset_connections: {rst_ni: "sys", rst_lc_ni: "lc"}, + // Note that this module also contains a bus host. + base_addrs: { + mem: {hart: "0x00040000"}, + regs: {hart: "0x21200000"}, + dbg: {soc_dbg: "0x00000000"}, + }, + param_decl: { + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED FOR + // PRODUCTION DEVICES. + SecVolatileRawUnlockEn: "top_pkg::SecVolatileRawUnlockEn", + // Use TL-UL based DMI + UseDmiInterface: "1" + }, + generate_dif: "False" + }, + { name: "rv_plic", + type: "rv_plic", + clock_srcs: {clk_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc"}, + base_addr: { + hart: "0x28000000", + }, + attr: "ipgen", + }, + { name: "aes", + type: "aes", + clock_srcs: {clk_i: "main", clk_edn_i: "main"}, + clock_group: "trans", + reset_connections: {rst_ni: "lc", rst_edn_ni: "lc"}, + param_decl: { + SecMasking: "1", + SecSBoxImpl: "aes_pkg::SBoxImplDom" + } + base_addr: { + hart: "0x21100000", + }, + }, + { name: "hmac", + type: "hmac", + clock_srcs: {clk_i: "main"}, + clock_group: "trans", + reset_connections: {rst_ni: "lc"}, + base_addr: { + hart: "0x21110000", + }, + }, + { name: "kmac", + type: "kmac", + param_decl: { + EnMasking: "1", + NumAppIntf: 4, + AppCfg: "'{kmac_pkg::AppCfgKeyMgr, kmac_pkg::AppCfgLcCtrl, kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgRomCtrl}" + } + clock_srcs: {clk_i: "main", clk_edn_i: "main"} + clock_group: "trans" + reset_connections: {rst_ni: "lc", rst_edn_ni: "lc"} + base_addr: { + hart: "0x21120000", + } + }, + { name: "otbn", + type: "otbn", + clock_srcs: { + clk_i: { + clock: "main", + group: "trans" + }, + clk_edn_i: { + clock: "main", + group: "secure" + }, + clk_otp_i: { + clock: "io_div4", + group: "secure" + }, + }, + clock_group: "trans", + reset_connections: {rst_ni: "lc", rst_edn_ni: "lc", rst_otp_ni: "lc_io_div4"}, + base_addr: { + hart: "0x21130000", + }, + }, + { name: "keymgr_dpe", + type: "keymgr_dpe", + clock_srcs: {clk_i: "main", clk_edn_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc", rst_edn_ni: "lc"}, + base_addr: { + hart: "0x21140000", + }, + }, + { name: "csrng", + type: "csrng", + clock_srcs: {clk_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc"}, + base_addr: { + hart: "0x21150000", + }, + }, + { name: "edn0", + type: "edn", + clock_srcs: {clk_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc"}, + base_addr: { + hart: "0x21170000", + }, + }, + { name: "edn1", + type: "edn", + clock_srcs: {clk_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc"}, + base_addr: { + hart: "0x21180000", + }, + }, + { name: "sram_ctrl_main", + type: "sram_ctrl", + clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"}, + // Note that while it might be useful to allow execution from SRAM for early testing, it can + // later be permanently disabled using the EN_SRAM_IFETCH switch in OTP. + param_decl: { + InstrExec: "1", + } + base_addrs: { + regs: {hart: "0x211c0000"}, + ram: {hart: "0x10000000"}, + }, + // Memory regions must be associated with a dedicated + // TL-UL device interface. + memory: { + ram: { + label: "ram_main", + swaccess: "rw", + data_intg_passthru: "true", + exec: "True", + byte_write: "True", + size: "0x10000" + } + } + }, + { name: "sram_ctrl_mbox", + type: "sram_ctrl", + clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"}, + param_decl: { + InstrExec: "0", + } + base_addrs: { + regs: {hart: "0x211d0000"}, + ram: {hart: "0x11000000"}, + }, + // Memory regions must be associated with a dedicated + // TL-UL device interface. + memory: { + ram: { + label: "ram_mbox", + swaccess: "rw", + data_intg_passthru: "true", + exec: "False", + byte_write: "True", + size: "0x1000" + } + } + }, + { name: "rom_ctrl0", + type: "rom_ctrl", + clock_srcs: {clk_i: "main"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + rom: {hart: "0x00008000"}, + regs: {hart: "0x211e0000"}, + } + memory: { + rom: { + label: "rom0", + swaccess: "ro", + data_intg_passthru: "true", + exec: "True", + byte_write: "False", + size: "0x8000" + data_intg_passthru: "True" + } + }, + param_decl: { + SecDisableScrambling: "1'b0" + } + }, + { name: "rom_ctrl1", + type: "rom_ctrl", + clock_srcs: {clk_i: "main"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + // TODO(opentitan-integrated/issues/251): + // This is not the final parameterization for Darjeeling. + base_addrs: { + rom: {hart: "0x00020000"}, + regs: {hart: "0x211e1000"}, + } + memory: { + rom: { + label: "rom1", + swaccess: "ro", + data_intg_passthru: "true", + exec: "True", + byte_write: "False", + size: "0x10000" + data_intg_passthru: "True" + } + }, + param_decl: { + SecDisableScrambling: "1'b0" + } + }, + { name: "dma", + type: "dma", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addr: {hart: "0x22010000"}, + }, + { name: "mbx0", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000000"}, + soc: {soc_mbx: "0x01465000"}, + }, + }, + { name: "mbx1", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000100"}, + soc: {soc_mbx: "0x01465100"}, + }, + }, + { name: "mbx2", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000200"}, + soc: {soc_mbx: "0x01465200"}, + }, + }, + { name: "mbx3", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000300"}, + soc: {soc_mbx: "0x01465300"}, + }, + }, + { name: "mbx4", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000400"}, + soc: {soc_mbx: "0x01465400"}, + }, + }, + { name: "mbx5", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000500"}, + soc: {soc_mbx: "0x01465500"}, + }, + }, + { name: "mbx6", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000600"}, + soc: {soc_mbx: "0x01465600"}, + }, + }, + { name: "mbx_jtag", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000800"}, + soc: {soc_dbg: "0x1000"}, + }, + }, + { name: "mbx_pcie0", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22040000"}, + soc: {soc_mbx: "0x01460100"}, + }, + }, + { name: "mbx_pcie1", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22040100"}, + soc: {soc_mbx: "0x01460200"}, + }, + }, + { name: "rv_core_ibex", + type: "rv_core_ibex", + param_decl: {PMPEnable: "1", + PMPGranularity: "0", + PMPNumRegions: "16", + MHPMCounterNum: "10", + MHPMCounterWidth: "32", + RV32E: "0", + RV32M: "ibex_pkg::RV32MSingleCycle", + RV32B: "ibex_pkg::RV32BOTEarlGrey", + RegFile: "ibex_pkg::RegFileFF", + BranchTargetALU: "1", + WritebackStage: "1", + ICache: "1", + ICacheECC: "1", + ICacheScramble: "1", + BranchPredictor: "0", + DbgTriggerEn: "1", + DbgHwBreakNum: "4", + SecureIbex: "1", + DmHaltAddr: "tl_main_pkg::ADDR_SPACE_RV_DM__MEM + dm::HaltAddress[31:0]", + DmExceptionAddr: "tl_main_pkg::ADDR_SPACE_RV_DM__MEM + dm::ExceptionAddress[31:0]", + PipeLine: "0" + }, + clock_srcs: { + clk_i: "main", + clk_edn_i: "main", + clk_esc_i: { + clock: "io_div4", + group: "secure", + } + clk_otp_i: { + clock: "io_div4", + group: "secure", + } + }, + clock_group: "infra", + reset_connections: {rst_ni: "lc", + rst_edn_ni: "lc", + rst_esc_ni: "lc_io_div4", + rst_otp_ni: "lc_io_div4"}, + base_addr: { + hart: "0x211f0000", + }, + }, + ] + + // All memories wrapped up in relevant controllers + memory: [], + + // The port data structure is not something that should be used liberally. + // It is used specifically to assign special attributes to specific ports. + // For example, this allows us to designate a port as part of inter-module + // connections. + port: [ + { name: "ast", + inter_signal_list: [ + { struct: "edn", + type: "req_rsp", + name: "edn", + // The activity direction for a port inter-signal is "opposite" of + // what the external module actually needs. + act: "rsp", + package: "edn_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_dft_en", + // The activity direction for a port inter-signal is "opposite" of + // what the external module actually needs. + act: "req", + package: "lc_ctrl_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_hw_debug_en", + // The activity direction for a port inter-signal is "opposite" of + // what the external module actually needs. + act: "req", + package: "lc_ctrl_pkg", + }, + + { struct: "ram_1p_cfg", + package: "prim_ram_1p_pkg", + type: "uni", + name: "ram_1p_cfg", + // The activity direction for a port inter-signal is "opposite" of + // what the external module actually needs. + act: "rcv" + }, + + { struct: "ram_2p_cfg", + package: "prim_ram_2p_pkg", + type: "uni", + name: "spi_ram_2p_cfg", + // The activity direction for a port inter-signal is "opposite" of + // what the external module actually needs. + act: "rcv" + }, + + { struct: "rom_cfg", + package: "prim_rom_pkg", + type: "uni", + name: "rom_cfg", + // The activity direction for a port inter-signal is "opposite" of + // what the external module actually needs. + act: "rcv" + } + + { struct: "ast_obs_ctrl", + type: "uni", + name: "obs_ctrl", + // The activity direction for a port inter-signal is "opposite" of + // what the external module actually needs. + act: "rcv", + package: "ast_pkg", + }, + ] + }, + ] + + // Inter-module Connection. + // format: + // requester: [ resp1, resp2, ... ], + // + // the field and value should be module_inst.port_name + // e.g flash_ctrl0.flash: [flash_phy0.flash_ctrl] + inter_module: { + 'connect': { + 'ast.obs_ctrl' : ['otp_ctrl.obs_ctrl'] + 'ast.ram_1p_cfg' : ['otbn.ram_cfg', + 'sram_ctrl_main.cfg', + 'sram_ctrl_ret_aon.cfg', + 'sram_ctrl_mbox.cfg', + 'rv_core_ibex.ram_cfg'], + 'ast.spi_ram_2p_cfg' : ['spi_device.ram_cfg'], + 'ast.rom_cfg' : ['rom_ctrl0.rom_cfg', + 'rom_ctrl1.rom_cfg'], + 'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'], + 'alert_handler.esc_rx' : ['rv_core_ibex.esc_rx', + 'lc_ctrl.esc_scrap_state0_rx', + 'lc_ctrl.esc_scrap_state1_rx' + 'pwrmgr_aon.esc_rst_rx'], + 'alert_handler.esc_tx' : ['rv_core_ibex.esc_tx', + 'lc_ctrl.esc_scrap_state0_tx', + 'lc_ctrl.esc_scrap_state1_tx', + 'pwrmgr_aon.esc_rst_tx'], + 'aon_timer_aon.nmi_wdog_timer_bark' : ['rv_core_ibex.nmi_wdog'] + 'csrng.csrng_cmd' : ['edn0.csrng_cmd', 'edn1.csrng_cmd'], + 'otp_ctrl.sram_otp_key' : ['sram_ctrl_main.sram_otp_key', + 'sram_ctrl_ret_aon.sram_otp_key', + 'sram_ctrl_mbox.sram_otp_key' + 'rv_core_ibex.icache_otp_key'] + 'pwrmgr_aon.pwr_rst' : ['rstmgr_aon.pwr'], + 'pwrmgr_aon.pwr_clk' : ['clkmgr_aon.pwr'], + 'pwrmgr_aon.pwr_otp' : ['otp_ctrl.pwr_otp'], + 'pwrmgr_aon.pwr_lc' : ['lc_ctrl.pwr_lc'], + 'pwrmgr_aon.strap' : ['pinmux_aon.strap_en', + 'gpio.strap_en', + 'rv_dm.strap_en'], + 'pwrmgr_aon.low_power' : ['pinmux_aon.sleep_en', + 'aon_timer_aon.sleep_mode'], + 'pwrmgr_aon.fetch_en' : ['rv_core_ibex.pwrmgr_cpu_en'], + 'pwrmgr_aon.rom_ctrl' : ['rom_ctrl0.pwrmgr_data', + 'rom_ctrl1.pwrmgr_data'], + 'keymgr_dpe.rom_digest' : ['rom_ctrl0.keymgr_data', + 'rom_ctrl1.keymgr_data'], + 'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'], + + // DMA LSIO triggers + 'dma.lsio_trigger' : ['soc_proxy.dma_lsio_trigger'], + 'i2c0.lsio_trigger' : ['soc_proxy.i2c_lsio_trigger'], + 'spi_host0.lsio_trigger' : ['soc_proxy.spi_host_lsio_trigger'], + 'uart0.lsio_trigger' : ['soc_proxy.uart_lsio_trigger'], + + // LC RMA req/ack interface: LC -> OTBN + // Note: this RoT configuration has no embedded flash, hence + // the RMA request is just routed to OTBN directly. + 'lc_ctrl.lc_flash_rma_req' : ['otbn.lc_rma_req'], + 'otbn.lc_rma_ack' : ['lc_ctrl.lc_flash_rma_ack'], + + // Edn connections + 'edn0.edn' : ['keymgr_dpe.edn', 'otp_ctrl.edn', 'ast.edn', 'kmac.entropy', + 'alert_handler.edn', 'aes.edn', 'otbn.edn_urnd', + 'rv_core_ibex.edn'], + 'edn1.edn' : ['otbn.edn_rnd'], + + // OTBN OTP scramble key + 'otp_ctrl.otbn_otp_key' : ['otbn.otbn_otp_key'], + + // KeyMgr Sideload & KDF function + 'otp_ctrl.otp_keymgr_key' : ['keymgr_dpe.otp_key'], + 'keymgr_dpe.aes_key' : ['aes.keymgr_key'], + 'keymgr_dpe.kmac_key' : ['kmac.keymgr_key'], + 'keymgr_dpe.otbn_key' : ['otbn.keymgr_key'], + + // KMAC Application Interface + // Note that arbitration is fixed priority top to bottom. + 'kmac.app' : ['keymgr_dpe.kmac_data', // Keymgr needs to be at index 0 + 'lc_ctrl.kmac_data', // LC needs to be at index 1 + 'rom_ctrl0.kmac_data', // ROM needs to be at index 2 or 3 + 'rom_ctrl1.kmac_data'], // ROM needs to be at index 2 or 3 + 'kmac.en_masking' : ['keymgr_dpe.kmac_en_masking'] + + // The idle connection is automatically connected through topgen. + // The user does not need to explicitly declare anything other than + // an empty list. + 'clkmgr_aon.idle' : [], + + // OTP LC interface + 'otp_ctrl.otp_lc_data' : ['lc_ctrl.otp_lc_data'], + 'lc_ctrl.lc_otp_program' : ['otp_ctrl.lc_otp_program'], + 'lc_ctrl.lc_otp_vendor_test' : ['otp_ctrl.lc_otp_vendor_test'], + + // Diversification constant coming from life cycle + 'lc_ctrl.lc_keymgr_div' : ['keymgr_dpe.lc_keymgr_div'], + + // Strap enable override signal, only used when SecVolatileRawUnlockEn = 1. + 'lc_ctrl.strap_en_override' : ['pinmux_aon.strap_en_override', + 'rv_dm.strap_en_override'], + + // LC function control signal broadcast + 'lc_ctrl.lc_dft_en' : ['otp_ctrl.lc_dft_en', + 'pinmux_aon.lc_dft_en', + 'ast.lc_dft_en', + 'pwrmgr_aon.lc_dft_en', + ], + 'lc_ctrl.lc_hw_debug_en' : ['sram_ctrl_main.lc_hw_debug_en', + 'pinmux_aon.lc_hw_debug_en', + 'ast.lc_hw_debug_en', + 'csrng.lc_hw_debug_en', + 'rv_dm.lc_hw_debug_en', + 'clkmgr_aon.lc_hw_debug_en', + 'pwrmgr_aon.lc_hw_debug_en',], + 'lc_ctrl.lc_cpu_en' : ['rv_core_ibex.lc_cpu_en'], + 'lc_ctrl.lc_keymgr_en' : ['keymgr_dpe.lc_keymgr_en'], + 'lc_ctrl.lc_escalate_en' : ['aes.lc_escalate_en', + 'kmac.lc_escalate_en', + 'otbn.lc_escalate_en', + 'otp_ctrl.lc_escalate_en', + 'sram_ctrl_main.lc_escalate_en', + 'sram_ctrl_ret_aon.lc_escalate_en', + 'sram_ctrl_mbox.lc_escalate_en', + 'aon_timer_aon.lc_escalate_en', + 'pinmux_aon.lc_escalate_en', + 'rv_dm.lc_escalate_en'], + + 'lc_ctrl.lc_check_byp_en' : ['otp_ctrl.lc_check_byp_en', + 'pinmux_aon.lc_check_byp_en', + 'rv_dm.lc_check_byp_en'], + 'lc_ctrl.lc_clk_byp_req' : ['clkmgr_aon.lc_clk_byp_req'], + 'lc_ctrl.lc_clk_byp_ack' : ['clkmgr_aon.lc_clk_byp_ack'], + + // LC access control signal broadcast + 'lc_ctrl.lc_creator_seed_sw_rw_en' : ['otp_ctrl.lc_creator_seed_sw_rw_en'], + 'lc_ctrl.lc_owner_seed_sw_rw_en' : ['otp_ctrl.lc_owner_seed_sw_rw_en'], + 'lc_ctrl.lc_seed_hw_rd_en' : ['otp_ctrl.lc_seed_hw_rd_en'], + + // rv_plic connections + 'rv_plic.msip' : ['rv_core_ibex.irq_software'], + 'rv_plic.irq' : ['rv_core_ibex.irq_external'], + + // rv_dm connections + 'rv_dm.debug_req': ['rv_core_ibex.debug_req'], + + // rv_timer connections + + + // rv core ibex connections + 'rv_core_ibex.crash_dump' : ['rstmgr_aon.cpu_dump'], + 'rv_core_ibex.pwrmgr' : ['pwrmgr_aon.pwr_cpu'], + + // spi passthrough connection + 'spi_device.passthrough' : ['spi_host0.passthrough'] + + // Debug module reset request to power manager + 'rv_dm.ndmreset_req' : ['pwrmgr_aon.ndmreset_req'], + + // Reset manager software reset request to pwrmgr + 'rstmgr_aon.sw_rst_req' : ['pwrmgr_aon.sw_rst_req'], + } + + // top is to connect to top net/struct. + // It defines the signal in the top and connect from the module, + // use of the signal is up to top template + 'top': [ + // top level net for clocks + 'clkmgr_aon.clocks', + + // top level clock gating indications for alert subsystem + 'clkmgr_aon.cg_en', + + // top level net for reset + 'rstmgr_aon.resets', + + // top level reset asserted indications for alert subsystem + 'rstmgr_aon.rst_en', + + // dedicated timer interrupt + 'rv_core_ibex.irq_timer', + + // hardwired connections + 'rv_core_ibex.hart_id', 'rv_core_ibex.boot_addr', + + // Xbars + + // OTP HW_CFG Broadcast signals. + // TODO(#6713): The actual struct breakout and mapping currently needs to + // be performed by hand in the toplevel template. + 'otp_ctrl.otp_broadcast', + 'lc_ctrl.otp_device_id', + 'lc_ctrl.otp_manuf_state', + 'keymgr_dpe.otp_device_id', + 'sram_ctrl_main.otp_en_sram_ifetch', + ], + + // ext is to create port in the top. + 'external': { + 'ast.edn' : '', + 'ast.lc_dft_en' : '', + 'ast.lc_hw_debug_en' : '', + 'ast.obs_ctrl' : 'obs_ctrl', + 'ast.ram_1p_cfg' : 'ram_1p_cfg', + 'ast.spi_ram_2p_cfg' : 'spi_ram_2p_cfg', + 'ast.rom_cfg' : 'rom_cfg', + // TODO: RS fix after pwrmgr merge + // 'pwrmgr_aon.boot_status' : 'pwrmgr_boot_status', + 'clkmgr_aon.jitter_en' : 'clk_main_jitter_en', + 'clkmgr_aon.io_clk_byp_req' : 'io_clk_byp_req', + 'clkmgr_aon.io_clk_byp_ack' : 'io_clk_byp_ack', + 'clkmgr_aon.all_clk_byp_req' : 'all_clk_byp_req', + 'clkmgr_aon.all_clk_byp_ack' : 'all_clk_byp_ack', + 'clkmgr_aon.hi_speed_sel' : 'hi_speed_sel', + 'clkmgr_aon.div_step_down_req' : 'div_step_down_req', + 'clkmgr_aon.calib_rdy' : 'calib_rdy', + 'csrng.entropy_src_hw_if' : 'entropy_src_hw_if', + 'dma.sys' : 'dma_sys', + 'dma.ctn_tl_h2d' : 'dma_ctn_tl_h2d', + 'dma.ctn_tl_d2h' : 'dma_ctn_tl_d2h', + 'mbx.tl_mbx' : 'mbx_tl', + 'mbx0.doe_intr' : 'mbx0_doe_intr', + 'mbx0.doe_intr_en' : 'mbx0_doe_intr_en', + 'mbx0.doe_intr_support' : 'mbx0_doe_intr_support', + 'mbx0.doe_async_msg_support' : 'mbx0_doe_async_msg_support', + 'mbx1.doe_intr' : 'mbx1_doe_intr', + 'mbx1.doe_intr_en' : 'mbx1_doe_intr_en', + 'mbx1.doe_intr_support' : 'mbx1_doe_intr_support', + 'mbx1.doe_async_msg_support' : 'mbx1_doe_async_msg_support', + 'mbx2.doe_intr' : 'mbx2_doe_intr', + 'mbx2.doe_intr_en' : 'mbx2_doe_intr_en', + 'mbx2.doe_intr_support' : 'mbx2_doe_intr_support', + 'mbx2.doe_async_msg_support' : 'mbx2_doe_async_msg_support', + 'mbx3.doe_intr' : 'mbx3_doe_intr', + 'mbx3.doe_intr_en' : 'mbx3_doe_intr_en', + 'mbx3.doe_intr_support' : 'mbx3_doe_intr_support', + 'mbx3.doe_async_msg_support' : 'mbx3_doe_async_msg_support', + 'mbx4.doe_intr' : 'mbx4_doe_intr', + 'mbx4.doe_intr_en' : 'mbx4_doe_intr_en', + 'mbx4.doe_intr_support' : 'mbx4_doe_intr_support', + 'mbx4.doe_async_msg_support' : 'mbx4_doe_async_msg_support', + 'mbx5.doe_intr' : 'mbx5_doe_intr', + 'mbx5.doe_intr_en' : 'mbx5_doe_intr_en', + 'mbx5.doe_intr_support' : 'mbx5_doe_intr_support', + 'mbx5.doe_async_msg_support' : 'mbx5_doe_async_msg_support', + 'mbx6.doe_intr' : 'mbx6_doe_intr', + 'mbx6.doe_intr_en' : 'mbx6_doe_intr_en', + 'mbx6.doe_intr_support' : 'mbx6_doe_intr_support', + 'mbx6.doe_async_msg_support' : 'mbx6_doe_async_msg_support', + 'mbx_jtag.doe_intr' : 'mbx_jtag_doe_intr', + 'mbx_jtag.doe_intr_en' : 'mbx_jtag_doe_intr_en', + 'mbx_jtag.doe_intr_support' : 'mbx_jtag_doe_intr_support', + 'mbx_jtag.doe_async_msg_support' : 'mbx_jtag_doe_async_msg_support', + 'mbx_pcie0.doe_intr' : 'mbx_pcie0_doe_intr', + 'mbx_pcie0.doe_intr_en' : 'mbx_pcie0_doe_intr_en', + 'mbx_pcie0.doe_intr_support' : 'mbx_pcie0_doe_intr_support', + 'mbx_pcie0.doe_async_msg_support' : 'mbx_pcie0_doe_async_msg_support', + 'mbx_pcie1.doe_intr' : 'mbx_pcie1_doe_intr', + 'mbx_pcie1.doe_intr_en' : 'mbx_pcie1_doe_intr_en', + 'mbx_pcie1.doe_intr_support' : 'mbx_pcie1_doe_intr_support', + 'mbx_pcie1.doe_async_msg_support' : 'mbx_pcie1_doe_async_msg_support', + 'dbg.tl_dbg' : 'dbg_tl', + 'rv_dm.next_dm_addr' : 'rv_dm_next_dm_addr', + 'peri.tl_ast' : 'ast_tl', + 'pinmux_aon.dft_strap_test' : 'dft_strap_test' + 'pinmux_aon.dft_hold_tap_sel' : 'dft_hold_tap_sel', + 'pwrmgr_aon.pwr_ast' : 'pwrmgr_ast', + 'otp_ctrl.otp_ast_pwr_seq' : '', + 'otp_ctrl.otp_ast_pwr_seq_h' : '', + 'otp_ctrl.otp_ext_voltage_h' : 'otp_ext_voltage_h', + 'otp_ctrl.otp_obs' : 'otp_obs', + 'rstmgr_aon.por_n' : 'por_n' + 'rv_core_ibex.fpga_info' : 'fpga_info' + 'sensor_ctrl.ast_alert' : 'sensor_ctrl_ast_alert', + 'sensor_ctrl.ast_status' : 'sensor_ctrl_ast_status', + 'sensor_ctrl.ast_init_done' : 'ast_init_done', + 'soc_proxy.ctn_tl_h2d' : 'ctn_tl_h2d', + 'soc_proxy.ctn_tl_d2h' : 'ctn_tl_d2h', + 'soc_proxy.soc_fatal_alert' : 'soc_fatal_alert', + 'soc_proxy.soc_recov_alert' : 'soc_recov_alert', + 'soc_proxy.soc_wkup_async' : 'soc_wkup_async', + 'soc_proxy.soc_rst_req_async' : 'soc_rst_req_async', + 'soc_proxy.soc_intr_async' : 'soc_intr_async', + 'soc_proxy.soc_lsio_trigger' : 'soc_lsio_trigger', + 'soc_proxy.soc_gpi_async' : 'soc_gpi_async', + 'soc_proxy.soc_gpo_async' : 'soc_gpo_async', + 'spi_device.sck_monitor' : 'sck_monitor', + }, + }, + + // Crossbars: having a top level crossbar + // This version assumes all crossbars are instantiated at the top. + // Assume xbar.hjson is located in the same directory of top.hjson + xbar: [ + { name: "main", + clock_srcs: {clk_main_i: "main", + clk_fixed_i: "io_div4", + clk_usb_i: "usb"}, + clock_group: "infra", + reset: "lc", + reset_connections: {rst_main_ni: "lc", + rst_fixed_ni: "lc_io_div4", + rst_usb_ni: "lc_usb"} + min_spacing: 0x100 + }, + { name: "peri", + clock_srcs: {clk_peri_i: "io_div4", }, + clock_group: "infra", + reset: "lc_io_div4", + reset_connections: {rst_peri_ni: "lc_io_div4"}, + }, + { name: "mbx", + clock_srcs: {clk_mbx_i: "main"}, + clock_group: "infra", + reset: "lc", + reset_connections: {rst_mbx_ni: "lc"}, + }, + { name: "dbg", + clock_srcs: {clk_dbg_i: "main", clk_peri_i: "io_div4"}, + clock_group: "infra", + reset: "lc", + reset_connections: {rst_dbg_ni: "lc", rst_peri_ni: "lc_io_div4"}, + }, + ], + + // ===== PINMUX & PINOUT ====================================================== + + pinout: { + // IO power bank declaration. + // This list defines the IO bank power domains on the ASIC. + // Each individual pad must be in one of the declared power domains. + banks: ['VIO'], + // Pad declaration. + // Each entry must have the following four keys: + // + // - name: Name of the pad (this will be exposed at the chiplevel). + // + // - type: Pad type (this maps to the pad types defined in prim_pad_wrapper_pkg.sv) + // + // - bank: Specifies in which of the IO power banks this pad lives. + // + // - connection: Can have either of the following values: + // + // 1) 'direct': This is a dedicated IO Pad that is directly connected to a peripheral. + // + // 2) 'manual': This is a dedicated IO signal that is not directly connected to a + // peripheral. It needs to be manually wired up in the template. + // + // 3) 'muxed': This is a muxed IO pad that will be connected to the pinmux. + // + // Optionally, each pad can also have a 'desc' field for further description, and a 'port_type' field + // to override the default 'inout wire' type (this is currently only used for simulating ADC connections + // where the ports have to be switched to a real type when the ANALOGSIM macro is defined). + pads: [ + // Special manually connected pads + { name: 'POR_N' , type: 'InputStd', bank: 'VIO' , connection: 'manual', desc: 'System reset'}, + { name: 'JTAG_TCK' , type: 'InputStd', bank: 'VIO' , connection: 'manual', desc: 'JTAG TCK signal'}, + { name: 'JTAG_TMS' , type: 'InputStd', bank: 'VIO' , connection: 'manual', desc: 'JTAG TMS signal'}, + { name: 'JTAG_TDI' , type: 'InputStd', bank: 'VIO' , connection: 'manual', desc: 'JTAG TDI signal'}, + { name: 'JTAG_TDO' , type: 'BidirStd', bank: 'VIO' , connection: 'manual', desc: 'JTAG TDO signal'}, + { name: 'JTAG_TRST_N' , type: 'InputStd', bank: 'VIO' , connection: 'manual', desc: 'JTAG TRST_N signal'}, + { name: 'OTP_EXT_VOLT' , type: 'AnalogIn1', bank: 'VIO' , connection: 'manual', desc: 'OTP external voltage input'}, + // Dedicated IOs + { name: 'SPI_HOST_D0' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI host data'}, + { name: 'SPI_HOST_D1' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI host data'}, + { name: 'SPI_HOST_D2' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI host data'}, + { name: 'SPI_HOST_D3' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI host data'}, + { name: 'SPI_HOST_CLK' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI host clock'}, + { name: 'SPI_HOST_CS_L' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI host chip select'}, + { name: 'SPI_DEV_D0' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI device data'}, + { name: 'SPI_DEV_D1' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI device data'}, + { name: 'SPI_DEV_D2' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI device data'}, + { name: 'SPI_DEV_D3' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI device data'}, + { name: 'SPI_DEV_CLK' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SPI device clock'}, + { name: 'SPI_DEV_CS_L' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SPI device chip select'}, + { name: 'SPI_DEV_TPM_CS_L', type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SPI device TPM chip select'}, + { name: 'UART_RX' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'UART receive'}, + { name: 'UART_TX' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'UART transmit'}, + { name: 'I2C_SCL' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'I2C clock'}, + { name: 'I2C_SDA' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'I2C data'}, + // RoT GPIO + { name: 'GPIO0' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO1' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO2' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO3' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO4' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO5' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO6' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO7' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO8' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO9' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO10' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO11' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO12' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO13' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO14' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO15' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO16' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO17' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO18' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO19' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO20' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO21' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO22' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO23' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO24' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO25' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO26' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO27' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO28' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO29' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO30' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO31' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + // SOC GPIO + { name: 'SOC_GPI0' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI1' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI2' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI3' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI4' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI5' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI6' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI7' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI8' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI9' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI10' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI11' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPO0' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO1' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO2' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO3' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO4' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO5' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO6' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO7' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO8' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO9' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO10' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO11' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + // Muxed pads + { name: 'MIO0' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO1' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO2' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO3' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO4' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO5' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO6' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO7' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO8' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO9' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO10' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO11' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + ] + } + + pinmux: { + // Signal to pinmux/pad mapping. + // Each entry in the list below must have the following two mandatory keys: + // + // - instance: This is the comportable IO instance name where the IO signal comes from. + // + // - connection: This key is similar to the connection key in the pinout/pad configuration and + // can have either of the following values: + // + // 1) 'direct': This is a dedicated IO signal that is directly connected to a pad. + // Such an IO signal must also specify the 'port' and 'pad' keys + // (see further below). + // + // 2) 'manual': This is a dedicated IO signal that is not directly connected to a pad. + // It needs to be manually wired up in the template. + // Such an IO signal may have a 'port' key, but no 'pad' key. + // + // 3) 'muxed': This is a muxed IO signal that will be connected to the pinmux. + // Such an IO signal may have a 'port' key, but no 'pad' key. + // + // Depending on the connection type specified, each entry may have the following optional keys: + // + // - port: Name of the available IO signal of the instance. + // This is required for 'direct' connections, but optional for the others. + // Individual signals of a bus IO signal must be indexed with square brackets, e.g. mybus[1]. + // Not specifying this key or setting it to an empty string acts as a wild card + // and includes all available IOs of this instance. + // + // - pad: Name of the pad the 'direct' connection should connect to. + // This is not required for 'muxed' and 'manual' connections. + // + // - desc: Optional description field. + // + // - attr: Manual direct IOs may specify an additional pad attr field. + // This is used to create the correct pad attribute CSR for that DIO channel (since the + // DIO is manual, there is no way to automatically infer the corresponding pad type). + // + signals: [ + // SPI Host0 + { instance: 'spi_host0', port: 'sck', connection: 'direct', pad: 'SPI_HOST_CLK' , desc: ''}, + { instance: 'spi_host0', port: 'csb', connection: 'direct', pad: 'SPI_HOST_CS_L' , desc: ''}, + { instance: 'spi_host0', port: 'sd[0]', connection: 'direct', pad: 'SPI_HOST_D0' , desc: ''}, + { instance: 'spi_host0', port: 'sd[1]', connection: 'direct', pad: 'SPI_HOST_D1' , desc: ''}, + { instance: 'spi_host0', port: 'sd[2]', connection: 'direct', pad: 'SPI_HOST_D2' , desc: ''}, + { instance: 'spi_host0', port: 'sd[3]', connection: 'direct', pad: 'SPI_HOST_D3' , desc: ''}, + // SPI Device + { instance: 'spi_device', port: 'sck', connection: 'direct', pad: 'SPI_DEV_CLK' , desc: ''}, + { instance: 'spi_device', port: 'csb', connection: 'direct', pad: 'SPI_DEV_CS_L' , desc: ''}, + { instance: 'spi_device', port: 'sd[0]', connection: 'direct', pad: 'SPI_DEV_D0' , desc: ''}, + { instance: 'spi_device', port: 'sd[1]', connection: 'direct', pad: 'SPI_DEV_D1' , desc: ''}, + { instance: 'spi_device', port: 'sd[2]', connection: 'direct', pad: 'SPI_DEV_D2' , desc: ''}, + { instance: 'spi_device', port: 'sd[3]', connection: 'direct', pad: 'SPI_DEV_D3' , desc: ''}, + { instance: "spi_device", port: 'tpm_csb', connection: 'direct', pad: 'SPI_DEV_TPM_CS_L' , desc: ''}, + // UART + { instance: "uart0", port: 'rx', connection: 'direct', pad: 'UART_RX' , desc: ''}, + { instance: "uart0", port: 'tx', connection: 'direct', pad: 'UART_TX' , desc: ''}, + // I2C + { instance: "i2c0", port: 'scl', connection: 'direct', pad: 'I2C_SCL' , desc: ''}, + { instance: "i2c0", port: 'sda', connection: 'direct', pad: 'I2C_SDA' , desc: ''}, + // RoT GPIO + { instance: "gpio", port: 'gpio[0]', connection: 'direct', pad: 'GPIO0' , desc: ''}, + { instance: "gpio", port: 'gpio[1]', connection: 'direct', pad: 'GPIO1' , desc: ''}, + { instance: "gpio", port: 'gpio[2]', connection: 'direct', pad: 'GPIO2' , desc: ''}, + { instance: "gpio", port: 'gpio[3]', connection: 'direct', pad: 'GPIO3' , desc: ''}, + { instance: "gpio", port: 'gpio[4]', connection: 'direct', pad: 'GPIO4' , desc: ''}, + { instance: "gpio", port: 'gpio[5]', connection: 'direct', pad: 'GPIO5' , desc: ''}, + { instance: "gpio", port: 'gpio[6]', connection: 'direct', pad: 'GPIO6' , desc: ''}, + { instance: "gpio", port: 'gpio[7]', connection: 'direct', pad: 'GPIO7' , desc: ''}, + { instance: "gpio", port: 'gpio[8]', connection: 'direct', pad: 'GPIO8' , desc: ''}, + { instance: "gpio", port: 'gpio[9]', connection: 'direct', pad: 'GPIO9' , desc: ''}, + { instance: "gpio", port: 'gpio[10]', connection: 'direct', pad: 'GPIO10' , desc: ''}, + { instance: "gpio", port: 'gpio[11]', connection: 'direct', pad: 'GPIO11' , desc: ''}, + { instance: "gpio", port: 'gpio[12]', connection: 'direct', pad: 'GPIO12' , desc: ''}, + { instance: "gpio", port: 'gpio[13]', connection: 'direct', pad: 'GPIO13' , desc: ''}, + { instance: "gpio", port: 'gpio[14]', connection: 'direct', pad: 'GPIO14' , desc: ''}, + { instance: "gpio", port: 'gpio[15]', connection: 'direct', pad: 'GPIO15' , desc: ''}, + { instance: "gpio", port: 'gpio[16]', connection: 'direct', pad: 'GPIO16' , desc: ''}, + { instance: "gpio", port: 'gpio[17]', connection: 'direct', pad: 'GPIO17' , desc: ''}, + { instance: "gpio", port: 'gpio[18]', connection: 'direct', pad: 'GPIO18' , desc: ''}, + { instance: "gpio", port: 'gpio[19]', connection: 'direct', pad: 'GPIO19' , desc: ''}, + { instance: "gpio", port: 'gpio[20]', connection: 'direct', pad: 'GPIO20' , desc: ''}, + { instance: "gpio", port: 'gpio[21]', connection: 'direct', pad: 'GPIO21' , desc: ''}, + { instance: "gpio", port: 'gpio[22]', connection: 'direct', pad: 'GPIO22' , desc: ''}, + { instance: "gpio", port: 'gpio[23]', connection: 'direct', pad: 'GPIO23' , desc: ''}, + { instance: "gpio", port: 'gpio[24]', connection: 'direct', pad: 'GPIO24' , desc: ''}, + { instance: "gpio", port: 'gpio[25]', connection: 'direct', pad: 'GPIO25' , desc: ''}, + { instance: "gpio", port: 'gpio[26]', connection: 'direct', pad: 'GPIO26' , desc: ''}, + { instance: "gpio", port: 'gpio[27]', connection: 'direct', pad: 'GPIO27' , desc: ''}, + { instance: "gpio", port: 'gpio[28]', connection: 'direct', pad: 'GPIO28' , desc: ''}, + { instance: "gpio", port: 'gpio[29]', connection: 'direct', pad: 'GPIO29' , desc: ''}, + { instance: "gpio", port: 'gpio[30]', connection: 'direct', pad: 'GPIO30' , desc: ''}, + { instance: "gpio", port: 'gpio[31]', connection: 'direct', pad: 'GPIO31' , desc: ''}, + // SoC GPIO + { instance: "soc_proxy", port: 'soc_gpi[0]', connection: 'direct', pad: 'SOC_GPI0' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[1]', connection: 'direct', pad: 'SOC_GPI1' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[2]', connection: 'direct', pad: 'SOC_GPI2' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[3]', connection: 'direct', pad: 'SOC_GPI3' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[4]', connection: 'direct', pad: 'SOC_GPI4' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[5]', connection: 'direct', pad: 'SOC_GPI5' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[6]', connection: 'direct', pad: 'SOC_GPI6' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[7]', connection: 'direct', pad: 'SOC_GPI7' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[8]', connection: 'direct', pad: 'SOC_GPI8' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[9]', connection: 'direct', pad: 'SOC_GPI9' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[10]', connection: 'direct', pad: 'SOC_GPI10' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[11]', connection: 'direct', pad: 'SOC_GPI11' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[12]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[13]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[14]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[15]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[0]', connection: 'direct', pad: 'SOC_GPO0' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[1]', connection: 'direct', pad: 'SOC_GPO1' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[2]', connection: 'direct', pad: 'SOC_GPO2' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[3]', connection: 'direct', pad: 'SOC_GPO3' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[4]', connection: 'direct', pad: 'SOC_GPO4' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[5]', connection: 'direct', pad: 'SOC_GPO5' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[6]', connection: 'direct', pad: 'SOC_GPO6' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[7]', connection: 'direct', pad: 'SOC_GPO7' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[8]', connection: 'direct', pad: 'SOC_GPO8' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[9]', connection: 'direct', pad: 'SOC_GPO9' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[10]', connection: 'direct', pad: 'SOC_GPO10' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[11]', connection: 'direct', pad: 'SOC_GPO11' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[12]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[13]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[14]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[15]', connection: 'muxed' , pad: '' , desc: ''}, + // Other MIOs + { instance: "otp_ctrl", port: 'test[0]', connection: 'muxed' , pad: '' , desc: ''}, + ], + + num_wkup_detect: 8 + wkup_cnt_width: 8 + // Disable USB wakeup and hardware strap sampling for integrated OpenTitan + enable_usb_wakeup: false + enable_strap_sampling: false + } + + // Implementation targets. + // This defines the configuration of the target-specific chip-levels to + // generate from the shared template. Each target uses the same base + // configuration for the pinmux and pinout as defined above, and the + // generated software constants for the pinmux DIF do not change among the + // implementation targets. However, in order to accommodate slight + // differences among the ASIC, FPGA emulation and simulation environments, + // it is possible to make very limited pinout changes below. In particular, + // it is possible to remove and tie-off specific pads, or add more 'manual' + // pads that need to be manually connected in the template. It is also possible + // to override the JTAG and strap locations indices, since the testing and DFT + // setups may differ among the targets. + targets: [ + { name: 'asic', + + // Pinout Changes. + pinout: { + // This is a list of port names to remove from the chip port list. + // The corresponding pad of a removed port will remain instantiated, + // and a wire net will be declared inside the chip-level hierarchy so + // that it can be manually connected as needed. + remove_ports: [], + + // This is a list of pad names to remove from the base pinout defined + // above. Removed pads will be stubbed off such that their inputs + // signals are driven with zero. Output signals and output enables + // will be left unconnected. If no changes are needed, this list can + // be left empty. + remove_pads: [], + + // This is a list of additional "manual" pads to add to the pinout. + // The pad entries have the same format as the pad entries in the pinout + // configuration above. However, the 'connection' key must always be set + // to 'manual' as it is not possible to connect these additional pads + // to the pinmux or peripherals. + add_pads: [], + }, + + pinmux: { + // Special signal positions. Each entry in the list below creates a + // target-specific pad position parameter in the chiplevel hierarchy + // that can be used to parameterize certain IPs like the pinmux or + // padring. This is mainly used to define the pad positions of special + // test and DFT signals such as the JTAG signals and the TAP and DFT + // straps. Straps in this context are special pads that get sampled at + // boot time during certain life cycle states in order to determine + // DFT modes and the TAP mux selection index (the JTAG signals can be + // muxed to either the lifecycle TAP, DFT TAP or RISC-V processor + // TAP). TODO: add more documentation to https://docs.opentitan.org/hw/ip/pinmux/doc/index.html + // Each entry must have the following two keys: + // + // - name: Basename for the SV parameter. + // + // - pad: The pad name that this special signal maps to. The generated + // parameter will be assigned the corresponding pad index. + // + // Each entry may have an optional 'desc' key for further description. + special_signals: [ + // Straps + { name: 'tap0', pad: 'MIO0', desc: 'TAP strap signal.' }, + { name: 'tap1', pad: 'MIO1', desc: 'TAP strap signal.' }, + { name: 'dft0', pad: 'MIO2', desc: 'DFT strap signal.' }, + { name: 'dft1', pad: 'MIO3', desc: 'DFT strap signal.' }, + // JTAG + { name: 'tck', pad: 'MIO4', desc: 'JTAG tck signal.' }, + { name: 'tms', pad: 'MIO5', desc: 'JTAG tms signal.' }, + { name: 'trst_n', pad: 'MIO6', desc: 'JTAG trst_n signal.' }, + { name: 'tdi', pad: 'MIO7', desc: 'JTAG tdi signal.' }, + { name: 'tdo', pad: 'MIO8', desc: 'JTAG tdo signal.' }, + ], + } + }, + { name: 'cw310', + + pinout: { + remove_ports: [], + remove_pads: [ + 'OTP_EXT_VOLT' + ], + + add_pads: [ + // Additional infrastructure pads + { name: 'IO_CLK', type: 'InputStd', bank: 'VIO', connection: 'manual', desc: 'Extra clock input for FPGA target'} + { name: 'POR_BUTTON_N', type: 'InputStd', bank: 'VIO', connection: 'manual', desc: 'Power-on reset button input'} + // ChipWhisperer IO + { name: 'IO_CLKOUT', type: 'BidirStd', bank: 'VIO', connection: 'manual', desc: 'Manual clock output for SCA setup'} + { name: 'IO_TRIGGER', type: 'BidirStd', bank: 'VIO', connection: 'manual', desc: 'Manual trigger output for SCA setup'} + ], + }, + + pinmux: { + special_signals: [ + // Straps + { name: 'tap0', pad: 'MIO0', desc: 'TAP strap signal.' }, + { name: 'tap1', pad: 'MIO1', desc: 'TAP strap signal.' }, + { name: 'dft0', pad: 'MIO2', desc: 'DFT strap signal.' }, + { name: 'dft1', pad: 'MIO3', desc: 'DFT strap signal.' }, + // JTAG + { name: 'tck', pad: 'MIO4', desc: 'JTAG tck signal.' }, + { name: 'tms', pad: 'MIO5', desc: 'JTAG tms signal.' }, + { name: 'trst_n', pad: 'MIO6', desc: 'JTAG trst_n signal.' }, + { name: 'tdi', pad: 'MIO7', desc: 'JTAG tdi signal.' }, + { name: 'tdo', pad: 'MIO8', desc: 'JTAG tdo signal.' }, + ], + } + } + ] +} diff --git a/hw/top_darjeeling/data/xbar_dbg.hjson b/hw/top_darjeeling/data/xbar_dbg.hjson new file mode 100644 index 0000000000000..d20f224003452 --- /dev/null +++ b/hw/top_darjeeling/data/xbar_dbg.hjson @@ -0,0 +1,47 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ name: "dbg", + type: "xbar", + clock_primary: "clk_dbg_i", // Main clock, used in sockets + other_clock_list: [ "clk_peri_i" ], // Secondary clocks used by specific nodes + reset_primary: "rst_dbg_ni", // Main reset, used in sockets + other_reset_list: [ "rst_peri_ni" ], // Secondary resets used by specific nodes + + nodes: [ + { name: "dbg", + type: "host", + addr_space: "soc_dbg", + clock: "clk_dbg_i", + reset: "rst_dbg_ni", + xbar: "true", + pipeline: false, + }, + { name: "rv_dm.dbg", + type: "device", + clock: "clk_dbg_i", + reset: "rst_dbg_ni", + pipeline: false, + }, + { name: "mbx_jtag.soc", + type: "device", + clock: "clk_dbg_i", + reset: "rst_dbg_ni", + pipeline: false, + }, + { name: "lc_ctrl.dmi", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + } + ], + + connections: { + dbg: [ + "rv_dm.dbg", + "mbx_jtag.soc", + "lc_ctrl.dmi" + ], + }, +} diff --git a/hw/top_darjeeling/data/xbar_main.hjson b/hw/top_darjeeling/data/xbar_main.hjson new file mode 100644 index 0000000000000..360b2f52ac62f --- /dev/null +++ b/hw/top_darjeeling/data/xbar_main.hjson @@ -0,0 +1,425 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ name: "main", + type: "xbar", + clock_primary: "clk_main_i", // Main clock, used in sockets + other_clock_list: [ "clk_fixed_i", "clk_usb_i"] // Secondary clocks used by specific nodes + reset_primary: "rst_main_ni", // Main reset, used in sockets + other_reset_list: [ "rst_fixed_ni", "rst_usb_ni"] // Secondary resets used by specific nodes + + // Rationale for pipeline and req/rsp_fifo_pass: + // For host interfaces that are used during production state (corei/cored), + // minimize the amount of host introduced latency. This is accomplished + // by setting pipeline to false. + // For host interfaces that are only used for debug, relax the timing by + // inserting a register slice and not allowing passthrough (more access + // latency. This is accomplished by setting `req/rsp_fifo_pass` to false, + // and implicitly using the default of pipeline true. + // + // For device interfaces, especially configuration registers, latency is + // not generally a concern, thus use `req/rsp_fifo_pass` false and pipeline + // true. + // For device accesses to memories (ram / rom / flash), performance is a concern, + // so use pipeline false where permissible by timing. If not, find a combination + // that works. + nodes: [ + { name: "rv_core_ibex.corei", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false + }, + { name: "rv_core_ibex.cored", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false + }, + { name: "rv_dm.sba", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "rv_dm.regs", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "rv_dm.mem", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "rom_ctrl0.rom", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: true, + rsp_fifo_pass: false, + }, + { name: "rom_ctrl0.regs", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "rom_ctrl1.rom", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: true, + rsp_fifo_pass: false, + }, + { name: "rom_ctrl1.regs", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "peri", + type: "device", + clock: "clk_fixed_i", + reset: "rst_fixed_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "soc_proxy.core", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "soc_proxy.ctn", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + pipefile: false, + }, + { name: "hmac", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "kmac" + type: "device" + clock: "clk_main_i" + reset: "rst_main_ni" + req_fifo_pass: false, + rsp_fifo_pass: false, + } + { name: "aes", + type: "device", + clock: "clk_main_i" + reset: "rst_main_ni" + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "csrng", + type: "device", + clock: "clk_main_i" + reset: "rst_main_ni" + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "edn0", + type: "device", + clock: "clk_main_i" + reset: "rst_main_ni" + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "edn1", + type: "device", + clock: "clk_main_i" + reset: "rst_main_ni" + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "rv_plic", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + inst_type: "rv_plic", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "otbn", + type: "device", + clock: "clk_main_i" + reset: "rst_main_ni" + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "keymgr_dpe", + type: "device", + clock: "clk_main_i" + reset: "rst_main_ni" + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "rv_core_ibex.cfg", + type: "device", + clock: "clk_main_i" + reset: "rst_main_ni" + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "sram_ctrl_main.regs", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "sram_ctrl_main.ram", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false + }, + { name: "sram_ctrl_mbox.regs", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false + }, + { name: "sram_ctrl_mbox.ram", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false + }, + { name: "dma", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "dma.host", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx0.core", + type: "device", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx0.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx1.core", + type: "device", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx1.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx2.core", + type: "device", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx2.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx3.core", + type: "device", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx3.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx4.core", + type: "device", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx4.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx5.core", + type: "device", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx5.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx6.core", + type: "device", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx6.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx_jtag.core", + type: "device", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx_jtag.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx_pcie0.core", + type: "device", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx_pcie0.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx_pcie1.core", + type: "device", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx_pcie1.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + + ], + connections: { + // TODO: remove rv_core_ibex.corei - sram_ctrl_main.ram connection + rv_core_ibex.corei: ["rom_ctrl0.rom", "rom_ctrl1.rom", + "rv_dm.mem", "sram_ctrl_main.ram", "soc_proxy.ctn"], + rv_core_ibex.cored: [ + "rom_ctrl0.rom", "rom_ctrl0.regs", "rom_ctrl1.rom", "rom_ctrl1.regs", + "rv_dm.mem", "rv_dm.regs", "sram_ctrl_main.ram", "peri", + "aes", "csrng", "edn0", "edn1", "hmac", + "rv_plic", "otbn", "keymgr_dpe", "kmac", "sram_ctrl_main.regs", + "rv_core_ibex.cfg", "sram_ctrl_mbox.ram", "sram_ctrl_mbox.regs", + "soc_proxy.ctn", "soc_proxy.core", "dma", "mbx0.core", "mbx1.core", + "mbx2.core", "mbx3.core", "mbx4.core", "mbx5.core", "mbx6.core", + "mbx_jtag.core", "mbx_pcie0.core", "mbx_pcie1.core", + ], + rv_dm.sba: [ + "rom_ctrl0.rom", "rom_ctrl0.regs", "rom_ctrl1.rom", "rom_ctrl1.regs", + "rv_dm.mem", "rv_dm.regs", "sram_ctrl_main.ram", "peri", + "aes", "csrng", "edn0", "edn1", "hmac", + "rv_plic", "otbn", "keymgr_dpe", "kmac", "sram_ctrl_main.regs", + "rv_core_ibex.cfg", "sram_ctrl_mbox.ram", "sram_ctrl_mbox.regs", + "soc_proxy.ctn", "soc_proxy.core", "dma", "mbx0.core", "mbx1.core", + "mbx2.core", "mbx3.core", "mbx4.core", "mbx5.core", "mbx6.core", + "mbx_jtag.core", "mbx_pcie0.core", "mbx_pcie1.core", + ], + // This is the same set of devices that rv_core_ibex.cored is connected to, + // but without ROM0/1 and RV_DM. + dma.host: [ + "sram_ctrl_main.ram", "sram_ctrl_mbox.ram", + "aes", "hmac", "otbn", "keymgr_dpe", "kmac", + "soc_proxy.ctn", "peri" + ], + mbx0.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx1.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx2.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx3.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx4.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx5.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx6.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx_jtag.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx_pcie0.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx_pcie1.sram: [ + "sram_ctrl_mbox.ram", + ], + }, +} diff --git a/hw/top_darjeeling/data/xbar_mbx.hjson b/hw/top_darjeeling/data/xbar_mbx.hjson new file mode 100644 index 0000000000000..e12ae568062e0 --- /dev/null +++ b/hw/top_darjeeling/data/xbar_mbx.hjson @@ -0,0 +1,91 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ name: "mbx", + type: "xbar", + clock_primary: "clk_mbx_i", // Main clock, used in sockets + other_clock_list: [], // Secondary clocks used by specific nodes + reset_primary: "rst_mbx_ni", // Main reset, used in sockets + other_reset_list: [], // Secondary resets used by specific nodes + + nodes: [ + { name: "mbx", + type: "host", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + xbar: "true", + pipeline: false, + }, + { name: "mbx0.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx1.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx2.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx3.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx4.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx5.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx6.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx_pcie0.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx_pcie1.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + ], + + connections: { + mbx: [ + "mbx0.soc", "mbx1.soc", "mbx2.soc", "mbx3.soc", "mbx4.soc", "mbx5.soc", + "mbx6.soc", "mbx_pcie0.soc", "mbx_pcie1.soc", + ], + }, +} diff --git a/hw/top_darjeeling/data/xbar_peri.hjson b/hw/top_darjeeling/data/xbar_peri.hjson new file mode 100644 index 0000000000000..5e906cfc2d257 --- /dev/null +++ b/hw/top_darjeeling/data/xbar_peri.hjson @@ -0,0 +1,150 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ name: "peri", + type: "xbar", + clock_primary: "clk_peri_i", // Main clock, used in sockets + other_clock_list: [] // Secondary clocks used by specific nodes + reset_primary: "rst_peri_ni", // Main reset, used in sockets + other_reset_list: [] // Secondary resets used by specific nodes + + nodes: [ + { name: "main", + type: "host", + addr_space: "hart", + clock: "clk_peri_i", + reset: "rst_peri_ni", + xbar: "true", + pipeline: false + + }, + { name: "uart0", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "i2c0", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "gpio", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "spi_host0", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "spi_device", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "rv_timer", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "pwrmgr_aon", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "rstmgr_aon", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "clkmgr_aon", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "pinmux_aon", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "otp_ctrl.core", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "otp_ctrl.prim", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "lc_ctrl.regs", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "sensor_ctrl", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false, + }, + { name: "alert_handler", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false, + }, + { name: "sram_ctrl_ret_aon.regs", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "sram_ctrl_ret_aon.ram", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "aon_timer_aon", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false, + }, + { name: "ast", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false, + }, + ], + connections: { + // Note that only the following masters have access to the peri + // crossbar: rv_dm.sba, rv_core_ibex.cored, TODO:dma_ctrl + // The ibex instruction fetch port does NOT have access to these + // peripherals. + main: [ + "uart0", "i2c0" + "gpio", "spi_host0", "spi_device", "rv_timer", + "pwrmgr_aon", "rstmgr_aon", "clkmgr_aon", "pinmux_aon", + "otp_ctrl.core", "otp_ctrl.prim", "lc_ctrl.regs", "sensor_ctrl", + "alert_handler", "ast", "sram_ctrl_ret_aon.ram", "sram_ctrl_ret_aon.regs", + "aon_timer_aon" + ], + }, +} From 963d6e3170b143439309b3b0e2f0851c42c233c5 Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Fri, 15 Nov 2024 12:14:27 +0100 Subject: [PATCH 3/8] [darjeeling] Generate Darjeeling from HJSON files Command run: make -C hw top_and_cmdgen Signed-off-by: Robert Schilling --- hw/Makefile | 2 +- .../data/autogen/top_darjeeling.gen.hjson | 27947 ++++++++++ .../dv/autogen/rstmgr_tgl_excl.cfg | 29 + .../dv/autogen/tb__alert_handler_connect.sv | 105 + .../dv/autogen/tb__xbar_connect.sv | 246 + .../dv/autogen/xbar_env_pkg__params.sv | 378 + .../dv/autogen/xbar_tgl_excl.cfg | 285 + .../dv/env/autogen/chip_env_pkg__params.sv | 109 + .../xbar_dbg/data/autogen/xbar_dbg.gen.hjson | 134 + .../ip/xbar_dbg/data/autogen/xbar_dbg.hjson | 41 + .../xbar_dbg/dv/autogen/tb__xbar_connect.sv | 25 + .../ip/xbar_dbg/dv/autogen/xbar_cov_excl.el | 14 + .../ip/xbar_dbg/dv/autogen/xbar_cover.cfg | 34 + .../ip/xbar_dbg/dv/autogen/xbar_dbg_bind.core | 19 + .../ip/xbar_dbg/dv/autogen/xbar_dbg_bind.sv | 36 + .../ip/xbar_dbg/dv/autogen/xbar_dbg_sim.core | 30 + .../dv/autogen/xbar_dbg_sim_cfg.hjson | 31 + .../dv/autogen/xbar_env_pkg__params.sv | 26 + .../ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv | 30 + .../ip/xbar_dbg/rtl/autogen/xbar_dbg.sv | 125 + hw/top_darjeeling/ip/xbar_dbg/xbar_dbg.core | 25 + .../data/autogen/xbar_main.gen.hjson | 1121 + .../ip/xbar_main/data/autogen/xbar_main.hjson | 305 + .../xbar_main/dv/autogen/tb__xbar_connect.sv | 72 + .../ip/xbar_main/dv/autogen/xbar_cov_excl.el | 71 + .../ip/xbar_main/dv/autogen/xbar_cover.cfg | 159 + .../dv/autogen/xbar_env_pkg__params.sv | 234 + .../xbar_main/dv/autogen/xbar_main_bind.core | 19 + .../ip/xbar_main/dv/autogen/xbar_main_bind.sv | 300 + .../xbar_main/dv/autogen/xbar_main_sim.core | 30 + .../dv/autogen/xbar_main_sim_cfg.hjson | 31 + .../ip/xbar_main/rtl/autogen/tl_main_pkg.sv | 140 + .../ip/xbar_main/rtl/autogen/xbar_main.sv | 1909 + hw/top_darjeeling/ip/xbar_main/xbar_main.core | 25 + .../xbar_mbx/data/autogen/xbar_mbx.gen.hjson | 268 + .../ip/xbar_mbx/data/autogen/xbar_mbx.hjson | 77 + .../xbar_mbx/dv/autogen/tb__xbar_connect.sv | 28 + .../ip/xbar_mbx/dv/autogen/xbar_cov_excl.el | 14 + .../ip/xbar_mbx/dv/autogen/xbar_cover.cfg | 88 + .../dv/autogen/xbar_env_pkg__params.sv | 50 + .../ip/xbar_mbx/dv/autogen/xbar_mbx_bind.core | 19 + .../ip/xbar_mbx/dv/autogen/xbar_mbx_bind.sv | 72 + .../ip/xbar_mbx/dv/autogen/xbar_mbx_sim.core | 30 + .../dv/autogen/xbar_mbx_sim_cfg.hjson | 31 + .../ip/xbar_mbx/rtl/autogen/tl_mbx_pkg.sv | 48 + .../ip/xbar_mbx/rtl/autogen/xbar_mbx.sv | 161 + hw/top_darjeeling/ip/xbar_mbx/xbar_mbx.core | 25 + .../data/autogen/xbar_peri.gen.hjson | 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hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv create mode 100644 hw/top_darjeeling/rtl/autogen/top_darjeeling_rnd_cnst_pkg.sv create mode 100644 hw/top_darjeeling/sw/autogen/.clang-format create mode 100644 hw/top_darjeeling/sw/autogen/chip/mod.rs create mode 100644 hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs create mode 100644 hw/top_darjeeling/sw/autogen/top_darjeeling.c create mode 100644 hw/top_darjeeling/sw/autogen/top_darjeeling.h create mode 100644 hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h create mode 100644 hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld create mode 100644 sw/host/opentitanlib/src/chip/autogen/darjeeling.rs diff --git a/hw/Makefile b/hw/Makefile index 5903ff7c86c0a..1b2af9c7f012b 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -46,7 +46,7 @@ IPS ?= aes \ uart \ usbdev -TOPS ?= top_earlgrey +TOPS ?= top_darjeeling top_earlgrey USE_BUFFER ?= 0 diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson new file mode 100644 index 0000000000000..f48271cead6b5 --- /dev/null +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -0,0 +1,27947 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \ +// -o hw/top_darjeeling/ \ +// --rnd_cnst_seed 1017106219537032642877583828875051302543807092889754935647094601236425074047 +{ + name: darjeeling + type: top + rnd_cnst_seed: 1017106219537032642877583828875051302543807092889754935647094601236425074047 + datawidth: "32" + power: + { + domains: + [ + Aon + "0" + ] + default: "0" + wait_for_external_reset: true + } + clocks: + { + hier_paths: + { + top: clkmgr_aon_clocks. + ext: "" + lpg: clkmgr_aon_cg_en. + } + srcs: + [ + { + name: main + aon: no + freq: "100000000" + ref: false + } + { + name: io + aon: no + freq: "96000000" + ref: false + } + { + name: usb + aon: no + freq: "48000000" + ref: false + } + { + name: aon + aon: yes + freq: "200000" + ref: true + } + ] + derived_srcs: + [ + { + name: io_div2 + aon: no + freq: "48000000" + ref: false + div: "2" + src: io + } + { + name: io_div4 + aon: no + freq: "24000000" + ref: false + div: "4" + src: io + } + ] + groups: + [ + { + name: ast + src: ext + sw_cg: no + unique: no + clocks: + { + clk_main_i: main + clk_io_i: io + clk_usb_i: usb + clk_aon_i: aon + } + } + { + name: powerup + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_powerup: io_div4 + clk_aon_powerup: aon + clk_main_powerup: main + clk_io_powerup: io + clk_usb_powerup: usb + clk_io_div2_powerup: io_div2 + } + } + { + name: trans + src: top + sw_cg: hint + unique: yes + clocks: + { + clk_main_aes: main + clk_main_hmac: main + clk_main_kmac: main + clk_main_otbn: main + } + } + { + name: infra + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_infra: io_div4 + clk_main_infra: main + clk_aon_infra: aon + clk_usb_infra: usb + } + } + { + name: secure + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_secure: io_div4 + clk_main_secure: main + clk_aon_secure: aon + } + } + { + name: peri + src: top + sw_cg: yes + unique: no + clocks: + { + clk_io_div4_peri: io_div4 + clk_io_div2_peri: io_div2 + clk_aon_peri: aon + clk_usb_peri: usb + } + } + { + name: timers + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_timers: io_div4 + clk_aon_timers: aon + } + } + ] + } + resets: + { + hier_paths: + { + top: rstmgr_aon_resets. + ext: "" + lpg: rstmgr_aon_rst_en. + } + nodes: + [ + { + name: por_aon + gen: false + type: top + domains: + [ + "0" + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_aon_n + clock: aon + } + { + name: lc_src + gen: false + type: int + domains: [] + shadowed: false + sw: false + path: "" + clock: io_div4 + } + { + name: sys_src + gen: false + type: int + domains: [] + shadowed: false + sw: false + path: "" + clock: io_div4 + } + { + name: por + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_n + parent: por_aon + clock: main + } + { + name: por_io + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_n + parent: por_aon + clock: io + } + { + name: por_io_div2 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_div2_n + parent: por_aon + clock: io_div2 + } + { + name: por_io_div4 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_div4_n + parent: por_aon + clock: io_div4 + } + { + name: por_usb + gen: true + type: top + domains: + [ + Aon + "0" + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_usb_n + parent: por_aon + clock: usb + } + { + name: lc + gen: true + type: top + domains: + [ + "0" + Aon + ] + shadowed: true + sw: false + path: rstmgr_aon_resets.rst_lc_n + parent: lc_src + clock: main + } + { + name: lc_aon + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_aon_n + parent: lc_src + clock: aon + } + { + name: lc_io + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_io_n + parent: lc_src + clock: io + } + { + name: lc_io_div2 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_io_div2_n + parent: lc_src + clock: io_div2 + } + { + name: lc_io_div4 + gen: true + type: top + domains: + [ + "0" + Aon + ] + shadowed: true + sw: false + path: rstmgr_aon_resets.rst_lc_io_div4_n + parent: lc_src + clock: io_div4 + } + { + name: lc_usb + gen: true + type: top + domains: + [ + Aon + "0" + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_usb_n + parent: lc_src + clock: usb + } + { + name: sys + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_sys_n + parent: sys_src + clock: main + } + { + name: sys_io_div4 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_sys_io_div4_n + parent: sys_src + clock: io_div4 + } + { + name: spi_device + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_spi_device_n + parent: lc_src + clock: io_div4 + } + { + name: spi_host0 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_spi_host0_n + parent: lc_src + clock: io_div4 + } + { + name: i2c0 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_i2c0_n + parent: lc_src + clock: io_div4 + } + ] + } + num_cores: "1" + addr_spaces: + [ + { + name: hart + desc: The main address space, shared between the CPU and DM + subspaces: + [ + { + name: mmio + desc: + ''' + MMIO region excludes any memory that is separate from the module configuration + space, i.e. ROM, main SRAM, and mbx SRAM are excluded but retention SRAM or + spi_device are included. + ''' + nodes: + [ + uart0 + gpio + spi_device + i2c0 + rv_timer + otp_ctrl + lc_ctrl.regs + alert_handler + spi_host0 + pwrmgr_aon + rstmgr_aon + clkmgr_aon + pinmux_aon + aon_timer_aon + ast + sensor_ctrl + soc_proxy.core + sram_ctrl_ret_aon + rv_plic + aes + hmac + otbn + keymgr_dpe + csrng + edn0 + edn1 + sram_ctrl_main.regs + sram_ctrl_mbox.regs + rom_ctrl0.regs + rom_ctrl1.regs + dma + mbx0.core + mbx1.core + mbx2.core + mbx3.core + mbx4.core + mbx5.core + mbx6.core + mbx_jtag.core + mbx_pcie0.core + mbx_pcie1.core + rv_core_ibex + ] + } + ] + } + { + name: soc_mbx + desc: SoC address space for mailbox access + } + { + name: soc_dbg + desc: SoC address space for debug module interfaces + } + ] + module: + [ + { + name: uart0 + type: uart + clock_srcs: + { + clk_i: io_div4 + } + clock_group: peri + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_peri + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: lsio_trigger + desc: + ''' + Self-clearing status trigger for the DMA. + Set when RX or TX FIFOs are past their configured watermarks matching watermark interrupt behaviour. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: uart0 + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: uart0_lsio_trigger + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: uart0 + default: "" + end_idx: -1 + top_signame: uart0_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30010000 + } + } + generate_dif: true + } + { + name: gpio + type: gpio + clock_srcs: + { + clk_i: io_div4 + } + clock_group: peri + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: "0" + } + } + param_decl: + { + GpioAsHwStrapsEn: "1" + GpioAsyncOn: "1" + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_peri + } + domain: + [ + "0" + ] + memory: {} + param_list: + [ + { + name: GpioAsyncOn + desc: Instantiates 2-flop synchronizers on all GPIO inputs if set to 1. + type: bit + default: "1" + local: "false" + expose: "true" + name_top: GpioGpioAsyncOn + } + { + name: GpioAsHwStrapsEn + desc: Enable HW straps sampling logic for GPIO inputs at initial cold boot + type: bit + default: "1" + local: "false" + expose: "true" + name_top: GpioGpioAsHwStrapsEn + } + ] + inter_signal_list: + [ + { + name: strap_en + desc: This signal is pulsed high by the power manager after reset in order to sample the HW straps. + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: gpio + package: "" + top_signame: pwrmgr_aon_strap + index: -1 + } + { + name: sampled_straps + desc: This vector contains the sampled strap values. + struct: gpio_straps + package: gpio_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: gpio + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: gpio + default: "" + end_idx: -1 + top_signame: gpio_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30000000 + } + } + generate_dif: true + } + { + name: spi_device + type: spi_device + clock_srcs: + { + clk_i: io_div4 + scan_clk_i: io_div2 + } + clock_group: peri + reset_connections: + { + rst_ni: + { + name: spi_device + domain: "0" + } + } + param_decl: + { + SramType: spi_device_pkg::SramType1r1w + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_peri + scan_clk_i: clkmgr_aon_clocks.clk_io_div2_peri + } + domain: + [ + "0" + ] + memory: {} + param_list: + [ + { + name: SramType + desc: Sram Entries. Word size is 32bit width. + type: spi_device_pkg::sram_type_e + default: spi_device_pkg::SramType1r1w + local: "false" + expose: "true" + name_top: SpiDeviceSramType + } + ] + inter_signal_list: + [ + { + name: ram_cfg + struct: ram_2p_cfg + package: prim_ram_2p_pkg + type: uni + act: rcv + width: 1 + inst_name: spi_device + default: "" + top_signame: ast_spi_ram_2p_cfg + index: -1 + } + { + name: passthrough + struct: passthrough + package: spi_device_pkg + type: req_rsp + act: req + width: 1 + inst_name: spi_device + default: "" + end_idx: -1 + top_signame: spi_device_passthrough + index: -1 + } + { + name: mbist_en + struct: logic + type: uni + act: rcv + width: 1 + inst_name: spi_device + index: -1 + } + { + name: sck_monitor + struct: logic + type: uni + act: req + width: 1 + inst_name: spi_device + default: "" + package: "" + external: true + top_signame: sck_monitor + conn_type: false + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: spi_device + default: "" + end_idx: -1 + top_signame: spi_device_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30310000 + } + } + generate_dif: true + } + { + name: i2c0 + type: i2c + clock_srcs: + { + clk_i: io_div4 + } + clock_group: peri + reset_connections: + { + rst_ni: + { + name: i2c0 + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_peri + } + domain: + [ + "0" + ] + param_decl: {} + memory: {} + param_list: + [ + { + name: InputDelayCycles + desc: + ''' + Maximum number of cycles of propagation delay between a change on the cio_scl_en_o or cio_sda_en_o pins and sensing the new values on the corresponding input pins, not including the rise/fall times. + For the purposes of this calculation, an input delay of 0 cycles means an output pin changing at the beginning of clock edge N will be sampled and observed on the input pins at clock edge N+1. + ''' + type: int + default: "0" + local: "false" + expose: "true" + name_top: I2c0InputDelayCycles + } + ] + inter_signal_list: + [ + { + name: ram_cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: lsio_trigger + desc: + ''' + Self-clearing status trigger for the DMA. + Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: i2c0 + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: i2c0_lsio_trigger + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: i2c0 + default: "" + end_idx: -1 + top_signame: i2c0_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30080000 + } + } + generate_dif: true + } + { + name: rv_timer + type: rv_timer + clock_srcs: + { + clk_i: io_div4 + } + clock_group: timers + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_timers + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_timer + default: "" + end_idx: -1 + top_signame: rv_timer_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30100000 + } + } + generate_dif: true + } + { + name: otp_ctrl + type: otp_ctrl + clock_srcs: + { + clk_i: io_div4 + clk_edn_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x30130000 + } + prim: + { + hart: 0x30138000 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_secure + clk_edn_i: clkmgr_aon_clocks.clk_main_secure + } + domain: + [ + "0" + ] + param_decl: {} + memory: {} + param_list: + [ + { + name: MemInitFile + desc: VMEM file to initialize the OTP macro. + type: "" + default: '''""''' + local: "false" + expose: "true" + name_top: OtpCtrlMemInitFile + } + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: otp_ctrl_pkg::lfsr_seed_t + randcount: 40 + randtype: data + name_top: RndCnstOtpCtrlLfsrSeed + default: 0x508e576e43 + randwidth: 40 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: otp_ctrl_pkg::lfsr_perm_t + randcount: 40 + randtype: perm + name_top: RndCnstOtpCtrlLfsrPerm + default: 0x7da5dd44319081848f24210e8de8a498830a0015672c74cd6e116559c654 + randwidth: 240 + } + { + name: RndCnstScrmblKeyInit + desc: Compile-time random permutation for scrambling key/nonce register reset value + type: otp_ctrl_pkg::scrmbl_key_init_t + randcount: 256 + randtype: data + name_top: RndCnstOtpCtrlScrmblKeyInit + default: 0x986313d612fdcd62afd0c3a5fc772ceb91c16f5d6e17dff0661bfba6f4e0571e + randwidth: 256 + } + ] + inter_signal_list: + [ + { + name: otp_ext_voltage_h + struct: "" + type: io + act: none + width: 1 + default: "'0" + inst_name: otp_ctrl + package: "" + external: true + top_signame: otp_ext_voltage_h + conn_type: false + index: -1 + } + { + name: otp_ast_pwr_seq + desc: Power sequencing signals to AST (VDD domain). + struct: otp_ast_req + package: otp_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + external: true + top_signame: otp_ctrl_otp_ast_pwr_seq + conn_type: false + index: -1 + } + { + name: otp_ast_pwr_seq_h + desc: Power sequencing signals coming from AST (VCC domain). + struct: otp_ast_rsp + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: otp_ctrl + external: true + top_signame: otp_ctrl_otp_ast_pwr_seq_h + conn_type: false + index: -1 + } + { + name: edn + desc: Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation. + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: otp_ctrl + default: "" + top_signame: edn0_edn + index: 1 + } + { + name: pwr_otp + desc: Initialization request/acknowledge from/to power manager. + struct: pwr_otp + package: pwrmgr_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: pwrmgr_aon_pwr_otp + index: -1 + } + { + name: lc_otp_vendor_test + desc: Vendor test control signals from/to the life cycle TAP. + struct: lc_otp_vendor_test + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_otp_vendor_test + index: -1 + } + { + name: lc_otp_program + desc: Life cycle state transition interface. + struct: lc_otp_program + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_otp_program + index: -1 + } + { + name: otp_lc_data + desc: + ''' + Life cycle state output holding the current life cycle state, + the value of the transition counter and the tokens needed for life cycle transitions. + ''' + struct: otp_lc_data + package: otp_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_type: broadcast + top_signame: otp_ctrl_otp_lc_data + index: -1 + } + { + name: lc_escalate_en + desc: + ''' + Life cycle escalation enable coming from life cycle controller. + This signal moves all FSMs within OTP into the error state. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_creator_seed_sw_rw_en + desc: + ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_creator_seed_sw_rw_en + index: -1 + } + { + name: lc_owner_seed_sw_rw_en + desc: + ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the OWNER_SEED. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_owner_seed_sw_rw_en + index: -1 + } + { + name: lc_seed_hw_rd_en + desc: + ''' + Seed read enable coming from life cycle controller. + This signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_seed_hw_rd_en + index: -1 + } + { + name: lc_dft_en + desc: + ''' + Test enable qualifier coming from life cycle controller. + This signals enables the TL-UL access port to the proprietary OTP IP. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_check_byp_en + desc: + ''' + Life cycle partition check bypass signal. + This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_check_byp_en + index: -1 + } + { + name: otp_keymgr_key + desc: Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + struct: otp_keymgr_key + package: otp_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_type: broadcast + top_signame: otp_ctrl_otp_keymgr_key + index: -1 + } + { + name: flash_otp_key + desc: Key derivation interface for FLASH scrambling. + struct: flash_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + index: -1 + } + { + name: sram_otp_key + desc: Array with key derivation interfaces for SRAM scrambling devices. + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 4 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_type: one-to-N + top_signame: otp_ctrl_sram_otp_key + index: -1 + } + { + name: otbn_otp_key + desc: Key derivation interface for OTBN scrambling devices. + struct: otbn_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_signame: otp_ctrl_otbn_otp_key + index: -1 + } + { + name: otp_broadcast + desc: Output of the HW partitions with breakout data types. + struct: otp_broadcast + package: otp_ctrl_part_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: otp_ctrl_otp_broadcast + index: -1 + } + { + name: obs_ctrl + desc: AST observability control signals. + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: otp_ctrl + default: "" + top_signame: ast_obs_ctrl + index: -1 + } + { + name: otp_obs + desc: AST observability bus. + struct: logic + type: uni + act: req + width: 8 + inst_name: otp_ctrl + default: "" + package: "" + external: true + top_signame: otp_obs + conn_type: false + index: -1 + } + { + name: core_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: otp_ctrl + default: "" + end_idx: -1 + top_signame: otp_ctrl_core_tl + index: -1 + } + { + name: prim_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: otp_ctrl + default: "" + end_idx: -1 + top_signame: otp_ctrl_prim_tl + index: -1 + } + ] + generate_dif: true + } + { + name: lc_ctrl + type: lc_ctrl + clock_srcs: + { + clk_i: io_div4 + clk_kmac_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: "0" + } + rst_kmac_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + regs: + { + hart: 0x30140000 + } + dmi: + { + soc_dbg: 0x00020000 + } + } + param_decl: + { + SecVolatileRawUnlockEn: top_pkg::SecVolatileRawUnlockEn + SiliconCreatorId: 16'h 4002 + ProductId: 16'h 4000 + RevisionId: 8'h 01 + UseDmiInterface: "1" + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_secure + clk_kmac_i: clkmgr_aon_clocks.clk_main_secure + } + domain: + [ + "0" + ] + memory: {} + param_list: + [ + { + name: SecVolatileRawUnlockEn + desc: + ''' + Disable (0) or enable (1) volatile RAW UNLOCK capability. + If enabled, it is possible to perform a volatile RAW -> TEST_UNLOCKED0 transition + without programming the OTP. This is a useful fallback mode in case the OTP is + not working correctly. + + IMPORTANT NOTE: This should only be used in test chips. The parameter must be set + to 0 in production tapeouts since this weakens the security posture of the RAW + UNLOCK mechanism. + ''' + type: bit + default: top_pkg::SecVolatileRawUnlockEn + local: "false" + expose: "true" + name_top: SecLcCtrlVolatileRawUnlockEn + } + { + name: UseDmiInterface + desc: When 1, a TLUL-based DMI interface is used. When 0, a JTAG TAP is used. + type: bit + default: "1" + local: "false" + expose: "true" + name_top: LcCtrlUseDmiInterface + } + { + name: RndCnstLcKeymgrDivInvalid + desc: Diversification value used for all invalid life cycle states. + type: lc_ctrl_pkg::lc_keymgr_div_t + randcount: 128 + randtype: data + name_top: RndCnstLcCtrlLcKeymgrDivInvalid + default: 0xae0fc6e6a1a665f042709b54cb121f70 + randwidth: 128 + } + { + name: RndCnstLcKeymgrDivTestUnlocked + desc: Diversification value used for the TEST_UNLOCKED* life cycle states. + type: lc_ctrl_pkg::lc_keymgr_div_t + randcount: 128 + randtype: data + name_top: RndCnstLcCtrlLcKeymgrDivTestUnlocked + default: 0x2a405ecdcf1feb0fa7a14877ec88637 + randwidth: 128 + } + { + name: RndCnstLcKeymgrDivDev + desc: Diversification value used for the DEV life cycle state. + type: lc_ctrl_pkg::lc_keymgr_div_t + randcount: 128 + randtype: data + name_top: RndCnstLcCtrlLcKeymgrDivDev + default: 0x87af272efaa51f0de710c891d47ff720 + randwidth: 128 + } + { + name: RndCnstLcKeymgrDivProduction + desc: Diversification value used for the PROD/PROD_END life cycle states. + type: lc_ctrl_pkg::lc_keymgr_div_t + randcount: 128 + randtype: data + name_top: RndCnstLcCtrlLcKeymgrDivProduction + default: 0x9f95d614848e38361cd9b7eb23d532c0 + randwidth: 128 + } + { + name: RndCnstLcKeymgrDivRma + desc: Diversification value used for the RMA life cycle state. + type: lc_ctrl_pkg::lc_keymgr_div_t + randcount: 128 + randtype: data + name_top: RndCnstLcCtrlLcKeymgrDivRma + default: 0xab44e1e92ccfebadad9193a3ee4ecd8c + randwidth: 128 + } + { + name: RndCnstInvalidTokens + desc: Compile-time random bits used for invalid tokens in the token mux + type: lc_ctrl_pkg::lc_token_mux_t + randcount: 1024 + randtype: data + name_top: RndCnstLcCtrlInvalidTokens + default: 0x32462b3e18549cb1e70d5a83de6673d2c1c0a7b55176264e55c329c8ae4725aeaf6728150127ac755d70063277642b5309a163990b966cd494444c3bcdf8087b7facd65e9654cd85bc66d10208c4fb51b97bbf4d12c378ccfd6a5a5bf3032db51fa1eb92f6ce10e90f9c5c06f733dc911a321dd4c0ac2406d467215dab3f2b5 + randwidth: 1024 + } + { + name: SiliconCreatorId + desc: Chip generation number. + type: logic [15:0] + default: 16'h 4002 + local: "false" + expose: "true" + name_top: LcCtrlSiliconCreatorId + } + { + name: ProductId + desc: Chip revision number. + type: logic [15:0] + default: 16'h 4000 + local: "false" + expose: "true" + name_top: LcCtrlProductId + } + { + name: RevisionId + desc: Chip revision number. + type: logic [7:0] + default: 8'h 01 + local: "false" + expose: "true" + name_top: LcCtrlRevisionId + } + { + name: IdcodeValue + desc: JTAG ID code. + type: logic [31:0] + default: 32'h00000001 + local: "false" + expose: "true" + name_top: LcCtrlIdcodeValue + } + ] + inter_signal_list: + [ + { + name: jtag + struct: jtag + package: jtag_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + index: -1 + } + { + name: esc_scrap_state0_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_tx + index: 1 + } + { + name: esc_scrap_state0_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_rx + index: 1 + } + { + name: esc_scrap_state1_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_tx + index: 2 + } + { + name: esc_scrap_state1_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_rx + index: 2 + } + { + name: pwr_lc + struct: pwr_lc + package: pwrmgr_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: pwrmgr_aon_pwr_lc + index: -1 + } + { + name: lc_otp_vendor_test + struct: lc_otp_vendor_test + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + end_idx: -1 + top_signame: lc_ctrl_lc_otp_vendor_test + index: -1 + } + { + name: otp_lc_data + struct: otp_lc_data + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT + inst_name: lc_ctrl + top_signame: otp_ctrl_otp_lc_data + index: -1 + } + { + name: lc_otp_program + struct: lc_otp_program + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + end_idx: -1 + top_signame: lc_ctrl_lc_otp_program + index: -1 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + top_signame: kmac_app + index: 1 + } + { + name: lc_dft_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_nvm_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: lc_cpu_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_cpu_en + index: -1 + } + { + name: lc_keymgr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_keymgr_en + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_clk_byp_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_clk_byp_req + index: -1 + } + { + name: lc_clk_byp_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_clk_byp_ack + index: -1 + } + { + name: lc_flash_rma_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_flash_rma_req + index: -1 + } + { + name: lc_flash_rma_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 2 + default: lc_ctrl_pkg::On + inst_name: lc_ctrl + top_signame: otbn_lc_rma_ack + index: -1 + } + { + name: lc_flash_rma_seed + struct: lc_flash_rma_seed + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + index: -1 + } + { + name: lc_check_byp_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_check_byp_en + index: -1 + } + { + name: lc_creator_seed_sw_rw_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_creator_seed_sw_rw_en + index: -1 + } + { + name: lc_owner_seed_sw_rw_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_owner_seed_sw_rw_en + index: -1 + } + { + name: lc_iso_part_sw_rd_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_iso_part_sw_wr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_seed_hw_rd_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_seed_hw_rd_en + index: -1 + } + { + name: lc_keymgr_div + struct: lc_keymgr_div + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_keymgr_div + index: -1 + } + { + name: otp_device_id + struct: otp_device_id + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: lc_ctrl + top_signame: lc_ctrl_otp_device_id + index: -1 + } + { + name: otp_manuf_state + struct: otp_manuf_state + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: lc_ctrl + top_signame: lc_ctrl_otp_manuf_state + index: -1 + } + { + name: hw_rev + struct: lc_hw_rev + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + index: -1 + } + { + name: strap_en_override + desc: + ''' + This signal transitions from 0 -> 1 by the lc_ctrl manager after volatile RAW_UNLOCK in order to re-sample the HW straps. + The signal stays at 1 until reset. + Note that this is only used in test chips when SecVolatileRawUnlockEn = 1. + Otherwise this signal is tied off to 0. + ''' + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: lc_ctrl + package: "" + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_strap_en_override + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + default: "" + end_idx: -1 + top_signame: lc_ctrl_regs_tl + index: -1 + } + { + name: dmi_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + default: "" + end_idx: -1 + top_signame: lc_ctrl_dmi_tl + index: -1 + } + ] + generate_dif: true + } + { + name: alert_handler + type: alert_handler + clock_srcs: + { + clk_i: io_div4 + clk_edn_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + } + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_secure + clk_edn_i: clkmgr_aon_clocks.clk_main_secure + } + domain: + [ + "0" + ] + param_decl: {} + memory: {} + param_list: + [ + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: alert_pkg::lfsr_seed_t + randcount: 32 + randtype: data + name_top: RndCnstAlertHandlerLfsrSeed + default: 0x4a52e672 + randwidth: 32 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: alert_pkg::lfsr_perm_t + randcount: 32 + randtype: perm + name_top: RndCnstAlertHandlerLfsrPerm + default: 0x1626ca235b3b6c124bfe5e54ebf4a934783055f0 + randwidth: 160 + } + ] + inter_signal_list: + [ + { + name: crashdump + struct: alert_crashdump + package: alert_pkg + type: uni + act: req + width: 1 + inst_name: alert_handler + default: "" + end_idx: -1 + top_type: broadcast + top_signame: alert_handler_crashdump + index: -1 + } + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: alert_handler + default: "" + top_signame: edn0_edn + index: 4 + } + { + name: esc_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: rcv + width: 4 + inst_name: alert_handler + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: alert_handler_esc_rx + index: -1 + } + { + name: esc_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: req + width: 4 + inst_name: alert_handler + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: alert_handler_esc_tx + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: alert_handler + default: "" + end_idx: -1 + top_signame: alert_handler_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30150000 + } + } + generate_dif: true + } + { + name: spi_host0 + type: spi_host + clock_srcs: + { + clk_i: io_div4 + } + clock_group: peri + reset_connections: + { + rst_ni: + { + name: spi_host0 + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_peri + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: passthrough + struct: passthrough + package: spi_device_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: spi_host0 + default: "" + top_signame: spi_device_passthrough + index: -1 + } + { + name: lsio_trigger + desc: + ''' + Self-clearing status trigger for the DMA. + Set when RX or TX FIFOs are past their configured watermarks matching watermark interrupt behaviour. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: spi_host0 + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: spi_host0_lsio_trigger + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: spi_host0 + default: "" + end_idx: -1 + top_signame: spi_host0_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30300000 + } + } + generate_dif: true + } + { + name: pwrmgr_aon + type: pwrmgr + clock_group: powerup + clock_srcs: + { + clk_i: io_div4 + clk_slow_i: aon + clk_lc_i: io_div4 + clk_esc_i: + { + clock: io_div4 + group: secure + } + } + reset_connections: + { + rst_ni: + { + name: por_io_div4 + domain: Aon + } + rst_main_ni: + { + name: por_aon + domain: "0" + } + rst_lc_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_esc_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_slow_ni: + { + name: por_aon + domain: Aon + } + } + domain: + [ + Aon + "0" + ] + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_powerup + clk_slow_i: clkmgr_aon_clocks.clk_aon_powerup + clk_lc_i: clkmgr_aon_clocks.clk_io_div4_powerup + clk_esc_i: clkmgr_aon_clocks.clk_io_div4_secure + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + index: -1 + } + { + name: pwr_ast + struct: pwr_ast + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + external: true + top_signame: pwrmgr_ast + conn_type: false + index: -1 + } + { + name: pwr_rst + struct: pwr_rst + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_rst + index: -1 + } + { + name: pwr_clk + struct: pwr_clk + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_clk + index: -1 + } + { + name: pwr_otp + struct: pwr_otp + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_otp + index: -1 + } + { + name: pwr_lc + struct: pwr_lc + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_lc + index: -1 + } + { + name: pwr_flash + struct: pwr_flash + package: pwrmgr_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + index: -1 + } + { + name: esc_rst_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: alert_handler_esc_tx + index: 3 + } + { + name: esc_rst_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: alert_handler_esc_rx + index: 3 + } + { + name: pwr_cpu + struct: pwr_cpu + package: pwrmgr_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: rv_core_ibex_pwrmgr + index: -1 + } + { + name: wakeups + struct: logic + type: uni + act: rcv + width: 6 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: one-to-N + top_signame: pwrmgr_aon_wakeups + index: -1 + } + { + name: rstreqs + struct: logic + type: uni + act: rcv + width: 2 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: one-to-N + top_signame: pwrmgr_aon_rstreqs + index: -1 + } + { + name: ndmreset_req + struct: logic + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + package: "" + top_signame: rv_dm_ndmreset_req + index: -1 + } + { + name: strap + struct: logic + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_strap + index: -1 + } + { + name: low_power + struct: logic + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_low_power + index: -1 + } + { + name: rom_ctrl + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_rom_ctrl + index: -1 + } + { + name: fetch_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_fetch_en + index: -1 + } + { + name: lc_dft_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: sw_rst_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: rstmgr_aon_sw_rst_req + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30400000 + } + } + generate_dif: true + } + { + name: rstmgr_aon + type: rstmgr + clock_srcs: + { + clk_i: + { + clock: io_div4 + group: powerup + } + clk_por_i: io_div4 + clk_aon_i: aon + clk_main_i: main + clk_io_i: io + clk_usb_i: usb + clk_io_div2_i: io_div2 + clk_io_div4_i: io_div4 + } + clock_group: powerup + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_por_ni: + { + name: por_io_div4 + domain: Aon + } + } + domain: + [ + Aon + "0" + ] + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_powerup + clk_por_i: clkmgr_aon_clocks.clk_io_div4_powerup + clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup + clk_main_i: clkmgr_aon_clocks.clk_main_powerup + clk_io_i: clkmgr_aon_clocks.clk_io_powerup + clk_usb_i: clkmgr_aon_clocks.clk_usb_powerup + clk_io_div2_i: clkmgr_aon_clocks.clk_io_div2_powerup + clk_io_div4_i: clkmgr_aon_clocks.clk_io_div4_powerup + } + param_decl: {} + memory: {} + param_list: + [ + { + name: SecCheck + desc: + ''' + When 1, enable rstmgr reset consistency checks. + When 0, there are no consistency checks. + ''' + type: bit + default: 1'b1 + local: "false" + expose: "true" + name_top: SecRstmgrAonCheck + } + { + name: SecMaxSyncDelay + desc: The maximum synchronization delay for parent / child reset checks. + type: int + default: "2" + local: "false" + expose: "true" + name_top: SecRstmgrAonMaxSyncDelay + } + ] + inter_signal_list: + [ + { + name: por_n + desc: + ''' + Root power on reset signals from ast. + There is one root reset signal for each core power domain. + ''' + struct: logic + type: uni + act: rcv + width: 2 + inst_name: rstmgr_aon + default: "" + package: "" + external: true + top_signame: por_n + conn_type: false + index: -1 + } + { + name: pwr + desc: + ''' + Reset request signals from power manager. + Power manager can request for specific domains of the lc/sys reset tree to assert. + ''' + struct: pwr_rst + type: req_rsp + act: rsp + width: 1 + inst_name: rstmgr_aon + default: "" + package: pwrmgr_pkg + top_signame: pwrmgr_aon_pwr_rst + index: -1 + } + { + name: resets + desc: Leaf resets fed to the system. + struct: rstmgr_out + package: rstmgr_pkg + type: uni + act: req + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: rstmgr_aon_resets + index: -1 + } + { + name: rst_en + desc: Low-power-group outputs used by alert handler. + struct: rstmgr_rst_en + package: rstmgr_pkg + type: uni + act: req + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: rstmgr_aon_rst_en + index: -1 + } + { + name: alert_dump + desc: Alert handler crash dump information. + struct: alert_crashdump + package: alert_pkg + type: uni + act: rcv + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: alert_handler_crashdump + index: -1 + } + { + name: cpu_dump + desc: Main processing element crash dump information. + struct: cpu_crash_dump + package: rv_core_ibex_pkg + type: uni + act: rcv + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: rv_core_ibex_crash_dump + index: -1 + } + { + name: sw_rst_req + desc: Software requested system reset to pwrmgr. + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: rstmgr_aon + default: "" + end_idx: -1 + top_type: broadcast + top_signame: rstmgr_aon_sw_rst_req + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rstmgr_aon + default: "" + end_idx: -1 + top_signame: rstmgr_aon_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30410000 + } + } + generate_dif: true + } + { + name: clkmgr_aon + type: clkmgr + clock_srcs: + { + clk_i: io_div4 + clk_main_i: + { + group: ast + clock: main + } + clk_io_i: + { + group: ast + clock: io + } + clk_usb_i: + { + group: ast + clock: usb + } + clk_aon_i: + { + group: ast + clock: aon + } + } + clock_group: powerup + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_aon_ni: + { + name: lc_aon + domain: Aon + } + rst_io_ni: + { + name: lc_io + domain: Aon + } + rst_io_div2_ni: + { + name: lc_io_div2 + domain: Aon + } + rst_io_div4_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_main_ni: + { + name: lc + domain: Aon + } + rst_usb_ni: + { + name: lc_usb + domain: Aon + } + rst_root_ni: + { + name: por_io_div4 + domain: Aon + } + rst_root_io_ni: + { + name: por_io + domain: Aon + } + rst_root_io_div2_ni: + { + name: por_io_div2 + domain: Aon + } + rst_root_io_div4_ni: + { + name: por_io_div4 + domain: Aon + } + rst_root_main_ni: + { + name: por + domain: Aon + } + rst_root_usb_ni: + { + name: por_usb + domain: Aon + } + } + domain: + [ + Aon + ] + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_powerup + clk_main_i: clk_main_i + clk_io_i: clk_io_i + clk_usb_i: clk_usb_i + clk_aon_i: clk_aon_i + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: clocks + struct: clkmgr_out + package: clkmgr_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: clkmgr_aon_clocks + index: -1 + } + { + name: cg_en + struct: clkmgr_cg_en + package: clkmgr_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: clkmgr_aon_cg_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: io_clk_byp_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: io_clk_byp_req + conn_type: false + index: -1 + } + { + name: io_clk_byp_ack + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: io_clk_byp_ack + conn_type: false + index: -1 + } + { + name: all_clk_byp_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: all_clk_byp_req + conn_type: false + index: -1 + } + { + name: all_clk_byp_ack + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: all_clk_byp_ack + conn_type: false + index: -1 + } + { + name: hi_speed_sel + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: hi_speed_sel + conn_type: false + index: -1 + } + { + name: div_step_down_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: div_step_down_req + conn_type: false + index: -1 + } + { + name: lc_clk_byp_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: lc_ctrl_lc_clk_byp_req + index: -1 + } + { + name: lc_clk_byp_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: lc_ctrl_lc_clk_byp_ack + index: -1 + } + { + name: jitter_en + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: clk_main_jitter_en + conn_type: false + index: -1 + } + { + name: pwr + struct: pwr_clk + type: req_rsp + act: rsp + width: 1 + inst_name: clkmgr_aon + default: "" + package: pwrmgr_pkg + top_signame: pwrmgr_aon_pwr_clk + index: -1 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 4 + inst_name: clkmgr_aon + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: clkmgr_aon_idle + index: -1 + } + { + name: calib_rdy + desc: Indicates clocks are calibrated and frequencies accurate + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi4True + inst_name: clkmgr_aon + external: true + top_signame: calib_rdy + conn_type: false + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: clkmgr_aon + default: "" + end_idx: -1 + top_signame: clkmgr_aon_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30420000 + } + } + generate_dif: true + } + { + name: pinmux_aon + type: pinmux + clock_srcs: + { + clk_i: io_div4 + clk_aon_i: aon + } + clock_group: powerup + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_aon_ni: + { + name: lc_aon + domain: Aon + } + rst_sys_ni: + { + name: sys_io_div4 + domain: Aon + } + } + domain: + [ + Aon + ] + attr: ipgen + param_decl: + { + SecVolatileRawUnlockEn: top_pkg::SecVolatileRawUnlockEn + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_powerup + clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup + } + memory: {} + param_list: + [ + { + name: SecVolatileRawUnlockEn + desc: + ''' + Disable (0) or enable (1) volatile RAW UNLOCK capability. + If enabled, the strap_en_override_i input can be used to re-sample the straps at runtime. + + IMPORTANT NOTE: This should only be used in test chips. The parameter must be set + to 0 in production tapeouts since this weakens the security posture of the RAW + UNLOCK mechanism. + ''' + type: bit + default: top_pkg::SecVolatileRawUnlockEn + local: "false" + expose: "true" + name_top: SecPinmuxAonVolatileRawUnlockEn + } + { + name: TargetCfg + desc: Target specific pinmux configuration. + type: pinmux_pkg::target_cfg_t + default: pinmux_pkg::DefaultTargetCfg + local: "false" + expose: "true" + name_top: PinmuxAonTargetCfg + } + ] + inter_signal_list: + [ + { + name: lc_hw_debug_en + desc: Debug enable qualifier coming from life cycle controller, used for HW strap qualification. + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: pinmux_aon + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: lc_dft_en + desc: Test enable qualifier coming from life cycle controller, used for HW strap qualification. + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: pinmux_aon + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_escalate_en + desc: + ''' + Escalation enable signal coming from life cycle controller, used for invalidating + the latched lc_hw_debug_en state inside the strap sampling logic. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: pinmux_aon + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_check_byp_en + desc: + ''' + Check bypass enable signal coming from life cycle controller, used for invalidating + the latched lc_hw_debug_en state inside the strap sampling logic. This signal is asserted + whenever the life cycle controller performs a life cycle transition. Its main use is + to skip any background checks inside the life cycle partition of the OTP controller while + a life cycle transition is in progress. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: pinmux_aon + top_signame: lc_ctrl_lc_check_byp_en + index: -1 + } + { + name: pinmux_hw_debug_en + desc: + ''' + This is the latched version of lc_hw_debug_en_i. We use it exclusively to gate the JTAG + signals and TAP side of the RV_DM so that RV_DM can remain live during an NDM reset cycle. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: pinmux_aon + index: -1 + } + { + name: lc_jtag + desc: Qualified JTAG signals for life cycle controller TAP. + struct: jtag + package: jtag_pkg + type: req_rsp + act: req + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: rv_jtag + desc: Qualified JTAG signals for RISC-V processor TAP. + struct: jtag + package: jtag_pkg + type: req_rsp + act: req + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: dft_jtag + desc: Qualified JTAG signals for DFT TAP. + struct: jtag + package: jtag_pkg + type: req_rsp + act: req + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: dft_strap_test + desc: Sampled DFT strap values, going to the DFT TAP. + struct: dft_strap_test_req + package: pinmux_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: pinmux_aon + external: true + top_signame: dft_strap_test + conn_type: false + index: -1 + } + { + name: dft_hold_tap_sel + desc: TAP selection hold indication, asserted by the DFT TAP during boundary scan. + struct: logic + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: pinmux_aon + package: "" + external: true + top_signame: dft_hold_tap_sel + conn_type: false + index: -1 + } + { + name: sleep_en + desc: Level signal that is asserted when the power manager enters sleep. + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: pwrmgr_aon_low_power + index: -1 + } + { + name: strap_en + desc: This signal is pulsed high by the power manager after reset in order to sample the HW straps. + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: pwrmgr_aon_strap + index: -1 + } + { + name: strap_en_override + desc: + ''' + This signal transitions from 0 -> 1 by the lc_ctrl manager after volatile RAW_UNLOCK in order to re-sample the HW straps. + The signal must stay at 1 until reset. + Note that this is only used in test chips when SecVolatileRawUnlockEn = 1. + Otherwise this signal is unused. + ''' + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: lc_ctrl_strap_en_override + index: -1 + } + { + name: pin_wkup_req + desc: Wakeup request from wakeup detectors, to the power manager, running on the AON clock. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: pwrmgr_aon_wakeups + index: 0 + } + { + name: usbdev_dppullup_en + desc: Pullup enable signal coming from the USB IP. + struct: logic + type: uni + act: rcv + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: usbdev_dnpullup_en + desc: Pullup enable signal coming from the USB IP. + struct: logic + type: uni + act: rcv + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: usb_dppullup_en + desc: " Pullup enable signal going to USB PHY, needs to be maintained in low-power mode." + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + index: -1 + } + { + name: usb_dnpullup_en + desc: Pullup enable signal going to USB PHY, needs to be maintained in low-power mode. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + index: -1 + } + { + name: usb_wkup_req + desc: Wakeup request from USB wakeup detector, going to the power manager, running on the AON clock. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: pwrmgr_aon_wakeups + index: 1 + } + { + name: usbdev_suspend_req + desc: Indicates whether USB is in suspended state, coming from the USB device. + struct: logic + type: uni + act: rcv + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: usbdev_wake_ack + desc: Acknowledges the USB wakeup request, coming from the USB device. + struct: logic + type: uni + act: rcv + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: usbdev_bus_not_idle + desc: Event signal that indicates that the USB was not idle while monitoring. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + index: -1 + } + { + name: usbdev_bus_reset + desc: Event signal that indicates that the USB issued a Bus Reset while monitoring. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + index: -1 + } + { + name: usbdev_sense_lost + desc: Event signal that indicates that USB SENSE signal was lost while monitoring. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + index: -1 + } + { + name: usbdev_wake_detect_active + desc: State debug information. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: pinmux_aon + default: "" + end_idx: -1 + top_signame: pinmux_aon_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30460000 + } + } + generate_dif: true + } + { + name: aon_timer_aon + type: aon_timer + clock_srcs: + { + clk_i: io_div4 + clk_aon_i: aon + } + clock_group: timers + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_aon_ni: + { + name: lc_aon + domain: Aon + } + } + domain: + [ + Aon + ] + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_timers + clk_aon_i: clkmgr_aon_clocks.clk_aon_timers + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: nmi_wdog_timer_bark + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: aon_timer_aon + package: "" + end_idx: -1 + top_type: broadcast + top_signame: aon_timer_aon_nmi_wdog_timer_bark + index: -1 + } + { + name: wkup_req + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: aon_timer_aon + package: "" + top_signame: pwrmgr_aon_wakeups + index: 2 + } + { + name: aon_timer_rst_req + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: aon_timer_aon + package: "" + top_signame: pwrmgr_aon_rstreqs + index: 0 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: aon_timer_aon + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: sleep_mode + struct: logic + type: uni + act: rcv + width: 1 + inst_name: aon_timer_aon + default: "" + package: "" + top_signame: pwrmgr_aon_low_power + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: aon_timer_aon + default: "" + end_idx: -1 + top_signame: aon_timer_aon_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30470000 + } + } + generate_dif: true + } + { + name: ast + type: ast + clock_srcs: + { + clk_ast_tlul_i: + { + clock: io_div4 + group: infra + } + clk_ast_adc_i: + { + clock: aon + group: peri + } + clk_ast_alert_i: + { + clock: io_div4 + group: secure + } + clk_ast_es_i: + { + clock: main + group: secure + } + clk_ast_rng_i: + { + clock: main + group: secure + } + clk_ast_usb_i: + { + clock: usb + group: peri + } + } + clock_group: secure + reset_connections: + { + rst_ast_tlul_ni: + { + name: lc_io_div4 + domain: "0" + } + rst_ast_adc_ni: + { + name: lc_aon + domain: Aon + } + rst_ast_alert_ni: + { + name: lc_io_div4 + domain: "0" + } + rst_ast_es_ni: + { + name: lc + domain: "0" + } + rst_ast_rng_ni: + { + name: lc + domain: "0" + } + rst_ast_usb_ni: + { + name: por_usb + domain: "0" + } + } + domain: + [ + Aon + "0" + ] + attr: reggen_only + clock_connections: + { + clk_ast_tlul_i: clkmgr_aon_clocks.clk_io_div4_infra + clk_ast_adc_i: clkmgr_aon_clocks.clk_aon_peri + clk_ast_alert_i: clkmgr_aon_clocks.clk_io_div4_secure + clk_ast_es_i: clkmgr_aon_clocks.clk_main_secure + clk_ast_rng_i: clkmgr_aon_clocks.clk_main_secure + clk_ast_usb_i: clkmgr_aon_clocks.clk_usb_peri + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: ast + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30480000 + } + } + generate_dif: true + } + { + name: sensor_ctrl + type: sensor_ctrl + clock_srcs: + { + clk_i: io_div4 + clk_aon_i: aon + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_aon_ni: + { + name: lc_aon + domain: Aon + } + } + domain: + [ + Aon + ] + attr: reggen_top + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_secure + clk_aon_i: clkmgr_aon_clocks.clk_aon_secure + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: ast_alert + struct: ast_alert + package: ast_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sensor_ctrl + default: "" + external: true + top_signame: sensor_ctrl_ast_alert + conn_type: false + index: -1 + } + { + name: ast_status + struct: ast_status + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: sensor_ctrl + default: "" + external: true + top_signame: sensor_ctrl_ast_status + conn_type: false + index: -1 + } + { + name: ast_init_done + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi4True + inst_name: sensor_ctrl + external: true + top_signame: ast_init_done + conn_type: false + index: -1 + } + { + name: wkup_req + struct: logic + type: uni + act: req + width: 1 + inst_name: sensor_ctrl + default: "" + package: "" + top_signame: pwrmgr_aon_wakeups + index: 3 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sensor_ctrl + default: "" + end_idx: -1 + top_signame: sensor_ctrl_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30020000 + } + } + generate_dif: true + } + { + name: soc_proxy + type: soc_proxy + clock_srcs: + { + clk_i: main + clk_aon_i: aon + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_por_ni: + { + name: por_io_div4 + domain: Aon + } + } + domain: + [ + Aon + "0" + ] + base_addrs: + { + core: + { + hart: 0x22030000 + } + ctn: + { + hart: 0x40000000 + } + } + attr: reggen_top + memory: + { + ctn: + { + label: ctn + swaccess: rw + data_intg_passthru: "true" + exec: True + byte_write: True + size: 0x40000000 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + clk_aon_i: clkmgr_aon_clocks.clk_aon_infra + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: wkup_internal_req + struct: logic + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: pwrmgr_aon_wakeups + index: 4 + } + { + name: wkup_external_req + struct: logic + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: pwrmgr_aon_wakeups + index: 5 + } + { + name: rst_req_external + struct: logic + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: pwrmgr_aon_rstreqs + index: 1 + } + { + name: ctn_tl_h2d + desc: TL-UL host port for egress into CTN (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + external: true + top_signame: ctn_tl_h2d + conn_type: false + index: -1 + } + { + name: ctn_tl_d2h + desc: TL-UL host port for egress into CTN (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + external: true + top_signame: ctn_tl_d2h + conn_type: false + index: -1 + } + { + name: i2c_lsio_trigger + desc: LSIO trigger signal from I2C + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: i2c0_lsio_trigger + index: -1 + } + { + name: spi_host_lsio_trigger + desc: LSIO trigger signal from SPI Host + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: spi_host0_lsio_trigger + index: -1 + } + { + name: uart_lsio_trigger + desc: LSIO trigger signal from UART + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: uart0_lsio_trigger + index: -1 + } + { + name: soc_lsio_trigger + desc: LSIO trigger signal from SoC, synchronous + struct: logic + type: uni + act: rcv + width: 8 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_lsio_trigger + conn_type: false + index: -1 + } + { + name: dma_lsio_trigger + desc: Collated synchronous LSIO trigger signals for DMA + struct: lsio_trigger + package: dma_pkg + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + top_signame: dma_lsio_trigger + index: -1 + } + { + name: soc_fatal_alert + desc: Differential fatal alert from SoC, synchronous + struct: soc_alert + package: soc_proxy_pkg + type: req_rsp + act: rsp + width: 24 + inst_name: soc_proxy + default: "" + external: true + top_signame: soc_fatal_alert + conn_type: false + index: -1 + } + { + name: soc_recov_alert + desc: Differential recoverable alert from SoC, synchronous + struct: soc_alert + package: soc_proxy_pkg + type: req_rsp + act: rsp + width: 4 + inst_name: soc_proxy + default: "" + external: true + top_signame: soc_recov_alert + conn_type: false + index: -1 + } + { + name: soc_wkup_async + desc: Wakeup request from SoC, asynchronous, level-encoded + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_wkup_async + conn_type: false + index: -1 + } + { + name: soc_rst_req_async + desc: Reset request from SoC, asynchronous, level-encoded + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_rst_req_async + conn_type: false + index: -1 + } + { + name: soc_intr_async + desc: Interrupt request from SoC, asynchronous, level-encoded + struct: logic + type: uni + act: rcv + width: 32 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_intr_async + conn_type: false + index: -1 + } + { + name: soc_gpi_async + desc: GPI from SoC, async + struct: logic + type: uni + act: req + width: 16 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_gpi_async + conn_type: false + index: -1 + } + { + name: soc_gpo_async + desc: GPO from SoC, async + struct: logic + type: uni + act: rcv + width: 16 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_gpo_async + conn_type: false + index: -1 + } + { + name: core_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_signame: soc_proxy_core_tl + index: -1 + } + { + name: ctn_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_signame: soc_proxy_ctn_tl + index: -1 + } + ] + generate_dif: true + } + { + name: sram_ctrl_ret_aon + type: sram_ctrl + clock_srcs: + { + clk_i: io_div4 + clk_otp_i: io_div4 + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_otp_ni: + { + name: lc_io_div4 + domain: Aon + } + } + domain: + [ + Aon + ] + param_decl: + { + InstrExec: "0" + } + base_addrs: + { + regs: + { + hart: 0x30500000 + } + ram: + { + hart: 0x30600000 + } + } + memory: + { + ram: + { + label: ram_ret_aon + swaccess: rw + data_intg_passthru: "true" + exec: True + byte_write: True + size: 0x1000 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_infra + clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra + } + param_list: + [ + { + name: RndCnstSramKey + desc: Compile-time random reset value for SRAM scrambling key. + type: otp_ctrl_pkg::sram_key_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlRetAonSramKey + default: 0x55e0f8150242862eb20eea9a1f754471 + randwidth: 128 + } + { + name: RndCnstSramNonce + desc: Compile-time random reset value for SRAM scrambling nonce. + type: otp_ctrl_pkg::sram_nonce_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlRetAonSramNonce + default: 0x6551512a112ded678ce824a08e29c772 + randwidth: 128 + } + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: sram_ctrl_pkg::lfsr_seed_t + randcount: 32 + randtype: data + name_top: RndCnstSramCtrlRetAonLfsrSeed + default: 0x795a358e + randwidth: 32 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: sram_ctrl_pkg::lfsr_perm_t + randcount: 32 + randtype: perm + name_top: RndCnstSramCtrlRetAonLfsrPerm + default: 0x44cfc8b58b71209029f2b7fa22de86de7d5d0c38 + randwidth: 160 + } + { + name: MemSizeRam + desc: Memory size of the RAM (in bytes). + type: int + name_top: MemSizeSramCtrlRetAonRam + default: 4096 + } + { + name: InstrExec + desc: Support execution from SRAM + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SramCtrlRetAonInstrExec + } + { + name: NumPrinceRoundsHalf + desc: Number of PRINCE half rounds for the SRAM scrambling feature + type: int + default: "3" + local: "false" + expose: "true" + name_top: SramCtrlRetAonNumPrinceRoundsHalf + } + ] + inter_signal_list: + [ + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_ret_aon + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 1 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: sram_ctrl_ret_aon + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_ret_aon + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_ret_aon + default: "" + end_idx: -1 + top_signame: sram_ctrl_ret_aon_regs_tl + index: -1 + } + { + name: ram_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_ret_aon + default: "" + end_idx: -1 + top_signame: sram_ctrl_ret_aon_ram_tl + index: -1 + } + ] + generate_dif: true + } + { + name: rv_dm + type: rv_dm + clock_srcs: + { + clk_i: main + clk_lc_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: sys + domain: "0" + } + rst_lc_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + mem: + { + hart: 0x00040000 + } + regs: + { + hart: 0x21200000 + } + dbg: + { + soc_dbg: 0x00000000 + } + } + param_decl: + { + SecVolatileRawUnlockEn: top_pkg::SecVolatileRawUnlockEn + UseDmiInterface: "1" + } + generate_dif: false + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + clk_lc_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + memory: {} + param_list: + [ + { + name: IdcodeValue + desc: RISC-V debug module JTAG ID code. + type: logic [31:0] + default: 32'h 0000_0001 + local: "false" + expose: "true" + name_top: RvDmIdcodeValue + } + { + name: UseDmiInterface + desc: When 1, a TLUL-based DMI interface is used. When 0, a JTAG TAP is used. + type: bit + default: "1" + local: "false" + expose: "true" + name_top: RvDmUseDmiInterface + } + { + name: SecVolatileRawUnlockEn + desc: + ''' + Disable (0) or enable (1) volatile RAW UNLOCK capability. + If enabled, the strap_en_override_i input can be used to re-sample the straps at runtime. + IMPORTANT NOTE: This should only be used in test chips. The parameter must be set + to 0 in production tapeouts since this weakens the security posture of the RAW + UNLOCK mechanism. + ''' + type: bit + default: top_pkg::SecVolatileRawUnlockEn + local: "false" + expose: "true" + name_top: SecRvDmVolatileRawUnlockEn + } + ] + inter_signal_list: + [ + { + name: next_dm_addr + desc: + ''' + 32bit word address of the next debug module. + Set to 0x0 if this is the last debug module in the chain. + ''' + struct: next_dm_addr + package: rv_dm_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: rv_dm + external: true + top_signame: rv_dm_next_dm_addr + conn_type: false + index: -1 + } + { + name: jtag + desc: JTAG signals for the RISC-V TAP. + struct: jtag + package: jtag_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + index: -1 + } + { + name: lc_hw_debug_en + desc: + ''' + Multibit life cycle hardware debug enable signal coming from life cycle controller, + asserted when the hardware debug mechanisms are enabled in the system. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: rv_dm + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: lc_dft_en + desc: + ''' + Multibit life cycle hardware debug enable signal coming from life cycle controller, + asserted when the DFT mechanisms are enabled in the system. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: rv_dm + index: -1 + } + { + name: pinmux_hw_debug_en + desc: + ''' + Multibit life cycle hardware debug enable signal coming from pinmux. + This is a latched version of the lc_hw_debug_en signal and is only used to + gate the JTAG / TAP side of the RV_DM. It is used to keep a debug session live + while the rest of the system undergoes an NDM reset. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: rv_dm + index: -1 + } + { + name: otp_dis_rv_dm_late_debug + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: rv_dm + index: -1 + } + { + name: unavailable + desc: + ''' + This signal indicates to the debug module that the main processor is not available + for debug (e.g. due to a low-power state). + ''' + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: rv_dm + index: -1 + } + { + name: ndmreset_req + desc: Non-debug module reset request going to the system reset infrastructure. + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_dm + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_dm_ndmreset_req + index: -1 + } + { + name: dmactive + desc: + ''' + This signal indicates whether the debug module is active and can be used to prevent + power down of the core and bus-attached peripherals. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_dm + index: -1 + } + { + name: debug_req + desc: This is the debug request interrupt going to the main processor. + struct: logic [rv_dm_reg_pkg::NrHarts-1:0] + type: uni + act: req + width: 1 + inst_name: rv_dm + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_dm_debug_req + index: -1 + } + { + name: lc_escalate_en + desc: + ''' + Escalation enable signal coming from life cycle controller, used for invalidating + the latched lc_hw_debug_en state inside the strap sampling logic. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: rv_dm + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_check_byp_en + desc: + ''' + Check bypass enable signal coming from life cycle controller, used for invalidating + the latched lc_hw_debug_en state inside the strap sampling logic. This signal is asserted + whenever the life cycle controller performs a life cycle transition. Its main use is + to skip any background checks inside the life cycle partition of the OTP controller while + a life cycle transition is in progress. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: rv_dm + top_signame: lc_ctrl_lc_check_byp_en + index: -1 + } + { + name: strap_en + desc: This signal is pulsed high by the power manager after reset in order to sample the HW straps. + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: rv_dm + package: "" + top_signame: pwrmgr_aon_strap + index: -1 + } + { + name: strap_en_override + desc: + ''' + This signal transitions from 0 -> 1 by the lc_ctrl manager after volatile RAW_UNLOCK in order to re-sample the HW straps. + The signal must stay at 1 until reset. + Note that this is only used in test chips when SecVolatileRawUnlockEn = 1. + Otherwise this signal is unused. + ''' + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: rv_dm + package: "" + top_signame: lc_ctrl_strap_en_override + index: -1 + } + { + name: sba_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_dm + default: "" + top_signame: main_tl_rv_dm__sba + index: -1 + } + { + name: regs_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_regs_tl_d + index: -1 + } + { + name: mem_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_mem_tl_d + index: -1 + } + { + name: dbg_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_dbg_tl_d + index: -1 + } + ] + } + { + name: rv_plic + type: rv_plic + clock_srcs: + { + clk_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_secure + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: irq + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_plic_irq + index: -1 + } + { + name: irq_id + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + index: -1 + } + { + name: msip + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_plic_msip + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_plic + default: "" + end_idx: -1 + top_signame: rv_plic_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x28000000 + } + } + generate_dif: true + } + { + name: aes + type: aes + clock_srcs: + { + clk_i: main + clk_edn_i: main + } + clock_group: trans + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + } + param_decl: + { + SecMasking: "1" + SecSBoxImpl: aes_pkg::SBoxImplDom + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_aes + clk_edn_i: clkmgr_aon_clocks.clk_main_aes + } + domain: + [ + "0" + ] + memory: {} + param_list: + [ + { + name: AES192Enable + desc: Disable (0) or enable (1) support for 192-bit key lengths (AES-192). + type: bit + default: 1'b1 + local: "false" + expose: "false" + name_top: AesAES192Enable + } + { + name: SecMasking + desc: + ''' + Disable (0) or enable (1) first-order masking of the AES cipher core. + Masking requires the use of a masked S-Box, see SecSBoxImpl parameter. + ''' + type: bit + default: "1" + local: "false" + expose: "true" + name_top: SecAesMasking + } + { + name: SecSBoxImpl + desc: Selection of the S-Box implementation. See aes_pkg.sv. + type: aes_pkg::sbox_impl_e + default: aes_pkg::SBoxImplDom + local: "false" + expose: "true" + name_top: SecAesSBoxImpl + } + { + name: SecStartTriggerDelay + desc: + ''' + Manual start trigger delay, useful for SCA measurements. + A value of e.g. 40 allows the processor to go into sleep before AES starts operation. + ''' + type: int unsigned + default: "0" + local: "false" + expose: "true" + name_top: SecAesStartTriggerDelay + } + { + name: SecAllowForcingMasks + desc: + ''' + Forbid (0) or allow (1) forcing the masking PRNG output to a constant value via FORCE_MASKS bit in the Auxiliary Control Register. + Useful for SCA measurements. + Meaningful only if masking is enabled. + ''' + type: bit + default: 1'b0 + local: "false" + expose: "true" + name_top: SecAesAllowForcingMasks + } + { + name: SecSkipPRNGReseeding + desc: + ''' + Perform (0) or skip (1) PRNG reseeding requests, useful for SCA measurements only. + The current SCA setup doesn't provide sufficient resources to implement the infrastructure required for PRNG reseeding (CSRNG, EDN). + To enable SCA resistance evaluations, we need to skip reseeding requests on the SCA platform. + ''' + type: bit + default: 1'b0 + local: "false" + expose: "true" + name_top: SecAesSkipPRNGReseeding + } + { + name: RndCnstClearingLfsrSeed + desc: Default seed of the PRNG used for register clearing. + type: aes_pkg::clearing_lfsr_seed_t + randcount: 64 + randtype: data + name_top: RndCnstAesClearingLfsrSeed + default: 0xd1095889fbd8a7b5 + randwidth: 64 + } + { + name: RndCnstClearingLfsrPerm + desc: Permutation applied to the LFSR of the PRNG used for clearing. + type: aes_pkg::clearing_lfsr_perm_t + randcount: 64 + randtype: perm + name_top: RndCnstAesClearingLfsrPerm + default: 0x392fa90de595ff713b4289dd4e117922432f280449db552506281ac8698b62bbb13cdf02b73d2a71b8d7f7ac191f8b1f + randwidth: 384 + } + { + name: RndCnstClearingSharePerm + desc: Permutation applied to the clearing PRNG output for clearing the second share of registers. + type: aes_pkg::clearing_lfsr_perm_t + randcount: 64 + randtype: perm + name_top: RndCnstAesClearingSharePerm + default: 0x3e5ab51c865bf6d4ddc1eb8653f32333b7dfca24814fa1f11d61b095a971ec8101b4c0e8d14a79392e689e6a9c6eec3 + randwidth: 384 + } + { + name: RndCnstMaskingLfsrSeed + desc: Default seed of the PRNG used for masking. + type: aes_pkg::masking_lfsr_seed_t + randcount: 288 + randtype: data + name_top: RndCnstAesMaskingLfsrSeed + default: 0x82fa14a8f2b75c265c9cb3b2f1c44a7287ab4c0618822e92a084a048ffe9fb86140a79d3 + randwidth: 288 + } + { + name: RndCnstMaskingLfsrPerm + desc: Permutation applied to the output of the PRNG used for masking. + type: aes_pkg::masking_lfsr_perm_t + randcount: 160 + randtype: perm + name_top: RndCnstAesMaskingLfsrPerm + default: 0x706668853241427a1d5665590d530c47458c23975c21863c917c5160370783248b9a7f93736277065a392f1b8e7e6f4e81118a1c79589d74042b0817710f252d486488192a2e49004610129e1a3192288257843f894c090a50695440616a1e966c362038144d159535346d02875d9c18754a268f0b015b1f781376299827220e9f7b8d90437d4f6b3d723a05639967169b30446e52942c335e033e3b5f4b5580 + randwidth: 1280 + } + ] + inter_signal_list: + [ + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: aes + default: "" + top_signame: clkmgr_aon_idle + index: 0 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: aes + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: aes + default: "" + top_signame: edn0_edn + index: 5 + } + { + name: keymgr_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: aes + default: "" + top_signame: keymgr_dpe_aes_key + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: aes + default: "" + end_idx: -1 + top_signame: aes_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21100000 + } + } + generate_dif: true + } + { + name: hmac + type: hmac + clock_srcs: + { + clk_i: main + } + clock_group: trans + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_hmac + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: hmac + default: "" + top_signame: clkmgr_aon_idle + index: 1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: hmac + default: "" + end_idx: -1 + top_signame: hmac_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21110000 + } + } + generate_dif: true + } + { + name: kmac + type: kmac + param_decl: + { + EnMasking: "1" + NumAppIntf: 4 + AppCfg: "'{kmac_pkg::AppCfgKeyMgr, kmac_pkg::AppCfgLcCtrl, kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgRomCtrl}" + } + clock_srcs: + { + clk_i: main + clk_edn_i: main + } + clock_group: trans + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_kmac + clk_edn_i: clkmgr_aon_clocks.clk_main_kmac + } + domain: + [ + "0" + ] + memory: {} + param_list: + [ + { + name: EnMasking + desc: Disable(0) or enable(1) first-order masking of Keccak round. + type: bit + default: "1" + local: "false" + expose: "true" + name_top: KmacEnMasking + } + { + name: SwKeyMasked + desc: + ''' + Disable(0) or enable(1) software key masking in case masking is disabled (EnMasking == 0). + If masking is enabled, this parameter has no effect. + Mainly useful for software interface compatibility between the masked and unmasked design. + Mostly relevant for SCA measurements. + ''' + type: bit + default: "0" + local: "false" + expose: "true" + name_top: KmacSwKeyMasked + } + { + name: SecCmdDelay + desc: + ''' + Command delay, useful for SCA measurements only. + A value of e.g. 40 allows the processor to go into sleep before KMAC starts operation. + If a value greater than 0 is chosen, software can pass two commands in series. + The second command is buffered internally and will be presented to the hardware SecCmdDelay number of cycles after the first one. + ''' + type: int + default: "0" + local: "false" + expose: "true" + name_top: SecKmacCmdDelay + } + { + name: SecIdleAcceptSwMsg + desc: + ''' + If enabled (1), software writes to the message FIFO before having received a START command are not ignored. + Disabled (0) by default. + Useful for SCA measurements only. + ''' + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SecKmacIdleAcceptSwMsg + } + { + name: NumAppIntf + desc: Number of application interfaces + type: int + default: 4 + local: "false" + expose: "true" + name_top: KmacNumAppIntf + } + { + name: AppCfg + desc: + ''' + Application interface configuration. + Top-level connection to the application interface must follow this definition. + ''' + type: kmac_pkg::app_config_t + unpacked_dimensions: "[KmacNumAppIntf]" + default: "'{kmac_pkg::AppCfgKeyMgr, kmac_pkg::AppCfgLcCtrl, kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgRomCtrl}" + local: "false" + expose: "true" + name_top: KmacAppCfg + } + { + name: RndCnstLfsrSeed + desc: Compile-time random data for PRNG default seed + type: kmac_pkg::lfsr_seed_t + randcount: 288 + randtype: data + name_top: RndCnstKmacLfsrSeed + default: 0xe933d88e2e1cf65460f23fb780499e6fcce64ceafd282c0e33fd2c07986c2a511755f072 + randwidth: 288 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for PRNG output + type: kmac_pkg::lfsr_perm_t + randcount: 800 + randtype: perm + name_top: RndCnstKmacLfsrPerm + default: 0x99e8e2963e89488b131d0c872324f63425f3cede85ef7490761b0ec0ad251fc8163069a65313c5ada542e455d553aeb37506368df89c1876c38c3186c6aa35aced838342b42d847188a8c8685c27895eb4905481af5de7e87210799f63a6ad1388d0561b49c2a1e99b8763592caa899bb52e072e92ba9a20abd6235d97aa5183c30f09cff5bcde2d5b6ae2e17b9347dd7c97164a698e620cb22e087c2318b8090190182aa8262847c4f77240a1453ab18bf07857400be5bb0d07c504fe02279ec0fc901a03ec0c339a18b2554d68dcb19079beec0c1c169bd569b62826ace962b26fcbb3e4b11019ebe0a119b149e27da4222ac45f4230123306a30ee28244bb52ca91b27f56c759b0625d131a005f6ff09569886c5932f6b70d2345cf83128c7c9426e6b049d9575eb1a8995d16a728e190adb5547b2e6617e6d750da619da7216bd1b65d6ad9348f1699a543925e3bdd8039a5180002beb529c9638b000c19271ee67b5c65c140b94d65e51b6021259cc0a71e5476c36e9acb0ab960504a791c6426c9d1b4a1ce8adc622b1d7c0a50195b377c6b4d824afe9391ac1b4dd07d4a6218718b56151de7868fc38f17c1429106e97f1cd398b08d0a4beafd13c217490c355a09048a6aafe0a1c804dbc939cc98f1021cc45da92af8a3a2cfe6e6706c6d4a9e3c80492540ca1571911d2252a83aea4344603c1160a089f3615c82ee88b0d370d2aa5a49161e14e4802baef60a8fbe6d912a60944cc0c68a1f6b44cecd07449179a8516c9825e403cfbc557ba75fb314c25d45266910a8571900c3b819d2f19c8db0a6580b7e9097a1993ca47860b358c48850370047e2d88474dd428b1e1d4dc88e59271f49d4088a44bbb00d99112654e72de2fb68fd3ea3a9e50db7c3552129ada65ba93c118c7512056f90a650930650b532f56b93b2ca4d008a883eb3b88898ca45499662757fbc2ca6d58d1b8107c83d41e7c43e94b6224a615a544363645c4f82660df8b1ebbb2f1369054a44058fe1faaa2b9ed49779e94c15f6dddd1d1ce8edf3b3f08a7c5ab40cf08b1ba943b06db86897395c5bb20b8988429683c20985a1a89712f492914564637bceb8102cc3a7a7a98f6f4cd9b92e7fa55485547fd3d706523d1e31e23323a1962903c4a0605d3208e88518ce662f2836155497245ce59207353cf51326915aee9d80cb90a99a87725ed1702304d6ae4e16d9c64faf2130e941a35dc47e7220cb4a5c04c26d58dd166101c14ee74099f61d13114436a470174abb5a5b94e9b1bef1560208f6f35e091aad19596391851e3827f00c591f0c1069e03e2b03a942768d4a0039b8e7723d1a87a85a81c5b31370bd2f4b44db765601cbd04673ab16885aa255d7e54d915e81436f1cc2d0ebf15ba0444c4638 + randwidth: 8000 + } + { + name: RndCnstBufferLfsrSeed + desc: Compile-time random data for PRNG buffer default seed + type: kmac_pkg::buffer_lfsr_seed_t + randcount: 800 + randtype: data + name_top: RndCnstKmacBufferLfsrSeed + default: 0x46c49f15a16a2a1fd01f8e09d92dd13e0298799d91c54bfd2a51f45aadf344c262bb0abde9b240d763da6c4250ba5a44a7d4f4d7f99b4a6480da2d53e7ca15201a8f56530010117f58c9e9946c11180407feb4710f404e6e4face59b972d1fdcaf711c05 + randwidth: 800 + } + { + name: RndCnstMsgPerm + desc: Compile-time random permutation for LFSR Message output + type: kmac_pkg::msg_perm_t + randcount: 64 + randtype: perm + name_top: RndCnstKmacMsgPerm + default: 0x1abba9f8ce16cf92d4b5c3c26435ecd4dde0615485c5d6e89bb244d3d7f0abc0641d346786323688abc0eb2fe541e39a + randwidth: 384 + } + ] + inter_signal_list: + [ + { + name: keymgr_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: kmac + default: "" + top_signame: keymgr_dpe_kmac_key + index: -1 + } + { + name: app + struct: app + package: kmac_pkg + type: req_rsp + act: rsp + width: + { + name: NumAppIntf + desc: Number of application interfaces + param_type: int + unpacked_dimensions: null + default: 3 + local: false + expose: true + name_top: KmacNumAppIntf + } + inst_name: kmac + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: kmac_app + index: -1 + } + { + name: entropy + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: kmac + default: "" + top_signame: edn0_edn + index: 3 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: kmac + default: "" + top_signame: clkmgr_aon_idle + index: 2 + } + { + name: en_masking + struct: logic + type: uni + act: req + width: 1 + inst_name: kmac + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: kmac_en_masking + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: kmac + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: kmac + default: "" + end_idx: -1 + top_signame: kmac_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21120000 + } + } + generate_dif: true + } + { + name: otbn + type: otbn + clock_srcs: + { + clk_i: + { + clock: main + group: trans + } + clk_edn_i: + { + clock: main + group: secure + } + clk_otp_i: + { + clock: io_div4 + group: secure + } + } + clock_group: trans + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + rst_otp_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_otbn + clk_edn_i: clkmgr_aon_clocks.clk_main_secure + clk_otp_i: clkmgr_aon_clocks.clk_io_div4_secure + } + domain: + [ + "0" + ] + param_decl: {} + memory: {} + param_list: + [ + { + name: Stub + desc: Stub out the core of Otbn logic + type: bit + default: "0" + local: "false" + expose: "true" + name_top: OtbnStub + } + { + name: RegFile + desc: Selection of the register file implementation. See otbn_pkg.sv. + type: otbn_pkg::regfile_e + default: otbn_pkg::RegFileFF + local: "false" + expose: "true" + name_top: OtbnRegFile + } + { + name: RndCnstUrndPrngSeed + desc: Default seed of the PRNG used for URND. + type: otbn_pkg::urnd_prng_seed_t + randcount: 256 + randtype: data + name_top: RndCnstOtbnUrndPrngSeed + default: 0xe24be7e1c96737b726a4c6f04993b3e6aae70f22aaf748b57c320264e157e2c7 + randwidth: 256 + } + { + name: SecMuteUrnd + desc: + ''' + If enabled (1), URND is advanced only when data is needed. + Disabled (0) by default. + Useful for SCA measurements only. + ''' + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SecOtbnMuteUrnd + } + { + name: SecSkipUrndReseedAtStart + desc: + ''' + If enabled (1), URND reseed is skipped at the start of an operation. + Disabled (0) by default. + Useful for SCA measurements only. + ''' + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SecOtbnSkipUrndReseedAtStart + } + { + name: RndCnstOtbnKey + desc: Compile-time random reset value for IMem/DMem scrambling key. + type: otp_ctrl_pkg::otbn_key_t + randcount: 128 + randtype: data + name_top: RndCnstOtbnOtbnKey + default: 0x4a28033261ee6cec10075c55a820f842 + randwidth: 128 + } + { + name: RndCnstOtbnNonce + desc: Compile-time random reset value for IMem/DMem scrambling nonce. + type: otp_ctrl_pkg::otbn_nonce_t + randcount: 64 + randtype: data + name_top: RndCnstOtbnOtbnNonce + default: 0xd43ee1ab1b3d78f9 + randwidth: 64 + } + ] + inter_signal_list: + [ + { + name: otbn_otp_key + struct: otbn_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: otbn + top_signame: otp_ctrl_otbn_otp_key + index: -1 + } + { + name: edn_rnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: otbn + default: "" + top_signame: edn1_edn + index: 0 + } + { + name: edn_urnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: otbn + default: "" + top_signame: edn0_edn + index: 6 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: otbn + default: "" + top_signame: clkmgr_aon_idle + index: 3 + } + { + name: ram_cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: otbn + default: "" + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otbn + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_rma_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otbn + top_signame: lc_ctrl_lc_flash_rma_req + index: -1 + } + { + name: lc_rma_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otbn + end_idx: -1 + top_type: broadcast + top_signame: otbn_lc_rma_ack + index: -1 + } + { + name: keymgr_key + struct: otbn_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: otbn + default: "" + top_signame: keymgr_dpe_otbn_key + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: otbn + default: "" + end_idx: -1 + top_signame: otbn_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21130000 + } + } + generate_dif: true + } + { + name: keymgr_dpe + type: keymgr_dpe + clock_srcs: + { + clk_i: main + clk_edn_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_secure + clk_edn_i: clkmgr_aon_clocks.clk_main_secure + } + domain: + [ + "0" + ] + param_decl: {} + memory: {} + param_list: + [ + { + name: KmacEnMasking + desc: Flag indicating with kmac masking is enabled + type: bit + default: "1" + local: "false" + expose: "true" + name_top: KeymgrDpeKmacEnMasking + } + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: keymgr_pkg::lfsr_seed_t + randcount: 64 + randtype: data + name_top: RndCnstKeymgrDpeLfsrSeed + default: 0x92d223469898eb2a + randwidth: 64 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: keymgr_pkg::lfsr_perm_t + randcount: 64 + randtype: perm + name_top: RndCnstKeymgrDpeLfsrPerm + default: 0xba87c33dd8319de0a103ececead9692398efc95d9b9383505fc4b550b9b459caa265a3b0311f582412ab4c5ec71371bf + randwidth: 384 + } + { + name: RndCnstRandPerm + desc: Compile-time random permutation for entropy used in share overriding + type: keymgr_pkg::rand_perm_t + randcount: 32 + randtype: perm + name_top: RndCnstKeymgrDpeRandPerm + default: 0xbce268203cc807b4b242f394f262a5b535f3f5ab + randwidth: 160 + } + { + name: RndCnstRevisionSeed + desc: Compile-time random bits for revision seed + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeRevisionSeed + default: 0x5e456f3b26d15f5584bb9879bd2497852c23d0fa289c3348ce364ed534970e1f + randwidth: 256 + } + { + name: RndCnstSoftOutputSeed + desc: Compile-time random bits for software generation seed + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeSoftOutputSeed + default: 0xd45ec606be134fc08318bd29b22b08df647bdc30068e7513200fa828bfee3ecc + randwidth: 256 + } + { + name: RndCnstHardOutputSeed + desc: Compile-time random bits for hardware generation seed + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeHardOutputSeed + default: 0xf02417fa68d004534267f60b34a8f072e77ee4859b243f92ceb098be6e65c359 + randwidth: 256 + } + { + name: RndCnstAesSeed + desc: Compile-time random bits for generation seed when aes destination selected + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeAesSeed + default: 0x480858c39611e658c97fb8d3e9cc0e7f8fa8725200c726c8f90ef5e2b74beee2 + randwidth: 256 + } + { + name: RndCnstKmacSeed + desc: Compile-time random bits for generation seed when kmac destination selected + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeKmacSeed + default: 0x7cfa19ea576ca8a8225c8e17053e44b68dd7822a6859f2cf52a55fd181b082d0 + randwidth: 256 + } + { + name: RndCnstOtbnSeed + desc: Compile-time random bits for generation seed when otbn destination selected + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeOtbnSeed + default: 0x3c583756f11aa5b37f9544c4aa90eb97e1c0f8086f627a281c5681d6566641ee + randwidth: 256 + } + { + name: RndCnstNoneSeed + desc: Compile-time random bits for generation seed when no destination selected + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeNoneSeed + default: 0xcccc88876ad113c50ad1be4d94dce8fca54128a3860ae1d3493fbef6b9ba5dfe + randwidth: 256 + } + ] + inter_signal_list: + [ + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: edn0_edn + index: 0 + } + { + name: aes_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_type: broadcast + top_signame: keymgr_dpe_aes_key + index: -1 + } + { + name: kmac_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_type: broadcast + top_signame: keymgr_dpe_kmac_key + index: -1 + } + { + name: otbn_key + struct: otbn_key_req + package: keymgr_pkg + type: uni + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_type: broadcast + top_signame: keymgr_dpe_otbn_key + index: -1 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: kmac_app + index: 0 + } + { + name: otp_key + struct: otp_keymgr_key + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: otp_ctrl_otp_keymgr_key + index: -1 + } + { + name: otp_device_id + struct: otp_device_id + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: keymgr_dpe_otp_device_id + index: -1 + } + { + name: lc_keymgr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::On + inst_name: keymgr_dpe + top_signame: lc_ctrl_lc_keymgr_en + index: -1 + } + { + name: lc_keymgr_div + struct: lc_keymgr_div + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: lc_ctrl_lc_keymgr_div + index: -1 + } + { + name: rom_digest + struct: keymgr_data + package: rom_ctrl_pkg + type: uni + act: rcv + width: 2 + default: rom_ctrl_pkg::KEYMGR_DATA_DEFAULT + inst_name: keymgr_dpe + end_idx: -1 + top_type: one-to-N + top_signame: keymgr_dpe_rom_digest + index: -1 + } + { + name: kmac_en_masking + struct: logic + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + package: "" + top_signame: kmac_en_masking + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_signame: keymgr_dpe_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21140000 + } + } + generate_dif: true + } + { + name: csrng + type: csrng + clock_srcs: + { + clk_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_secure + } + domain: + [ + "0" + ] + param_decl: {} + memory: {} + param_list: + [ + { + name: RndCnstCsKeymgrDivNonProduction + desc: Compile-time random bits for csrng state group diversification value + type: csrng_pkg::cs_keymgr_div_t + randcount: 384 + randtype: data + name_top: RndCnstCsrngCsKeymgrDivNonProduction + default: 0x4463a4615ef46762a794a8c2597e69fb259b961914cd75bbfd36ba48e780d27cd582540c7a68ff254edfd852829feccc + randwidth: 384 + } + { + name: RndCnstCsKeymgrDivProduction + desc: Compile-time random bits for csrng state group diversification value + type: csrng_pkg::cs_keymgr_div_t + randcount: 384 + randtype: data + name_top: RndCnstCsrngCsKeymgrDivProduction + default: 0xabd4af9c9032da20bdaf59fe2ae209b8325d2c8c35fc960679b106a87e59e6aeb1b5302d33401070251696fbb4ba169a + randwidth: 384 + } + { + name: SBoxImpl + desc: Selection of the S-Box implementation. See aes_pkg.sv. + type: aes_pkg::sbox_impl_e + default: aes_pkg::SBoxImplCanright + local: "false" + expose: "true" + name_top: CsrngSBoxImpl + } + ] + inter_signal_list: + [ + { + name: csrng_cmd + struct: csrng + package: csrng_pkg + type: req_rsp + act: rsp + width: 2 + inst_name: csrng + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: csrng_csrng_cmd + index: -1 + } + { + name: entropy_src_hw_if + struct: entropy_src_hw_if + package: entropy_src_pkg + type: req_rsp + act: req + width: 1 + inst_name: csrng + default: "" + external: true + top_signame: entropy_src_hw_if + conn_type: false + index: -1 + } + { + name: cs_aes_halt + desc: + ''' + Coordinate activity between CSRNG's AES and Entropy Source's SHA3. + When CSRNG gets a request and its AES is not active, it acknowledges and until the request has dropped neither runs its AES nor drops the acknowledge. + ''' + struct: cs_aes_halt + package: entropy_src_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: csrng + index: -1 + } + { + name: otp_en_csrng_sw_app_read + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8True + inst_name: csrng + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: csrng + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: csrng + default: "" + end_idx: -1 + top_signame: csrng_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21150000 + } + } + generate_dif: true + } + { + name: edn0 + type: edn + clock_srcs: + { + clk_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_secure + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: csrng_cmd + desc: EDN supports a signal CSRNG application interface. + struct: csrng + package: csrng_pkg + type: req_rsp + act: req + width: 1 + inst_name: edn0 + default: "" + top_signame: csrng_csrng_cmd + index: 0 + } + { + name: edn + desc: + ''' + The collection of peripheral ports supported by edn. The width (4) + indicates the number of peripheral ports on a single instance. + Due to limitations in the parametrization of top-level interconnects + this value is not currently parameterizable. However, the number + of peripheral ports may change in a future revision. + ''' + struct: edn + package: edn_pkg + type: req_rsp + act: rsp + width: 8 + default: "'0" + inst_name: edn0 + end_idx: -1 + top_type: one-to-N + top_signame: edn0_edn + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: edn0 + default: "" + end_idx: -1 + top_signame: edn0_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21170000 + } + } + generate_dif: true + } + { + name: edn1 + type: edn + clock_srcs: + { + clk_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_secure + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: csrng_cmd + desc: EDN supports a signal CSRNG application interface. + struct: csrng + package: csrng_pkg + type: req_rsp + act: req + width: 1 + inst_name: edn1 + default: "" + top_signame: csrng_csrng_cmd + index: 1 + } + { + name: edn + desc: + ''' + The collection of peripheral ports supported by edn. The width (4) + indicates the number of peripheral ports on a single instance. + Due to limitations in the parametrization of top-level interconnects + this value is not currently parameterizable. However, the number + of peripheral ports may change in a future revision. + ''' + struct: edn + package: edn_pkg + type: req_rsp + act: rsp + width: 8 + default: "'0" + inst_name: edn1 + end_idx: 1 + top_type: partial-one-to-N + top_signame: edn1_edn + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: edn1 + default: "" + end_idx: -1 + top_signame: edn1_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21180000 + } + } + generate_dif: true + } + { + name: sram_ctrl_main + type: sram_ctrl + clock_srcs: + { + clk_i: main + clk_otp_i: io_div4 + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_otp_ni: + { + name: lc_io_div4 + domain: "0" + } + } + param_decl: + { + InstrExec: "1" + } + base_addrs: + { + regs: + { + hart: 0x211c0000 + } + ram: + { + hart: 0x10000000 + } + } + memory: + { + ram: + { + label: ram_main + swaccess: rw + data_intg_passthru: "true" + exec: True + byte_write: True + size: 0x10000 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + param_list: + [ + { + name: RndCnstSramKey + desc: Compile-time random reset value for SRAM scrambling key. + type: otp_ctrl_pkg::sram_key_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlMainSramKey + default: 0x6cd82fad46a0a5c04009bb934c7ef7b8 + randwidth: 128 + } + { + name: RndCnstSramNonce + desc: Compile-time random reset value for SRAM scrambling nonce. + type: otp_ctrl_pkg::sram_nonce_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlMainSramNonce + default: 0x3b6e40610b4309fcb9dc54d4276137f9 + randwidth: 128 + } + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: sram_ctrl_pkg::lfsr_seed_t + randcount: 32 + randtype: data + name_top: RndCnstSramCtrlMainLfsrSeed + default: 0x901d09a7 + randwidth: 32 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: sram_ctrl_pkg::lfsr_perm_t + randcount: 32 + randtype: perm + name_top: RndCnstSramCtrlMainLfsrPerm + default: 0x1036ed2be8b646c824a692f95f1031b9df89d3ad + randwidth: 160 + } + { + name: MemSizeRam + desc: Memory size of the RAM (in bytes). + type: int + name_top: MemSizeSramCtrlMainRam + default: 65536 + } + { + name: InstrExec + desc: Support execution from SRAM + type: bit + default: "1" + local: "false" + expose: "true" + name_top: SramCtrlMainInstrExec + } + { + name: NumPrinceRoundsHalf + desc: Number of PRINCE half rounds for the SRAM scrambling feature + type: int + default: "3" + local: "false" + expose: "true" + name_top: SramCtrlMainNumPrinceRoundsHalf + } + ] + inter_signal_list: + [ + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_main + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 0 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: sram_ctrl_main + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_main + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_main + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_main + top_signame: sram_ctrl_main_otp_en_sram_ifetch + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_main + default: "" + end_idx: -1 + top_signame: sram_ctrl_main_regs_tl + index: -1 + } + { + name: ram_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_main + default: "" + end_idx: -1 + top_signame: sram_ctrl_main_ram_tl + index: -1 + } + ] + generate_dif: true + } + { + name: sram_ctrl_mbox + type: sram_ctrl + clock_srcs: + { + clk_i: main + clk_otp_i: io_div4 + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_otp_ni: + { + name: lc_io_div4 + domain: "0" + } + } + param_decl: + { + InstrExec: "0" + } + base_addrs: + { + regs: + { + hart: 0x211d0000 + } + ram: + { + hart: 0x11000000 + } + } + memory: + { + ram: + { + label: ram_mbox + swaccess: rw + data_intg_passthru: "true" + exec: False + byte_write: True + size: 0x1000 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + param_list: + [ + { + name: RndCnstSramKey + desc: Compile-time random reset value for SRAM scrambling key. + type: otp_ctrl_pkg::sram_key_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlMboxSramKey + default: 0xe927f6d9e4abac398d42c745eef646c1 + randwidth: 128 + } + { + name: RndCnstSramNonce + desc: Compile-time random reset value for SRAM scrambling nonce. + type: otp_ctrl_pkg::sram_nonce_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlMboxSramNonce + default: 0x464dca86dafd7c7c71e6058ddfd871c5 + randwidth: 128 + } + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: sram_ctrl_pkg::lfsr_seed_t + randcount: 32 + randtype: data + name_top: RndCnstSramCtrlMboxLfsrSeed + default: 0x1cacbaf4 + randwidth: 32 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: sram_ctrl_pkg::lfsr_perm_t + randcount: 32 + randtype: perm + name_top: RndCnstSramCtrlMboxLfsrPerm + default: 0x2c32ae9387fda299e9ccf52abbc8627b4d8d8028 + randwidth: 160 + } + { + name: MemSizeRam + desc: Memory size of the RAM (in bytes). + type: int + name_top: MemSizeSramCtrlMboxRam + default: 4096 + } + { + name: InstrExec + desc: Support execution from SRAM + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SramCtrlMboxInstrExec + } + { + name: NumPrinceRoundsHalf + desc: Number of PRINCE half rounds for the SRAM scrambling feature + type: int + default: "3" + local: "false" + expose: "true" + name_top: SramCtrlMboxNumPrinceRoundsHalf + } + ] + inter_signal_list: + [ + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_mbox + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 2 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: sram_ctrl_mbox + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_mbox + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_mbox + default: "" + end_idx: -1 + top_signame: sram_ctrl_mbox_regs_tl + index: -1 + } + { + name: ram_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_mbox + default: "" + end_idx: -1 + top_signame: sram_ctrl_mbox_ram_tl + index: -1 + } + ] + generate_dif: true + } + { + name: rom_ctrl0 + type: rom_ctrl + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + rom: + { + hart: 0x00008000 + } + regs: + { + hart: 0x211e0000 + } + } + memory: + { + rom: + { + label: rom0 + swaccess: ro + data_intg_passthru: True + exec: True + byte_write: False + size: 0x8000 + } + } + param_decl: + { + SecDisableScrambling: 1'b0 + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + param_list: + [ + { + name: BootRomInitFile + desc: Contents of ROM + type: "" + default: '''""''' + local: "false" + expose: "true" + name_top: RomCtrl0BootRomInitFile + } + { + name: RndCnstScrNonce + desc: Fixed nonce used for address / data scrambling + type: bit [63:0] + randcount: 64 + randtype: data + name_top: RndCnstRomCtrl0ScrNonce + default: 0x6fd468a77efde3de + randwidth: 64 + } + { + name: RndCnstScrKey + desc: Randomised constant used as a scrambling key for ROM data + type: bit [127:0] + randcount: 128 + randtype: data + name_top: RndCnstRomCtrl0ScrKey + default: 0x5b4caf4776a247baba4c9908ed16bc54 + randwidth: 128 + } + { + name: SecDisableScrambling + desc: + ''' + Disable scrambling and checking in rom_ctrl, turning the block into a + simple ROM wrapper. This isn't intended for real chips, but is useful + for small FPGA targets where there's not space for the PRINCE + primitives. + ''' + type: bit + default: 1'b0 + local: "false" + expose: "true" + name_top: SecRomCtrl0DisableScrambling + } + { + name: MemSizeRom + desc: Memory size of the ROM (in bytes). + type: int + name_top: MemSizeRomCtrl0Rom + default: 32768 + } + ] + inter_signal_list: + [ + { + name: rom_cfg + struct: rom_cfg + package: prim_rom_pkg + type: uni + act: rcv + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: ast_rom_cfg + index: -1 + } + { + name: pwrmgr_data + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: pwrmgr_aon_rom_ctrl + index: -1 + } + { + name: keymgr_data + struct: keymgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: keymgr_dpe_rom_digest + index: 0 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: kmac_app + index: 2 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl0 + default: "" + end_idx: -1 + top_signame: rom_ctrl0_regs_tl + index: -1 + } + { + name: rom_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl0 + default: "" + end_idx: -1 + top_signame: rom_ctrl0_rom_tl + index: -1 + } + ] + generate_dif: true + } + { + name: rom_ctrl1 + type: rom_ctrl + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + rom: + { + hart: 0x00020000 + } + regs: + { + hart: 0x211e1000 + } + } + memory: + { + rom: + { + label: rom1 + swaccess: ro + data_intg_passthru: True + exec: True + byte_write: False + size: 0x10000 + } + } + param_decl: + { + SecDisableScrambling: 1'b0 + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + param_list: + [ + { + name: BootRomInitFile + desc: Contents of ROM + type: "" + default: '''""''' + local: "false" + expose: "true" + name_top: RomCtrl1BootRomInitFile + } + { + name: RndCnstScrNonce + desc: Fixed nonce used for address / data scrambling + type: bit [63:0] + randcount: 64 + randtype: data + name_top: RndCnstRomCtrl1ScrNonce + default: 0x15ec16d28c535513 + randwidth: 64 + } + { + name: RndCnstScrKey + desc: Randomised constant used as a scrambling key for ROM data + type: bit [127:0] + randcount: 128 + randtype: data + name_top: RndCnstRomCtrl1ScrKey + default: 0x12fcedcf2832a66ceacf8ed4d5b61617 + randwidth: 128 + } + { + name: SecDisableScrambling + desc: + ''' + Disable scrambling and checking in rom_ctrl, turning the block into a + simple ROM wrapper. This isn't intended for real chips, but is useful + for small FPGA targets where there's not space for the PRINCE + primitives. + ''' + type: bit + default: 1'b0 + local: "false" + expose: "true" + name_top: SecRomCtrl1DisableScrambling + } + { + name: MemSizeRom + desc: Memory size of the ROM (in bytes). + type: int + name_top: MemSizeRomCtrl1Rom + default: 65536 + } + ] + inter_signal_list: + [ + { + name: rom_cfg + struct: rom_cfg + package: prim_rom_pkg + type: uni + act: rcv + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: ast_rom_cfg + index: -1 + } + { + name: pwrmgr_data + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: pwrmgr_aon_rom_ctrl + index: -1 + } + { + name: keymgr_data + struct: keymgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: keymgr_dpe_rom_digest + index: 1 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: kmac_app + index: 3 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl1 + default: "" + end_idx: -1 + top_signame: rom_ctrl1_regs_tl + index: -1 + } + { + name: rom_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl1 + default: "" + end_idx: -1 + top_signame: rom_ctrl1_rom_tl + index: -1 + } + ] + generate_dif: true + } + { + name: dma + type: dma + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + param_decl: {} + memory: {} + param_list: + [ + { + name: EnableDataIntgGen + desc: Compute integrity bits for A channel data on all TL-UL host ports + type: bit + default: 1'b1 + local: "false" + expose: "true" + name_top: DmaEnableDataIntgGen + } + { + name: EnableRspDataIntgCheck + desc: Enable integrity checks on the response TL-UL D channel + type: bit + default: 1'b1 + local: "false" + expose: "true" + name_top: DmaEnableRspDataIntgCheck + } + { + name: TlUserRsvd + desc: Value of `rsvd` field in A channel of all TL-UL host ports + type: logic [tlul_pkg::RsvdWidth-1:0] + default: "'0" + local: "false" + expose: "true" + name_top: DmaTlUserRsvd + } + { + name: SysRacl + desc: Value of `racl_vec` field in `sys` output + type: logic [dma_pkg::SYS_RACL_WIDTH-1:0] + default: "'0" + local: "false" + expose: "true" + name_top: DmaSysRacl + } + { + name: OtAgentId + desc: OT Agent ID + type: int unsigned + default: "0" + local: "false" + expose: "true" + name_top: DmaOtAgentId + } + ] + inter_signal_list: + [ + { + name: lsio_trigger + struct: lsio_trigger + package: dma_pkg + type: uni + act: rcv + width: 1 + inst_name: dma + default: "" + end_idx: -1 + top_type: broadcast + top_signame: dma_lsio_trigger + index: -1 + } + { + name: sys + struct: sys + package: dma_pkg + type: req_rsp + act: req + width: 1 + inst_name: dma + default: "" + external: true + top_signame: dma_sys + conn_type: false + index: -1 + } + { + name: ctn_tl_h2d + desc: TL-UL host port for egress into CTN (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: dma + default: "" + external: true + top_signame: dma_ctn_tl_h2d + conn_type: false + index: -1 + } + { + name: ctn_tl_d2h + desc: TL-UL host port for egress into CTN (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: dma + default: "" + external: true + top_signame: dma_ctn_tl_d2h + conn_type: false + index: -1 + } + { + name: host_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: dma + default: "" + top_signame: main_tl_dma__host + index: -1 + } + { + name: tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: dma + default: "" + end_idx: -1 + top_signame: dma_tl_d + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x22010000 + } + } + generate_dif: true + } + { + name: mbx0 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000000 + } + soc: + { + soc_mbx: 0x01465000 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx0 + default: "" + top_signame: main_tl_mbx0__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx0 + default: "" + end_idx: -1 + top_signame: mbx0_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx0 + default: "" + end_idx: -1 + top_signame: mbx0_soc_tl_d + index: -1 + } + ] + generate_dif: true + } + { + name: mbx1 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000100 + } + soc: + { + soc_mbx: 0x01465100 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx1 + default: "" + top_signame: main_tl_mbx1__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx1 + default: "" + end_idx: -1 + top_signame: mbx1_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx1 + default: "" + end_idx: -1 + top_signame: mbx1_soc_tl_d + index: -1 + } + ] + generate_dif: true + } + { + name: mbx2 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000200 + } + soc: + { + soc_mbx: 0x01465200 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx2 + default: "" + top_signame: main_tl_mbx2__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx2 + default: "" + end_idx: -1 + top_signame: mbx2_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx2 + default: "" + end_idx: -1 + top_signame: mbx2_soc_tl_d + index: -1 + } + ] + generate_dif: true + } + { + name: mbx3 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000300 + } + soc: + { + soc_mbx: 0x01465300 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx3 + default: "" + top_signame: main_tl_mbx3__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx3 + default: "" + end_idx: -1 + top_signame: mbx3_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx3 + default: "" + end_idx: -1 + top_signame: mbx3_soc_tl_d + index: -1 + } + ] + generate_dif: true + } + { + name: mbx4 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000400 + } + soc: + { + soc_mbx: 0x01465400 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx4 + default: "" + top_signame: main_tl_mbx4__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx4 + default: "" + end_idx: -1 + top_signame: mbx4_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx4 + default: "" + end_idx: -1 + top_signame: mbx4_soc_tl_d + index: -1 + } + ] + generate_dif: true + } + { + name: mbx5 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000500 + } + soc: + { + soc_mbx: 0x01465500 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx5 + default: "" + top_signame: main_tl_mbx5__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx5 + default: "" + end_idx: -1 + top_signame: mbx5_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx5 + default: "" + end_idx: -1 + top_signame: mbx5_soc_tl_d + index: -1 + } + ] + generate_dif: true + } + { + name: mbx6 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000600 + } + soc: + { + soc_mbx: 0x01465600 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx6 + default: "" + top_signame: main_tl_mbx6__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx6 + default: "" + end_idx: -1 + top_signame: mbx6_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx6 + default: "" + end_idx: -1 + top_signame: mbx6_soc_tl_d + index: -1 + } + ] + generate_dif: true + } + { + name: mbx_jtag + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000800 + } + soc: + { + soc_dbg: 0x1000 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx_jtag + default: "" + top_signame: main_tl_mbx_jtag__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_jtag + default: "" + end_idx: -1 + top_signame: mbx_jtag_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_jtag + default: "" + end_idx: -1 + top_signame: mbx_jtag_soc_tl_d + index: -1 + } + ] + generate_dif: true + } + { + name: mbx_pcie0 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22040000 + } + soc: + { + soc_mbx: 0x01460100 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx_pcie0 + default: "" + top_signame: main_tl_mbx_pcie0__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie0 + default: "" + end_idx: -1 + top_signame: mbx_pcie0_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie0 + default: "" + end_idx: -1 + top_signame: mbx_pcie0_soc_tl_d + index: -1 + } + ] + generate_dif: true + } + { + name: mbx_pcie1 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22040100 + } + soc: + { + soc_mbx: 0x01460200 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx_pcie1 + default: "" + top_signame: main_tl_mbx_pcie1__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie1 + default: "" + end_idx: -1 + top_signame: mbx_pcie1_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie1 + default: "" + end_idx: -1 + top_signame: mbx_pcie1_soc_tl_d + index: -1 + } + ] + generate_dif: true + } + { + name: rv_core_ibex + type: rv_core_ibex + param_decl: + { + PMPEnable: "1" + PMPGranularity: "0" + PMPNumRegions: "16" + MHPMCounterNum: "10" + MHPMCounterWidth: "32" + RV32E: "0" + RV32M: ibex_pkg::RV32MSingleCycle + RV32B: ibex_pkg::RV32BOTEarlGrey + RegFile: ibex_pkg::RegFileFF + BranchTargetALU: "1" + WritebackStage: "1" + ICache: "1" + ICacheECC: "1" + ICacheScramble: "1" + BranchPredictor: "0" + DbgTriggerEn: "1" + DbgHwBreakNum: "4" + SecureIbex: "1" + DmHaltAddr: tl_main_pkg::ADDR_SPACE_RV_DM__MEM + dm::HaltAddress[31:0] + DmExceptionAddr: tl_main_pkg::ADDR_SPACE_RV_DM__MEM + dm::ExceptionAddress[31:0] + PipeLine: "0" + } + clock_srcs: + { + clk_i: main + clk_edn_i: main + clk_esc_i: + { + clock: io_div4 + group: secure + } + clk_otp_i: + { + clock: io_div4 + group: secure + } + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + rst_esc_ni: + { + name: lc_io_div4 + domain: "0" + } + rst_otp_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + clk_edn_i: clkmgr_aon_clocks.clk_main_infra + clk_esc_i: clkmgr_aon_clocks.clk_io_div4_secure + clk_otp_i: clkmgr_aon_clocks.clk_io_div4_secure + } + domain: + [ + "0" + ] + memory: {} + param_list: + [ + { + name: RndCnstLfsrSeed + desc: Default seed of the PRNG used for random instructions. + type: ibex_pkg::lfsr_seed_t + randcount: 32 + randtype: data + name_top: RndCnstRvCoreIbexLfsrSeed + default: 0x7dd43b56 + randwidth: 32 + } + { + name: RndCnstLfsrPerm + desc: Permutation applied to the LFSR of the PRNG used for random instructions. + type: ibex_pkg::lfsr_perm_t + randcount: 32 + randtype: perm + name_top: RndCnstRvCoreIbexLfsrPerm + default: 0x1440b451b8d7081796663dfdbee6d2832aa1a5df + randwidth: 160 + } + { + name: RndCnstIbexKeyDefault + desc: Default icache scrambling key + type: logic [ibex_pkg::SCRAMBLE_KEY_W-1:0] + randcount: 128 + randtype: data + name_top: RndCnstRvCoreIbexIbexKeyDefault + default: 0x74f35c79f397c4e4c7e22b7581848a90 + randwidth: 128 + } + { + name: RndCnstIbexNonceDefault + desc: Default icache scrambling nonce + type: logic [ibex_pkg::SCRAMBLE_NONCE_W-1:0] + randcount: 64 + randtype: data + name_top: RndCnstRvCoreIbexIbexNonceDefault + default: 0xa1254b2276bec9fc + randwidth: 64 + } + { + name: PMPEnable + desc: Enable PMP + type: bit + default: "1" + local: "false" + expose: "true" + name_top: RvCoreIbexPMPEnable + } + { + name: PMPGranularity + desc: PMP Granularity + type: int unsigned + default: "0" + local: "false" + expose: "true" + name_top: RvCoreIbexPMPGranularity + } + { + name: PMPNumRegions + desc: PMP number of regions + type: int unsigned + default: "16" + local: "false" + expose: "true" + name_top: RvCoreIbexPMPNumRegions + } + { + name: MHPMCounterNum + desc: "Number of the MHPM counter " + type: int unsigned + default: "10" + local: "false" + expose: "true" + name_top: RvCoreIbexMHPMCounterNum + } + { + name: MHPMCounterWidth + desc: "Width of the MHPM Counter " + type: int unsigned + default: "32" + local: "false" + expose: "true" + name_top: RvCoreIbexMHPMCounterWidth + } + { + name: PMPRstCfg + desc: Reset value of PMP config CSRs + type: ibex_pkg::pmp_cfg_t + unpacked_dimensions: "[16]" + default: ibex_pkg::PmpCfgRst + local: "false" + expose: "true" + name_top: RvCoreIbexPMPRstCfg + } + { + name: PMPRstAddr + desc: Reset value of PMP address CSRs + type: logic [33:0] + unpacked_dimensions: "[16]" + default: ibex_pkg::PmpAddrRst + local: "false" + expose: "true" + name_top: RvCoreIbexPMPRstAddr + } + { + name: PMPRstMsecCfg + desc: Reset value of MSECCFG CSR + type: ibex_pkg::pmp_mseccfg_t + default: ibex_pkg::PmpMseccfgRst + local: "false" + expose: "true" + name_top: RvCoreIbexPMPRstMsecCfg + } + { + name: RV32E + desc: RV32E + type: bit + default: "0" + local: "false" + expose: "true" + name_top: RvCoreIbexRV32E + } + { + name: RV32M + desc: RV32M + type: ibex_pkg::rv32m_e + default: ibex_pkg::RV32MSingleCycle + local: "false" + expose: "true" + name_top: RvCoreIbexRV32M + } + { + name: RV32B + desc: RV32B + type: ibex_pkg::rv32b_e + default: ibex_pkg::RV32BOTEarlGrey + local: "false" + expose: "true" + name_top: RvCoreIbexRV32B + } + { + name: RegFile + desc: Reg file + type: ibex_pkg::regfile_e + default: ibex_pkg::RegFileFF + local: "false" + expose: "true" + name_top: RvCoreIbexRegFile + } + { + name: BranchTargetALU + desc: Branch target ALU + type: bit + default: "1" + local: "false" + expose: "true" + name_top: RvCoreIbexBranchTargetALU + } + { + name: WritebackStage + desc: Write back stage + type: bit + default: "1" + local: "false" + expose: "true" + name_top: RvCoreIbexWritebackStage + } + { + name: ICache + desc: Instruction cache + type: bit + default: "1" + local: "false" + expose: "true" + name_top: RvCoreIbexICache + } + { + name: ICacheECC + desc: Instruction cache ECC + type: bit + default: "1" + local: "false" + expose: "true" + name_top: RvCoreIbexICacheECC + } + { + name: ICacheScramble + desc: Scramble instruction cach + type: bit + default: "1" + local: "false" + expose: "true" + name_top: RvCoreIbexICacheScramble + } + { + name: BranchPredictor + desc: Branch predictor + type: bit + default: "0" + local: "false" + expose: "true" + name_top: RvCoreIbexBranchPredictor + } + { + name: DbgTriggerEn + desc: Enable degug trigger + type: bit + default: "1" + local: "false" + expose: "true" + name_top: RvCoreIbexDbgTriggerEn + } + { + name: DbgHwBreakNum + desc: Number of debug hardware break + type: int + default: "4" + local: "false" + expose: "true" + name_top: RvCoreIbexDbgHwBreakNum + } + { + name: SecureIbex + desc: "Width of the MHPM Counter " + type: bit + default: "1" + local: "false" + expose: "true" + name_top: RvCoreIbexSecureIbex + } + { + name: DmHaltAddr + desc: Halt address + type: int unsigned + default: tl_main_pkg::ADDR_SPACE_RV_DM__MEM + dm::HaltAddress[31:0] + local: "false" + expose: "true" + name_top: RvCoreIbexDmHaltAddr + } + { + name: DmExceptionAddr + desc: Exception address + type: int unsigned + default: tl_main_pkg::ADDR_SPACE_RV_DM__MEM + dm::ExceptionAddress[31:0] + local: "false" + expose: "true" + name_top: RvCoreIbexDmExceptionAddr + } + { + name: PipeLine + desc: Pipe line + type: bit + default: "0" + local: "false" + expose: "true" + name_top: RvCoreIbexPipeLine + } + ] + inter_signal_list: + [ + { + name: rst_cpu_n + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_core_ibex + index: -1 + } + { + name: ram_cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: hart_id + struct: logic + type: uni + act: rcv + width: 32 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: rv_core_ibex_hart_id + index: -1 + } + { + name: boot_addr + struct: logic + type: uni + act: rcv + width: 32 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: rv_core_ibex_boot_addr + index: -1 + } + { + name: irq_software + struct: logic + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: rv_plic_msip + index: -1 + } + { + name: irq_timer + struct: logic + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: rv_core_ibex_irq_timer + index: -1 + } + { + name: irq_external + struct: logic + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: rv_plic_irq + index: -1 + } + { + name: esc_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: alert_handler_esc_tx + index: 0 + } + { + name: esc_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: alert_handler_esc_rx + index: 0 + } + { + name: debug_req + struct: logic + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: rv_dm_debug_req + index: -1 + } + { + name: crash_dump + struct: cpu_crash_dump + package: rv_core_ibex_pkg + type: uni + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_core_ibex_crash_dump + index: -1 + } + { + name: lc_cpu_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: lc_ctrl_lc_cpu_en + index: -1 + } + { + name: pwrmgr_cpu_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: pwrmgr_aon_fetch_en + index: -1 + } + { + name: pwrmgr + struct: pwr_cpu + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_core_ibex_pwrmgr + index: -1 + } + { + name: nmi_wdog + struct: logic + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: aon_timer_aon_nmi_wdog_timer_bark + index: -1 + } + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: edn0_edn + index: 7 + } + { + name: icache_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 3 + } + { + name: fpga_info + struct: logic + type: uni + act: rcv + width: 32 + inst_name: rv_core_ibex + default: "" + package: "" + external: true + top_signame: fpga_info + conn_type: false + index: -1 + } + { + name: corei_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: main_tl_rv_core_ibex__corei + index: -1 + } + { + name: cored_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: main_tl_rv_core_ibex__cored + index: -1 + } + { + name: cfg_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_core_ibex + default: "" + end_idx: -1 + top_signame: rv_core_ibex_cfg_tl_d + index: -1 + } + ] + base_addrs: + { + cfg: + { + hart: 0x211f0000 + } + } + generate_dif: true + } + ] + memory: [] + port: + [ + { + name: ast + inter_signal_list: + [ + { + struct: edn + type: req_rsp + name: edn + act: rsp + package: edn_pkg + inst_name: ast + width: 1 + default: "" + top_signame: edn0_edn + index: 2 + external: true + conn_type: true + } + { + struct: lc_tx + type: uni + name: lc_dft_en + act: req + package: lc_ctrl_pkg + inst_name: ast + width: 1 + default: "" + top_signame: lc_ctrl_lc_dft_en + index: -1 + external: true + conn_type: true + } + { + struct: lc_tx + type: uni + name: lc_hw_debug_en + act: req + package: lc_ctrl_pkg + inst_name: ast + width: 1 + default: "" + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + external: true + conn_type: true + } + { + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + name: ram_1p_cfg + act: rcv + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_ram_1p_cfg + index: -1 + external: true + conn_type: true + } + { + struct: ram_2p_cfg + package: prim_ram_2p_pkg + type: uni + name: spi_ram_2p_cfg + act: rcv + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_spi_ram_2p_cfg + index: -1 + external: true + conn_type: true + } + { + struct: rom_cfg + package: prim_rom_pkg + type: uni + name: rom_cfg + act: rcv + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_rom_cfg + index: -1 + external: true + conn_type: true + } + { + struct: ast_obs_ctrl + type: uni + name: obs_ctrl + act: rcv + package: ast_pkg + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_obs_ctrl + index: -1 + external: true + conn_type: true + } + ] + } + ] + inter_module: + { + connect: + { + ast.obs_ctrl: + [ + otp_ctrl.obs_ctrl + ] + ast.ram_1p_cfg: + [ + otbn.ram_cfg + sram_ctrl_main.cfg + sram_ctrl_ret_aon.cfg + sram_ctrl_mbox.cfg + rv_core_ibex.ram_cfg + ] + ast.spi_ram_2p_cfg: + [ + spi_device.ram_cfg + ] + ast.rom_cfg: + [ + rom_ctrl0.rom_cfg + rom_ctrl1.rom_cfg + ] + alert_handler.crashdump: + [ + rstmgr_aon.alert_dump + ] + alert_handler.esc_rx: + [ + rv_core_ibex.esc_rx + lc_ctrl.esc_scrap_state0_rx + lc_ctrl.esc_scrap_state1_rx + pwrmgr_aon.esc_rst_rx + ] + alert_handler.esc_tx: + [ + rv_core_ibex.esc_tx + lc_ctrl.esc_scrap_state0_tx + lc_ctrl.esc_scrap_state1_tx + pwrmgr_aon.esc_rst_tx + ] + aon_timer_aon.nmi_wdog_timer_bark: + [ + rv_core_ibex.nmi_wdog + ] + csrng.csrng_cmd: + [ + edn0.csrng_cmd + edn1.csrng_cmd + ] + otp_ctrl.sram_otp_key: + [ + sram_ctrl_main.sram_otp_key + sram_ctrl_ret_aon.sram_otp_key + sram_ctrl_mbox.sram_otp_key + rv_core_ibex.icache_otp_key + ] + pwrmgr_aon.pwr_rst: + [ + rstmgr_aon.pwr + ] + pwrmgr_aon.pwr_clk: + [ + clkmgr_aon.pwr + ] + pwrmgr_aon.pwr_otp: + [ + otp_ctrl.pwr_otp + ] + pwrmgr_aon.pwr_lc: + [ + lc_ctrl.pwr_lc + ] + pwrmgr_aon.strap: + [ + pinmux_aon.strap_en + gpio.strap_en + rv_dm.strap_en + ] + pwrmgr_aon.low_power: + [ + pinmux_aon.sleep_en + aon_timer_aon.sleep_mode + ] + pwrmgr_aon.fetch_en: + [ + rv_core_ibex.pwrmgr_cpu_en + ] + pwrmgr_aon.rom_ctrl: + [ + rom_ctrl0.pwrmgr_data + rom_ctrl1.pwrmgr_data + ] + keymgr_dpe.rom_digest: + [ + rom_ctrl0.keymgr_data + rom_ctrl1.keymgr_data + ] + dma.lsio_trigger: + [ + soc_proxy.dma_lsio_trigger + ] + i2c0.lsio_trigger: + [ + soc_proxy.i2c_lsio_trigger + ] + spi_host0.lsio_trigger: + [ + soc_proxy.spi_host_lsio_trigger + ] + uart0.lsio_trigger: + [ + soc_proxy.uart_lsio_trigger + ] + lc_ctrl.lc_flash_rma_req: + [ + otbn.lc_rma_req + ] + otbn.lc_rma_ack: + [ + lc_ctrl.lc_flash_rma_ack + ] + edn0.edn: + [ + keymgr_dpe.edn + otp_ctrl.edn + ast.edn + kmac.entropy + alert_handler.edn + aes.edn + otbn.edn_urnd + rv_core_ibex.edn + ] + edn1.edn: + [ + otbn.edn_rnd + ] + otp_ctrl.otbn_otp_key: + [ + otbn.otbn_otp_key + ] + otp_ctrl.otp_keymgr_key: + [ + keymgr_dpe.otp_key + ] + keymgr_dpe.aes_key: + [ + aes.keymgr_key + ] + keymgr_dpe.kmac_key: + [ + kmac.keymgr_key + ] + keymgr_dpe.otbn_key: + [ + otbn.keymgr_key + ] + kmac.app: + [ + keymgr_dpe.kmac_data + lc_ctrl.kmac_data + rom_ctrl0.kmac_data + rom_ctrl1.kmac_data + ] + kmac.en_masking: + [ + keymgr_dpe.kmac_en_masking + ] + clkmgr_aon.idle: + [ + aes.idle + hmac.idle + kmac.idle + otbn.idle + ] + otp_ctrl.otp_lc_data: + [ + lc_ctrl.otp_lc_data + ] + lc_ctrl.lc_otp_program: + [ + otp_ctrl.lc_otp_program + ] + lc_ctrl.lc_otp_vendor_test: + [ + otp_ctrl.lc_otp_vendor_test + ] + lc_ctrl.lc_keymgr_div: + [ + keymgr_dpe.lc_keymgr_div + ] + lc_ctrl.strap_en_override: + [ + pinmux_aon.strap_en_override + rv_dm.strap_en_override + ] + lc_ctrl.lc_dft_en: + [ + otp_ctrl.lc_dft_en + pinmux_aon.lc_dft_en + ast.lc_dft_en + pwrmgr_aon.lc_dft_en + ] + lc_ctrl.lc_hw_debug_en: + [ + sram_ctrl_main.lc_hw_debug_en + pinmux_aon.lc_hw_debug_en + ast.lc_hw_debug_en + csrng.lc_hw_debug_en + rv_dm.lc_hw_debug_en + clkmgr_aon.lc_hw_debug_en + pwrmgr_aon.lc_hw_debug_en + ] + lc_ctrl.lc_cpu_en: + [ + rv_core_ibex.lc_cpu_en + ] + lc_ctrl.lc_keymgr_en: + [ + keymgr_dpe.lc_keymgr_en + ] + lc_ctrl.lc_escalate_en: + [ + aes.lc_escalate_en + kmac.lc_escalate_en + otbn.lc_escalate_en + otp_ctrl.lc_escalate_en + sram_ctrl_main.lc_escalate_en + sram_ctrl_ret_aon.lc_escalate_en + sram_ctrl_mbox.lc_escalate_en + aon_timer_aon.lc_escalate_en + pinmux_aon.lc_escalate_en + rv_dm.lc_escalate_en + ] + lc_ctrl.lc_check_byp_en: + [ + otp_ctrl.lc_check_byp_en + pinmux_aon.lc_check_byp_en + rv_dm.lc_check_byp_en + ] + lc_ctrl.lc_clk_byp_req: + [ + clkmgr_aon.lc_clk_byp_req + ] + lc_ctrl.lc_clk_byp_ack: + [ + clkmgr_aon.lc_clk_byp_ack + ] + lc_ctrl.lc_creator_seed_sw_rw_en: + [ + otp_ctrl.lc_creator_seed_sw_rw_en + ] + lc_ctrl.lc_owner_seed_sw_rw_en: + [ + otp_ctrl.lc_owner_seed_sw_rw_en + ] + lc_ctrl.lc_seed_hw_rd_en: + [ + otp_ctrl.lc_seed_hw_rd_en + ] + rv_plic.msip: + [ + rv_core_ibex.irq_software + ] + rv_plic.irq: + [ + rv_core_ibex.irq_external + ] + rv_dm.debug_req: + [ + rv_core_ibex.debug_req + ] + rv_core_ibex.crash_dump: + [ + rstmgr_aon.cpu_dump + ] + rv_core_ibex.pwrmgr: + [ + pwrmgr_aon.pwr_cpu + ] + spi_device.passthrough: + [ + spi_host0.passthrough + ] + rv_dm.ndmreset_req: + [ + pwrmgr_aon.ndmreset_req + ] + rstmgr_aon.sw_rst_req: + [ + pwrmgr_aon.sw_rst_req + ] + pwrmgr_aon.wakeups: + [ + pinmux_aon.pin_wkup_req + pinmux_aon.usb_wkup_req + aon_timer_aon.wkup_req + sensor_ctrl.wkup_req + soc_proxy.wkup_internal_req + soc_proxy.wkup_external_req + ] + pwrmgr_aon.rstreqs: + [ + aon_timer_aon.aon_timer_rst_req + soc_proxy.rst_req_external + ] + main.tl_rv_core_ibex__corei: + [ + rv_core_ibex.corei_tl_h + ] + main.tl_rv_core_ibex__cored: + [ + rv_core_ibex.cored_tl_h + ] + main.tl_rv_dm__sba: + [ + rv_dm.sba_tl_h + ] + rv_dm.regs_tl_d: + [ + main.tl_rv_dm__regs + ] + rv_dm.mem_tl_d: + [ + main.tl_rv_dm__mem + ] + rom_ctrl0.rom_tl: + [ + main.tl_rom_ctrl0__rom + ] + rom_ctrl0.regs_tl: + [ + main.tl_rom_ctrl0__regs + ] + rom_ctrl1.rom_tl: + [ + main.tl_rom_ctrl1__rom + ] + rom_ctrl1.regs_tl: + [ + main.tl_rom_ctrl1__regs + ] + main.tl_peri: + [ + peri.tl_main + ] + soc_proxy.core_tl: + [ + main.tl_soc_proxy__core + ] + soc_proxy.ctn_tl: + [ + main.tl_soc_proxy__ctn + ] + hmac.tl: + [ + main.tl_hmac + ] + kmac.tl: + [ + main.tl_kmac + ] + aes.tl: + [ + main.tl_aes + ] + csrng.tl: + [ + main.tl_csrng + ] + edn0.tl: + [ + main.tl_edn0 + ] + edn1.tl: + [ + main.tl_edn1 + ] + rv_plic.tl: + [ + main.tl_rv_plic + ] + otbn.tl: + [ + main.tl_otbn + ] + keymgr_dpe.tl: + [ + main.tl_keymgr_dpe + ] + rv_core_ibex.cfg_tl_d: + [ + main.tl_rv_core_ibex__cfg + ] + sram_ctrl_main.regs_tl: + [ + main.tl_sram_ctrl_main__regs + ] + sram_ctrl_main.ram_tl: + [ + main.tl_sram_ctrl_main__ram + ] + sram_ctrl_mbox.regs_tl: + [ + main.tl_sram_ctrl_mbox__regs + ] + sram_ctrl_mbox.ram_tl: + [ + main.tl_sram_ctrl_mbox__ram + ] + dma.tl_d: + [ + main.tl_dma + ] + main.tl_dma__host: + [ + dma.host_tl_h + ] + mbx0.core_tl_d: + [ + main.tl_mbx0__core + ] + main.tl_mbx0__sram: + [ + mbx0.sram_tl_h + ] + mbx1.core_tl_d: + [ + main.tl_mbx1__core + ] + main.tl_mbx1__sram: + [ + mbx1.sram_tl_h + ] + mbx2.core_tl_d: + [ + main.tl_mbx2__core + ] + main.tl_mbx2__sram: + [ + mbx2.sram_tl_h + ] + mbx3.core_tl_d: + [ + main.tl_mbx3__core + ] + main.tl_mbx3__sram: + [ + mbx3.sram_tl_h + ] + mbx4.core_tl_d: + [ + main.tl_mbx4__core + ] + main.tl_mbx4__sram: + [ + mbx4.sram_tl_h + ] + mbx5.core_tl_d: + [ + main.tl_mbx5__core + ] + main.tl_mbx5__sram: + [ + mbx5.sram_tl_h + ] + mbx6.core_tl_d: + [ + main.tl_mbx6__core + ] + main.tl_mbx6__sram: + [ + mbx6.sram_tl_h + ] + mbx_jtag.core_tl_d: + [ + main.tl_mbx_jtag__core + ] + main.tl_mbx_jtag__sram: + [ + mbx_jtag.sram_tl_h + ] + mbx_pcie0.core_tl_d: + [ + main.tl_mbx_pcie0__core + ] + main.tl_mbx_pcie0__sram: + [ + mbx_pcie0.sram_tl_h + ] + mbx_pcie1.core_tl_d: + [ + main.tl_mbx_pcie1__core + ] + main.tl_mbx_pcie1__sram: + [ + mbx_pcie1.sram_tl_h + ] + uart0.tl: + [ + peri.tl_uart0 + ] + i2c0.tl: + [ + peri.tl_i2c0 + ] + gpio.tl: + [ + peri.tl_gpio + ] + spi_host0.tl: + [ + peri.tl_spi_host0 + ] + spi_device.tl: + [ + peri.tl_spi_device + ] + rv_timer.tl: + [ + peri.tl_rv_timer + ] + pwrmgr_aon.tl: + [ + peri.tl_pwrmgr_aon + ] + rstmgr_aon.tl: + [ + peri.tl_rstmgr_aon + ] + clkmgr_aon.tl: + [ + peri.tl_clkmgr_aon + ] + pinmux_aon.tl: + [ + peri.tl_pinmux_aon + ] + otp_ctrl.core_tl: + [ + peri.tl_otp_ctrl__core + ] + otp_ctrl.prim_tl: + [ + peri.tl_otp_ctrl__prim + ] + lc_ctrl.regs_tl: + [ + peri.tl_lc_ctrl__regs + ] + sensor_ctrl.tl: + [ + peri.tl_sensor_ctrl + ] + alert_handler.tl: + [ + peri.tl_alert_handler + ] + sram_ctrl_ret_aon.regs_tl: + [ + peri.tl_sram_ctrl_ret_aon__regs + ] + sram_ctrl_ret_aon.ram_tl: + [ + peri.tl_sram_ctrl_ret_aon__ram + ] + aon_timer_aon.tl: + [ + peri.tl_aon_timer_aon + ] + mbx0.soc_tl_d: + [ + mbx.tl_mbx0__soc + ] + mbx1.soc_tl_d: + [ + mbx.tl_mbx1__soc + ] + mbx2.soc_tl_d: + [ + mbx.tl_mbx2__soc + ] + mbx3.soc_tl_d: + [ + mbx.tl_mbx3__soc + ] + mbx4.soc_tl_d: + [ + mbx.tl_mbx4__soc + ] + mbx5.soc_tl_d: + [ + mbx.tl_mbx5__soc + ] + mbx6.soc_tl_d: + [ + mbx.tl_mbx6__soc + ] + mbx_pcie0.soc_tl_d: + [ + mbx.tl_mbx_pcie0__soc + ] + mbx_pcie1.soc_tl_d: + [ + mbx.tl_mbx_pcie1__soc + ] + rv_dm.dbg_tl_d: + [ + dbg.tl_rv_dm__dbg + ] + mbx_jtag.soc_tl_d: + [ + dbg.tl_mbx_jtag__soc + ] + lc_ctrl.dmi_tl: + [ + dbg.tl_lc_ctrl__dmi + ] + } + top: + [ + clkmgr_aon.clocks + clkmgr_aon.cg_en + rstmgr_aon.resets + rstmgr_aon.rst_en + rv_core_ibex.irq_timer + rv_core_ibex.hart_id + rv_core_ibex.boot_addr + otp_ctrl.otp_broadcast + lc_ctrl.otp_device_id + lc_ctrl.otp_manuf_state + keymgr_dpe.otp_device_id + sram_ctrl_main.otp_en_sram_ifetch + ] + external: + { + ast.edn: "" + ast.lc_dft_en: "" + ast.lc_hw_debug_en: "" + ast.obs_ctrl: obs_ctrl + ast.ram_1p_cfg: ram_1p_cfg + ast.spi_ram_2p_cfg: spi_ram_2p_cfg + ast.rom_cfg: rom_cfg + clkmgr_aon.jitter_en: clk_main_jitter_en + clkmgr_aon.io_clk_byp_req: io_clk_byp_req + clkmgr_aon.io_clk_byp_ack: io_clk_byp_ack + clkmgr_aon.all_clk_byp_req: all_clk_byp_req + clkmgr_aon.all_clk_byp_ack: all_clk_byp_ack + clkmgr_aon.hi_speed_sel: hi_speed_sel + clkmgr_aon.div_step_down_req: div_step_down_req + clkmgr_aon.calib_rdy: calib_rdy + csrng.entropy_src_hw_if: entropy_src_hw_if + dma.sys: dma_sys + dma.ctn_tl_h2d: dma_ctn_tl_h2d + dma.ctn_tl_d2h: dma_ctn_tl_d2h + mbx.tl_mbx: mbx_tl + mbx0.doe_intr: mbx0_doe_intr + mbx0.doe_intr_en: mbx0_doe_intr_en + mbx0.doe_intr_support: mbx0_doe_intr_support + mbx0.doe_async_msg_support: mbx0_doe_async_msg_support + mbx1.doe_intr: mbx1_doe_intr + mbx1.doe_intr_en: mbx1_doe_intr_en + mbx1.doe_intr_support: mbx1_doe_intr_support + mbx1.doe_async_msg_support: mbx1_doe_async_msg_support + mbx2.doe_intr: mbx2_doe_intr + mbx2.doe_intr_en: mbx2_doe_intr_en + mbx2.doe_intr_support: mbx2_doe_intr_support + mbx2.doe_async_msg_support: mbx2_doe_async_msg_support + mbx3.doe_intr: mbx3_doe_intr + mbx3.doe_intr_en: mbx3_doe_intr_en + mbx3.doe_intr_support: mbx3_doe_intr_support + mbx3.doe_async_msg_support: mbx3_doe_async_msg_support + mbx4.doe_intr: mbx4_doe_intr + mbx4.doe_intr_en: mbx4_doe_intr_en + mbx4.doe_intr_support: mbx4_doe_intr_support + mbx4.doe_async_msg_support: mbx4_doe_async_msg_support + mbx5.doe_intr: mbx5_doe_intr + mbx5.doe_intr_en: mbx5_doe_intr_en + mbx5.doe_intr_support: mbx5_doe_intr_support + mbx5.doe_async_msg_support: mbx5_doe_async_msg_support + mbx6.doe_intr: mbx6_doe_intr + mbx6.doe_intr_en: mbx6_doe_intr_en + mbx6.doe_intr_support: mbx6_doe_intr_support + mbx6.doe_async_msg_support: mbx6_doe_async_msg_support + mbx_jtag.doe_intr: mbx_jtag_doe_intr + mbx_jtag.doe_intr_en: mbx_jtag_doe_intr_en + mbx_jtag.doe_intr_support: mbx_jtag_doe_intr_support + mbx_jtag.doe_async_msg_support: mbx_jtag_doe_async_msg_support + mbx_pcie0.doe_intr: mbx_pcie0_doe_intr + mbx_pcie0.doe_intr_en: mbx_pcie0_doe_intr_en + mbx_pcie0.doe_intr_support: mbx_pcie0_doe_intr_support + mbx_pcie0.doe_async_msg_support: mbx_pcie0_doe_async_msg_support + mbx_pcie1.doe_intr: mbx_pcie1_doe_intr + mbx_pcie1.doe_intr_en: mbx_pcie1_doe_intr_en + mbx_pcie1.doe_intr_support: mbx_pcie1_doe_intr_support + mbx_pcie1.doe_async_msg_support: mbx_pcie1_doe_async_msg_support + dbg.tl_dbg: dbg_tl + rv_dm.next_dm_addr: rv_dm_next_dm_addr + peri.tl_ast: ast_tl + pinmux_aon.dft_strap_test: dft_strap_test + pinmux_aon.dft_hold_tap_sel: dft_hold_tap_sel + pwrmgr_aon.pwr_ast: pwrmgr_ast + otp_ctrl.otp_ast_pwr_seq: "" + otp_ctrl.otp_ast_pwr_seq_h: "" + otp_ctrl.otp_ext_voltage_h: otp_ext_voltage_h + otp_ctrl.otp_obs: otp_obs + rstmgr_aon.por_n: por_n + rv_core_ibex.fpga_info: fpga_info + sensor_ctrl.ast_alert: sensor_ctrl_ast_alert + sensor_ctrl.ast_status: sensor_ctrl_ast_status + sensor_ctrl.ast_init_done: ast_init_done + soc_proxy.ctn_tl_h2d: ctn_tl_h2d + soc_proxy.ctn_tl_d2h: ctn_tl_d2h + soc_proxy.soc_fatal_alert: soc_fatal_alert + soc_proxy.soc_recov_alert: soc_recov_alert + soc_proxy.soc_wkup_async: soc_wkup_async + soc_proxy.soc_rst_req_async: soc_rst_req_async + soc_proxy.soc_intr_async: soc_intr_async + soc_proxy.soc_lsio_trigger: soc_lsio_trigger + soc_proxy.soc_gpi_async: soc_gpi_async + soc_proxy.soc_gpo_async: soc_gpo_async + spi_device.sck_monitor: sck_monitor + } + } + xbar: + [ + { + name: main + clock_srcs: + { + clk_main_i: main + clk_fixed_i: io_div4 + clk_usb_i: usb + } + clock_group: infra + reset: rst_main_ni + reset_connections: + { + rst_main_ni: + { + name: lc + domain: "0" + } + rst_fixed_ni: + { + name: lc_io_div4 + domain: "0" + } + rst_usb_ni: + { + name: lc_usb + domain: "0" + } + } + min_spacing: 0x100 + clock_connections: + { + clk_main_i: clkmgr_aon_clocks.clk_main_infra + clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra + clk_usb_i: clkmgr_aon_clocks.clk_usb_infra + } + domain: + [ + "0" + ] + connections: + { + rv_core_ibex.corei: + [ + rom_ctrl0.rom + rom_ctrl1.rom + rv_dm.mem + sram_ctrl_main.ram + soc_proxy.ctn + ] + rv_core_ibex.cored: + [ + rom_ctrl0.rom + rom_ctrl0.regs + rom_ctrl1.rom + rom_ctrl1.regs + rv_dm.mem + rv_dm.regs + sram_ctrl_main.ram + peri + aes + csrng + edn0 + edn1 + hmac + rv_plic + otbn + keymgr_dpe + kmac + sram_ctrl_main.regs + rv_core_ibex.cfg + sram_ctrl_mbox.ram + sram_ctrl_mbox.regs + soc_proxy.ctn + soc_proxy.core + dma + mbx0.core + mbx1.core + mbx2.core + mbx3.core + mbx4.core + mbx5.core + mbx6.core + mbx_jtag.core + mbx_pcie0.core + mbx_pcie1.core + ] + rv_dm.sba: + [ + rom_ctrl0.rom + rom_ctrl0.regs + rom_ctrl1.rom + rom_ctrl1.regs + rv_dm.mem + rv_dm.regs + sram_ctrl_main.ram + peri + aes + csrng + edn0 + edn1 + hmac + rv_plic + otbn + keymgr_dpe + kmac + sram_ctrl_main.regs + rv_core_ibex.cfg + sram_ctrl_mbox.ram + sram_ctrl_mbox.regs + soc_proxy.ctn + soc_proxy.core + dma + mbx0.core + mbx1.core + mbx2.core + mbx3.core + mbx4.core + mbx5.core + mbx6.core + mbx_jtag.core + mbx_pcie0.core + mbx_pcie1.core + ] + dma.host: + [ + sram_ctrl_main.ram + sram_ctrl_mbox.ram + aes + hmac + otbn + keymgr_dpe + kmac + soc_proxy.ctn + peri + ] + mbx0.sram: + [ + sram_ctrl_mbox.ram + ] + mbx1.sram: + [ + sram_ctrl_mbox.ram + ] + mbx2.sram: + [ + sram_ctrl_mbox.ram + ] + mbx3.sram: + [ + sram_ctrl_mbox.ram + ] + mbx4.sram: + [ + sram_ctrl_mbox.ram + ] + mbx5.sram: + [ + sram_ctrl_mbox.ram + ] + mbx6.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_jtag.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_pcie0.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_pcie1.sram: + [ + sram_ctrl_mbox.ram + ] + } + nodes: + [ + { + name: rv_core_ibex.corei + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: rv_core_ibex.cored + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: rv_dm.sba + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + xbar: false + stub: false + inst_type: "" + pipeline: true + } + { + name: rv_dm.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rv_dm + addr_range: + [ + { + base_addrs: + { + hart: 0x21200000 + } + size_byte: 0x10 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rv_dm.mem + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rv_dm + addr_range: + [ + { + base_addrs: + { + hart: 0x40000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rom_ctrl0.rom + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: true + rsp_fifo_pass: false + inst_type: rom_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x8000 + } + size_byte: 0x8000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rom_ctrl0.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rom_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x211e0000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rom_ctrl1.rom + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: true + rsp_fifo_pass: false + inst_type: rom_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x20000 + } + size_byte: 0x10000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rom_ctrl1.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rom_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x211e1000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: peri + type: device + clock: clk_fixed_i + reset: rst_fixed_ni + req_fifo_pass: false + rsp_fifo_pass: false + xbar: true + stub: false + pipeline: true + addr_space: hart + addr_range: + [ + { + base_addrs: + { + hart: 0x30000000 + } + size_byte: 0x800000 + } + ] + } + { + name: soc_proxy.core + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: soc_proxy + addr_range: + [ + { + base_addrs: + { + hart: 0x22030000 + } + size_byte: 0x10 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: soc_proxy.ctn + type: device + clock: clk_main_i + reset: rst_main_ni + pipefile: false + inst_type: soc_proxy + addr_range: + [ + { + base_addrs: + { + hart: 0x40000000 + } + size_byte: 0x40000000 + } + ] + xbar: false + stub: false + pipeline: true + req_fifo_pass: true + } + { + name: hmac + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: hmac + addr_range: + [ + { + base_addrs: + { + hart: 0x21110000 + } + size_byte: 0x2000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: kmac + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: kmac + addr_range: + [ + { + base_addrs: + { + hart: 0x21120000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: aes + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: aes + addr_range: + [ + { + base_addrs: + { + hart: 0x21100000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: csrng + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: csrng + addr_range: + [ + { + base_addrs: + { + hart: 0x21150000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: edn0 + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: edn + addr_range: + [ + { + base_addrs: + { + hart: 0x21170000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: edn1 + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: edn + addr_range: + [ + { + base_addrs: + { + hart: 0x21180000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rv_plic + type: device + clock: clk_main_i + reset: rst_main_ni + inst_type: rv_plic + req_fifo_pass: false + rsp_fifo_pass: false + addr_range: + [ + { + base_addrs: + { + hart: 0x28000000 + } + size_byte: 0x8000000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: otbn + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: otbn + addr_range: + [ + { + base_addrs: + { + hart: 0x21130000 + } + size_byte: 0x10000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: keymgr_dpe + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: keymgr_dpe + addr_range: + [ + { + base_addrs: + { + hart: 0x21140000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rv_core_ibex.cfg + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rv_core_ibex + addr_range: + [ + { + base_addrs: + { + hart: 0x211f0000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: sram_ctrl_main.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x211c0000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: sram_ctrl_main.ram + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x10000000 + } + size_byte: 0x10000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_mbox.regs + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x211d0000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_mbox.ram + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x11000000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: dma + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: dma + addr_range: + [ + { + base_addrs: + { + hart: 0x22010000 + } + size_byte: 0x200 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: dma.host + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx0.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx0.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx1.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000100 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx1.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx2.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000200 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx2.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx3.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000300 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx3.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx4.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000400 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx4.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx5.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000500 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx5.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx6.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000600 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx6.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_jtag.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000800 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_jtag.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_pcie0.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22040000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie0.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_pcie1.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22040100 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie1.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + ] + addr_spaces: + [ + hart + ] + clock: clk_main_i + type: xbar + inter_signal_list: + [ + { + name: tl_rv_core_ibex__corei + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_rv_core_ibex__corei + index: -1 + } + { + name: tl_rv_core_ibex__cored + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_rv_core_ibex__cored + index: -1 + } + { + name: tl_rv_dm__sba + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_rv_dm__sba + index: -1 + } + { + name: tl_dma__host + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_dma__host + index: -1 + } + { + name: tl_mbx0__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx0__sram + index: -1 + } + { + name: tl_mbx1__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx1__sram + index: -1 + } + { + name: tl_mbx2__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx2__sram + index: -1 + } + { + name: tl_mbx3__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx3__sram + index: -1 + } + { + name: tl_mbx4__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx4__sram + index: -1 + } + { + name: tl_mbx5__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx5__sram + index: -1 + } + { + name: tl_mbx6__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx6__sram + index: -1 + } + { + name: tl_mbx_jtag__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx_jtag__sram + index: -1 + } + { + name: tl_mbx_pcie0__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx_pcie0__sram + index: -1 + } + { + name: tl_mbx_pcie1__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx_pcie1__sram + index: -1 + } + { + name: tl_rv_dm__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rv_dm_regs_tl_d + index: -1 + } + { + name: tl_rv_dm__mem + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rv_dm_mem_tl_d + index: -1 + } + { + name: tl_rom_ctrl0__rom + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rom_ctrl0_rom_tl + index: -1 + } + { + name: tl_rom_ctrl0__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rom_ctrl0_regs_tl + index: -1 + } + { + name: tl_rom_ctrl1__rom + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rom_ctrl1_rom_tl + index: -1 + } + { + name: tl_rom_ctrl1__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rom_ctrl1_regs_tl + index: -1 + } + { + name: tl_peri + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_peri + index: -1 + } + { + name: tl_soc_proxy__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: soc_proxy_core_tl + index: -1 + } + { + name: tl_soc_proxy__ctn + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: soc_proxy_ctn_tl + index: -1 + } + { + name: tl_hmac + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: hmac_tl + index: -1 + } + { + name: tl_kmac + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: kmac_tl + index: -1 + } + { + name: tl_aes + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: aes_tl + index: -1 + } + { + name: tl_csrng + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: csrng_tl + index: -1 + } + { + name: tl_edn0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: edn0_tl + index: -1 + } + { + name: tl_edn1 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: edn1_tl + index: -1 + } + { + name: tl_rv_plic + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rv_plic_tl + index: -1 + } + { + name: tl_otbn + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: otbn_tl + index: -1 + } + { + name: tl_keymgr_dpe + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: keymgr_dpe_tl + index: -1 + } + { + name: tl_rv_core_ibex__cfg + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rv_core_ibex_cfg_tl_d + index: -1 + } + { + name: tl_sram_ctrl_main__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: sram_ctrl_main_regs_tl + index: -1 + } + { + name: tl_sram_ctrl_main__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: sram_ctrl_main_ram_tl + index: -1 + } + { + name: tl_sram_ctrl_mbox__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: sram_ctrl_mbox_regs_tl + index: -1 + } + { + name: tl_sram_ctrl_mbox__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: sram_ctrl_mbox_ram_tl + index: -1 + } + { + name: tl_dma + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: dma_tl_d + index: -1 + } + { + name: tl_mbx0__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx0_core_tl_d + index: -1 + } + { + name: tl_mbx1__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx1_core_tl_d + index: -1 + } + { + name: tl_mbx2__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx2_core_tl_d + index: -1 + } + { + name: tl_mbx3__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx3_core_tl_d + index: -1 + } + { + name: tl_mbx4__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx4_core_tl_d + index: -1 + } + { + name: tl_mbx5__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx5_core_tl_d + index: -1 + } + { + name: tl_mbx6__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx6_core_tl_d + index: -1 + } + { + name: tl_mbx_jtag__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx_jtag_core_tl_d + index: -1 + } + { + name: tl_mbx_pcie0__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx_pcie0_core_tl_d + index: -1 + } + { + name: tl_mbx_pcie1__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx_pcie1_core_tl_d + index: -1 + } + ] + } + { + name: peri + clock_srcs: + { + clk_peri_i: io_div4 + } + clock_group: infra + reset: rst_peri_ni + reset_connections: + { + rst_peri_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + connections: + { + main: + [ + uart0 + i2c0 + gpio + spi_host0 + spi_device + rv_timer + pwrmgr_aon + rstmgr_aon + clkmgr_aon + pinmux_aon + otp_ctrl.core + otp_ctrl.prim + lc_ctrl.regs + sensor_ctrl + alert_handler + ast + sram_ctrl_ret_aon.ram + sram_ctrl_ret_aon.regs + aon_timer_aon + ] + } + nodes: + [ + { + name: main + type: host + addr_space: hart + clock: clk_peri_i + reset: rst_peri_ni + xbar: true + pipeline: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: uart0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: uart + addr_range: + [ + { + base_addrs: + { + hart: 0x30010000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: i2c0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: i2c + addr_range: + [ + { + base_addrs: + { + hart: 0x30080000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: gpio + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: gpio + addr_range: + [ + { + base_addrs: + { + hart: 0x30000000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: spi_host0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: spi_host + addr_range: + [ + { + base_addrs: + { + hart: 0x30300000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: spi_device + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: spi_device + addr_range: + [ + { + base_addrs: + { + hart: 0x30310000 + } + size_byte: 0x2000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: rv_timer + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: rv_timer + addr_range: + [ + { + base_addrs: + { + hart: 0x30100000 + } + size_byte: 0x200 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: pwrmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: pwrmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30400000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: rstmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: rstmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30410000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: clkmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: clkmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30420000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: pinmux_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: pinmux + addr_range: + [ + { + base_addrs: + { + hart: 0x30460000 + } + size_byte: 0x800 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: otp_ctrl.core + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: otp_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30130000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: otp_ctrl.prim + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: otp_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30138000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: lc_ctrl.regs + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: lc_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30140000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sensor_ctrl + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: sensor_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30020000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: alert_handler + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: alert_handler + addr_range: + [ + { + base_addrs: + { + hart: 0x30150000 + } + size_byte: 0x800 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_ret_aon.regs + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30500000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_ret_aon.ram + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30600000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: aon_timer_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: aon_timer + addr_range: + [ + { + base_addrs: + { + hart: 0x30470000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: ast + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: ast + addr_range: + [ + { + base_addrs: + { + hart: 0x30480000 + } + size_byte: 0x400 + } + ] + xbar: false + stub: true + req_fifo_pass: true + } + ] + addr_spaces: + [ + hart + ] + clock: clk_peri_i + type: xbar + inter_signal_list: + [ + { + name: tl_main + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: peri + default: "" + top_signame: main_tl_peri + index: -1 + } + { + name: tl_uart0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: uart0_tl + index: -1 + } + { + name: tl_i2c0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: i2c0_tl + index: -1 + } + { + name: tl_gpio + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: gpio_tl + index: -1 + } + { + name: tl_spi_host0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: spi_host0_tl + index: -1 + } + { + name: tl_spi_device + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: spi_device_tl + index: -1 + } + { + name: tl_rv_timer + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: rv_timer_tl + index: -1 + } + { + name: tl_pwrmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: pwrmgr_aon_tl + index: -1 + } + { + name: tl_rstmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: rstmgr_aon_tl + index: -1 + } + { + name: tl_clkmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: clkmgr_aon_tl + index: -1 + } + { + name: tl_pinmux_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: pinmux_aon_tl + index: -1 + } + { + name: tl_otp_ctrl__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: otp_ctrl_core_tl + index: -1 + } + { + name: tl_otp_ctrl__prim + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: otp_ctrl_prim_tl + index: -1 + } + { + name: tl_lc_ctrl__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: lc_ctrl_regs_tl + index: -1 + } + { + name: tl_sensor_ctrl + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: sensor_ctrl_tl + index: -1 + } + { + name: tl_alert_handler + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: alert_handler_tl + index: -1 + } + { + name: tl_sram_ctrl_ret_aon__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: sram_ctrl_ret_aon_regs_tl + index: -1 + } + { + name: tl_sram_ctrl_ret_aon__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: sram_ctrl_ret_aon_ram_tl + index: -1 + } + { + name: tl_aon_timer_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: aon_timer_aon_tl + index: -1 + } + { + name: tl_ast + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + external: true + top_signame: ast_tl + conn_type: false + index: -1 + } + ] + } + { + name: mbx + clock_srcs: + { + clk_mbx_i: main + } + clock_group: infra + reset: rst_mbx_ni + reset_connections: + { + rst_mbx_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_mbx_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + connections: + { + mbx: + [ + mbx0.soc + mbx1.soc + mbx2.soc + mbx3.soc + mbx4.soc + mbx5.soc + mbx6.soc + mbx_pcie0.soc + mbx_pcie1.soc + ] + } + nodes: + [ + { + name: mbx + type: host + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + xbar: true + pipeline: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx0.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx1.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465100 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx2.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465200 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx3.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465300 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx4.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465400 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx5.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465500 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx6.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465600 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie0.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1460100 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie1.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1460200 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + ] + addr_spaces: + [ + soc_mbx + ] + clock: clk_mbx_i + type: xbar + inter_signal_list: + [ + { + name: tl_mbx + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx + default: "" + external: true + top_signame: mbx_tl + conn_type: false + index: -1 + } + { + name: tl_mbx0__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx0_soc_tl_d + index: -1 + } + { + name: tl_mbx1__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx1_soc_tl_d + index: -1 + } + { + name: tl_mbx2__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx2_soc_tl_d + index: -1 + } + { + name: tl_mbx3__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx3_soc_tl_d + index: -1 + } + { + name: tl_mbx4__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx4_soc_tl_d + index: -1 + } + { + name: tl_mbx5__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx5_soc_tl_d + index: -1 + } + { + name: tl_mbx6__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx6_soc_tl_d + index: -1 + } + { + name: tl_mbx_pcie0__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx_pcie0_soc_tl_d + index: -1 + } + { + name: tl_mbx_pcie1__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx_pcie1_soc_tl_d + index: -1 + } + ] + } + { + name: dbg + clock_srcs: + { + clk_dbg_i: main + clk_peri_i: io_div4 + } + clock_group: infra + reset: rst_dbg_ni + reset_connections: + { + rst_dbg_ni: + { + name: lc + domain: "0" + } + rst_peri_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_dbg_i: clkmgr_aon_clocks.clk_main_infra + clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + connections: + { + dbg: + [ + rv_dm.dbg + mbx_jtag.soc + lc_ctrl.dmi + ] + } + nodes: + [ + { + name: dbg + type: host + addr_space: soc_dbg + clock: clk_dbg_i + reset: rst_dbg_ni + xbar: true + pipeline: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: rv_dm.dbg + type: device + clock: clk_dbg_i + reset: rst_dbg_ni + pipeline: false + inst_type: rv_dm + addr_range: + [ + { + base_addrs: + { + soc_dbg: 0x0 + } + size_byte: 0x200 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_jtag.soc + type: device + clock: clk_dbg_i + reset: rst_dbg_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_dbg: 0x1000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: lc_ctrl.dmi + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: lc_ctrl + addr_range: + [ + { + base_addrs: + { + soc_dbg: 0x20000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + ] + addr_spaces: + [ + soc_dbg + ] + clock: clk_dbg_i + type: xbar + inter_signal_list: + [ + { + name: tl_dbg + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: dbg + default: "" + external: true + top_signame: dbg_tl + conn_type: false + index: -1 + } + { + name: tl_rv_dm__dbg + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: dbg + default: "" + top_signame: rv_dm_dbg_tl_d + index: -1 + } + { + name: tl_mbx_jtag__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: dbg + default: "" + top_signame: mbx_jtag_soc_tl_d + index: -1 + } + { + name: tl_lc_ctrl__dmi + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: dbg + default: "" + top_signame: lc_ctrl_dmi_tl + index: -1 + } + ] + } + ] + pinout: + { + banks: + [ + VIO + ] + pads: + [ + { + name: POR_N + type: InputStd + bank: VIO + connection: manual + desc: System reset + port_type: inout + idx: 0 + } + { + name: JTAG_TCK + type: InputStd + bank: VIO + connection: manual + desc: JTAG TCK signal + port_type: inout + idx: 1 + } + { + name: JTAG_TMS + type: InputStd + bank: VIO + connection: manual + desc: JTAG TMS signal + port_type: inout + idx: 2 + } + { + name: JTAG_TDI + type: InputStd + bank: VIO + connection: manual + desc: JTAG TDI signal + port_type: inout + idx: 3 + } + { + name: JTAG_TDO + type: BidirStd + bank: VIO + connection: manual + desc: JTAG TDO signal + port_type: inout + idx: 4 + } + { + name: JTAG_TRST_N + type: InputStd + bank: VIO + connection: manual + desc: JTAG TRST_N signal + port_type: inout + idx: 5 + } + { + name: OTP_EXT_VOLT + type: AnalogIn1 + bank: VIO + connection: manual + desc: OTP external voltage input + port_type: inout + idx: 6 + } + { + name: SPI_HOST_D0 + type: BidirStd + bank: VIO + connection: direct + desc: SPI host data + port_type: inout + idx: 7 + } + { + name: SPI_HOST_D1 + type: BidirStd + bank: VIO + connection: direct + desc: SPI host data + port_type: inout + idx: 8 + } + { + name: SPI_HOST_D2 + type: BidirStd + bank: VIO + connection: direct + desc: SPI host data + port_type: inout + idx: 9 + } + { + name: SPI_HOST_D3 + type: BidirStd + bank: VIO + connection: direct + desc: SPI host data + port_type: inout + idx: 10 + } + { + name: SPI_HOST_CLK + type: BidirStd + bank: VIO + connection: direct + desc: SPI host clock + port_type: inout + idx: 11 + } + { + name: SPI_HOST_CS_L + type: BidirStd + bank: VIO + connection: direct + desc: SPI host chip select + port_type: inout + idx: 12 + } + { + name: SPI_DEV_D0 + type: BidirStd + bank: VIO + connection: direct + desc: SPI device data + port_type: inout + idx: 13 + } + { + name: SPI_DEV_D1 + type: BidirStd + bank: VIO + connection: direct + desc: SPI device data + port_type: inout + idx: 14 + } + { + name: SPI_DEV_D2 + type: BidirStd + bank: VIO + connection: direct + desc: SPI device data + port_type: inout + idx: 15 + } + { + name: SPI_DEV_D3 + type: BidirStd + bank: VIO + connection: direct + desc: SPI device data + port_type: inout + idx: 16 + } + { + name: SPI_DEV_CLK + type: InputStd + bank: VIO + connection: direct + desc: SPI device clock + port_type: inout + idx: 17 + } + { + name: SPI_DEV_CS_L + type: InputStd + bank: VIO + connection: direct + desc: SPI device chip select + port_type: inout + idx: 18 + } + { + name: SPI_DEV_TPM_CS_L + type: InputStd + bank: VIO + connection: direct + desc: SPI device TPM chip select + port_type: inout + idx: 19 + } + { + name: UART_RX + type: InputStd + bank: VIO + connection: direct + desc: UART receive + port_type: inout + idx: 20 + } + { + name: UART_TX + type: BidirStd + bank: VIO + connection: direct + desc: UART transmit + port_type: inout + idx: 21 + } + { + name: I2C_SCL + type: BidirStd + bank: VIO + connection: direct + desc: I2C clock + port_type: inout + idx: 22 + } + { + name: I2C_SDA + type: BidirStd + bank: VIO + connection: direct + desc: I2C data + port_type: inout + idx: 23 + } + { + name: GPIO0 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 24 + } + { + name: GPIO1 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 25 + } + { + name: GPIO2 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 26 + } + { + name: GPIO3 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 27 + } + { + name: GPIO4 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 28 + } + { + name: GPIO5 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 29 + } + { + name: GPIO6 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 30 + } + { + name: GPIO7 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 31 + } + { + name: GPIO8 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 32 + } + { + name: GPIO9 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 33 + } + { + name: GPIO10 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 34 + } + { + name: GPIO11 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 35 + } + { + name: GPIO12 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 36 + } + { + name: GPIO13 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 37 + } + { + name: GPIO14 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 38 + } + { + name: GPIO15 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 39 + } + { + name: GPIO16 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 40 + } + { + name: GPIO17 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 41 + } + { + name: GPIO18 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 42 + } + { + name: GPIO19 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 43 + } + { + name: GPIO20 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 44 + } + { + name: GPIO21 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 45 + } + { + name: GPIO22 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 46 + } + { + name: GPIO23 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 47 + } + { + name: GPIO24 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 48 + } + { + name: GPIO25 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 49 + } + { + name: GPIO26 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 50 + } + { + name: GPIO27 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 51 + } + { + name: GPIO28 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 52 + } + { + name: GPIO29 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 53 + } + { + name: GPIO30 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 54 + } + { + name: GPIO31 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + port_type: inout + idx: 55 + } + { + name: SOC_GPI0 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + port_type: inout + idx: 56 + } + { + name: SOC_GPI1 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + port_type: inout + idx: 57 + } + { + name: SOC_GPI2 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + port_type: inout + idx: 58 + } + { + name: SOC_GPI3 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + port_type: inout + idx: 59 + } + { + name: SOC_GPI4 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + port_type: inout + idx: 60 + } + { + name: SOC_GPI5 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + port_type: inout + idx: 61 + } + { + name: SOC_GPI6 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + port_type: inout + idx: 62 + } + { + name: SOC_GPI7 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + port_type: inout + idx: 63 + } + { + name: SOC_GPI8 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + port_type: inout + idx: 64 + } + { + name: SOC_GPI9 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + port_type: inout + idx: 65 + } + { + name: SOC_GPI10 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + port_type: inout + idx: 66 + } + { + name: SOC_GPI11 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + port_type: inout + idx: 67 + } + { + name: SOC_GPO0 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + port_type: inout + idx: 68 + } + { + name: SOC_GPO1 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + port_type: inout + idx: 69 + } + { + name: SOC_GPO2 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + port_type: inout + idx: 70 + } + { + name: SOC_GPO3 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + port_type: inout + idx: 71 + } + { + name: SOC_GPO4 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + port_type: inout + idx: 72 + } + { + name: SOC_GPO5 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + port_type: inout + idx: 73 + } + { + name: SOC_GPO6 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + port_type: inout + idx: 74 + } + { + name: SOC_GPO7 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + port_type: inout + idx: 75 + } + { + name: SOC_GPO8 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + port_type: inout + idx: 76 + } + { + name: SOC_GPO9 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + port_type: inout + idx: 77 + } + { + name: SOC_GPO10 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + port_type: inout + idx: 78 + } + { + name: SOC_GPO11 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + port_type: inout + idx: 79 + } + { + name: MIO0 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + port_type: inout + idx: 0 + } + { + name: MIO1 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + port_type: inout + idx: 1 + } + { + name: MIO2 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + port_type: inout + idx: 2 + } + { + name: MIO3 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + port_type: inout + idx: 3 + } + { + name: MIO4 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + port_type: inout + idx: 4 + } + { + name: MIO5 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + port_type: inout + idx: 5 + } + { + name: MIO6 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + port_type: inout + idx: 6 + } + { + name: MIO7 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + port_type: inout + idx: 7 + } + { + name: MIO8 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + port_type: inout + idx: 8 + } + { + name: MIO9 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + port_type: inout + idx: 9 + } + { + name: MIO10 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + port_type: inout + idx: 10 + } + { + name: MIO11 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + port_type: inout + idx: 11 + } + ] + } + pinmux: + { + signals: + [ + { + instance: spi_host0 + port: sck + connection: direct + pad: SPI_HOST_CLK + desc: "" + attr: BidirStd + } + { + instance: spi_host0 + port: csb + connection: direct + pad: SPI_HOST_CS_L + desc: "" + attr: BidirStd + } + { + instance: spi_host0 + port: sd[0] + connection: direct + pad: SPI_HOST_D0 + desc: "" + attr: BidirStd + } + { + instance: spi_host0 + port: sd[1] + connection: direct + pad: SPI_HOST_D1 + desc: "" + attr: BidirStd + } + { + instance: spi_host0 + port: sd[2] + connection: direct + pad: SPI_HOST_D2 + desc: "" + attr: BidirStd + } + { + instance: spi_host0 + port: sd[3] + connection: direct + pad: SPI_HOST_D3 + desc: "" + attr: BidirStd + } + { + instance: spi_device + port: sck + connection: direct + pad: SPI_DEV_CLK + desc: "" + attr: InputStd + } + { + instance: spi_device + port: csb + connection: direct + pad: SPI_DEV_CS_L + desc: "" + attr: InputStd + } + { + instance: spi_device + port: sd[0] + connection: direct + pad: SPI_DEV_D0 + desc: "" + attr: BidirStd + } + { + instance: spi_device + port: sd[1] + connection: direct + pad: SPI_DEV_D1 + desc: "" + attr: BidirStd + } + { + instance: spi_device + port: sd[2] + connection: direct + pad: SPI_DEV_D2 + desc: "" + attr: BidirStd + } + { + instance: spi_device + port: sd[3] + connection: direct + pad: SPI_DEV_D3 + desc: "" + attr: BidirStd + } + { + instance: spi_device + port: tpm_csb + connection: direct + pad: SPI_DEV_TPM_CS_L + desc: "" + attr: InputStd + } + { + instance: uart0 + port: rx + connection: direct + pad: UART_RX + desc: "" + attr: InputStd + } + { + instance: uart0 + port: tx + connection: direct + pad: UART_TX + desc: "" + attr: BidirStd + } + { + instance: i2c0 + port: scl + connection: direct + pad: I2C_SCL + desc: "" + attr: BidirStd + } + { + instance: i2c0 + port: sda + connection: direct + pad: I2C_SDA + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[0] + connection: direct + pad: GPIO0 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[1] + connection: direct + pad: GPIO1 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[2] + connection: direct + pad: GPIO2 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[3] + connection: direct + pad: GPIO3 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[4] + connection: direct + pad: GPIO4 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[5] + connection: direct + pad: GPIO5 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[6] + connection: direct + pad: GPIO6 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[7] + connection: direct + pad: GPIO7 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[8] + connection: direct + pad: GPIO8 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[9] + connection: direct + pad: GPIO9 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[10] + connection: direct + pad: GPIO10 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[11] + connection: direct + pad: GPIO11 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[12] + connection: direct + pad: GPIO12 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[13] + connection: direct + pad: GPIO13 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[14] + connection: direct + pad: GPIO14 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[15] + connection: direct + pad: GPIO15 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[16] + connection: direct + pad: GPIO16 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[17] + connection: direct + pad: GPIO17 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[18] + connection: direct + pad: GPIO18 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[19] + connection: direct + pad: GPIO19 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[20] + connection: direct + pad: GPIO20 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[21] + connection: direct + pad: GPIO21 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[22] + connection: direct + pad: GPIO22 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[23] + connection: direct + pad: GPIO23 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[24] + connection: direct + pad: GPIO24 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[25] + connection: direct + pad: GPIO25 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[26] + connection: direct + pad: GPIO26 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[27] + connection: direct + pad: GPIO27 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[28] + connection: direct + pad: GPIO28 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[29] + connection: direct + pad: GPIO29 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[30] + connection: direct + pad: GPIO30 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[31] + connection: direct + pad: GPIO31 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpi[0] + connection: direct + pad: SOC_GPI0 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[1] + connection: direct + pad: SOC_GPI1 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[2] + connection: direct + pad: SOC_GPI2 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[3] + connection: direct + pad: SOC_GPI3 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[4] + connection: direct + pad: SOC_GPI4 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[5] + connection: direct + pad: SOC_GPI5 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[6] + connection: direct + pad: SOC_GPI6 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[7] + connection: direct + pad: SOC_GPI7 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[8] + connection: direct + pad: SOC_GPI8 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[9] + connection: direct + pad: SOC_GPI9 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[10] + connection: direct + pad: SOC_GPI10 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[11] + connection: direct + pad: SOC_GPI11 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[12] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpi[13] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpi[14] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpi[15] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpo[0] + connection: direct + pad: SOC_GPO0 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[1] + connection: direct + pad: SOC_GPO1 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[2] + connection: direct + pad: SOC_GPO2 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[3] + connection: direct + pad: SOC_GPO3 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[4] + connection: direct + pad: SOC_GPO4 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[5] + connection: direct + pad: SOC_GPO5 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[6] + connection: direct + pad: SOC_GPO6 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[7] + connection: direct + pad: SOC_GPO7 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[8] + connection: direct + pad: SOC_GPO8 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[9] + connection: direct + pad: SOC_GPO9 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[10] + connection: direct + pad: SOC_GPO10 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[11] + connection: direct + pad: SOC_GPO11 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[12] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpo[13] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpo[14] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpo[15] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: otp_ctrl + port: test[0] + connection: muxed + pad: "" + desc: "" + attr: "" + } + ] + num_wkup_detect: 8 + wkup_cnt_width: 8 + enable_usb_wakeup: false + enable_strap_sampling: false + ios: + [ + { + name: spi_host0_sd + width: 4 + type: inout + idx: 0 + pad: SPI_HOST_D0 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 0 + } + { + name: spi_host0_sd + width: 4 + type: inout + idx: 1 + pad: SPI_HOST_D1 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 1 + } + { + name: spi_host0_sd + width: 4 + type: inout + idx: 2 + pad: SPI_HOST_D2 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 2 + } + { + name: spi_host0_sd + width: 4 + type: inout + idx: 3 + pad: SPI_HOST_D3 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 3 + } + { + name: spi_device_sd + width: 4 + type: inout + idx: 0 + pad: SPI_DEV_D0 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 4 + } + { + name: spi_device_sd + width: 4 + type: inout + idx: 1 + pad: SPI_DEV_D1 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 5 + } + { + name: spi_device_sd + width: 4 + type: inout + idx: 2 + pad: SPI_DEV_D2 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 6 + } + { + name: spi_device_sd + width: 4 + type: inout + idx: 3 + pad: SPI_DEV_D3 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 7 + } + { + name: i2c0_scl + width: 1 + type: inout + idx: -1 + pad: I2C_SCL + attr: BidirStd + connection: direct + desc: "" + glob_idx: 8 + } + { + name: i2c0_sda + width: 1 + type: inout + idx: -1 + pad: I2C_SDA + attr: BidirStd + connection: direct + desc: "" + glob_idx: 9 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 0 + pad: GPIO0 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 10 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 1 + pad: GPIO1 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 11 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 2 + pad: GPIO2 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 12 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 3 + pad: GPIO3 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 13 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 4 + pad: GPIO4 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 14 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 5 + pad: GPIO5 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 15 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 6 + pad: GPIO6 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 16 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 7 + pad: GPIO7 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 17 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 8 + pad: GPIO8 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 18 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 9 + pad: GPIO9 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 19 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 10 + pad: GPIO10 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 20 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 11 + pad: GPIO11 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 21 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 12 + pad: GPIO12 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 22 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 13 + pad: GPIO13 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 23 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 14 + pad: GPIO14 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 24 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 15 + pad: GPIO15 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 25 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 16 + pad: GPIO16 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 26 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 17 + pad: GPIO17 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 27 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 18 + pad: GPIO18 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 28 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 19 + pad: GPIO19 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 29 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 20 + pad: GPIO20 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 30 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 21 + pad: GPIO21 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 31 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 22 + pad: GPIO22 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 32 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 23 + pad: GPIO23 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 33 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 24 + pad: GPIO24 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 34 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 25 + pad: GPIO25 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 35 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 26 + pad: GPIO26 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 36 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 27 + pad: GPIO27 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 37 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 28 + pad: GPIO28 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 38 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 29 + pad: GPIO29 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 39 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 30 + pad: GPIO30 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 40 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 31 + pad: GPIO31 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 41 + } + { + name: spi_device_sck + width: 1 + type: input + idx: -1 + pad: SPI_DEV_CLK + attr: InputStd + connection: direct + desc: "" + glob_idx: 42 + } + { + name: spi_device_csb + width: 1 + type: input + idx: -1 + pad: SPI_DEV_CS_L + attr: InputStd + connection: direct + desc: "" + glob_idx: 43 + } + { + name: spi_device_tpm_csb + width: 1 + type: input + idx: -1 + pad: SPI_DEV_TPM_CS_L + attr: InputStd + connection: direct + desc: "" + glob_idx: 44 + } + { + name: uart0_rx + width: 1 + type: input + idx: -1 + pad: UART_RX + attr: InputStd + connection: direct + desc: "" + glob_idx: 45 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 0 + pad: SOC_GPI0 + attr: InputStd + connection: direct + desc: "" + glob_idx: 46 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 1 + pad: SOC_GPI1 + attr: InputStd + connection: direct + desc: "" + glob_idx: 47 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 2 + pad: SOC_GPI2 + attr: InputStd + connection: direct + desc: "" + glob_idx: 48 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 3 + pad: SOC_GPI3 + attr: InputStd + connection: direct + desc: "" + glob_idx: 49 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 4 + pad: SOC_GPI4 + attr: InputStd + connection: direct + desc: "" + glob_idx: 50 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 5 + pad: SOC_GPI5 + attr: InputStd + connection: direct + desc: "" + glob_idx: 51 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 6 + pad: SOC_GPI6 + attr: InputStd + connection: direct + desc: "" + glob_idx: 52 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 7 + pad: SOC_GPI7 + attr: InputStd + connection: direct + desc: "" + glob_idx: 53 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 8 + pad: SOC_GPI8 + attr: InputStd + connection: direct + desc: "" + glob_idx: 54 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 9 + pad: SOC_GPI9 + attr: InputStd + connection: direct + desc: "" + glob_idx: 55 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 10 + pad: SOC_GPI10 + attr: InputStd + connection: direct + desc: "" + glob_idx: 56 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 11 + pad: SOC_GPI11 + attr: InputStd + connection: direct + desc: "" + glob_idx: 57 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 12 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 0 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 13 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 1 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 14 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 2 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 15 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 3 + } + { + name: spi_host0_sck + width: 1 + type: output + idx: -1 + pad: SPI_HOST_CLK + attr: BidirStd + connection: direct + desc: "" + glob_idx: 58 + } + { + name: spi_host0_csb + width: 1 + type: output + idx: -1 + pad: SPI_HOST_CS_L + attr: BidirStd + connection: direct + desc: "" + glob_idx: 59 + } + { + name: uart0_tx + width: 1 + type: output + idx: -1 + pad: UART_TX + attr: BidirStd + connection: direct + desc: "" + glob_idx: 60 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 0 + pad: SOC_GPO0 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 61 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 1 + pad: SOC_GPO1 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 62 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 2 + pad: SOC_GPO2 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 63 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 3 + pad: SOC_GPO3 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 64 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 4 + pad: SOC_GPO4 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 65 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 5 + pad: SOC_GPO5 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 66 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 6 + pad: SOC_GPO6 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 67 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 7 + pad: SOC_GPO7 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 68 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 8 + pad: SOC_GPO8 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 69 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 9 + pad: SOC_GPO9 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 70 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 10 + pad: SOC_GPO10 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 71 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 11 + pad: SOC_GPO11 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 72 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 12 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 0 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 13 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 1 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 14 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 2 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 15 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 3 + } + { + name: otp_ctrl_test + width: 8 + type: output + idx: 0 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 4 + } + ] + io_counts: + { + dedicated: + { + inouts: 42 + inputs: 16 + outputs: 15 + pads: 80 + } + muxed: + { + inouts: 0 + inputs: 4 + outputs: 5 + pads: 12 + } + } + } + targets: + [ + { + name: asic + pinout: + { + remove_ports: [] + remove_pads: [] + add_pads: [] + } + pinmux: + { + special_signals: + [ + { + name: tap0 + pad: MIO0 + desc: TAP strap signal. + idx: 0 + } + { + name: tap1 + pad: MIO1 + desc: TAP strap signal. + idx: 1 + } + { + name: dft0 + pad: MIO2 + desc: DFT strap signal. + idx: 2 + } + { + name: dft1 + pad: MIO3 + desc: DFT strap signal. + idx: 3 + } + { + name: tck + pad: MIO4 + desc: JTAG tck signal. + idx: 4 + } + { + name: tms + pad: MIO5 + desc: JTAG tms signal. + idx: 5 + } + { + name: trst_n + pad: MIO6 + desc: JTAG trst_n signal. + idx: 6 + } + { + name: tdi + pad: MIO7 + desc: JTAG tdi signal. + idx: 7 + } + { + name: tdo + pad: MIO8 + desc: JTAG tdo signal. + idx: 8 + } + ] + } + } + { + name: cw310 + pinout: + { + remove_ports: [] + remove_pads: + [ + OTP_EXT_VOLT + ] + add_pads: + [ + { + name: IO_CLK + type: InputStd + bank: VIO + connection: manual + desc: Extra clock input for FPGA target + port_type: inout + } + { + name: POR_BUTTON_N + type: InputStd + bank: VIO + connection: manual + desc: Power-on reset button input + port_type: inout + } + { + name: IO_CLKOUT + type: BidirStd + bank: VIO + connection: manual + desc: Manual clock output for SCA setup + port_type: inout + } + { + name: IO_TRIGGER + type: BidirStd + bank: VIO + connection: manual + desc: Manual trigger output for SCA setup + port_type: inout + } + ] + } + pinmux: + { + special_signals: + [ + { + name: tap0 + pad: MIO0 + desc: TAP strap signal. + idx: 0 + } + { + name: tap1 + pad: MIO1 + desc: TAP strap signal. + idx: 1 + } + { + name: dft0 + pad: MIO2 + desc: DFT strap signal. + idx: 2 + } + { + name: dft1 + pad: MIO3 + desc: DFT strap signal. + idx: 3 + } + { + name: tck + pad: MIO4 + desc: JTAG tck signal. + idx: 4 + } + { + name: tms + pad: MIO5 + desc: JTAG tms signal. + idx: 5 + } + { + name: trst_n + pad: MIO6 + desc: JTAG trst_n signal. + idx: 6 + } + { + name: tdi + pad: MIO7 + desc: JTAG tdi signal. + idx: 7 + } + { + name: tdo + pad: MIO8 + desc: JTAG tdo signal. + idx: 8 + } + ] + } + } + ] + exported_clks: {} + wakeups: + [ + { + name: pin_wkup_req + width: "1" + module: pinmux_aon + } + { + name: usb_wkup_req + width: "1" + module: pinmux_aon + } + { + name: wkup_req + width: "1" + module: aon_timer_aon + } + { + name: wkup_req + width: "1" + module: sensor_ctrl + } + { + name: wkup_internal_req + width: "1" + module: soc_proxy + } + { + name: wkup_external_req + width: "1" + module: soc_proxy + } + ] + reset_requests: + { + peripheral: + [ + { + name: aon_timer_rst_req + width: "1" + module: aon_timer_aon + desc: watchdog reset requestt + } + { + name: rst_req_external + width: "1" + module: soc_proxy + desc: External reset request + } + ] + int: + [ + { + name: MainPwr + desc: main power glitch reset request + module: pwrmgr_aon + } + { + name: Esc + desc: escalation reset request + module: alert_handler + } + ] + debug: + [ + { + name: Ndm + desc: non-debug-module reset request + module: rv_dm + } + ] + } + interrupt_module: + [ + uart0 + gpio + spi_device + i2c0 + rv_timer + otp_ctrl + alert_handler + spi_host0 + pwrmgr_aon + aon_timer_aon + sensor_ctrl + soc_proxy + hmac + kmac + otbn + keymgr_dpe + csrng + edn0 + edn1 + dma + mbx0 + mbx1 + mbx2 + mbx3 + mbx4 + mbx5 + mbx6 + mbx_jtag + mbx_pcie0 + mbx_pcie1 + ] + interrupt: + [ + { + name: uart0_tx_watermark + width: 1 + type: interrupt + module_name: uart0 + intr_type: IntrType.Status + default_val: true + } + { + name: uart0_rx_watermark + width: 1 + type: interrupt + module_name: uart0 + intr_type: IntrType.Status + default_val: false + } + { + name: uart0_tx_done + width: 1 + type: interrupt + module_name: uart0 + intr_type: IntrType.Event + default_val: false + } + { + name: uart0_rx_overflow + width: 1 + type: interrupt + module_name: uart0 + intr_type: IntrType.Event + default_val: false + } + { + name: uart0_rx_frame_err + width: 1 + type: interrupt + module_name: uart0 + intr_type: IntrType.Event + default_val: false + } + { + name: uart0_rx_break_err + width: 1 + type: interrupt + module_name: uart0 + intr_type: IntrType.Event + default_val: false + } + { + name: uart0_rx_timeout + width: 1 + type: interrupt + module_name: uart0 + intr_type: IntrType.Event + default_val: false + } + { + name: uart0_rx_parity_err + width: 1 + type: interrupt + module_name: uart0 + intr_type: IntrType.Event + default_val: false + } + { + name: uart0_tx_empty + width: 1 + type: interrupt + module_name: uart0 + intr_type: IntrType.Status + default_val: true + } + { + name: gpio_gpio + width: 32 + type: interrupt + module_name: gpio + intr_type: IntrType.Event + default_val: false + } + { + name: spi_device_upload_cmdfifo_not_empty + width: 1 + type: interrupt + module_name: spi_device + intr_type: IntrType.Event + default_val: false + } + { + name: spi_device_upload_payload_not_empty + width: 1 + type: interrupt + module_name: spi_device + intr_type: IntrType.Event + default_val: false + } + { + name: spi_device_upload_payload_overflow + width: 1 + type: interrupt + module_name: spi_device + intr_type: IntrType.Event + default_val: false + } + { + name: spi_device_readbuf_watermark + width: 1 + type: interrupt + module_name: spi_device + intr_type: IntrType.Event + default_val: false + } + { + name: spi_device_readbuf_flip + width: 1 + type: interrupt + module_name: spi_device + intr_type: IntrType.Event + default_val: false + } + { + name: spi_device_tpm_header_not_empty + width: 1 + type: interrupt + module_name: spi_device + intr_type: IntrType.Status + default_val: false + } + { + name: spi_device_tpm_rdfifo_cmd_end + width: 1 + type: interrupt + module_name: spi_device + intr_type: IntrType.Event + default_val: false + } + { + name: spi_device_tpm_rdfifo_drop + width: 1 + type: interrupt + module_name: spi_device + intr_type: IntrType.Event + default_val: false + } + { + name: i2c0_fmt_threshold + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Status + default_val: false + } + { + name: i2c0_rx_threshold + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Status + default_val: false + } + { + name: i2c0_acq_threshold + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Status + default_val: false + } + { + name: i2c0_rx_overflow + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Event + default_val: false + } + { + name: i2c0_controller_halt + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Status + default_val: false + } + { + name: i2c0_scl_interference + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Event + default_val: false + } + { + name: i2c0_sda_interference + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Event + default_val: false + } + { + name: i2c0_stretch_timeout + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Event + default_val: false + } + { + name: i2c0_sda_unstable + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Event + default_val: false + } + { + name: i2c0_cmd_complete + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Event + default_val: false + } + { + name: i2c0_tx_stretch + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Status + default_val: false + } + { + name: i2c0_tx_threshold + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Status + default_val: false + } + { + name: i2c0_acq_stretch + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Status + default_val: false + } + { + name: i2c0_unexp_stop + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Event + default_val: false + } + { + name: i2c0_host_timeout + width: 1 + type: interrupt + module_name: i2c0 + intr_type: IntrType.Event + default_val: false + } + { + name: rv_timer_timer_expired_hart0_timer0 + width: 1 + type: interrupt + module_name: rv_timer + intr_type: IntrType.Event + default_val: false + } + { + name: otp_ctrl_otp_operation_done + width: 1 + type: interrupt + module_name: otp_ctrl + intr_type: IntrType.Event + default_val: false + } + { + name: otp_ctrl_otp_error + width: 1 + type: interrupt + module_name: otp_ctrl + intr_type: IntrType.Event + default_val: false + } + { + name: alert_handler_classa + width: 1 + type: interrupt + module_name: alert_handler + intr_type: IntrType.Event + default_val: false + } + { + name: alert_handler_classb + width: 1 + type: interrupt + module_name: alert_handler + intr_type: IntrType.Event + default_val: false + } + { + name: alert_handler_classc + width: 1 + type: interrupt + module_name: alert_handler + intr_type: IntrType.Event + default_val: false + } + { + name: alert_handler_classd + width: 1 + type: interrupt + module_name: alert_handler + intr_type: IntrType.Event + default_val: false + } + { + name: spi_host0_error + width: 1 + type: interrupt + module_name: spi_host0 + intr_type: IntrType.Event + default_val: false + } + { + name: spi_host0_spi_event + width: 1 + type: interrupt + module_name: spi_host0 + intr_type: IntrType.Status + default_val: false + } + { + name: pwrmgr_aon_wakeup + width: 1 + type: interrupt + module_name: pwrmgr_aon + intr_type: IntrType.Event + default_val: false + } + { + name: aon_timer_aon_wkup_timer_expired + width: 1 + type: interrupt + module_name: aon_timer_aon + intr_type: IntrType.Event + default_val: false + } + { + name: aon_timer_aon_wdog_timer_bark + width: 1 + type: interrupt + module_name: aon_timer_aon + intr_type: IntrType.Event + default_val: false + } + { + name: sensor_ctrl_io_status_change + width: 1 + type: interrupt + module_name: sensor_ctrl + intr_type: IntrType.Event + default_val: false + } + { + name: sensor_ctrl_init_status_change + width: 1 + type: interrupt + module_name: sensor_ctrl + intr_type: IntrType.Event + default_val: false + } + { + name: soc_proxy_external + width: 32 + type: interrupt + module_name: soc_proxy + intr_type: IntrType.Event + default_val: false + } + { + name: hmac_hmac_done + width: 1 + type: interrupt + module_name: hmac + intr_type: IntrType.Event + default_val: false + } + { + name: hmac_fifo_empty + width: 1 + type: interrupt + module_name: hmac + intr_type: IntrType.Status + default_val: false + } + { + name: hmac_hmac_err + width: 1 + type: interrupt + module_name: hmac + intr_type: IntrType.Event + default_val: false + } + { + name: kmac_kmac_done + width: 1 + type: interrupt + module_name: kmac + intr_type: IntrType.Event + default_val: false + } + { + name: kmac_fifo_empty + width: 1 + type: interrupt + module_name: kmac + intr_type: IntrType.Status + default_val: false + } + { + name: kmac_kmac_err + width: 1 + type: interrupt + module_name: kmac + intr_type: IntrType.Event + default_val: false + } + { + name: otbn_done + width: 1 + type: interrupt + module_name: otbn + intr_type: IntrType.Event + default_val: false + } + { + name: keymgr_dpe_op_done + width: 1 + type: interrupt + module_name: keymgr_dpe + intr_type: IntrType.Event + default_val: false + } + { + name: csrng_cs_cmd_req_done + width: 1 + type: interrupt + module_name: csrng + intr_type: IntrType.Event + default_val: false + } + { + name: csrng_cs_entropy_req + width: 1 + type: interrupt + module_name: csrng + intr_type: IntrType.Event + default_val: false + } + { + name: csrng_cs_hw_inst_exc + width: 1 + type: interrupt + module_name: csrng + intr_type: IntrType.Event + default_val: false + } + { + name: csrng_cs_fatal_err + width: 1 + type: interrupt + module_name: csrng + intr_type: IntrType.Event + default_val: false + } + { + name: edn0_edn_cmd_req_done + width: 1 + type: interrupt + module_name: edn0 + intr_type: IntrType.Event + default_val: false + } + { + name: edn0_edn_fatal_err + width: 1 + type: interrupt + module_name: edn0 + intr_type: IntrType.Event + default_val: false + } + { + name: edn1_edn_cmd_req_done + width: 1 + type: interrupt + module_name: edn1 + intr_type: IntrType.Event + default_val: false + } + { + name: edn1_edn_fatal_err + width: 1 + type: interrupt + module_name: edn1 + intr_type: IntrType.Event + default_val: false + } + { + name: dma_dma_done + width: 1 + type: interrupt + module_name: dma + intr_type: IntrType.Status + default_val: false + } + { + name: dma_dma_chunk_done + width: 1 + type: interrupt + module_name: dma + intr_type: IntrType.Status + default_val: false + } + { + name: dma_dma_error + width: 1 + type: interrupt + module_name: dma + intr_type: IntrType.Status + default_val: false + } + { + name: mbx0_mbx_ready + width: 1 + type: interrupt + module_name: mbx0 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx0_mbx_abort + width: 1 + type: interrupt + module_name: mbx0 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx0_mbx_error + width: 1 + type: interrupt + module_name: mbx0 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx1_mbx_ready + width: 1 + type: interrupt + module_name: mbx1 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx1_mbx_abort + width: 1 + type: interrupt + module_name: mbx1 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx1_mbx_error + width: 1 + type: interrupt + module_name: mbx1 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx2_mbx_ready + width: 1 + type: interrupt + module_name: mbx2 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx2_mbx_abort + width: 1 + type: interrupt + module_name: mbx2 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx2_mbx_error + width: 1 + type: interrupt + module_name: mbx2 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx3_mbx_ready + width: 1 + type: interrupt + module_name: mbx3 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx3_mbx_abort + width: 1 + type: interrupt + module_name: mbx3 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx3_mbx_error + width: 1 + type: interrupt + module_name: mbx3 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx4_mbx_ready + width: 1 + type: interrupt + module_name: mbx4 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx4_mbx_abort + width: 1 + type: interrupt + module_name: mbx4 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx4_mbx_error + width: 1 + type: interrupt + module_name: mbx4 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx5_mbx_ready + width: 1 + type: interrupt + module_name: mbx5 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx5_mbx_abort + width: 1 + type: interrupt + module_name: mbx5 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx5_mbx_error + width: 1 + type: interrupt + module_name: mbx5 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx6_mbx_ready + width: 1 + type: interrupt + module_name: mbx6 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx6_mbx_abort + width: 1 + type: interrupt + module_name: mbx6 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx6_mbx_error + width: 1 + type: interrupt + module_name: mbx6 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx_jtag_mbx_ready + width: 1 + type: interrupt + module_name: mbx_jtag + intr_type: IntrType.Event + default_val: false + } + { + name: mbx_jtag_mbx_abort + width: 1 + type: interrupt + module_name: mbx_jtag + intr_type: IntrType.Event + default_val: false + } + { + name: mbx_jtag_mbx_error + width: 1 + type: interrupt + module_name: mbx_jtag + intr_type: IntrType.Event + default_val: false + } + { + name: mbx_pcie0_mbx_ready + width: 1 + type: interrupt + module_name: mbx_pcie0 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx_pcie0_mbx_abort + width: 1 + type: interrupt + module_name: mbx_pcie0 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx_pcie0_mbx_error + width: 1 + type: interrupt + module_name: mbx_pcie0 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx_pcie1_mbx_ready + width: 1 + type: interrupt + module_name: mbx_pcie1 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx_pcie1_mbx_abort + width: 1 + type: interrupt + module_name: mbx_pcie1 + intr_type: IntrType.Event + default_val: false + } + { + name: mbx_pcie1_mbx_error + width: 1 + type: interrupt + module_name: mbx_pcie1 + intr_type: IntrType.Event + default_val: false + } + ] + alert_module: + [ + uart0 + gpio + spi_device + i2c0 + rv_timer + otp_ctrl + lc_ctrl + spi_host0 + pwrmgr_aon + rstmgr_aon + clkmgr_aon + pinmux_aon + aon_timer_aon + sensor_ctrl + soc_proxy + sram_ctrl_ret_aon + rv_dm + rv_plic + aes + hmac + kmac + otbn + keymgr_dpe + csrng + edn0 + edn1 + sram_ctrl_main + sram_ctrl_mbox + rom_ctrl0 + rom_ctrl1 + dma + mbx0 + mbx1 + mbx2 + mbx3 + mbx4 + mbx5 + mbx6 + mbx_jtag + mbx_pcie0 + mbx_pcie1 + rv_core_ibex + ] + alert: + [ + { + name: uart0_fatal_fault + width: 1 + type: alert + async: "1" + module_name: uart0 + lpg_name: peri_lc_io_div4_0 + lpg_idx: 0 + } + { + name: gpio_fatal_fault + width: 1 + type: alert + async: "1" + module_name: gpio + lpg_name: peri_lc_io_div4_0 + lpg_idx: 0 + } + { + name: spi_device_fatal_fault + width: 1 + type: alert + async: "1" + module_name: spi_device + lpg_name: peri_spi_device_0 + lpg_idx: 1 + } + { + name: i2c0_fatal_fault + width: 1 + type: alert + async: "1" + module_name: i2c0 + lpg_name: peri_i2c0_0 + lpg_idx: 2 + } + { + name: rv_timer_fatal_fault + width: 1 + type: alert + async: "1" + module_name: rv_timer + lpg_name: timers_lc_io_div4_0 + lpg_idx: 3 + } + { + name: otp_ctrl_fatal_macro_error + width: 1 + type: alert + async: "1" + module_name: otp_ctrl + lpg_name: secure_lc_io_div4_0 + lpg_idx: 4 + } + { + name: otp_ctrl_fatal_check_error + width: 1 + type: alert + async: "1" + module_name: otp_ctrl + lpg_name: secure_lc_io_div4_0 + lpg_idx: 4 + } + { + name: otp_ctrl_fatal_bus_integ_error + width: 1 + type: alert + async: "1" + module_name: otp_ctrl + lpg_name: secure_lc_io_div4_0 + lpg_idx: 4 + } + { + name: otp_ctrl_fatal_prim_otp_alert + width: 1 + type: alert + async: "1" + module_name: otp_ctrl + lpg_name: secure_lc_io_div4_0 + lpg_idx: 4 + } + { + name: otp_ctrl_recov_prim_otp_alert + width: 1 + type: alert + async: "1" + module_name: otp_ctrl + lpg_name: secure_lc_io_div4_0 + lpg_idx: 4 + } + { + name: lc_ctrl_fatal_prog_error + width: 1 + type: alert + async: "1" + module_name: lc_ctrl + lpg_name: secure_lc_io_div4_0 + lpg_idx: 4 + } + { + name: lc_ctrl_fatal_state_error + width: 1 + type: alert + async: "1" + module_name: lc_ctrl + lpg_name: secure_lc_io_div4_0 + lpg_idx: 4 + } + { + name: lc_ctrl_fatal_bus_integ_error + width: 1 + type: alert + async: "1" + module_name: lc_ctrl + lpg_name: secure_lc_io_div4_0 + lpg_idx: 4 + } + { + name: spi_host0_fatal_fault + width: 1 + type: alert + async: "1" + module_name: spi_host0 + lpg_name: peri_spi_host0_0 + lpg_idx: 5 + } + { + name: pwrmgr_aon_fatal_fault + width: 1 + type: alert + async: "1" + module_name: pwrmgr_aon + lpg_name: powerup_por_io_div4_Aon + lpg_idx: 6 + } + { + name: rstmgr_aon_fatal_fault + width: 1 + type: alert + async: "1" + module_name: rstmgr_aon + lpg_name: powerup_lc_io_div4_Aon + lpg_idx: 7 + } + { + name: rstmgr_aon_fatal_cnsty_fault + width: 1 + type: alert + async: "1" + module_name: rstmgr_aon + lpg_name: powerup_lc_io_div4_Aon + lpg_idx: 7 + } + { + name: clkmgr_aon_recov_fault + width: 1 + type: alert + async: "1" + module_name: clkmgr_aon + lpg_name: powerup_lc_io_div4_Aon + lpg_idx: 7 + } + { + name: clkmgr_aon_fatal_fault + width: 1 + type: alert + async: "1" + module_name: clkmgr_aon + lpg_name: powerup_lc_io_div4_Aon + lpg_idx: 7 + } + { + name: pinmux_aon_fatal_fault + width: 1 + type: alert + async: "1" + module_name: pinmux_aon + lpg_name: powerup_lc_io_div4_Aon + lpg_idx: 7 + } + { + name: aon_timer_aon_fatal_fault + width: 1 + type: alert + async: "1" + module_name: aon_timer_aon + lpg_name: timers_lc_io_div4_Aon + lpg_idx: 8 + } + { + name: sensor_ctrl_recov_alert + width: 1 + type: alert + async: "1" + module_name: sensor_ctrl + lpg_name: secure_lc_io_div4_Aon + lpg_idx: 10 + } + { + name: sensor_ctrl_fatal_alert + width: 1 + type: alert + async: "1" + module_name: sensor_ctrl + lpg_name: secure_lc_io_div4_Aon + lpg_idx: 10 + } + { + name: soc_proxy_fatal_alert_intg + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_0 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_1 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_2 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_3 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_4 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_5 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_6 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_7 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_8 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_9 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_10 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_11 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_12 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_13 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_14 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_15 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_16 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_17 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_18 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_19 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_20 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_21 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_22 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_fatal_alert_external_23 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_recov_alert_external_0 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_recov_alert_external_1 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_recov_alert_external_2 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: soc_proxy_recov_alert_external_3 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: sram_ctrl_ret_aon_fatal_error + width: 1 + type: alert + async: "1" + module_name: sram_ctrl_ret_aon + lpg_name: infra_lc_io_div4_Aon + lpg_idx: 12 + } + { + name: rv_dm_fatal_fault + width: 1 + type: alert + async: "1" + module_name: rv_dm + lpg_name: infra_sys_0 + lpg_idx: 13 + } + { + name: rv_plic_fatal_fault + width: 1 + type: alert + async: "1" + module_name: rv_plic + lpg_name: secure_lc_0 + lpg_idx: 14 + } + { + name: aes_recov_ctrl_update_err + width: 1 + type: alert + async: "1" + module_name: aes + lpg_name: aes_trans_lc_0 + lpg_idx: 15 + } + { + name: aes_fatal_fault + width: 1 + type: alert + async: "1" + module_name: aes + lpg_name: aes_trans_lc_0 + lpg_idx: 15 + } + { + name: hmac_fatal_fault + width: 1 + type: alert + async: "1" + module_name: hmac + lpg_name: hmac_trans_lc_0 + lpg_idx: 16 + } + { + name: kmac_recov_operation_err + width: 1 + type: alert + async: "1" + module_name: kmac + lpg_name: kmac_trans_lc_0 + lpg_idx: 17 + } + { + name: kmac_fatal_fault_err + width: 1 + type: alert + async: "1" + module_name: kmac + lpg_name: kmac_trans_lc_0 + lpg_idx: 17 + } + { + name: otbn_fatal + width: 1 + type: alert + async: "1" + module_name: otbn + lpg_name: otbn_trans_lc_0 + lpg_idx: 18 + } + { + name: otbn_recov + width: 1 + type: alert + async: "1" + module_name: otbn + lpg_name: otbn_trans_lc_0 + lpg_idx: 18 + } + { + name: keymgr_dpe_recov_operation_err + width: 1 + type: alert + async: "1" + module_name: keymgr_dpe + lpg_name: secure_lc_0 + lpg_idx: 14 + } + { + name: keymgr_dpe_fatal_fault_err + width: 1 + type: alert + async: "1" + module_name: keymgr_dpe + lpg_name: secure_lc_0 + lpg_idx: 14 + } + { + name: csrng_recov_alert + width: 1 + type: alert + async: "1" + module_name: csrng + lpg_name: secure_lc_0 + lpg_idx: 14 + } + { + name: csrng_fatal_alert + width: 1 + type: alert + async: "1" + module_name: csrng + lpg_name: secure_lc_0 + lpg_idx: 14 + } + { + name: edn0_recov_alert + width: 1 + type: alert + async: "1" + module_name: edn0 + lpg_name: secure_lc_0 + lpg_idx: 14 + } + { + name: edn0_fatal_alert + width: 1 + type: alert + async: "1" + module_name: edn0 + lpg_name: secure_lc_0 + lpg_idx: 14 + } + { + name: edn1_recov_alert + width: 1 + type: alert + async: "1" + module_name: edn1 + lpg_name: secure_lc_0 + lpg_idx: 14 + } + { + name: edn1_fatal_alert + width: 1 + type: alert + async: "1" + module_name: edn1 + lpg_name: secure_lc_0 + lpg_idx: 14 + } + { + name: sram_ctrl_main_fatal_error + width: 1 + type: alert + async: "1" + module_name: sram_ctrl_main + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: sram_ctrl_mbox_fatal_error + width: 1 + type: alert + async: "1" + module_name: sram_ctrl_mbox + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: rom_ctrl0_fatal + width: 1 + type: alert + async: "1" + module_name: rom_ctrl0 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: rom_ctrl1_fatal + width: 1 + type: alert + async: "1" + module_name: rom_ctrl1 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: dma_fatal_fault + width: 1 + type: alert + async: "1" + module_name: dma + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx0_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx0 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx0_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx0 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx1_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx1 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx1_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx1 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx2_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx2 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx2_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx2 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx3_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx3 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx3_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx3 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx4_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx4 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx4_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx4 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx5_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx5 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx5_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx5 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx6_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx6 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx6_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx6 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx_jtag_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx_jtag + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx_jtag_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx_jtag + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx_pcie0_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx_pcie0 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx_pcie0_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx_pcie0 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx_pcie1_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx_pcie1 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: mbx_pcie1_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx_pcie1 + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: rv_core_ibex_fatal_sw_err + width: 1 + type: alert + async: "1" + module_name: rv_core_ibex + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: rv_core_ibex_recov_sw_err + width: 1 + type: alert + async: "1" + module_name: rv_core_ibex + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: rv_core_ibex_fatal_hw_err + width: 1 + type: alert + async: "1" + module_name: rv_core_ibex + lpg_name: infra_lc_0 + lpg_idx: 11 + } + { + name: rv_core_ibex_recov_hw_err + width: 1 + type: alert + async: "1" + module_name: rv_core_ibex + lpg_name: infra_lc_0 + lpg_idx: 11 + } + ] + exported_rsts: {} + alert_lpgs: + [ + { + name: peri_lc_io_div4_0 + clock_group: + { + name: peri + src: top + sw_cg: yes + unique: no + clocks: + { + clk_io_div4_peri: io_div4 + clk_io_div2_peri: io_div2 + clk_aon_peri: aon + clk_usb_peri: usb + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_peri + reset_connection: + { + name: lc_io_div4 + domain: "0" + } + } + { + name: peri_spi_device_0 + clock_group: + { + name: peri + src: top + sw_cg: yes + unique: no + clocks: + { + clk_io_div4_peri: io_div4 + clk_io_div2_peri: io_div2 + clk_aon_peri: aon + clk_usb_peri: usb + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_peri + reset_connection: + { + name: spi_device + domain: "0" + } + } + { + name: peri_i2c0_0 + clock_group: + { + name: peri + src: top + sw_cg: yes + unique: no + clocks: + { + clk_io_div4_peri: io_div4 + clk_io_div2_peri: io_div2 + clk_aon_peri: aon + clk_usb_peri: usb + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_peri + reset_connection: + { + name: i2c0 + domain: "0" + } + } + { + name: timers_lc_io_div4_0 + clock_group: + { + name: timers + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_timers: io_div4 + clk_aon_timers: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_timers + reset_connection: + { + name: lc_io_div4 + domain: "0" + } + } + { + name: secure_lc_io_div4_0 + clock_group: + { + name: secure + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_secure: io_div4 + clk_main_secure: main + clk_aon_secure: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_secure + reset_connection: + { + name: lc_io_div4 + domain: "0" + } + } + { + name: peri_spi_host0_0 + clock_group: + { + name: peri + src: top + sw_cg: yes + unique: no + clocks: + { + clk_io_div4_peri: io_div4 + clk_io_div2_peri: io_div2 + clk_aon_peri: aon + clk_usb_peri: usb + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_peri + reset_connection: + { + name: spi_host0 + domain: "0" + } + } + { + name: powerup_por_io_div4_Aon + clock_group: + { + name: powerup + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_powerup: io_div4 + clk_aon_powerup: aon + clk_main_powerup: main + clk_io_powerup: io + clk_usb_powerup: usb + clk_io_div2_powerup: io_div2 + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_powerup + reset_connection: + { + name: por_io_div4 + domain: Aon + } + } + { + name: powerup_lc_io_div4_Aon + clock_group: + { + name: powerup + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_powerup: io_div4 + clk_aon_powerup: aon + clk_main_powerup: main + clk_io_powerup: io + clk_usb_powerup: usb + clk_io_div2_powerup: io_div2 + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_powerup + reset_connection: + { + name: lc_io_div4 + domain: Aon + } + } + { + name: timers_lc_io_div4_Aon + clock_group: + { + name: timers + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_timers: io_div4 + clk_aon_timers: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_timers + reset_connection: + { + name: lc_io_div4 + domain: Aon + } + } + { + name: infra_lc_io_div4_0 + clock_group: + { + name: infra + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_infra: io_div4 + clk_main_infra: main + clk_aon_infra: aon + clk_usb_infra: usb + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_infra + reset_connection: + { + name: lc_io_div4 + domain: "0" + } + } + { + name: secure_lc_io_div4_Aon + clock_group: + { + name: secure + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_secure: io_div4 + clk_main_secure: main + clk_aon_secure: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_secure + reset_connection: + { + name: lc_io_div4 + domain: Aon + } + } + { + name: infra_lc_0 + clock_group: + { + name: infra + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_infra: io_div4 + clk_main_infra: main + clk_aon_infra: aon + clk_usb_infra: usb + } + } + clock_connection: clkmgr_aon_clocks.clk_main_infra + reset_connection: + { + name: lc + domain: "0" + } + } + { + name: infra_lc_io_div4_Aon + clock_group: + { + name: infra + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_infra: io_div4 + clk_main_infra: main + clk_aon_infra: aon + clk_usb_infra: usb + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_infra + reset_connection: + { + name: lc_io_div4 + domain: Aon + } + } + { + name: infra_sys_0 + clock_group: + { + name: infra + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_infra: io_div4 + clk_main_infra: main + clk_aon_infra: aon + clk_usb_infra: usb + } + } + clock_connection: clkmgr_aon_clocks.clk_main_infra + reset_connection: + { + name: sys + domain: "0" + } + } + { + name: secure_lc_0 + clock_group: + { + name: secure + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_secure: io_div4 + clk_main_secure: main + clk_aon_secure: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_main_secure + reset_connection: + { + name: lc + domain: "0" + } + } + { + name: aes_trans_lc_0 + clock_group: + { + name: trans + src: top + sw_cg: hint + unique: yes + clocks: + { + clk_main_aes: main + clk_main_hmac: main + clk_main_kmac: main + clk_main_otbn: main + } + } + clock_connection: clkmgr_aon_clocks.clk_main_aes + reset_connection: + { + name: lc + domain: "0" + } + } + { + name: hmac_trans_lc_0 + clock_group: + { + name: trans + src: top + sw_cg: hint + unique: yes + clocks: + { + clk_main_aes: main + clk_main_hmac: main + clk_main_kmac: main + clk_main_otbn: main + } + } + clock_connection: clkmgr_aon_clocks.clk_main_hmac + reset_connection: + { + name: lc + domain: "0" + } + } + { + name: kmac_trans_lc_0 + clock_group: + { + name: trans + src: top + sw_cg: hint + unique: yes + clocks: + { + clk_main_aes: main + clk_main_hmac: main + clk_main_kmac: main + clk_main_otbn: main + } + } + clock_connection: clkmgr_aon_clocks.clk_main_kmac + reset_connection: + { + name: lc + domain: "0" + } + } + { + name: otbn_trans_lc_0 + clock_group: + { + name: trans + src: top + sw_cg: hint + unique: yes + clocks: + { + clk_main_aes: main + clk_main_hmac: main + clk_main_kmac: main + clk_main_otbn: main + } + } + clock_connection: clkmgr_aon_clocks.clk_main_otbn + reset_connection: + { + name: lc + domain: "0" + } + } + ] + inter_signal: + { + signals: + [ + { + name: lsio_trigger + desc: + ''' + Self-clearing status trigger for the DMA. + Set when RX or TX FIFOs are past their configured watermarks matching watermark interrupt behaviour. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: uart0 + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: uart0_lsio_trigger + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: uart0 + default: "" + end_idx: -1 + top_signame: uart0_tl + index: -1 + } + { + name: strap_en + desc: This signal is pulsed high by the power manager after reset in order to sample the HW straps. + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: gpio + package: "" + top_signame: pwrmgr_aon_strap + index: -1 + } + { + name: sampled_straps + desc: This vector contains the sampled strap values. + struct: gpio_straps + package: gpio_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: gpio + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: gpio + default: "" + end_idx: -1 + top_signame: gpio_tl + index: -1 + } + { + name: ram_cfg + struct: ram_2p_cfg + package: prim_ram_2p_pkg + type: uni + act: rcv + width: 1 + inst_name: spi_device + default: "" + top_signame: ast_spi_ram_2p_cfg + index: -1 + } + { + name: passthrough + struct: passthrough + package: spi_device_pkg + type: req_rsp + act: req + width: 1 + inst_name: spi_device + default: "" + end_idx: -1 + top_signame: spi_device_passthrough + index: -1 + } + { + name: mbist_en + struct: logic + type: uni + act: rcv + width: 1 + inst_name: spi_device + index: -1 + } + { + name: sck_monitor + struct: logic + type: uni + act: req + width: 1 + inst_name: spi_device + default: "" + package: "" + external: true + top_signame: sck_monitor + conn_type: false + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: spi_device + default: "" + end_idx: -1 + top_signame: spi_device_tl + index: -1 + } + { + name: ram_cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: lsio_trigger + desc: + ''' + Self-clearing status trigger for the DMA. + Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: i2c0 + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: i2c0_lsio_trigger + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: i2c0 + default: "" + end_idx: -1 + top_signame: i2c0_tl + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_timer + default: "" + end_idx: -1 + top_signame: rv_timer_tl + index: -1 + } + { + name: otp_ext_voltage_h + struct: "" + type: io + act: none + width: 1 + default: "'0" + inst_name: otp_ctrl + package: "" + external: true + top_signame: otp_ext_voltage_h + conn_type: false + index: -1 + } + { + name: otp_ast_pwr_seq + desc: Power sequencing signals to AST (VDD domain). + struct: otp_ast_req + package: otp_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + external: true + top_signame: otp_ctrl_otp_ast_pwr_seq + conn_type: false + index: -1 + } + { + name: otp_ast_pwr_seq_h + desc: Power sequencing signals coming from AST (VCC domain). + struct: otp_ast_rsp + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: otp_ctrl + external: true + top_signame: otp_ctrl_otp_ast_pwr_seq_h + conn_type: false + index: -1 + } + { + name: edn + desc: Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation. + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: otp_ctrl + default: "" + top_signame: edn0_edn + index: 1 + } + { + name: pwr_otp + desc: Initialization request/acknowledge from/to power manager. + struct: pwr_otp + package: pwrmgr_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: pwrmgr_aon_pwr_otp + index: -1 + } + { + name: lc_otp_vendor_test + desc: Vendor test control signals from/to the life cycle TAP. + struct: lc_otp_vendor_test + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_otp_vendor_test + index: -1 + } + { + name: lc_otp_program + desc: Life cycle state transition interface. + struct: lc_otp_program + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_otp_program + index: -1 + } + { + name: otp_lc_data + desc: + ''' + Life cycle state output holding the current life cycle state, + the value of the transition counter and the tokens needed for life cycle transitions. + ''' + struct: otp_lc_data + package: otp_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_type: broadcast + top_signame: otp_ctrl_otp_lc_data + index: -1 + } + { + name: lc_escalate_en + desc: + ''' + Life cycle escalation enable coming from life cycle controller. + This signal moves all FSMs within OTP into the error state. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_creator_seed_sw_rw_en + desc: + ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_creator_seed_sw_rw_en + index: -1 + } + { + name: lc_owner_seed_sw_rw_en + desc: + ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the OWNER_SEED. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_owner_seed_sw_rw_en + index: -1 + } + { + name: lc_seed_hw_rd_en + desc: + ''' + Seed read enable coming from life cycle controller. + This signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_seed_hw_rd_en + index: -1 + } + { + name: lc_dft_en + desc: + ''' + Test enable qualifier coming from life cycle controller. + This signals enables the TL-UL access port to the proprietary OTP IP. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_check_byp_en + desc: + ''' + Life cycle partition check bypass signal. + This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_check_byp_en + index: -1 + } + { + name: otp_keymgr_key + desc: Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + struct: otp_keymgr_key + package: otp_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_type: broadcast + top_signame: otp_ctrl_otp_keymgr_key + index: -1 + } + { + name: flash_otp_key + desc: Key derivation interface for FLASH scrambling. + struct: flash_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + index: -1 + } + { + name: sram_otp_key + desc: Array with key derivation interfaces for SRAM scrambling devices. + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 4 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_type: one-to-N + top_signame: otp_ctrl_sram_otp_key + index: -1 + } + { + name: otbn_otp_key + desc: Key derivation interface for OTBN scrambling devices. + struct: otbn_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_signame: otp_ctrl_otbn_otp_key + index: -1 + } + { + name: otp_broadcast + desc: Output of the HW partitions with breakout data types. + struct: otp_broadcast + package: otp_ctrl_part_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: otp_ctrl_otp_broadcast + index: -1 + } + { + name: obs_ctrl + desc: AST observability control signals. + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: otp_ctrl + default: "" + top_signame: ast_obs_ctrl + index: -1 + } + { + name: otp_obs + desc: AST observability bus. + struct: logic + type: uni + act: req + width: 8 + inst_name: otp_ctrl + default: "" + package: "" + external: true + top_signame: otp_obs + conn_type: false + index: -1 + } + { + name: core_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: otp_ctrl + default: "" + end_idx: -1 + top_signame: otp_ctrl_core_tl + index: -1 + } + { + name: prim_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: otp_ctrl + default: "" + end_idx: -1 + top_signame: otp_ctrl_prim_tl + index: -1 + } + { + name: jtag + struct: jtag + package: jtag_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + index: -1 + } + { + name: esc_scrap_state0_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_tx + index: 1 + } + { + name: esc_scrap_state0_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_rx + index: 1 + } + { + name: esc_scrap_state1_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_tx + index: 2 + } + { + name: esc_scrap_state1_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_rx + index: 2 + } + { + name: pwr_lc + struct: pwr_lc + package: pwrmgr_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: pwrmgr_aon_pwr_lc + index: -1 + } + { + name: lc_otp_vendor_test + struct: lc_otp_vendor_test + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + end_idx: -1 + top_signame: lc_ctrl_lc_otp_vendor_test + index: -1 + } + { + name: otp_lc_data + struct: otp_lc_data + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT + inst_name: lc_ctrl + top_signame: otp_ctrl_otp_lc_data + index: -1 + } + { + name: lc_otp_program + struct: lc_otp_program + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + end_idx: -1 + top_signame: lc_ctrl_lc_otp_program + index: -1 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + top_signame: kmac_app + index: 1 + } + { + name: lc_dft_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_nvm_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: lc_cpu_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_cpu_en + index: -1 + } + { + name: lc_keymgr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_keymgr_en + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_clk_byp_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_clk_byp_req + index: -1 + } + { + name: lc_clk_byp_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_clk_byp_ack + index: -1 + } + { + name: lc_flash_rma_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_flash_rma_req + index: -1 + } + { + name: lc_flash_rma_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 2 + default: lc_ctrl_pkg::On + inst_name: lc_ctrl + top_signame: otbn_lc_rma_ack + index: -1 + } + { + name: lc_flash_rma_seed + struct: lc_flash_rma_seed + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + index: -1 + } + { + name: lc_check_byp_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_check_byp_en + index: -1 + } + { + name: lc_creator_seed_sw_rw_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_creator_seed_sw_rw_en + index: -1 + } + { + name: lc_owner_seed_sw_rw_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_owner_seed_sw_rw_en + index: -1 + } + { + name: lc_iso_part_sw_rd_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_iso_part_sw_wr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_seed_hw_rd_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_seed_hw_rd_en + index: -1 + } + { + name: lc_keymgr_div + struct: lc_keymgr_div + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_keymgr_div + index: -1 + } + { + name: otp_device_id + struct: otp_device_id + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: lc_ctrl + top_signame: lc_ctrl_otp_device_id + index: -1 + } + { + name: otp_manuf_state + struct: otp_manuf_state + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: lc_ctrl + top_signame: lc_ctrl_otp_manuf_state + index: -1 + } + { + name: hw_rev + struct: lc_hw_rev + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + index: -1 + } + { + name: strap_en_override + desc: + ''' + This signal transitions from 0 -> 1 by the lc_ctrl manager after volatile RAW_UNLOCK in order to re-sample the HW straps. + The signal stays at 1 until reset. + Note that this is only used in test chips when SecVolatileRawUnlockEn = 1. + Otherwise this signal is tied off to 0. + ''' + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: lc_ctrl + package: "" + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_strap_en_override + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + default: "" + end_idx: -1 + top_signame: lc_ctrl_regs_tl + index: -1 + } + { + name: dmi_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + default: "" + end_idx: -1 + top_signame: lc_ctrl_dmi_tl + index: -1 + } + { + name: crashdump + struct: alert_crashdump + package: alert_pkg + type: uni + act: req + width: 1 + inst_name: alert_handler + default: "" + end_idx: -1 + top_type: broadcast + top_signame: alert_handler_crashdump + index: -1 + } + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: alert_handler + default: "" + top_signame: edn0_edn + index: 4 + } + { + name: esc_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: rcv + width: 4 + inst_name: alert_handler + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: alert_handler_esc_rx + index: -1 + } + { + name: esc_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: req + width: 4 + inst_name: alert_handler + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: alert_handler_esc_tx + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: alert_handler + default: "" + end_idx: -1 + top_signame: alert_handler_tl + index: -1 + } + { + name: passthrough + struct: passthrough + package: spi_device_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: spi_host0 + default: "" + top_signame: spi_device_passthrough + index: -1 + } + { + name: lsio_trigger + desc: + ''' + Self-clearing status trigger for the DMA. + Set when RX or TX FIFOs are past their configured watermarks matching watermark interrupt behaviour. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: spi_host0 + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: spi_host0_lsio_trigger + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: spi_host0 + default: "" + end_idx: -1 + top_signame: spi_host0_tl + index: -1 + } + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + index: -1 + } + { + name: pwr_ast + struct: pwr_ast + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + external: true + top_signame: pwrmgr_ast + conn_type: false + index: -1 + } + { + name: pwr_rst + struct: pwr_rst + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_rst + index: -1 + } + { + name: pwr_clk + struct: pwr_clk + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_clk + index: -1 + } + { + name: pwr_otp + struct: pwr_otp + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_otp + index: -1 + } + { + name: pwr_lc + struct: pwr_lc + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_lc + index: -1 + } + { + name: pwr_flash + struct: pwr_flash + package: pwrmgr_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + index: -1 + } + { + name: esc_rst_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: alert_handler_esc_tx + index: 3 + } + { + name: esc_rst_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: alert_handler_esc_rx + index: 3 + } + { + name: pwr_cpu + struct: pwr_cpu + package: pwrmgr_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: rv_core_ibex_pwrmgr + index: -1 + } + { + name: wakeups + struct: logic + type: uni + act: rcv + width: 6 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: one-to-N + top_signame: pwrmgr_aon_wakeups + index: -1 + } + { + name: rstreqs + struct: logic + type: uni + act: rcv + width: 2 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: one-to-N + top_signame: pwrmgr_aon_rstreqs + index: -1 + } + { + name: ndmreset_req + struct: logic + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + package: "" + top_signame: rv_dm_ndmreset_req + index: -1 + } + { + name: strap + struct: logic + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_strap + index: -1 + } + { + name: low_power + struct: logic + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_low_power + index: -1 + } + { + name: rom_ctrl + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_rom_ctrl + index: -1 + } + { + name: fetch_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_fetch_en + index: -1 + } + { + name: lc_dft_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: sw_rst_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: rstmgr_aon_sw_rst_req + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_tl + index: -1 + } + { + name: por_n + desc: + ''' + Root power on reset signals from ast. + There is one root reset signal for each core power domain. + ''' + struct: logic + type: uni + act: rcv + width: 2 + inst_name: rstmgr_aon + default: "" + package: "" + external: true + top_signame: por_n + conn_type: false + index: -1 + } + { + name: pwr + desc: + ''' + Reset request signals from power manager. + Power manager can request for specific domains of the lc/sys reset tree to assert. + ''' + struct: pwr_rst + type: req_rsp + act: rsp + width: 1 + inst_name: rstmgr_aon + default: "" + package: pwrmgr_pkg + top_signame: pwrmgr_aon_pwr_rst + index: -1 + } + { + name: resets + desc: Leaf resets fed to the system. + struct: rstmgr_out + package: rstmgr_pkg + type: uni + act: req + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: rstmgr_aon_resets + index: -1 + } + { + name: rst_en + desc: Low-power-group outputs used by alert handler. + struct: rstmgr_rst_en + package: rstmgr_pkg + type: uni + act: req + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: rstmgr_aon_rst_en + index: -1 + } + { + name: alert_dump + desc: Alert handler crash dump information. + struct: alert_crashdump + package: alert_pkg + type: uni + act: rcv + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: alert_handler_crashdump + index: -1 + } + { + name: cpu_dump + desc: Main processing element crash dump information. + struct: cpu_crash_dump + package: rv_core_ibex_pkg + type: uni + act: rcv + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: rv_core_ibex_crash_dump + index: -1 + } + { + name: sw_rst_req + desc: Software requested system reset to pwrmgr. + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: rstmgr_aon + default: "" + end_idx: -1 + top_type: broadcast + top_signame: rstmgr_aon_sw_rst_req + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rstmgr_aon + default: "" + end_idx: -1 + top_signame: rstmgr_aon_tl + index: -1 + } + { + name: clocks + struct: clkmgr_out + package: clkmgr_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: clkmgr_aon_clocks + index: -1 + } + { + name: cg_en + struct: clkmgr_cg_en + package: clkmgr_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: clkmgr_aon_cg_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: io_clk_byp_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: io_clk_byp_req + conn_type: false + index: -1 + } + { + name: io_clk_byp_ack + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: io_clk_byp_ack + conn_type: false + index: -1 + } + { + name: all_clk_byp_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: all_clk_byp_req + conn_type: false + index: -1 + } + { + name: all_clk_byp_ack + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: all_clk_byp_ack + conn_type: false + index: -1 + } + { + name: hi_speed_sel + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: hi_speed_sel + conn_type: false + index: -1 + } + { + name: div_step_down_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: div_step_down_req + conn_type: false + index: -1 + } + { + name: lc_clk_byp_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: lc_ctrl_lc_clk_byp_req + index: -1 + } + { + name: lc_clk_byp_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: lc_ctrl_lc_clk_byp_ack + index: -1 + } + { + name: jitter_en + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: clk_main_jitter_en + conn_type: false + index: -1 + } + { + name: pwr + struct: pwr_clk + type: req_rsp + act: rsp + width: 1 + inst_name: clkmgr_aon + default: "" + package: pwrmgr_pkg + top_signame: pwrmgr_aon_pwr_clk + index: -1 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 4 + inst_name: clkmgr_aon + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: clkmgr_aon_idle + index: -1 + } + { + name: calib_rdy + desc: Indicates clocks are calibrated and frequencies accurate + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi4True + inst_name: clkmgr_aon + external: true + top_signame: calib_rdy + conn_type: false + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: clkmgr_aon + default: "" + end_idx: -1 + top_signame: clkmgr_aon_tl + index: -1 + } + { + name: lc_hw_debug_en + desc: Debug enable qualifier coming from life cycle controller, used for HW strap qualification. + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: pinmux_aon + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: lc_dft_en + desc: Test enable qualifier coming from life cycle controller, used for HW strap qualification. + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: pinmux_aon + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_escalate_en + desc: + ''' + Escalation enable signal coming from life cycle controller, used for invalidating + the latched lc_hw_debug_en state inside the strap sampling logic. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: pinmux_aon + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_check_byp_en + desc: + ''' + Check bypass enable signal coming from life cycle controller, used for invalidating + the latched lc_hw_debug_en state inside the strap sampling logic. This signal is asserted + whenever the life cycle controller performs a life cycle transition. Its main use is + to skip any background checks inside the life cycle partition of the OTP controller while + a life cycle transition is in progress. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: pinmux_aon + top_signame: lc_ctrl_lc_check_byp_en + index: -1 + } + { + name: pinmux_hw_debug_en + desc: + ''' + This is the latched version of lc_hw_debug_en_i. We use it exclusively to gate the JTAG + signals and TAP side of the RV_DM so that RV_DM can remain live during an NDM reset cycle. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: pinmux_aon + index: -1 + } + { + name: lc_jtag + desc: Qualified JTAG signals for life cycle controller TAP. + struct: jtag + package: jtag_pkg + type: req_rsp + act: req + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: rv_jtag + desc: Qualified JTAG signals for RISC-V processor TAP. + struct: jtag + package: jtag_pkg + type: req_rsp + act: req + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: dft_jtag + desc: Qualified JTAG signals for DFT TAP. + struct: jtag + package: jtag_pkg + type: req_rsp + act: req + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: dft_strap_test + desc: Sampled DFT strap values, going to the DFT TAP. + struct: dft_strap_test_req + package: pinmux_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: pinmux_aon + external: true + top_signame: dft_strap_test + conn_type: false + index: -1 + } + { + name: dft_hold_tap_sel + desc: TAP selection hold indication, asserted by the DFT TAP during boundary scan. + struct: logic + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: pinmux_aon + package: "" + external: true + top_signame: dft_hold_tap_sel + conn_type: false + index: -1 + } + { + name: sleep_en + desc: Level signal that is asserted when the power manager enters sleep. + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: pwrmgr_aon_low_power + index: -1 + } + { + name: strap_en + desc: This signal is pulsed high by the power manager after reset in order to sample the HW straps. + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: pwrmgr_aon_strap + index: -1 + } + { + name: strap_en_override + desc: + ''' + This signal transitions from 0 -> 1 by the lc_ctrl manager after volatile RAW_UNLOCK in order to re-sample the HW straps. + The signal must stay at 1 until reset. + Note that this is only used in test chips when SecVolatileRawUnlockEn = 1. + Otherwise this signal is unused. + ''' + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: lc_ctrl_strap_en_override + index: -1 + } + { + name: pin_wkup_req + desc: Wakeup request from wakeup detectors, to the power manager, running on the AON clock. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: pwrmgr_aon_wakeups + index: 0 + } + { + name: usbdev_dppullup_en + desc: Pullup enable signal coming from the USB IP. + struct: logic + type: uni + act: rcv + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: usbdev_dnpullup_en + desc: Pullup enable signal coming from the USB IP. + struct: logic + type: uni + act: rcv + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: usb_dppullup_en + desc: " Pullup enable signal going to USB PHY, needs to be maintained in low-power mode." + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + index: -1 + } + { + name: usb_dnpullup_en + desc: Pullup enable signal going to USB PHY, needs to be maintained in low-power mode. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + index: -1 + } + { + name: usb_wkup_req + desc: Wakeup request from USB wakeup detector, going to the power manager, running on the AON clock. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: pwrmgr_aon_wakeups + index: 1 + } + { + name: usbdev_suspend_req + desc: Indicates whether USB is in suspended state, coming from the USB device. + struct: logic + type: uni + act: rcv + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: usbdev_wake_ack + desc: Acknowledges the USB wakeup request, coming from the USB device. + struct: logic + type: uni + act: rcv + width: 1 + inst_name: pinmux_aon + index: -1 + } + { + name: usbdev_bus_not_idle + desc: Event signal that indicates that the USB was not idle while monitoring. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + index: -1 + } + { + name: usbdev_bus_reset + desc: Event signal that indicates that the USB issued a Bus Reset while monitoring. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + index: -1 + } + { + name: usbdev_sense_lost + desc: Event signal that indicates that USB SENSE signal was lost while monitoring. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + index: -1 + } + { + name: usbdev_wake_detect_active + desc: State debug information. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: pinmux_aon + default: "" + end_idx: -1 + top_signame: pinmux_aon_tl + index: -1 + } + { + name: nmi_wdog_timer_bark + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: aon_timer_aon + package: "" + end_idx: -1 + top_type: broadcast + top_signame: aon_timer_aon_nmi_wdog_timer_bark + index: -1 + } + { + name: wkup_req + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: aon_timer_aon + package: "" + top_signame: pwrmgr_aon_wakeups + index: 2 + } + { + name: aon_timer_rst_req + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: aon_timer_aon + package: "" + top_signame: pwrmgr_aon_rstreqs + index: 0 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: aon_timer_aon + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: sleep_mode + struct: logic + type: uni + act: rcv + width: 1 + inst_name: aon_timer_aon + default: "" + package: "" + top_signame: pwrmgr_aon_low_power + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: aon_timer_aon + default: "" + end_idx: -1 + top_signame: aon_timer_aon_tl + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: ast + index: -1 + } + { + name: ast_alert + struct: ast_alert + package: ast_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sensor_ctrl + default: "" + external: true + top_signame: sensor_ctrl_ast_alert + conn_type: false + index: -1 + } + { + name: ast_status + struct: ast_status + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: sensor_ctrl + default: "" + external: true + top_signame: sensor_ctrl_ast_status + conn_type: false + index: -1 + } + { + name: ast_init_done + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi4True + inst_name: sensor_ctrl + external: true + top_signame: ast_init_done + conn_type: false + index: -1 + } + { + name: wkup_req + struct: logic + type: uni + act: req + width: 1 + inst_name: sensor_ctrl + default: "" + package: "" + top_signame: pwrmgr_aon_wakeups + index: 3 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sensor_ctrl + default: "" + end_idx: -1 + top_signame: sensor_ctrl_tl + index: -1 + } + { + name: wkup_internal_req + struct: logic + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: pwrmgr_aon_wakeups + index: 4 + } + { + name: wkup_external_req + struct: logic + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: pwrmgr_aon_wakeups + index: 5 + } + { + name: rst_req_external + struct: logic + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: pwrmgr_aon_rstreqs + index: 1 + } + { + name: ctn_tl_h2d + desc: TL-UL host port for egress into CTN (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + external: true + top_signame: ctn_tl_h2d + conn_type: false + index: -1 + } + { + name: ctn_tl_d2h + desc: TL-UL host port for egress into CTN (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + external: true + top_signame: ctn_tl_d2h + conn_type: false + index: -1 + } + { + name: i2c_lsio_trigger + desc: LSIO trigger signal from I2C + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: i2c0_lsio_trigger + index: -1 + } + { + name: spi_host_lsio_trigger + desc: LSIO trigger signal from SPI Host + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: spi_host0_lsio_trigger + index: -1 + } + { + name: uart_lsio_trigger + desc: LSIO trigger signal from UART + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: uart0_lsio_trigger + index: -1 + } + { + name: soc_lsio_trigger + desc: LSIO trigger signal from SoC, synchronous + struct: logic + type: uni + act: rcv + width: 8 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_lsio_trigger + conn_type: false + index: -1 + } + { + name: dma_lsio_trigger + desc: Collated synchronous LSIO trigger signals for DMA + struct: lsio_trigger + package: dma_pkg + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + top_signame: dma_lsio_trigger + index: -1 + } + { + name: soc_fatal_alert + desc: Differential fatal alert from SoC, synchronous + struct: soc_alert + package: soc_proxy_pkg + type: req_rsp + act: rsp + width: 24 + inst_name: soc_proxy + default: "" + external: true + top_signame: soc_fatal_alert + conn_type: false + index: -1 + } + { + name: soc_recov_alert + desc: Differential recoverable alert from SoC, synchronous + struct: soc_alert + package: soc_proxy_pkg + type: req_rsp + act: rsp + width: 4 + inst_name: soc_proxy + default: "" + external: true + top_signame: soc_recov_alert + conn_type: false + index: -1 + } + { + name: soc_wkup_async + desc: Wakeup request from SoC, asynchronous, level-encoded + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_wkup_async + conn_type: false + index: -1 + } + { + name: soc_rst_req_async + desc: Reset request from SoC, asynchronous, level-encoded + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_rst_req_async + conn_type: false + index: -1 + } + { + name: soc_intr_async + desc: Interrupt request from SoC, asynchronous, level-encoded + struct: logic + type: uni + act: rcv + width: 32 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_intr_async + conn_type: false + index: -1 + } + { + name: soc_gpi_async + desc: GPI from SoC, async + struct: logic + type: uni + act: req + width: 16 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_gpi_async + conn_type: false + index: -1 + } + { + name: soc_gpo_async + desc: GPO from SoC, async + struct: logic + type: uni + act: rcv + width: 16 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_gpo_async + conn_type: false + index: -1 + } + { + name: core_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_signame: soc_proxy_core_tl + index: -1 + } + { + name: ctn_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_signame: soc_proxy_ctn_tl + index: -1 + } + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_ret_aon + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 1 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: sram_ctrl_ret_aon + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_ret_aon + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_ret_aon + default: "" + end_idx: -1 + top_signame: sram_ctrl_ret_aon_regs_tl + index: -1 + } + { + name: ram_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_ret_aon + default: "" + end_idx: -1 + top_signame: sram_ctrl_ret_aon_ram_tl + index: -1 + } + { + name: next_dm_addr + desc: + ''' + 32bit word address of the next debug module. + Set to 0x0 if this is the last debug module in the chain. + ''' + struct: next_dm_addr + package: rv_dm_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: rv_dm + external: true + top_signame: rv_dm_next_dm_addr + conn_type: false + index: -1 + } + { + name: jtag + desc: JTAG signals for the RISC-V TAP. + struct: jtag + package: jtag_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + index: -1 + } + { + name: lc_hw_debug_en + desc: + ''' + Multibit life cycle hardware debug enable signal coming from life cycle controller, + asserted when the hardware debug mechanisms are enabled in the system. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: rv_dm + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: lc_dft_en + desc: + ''' + Multibit life cycle hardware debug enable signal coming from life cycle controller, + asserted when the DFT mechanisms are enabled in the system. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: rv_dm + index: -1 + } + { + name: pinmux_hw_debug_en + desc: + ''' + Multibit life cycle hardware debug enable signal coming from pinmux. + This is a latched version of the lc_hw_debug_en signal and is only used to + gate the JTAG / TAP side of the RV_DM. It is used to keep a debug session live + while the rest of the system undergoes an NDM reset. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: rv_dm + index: -1 + } + { + name: otp_dis_rv_dm_late_debug + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: rv_dm + index: -1 + } + { + name: unavailable + desc: + ''' + This signal indicates to the debug module that the main processor is not available + for debug (e.g. due to a low-power state). + ''' + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: rv_dm + index: -1 + } + { + name: ndmreset_req + desc: Non-debug module reset request going to the system reset infrastructure. + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_dm + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_dm_ndmreset_req + index: -1 + } + { + name: dmactive + desc: + ''' + This signal indicates whether the debug module is active and can be used to prevent + power down of the core and bus-attached peripherals. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_dm + index: -1 + } + { + name: debug_req + desc: This is the debug request interrupt going to the main processor. + struct: logic [rv_dm_reg_pkg::NrHarts-1:0] + type: uni + act: req + width: 1 + inst_name: rv_dm + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_dm_debug_req + index: -1 + } + { + name: lc_escalate_en + desc: + ''' + Escalation enable signal coming from life cycle controller, used for invalidating + the latched lc_hw_debug_en state inside the strap sampling logic. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: rv_dm + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_check_byp_en + desc: + ''' + Check bypass enable signal coming from life cycle controller, used for invalidating + the latched lc_hw_debug_en state inside the strap sampling logic. This signal is asserted + whenever the life cycle controller performs a life cycle transition. Its main use is + to skip any background checks inside the life cycle partition of the OTP controller while + a life cycle transition is in progress. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: rv_dm + top_signame: lc_ctrl_lc_check_byp_en + index: -1 + } + { + name: strap_en + desc: This signal is pulsed high by the power manager after reset in order to sample the HW straps. + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: rv_dm + package: "" + top_signame: pwrmgr_aon_strap + index: -1 + } + { + name: strap_en_override + desc: + ''' + This signal transitions from 0 -> 1 by the lc_ctrl manager after volatile RAW_UNLOCK in order to re-sample the HW straps. + The signal must stay at 1 until reset. + Note that this is only used in test chips when SecVolatileRawUnlockEn = 1. + Otherwise this signal is unused. + ''' + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: rv_dm + package: "" + top_signame: lc_ctrl_strap_en_override + index: -1 + } + { + name: sba_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_dm + default: "" + top_signame: main_tl_rv_dm__sba + index: -1 + } + { + name: regs_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_regs_tl_d + index: -1 + } + { + name: mem_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_mem_tl_d + index: -1 + } + { + name: dbg_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_dbg_tl_d + index: -1 + } + { + name: irq + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_plic_irq + index: -1 + } + { + name: irq_id + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + index: -1 + } + { + name: msip + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_plic_msip + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_plic + default: "" + end_idx: -1 + top_signame: rv_plic_tl + index: -1 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: aes + default: "" + top_signame: clkmgr_aon_idle + index: 0 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: aes + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: aes + default: "" + top_signame: edn0_edn + index: 5 + } + { + name: keymgr_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: aes + default: "" + top_signame: keymgr_dpe_aes_key + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: aes + default: "" + end_idx: -1 + top_signame: aes_tl + index: -1 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: hmac + default: "" + top_signame: clkmgr_aon_idle + index: 1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: hmac + default: "" + end_idx: -1 + top_signame: hmac_tl + index: -1 + } + { + name: keymgr_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: kmac + default: "" + top_signame: keymgr_dpe_kmac_key + index: -1 + } + { + name: app + struct: app + package: kmac_pkg + type: req_rsp + act: rsp + width: + { + name: NumAppIntf + desc: Number of application interfaces + param_type: int + unpacked_dimensions: null + default: 3 + local: false + expose: true + name_top: KmacNumAppIntf + } + inst_name: kmac + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: kmac_app + index: -1 + } + { + name: entropy + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: kmac + default: "" + top_signame: edn0_edn + index: 3 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: kmac + default: "" + top_signame: clkmgr_aon_idle + index: 2 + } + { + name: en_masking + struct: logic + type: uni + act: req + width: 1 + inst_name: kmac + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: kmac_en_masking + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: kmac + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: kmac + default: "" + end_idx: -1 + top_signame: kmac_tl + index: -1 + } + { + name: otbn_otp_key + struct: otbn_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: otbn + top_signame: otp_ctrl_otbn_otp_key + index: -1 + } + { + name: edn_rnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: otbn + default: "" + top_signame: edn1_edn + index: 0 + } + { + name: edn_urnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: otbn + default: "" + top_signame: edn0_edn + index: 6 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: otbn + default: "" + top_signame: clkmgr_aon_idle + index: 3 + } + { + name: ram_cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: otbn + default: "" + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otbn + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_rma_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otbn + top_signame: lc_ctrl_lc_flash_rma_req + index: -1 + } + { + name: lc_rma_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otbn + end_idx: -1 + top_type: broadcast + top_signame: otbn_lc_rma_ack + index: -1 + } + { + name: keymgr_key + struct: otbn_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: otbn + default: "" + top_signame: keymgr_dpe_otbn_key + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: otbn + default: "" + end_idx: -1 + top_signame: otbn_tl + index: -1 + } + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: edn0_edn + index: 0 + } + { + name: aes_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_type: broadcast + top_signame: keymgr_dpe_aes_key + index: -1 + } + { + name: kmac_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_type: broadcast + top_signame: keymgr_dpe_kmac_key + index: -1 + } + { + name: otbn_key + struct: otbn_key_req + package: keymgr_pkg + type: uni + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_type: broadcast + top_signame: keymgr_dpe_otbn_key + index: -1 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: kmac_app + index: 0 + } + { + name: otp_key + struct: otp_keymgr_key + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: otp_ctrl_otp_keymgr_key + index: -1 + } + { + name: otp_device_id + struct: otp_device_id + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: keymgr_dpe_otp_device_id + index: -1 + } + { + name: lc_keymgr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::On + inst_name: keymgr_dpe + top_signame: lc_ctrl_lc_keymgr_en + index: -1 + } + { + name: lc_keymgr_div + struct: lc_keymgr_div + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: lc_ctrl_lc_keymgr_div + index: -1 + } + { + name: rom_digest + struct: keymgr_data + package: rom_ctrl_pkg + type: uni + act: rcv + width: 2 + default: rom_ctrl_pkg::KEYMGR_DATA_DEFAULT + inst_name: keymgr_dpe + end_idx: -1 + top_type: one-to-N + top_signame: keymgr_dpe_rom_digest + index: -1 + } + { + name: kmac_en_masking + struct: logic + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + package: "" + top_signame: kmac_en_masking + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_signame: keymgr_dpe_tl + index: -1 + } + { + name: csrng_cmd + struct: csrng + package: csrng_pkg + type: req_rsp + act: rsp + width: 2 + inst_name: csrng + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: csrng_csrng_cmd + index: -1 + } + { + name: entropy_src_hw_if + struct: entropy_src_hw_if + package: entropy_src_pkg + type: req_rsp + act: req + width: 1 + inst_name: csrng + default: "" + external: true + top_signame: entropy_src_hw_if + conn_type: false + index: -1 + } + { + name: cs_aes_halt + desc: + ''' + Coordinate activity between CSRNG's AES and Entropy Source's SHA3. + When CSRNG gets a request and its AES is not active, it acknowledges and until the request has dropped neither runs its AES nor drops the acknowledge. + ''' + struct: cs_aes_halt + package: entropy_src_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: csrng + index: -1 + } + { + name: otp_en_csrng_sw_app_read + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8True + inst_name: csrng + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: csrng + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: csrng + default: "" + end_idx: -1 + top_signame: csrng_tl + index: -1 + } + { + name: csrng_cmd + desc: EDN supports a signal CSRNG application interface. + struct: csrng + package: csrng_pkg + type: req_rsp + act: req + width: 1 + inst_name: edn0 + default: "" + top_signame: csrng_csrng_cmd + index: 0 + } + { + name: edn + desc: + ''' + The collection of peripheral ports supported by edn. The width (4) + indicates the number of peripheral ports on a single instance. + Due to limitations in the parametrization of top-level interconnects + this value is not currently parameterizable. However, the number + of peripheral ports may change in a future revision. + ''' + struct: edn + package: edn_pkg + type: req_rsp + act: rsp + width: 8 + default: "'0" + inst_name: edn0 + end_idx: -1 + top_type: one-to-N + top_signame: edn0_edn + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: edn0 + default: "" + end_idx: -1 + top_signame: edn0_tl + index: -1 + } + { + name: csrng_cmd + desc: EDN supports a signal CSRNG application interface. + struct: csrng + package: csrng_pkg + type: req_rsp + act: req + width: 1 + inst_name: edn1 + default: "" + top_signame: csrng_csrng_cmd + index: 1 + } + { + name: edn + desc: + ''' + The collection of peripheral ports supported by edn. The width (4) + indicates the number of peripheral ports on a single instance. + Due to limitations in the parametrization of top-level interconnects + this value is not currently parameterizable. However, the number + of peripheral ports may change in a future revision. + ''' + struct: edn + package: edn_pkg + type: req_rsp + act: rsp + width: 8 + default: "'0" + inst_name: edn1 + end_idx: 1 + top_type: partial-one-to-N + top_signame: edn1_edn + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: edn1 + default: "" + end_idx: -1 + top_signame: edn1_tl + index: -1 + } + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_main + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 0 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: sram_ctrl_main + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_main + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_main + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_main + top_signame: sram_ctrl_main_otp_en_sram_ifetch + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_main + default: "" + end_idx: -1 + top_signame: sram_ctrl_main_regs_tl + index: -1 + } + { + name: ram_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_main + default: "" + end_idx: -1 + top_signame: sram_ctrl_main_ram_tl + index: -1 + } + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_mbox + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 2 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: sram_ctrl_mbox + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_mbox + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_mbox + default: "" + end_idx: -1 + top_signame: sram_ctrl_mbox_regs_tl + index: -1 + } + { + name: ram_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_mbox + default: "" + end_idx: -1 + top_signame: sram_ctrl_mbox_ram_tl + index: -1 + } + { + name: rom_cfg + struct: rom_cfg + package: prim_rom_pkg + type: uni + act: rcv + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: ast_rom_cfg + index: -1 + } + { + name: pwrmgr_data + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: pwrmgr_aon_rom_ctrl + index: -1 + } + { + name: keymgr_data + struct: keymgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: keymgr_dpe_rom_digest + index: 0 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: kmac_app + index: 2 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl0 + default: "" + end_idx: -1 + top_signame: rom_ctrl0_regs_tl + index: -1 + } + { + name: rom_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl0 + default: "" + end_idx: -1 + top_signame: rom_ctrl0_rom_tl + index: -1 + } + { + name: rom_cfg + struct: rom_cfg + package: prim_rom_pkg + type: uni + act: rcv + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: ast_rom_cfg + index: -1 + } + { + name: pwrmgr_data + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: pwrmgr_aon_rom_ctrl + index: -1 + } + { + name: keymgr_data + struct: keymgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: keymgr_dpe_rom_digest + index: 1 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: kmac_app + index: 3 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl1 + default: "" + end_idx: -1 + top_signame: rom_ctrl1_regs_tl + index: -1 + } + { + name: rom_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl1 + default: "" + end_idx: -1 + top_signame: rom_ctrl1_rom_tl + index: -1 + } + { + name: lsio_trigger + struct: lsio_trigger + package: dma_pkg + type: uni + act: rcv + width: 1 + inst_name: dma + default: "" + end_idx: -1 + top_type: broadcast + top_signame: dma_lsio_trigger + index: -1 + } + { + name: sys + struct: sys + package: dma_pkg + type: req_rsp + act: req + width: 1 + inst_name: dma + default: "" + external: true + top_signame: dma_sys + conn_type: false + index: -1 + } + { + name: ctn_tl_h2d + desc: TL-UL host port for egress into CTN (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: dma + default: "" + external: true + top_signame: dma_ctn_tl_h2d + conn_type: false + index: -1 + } + { + name: ctn_tl_d2h + desc: TL-UL host port for egress into CTN (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: dma + default: "" + external: true + top_signame: dma_ctn_tl_d2h + conn_type: false + index: -1 + } + { + name: host_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: dma + default: "" + top_signame: main_tl_dma__host + index: -1 + } + { + name: tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: dma + default: "" + end_idx: -1 + top_signame: dma_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx0 + default: "" + top_signame: main_tl_mbx0__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx0 + default: "" + end_idx: -1 + top_signame: mbx0_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx0 + default: "" + end_idx: -1 + top_signame: mbx0_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx1 + default: "" + top_signame: main_tl_mbx1__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx1 + default: "" + end_idx: -1 + top_signame: mbx1_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx1 + default: "" + end_idx: -1 + top_signame: mbx1_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx2 + default: "" + top_signame: main_tl_mbx2__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx2 + default: "" + end_idx: -1 + top_signame: mbx2_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx2 + default: "" + end_idx: -1 + top_signame: mbx2_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx3 + default: "" + top_signame: main_tl_mbx3__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx3 + default: "" + end_idx: -1 + top_signame: mbx3_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx3 + default: "" + end_idx: -1 + top_signame: mbx3_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx4 + default: "" + top_signame: main_tl_mbx4__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx4 + default: "" + end_idx: -1 + top_signame: mbx4_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx4 + default: "" + end_idx: -1 + top_signame: mbx4_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx5 + default: "" + top_signame: main_tl_mbx5__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx5 + default: "" + end_idx: -1 + top_signame: mbx5_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx5 + default: "" + end_idx: -1 + top_signame: mbx5_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx6 + default: "" + top_signame: main_tl_mbx6__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx6 + default: "" + end_idx: -1 + top_signame: mbx6_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx6 + default: "" + end_idx: -1 + top_signame: mbx6_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx_jtag + default: "" + top_signame: main_tl_mbx_jtag__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_jtag + default: "" + end_idx: -1 + top_signame: mbx_jtag_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_jtag + default: "" + end_idx: -1 + top_signame: mbx_jtag_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx_pcie0 + default: "" + top_signame: main_tl_mbx_pcie0__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie0 + default: "" + end_idx: -1 + top_signame: mbx_pcie0_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie0 + default: "" + end_idx: -1 + top_signame: mbx_pcie0_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx_pcie1 + default: "" + top_signame: main_tl_mbx_pcie1__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie1 + default: "" + end_idx: -1 + top_signame: mbx_pcie1_core_tl_d + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie1 + default: "" + end_idx: -1 + top_signame: mbx_pcie1_soc_tl_d + index: -1 + } + { + name: rst_cpu_n + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_core_ibex + index: -1 + } + { + name: ram_cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: ast_ram_1p_cfg + index: -1 + } + { + name: hart_id + struct: logic + type: uni + act: rcv + width: 32 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: rv_core_ibex_hart_id + index: -1 + } + { + name: boot_addr + struct: logic + type: uni + act: rcv + width: 32 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: rv_core_ibex_boot_addr + index: -1 + } + { + name: irq_software + struct: logic + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: rv_plic_msip + index: -1 + } + { + name: irq_timer + struct: logic + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: rv_core_ibex_irq_timer + index: -1 + } + { + name: irq_external + struct: logic + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: rv_plic_irq + index: -1 + } + { + name: esc_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: alert_handler_esc_tx + index: 0 + } + { + name: esc_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: alert_handler_esc_rx + index: 0 + } + { + name: debug_req + struct: logic + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: rv_dm_debug_req + index: -1 + } + { + name: crash_dump + struct: cpu_crash_dump + package: rv_core_ibex_pkg + type: uni + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_core_ibex_crash_dump + index: -1 + } + { + name: lc_cpu_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: lc_ctrl_lc_cpu_en + index: -1 + } + { + name: pwrmgr_cpu_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: pwrmgr_aon_fetch_en + index: -1 + } + { + name: pwrmgr + struct: pwr_cpu + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_core_ibex_pwrmgr + index: -1 + } + { + name: nmi_wdog + struct: logic + type: uni + act: rcv + width: 1 + inst_name: rv_core_ibex + default: "" + package: "" + top_signame: aon_timer_aon_nmi_wdog_timer_bark + index: -1 + } + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: edn0_edn + index: 7 + } + { + name: icache_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 3 + } + { + name: fpga_info + struct: logic + type: uni + act: rcv + width: 32 + inst_name: rv_core_ibex + default: "" + package: "" + external: true + top_signame: fpga_info + conn_type: false + index: -1 + } + { + name: corei_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: main_tl_rv_core_ibex__corei + index: -1 + } + { + name: cored_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_core_ibex + default: "" + top_signame: main_tl_rv_core_ibex__cored + index: -1 + } + { + name: cfg_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_core_ibex + default: "" + end_idx: -1 + top_signame: rv_core_ibex_cfg_tl_d + index: -1 + } + { + name: tl_rv_core_ibex__corei + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_rv_core_ibex__corei + index: -1 + } + { + name: tl_rv_core_ibex__cored + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_rv_core_ibex__cored + index: -1 + } + { + name: tl_rv_dm__sba + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_rv_dm__sba + index: -1 + } + { + name: tl_dma__host + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_dma__host + index: -1 + } + { + name: tl_mbx0__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx0__sram + index: -1 + } + { + name: tl_mbx1__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx1__sram + index: -1 + } + { + name: tl_mbx2__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx2__sram + index: -1 + } + { + name: tl_mbx3__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx3__sram + index: -1 + } + { + name: tl_mbx4__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx4__sram + index: -1 + } + { + name: tl_mbx5__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx5__sram + index: -1 + } + { + name: tl_mbx6__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx6__sram + index: -1 + } + { + name: tl_mbx_jtag__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx_jtag__sram + index: -1 + } + { + name: tl_mbx_pcie0__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx_pcie0__sram + index: -1 + } + { + name: tl_mbx_pcie1__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_mbx_pcie1__sram + index: -1 + } + { + name: tl_rv_dm__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rv_dm_regs_tl_d + index: -1 + } + { + name: tl_rv_dm__mem + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rv_dm_mem_tl_d + index: -1 + } + { + name: tl_rom_ctrl0__rom + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rom_ctrl0_rom_tl + index: -1 + } + { + name: tl_rom_ctrl0__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rom_ctrl0_regs_tl + index: -1 + } + { + name: tl_rom_ctrl1__rom + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rom_ctrl1_rom_tl + index: -1 + } + { + name: tl_rom_ctrl1__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rom_ctrl1_regs_tl + index: -1 + } + { + name: tl_peri + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + end_idx: -1 + top_signame: main_tl_peri + index: -1 + } + { + name: tl_soc_proxy__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: soc_proxy_core_tl + index: -1 + } + { + name: tl_soc_proxy__ctn + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: soc_proxy_ctn_tl + index: -1 + } + { + name: tl_hmac + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: hmac_tl + index: -1 + } + { + name: tl_kmac + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: kmac_tl + index: -1 + } + { + name: tl_aes + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: aes_tl + index: -1 + } + { + name: tl_csrng + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: csrng_tl + index: -1 + } + { + name: tl_edn0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: edn0_tl + index: -1 + } + { + name: tl_edn1 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: edn1_tl + index: -1 + } + { + name: tl_rv_plic + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rv_plic_tl + index: -1 + } + { + name: tl_otbn + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: otbn_tl + index: -1 + } + { + name: tl_keymgr_dpe + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: keymgr_dpe_tl + index: -1 + } + { + name: tl_rv_core_ibex__cfg + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rv_core_ibex_cfg_tl_d + index: -1 + } + { + name: tl_sram_ctrl_main__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: sram_ctrl_main_regs_tl + index: -1 + } + { + name: tl_sram_ctrl_main__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: sram_ctrl_main_ram_tl + index: -1 + } + { + name: tl_sram_ctrl_mbox__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: sram_ctrl_mbox_regs_tl + index: -1 + } + { + name: tl_sram_ctrl_mbox__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: sram_ctrl_mbox_ram_tl + index: -1 + } + { + name: tl_dma + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: dma_tl_d + index: -1 + } + { + name: tl_mbx0__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx0_core_tl_d + index: -1 + } + { + name: tl_mbx1__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx1_core_tl_d + index: -1 + } + { + name: tl_mbx2__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx2_core_tl_d + index: -1 + } + { + name: tl_mbx3__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx3_core_tl_d + index: -1 + } + { + name: tl_mbx4__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx4_core_tl_d + index: -1 + } + { + name: tl_mbx5__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx5_core_tl_d + index: -1 + } + { + name: tl_mbx6__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx6_core_tl_d + index: -1 + } + { + name: tl_mbx_jtag__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx_jtag_core_tl_d + index: -1 + } + { + name: tl_mbx_pcie0__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx_pcie0_core_tl_d + index: -1 + } + { + name: tl_mbx_pcie1__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: mbx_pcie1_core_tl_d + index: -1 + } + { + name: tl_main + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: peri + default: "" + top_signame: main_tl_peri + index: -1 + } + { + name: tl_uart0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: uart0_tl + index: -1 + } + { + name: tl_i2c0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: i2c0_tl + index: -1 + } + { + name: tl_gpio + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: gpio_tl + index: -1 + } + { + name: tl_spi_host0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: spi_host0_tl + index: -1 + } + { + name: tl_spi_device + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: spi_device_tl + index: -1 + } + { + name: tl_rv_timer + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: rv_timer_tl + index: -1 + } + { + name: tl_pwrmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: pwrmgr_aon_tl + index: -1 + } + { + name: tl_rstmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: rstmgr_aon_tl + index: -1 + } + { + name: tl_clkmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: clkmgr_aon_tl + index: -1 + } + { + name: tl_pinmux_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: pinmux_aon_tl + index: -1 + } + { + name: tl_otp_ctrl__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: otp_ctrl_core_tl + index: -1 + } + { + name: tl_otp_ctrl__prim + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: otp_ctrl_prim_tl + index: -1 + } + { + name: tl_lc_ctrl__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: lc_ctrl_regs_tl + index: -1 + } + { + name: tl_sensor_ctrl + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: sensor_ctrl_tl + index: -1 + } + { + name: tl_alert_handler + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: alert_handler_tl + index: -1 + } + { + name: tl_sram_ctrl_ret_aon__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: sram_ctrl_ret_aon_regs_tl + index: -1 + } + { + name: tl_sram_ctrl_ret_aon__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: sram_ctrl_ret_aon_ram_tl + index: -1 + } + { + name: tl_aon_timer_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + top_signame: aon_timer_aon_tl + index: -1 + } + { + name: tl_ast + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: peri + default: "" + external: true + top_signame: ast_tl + conn_type: false + index: -1 + } + { + name: tl_mbx + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx + default: "" + external: true + top_signame: mbx_tl + conn_type: false + index: -1 + } + { + name: tl_mbx0__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx0_soc_tl_d + index: -1 + } + { + name: tl_mbx1__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx1_soc_tl_d + index: -1 + } + { + name: tl_mbx2__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx2_soc_tl_d + index: -1 + } + { + name: tl_mbx3__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx3_soc_tl_d + index: -1 + } + { + name: tl_mbx4__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx4_soc_tl_d + index: -1 + } + { + name: tl_mbx5__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx5_soc_tl_d + index: -1 + } + { + name: tl_mbx6__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx6_soc_tl_d + index: -1 + } + { + name: tl_mbx_pcie0__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx_pcie0_soc_tl_d + index: -1 + } + { + name: tl_mbx_pcie1__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx + default: "" + top_signame: mbx_pcie1_soc_tl_d + index: -1 + } + { + name: tl_dbg + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: dbg + default: "" + external: true + top_signame: dbg_tl + conn_type: false + index: -1 + } + { + name: tl_rv_dm__dbg + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: dbg + default: "" + top_signame: rv_dm_dbg_tl_d + index: -1 + } + { + name: tl_mbx_jtag__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: dbg + default: "" + top_signame: mbx_jtag_soc_tl_d + index: -1 + } + { + name: tl_lc_ctrl__dmi + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: dbg + default: "" + top_signame: lc_ctrl_dmi_tl + index: -1 + } + { + struct: edn + type: req_rsp + name: edn + act: rsp + package: edn_pkg + inst_name: ast + width: 1 + default: "" + top_signame: edn0_edn + index: 2 + external: true + conn_type: true + } + { + struct: lc_tx + type: uni + name: lc_dft_en + act: req + package: lc_ctrl_pkg + inst_name: ast + width: 1 + default: "" + top_signame: lc_ctrl_lc_dft_en + index: -1 + external: true + conn_type: true + } + { + struct: lc_tx + type: uni + name: lc_hw_debug_en + act: req + package: lc_ctrl_pkg + inst_name: ast + width: 1 + default: "" + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + external: true + conn_type: true + } + { + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + name: ram_1p_cfg + act: rcv + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_ram_1p_cfg + index: -1 + external: true + conn_type: true + } + { + struct: ram_2p_cfg + package: prim_ram_2p_pkg + type: uni + name: spi_ram_2p_cfg + act: rcv + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_spi_ram_2p_cfg + index: -1 + external: true + conn_type: true + } + { + struct: rom_cfg + package: prim_rom_pkg + type: uni + name: rom_cfg + act: rcv + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_rom_cfg + index: -1 + external: true + conn_type: true + } + { + struct: ast_obs_ctrl + type: uni + name: obs_ctrl + act: rcv + package: ast_pkg + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_obs_ctrl + index: -1 + external: true + conn_type: true + } + ] + external: + [ + { + package: edn_pkg + struct: edn_req + signame: ast_edn_req_i + width: 1 + type: req_rsp + default: "" + direction: in + conn_type: true + index: 2 + netname: edn0_edn_req + } + { + package: edn_pkg + struct: edn_rsp + signame: ast_edn_rsp_o + width: 1 + type: req_rsp + default: "" + direction: out + conn_type: true + index: 2 + netname: edn0_edn_rsp + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: ast_lc_dft_en_o + width: 1 + type: uni + default: "" + direction: out + conn_type: true + index: -1 + netname: lc_ctrl_lc_dft_en + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: ast_lc_hw_debug_en_o + width: 1 + type: uni + default: "" + direction: out + conn_type: true + index: -1 + netname: lc_ctrl_lc_hw_debug_en + } + { + package: ast_pkg + struct: ast_obs_ctrl + signame: obs_ctrl_i + width: 1 + type: uni + default: "" + direction: in + conn_type: true + index: -1 + netname: ast_obs_ctrl + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg + signame: ram_1p_cfg_i + width: 1 + type: uni + default: "" + direction: in + conn_type: true + index: -1 + netname: ast_ram_1p_cfg + } + { + package: prim_ram_2p_pkg + struct: ram_2p_cfg + signame: spi_ram_2p_cfg_i + width: 1 + type: uni + default: "" + direction: in + conn_type: true + index: -1 + netname: ast_spi_ram_2p_cfg + } + { + package: prim_rom_pkg + struct: rom_cfg + signame: rom_cfg_i + width: 1 + type: uni + default: "" + direction: in + conn_type: true + index: -1 + netname: ast_rom_cfg + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: clk_main_jitter_en_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: clk_main_jitter_en + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: io_clk_byp_req_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: io_clk_byp_req + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: io_clk_byp_ack_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: io_clk_byp_ack + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: all_clk_byp_req_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: all_clk_byp_req + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: all_clk_byp_ack_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: all_clk_byp_ack + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: hi_speed_sel_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: hi_speed_sel + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: div_step_down_req_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: div_step_down_req + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: calib_rdy_i + width: 1 + type: uni + default: prim_mubi_pkg::MuBi4True + direction: in + conn_type: false + index: -1 + netname: calib_rdy + } + { + package: entropy_src_pkg + struct: entropy_src_hw_if_req + signame: entropy_src_hw_if_req_o + width: 1 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: entropy_src_hw_if_req + } + { + package: entropy_src_pkg + struct: entropy_src_hw_if_rsp + signame: entropy_src_hw_if_rsp_i + width: 1 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: entropy_src_hw_if_rsp + } + { + package: dma_pkg + struct: sys_req + signame: dma_sys_req_o + width: 1 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: dma_sys_req + } + { + package: dma_pkg + struct: sys_rsp + signame: dma_sys_rsp_i + width: 1 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: dma_sys_rsp + } + { + package: tlul_pkg + struct: tl_h2d + signame: dma_ctn_tl_h2d_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: dma_ctn_tl_h2d + } + { + package: tlul_pkg + struct: tl_d2h + signame: dma_ctn_tl_d2h_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: dma_ctn_tl_d2h + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx_tl_req_i + width: 1 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: mbx_tl_h2d + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx_tl_rsp_o + width: 1 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: mbx_tl_d2h + } + { + package: "" + struct: logic + signame: mbx0_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx0_doe_intr + } + { + package: "" + struct: logic + signame: mbx0_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx0_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx0_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx0_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx0_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx0_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx1_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx1_doe_intr + } + { + package: "" + struct: logic + signame: mbx1_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx1_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx1_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx1_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx1_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx1_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx2_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx2_doe_intr + } + { + package: "" + struct: logic + signame: mbx2_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx2_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx2_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx2_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx2_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx2_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx3_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx3_doe_intr + } + { + package: "" + struct: logic + signame: mbx3_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx3_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx3_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx3_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx3_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx3_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx4_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx4_doe_intr + } + { + package: "" + struct: logic + signame: mbx4_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx4_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx4_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx4_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx4_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx4_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx5_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx5_doe_intr + } + { + package: "" + struct: logic + signame: mbx5_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx5_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx5_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx5_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx5_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx5_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx6_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx6_doe_intr + } + { + package: "" + struct: logic + signame: mbx6_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx6_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx6_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx6_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx6_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx6_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx_jtag_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_jtag_doe_intr + } + { + package: "" + struct: logic + signame: mbx_jtag_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_jtag_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx_jtag_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_jtag_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx_jtag_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_jtag_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx_pcie0_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie0_doe_intr + } + { + package: "" + struct: logic + signame: mbx_pcie0_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie0_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx_pcie0_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie0_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx_pcie0_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie0_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx_pcie1_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie1_doe_intr + } + { + package: "" + struct: logic + signame: mbx_pcie1_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie1_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx_pcie1_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie1_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx_pcie1_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie1_doe_async_msg_support + } + { + package: tlul_pkg + struct: tl_h2d + signame: dbg_tl_req_i + width: 1 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: dbg_tl_h2d + } + { + package: tlul_pkg + struct: tl_d2h + signame: dbg_tl_rsp_o + width: 1 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: dbg_tl_d2h + } + { + package: rv_dm_pkg + struct: next_dm_addr + signame: rv_dm_next_dm_addr_i + width: 1 + type: uni + default: "'0" + direction: in + conn_type: false + index: -1 + netname: rv_dm_next_dm_addr + } + { + package: tlul_pkg + struct: tl_h2d + signame: ast_tl_req_o + width: 1 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: ast_tl_h2d + } + { + package: tlul_pkg + struct: tl_d2h + signame: ast_tl_rsp_i + width: 1 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: ast_tl_d2h + } + { + package: pinmux_pkg + struct: dft_strap_test_req + signame: dft_strap_test_o + width: 1 + type: uni + default: "'0" + direction: out + conn_type: false + index: -1 + netname: dft_strap_test + } + { + package: "" + struct: logic + signame: dft_hold_tap_sel_i + width: 1 + type: uni + default: "'0" + direction: in + conn_type: false + index: -1 + netname: dft_hold_tap_sel + } + { + package: pwrmgr_pkg + struct: pwr_ast_req + signame: pwrmgr_ast_req_o + width: 1 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: pwrmgr_ast_req + } + { + package: pwrmgr_pkg + struct: pwr_ast_rsp + signame: pwrmgr_ast_rsp_i + width: 1 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: pwrmgr_ast_rsp + } + { + package: otp_ctrl_pkg + struct: otp_ast_req + signame: otp_ctrl_otp_ast_pwr_seq_o + width: 1 + type: uni + default: "'0" + direction: out + conn_type: false + index: -1 + netname: otp_ctrl_otp_ast_pwr_seq + } + { + package: otp_ctrl_pkg + struct: otp_ast_rsp + signame: otp_ctrl_otp_ast_pwr_seq_h_i + width: 1 + type: uni + default: "'0" + direction: in + conn_type: false + index: -1 + netname: otp_ctrl_otp_ast_pwr_seq_h + } + { + package: "" + struct: "" + signame: otp_ext_voltage_h_io + width: 1 + type: io + default: "'0" + direction: inout + conn_type: false + index: -1 + netname: otp_ext_voltage_h + } + { + package: "" + struct: logic + signame: otp_obs_o + width: 8 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: otp_obs + } + { + package: "" + struct: logic + signame: por_n_i + width: 2 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: por_n + } + { + package: "" + struct: logic + signame: fpga_info_i + width: 32 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: fpga_info + } + { + package: ast_pkg + struct: ast_alert_req + signame: sensor_ctrl_ast_alert_req_i + width: 1 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: sensor_ctrl_ast_alert_req + } + { + package: ast_pkg + struct: ast_alert_rsp + signame: sensor_ctrl_ast_alert_rsp_o + width: 1 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: sensor_ctrl_ast_alert_rsp + } + { + package: ast_pkg + struct: ast_status + signame: sensor_ctrl_ast_status_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: sensor_ctrl_ast_status + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: ast_init_done_i + width: 1 + type: uni + default: prim_mubi_pkg::MuBi4True + direction: in + conn_type: false + index: -1 + netname: ast_init_done + } + { + package: tlul_pkg + struct: tl_h2d + signame: ctn_tl_h2d_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: ctn_tl_h2d + } + { + package: tlul_pkg + struct: tl_d2h + signame: ctn_tl_d2h_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: ctn_tl_d2h + } + { + package: soc_proxy_pkg + struct: soc_alert_req + signame: soc_fatal_alert_req_i + width: 24 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_fatal_alert_req + } + { + package: soc_proxy_pkg + struct: soc_alert_rsp + signame: soc_fatal_alert_rsp_o + width: 24 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: soc_fatal_alert_rsp + } + { + package: soc_proxy_pkg + struct: soc_alert_req + signame: soc_recov_alert_req_i + width: 4 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_recov_alert_req + } + { + package: soc_proxy_pkg + struct: soc_alert_rsp + signame: soc_recov_alert_rsp_o + width: 4 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: soc_recov_alert_rsp + } + { + package: "" + struct: logic + signame: soc_wkup_async_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_wkup_async + } + { + package: "" + struct: logic + signame: soc_rst_req_async_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_rst_req_async + } + { + package: "" + struct: logic + signame: soc_intr_async_i + width: 32 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_intr_async + } + { + package: "" + struct: logic + signame: soc_lsio_trigger_i + width: 8 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_lsio_trigger + } + { + package: "" + struct: logic + signame: soc_gpi_async_o + width: 16 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: soc_gpi_async + } + { + package: "" + struct: logic + signame: soc_gpo_async_i + width: 16 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_gpo_async + } + { + package: "" + struct: logic + signame: sck_monitor_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: sck_monitor + } + ] + definitions: + [ + { + package: ast_pkg + struct: ast_obs_ctrl + signame: ast_obs_ctrl + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: ast_pkg::AST_OBS_CTRL_DEFAULT + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg + signame: ast_ram_1p_cfg + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT + } + { + package: prim_ram_2p_pkg + struct: ram_2p_cfg + signame: ast_spi_ram_2p_cfg + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: prim_ram_2p_pkg::RAM_2P_CFG_DEFAULT + } + { + package: prim_rom_pkg + struct: rom_cfg + signame: ast_rom_cfg + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: prim_rom_pkg::ROM_CFG_DEFAULT + } + { + package: alert_pkg + struct: alert_crashdump + signame: alert_handler_crashdump + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: alert_pkg::ALERT_CRASHDUMP_DEFAULT + } + { + package: prim_esc_pkg + struct: esc_rx + signame: alert_handler_esc_rx + width: 4 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: prim_esc_pkg::ESC_RX_DEFAULT + } + { + package: prim_esc_pkg + struct: esc_tx + signame: alert_handler_esc_tx + width: 4 + type: uni + end_idx: -1 + act: req + suffix: "" + default: prim_esc_pkg::ESC_TX_DEFAULT + } + { + package: "" + struct: logic + signame: aon_timer_aon_nmi_wdog_timer_bark + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: 1'b0 + } + { + package: csrng_pkg + struct: csrng_req + signame: csrng_csrng_cmd_req + width: 2 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: csrng_pkg::CSRNG_REQ_DEFAULT + } + { + package: csrng_pkg + struct: csrng_rsp + signame: csrng_csrng_cmd_rsp + width: 2 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: otp_ctrl_pkg + struct: sram_otp_key_req + signame: otp_ctrl_sram_otp_key_req + width: 4 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: "'0" + } + { + package: otp_ctrl_pkg + struct: sram_otp_key_rsp + signame: otp_ctrl_sram_otp_key_rsp + width: 4 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: pwrmgr_pkg + struct: pwr_rst_req + signame: pwrmgr_aon_pwr_rst_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: pwrmgr_pkg + struct: pwr_rst_rsp + signame: pwrmgr_aon_pwr_rst_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: pwrmgr_pkg::PWR_RST_RSP_DEFAULT + } + { + package: pwrmgr_pkg + struct: pwr_clk_req + signame: pwrmgr_aon_pwr_clk_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: pwrmgr_pkg + struct: pwr_clk_rsp + signame: pwrmgr_aon_pwr_clk_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: pwrmgr_pkg::PWR_CLK_RSP_DEFAULT + } + { + package: pwrmgr_pkg + struct: pwr_otp_req + signame: pwrmgr_aon_pwr_otp_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: pwrmgr_pkg + struct: pwr_otp_rsp + signame: pwrmgr_aon_pwr_otp_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: pwrmgr_pkg::PWR_OTP_RSP_DEFAULT + } + { + package: pwrmgr_pkg + struct: pwr_lc_req + signame: pwrmgr_aon_pwr_lc_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: pwrmgr_pkg + struct: pwr_lc_rsp + signame: pwrmgr_aon_pwr_lc_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: pwrmgr_pkg::PWR_LC_RSP_DEFAULT + } + { + package: "" + struct: logic + signame: pwrmgr_aon_strap + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: "" + struct: logic + signame: pwrmgr_aon_low_power + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: pwrmgr_aon_fetch_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::LC_TX_DEFAULT + } + { + package: rom_ctrl_pkg + struct: pwrmgr_data + signame: pwrmgr_aon_rom_ctrl + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: rom_ctrl_pkg::PWRMGR_DATA_DEFAULT + } + { + package: rom_ctrl_pkg + struct: keymgr_data + signame: keymgr_dpe_rom_digest + width: 2 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: rom_ctrl_pkg::KEYMGR_DATA_DEFAULT + } + { + package: dma_pkg + struct: lsio_trigger + signame: dma_lsio_trigger + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: dma_pkg::LSIO_TRIGGER_DEFAULT + } + { + package: "" + struct: logic + signame: i2c0_lsio_trigger + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: "" + struct: logic + signame: spi_host0_lsio_trigger + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: "" + struct: logic + signame: uart0_lsio_trigger + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_flash_rma_req + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: otbn_lc_rma_ack + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: edn_pkg + struct: edn_req + signame: edn0_edn_req + width: 8 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: "'0" + } + { + package: edn_pkg + struct: edn_rsp + signame: edn0_edn_rsp + width: 8 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: edn_pkg + struct: edn_req + signame: edn1_edn_req + width: 8 + type: req_rsp + end_idx: 1 + act: rsp + suffix: req + default: "'0" + } + { + package: edn_pkg + struct: edn_rsp + signame: edn1_edn_rsp + width: 8 + type: req_rsp + end_idx: 1 + act: rsp + suffix: rsp + default: "" + } + { + package: otp_ctrl_pkg + struct: otbn_otp_key_req + signame: otp_ctrl_otbn_otp_key_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: "'0" + } + { + package: otp_ctrl_pkg + struct: otbn_otp_key_rsp + signame: otp_ctrl_otbn_otp_key_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: otp_ctrl_pkg + struct: otp_keymgr_key + signame: otp_ctrl_otp_keymgr_key + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: keymgr_pkg + struct: hw_key_req + signame: keymgr_dpe_aes_key + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: keymgr_pkg::HW_KEY_REQ_DEFAULT + } + { + package: keymgr_pkg + struct: hw_key_req + signame: keymgr_dpe_kmac_key + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: keymgr_pkg::HW_KEY_REQ_DEFAULT + } + { + package: keymgr_pkg + struct: otbn_key_req + signame: keymgr_dpe_otbn_key + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: keymgr_pkg::OTBN_KEY_REQ_DEFAULT + } + { + package: kmac_pkg + struct: app_req + signame: kmac_app_req + width: + { + name: NumAppIntf + desc: Number of application interfaces + param_type: int + unpacked_dimensions: null + default: 3 + local: false + expose: true + name_top: KmacNumAppIntf + } + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: kmac_pkg::APP_REQ_DEFAULT + } + { + package: kmac_pkg + struct: app_rsp + signame: kmac_app_rsp + width: + { + name: NumAppIntf + desc: Number of application interfaces + param_type: int + unpacked_dimensions: null + default: 3 + local: false + expose: true + name_top: KmacNumAppIntf + } + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: "" + struct: logic + signame: kmac_en_masking + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: clkmgr_aon_idle + width: 4 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: prim_mubi_pkg::MUBI4_DEFAULT + } + { + package: otp_ctrl_pkg + struct: otp_lc_data + signame: otp_ctrl_otp_lc_data + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: otp_ctrl_pkg + struct: lc_otp_program_req + signame: lc_ctrl_lc_otp_program_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: otp_ctrl_pkg + struct: lc_otp_program_rsp + signame: lc_ctrl_lc_otp_program_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: "'0" + } + { + package: otp_ctrl_pkg + struct: lc_otp_vendor_test_req + signame: lc_ctrl_lc_otp_vendor_test_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: otp_ctrl_pkg + struct: lc_otp_vendor_test_rsp + signame: lc_ctrl_lc_otp_vendor_test_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: "'0" + } + { + package: lc_ctrl_pkg + struct: lc_keymgr_div + signame: lc_ctrl_lc_keymgr_div + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: "" + struct: logic + signame: lc_ctrl_strap_en_override + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: 1'b0 + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_dft_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_hw_debug_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_cpu_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_keymgr_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_escalate_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_check_byp_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_clk_byp_req + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_clk_byp_ack + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_creator_seed_sw_rw_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_owner_seed_sw_rw_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_seed_hw_rd_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: "" + struct: logic + signame: rv_plic_msip + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: "" + struct: logic + signame: rv_plic_irq + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: "" + struct: logic [rv_dm_reg_pkg::NrHarts-1:0] + signame: rv_dm_debug_req + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: rv_core_ibex_pkg + struct: cpu_crash_dump + signame: rv_core_ibex_crash_dump + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: rv_core_ibex_pkg::CPU_CRASH_DUMP_DEFAULT + } + { + package: pwrmgr_pkg + struct: pwr_cpu + signame: rv_core_ibex_pwrmgr + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: pwrmgr_pkg::PWR_CPU_DEFAULT + } + { + package: spi_device_pkg + struct: passthrough_req + signame: spi_device_passthrough_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: spi_device_pkg + struct: passthrough_rsp + signame: spi_device_passthrough_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: spi_device_pkg::PASSTHROUGH_RSP_DEFAULT + } + { + package: "" + struct: logic + signame: rv_dm_ndmreset_req + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: rstmgr_aon_sw_rst_req + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: prim_mubi_pkg::MUBI4_DEFAULT + } + { + package: "" + struct: logic + signame: pwrmgr_aon_wakeups + width: 6 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: "'0" + } + { + package: "" + struct: logic + signame: pwrmgr_aon_rstreqs + width: 2 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: "'0" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_rv_core_ibex__corei_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_rv_core_ibex__corei_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_rv_core_ibex__cored_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_rv_core_ibex__cored_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_rv_dm__sba_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_rv_dm__sba_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rv_dm_regs_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rv_dm_regs_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rv_dm_mem_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rv_dm_mem_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rom_ctrl0_rom_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rom_ctrl0_rom_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rom_ctrl0_regs_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rom_ctrl0_regs_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rom_ctrl1_rom_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rom_ctrl1_rom_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rom_ctrl1_regs_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rom_ctrl1_regs_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_peri_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_peri_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: tlul_pkg::TL_D2H_DEFAULT + } + { + package: tlul_pkg + struct: tl_h2d + signame: soc_proxy_core_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: soc_proxy_core_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: soc_proxy_ctn_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: soc_proxy_ctn_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: hmac_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: hmac_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: kmac_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: kmac_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: aes_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: aes_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: csrng_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: csrng_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: edn0_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: edn0_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: edn1_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: edn1_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rv_plic_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rv_plic_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: otbn_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: otbn_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: keymgr_dpe_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: keymgr_dpe_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rv_core_ibex_cfg_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rv_core_ibex_cfg_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: sram_ctrl_main_regs_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: sram_ctrl_main_regs_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: sram_ctrl_main_ram_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: sram_ctrl_main_ram_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: sram_ctrl_mbox_regs_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: sram_ctrl_mbox_regs_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: sram_ctrl_mbox_ram_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: sram_ctrl_mbox_ram_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: dma_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: dma_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_dma__host_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_dma__host_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx0_core_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx0_core_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx0__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx0__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx1_core_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx1_core_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx1__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx1__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx2_core_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx2_core_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx2__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx2__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx3_core_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx3_core_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx3__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx3__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx4_core_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx4_core_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx4__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx4__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx5_core_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx5_core_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx5__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx5__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx6_core_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx6_core_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx6__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx6__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx_jtag_core_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx_jtag_core_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx_jtag__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx_jtag__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx_pcie0_core_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx_pcie0_core_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx_pcie0__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx_pcie0__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx_pcie1_core_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx_pcie1_core_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx_pcie1__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx_pcie1__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: uart0_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: uart0_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: i2c0_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: i2c0_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: gpio_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: gpio_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: spi_host0_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: spi_host0_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: spi_device_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: spi_device_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rv_timer_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rv_timer_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: pwrmgr_aon_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: pwrmgr_aon_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rstmgr_aon_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rstmgr_aon_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: clkmgr_aon_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: clkmgr_aon_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: pinmux_aon_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: pinmux_aon_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: otp_ctrl_core_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: otp_ctrl_core_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: otp_ctrl_prim_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: otp_ctrl_prim_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: lc_ctrl_regs_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: lc_ctrl_regs_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: sensor_ctrl_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: sensor_ctrl_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: alert_handler_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: alert_handler_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: sram_ctrl_ret_aon_regs_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: sram_ctrl_ret_aon_regs_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: sram_ctrl_ret_aon_ram_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: sram_ctrl_ret_aon_ram_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: aon_timer_aon_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: aon_timer_aon_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx0_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx0_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx1_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx1_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx2_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx2_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx3_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx3_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx4_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx4_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx5_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx5_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx6_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx6_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx_pcie0_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx_pcie0_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx_pcie1_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx_pcie1_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rv_dm_dbg_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rv_dm_dbg_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx_jtag_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx_jtag_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: lc_ctrl_dmi_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: lc_ctrl_dmi_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: clkmgr_pkg + struct: clkmgr_out + signame: clkmgr_aon_clocks + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: clkmgr_pkg + struct: clkmgr_cg_en + signame: clkmgr_aon_cg_en + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: rstmgr_pkg + struct: rstmgr_out + signame: rstmgr_aon_resets + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: rstmgr_pkg + struct: rstmgr_rst_en + signame: rstmgr_aon_rst_en + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: "" + struct: logic + signame: rv_core_ibex_irq_timer + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: "" + struct: logic + signame: rv_core_ibex_hart_id + width: 32 + type: uni + end_idx: -1 + default: "" + } + { + package: "" + struct: logic + signame: rv_core_ibex_boot_addr + width: 32 + type: uni + end_idx: -1 + default: "" + } + { + package: otp_ctrl_part_pkg + struct: otp_broadcast + signame: otp_ctrl_otp_broadcast + width: 1 + type: uni + end_idx: -1 + default: "'0" + } + { + package: otp_ctrl_pkg + struct: otp_device_id + signame: lc_ctrl_otp_device_id + width: 1 + type: uni + end_idx: -1 + default: "'0" + } + { + package: otp_ctrl_pkg + struct: otp_manuf_state + signame: lc_ctrl_otp_manuf_state + width: 1 + type: uni + end_idx: -1 + default: "'0" + } + { + package: otp_ctrl_pkg + struct: otp_device_id + signame: keymgr_dpe_otp_device_id + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: prim_mubi_pkg + struct: mubi8 + signame: sram_ctrl_main_otp_en_sram_ifetch + width: 1 + type: uni + end_idx: -1 + default: prim_mubi_pkg::MuBi8False + } + ] + } +} diff --git a/hw/top_darjeeling/dv/autogen/rstmgr_tgl_excl.cfg b/hw/top_darjeeling/dv/autogen/rstmgr_tgl_excl.cfg new file mode 100644 index 0000000000000..7e8f665ab6522 --- /dev/null +++ b/hw/top_darjeeling/dv/autogen/rstmgr_tgl_excl.cfg @@ -0,0 +1,29 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// rstmgr_tgl_excl.cfg generated by `topgen.py` tool +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \ +// -o hw/top_darjeeling/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + +//========================================================= +// This file contains resets that are not used at top level +//========================================================= +-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_div2_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_div4_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_aon_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_io_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_io_div2_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_sys_n[0] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_sys_io_div4_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_spi_device_n[0] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_spi_host0_n[0] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_i2c0_n[0] diff --git a/hw/top_darjeeling/dv/autogen/tb__alert_handler_connect.sv b/hw/top_darjeeling/dv/autogen/tb__alert_handler_connect.sv new file mode 100644 index 0000000000000..f2f4b69c56205 --- /dev/null +++ b/hw/top_darjeeling/dv/autogen/tb__alert_handler_connect.sv @@ -0,0 +1,105 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__alert_handler_connect.sv is auto-generated by `topgen.py` tool + +assign alert_if[0].alert_tx = `CHIP_HIER.u_uart0.alert_tx_o[0]; +assign alert_if[1].alert_tx = `CHIP_HIER.u_gpio.alert_tx_o[0]; +assign alert_if[2].alert_tx = `CHIP_HIER.u_spi_device.alert_tx_o[0]; +assign alert_if[3].alert_tx = `CHIP_HIER.u_i2c0.alert_tx_o[0]; +assign alert_if[4].alert_tx = `CHIP_HIER.u_rv_timer.alert_tx_o[0]; +assign alert_if[5].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0]; +assign alert_if[6].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1]; +assign alert_if[7].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[2]; +assign alert_if[8].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[3]; +assign alert_if[9].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[4]; +assign alert_if[10].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0]; +assign alert_if[11].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1]; +assign alert_if[12].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2]; +assign alert_if[13].alert_tx = `CHIP_HIER.u_spi_host0.alert_tx_o[0]; +assign alert_if[14].alert_tx = `CHIP_HIER.u_pwrmgr_aon.alert_tx_o[0]; +assign alert_if[15].alert_tx = `CHIP_HIER.u_rstmgr_aon.alert_tx_o[0]; +assign alert_if[16].alert_tx = `CHIP_HIER.u_rstmgr_aon.alert_tx_o[1]; +assign alert_if[17].alert_tx = `CHIP_HIER.u_clkmgr_aon.alert_tx_o[0]; +assign alert_if[18].alert_tx = `CHIP_HIER.u_clkmgr_aon.alert_tx_o[1]; +assign alert_if[19].alert_tx = `CHIP_HIER.u_pinmux_aon.alert_tx_o[0]; +assign alert_if[20].alert_tx = `CHIP_HIER.u_aon_timer_aon.alert_tx_o[0]; +assign alert_if[21].alert_tx = `CHIP_HIER.u_sensor_ctrl.alert_tx_o[0]; +assign alert_if[22].alert_tx = `CHIP_HIER.u_sensor_ctrl.alert_tx_o[1]; +assign alert_if[23].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[0]; +assign alert_if[24].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[1]; +assign alert_if[25].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[2]; +assign alert_if[26].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[3]; +assign alert_if[27].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[4]; +assign alert_if[28].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[5]; +assign alert_if[29].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[6]; +assign alert_if[30].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[7]; +assign alert_if[31].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[8]; +assign alert_if[32].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[9]; +assign alert_if[33].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[10]; +assign alert_if[34].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[11]; +assign alert_if[35].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[12]; +assign alert_if[36].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[13]; +assign alert_if[37].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[14]; +assign alert_if[38].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[15]; +assign alert_if[39].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[16]; +assign alert_if[40].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[17]; +assign alert_if[41].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[18]; +assign alert_if[42].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[19]; +assign alert_if[43].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[20]; +assign alert_if[44].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[21]; +assign alert_if[45].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[22]; +assign alert_if[46].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[23]; +assign alert_if[47].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[24]; +assign alert_if[48].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[25]; +assign alert_if[49].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[26]; +assign alert_if[50].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[27]; +assign alert_if[51].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[28]; +assign alert_if[52].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0]; +assign alert_if[53].alert_tx = `CHIP_HIER.u_rv_dm.alert_tx_o[0]; +assign alert_if[54].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0]; +assign alert_if[55].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; +assign alert_if[56].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; +assign alert_if[57].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0]; +assign alert_if[58].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0]; +assign alert_if[59].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1]; +assign alert_if[60].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0]; +assign alert_if[61].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1]; +assign alert_if[62].alert_tx = `CHIP_HIER.u_keymgr_dpe.alert_tx_o[0]; +assign alert_if[63].alert_tx = `CHIP_HIER.u_keymgr_dpe.alert_tx_o[1]; +assign alert_if[64].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0]; +assign alert_if[65].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[1]; +assign alert_if[66].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0]; +assign alert_if[67].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[1]; +assign alert_if[68].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0]; +assign alert_if[69].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[1]; +assign alert_if[70].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0]; +assign alert_if[71].alert_tx = `CHIP_HIER.u_sram_ctrl_mbox.alert_tx_o[0]; +assign alert_if[72].alert_tx = `CHIP_HIER.u_rom_ctrl0.alert_tx_o[0]; +assign alert_if[73].alert_tx = `CHIP_HIER.u_rom_ctrl1.alert_tx_o[0]; +assign alert_if[74].alert_tx = `CHIP_HIER.u_dma.alert_tx_o[0]; +assign alert_if[75].alert_tx = `CHIP_HIER.u_mbx0.alert_tx_o[0]; +assign alert_if[76].alert_tx = `CHIP_HIER.u_mbx0.alert_tx_o[1]; +assign alert_if[77].alert_tx = `CHIP_HIER.u_mbx1.alert_tx_o[0]; +assign alert_if[78].alert_tx = `CHIP_HIER.u_mbx1.alert_tx_o[1]; +assign alert_if[79].alert_tx = `CHIP_HIER.u_mbx2.alert_tx_o[0]; +assign alert_if[80].alert_tx = `CHIP_HIER.u_mbx2.alert_tx_o[1]; +assign alert_if[81].alert_tx = `CHIP_HIER.u_mbx3.alert_tx_o[0]; +assign alert_if[82].alert_tx = `CHIP_HIER.u_mbx3.alert_tx_o[1]; +assign alert_if[83].alert_tx = `CHIP_HIER.u_mbx4.alert_tx_o[0]; +assign alert_if[84].alert_tx = `CHIP_HIER.u_mbx4.alert_tx_o[1]; +assign alert_if[85].alert_tx = `CHIP_HIER.u_mbx5.alert_tx_o[0]; +assign alert_if[86].alert_tx = `CHIP_HIER.u_mbx5.alert_tx_o[1]; +assign alert_if[87].alert_tx = `CHIP_HIER.u_mbx6.alert_tx_o[0]; +assign alert_if[88].alert_tx = `CHIP_HIER.u_mbx6.alert_tx_o[1]; +assign alert_if[89].alert_tx = `CHIP_HIER.u_mbx_jtag.alert_tx_o[0]; +assign alert_if[90].alert_tx = `CHIP_HIER.u_mbx_jtag.alert_tx_o[1]; +assign alert_if[91].alert_tx = `CHIP_HIER.u_mbx_pcie0.alert_tx_o[0]; +assign alert_if[92].alert_tx = `CHIP_HIER.u_mbx_pcie0.alert_tx_o[1]; +assign alert_if[93].alert_tx = `CHIP_HIER.u_mbx_pcie1.alert_tx_o[0]; +assign alert_if[94].alert_tx = `CHIP_HIER.u_mbx_pcie1.alert_tx_o[1]; +assign alert_if[95].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[0]; +assign alert_if[96].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[1]; +assign alert_if[97].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[2]; +assign alert_if[98].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[3]; diff --git a/hw/top_darjeeling/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling/dv/autogen/tb__xbar_connect.sv new file mode 100644 index 0000000000000..aadf0359e9ac3 --- /dev/null +++ b/hw/top_darjeeling/dv/autogen/tb__xbar_connect.sv @@ -0,0 +1,246 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__xbar_connect generated by `topgen.py` tool + +// This file must be `included in `hw/top_/dv/tb/tb.sv. + +`define DRIVE_CHIP_TL_HOST_IF(tl_name, inst_name, sig_name) \ + force ``tl_name``_tl_if.d2h = dut.top_darjeeling.u_``inst_name``.``sig_name``_i; \ + force dut.top_darjeeling.u_``inst_name``.``sig_name``_o = ``tl_name``_tl_if.h2d; \ + force dut.top_darjeeling.u_``inst_name``.clk_i = 0; \ + uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \ + ``tl_name``_tl_if); + +`define DRIVE_CHIP_TL_DEVICE_IF(tl_name, inst_name, sig_name) \ + force ``tl_name``_tl_if.h2d = dut.top_darjeeling.u_``inst_name``.``sig_name``_i; \ + force dut.top_darjeeling.u_``inst_name``.``sig_name``_o = ``tl_name``_tl_if.d2h; \ + force dut.top_darjeeling.u_``inst_name``.clk_i = 0; \ + uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \ + ``tl_name``_tl_if); + +`define DRIVE_CHIP_TL_EXT_DEVICE_IF(tl_name, inst_name, port_name) \ + force ``tl_name``_tl_if.h2d = dut.u_``inst_name``.``port_name``_i; \ + force dut.u_``inst_name``.``port_name``_o = ``tl_name``_tl_if.d2h; \ + uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \ + ``tl_name``_tl_if); + +wire clk_main; +clk_rst_if clk_rst_if_main(.clk(clk_main), .rst_n(rst_n)); +wire clk_usb; +clk_rst_if clk_rst_if_usb(.clk(clk_usb), .rst_n(rst_n)); +wire clk_io_div4; +clk_rst_if clk_rst_if_io_div4(.clk(clk_io_div4), .rst_n(rst_n)); + +tl_if rv_core_ibex__corei_tl_if(clk_main, rst_n); +tl_if rv_core_ibex__cored_tl_if(clk_main, rst_n); +tl_if rv_dm__sba_tl_if(clk_main, rst_n); +tl_if dma__host_tl_if(clk_main, rst_n); +tl_if mbx0__sram_tl_if(clk_main, rst_n); +tl_if mbx1__sram_tl_if(clk_main, rst_n); +tl_if mbx2__sram_tl_if(clk_main, rst_n); +tl_if mbx3__sram_tl_if(clk_main, rst_n); +tl_if mbx4__sram_tl_if(clk_main, rst_n); +tl_if mbx5__sram_tl_if(clk_main, rst_n); +tl_if mbx6__sram_tl_if(clk_main, rst_n); +tl_if mbx_jtag__sram_tl_if(clk_main, rst_n); +tl_if mbx_pcie0__sram_tl_if(clk_main, rst_n); +tl_if mbx_pcie1__sram_tl_if(clk_main, rst_n); + +tl_if rv_dm__regs_tl_if(clk_main, rst_n); +tl_if rv_dm__mem_tl_if(clk_main, rst_n); +tl_if rom_ctrl0__rom_tl_if(clk_main, rst_n); +tl_if rom_ctrl0__regs_tl_if(clk_main, rst_n); +tl_if rom_ctrl1__rom_tl_if(clk_main, rst_n); +tl_if rom_ctrl1__regs_tl_if(clk_main, rst_n); +tl_if soc_proxy__core_tl_if(clk_main, rst_n); +tl_if soc_proxy__ctn_tl_if(clk_main, rst_n); +tl_if hmac_tl_if(clk_main, rst_n); +tl_if kmac_tl_if(clk_main, rst_n); +tl_if aes_tl_if(clk_main, rst_n); +tl_if csrng_tl_if(clk_main, rst_n); +tl_if edn0_tl_if(clk_main, rst_n); +tl_if edn1_tl_if(clk_main, rst_n); +tl_if rv_plic_tl_if(clk_main, rst_n); +tl_if otbn_tl_if(clk_main, rst_n); +tl_if keymgr_dpe_tl_if(clk_main, rst_n); +tl_if rv_core_ibex__cfg_tl_if(clk_main, rst_n); +tl_if sram_ctrl_main__regs_tl_if(clk_main, rst_n); +tl_if sram_ctrl_main__ram_tl_if(clk_main, rst_n); +tl_if sram_ctrl_mbox__regs_tl_if(clk_main, rst_n); +tl_if sram_ctrl_mbox__ram_tl_if(clk_main, rst_n); +tl_if dma_tl_if(clk_main, rst_n); +tl_if mbx0__core_tl_if(clk_main, rst_n); +tl_if mbx1__core_tl_if(clk_main, rst_n); +tl_if mbx2__core_tl_if(clk_main, rst_n); +tl_if mbx3__core_tl_if(clk_main, rst_n); +tl_if mbx4__core_tl_if(clk_main, rst_n); +tl_if mbx5__core_tl_if(clk_main, rst_n); +tl_if mbx6__core_tl_if(clk_main, rst_n); +tl_if mbx_jtag__core_tl_if(clk_main, rst_n); +tl_if mbx_pcie0__core_tl_if(clk_main, rst_n); +tl_if mbx_pcie1__core_tl_if(clk_main, rst_n); +tl_if uart0_tl_if(clk_io_div4, rst_n); +tl_if i2c0_tl_if(clk_io_div4, rst_n); +tl_if gpio_tl_if(clk_io_div4, rst_n); +tl_if spi_host0_tl_if(clk_io_div4, rst_n); +tl_if spi_device_tl_if(clk_io_div4, rst_n); +tl_if rv_timer_tl_if(clk_io_div4, rst_n); +tl_if pwrmgr_aon_tl_if(clk_io_div4, rst_n); +tl_if rstmgr_aon_tl_if(clk_io_div4, rst_n); +tl_if clkmgr_aon_tl_if(clk_io_div4, rst_n); +tl_if pinmux_aon_tl_if(clk_io_div4, rst_n); +tl_if otp_ctrl__core_tl_if(clk_io_div4, rst_n); +tl_if otp_ctrl__prim_tl_if(clk_io_div4, rst_n); +tl_if lc_ctrl__regs_tl_if(clk_io_div4, rst_n); +tl_if sensor_ctrl_tl_if(clk_io_div4, rst_n); +tl_if alert_handler_tl_if(clk_io_div4, rst_n); +tl_if sram_ctrl_ret_aon__regs_tl_if(clk_io_div4, rst_n); +tl_if sram_ctrl_ret_aon__ram_tl_if(clk_io_div4, rst_n); +tl_if aon_timer_aon_tl_if(clk_io_div4, rst_n); +tl_if ast_tl_if(clk_io_div4, rst_n); +tl_if mbx0__soc_tl_if(clk_main, rst_n); +tl_if mbx1__soc_tl_if(clk_main, rst_n); +tl_if mbx2__soc_tl_if(clk_main, rst_n); +tl_if mbx3__soc_tl_if(clk_main, rst_n); +tl_if mbx4__soc_tl_if(clk_main, rst_n); +tl_if mbx5__soc_tl_if(clk_main, rst_n); +tl_if mbx6__soc_tl_if(clk_main, rst_n); +tl_if mbx_pcie0__soc_tl_if(clk_main, rst_n); +tl_if mbx_pcie1__soc_tl_if(clk_main, rst_n); +tl_if rv_dm__dbg_tl_if(clk_main, rst_n); +tl_if mbx_jtag__soc_tl_if(clk_main, rst_n); +tl_if lc_ctrl__dmi_tl_if(clk_io_div4, rst_n); + +initial begin + wait (xbar_mode !== 1'bx); + if (xbar_mode) begin + // only enable assertions in xbar as many pins are unconnected + $assertoff(0, tb); + $asserton(0, tb.dut.top_darjeeling.u_xbar_main); + $asserton(0, tb.dut.top_darjeeling.u_xbar_peri); + $asserton(0, tb.dut.top_darjeeling.u_xbar_mbx); + $asserton(0, tb.dut.top_darjeeling.u_xbar_dbg); + + + // These are all zero-time: anything that consumes time go at the end. + + // bypass clkmgr, force clocks directly + force tb.dut.top_darjeeling.u_xbar_main.clk_main_i = clk_main; + force tb.dut.top_darjeeling.u_xbar_main.clk_fixed_i = clk_io_div4; + force tb.dut.top_darjeeling.u_xbar_main.clk_usb_i = clk_usb; + force tb.dut.top_darjeeling.u_xbar_peri.clk_peri_i = clk_io_div4; + force tb.dut.top_darjeeling.u_xbar_mbx.clk_mbx_i = clk_main; + force tb.dut.top_darjeeling.u_xbar_dbg.clk_dbg_i = clk_main; + force tb.dut.top_darjeeling.u_xbar_dbg.clk_peri_i = clk_io_div4; + + // bypass rstmgr, force resets directly + force tb.dut.top_darjeeling.u_xbar_main.rst_main_ni = rst_n; + force tb.dut.top_darjeeling.u_xbar_main.rst_fixed_ni = rst_n; + force tb.dut.top_darjeeling.u_xbar_main.rst_usb_ni = rst_n; + force tb.dut.top_darjeeling.u_xbar_peri.rst_peri_ni = rst_n; + force tb.dut.top_darjeeling.u_xbar_mbx.rst_mbx_ni = rst_n; + force tb.dut.top_darjeeling.u_xbar_dbg.rst_dbg_ni = rst_n; + force tb.dut.top_darjeeling.u_xbar_dbg.rst_peri_ni = rst_n; + +`ifndef GATE_LEVEL + `DRIVE_CHIP_TL_HOST_IF(rv_core_ibex__corei, rv_core_ibex, corei_tl_h) + `DRIVE_CHIP_TL_HOST_IF(rv_core_ibex__cored, rv_core_ibex, cored_tl_h) + `DRIVE_CHIP_TL_HOST_IF(rv_dm__sba, rv_dm, sba_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(rv_dm__regs, rv_dm, regs_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(rv_dm__mem, rv_dm, mem_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(rom_ctrl0__rom, rom_ctrl0, rom_tl) + `DRIVE_CHIP_TL_DEVICE_IF(rom_ctrl0__regs, rom_ctrl0, regs_tl) + `DRIVE_CHIP_TL_DEVICE_IF(rom_ctrl1__rom, rom_ctrl1, rom_tl) + `DRIVE_CHIP_TL_DEVICE_IF(rom_ctrl1__regs, rom_ctrl1, regs_tl) + `DRIVE_CHIP_TL_DEVICE_IF(soc_proxy__core, soc_proxy, core_tl) + `DRIVE_CHIP_TL_DEVICE_IF(soc_proxy__ctn, soc_proxy, ctn_tl) + `DRIVE_CHIP_TL_DEVICE_IF(hmac, hmac, tl) + `DRIVE_CHIP_TL_DEVICE_IF(kmac, kmac, tl) + `DRIVE_CHIP_TL_DEVICE_IF(aes, aes, tl) + `DRIVE_CHIP_TL_DEVICE_IF(csrng, csrng, tl) + `DRIVE_CHIP_TL_DEVICE_IF(edn0, edn0, tl) + `DRIVE_CHIP_TL_DEVICE_IF(edn1, edn1, tl) + `DRIVE_CHIP_TL_DEVICE_IF(rv_plic, rv_plic, tl) + `DRIVE_CHIP_TL_DEVICE_IF(otbn, otbn, tl) + `DRIVE_CHIP_TL_DEVICE_IF(keymgr_dpe, keymgr_dpe, tl) + `DRIVE_CHIP_TL_DEVICE_IF(rv_core_ibex__cfg, rv_core_ibex, cfg_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_main__regs, sram_ctrl_main, regs_tl) + `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_main__ram, sram_ctrl_main, ram_tl) + `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_mbox__regs, sram_ctrl_mbox, regs_tl) + `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_mbox__ram, sram_ctrl_mbox, ram_tl) + `DRIVE_CHIP_TL_DEVICE_IF(dma, dma, tl_d) + `DRIVE_CHIP_TL_HOST_IF(dma__host, dma, host_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(mbx0__core, mbx0, core_tl_d) + `DRIVE_CHIP_TL_HOST_IF(mbx0__sram, mbx0, sram_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(mbx1__core, mbx1, core_tl_d) + `DRIVE_CHIP_TL_HOST_IF(mbx1__sram, mbx1, sram_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(mbx2__core, mbx2, core_tl_d) + `DRIVE_CHIP_TL_HOST_IF(mbx2__sram, mbx2, sram_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(mbx3__core, mbx3, core_tl_d) + `DRIVE_CHIP_TL_HOST_IF(mbx3__sram, mbx3, sram_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(mbx4__core, mbx4, core_tl_d) + `DRIVE_CHIP_TL_HOST_IF(mbx4__sram, mbx4, sram_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(mbx5__core, mbx5, core_tl_d) + `DRIVE_CHIP_TL_HOST_IF(mbx5__sram, mbx5, sram_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(mbx6__core, mbx6, core_tl_d) + `DRIVE_CHIP_TL_HOST_IF(mbx6__sram, mbx6, sram_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(mbx_jtag__core, mbx_jtag, core_tl_d) + `DRIVE_CHIP_TL_HOST_IF(mbx_jtag__sram, mbx_jtag, sram_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(mbx_pcie0__core, mbx_pcie0, core_tl_d) + `DRIVE_CHIP_TL_HOST_IF(mbx_pcie0__sram, mbx_pcie0, sram_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(mbx_pcie1__core, mbx_pcie1, core_tl_d) + `DRIVE_CHIP_TL_HOST_IF(mbx_pcie1__sram, mbx_pcie1, sram_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(uart0, uart0, tl) + `DRIVE_CHIP_TL_DEVICE_IF(i2c0, i2c0, tl) + `DRIVE_CHIP_TL_DEVICE_IF(gpio, gpio, tl) + `DRIVE_CHIP_TL_DEVICE_IF(spi_host0, spi_host0, tl) + `DRIVE_CHIP_TL_DEVICE_IF(spi_device, spi_device, tl) + `DRIVE_CHIP_TL_DEVICE_IF(rv_timer, rv_timer, tl) + `DRIVE_CHIP_TL_DEVICE_IF(pwrmgr_aon, pwrmgr_aon, tl) + `DRIVE_CHIP_TL_DEVICE_IF(rstmgr_aon, rstmgr_aon, tl) + `DRIVE_CHIP_TL_DEVICE_IF(clkmgr_aon, clkmgr_aon, tl) + `DRIVE_CHIP_TL_DEVICE_IF(pinmux_aon, pinmux_aon, tl) + `DRIVE_CHIP_TL_DEVICE_IF(otp_ctrl__core, otp_ctrl, core_tl) + `DRIVE_CHIP_TL_DEVICE_IF(otp_ctrl__prim, otp_ctrl, prim_tl) + `DRIVE_CHIP_TL_DEVICE_IF(lc_ctrl__regs, lc_ctrl, regs_tl) + `DRIVE_CHIP_TL_DEVICE_IF(sensor_ctrl, sensor_ctrl, tl) + `DRIVE_CHIP_TL_DEVICE_IF(alert_handler, alert_handler, tl) + `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_ret_aon__regs, sram_ctrl_ret_aon, regs_tl) + `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_ret_aon__ram, sram_ctrl_ret_aon, ram_tl) + `DRIVE_CHIP_TL_DEVICE_IF(aon_timer_aon, aon_timer_aon, tl) + `DRIVE_CHIP_TL_EXT_DEVICE_IF(ast, ast, tl) + `DRIVE_CHIP_TL_DEVICE_IF(mbx0__soc, mbx0, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx1__soc, mbx1, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx2__soc, mbx2, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx3__soc, mbx3, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx4__soc, mbx4, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx5__soc, mbx5, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx6__soc, mbx6, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx_pcie0__soc, mbx_pcie0, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx_pcie1__soc, mbx_pcie1, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(rv_dm__dbg, rv_dm, dbg_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx_jtag__soc, mbx_jtag, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(lc_ctrl__dmi, lc_ctrl, dmi_tl) +`endif + + // And this can consume time, so they go at the end of this block. + + // Wait for a negedge of rst_n, or else we will have clock edges before + // reset, which could capture 'X values. + xbar_clk_rst_if.wait_for_reset(.wait_posedge(1'b0)); + + clk_rst_if_main.set_active(.drive_rst_n_val(0)); + clk_rst_if_main.set_freq_khz(100000000 / 1000); + clk_rst_if_usb.set_active(.drive_rst_n_val(0)); + clk_rst_if_usb.set_freq_khz(48000000 / 1000); + clk_rst_if_io_div4.set_active(.drive_rst_n_val(0)); + clk_rst_if_io_div4.set_freq_khz(24000000 / 1000); + + end +end + +`undef DRIVE_CHIP_TL_HOST_IF +`undef DRIVE_CHIP_TL_DEVICE_IF +`undef DRIVE_CHIP_TL_EXT_DEVICE_IF diff --git a/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv new file mode 100644 index 0000000000000..4f4d289e8508d --- /dev/null +++ b/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv @@ -0,0 +1,378 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_env_pkg__params generated by `topgen.py` tool + + +// List of Xbar device memory map +tl_device_t xbar_devices[$] = '{ + '{"rv_dm__regs", '{ + '{32'h21200000, 32'h2120000f} + }}, + '{"rv_dm__mem", '{ + '{32'h00040000, 32'h00040fff} + }}, + '{"rom_ctrl0__rom", '{ + '{32'h00008000, 32'h0000ffff} + }}, + '{"rom_ctrl0__regs", '{ + '{32'h211e0000, 32'h211e007f} + }}, + '{"rom_ctrl1__rom", '{ + '{32'h00020000, 32'h0002ffff} + }}, + '{"rom_ctrl1__regs", '{ + '{32'h211e1000, 32'h211e107f} + }}, + '{"soc_proxy__core", '{ + '{32'h22030000, 32'h2203000f} + }}, + '{"soc_proxy__ctn", '{ + '{32'h40000000, 32'h7fffffff} + }}, + '{"hmac", '{ + '{32'h21110000, 32'h21111fff} + }}, + '{"kmac", '{ + '{32'h21120000, 32'h21120fff} + }}, + '{"aes", '{ + '{32'h21100000, 32'h211000ff} + }}, + '{"csrng", '{ + '{32'h21150000, 32'h2115007f} + }}, + '{"edn0", '{ + '{32'h21170000, 32'h2117007f} + }}, + '{"edn1", '{ + '{32'h21180000, 32'h2118007f} + }}, + '{"rv_plic", '{ + '{32'h28000000, 32'h2fffffff} + }}, + '{"otbn", '{ + '{32'h21130000, 32'h2113ffff} + }}, + '{"keymgr_dpe", '{ + '{32'h21140000, 32'h211400ff} + }}, + '{"rv_core_ibex__cfg", '{ + '{32'h211f0000, 32'h211f00ff} + }}, + '{"sram_ctrl_main__regs", '{ + '{32'h211c0000, 32'h211c003f} + }}, + '{"sram_ctrl_main__ram", '{ + '{32'h10000000, 32'h1000ffff} + }}, + '{"sram_ctrl_mbox__regs", '{ + '{32'h211d0000, 32'h211d003f} + }}, + '{"sram_ctrl_mbox__ram", '{ + '{32'h11000000, 32'h11000fff} + }}, + '{"dma", '{ + '{32'h22010000, 32'h220101ff} + }}, + '{"mbx0__core", '{ + '{32'h22000000, 32'h2200007f} + }}, + '{"mbx1__core", '{ + '{32'h22000100, 32'h2200017f} + }}, + '{"mbx2__core", '{ + '{32'h22000200, 32'h2200027f} + }}, + '{"mbx3__core", '{ + '{32'h22000300, 32'h2200037f} + }}, + '{"mbx4__core", '{ + '{32'h22000400, 32'h2200047f} + }}, + '{"mbx5__core", '{ + '{32'h22000500, 32'h2200057f} + }}, + '{"mbx6__core", '{ + '{32'h22000600, 32'h2200067f} + }}, + '{"mbx_jtag__core", '{ + '{32'h22000800, 32'h2200087f} + }}, + '{"mbx_pcie0__core", '{ + '{32'h22040000, 32'h2204007f} + }}, + '{"mbx_pcie1__core", '{ + '{32'h22040100, 32'h2204017f} + }}, + '{"uart0", '{ + '{32'h30010000, 32'h3001003f} + }}, + '{"i2c0", '{ + '{32'h30080000, 32'h3008007f} + }}, + '{"gpio", '{ + '{32'h30000000, 32'h3000007f} + }}, + '{"spi_host0", '{ + '{32'h30300000, 32'h3030003f} + }}, + '{"spi_device", '{ + '{32'h30310000, 32'h30311fff} + }}, + '{"rv_timer", '{ + '{32'h30100000, 32'h301001ff} + }}, + '{"pwrmgr_aon", '{ + '{32'h30400000, 32'h3040007f} + }}, + '{"rstmgr_aon", '{ + '{32'h30410000, 32'h3041007f} + }}, + '{"clkmgr_aon", '{ + '{32'h30420000, 32'h3042007f} + }}, + '{"pinmux_aon", '{ + '{32'h30460000, 32'h304607ff} + }}, + '{"otp_ctrl__core", '{ + '{32'h30130000, 32'h30130fff} + }}, + '{"otp_ctrl__prim", '{ + '{32'h30138000, 32'h3013801f} + }}, + '{"lc_ctrl__regs", '{ + '{32'h30140000, 32'h301400ff} + }}, + '{"sensor_ctrl", '{ + '{32'h30020000, 32'h3002003f} + }}, + '{"alert_handler", '{ + '{32'h30150000, 32'h301507ff} + }}, + '{"sram_ctrl_ret_aon__regs", '{ + '{32'h30500000, 32'h3050003f} + }}, + '{"sram_ctrl_ret_aon__ram", '{ + '{32'h30600000, 32'h30600fff} + }}, + '{"aon_timer_aon", '{ + '{32'h30470000, 32'h3047003f} + }}, + '{"ast", '{ + '{32'h30480000, 32'h304803ff} + }}, + '{"mbx0__soc", '{ + '{32'h01465000, 32'h0146501f} + }}, + '{"mbx1__soc", '{ + '{32'h01465100, 32'h0146511f} + }}, + '{"mbx2__soc", '{ + '{32'h01465200, 32'h0146521f} + }}, + '{"mbx3__soc", '{ + '{32'h01465300, 32'h0146531f} + }}, + '{"mbx4__soc", '{ + '{32'h01465400, 32'h0146541f} + }}, + '{"mbx5__soc", '{ + '{32'h01465500, 32'h0146551f} + }}, + '{"mbx6__soc", '{ + '{32'h01465600, 32'h0146561f} + }}, + '{"mbx_pcie0__soc", '{ + '{32'h01460100, 32'h0146011f} + }}, + '{"mbx_pcie1__soc", '{ + '{32'h01460200, 32'h0146021f} + }}, + '{"rv_dm__dbg", '{ + '{32'h00000000, 32'h000001ff} + }}, + '{"mbx_jtag__soc", '{ + '{32'h00001000, 32'h0000101f} + }}, + '{"lc_ctrl__dmi", '{ + '{32'h00020000, 32'h00020fff} + }}}; + + // List of Xbar hosts +tl_host_t xbar_hosts[$] = '{ + '{"rv_core_ibex__corei", 0, '{ + "rom_ctrl0__rom", + "rom_ctrl1__rom", + "rv_dm__mem", + "sram_ctrl_main__ram", + "soc_proxy__ctn"}} + , + '{"rv_core_ibex__cored", 1, '{ + "rom_ctrl0__rom", + "rom_ctrl0__regs", + "rom_ctrl1__rom", + "rom_ctrl1__regs", + "rv_dm__mem", + "rv_dm__regs", + "sram_ctrl_main__ram", + "uart0", + "i2c0", + "gpio", + "spi_host0", + "spi_device", + "rv_timer", + "pwrmgr_aon", + "rstmgr_aon", + "clkmgr_aon", + "pinmux_aon", + "otp_ctrl__core", + "otp_ctrl__prim", + "lc_ctrl__regs", + "sensor_ctrl", + "alert_handler", + "ast", + "sram_ctrl_ret_aon__ram", + "sram_ctrl_ret_aon__regs", + "aon_timer_aon", + "aes", + "csrng", + "edn0", + "edn1", + "hmac", + "rv_plic", + "otbn", + "keymgr_dpe", + "kmac", + "sram_ctrl_main__regs", + "rv_core_ibex__cfg", + "sram_ctrl_mbox__ram", + "sram_ctrl_mbox__regs", + "soc_proxy__ctn", + "soc_proxy__core", + "dma", + "mbx0__core", + "mbx1__core", + "mbx2__core", + "mbx3__core", + "mbx4__core", + "mbx5__core", + "mbx6__core", + "mbx_jtag__core", + "mbx_pcie0__core", + "mbx_pcie1__core"}} + , + '{"rv_dm__sba", 2, '{ + "rom_ctrl0__rom", + "rom_ctrl0__regs", + "rom_ctrl1__rom", + "rom_ctrl1__regs", + "rv_dm__mem", + "rv_dm__regs", + "sram_ctrl_main__ram", + "uart0", + "i2c0", + "gpio", + "spi_host0", + "spi_device", + "rv_timer", + "pwrmgr_aon", + "rstmgr_aon", + "clkmgr_aon", + "pinmux_aon", + "otp_ctrl__core", + "otp_ctrl__prim", + "lc_ctrl__regs", + "sensor_ctrl", + "alert_handler", + "ast", + "sram_ctrl_ret_aon__ram", + "sram_ctrl_ret_aon__regs", + "aon_timer_aon", + "aes", + "csrng", + "edn0", + "edn1", + "hmac", + "rv_plic", + "otbn", + "keymgr_dpe", + "kmac", + "sram_ctrl_main__regs", + "rv_core_ibex__cfg", + "sram_ctrl_mbox__ram", + "sram_ctrl_mbox__regs", + "soc_proxy__ctn", + "soc_proxy__core", + "dma", + "mbx0__core", + "mbx1__core", + "mbx2__core", + "mbx3__core", + "mbx4__core", + "mbx5__core", + "mbx6__core", + "mbx_jtag__core", + "mbx_pcie0__core", + "mbx_pcie1__core"}} + , + '{"dma__host", 3, '{ + "sram_ctrl_main__ram", + "sram_ctrl_mbox__ram", + "aes", + "hmac", + "otbn", + "keymgr_dpe", + "kmac", + "soc_proxy__ctn", + "uart0", + "i2c0", + "gpio", + "spi_host0", + "spi_device", + "rv_timer", + "pwrmgr_aon", + "rstmgr_aon", + "clkmgr_aon", + "pinmux_aon", + "otp_ctrl__core", + "otp_ctrl__prim", + "lc_ctrl__regs", + "sensor_ctrl", + "alert_handler", + "ast", + "sram_ctrl_ret_aon__ram", + "sram_ctrl_ret_aon__regs", + "aon_timer_aon"}} + , + '{"mbx0__sram", 4, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx1__sram", 5, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx2__sram", 6, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx3__sram", 7, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx4__sram", 8, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx5__sram", 9, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx6__sram", 10, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_jtag__sram", 11, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_pcie0__sram", 12, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_pcie1__sram", 13, '{ + "sram_ctrl_mbox__ram"}} +}; diff --git a/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg b/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg new file mode 100644 index 0000000000000..56528d11f4a44 --- /dev/null +++ b/hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg @@ -0,0 +1,285 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_tgl_excl.cfg generated by `topgen.py` tool + +// [UNSUPPORTED] Exclude unused TL port signals at all hierarchies, wherever port toggle coverage is +// enabled. Exercising these reserved signals will result in assertion errors thrown by the design. +-node tb.dut*.u_* *tl_*.a_param +-node tb.dut*.u_* *tl_*.a_user.rsvd +-node tb.dut*.u_* *tl_*.d_param +-node tb.dut*.u_* *tl_*.d_opcode[2:1] +-node tb.dut*.u_* *tl_*.a_source[7:6] +-node tb.dut*.u_* *tl_*.d_source[7:6] +-node tb.dut.top_darjeeling *tl_*.a_param +-node tb.dut.top_darjeeling *tl_*.a_user.rsvd +-node tb.dut.top_darjeeling *tl_*.d_param +-node tb.dut.top_darjeeling *tl_*.d_opcode[2:1] +-node tb.dut.top_darjeeling *tl_*.a_source[7:6] +-node tb.dut.top_darjeeling *tl_*.d_source[7:6] + +// [LOW_RISK] Exclude the full TL a_address signal on all pass-through hierarchies. We instead look +// at the full coverage of this signal directly at the host or at the device. +-node tb.dut.top_darjeeling *tl_*.a_address +-node tb.dut.top_darjeeling.u_xbar_* tl_*.a_address + +// [UNR] Exclude unused address bits based on IP address range. It is not possible to cover this. +-node tb.dut*.u_rv_dm regs_tl_*i.a_address[20:4] +-node tb.dut*.u_rv_dm regs_tl_*i.a_address[23:22] +-node tb.dut*.u_rv_dm regs_tl_*i.a_address[28:25] +-node tb.dut*.u_rv_dm regs_tl_*i.a_address[31:30] +-node tb.dut*.u_rv_dm mem_tl_*i.a_address[17:12] +-node tb.dut*.u_rv_dm mem_tl_*i.a_address[31:19] +-node tb.dut*.u_rom_ctrl0 rom_tl_*i.a_address[31:16] +-node tb.dut*.u_rom_ctrl0 regs_tl_*i.a_address[16:7] +-node tb.dut*.u_rom_ctrl0 regs_tl_*i.a_address[23:21] +-node tb.dut*.u_rom_ctrl0 regs_tl_*i.a_address[28:25] +-node tb.dut*.u_rom_ctrl0 regs_tl_*i.a_address[31:30] +-node tb.dut*.u_rom_ctrl1 rom_tl_*i.a_address[16:16] +-node tb.dut*.u_rom_ctrl1 rom_tl_*i.a_address[31:18] +-node tb.dut*.u_rom_ctrl1 regs_tl_*i.a_address[11:7] +-node tb.dut*.u_rom_ctrl1 regs_tl_*i.a_address[16:13] +-node tb.dut*.u_rom_ctrl1 regs_tl_*i.a_address[23:21] +-node tb.dut*.u_rom_ctrl1 regs_tl_*i.a_address[28:25] +-node tb.dut*.u_rom_ctrl1 regs_tl_*i.a_address[31:30] +-node tb.dut*.u_soc_proxy core_tl_*i.a_address[15:4] +-node tb.dut*.u_soc_proxy core_tl_*i.a_address[24:18] +-node tb.dut*.u_soc_proxy core_tl_*i.a_address[28:26] +-node tb.dut*.u_soc_proxy core_tl_*i.a_address[31:30] +-node tb.dut*.u_soc_proxy ctn_tl_*i.a_address[31:31] +-node tb.dut*.u_hmac tl_*i.a_address[15:13] +-node tb.dut*.u_hmac tl_*i.a_address[19:17] +-node tb.dut*.u_hmac tl_*i.a_address[23:21] +-node tb.dut*.u_hmac tl_*i.a_address[28:25] +-node tb.dut*.u_hmac tl_*i.a_address[31:30] +-node tb.dut*.u_kmac tl_*i.a_address[16:12] +-node tb.dut*.u_kmac tl_*i.a_address[19:18] +-node tb.dut*.u_kmac tl_*i.a_address[23:21] +-node tb.dut*.u_kmac tl_*i.a_address[28:25] +-node tb.dut*.u_kmac tl_*i.a_address[31:30] +-node tb.dut*.u_aes tl_*i.a_address[19:8] +-node tb.dut*.u_aes tl_*i.a_address[23:21] +-node tb.dut*.u_aes tl_*i.a_address[28:25] +-node tb.dut*.u_aes tl_*i.a_address[31:30] +-node tb.dut*.u_csrng tl_*i.a_address[15:7] +-node tb.dut*.u_csrng tl_*i.a_address[17:17] +-node tb.dut*.u_csrng tl_*i.a_address[19:19] +-node tb.dut*.u_csrng tl_*i.a_address[23:21] +-node tb.dut*.u_csrng tl_*i.a_address[28:25] +-node tb.dut*.u_csrng tl_*i.a_address[31:30] +-node tb.dut*.u_edn0 tl_*i.a_address[15:7] +-node tb.dut*.u_edn0 tl_*i.a_address[19:19] +-node tb.dut*.u_edn0 tl_*i.a_address[23:21] +-node tb.dut*.u_edn0 tl_*i.a_address[28:25] +-node tb.dut*.u_edn0 tl_*i.a_address[31:30] +-node tb.dut*.u_edn1 tl_*i.a_address[18:7] +-node tb.dut*.u_edn1 tl_*i.a_address[23:21] +-node tb.dut*.u_edn1 tl_*i.a_address[28:25] +-node tb.dut*.u_edn1 tl_*i.a_address[31:30] +-node tb.dut*.u_rv_plic tl_*i.a_address[28:28] +-node tb.dut*.u_rv_plic tl_*i.a_address[31:30] +-node tb.dut*.u_otbn tl_*i.a_address[19:18] +-node tb.dut*.u_otbn tl_*i.a_address[23:21] +-node tb.dut*.u_otbn tl_*i.a_address[28:25] +-node tb.dut*.u_otbn tl_*i.a_address[31:30] +-node tb.dut*.u_keymgr_dpe tl_*i.a_address[17:8] +-node tb.dut*.u_keymgr_dpe tl_*i.a_address[19:19] +-node tb.dut*.u_keymgr_dpe tl_*i.a_address[23:21] +-node tb.dut*.u_keymgr_dpe tl_*i.a_address[28:25] +-node tb.dut*.u_keymgr_dpe tl_*i.a_address[31:30] +-node tb.dut*.u_rv_core_ibex cfg_tl_*i.a_address[15:8] +-node tb.dut*.u_rv_core_ibex cfg_tl_*i.a_address[23:21] +-node tb.dut*.u_rv_core_ibex cfg_tl_*i.a_address[28:25] +-node tb.dut*.u_rv_core_ibex cfg_tl_*i.a_address[31:30] +-node tb.dut*.u_sram_ctrl_main regs_tl_*i.a_address[17:6] +-node tb.dut*.u_sram_ctrl_main regs_tl_*i.a_address[23:21] +-node tb.dut*.u_sram_ctrl_main regs_tl_*i.a_address[28:25] +-node tb.dut*.u_sram_ctrl_main regs_tl_*i.a_address[31:30] +-node tb.dut*.u_sram_ctrl_main ram_tl_*i.a_address[27:16] +-node tb.dut*.u_sram_ctrl_main ram_tl_*i.a_address[31:29] +-node tb.dut*.u_sram_ctrl_mbox regs_tl_*i.a_address[15:6] +-node tb.dut*.u_sram_ctrl_mbox regs_tl_*i.a_address[17:17] +-node tb.dut*.u_sram_ctrl_mbox regs_tl_*i.a_address[23:21] +-node tb.dut*.u_sram_ctrl_mbox regs_tl_*i.a_address[28:25] +-node tb.dut*.u_sram_ctrl_mbox regs_tl_*i.a_address[31:30] +-node tb.dut*.u_sram_ctrl_mbox ram_tl_*i.a_address[23:12] +-node tb.dut*.u_sram_ctrl_mbox ram_tl_*i.a_address[27:25] +-node tb.dut*.u_sram_ctrl_mbox ram_tl_*i.a_address[31:29] +-node tb.dut*.u_dma tl_*i.a_address[15:9] +-node tb.dut*.u_dma tl_*i.a_address[24:17] +-node tb.dut*.u_dma tl_*i.a_address[28:26] +-node tb.dut*.u_dma tl_*i.a_address[31:30] +-node tb.dut*.u_mbx0 core_tl_*i.a_address[24:7] +-node tb.dut*.u_mbx0 core_tl_*i.a_address[28:26] +-node tb.dut*.u_mbx0 core_tl_*i.a_address[31:30] +-node tb.dut*.u_mbx1 core_tl_*i.a_address[7:7] +-node tb.dut*.u_mbx1 core_tl_*i.a_address[24:9] +-node tb.dut*.u_mbx1 core_tl_*i.a_address[28:26] +-node tb.dut*.u_mbx1 core_tl_*i.a_address[31:30] +-node tb.dut*.u_mbx2 core_tl_*i.a_address[8:7] +-node tb.dut*.u_mbx2 core_tl_*i.a_address[24:10] +-node tb.dut*.u_mbx2 core_tl_*i.a_address[28:26] +-node tb.dut*.u_mbx2 core_tl_*i.a_address[31:30] +-node tb.dut*.u_mbx3 core_tl_*i.a_address[7:7] +-node tb.dut*.u_mbx3 core_tl_*i.a_address[24:10] +-node tb.dut*.u_mbx3 core_tl_*i.a_address[28:26] +-node tb.dut*.u_mbx3 core_tl_*i.a_address[31:30] +-node tb.dut*.u_mbx4 core_tl_*i.a_address[9:7] +-node tb.dut*.u_mbx4 core_tl_*i.a_address[24:11] +-node tb.dut*.u_mbx4 core_tl_*i.a_address[28:26] +-node tb.dut*.u_mbx4 core_tl_*i.a_address[31:30] +-node tb.dut*.u_mbx5 core_tl_*i.a_address[7:7] +-node tb.dut*.u_mbx5 core_tl_*i.a_address[9:9] +-node tb.dut*.u_mbx5 core_tl_*i.a_address[24:11] +-node tb.dut*.u_mbx5 core_tl_*i.a_address[28:26] +-node tb.dut*.u_mbx5 core_tl_*i.a_address[31:30] +-node tb.dut*.u_mbx6 core_tl_*i.a_address[8:7] +-node tb.dut*.u_mbx6 core_tl_*i.a_address[24:11] +-node tb.dut*.u_mbx6 core_tl_*i.a_address[28:26] +-node tb.dut*.u_mbx6 core_tl_*i.a_address[31:30] +-node tb.dut*.u_mbx_jtag core_tl_*i.a_address[10:7] +-node tb.dut*.u_mbx_jtag core_tl_*i.a_address[24:12] +-node tb.dut*.u_mbx_jtag core_tl_*i.a_address[28:26] +-node tb.dut*.u_mbx_jtag core_tl_*i.a_address[31:30] +-node tb.dut*.u_mbx_pcie0 core_tl_*i.a_address[17:7] +-node tb.dut*.u_mbx_pcie0 core_tl_*i.a_address[24:19] +-node tb.dut*.u_mbx_pcie0 core_tl_*i.a_address[28:26] +-node tb.dut*.u_mbx_pcie0 core_tl_*i.a_address[31:30] +-node tb.dut*.u_mbx_pcie1 core_tl_*i.a_address[7:7] +-node tb.dut*.u_mbx_pcie1 core_tl_*i.a_address[17:9] +-node tb.dut*.u_mbx_pcie1 core_tl_*i.a_address[24:19] +-node tb.dut*.u_mbx_pcie1 core_tl_*i.a_address[28:26] +-node tb.dut*.u_mbx_pcie1 core_tl_*i.a_address[31:30] +-node tb.dut*.u_uart0 tl_*i.a_address[15:6] +-node tb.dut*.u_uart0 tl_*i.a_address[27:17] +-node tb.dut*.u_uart0 tl_*i.a_address[31:30] +-node tb.dut*.u_i2c0 tl_*i.a_address[18:7] +-node tb.dut*.u_i2c0 tl_*i.a_address[27:20] +-node tb.dut*.u_i2c0 tl_*i.a_address[31:30] +-node tb.dut*.u_gpio tl_*i.a_address[27:7] +-node tb.dut*.u_gpio tl_*i.a_address[31:30] +-node tb.dut*.u_spi_host0 tl_*i.a_address[19:6] +-node tb.dut*.u_spi_host0 tl_*i.a_address[27:22] +-node tb.dut*.u_spi_host0 tl_*i.a_address[31:30] +-node tb.dut*.u_spi_device tl_*i.a_address[15:13] +-node tb.dut*.u_spi_device tl_*i.a_address[19:17] +-node tb.dut*.u_spi_device tl_*i.a_address[27:22] +-node tb.dut*.u_spi_device tl_*i.a_address[31:30] +-node tb.dut*.u_rv_timer tl_*i.a_address[19:9] +-node tb.dut*.u_rv_timer tl_*i.a_address[27:21] +-node tb.dut*.u_rv_timer tl_*i.a_address[31:30] +-node tb.dut*.u_pwrmgr_aon tl_*i.a_address[21:7] +-node tb.dut*.u_pwrmgr_aon tl_*i.a_address[27:23] +-node tb.dut*.u_pwrmgr_aon tl_*i.a_address[31:30] +-node tb.dut*.u_rstmgr_aon tl_*i.a_address[15:7] +-node tb.dut*.u_rstmgr_aon tl_*i.a_address[21:17] +-node tb.dut*.u_rstmgr_aon tl_*i.a_address[27:23] +-node tb.dut*.u_rstmgr_aon tl_*i.a_address[31:30] +-node tb.dut*.u_clkmgr_aon tl_*i.a_address[16:7] +-node tb.dut*.u_clkmgr_aon tl_*i.a_address[21:18] +-node tb.dut*.u_clkmgr_aon tl_*i.a_address[27:23] +-node tb.dut*.u_clkmgr_aon tl_*i.a_address[31:30] +-node tb.dut*.u_pinmux_aon tl_*i.a_address[16:11] +-node tb.dut*.u_pinmux_aon tl_*i.a_address[21:19] +-node tb.dut*.u_pinmux_aon tl_*i.a_address[27:23] +-node tb.dut*.u_pinmux_aon tl_*i.a_address[31:30] +-node tb.dut*.u_otp_ctrl core_tl_*i.a_address[15:12] +-node tb.dut*.u_otp_ctrl core_tl_*i.a_address[19:18] +-node tb.dut*.u_otp_ctrl core_tl_*i.a_address[27:21] +-node tb.dut*.u_otp_ctrl core_tl_*i.a_address[31:30] +-node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[14:5] +-node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[19:18] +-node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[27:21] +-node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[31:30] +-node tb.dut*.u_lc_ctrl regs_tl_*i.a_address[17:8] +-node tb.dut*.u_lc_ctrl regs_tl_*i.a_address[19:19] +-node tb.dut*.u_lc_ctrl regs_tl_*i.a_address[27:21] +-node tb.dut*.u_lc_ctrl regs_tl_*i.a_address[31:30] +-node tb.dut*.u_sensor_ctrl tl_*i.a_address[16:6] +-node tb.dut*.u_sensor_ctrl tl_*i.a_address[27:18] +-node tb.dut*.u_sensor_ctrl tl_*i.a_address[31:30] +-node tb.dut*.u_alert_handler tl_*i.a_address[15:11] +-node tb.dut*.u_alert_handler tl_*i.a_address[17:17] +-node tb.dut*.u_alert_handler tl_*i.a_address[19:19] +-node tb.dut*.u_alert_handler tl_*i.a_address[27:21] +-node tb.dut*.u_alert_handler tl_*i.a_address[31:30] +-node tb.dut*.u_sram_ctrl_ret_aon regs_tl_*i.a_address[19:6] +-node tb.dut*.u_sram_ctrl_ret_aon regs_tl_*i.a_address[21:21] +-node tb.dut*.u_sram_ctrl_ret_aon regs_tl_*i.a_address[27:23] +-node tb.dut*.u_sram_ctrl_ret_aon regs_tl_*i.a_address[31:30] +-node tb.dut*.u_sram_ctrl_ret_aon ram_tl_*i.a_address[20:12] +-node tb.dut*.u_sram_ctrl_ret_aon ram_tl_*i.a_address[27:23] +-node tb.dut*.u_sram_ctrl_ret_aon ram_tl_*i.a_address[31:30] +-node tb.dut*.u_aon_timer_aon tl_*i.a_address[15:6] +-node tb.dut*.u_aon_timer_aon tl_*i.a_address[21:19] +-node tb.dut*.u_aon_timer_aon tl_*i.a_address[27:23] +-node tb.dut*.u_aon_timer_aon tl_*i.a_address[31:30] +-node tb.dut*.u_ast tl_*i.a_address[18:10] +-node tb.dut*.u_ast tl_*i.a_address[21:20] +-node tb.dut*.u_ast tl_*i.a_address[27:23] +-node tb.dut*.u_ast tl_*i.a_address[31:30] +-node tb.dut*.u_mbx0 soc_tl_*i.a_address[11:5] +-node tb.dut*.u_mbx0 soc_tl_*i.a_address[13:13] +-node tb.dut*.u_mbx0 soc_tl_*i.a_address[16:15] +-node tb.dut*.u_mbx0 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx0 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx0 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[7:5] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[11:9] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[13:13] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[16:15] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[8:5] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[11:10] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[13:13] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[16:15] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[7:5] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[11:10] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[13:13] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[16:15] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[9:5] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[11:11] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[13:13] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[16:15] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[7:5] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[9:9] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[11:11] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[13:13] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[16:15] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx6 soc_tl_*i.a_address[8:5] +-node tb.dut*.u_mbx6 soc_tl_*i.a_address[11:11] +-node tb.dut*.u_mbx6 soc_tl_*i.a_address[13:13] +-node tb.dut*.u_mbx6 soc_tl_*i.a_address[16:15] +-node tb.dut*.u_mbx6 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx6 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx6 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx_pcie0 soc_tl_*i.a_address[7:5] +-node tb.dut*.u_mbx_pcie0 soc_tl_*i.a_address[16:9] +-node tb.dut*.u_mbx_pcie0 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx_pcie0 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx_pcie0 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx_pcie1 soc_tl_*i.a_address[8:5] +-node tb.dut*.u_mbx_pcie1 soc_tl_*i.a_address[16:10] +-node tb.dut*.u_mbx_pcie1 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx_pcie1 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx_pcie1 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_rv_dm dbg_tl_*i.a_address[31:9] +-node tb.dut*.u_mbx_jtag soc_tl_*i.a_address[11:5] +-node tb.dut*.u_mbx_jtag soc_tl_*i.a_address[31:13] +-node tb.dut*.u_lc_ctrl dmi_tl_*i.a_address[16:12] +-node tb.dut*.u_lc_ctrl dmi_tl_*i.a_address[31:18] diff --git a/hw/top_darjeeling/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_darjeeling/dv/env/autogen/chip_env_pkg__params.sv new file mode 100644 index 0000000000000..19e4423eca468 --- /dev/null +++ b/hw/top_darjeeling/dv/env/autogen/chip_env_pkg__params.sv @@ -0,0 +1,109 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Generated by topgen.py + +parameter string LIST_OF_ALERTS[] = { + "uart0_fatal_fault", + "gpio_fatal_fault", + "spi_device_fatal_fault", + "i2c0_fatal_fault", + "rv_timer_fatal_fault", + "otp_ctrl_fatal_macro_error", + "otp_ctrl_fatal_check_error", + "otp_ctrl_fatal_bus_integ_error", + "otp_ctrl_fatal_prim_otp_alert", + "otp_ctrl_recov_prim_otp_alert", + "lc_ctrl_fatal_prog_error", + "lc_ctrl_fatal_state_error", + "lc_ctrl_fatal_bus_integ_error", + "spi_host0_fatal_fault", + "pwrmgr_aon_fatal_fault", + "rstmgr_aon_fatal_fault", + "rstmgr_aon_fatal_cnsty_fault", + "clkmgr_aon_recov_fault", + "clkmgr_aon_fatal_fault", + "pinmux_aon_fatal_fault", + "aon_timer_aon_fatal_fault", + "sensor_ctrl_recov_alert", + "sensor_ctrl_fatal_alert", + "soc_proxy_fatal_alert_intg", + "soc_proxy_fatal_alert_external_0", + "soc_proxy_fatal_alert_external_1", + "soc_proxy_fatal_alert_external_2", + "soc_proxy_fatal_alert_external_3", + "soc_proxy_fatal_alert_external_4", + "soc_proxy_fatal_alert_external_5", + "soc_proxy_fatal_alert_external_6", + "soc_proxy_fatal_alert_external_7", + "soc_proxy_fatal_alert_external_8", + "soc_proxy_fatal_alert_external_9", + "soc_proxy_fatal_alert_external_10", + "soc_proxy_fatal_alert_external_11", + "soc_proxy_fatal_alert_external_12", + "soc_proxy_fatal_alert_external_13", + "soc_proxy_fatal_alert_external_14", + "soc_proxy_fatal_alert_external_15", + "soc_proxy_fatal_alert_external_16", + "soc_proxy_fatal_alert_external_17", + "soc_proxy_fatal_alert_external_18", + "soc_proxy_fatal_alert_external_19", + "soc_proxy_fatal_alert_external_20", + "soc_proxy_fatal_alert_external_21", + "soc_proxy_fatal_alert_external_22", + "soc_proxy_fatal_alert_external_23", + "soc_proxy_recov_alert_external_0", + "soc_proxy_recov_alert_external_1", + "soc_proxy_recov_alert_external_2", + "soc_proxy_recov_alert_external_3", + "sram_ctrl_ret_aon_fatal_error", + "rv_dm_fatal_fault", + "rv_plic_fatal_fault", + "aes_recov_ctrl_update_err", + "aes_fatal_fault", + "hmac_fatal_fault", + "kmac_recov_operation_err", + "kmac_fatal_fault_err", + "otbn_fatal", + "otbn_recov", + "keymgr_dpe_recov_operation_err", + "keymgr_dpe_fatal_fault_err", + "csrng_recov_alert", + "csrng_fatal_alert", + "edn0_recov_alert", + "edn0_fatal_alert", + "edn1_recov_alert", + "edn1_fatal_alert", + "sram_ctrl_main_fatal_error", + "sram_ctrl_mbox_fatal_error", + "rom_ctrl0_fatal", + "rom_ctrl1_fatal", + "dma_fatal_fault", + "mbx0_fatal_fault", + "mbx0_recov_fault", + "mbx1_fatal_fault", + "mbx1_recov_fault", + "mbx2_fatal_fault", + "mbx2_recov_fault", + "mbx3_fatal_fault", + "mbx3_recov_fault", + "mbx4_fatal_fault", + "mbx4_recov_fault", + "mbx5_fatal_fault", + "mbx5_recov_fault", + "mbx6_fatal_fault", + "mbx6_recov_fault", + "mbx_jtag_fatal_fault", + "mbx_jtag_recov_fault", + "mbx_pcie0_fatal_fault", + "mbx_pcie0_recov_fault", + "mbx_pcie1_fatal_fault", + "mbx_pcie1_recov_fault", + "rv_core_ibex_fatal_sw_err", + "rv_core_ibex_recov_sw_err", + "rv_core_ibex_fatal_hw_err", + "rv_core_ibex_recov_hw_err" +}; + +parameter uint NUM_ALERTS = 99; diff --git a/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson b/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson new file mode 100644 index 0000000000000..cc11eb299ce96 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson @@ -0,0 +1,134 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson -o hw/top_darjeeling/ + +{ + name: dbg + clock_srcs: + { + clk_dbg_i: main + clk_peri_i: io_div4 + } + clock_group: infra + reset: rst_dbg_ni + reset_connections: + { + rst_dbg_ni: + { + name: lc + domain: "0" + } + rst_peri_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_dbg_i: clkmgr_aon_clocks.clk_main_infra + clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + connections: + { + dbg: + [ + rv_dm.dbg + mbx_jtag.soc + lc_ctrl.dmi + ] + } + nodes: + [ + { + name: dbg + type: host + addr_space: soc_dbg + clock: clk_dbg_i + reset: rst_dbg_ni + xbar: true + pipeline: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: rv_dm.dbg + type: device + clock: clk_dbg_i + reset: rst_dbg_ni + pipeline: false + inst_type: rv_dm + addr_range: + [ + { + base_addrs: + { + soc_dbg: 0x0 + } + size_byte: 0x200 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_jtag.soc + type: device + clock: clk_dbg_i + reset: rst_dbg_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_dbg: 0x1000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: lc_ctrl.dmi + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: lc_ctrl + addr_range: + [ + { + base_addrs: + { + soc_dbg: 0x20000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + ] + addr_spaces: + [ + soc_dbg + ] + clock: clk_dbg_i + type: xbar +} diff --git a/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.hjson b/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.hjson new file mode 100644 index 0000000000000..7c0bbc703178a --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.hjson @@ -0,0 +1,41 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_dbg comportable IP spec generated by `tlgen.py` tool +{ name: "xbar_dbg" + clock_primary: "" + other_clock_list: [] + reset_primary: "" + other_reset_list: [] + //available_input_list: [] + + inter_signal_list: [ + // host + { struct: "tl" + type: "req_rsp" + name: "tl_dbg" + act: "rsp" + package: "tlul_pkg" + } + // device + { struct: "tl" + type: "req_rsp" + name: "tl_rv_dm__dbg" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_jtag__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_lc_ctrl__dmi" + act: "req" + package: "tlul_pkg" + } + ] +} diff --git a/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/tb__xbar_connect.sv new file mode 100644 index 0000000000000..4dc615e6ee5c3 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/tb__xbar_connect.sv @@ -0,0 +1,25 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__xbar_connect generated by `tlgen.py` tool + +xbar_dbg dut(); + +`DRIVE_CLK(clk_dbg_i) +`DRIVE_CLK(clk_peri_i) + +initial force dut.clk_dbg_i = clk_dbg_i; +initial force dut.clk_peri_i = clk_peri_i; + +// TODO, all resets tie together +initial force dut.rst_dbg_ni = rst_n; +initial force dut.rst_peri_ni = rst_n; + +// Host TileLink interface connections +`CONNECT_TL_HOST_IF(dbg, dut, clk_dbg_i, rst_n) + +// Device TileLink interface connections +`CONNECT_TL_DEVICE_IF(rv_dm__dbg, dut, clk_dbg_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx_jtag__soc, dut, clk_dbg_i, rst_n) +`CONNECT_TL_DEVICE_IF(lc_ctrl__dmi, dut, clk_peri_i, rst_n) diff --git a/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_cov_excl.el b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_cov_excl.el new file mode 100644 index 0000000000000..fa86a7e7963b0 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_cov_excl.el @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cov_excl.el generated by `tlgen.py` tool + +ANNOTATION: "[NON_RTL]" +MODULE: uvm_pkg +Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion" +Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion" + +ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim" +MODULE: xbar_dbg +Block 1 "0" "assign unused_scanmode = scanmode_i;" diff --git a/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_cover.cfg b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_cover.cfg new file mode 100644 index 0000000000000..572c0f62c0cdb --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_cover.cfg @@ -0,0 +1,34 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cover.cfg generated by `tlgen.py` tool + ++tree tb.dut +-module pins_if // DV construct. +-module clk_rst_if // DV construct. + +-assert legalAOpcodeErr_A +-assert sizeGTEMaskErr_A +-assert sizeMatchesMaskErr_A +-assert addrSizeAlignedErr_A + +// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after. +-node tb.dut tl_*.a_param +-node tb.dut tl_*.d_param +-node tb.dut tl_*.d_opcode[2:1] + +-moduletree prim_cdc_rand_delay // exclude DV construct. + +// [UNR] these device address bits are always 0 +-node tb.dut tl_rv_dm__dbg_o.a_address[31:9] +-node tb.dut tl_mbx_jtag__soc_o.a_address[11:5] +-node tb.dut tl_mbx_jtag__soc_o.a_address[31:13] +-node tb.dut tl_lc_ctrl__dmi_o.a_address[16:12] +-node tb.dut tl_lc_ctrl__dmi_o.a_address[31:18] + +begin tgl + -tree tb + +tree tb.dut 1 + -node tb.dut.scanmode_i +end diff --git a/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.core b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.core new file mode 100644 index 0000000000000..99c8ffb5a7805 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_dbg_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_xbar_dbg_bind:0.1" +description: "XBAR dbg assertion bind" +filesets: + files_dv: + files: + - xbar_dbg_bind.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.sv b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.sv new file mode 100644 index 0000000000000..a014706e8c7d2 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.sv @@ -0,0 +1,36 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_dbg_bind module generated by `tlgen.py` tool for assertions +module xbar_dbg_bind; +`ifndef GATE_LEVEL + // Host interfaces + bind xbar_dbg tlul_assert #(.EndpointType("Device")) tlul_assert_host_dbg ( + .clk_i (clk_dbg_i), + .rst_ni (rst_dbg_ni), + .h2d (tl_dbg_i), + .d2h (tl_dbg_o) + ); + + // Device interfaces + bind xbar_dbg tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_dm__dbg ( + .clk_i (clk_dbg_i), + .rst_ni (rst_dbg_ni), + .h2d (tl_rv_dm__dbg_o), + .d2h (tl_rv_dm__dbg_i) + ); + bind xbar_dbg tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx_jtag__soc ( + .clk_i (clk_dbg_i), + .rst_ni (rst_dbg_ni), + .h2d (tl_mbx_jtag__soc_o), + .d2h (tl_mbx_jtag__soc_i) + ); + bind xbar_dbg tlul_assert #(.EndpointType("Host")) tlul_assert_device_lc_ctrl__dmi ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_lc_ctrl__dmi_o), + .d2h (tl_lc_ctrl__dmi_i) + ); +`endif +endmodule diff --git a/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_dbg_sim.core b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_dbg_sim.core new file mode 100644 index 0000000000000..f2d0e5e02cf0d --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_dbg_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_dbg_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_xbar_dbg_sim:0.1" +description: "XBAR DV sim target" +filesets: + files_dv: + depend: + - lowrisc:top_darjeeling:xbar_dbg + - lowrisc:dv:dv_utils + - lowrisc:dv:xbar_tb + - lowrisc:dv:top_darjeeling_xbar_dbg_bind + files: + - tb__xbar_connect.sv: {is_include_file: true} + - xbar_env_pkg__params.sv: {is_include_file: true} + file_type: systemVerilogSource + + +targets: + sim: &sim_target + toplevel: xbar_tb_top + filesets: + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_dbg_sim_cfg.hjson b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_dbg_sim_cfg.hjson new file mode 100644 index 0000000000000..2edbe882e3060 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_dbg_sim_cfg.hjson @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_dbg_sim_cfg.hjson file generated by `tlgen.py` tool +{ + name: xbar_dbg + + // Top level dut name (sv module). + dut: xbar_dbg + + // The name of the chip this XBAR configuration is made for. + top_chip: top_darjeeling + + // Testplan hjson file. + testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson" + + // Add xbar_main specific exclusion files. + vcs_cov_excl_files: ["{proj_root}/hw/top_darjeeling/ip/{dut}/dv/autogen/xbar_cov_excl.el"] + + // replace common cover.cfg with a generated one, which includes xbar toggle exclusions + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/top_darjeeling/ip/{dut}/dv/autogen/xbar_cover.cfg" + } + ] + // Import additional common sim cfg files. + import_cfgs: [// xbar common sim cfg file + "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"] +} diff --git a/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_env_pkg__params.sv new file mode 100644 index 0000000000000..2b7347158097b --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_dbg/dv/autogen/xbar_env_pkg__params.sv @@ -0,0 +1,26 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_env_pkg__params generated by `tlgen.py` tool + + +// List of Xbar device memory map +tl_device_t xbar_devices[$] = '{ + '{"rv_dm__dbg", '{ + '{32'h00000000, 32'h000001ff} + }}, + '{"mbx_jtag__soc", '{ + '{32'h00001000, 32'h0000101f} + }}, + '{"lc_ctrl__dmi", '{ + '{32'h00020000, 32'h00020fff} +}}}; + + // List of Xbar hosts +tl_host_t xbar_hosts[$] = '{ + '{"dbg", 0, '{ + "rv_dm__dbg", + "mbx_jtag__soc", + "lc_ctrl__dmi"}} +}; diff --git a/hw/top_darjeeling/ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv b/hw/top_darjeeling/ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv new file mode 100644 index 0000000000000..b382767f137ca --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv @@ -0,0 +1,30 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tl_dbg package generated by `tlgen.py` tool + +package tl_dbg_pkg; + + localparam logic [31:0] ADDR_SPACE_RV_DM__DBG = 32'h 00000000; + localparam logic [31:0] ADDR_SPACE_MBX_JTAG__SOC = 32'h 00001000; + localparam logic [31:0] ADDR_SPACE_LC_CTRL__DMI = 32'h 00020000; + + localparam logic [31:0] ADDR_MASK_RV_DM__DBG = 32'h 000001ff; + localparam logic [31:0] ADDR_MASK_MBX_JTAG__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_LC_CTRL__DMI = 32'h 00000fff; + + localparam int N_HOST = 1; + localparam int N_DEVICE = 3; + + typedef enum int { + TlRvDmDbg = 0, + TlMbxJtagSoc = 1, + TlLcCtrlDmi = 2 + } tl_device_e; + + typedef enum int { + TlDbg = 0 + } tl_host_e; + +endpackage diff --git a/hw/top_darjeeling/ip/xbar_dbg/rtl/autogen/xbar_dbg.sv b/hw/top_darjeeling/ip/xbar_dbg/rtl/autogen/xbar_dbg.sv new file mode 100644 index 0000000000000..f758edb13f019 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_dbg/rtl/autogen/xbar_dbg.sv @@ -0,0 +1,125 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_dbg module generated by `tlgen.py` tool +// all reset signals should be generated from one reset signal to not make any deadlock +// +// Interconnect +// dbg +// -> s1n_4 +// -> rv_dm.dbg +// -> mbx_jtag.soc +// -> asf_5 +// -> lc_ctrl.dmi + +module xbar_dbg ( + input clk_dbg_i, + input clk_peri_i, + input rst_dbg_ni, + input rst_peri_ni, + + // Host interfaces + input tlul_pkg::tl_h2d_t tl_dbg_i, + output tlul_pkg::tl_d2h_t tl_dbg_o, + + // Device interfaces + output tlul_pkg::tl_h2d_t tl_rv_dm__dbg_o, + input tlul_pkg::tl_d2h_t tl_rv_dm__dbg_i, + output tlul_pkg::tl_h2d_t tl_mbx_jtag__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx_jtag__soc_i, + output tlul_pkg::tl_h2d_t tl_lc_ctrl__dmi_o, + input tlul_pkg::tl_d2h_t tl_lc_ctrl__dmi_i, + + input prim_mubi_pkg::mubi4_t scanmode_i +); + + import tlul_pkg::*; + import tl_dbg_pkg::*; + + // scanmode_i is currently not used, but provisioned for future use + // this assignment prevents lint warnings + logic unused_scanmode; + assign unused_scanmode = ^scanmode_i; + + tl_h2d_t tl_s1n_4_us_h2d ; + tl_d2h_t tl_s1n_4_us_d2h ; + + + tl_h2d_t tl_s1n_4_ds_h2d [3]; + tl_d2h_t tl_s1n_4_ds_d2h [3]; + + // Create steering signal + logic [1:0] dev_sel_s1n_4; + + tl_h2d_t tl_asf_5_us_h2d ; + tl_d2h_t tl_asf_5_us_d2h ; + tl_h2d_t tl_asf_5_ds_h2d ; + tl_d2h_t tl_asf_5_ds_d2h ; + + + + assign tl_rv_dm__dbg_o = tl_s1n_4_ds_h2d[0]; + assign tl_s1n_4_ds_d2h[0] = tl_rv_dm__dbg_i; + + assign tl_mbx_jtag__soc_o = tl_s1n_4_ds_h2d[1]; + assign tl_s1n_4_ds_d2h[1] = tl_mbx_jtag__soc_i; + + assign tl_asf_5_us_h2d = tl_s1n_4_ds_h2d[2]; + assign tl_s1n_4_ds_d2h[2] = tl_asf_5_us_d2h; + + assign tl_s1n_4_us_h2d = tl_dbg_i; + assign tl_dbg_o = tl_s1n_4_us_d2h; + + assign tl_lc_ctrl__dmi_o = tl_asf_5_ds_h2d; + assign tl_asf_5_ds_d2h = tl_lc_ctrl__dmi_i; + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_4 = 2'd3; + if ((tl_s1n_4_us_h2d.a_address & + ~(ADDR_MASK_RV_DM__DBG)) == ADDR_SPACE_RV_DM__DBG) begin + dev_sel_s1n_4 = 2'd0; + + end else if ((tl_s1n_4_us_h2d.a_address & + ~(ADDR_MASK_MBX_JTAG__SOC)) == ADDR_SPACE_MBX_JTAG__SOC) begin + dev_sel_s1n_4 = 2'd1; + + end else if ((tl_s1n_4_us_h2d.a_address & + ~(ADDR_MASK_LC_CTRL__DMI)) == ADDR_SPACE_LC_CTRL__DMI) begin + dev_sel_s1n_4 = 2'd2; +end + end + + + // Instantiation phase + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (12'h0), + .DRspDepth (12'h0), + .N (3) + ) u_s1n_4 ( + .clk_i (clk_dbg_i), + .rst_ni (rst_dbg_ni), + .tl_h_i (tl_s1n_4_us_h2d), + .tl_h_o (tl_s1n_4_us_d2h), + .tl_d_o (tl_s1n_4_ds_h2d), + .tl_d_i (tl_s1n_4_ds_d2h), + .dev_select_i (dev_sel_s1n_4) + ); + tlul_fifo_async #( + .ReqDepth (1), + .RspDepth (1) + ) u_asf_5 ( + .clk_h_i (clk_dbg_i), + .rst_h_ni (rst_dbg_ni), + .clk_d_i (clk_peri_i), + .rst_d_ni (rst_peri_ni), + .tl_h_i (tl_asf_5_us_h2d), + .tl_h_o (tl_asf_5_us_d2h), + .tl_d_o (tl_asf_5_ds_h2d), + .tl_d_i (tl_asf_5_ds_d2h) + ); + +endmodule diff --git a/hw/top_darjeeling/ip/xbar_dbg/xbar_dbg.core b/hw/top_darjeeling/ip/xbar_dbg/xbar_dbg.core new file mode 100644 index 0000000000000..25582d37f25e1 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_dbg/xbar_dbg.core @@ -0,0 +1,25 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_dbg core file generated by `tlgen.py` tool +name: "lowrisc:top_darjeeling:xbar_dbg:0.1" +description: "Generated RTL xbar_dbg" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:ip:lc_ctrl_pkg + files: + - rtl/autogen/tl_dbg_pkg.sv + - rtl/autogen/xbar_dbg.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: xbar_dbg diff --git a/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson new file mode 100644 index 0000000000000..f7f1449aad97c --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -0,0 +1,1121 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson -o hw/top_darjeeling/ + +{ + name: main + clock_srcs: + { + clk_main_i: main + clk_fixed_i: io_div4 + clk_usb_i: usb + } + clock_group: infra + reset: rst_main_ni + reset_connections: + { + rst_main_ni: + { + name: lc + domain: "0" + } + rst_fixed_ni: + { + name: lc_io_div4 + domain: "0" + } + rst_usb_ni: + { + name: lc_usb + domain: "0" + } + } + min_spacing: 0x100 + clock_connections: + { + clk_main_i: clkmgr_aon_clocks.clk_main_infra + clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra + clk_usb_i: clkmgr_aon_clocks.clk_usb_infra + } + domain: + [ + "0" + ] + connections: + { + rv_core_ibex.corei: + [ + rom_ctrl0.rom + rom_ctrl1.rom + rv_dm.mem + sram_ctrl_main.ram + soc_proxy.ctn + ] + rv_core_ibex.cored: + [ + rom_ctrl0.rom + rom_ctrl0.regs + rom_ctrl1.rom + rom_ctrl1.regs + rv_dm.mem + rv_dm.regs + sram_ctrl_main.ram + peri + aes + csrng + edn0 + edn1 + hmac + rv_plic + otbn + keymgr_dpe + kmac + sram_ctrl_main.regs + rv_core_ibex.cfg + sram_ctrl_mbox.ram + sram_ctrl_mbox.regs + soc_proxy.ctn + soc_proxy.core + dma + mbx0.core + mbx1.core + mbx2.core + mbx3.core + mbx4.core + mbx5.core + mbx6.core + mbx_jtag.core + mbx_pcie0.core + mbx_pcie1.core + ] + rv_dm.sba: + [ + rom_ctrl0.rom + rom_ctrl0.regs + rom_ctrl1.rom + rom_ctrl1.regs + rv_dm.mem + rv_dm.regs + sram_ctrl_main.ram + peri + aes + csrng + edn0 + edn1 + hmac + rv_plic + otbn + keymgr_dpe + kmac + sram_ctrl_main.regs + rv_core_ibex.cfg + sram_ctrl_mbox.ram + sram_ctrl_mbox.regs + soc_proxy.ctn + soc_proxy.core + dma + mbx0.core + mbx1.core + mbx2.core + mbx3.core + mbx4.core + mbx5.core + mbx6.core + mbx_jtag.core + mbx_pcie0.core + mbx_pcie1.core + ] + dma.host: + [ + sram_ctrl_main.ram + sram_ctrl_mbox.ram + aes + hmac + otbn + keymgr_dpe + kmac + soc_proxy.ctn + peri + ] + mbx0.sram: + [ + sram_ctrl_mbox.ram + ] + mbx1.sram: + [ + sram_ctrl_mbox.ram + ] + mbx2.sram: + [ + sram_ctrl_mbox.ram + ] + mbx3.sram: + [ + sram_ctrl_mbox.ram + ] + mbx4.sram: + [ + sram_ctrl_mbox.ram + ] + mbx5.sram: + [ + sram_ctrl_mbox.ram + ] + mbx6.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_jtag.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_pcie0.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_pcie1.sram: + [ + sram_ctrl_mbox.ram + ] + } + nodes: + [ + { + name: rv_core_ibex.corei + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: rv_core_ibex.cored + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: rv_dm.sba + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + xbar: false + stub: false + inst_type: "" + pipeline: true + } + { + name: rv_dm.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rv_dm + addr_range: + [ + { + base_addrs: + { + hart: 0x21200000 + } + size_byte: 0x10 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rv_dm.mem + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rv_dm + addr_range: + [ + { + base_addrs: + { + hart: 0x40000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rom_ctrl0.rom + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: true + rsp_fifo_pass: false + inst_type: rom_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x8000 + } + size_byte: 0x8000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rom_ctrl0.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rom_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x211e0000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rom_ctrl1.rom + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: true + rsp_fifo_pass: false + inst_type: rom_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x20000 + } + size_byte: 0x10000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rom_ctrl1.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rom_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x211e1000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: peri + type: device + clock: clk_fixed_i + reset: rst_fixed_ni + req_fifo_pass: false + rsp_fifo_pass: false + xbar: true + stub: false + pipeline: true + addr_space: hart + addr_range: + [ + { + base_addrs: + { + hart: 0x30000000 + } + size_byte: 0x800000 + } + ] + } + { + name: soc_proxy.core + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: soc_proxy + addr_range: + [ + { + base_addrs: + { + hart: 0x22030000 + } + size_byte: 0x10 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: soc_proxy.ctn + type: device + clock: clk_main_i + reset: rst_main_ni + pipefile: false + inst_type: soc_proxy + addr_range: + [ + { + base_addrs: + { + hart: 0x40000000 + } + size_byte: 0x40000000 + } + ] + xbar: false + stub: false + pipeline: true + req_fifo_pass: true + } + { + name: hmac + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: hmac + addr_range: + [ + { + base_addrs: + { + hart: 0x21110000 + } + size_byte: 0x2000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: kmac + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: kmac + addr_range: + [ + { + base_addrs: + { + hart: 0x21120000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: aes + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: aes + addr_range: + [ + { + base_addrs: + { + hart: 0x21100000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: csrng + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: csrng + addr_range: + [ + { + base_addrs: + { + hart: 0x21150000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: edn0 + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: edn + addr_range: + [ + { + base_addrs: + { + hart: 0x21170000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: edn1 + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: edn + addr_range: + [ + { + base_addrs: + { + hart: 0x21180000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rv_plic + type: device + clock: clk_main_i + reset: rst_main_ni + inst_type: rv_plic + req_fifo_pass: false + rsp_fifo_pass: false + addr_range: + [ + { + base_addrs: + { + hart: 0x28000000 + } + size_byte: 0x8000000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: otbn + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: otbn + addr_range: + [ + { + base_addrs: + { + hart: 0x21130000 + } + size_byte: 0x10000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: keymgr_dpe + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: keymgr_dpe + addr_range: + [ + { + base_addrs: + { + hart: 0x21140000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rv_core_ibex.cfg + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rv_core_ibex + addr_range: + [ + { + base_addrs: + { + hart: 0x211f0000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: sram_ctrl_main.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x211c0000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: sram_ctrl_main.ram + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x10000000 + } + size_byte: 0x10000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_mbox.regs + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x211d0000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_mbox.ram + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x11000000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: dma + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: dma + addr_range: + [ + { + base_addrs: + { + hart: 0x22010000 + } + size_byte: 0x200 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: dma.host + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx0.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx0.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx1.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000100 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx1.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx2.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000200 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx2.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx3.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000300 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx3.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx4.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000400 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx4.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx5.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000500 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx5.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx6.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000600 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx6.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_jtag.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000800 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_jtag.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_pcie0.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22040000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie0.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_pcie1.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22040100 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie1.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + ] + addr_spaces: + [ + hart + ] + clock: clk_main_i + type: xbar +} diff --git a/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.hjson new file mode 100644 index 0000000000000..4e9d2fc05e67a --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.hjson @@ -0,0 +1,305 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main comportable IP spec generated by `tlgen.py` tool +{ name: "xbar_main" + clock_primary: "" + other_clock_list: [] + reset_primary: "" + other_reset_list: [] + //available_input_list: [] + + inter_signal_list: [ + // host + { struct: "tl" + type: "req_rsp" + name: "tl_rv_core_ibex__corei" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rv_core_ibex__cored" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rv_dm__sba" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_dma__host" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx0__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx1__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx2__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx3__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx4__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx5__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx6__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_jtag__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie0__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie1__sram" + act: "rsp" + package: "tlul_pkg" + } + // device + { struct: "tl" + type: "req_rsp" + name: "tl_rv_dm__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rv_dm__mem" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rom_ctrl0__rom" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rom_ctrl0__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rom_ctrl1__rom" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rom_ctrl1__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_peri" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_soc_proxy__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_soc_proxy__ctn" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_hmac" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_kmac" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_aes" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_csrng" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_edn0" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_edn1" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rv_plic" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_otbn" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_keymgr_dpe" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rv_core_ibex__cfg" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_main__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_main__ram" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_mbox__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_mbox__ram" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_dma" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx0__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx1__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx2__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx3__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx4__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx5__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx6__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_jtag__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie0__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie1__core" + act: "req" + package: "tlul_pkg" + } + ] +} diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling/ip/xbar_main/dv/autogen/tb__xbar_connect.sv new file mode 100644 index 0000000000000..8df7f313c8450 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/tb__xbar_connect.sv @@ -0,0 +1,72 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__xbar_connect generated by `tlgen.py` tool + +xbar_main dut(); + +`DRIVE_CLK(clk_main_i) +`DRIVE_CLK(clk_fixed_i) +`DRIVE_CLK(clk_usb_i) + +initial force dut.clk_main_i = clk_main_i; +initial force dut.clk_fixed_i = clk_fixed_i; +initial force dut.clk_usb_i = clk_usb_i; + +// TODO, all resets tie together +initial force dut.rst_main_ni = rst_n; +initial force dut.rst_fixed_ni = rst_n; +initial force dut.rst_usb_ni = rst_n; + +// Host TileLink interface connections +`CONNECT_TL_HOST_IF(rv_core_ibex__corei, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(rv_core_ibex__cored, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(rv_dm__sba, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(dma__host, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx0__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx1__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx2__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx3__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx4__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx5__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx6__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx_jtag__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx_pcie0__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx_pcie1__sram, dut, clk_main_i, rst_n) + +// Device TileLink interface connections +`CONNECT_TL_DEVICE_IF(rv_dm__regs, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rv_dm__mem, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rom_ctrl0__rom, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rom_ctrl0__regs, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rom_ctrl1__rom, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rom_ctrl1__regs, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(peri, dut, clk_fixed_i, rst_n) +`CONNECT_TL_DEVICE_IF(soc_proxy__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(soc_proxy__ctn, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(hmac, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(kmac, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(aes, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(csrng, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(edn0, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(edn1, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rv_plic, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(otbn, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(keymgr_dpe, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rv_core_ibex__cfg, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_main__regs, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_main__ram, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_mbox__regs, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_mbox__ram, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(dma, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx0__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx1__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx2__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx3__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx4__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx5__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx6__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx_jtag__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx_pcie0__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx_pcie1__core, dut, clk_main_i, rst_n) diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cov_excl.el b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cov_excl.el new file mode 100644 index 0000000000000..5e205b00fc233 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cov_excl.el @@ -0,0 +1,71 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cov_excl.el generated by `tlgen.py` tool + +ANNOTATION: "[NON_RTL]" +MODULE: uvm_pkg +Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion" +Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion" + +ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim" +MODULE: xbar_main +Block 1 "0" "assign unused_scanmode = scanmode_i;" + +ANNOTATION: "[UNR]" +MODULE: prim_fifo_sync +Branch 2 "2323268504" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-" +Branch 3 "3736627057" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-" + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=2,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=3,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=4,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=5,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=6,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=7,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=8,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=9,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=10,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=11,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=12,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=13,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=14,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cover.cfg new file mode 100644 index 0000000000000..014cd4a332376 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cover.cfg @@ -0,0 +1,159 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cover.cfg generated by `tlgen.py` tool + ++tree tb.dut +-module pins_if // DV construct. +-module clk_rst_if // DV construct. + +-assert legalAOpcodeErr_A +-assert sizeGTEMaskErr_A +-assert sizeMatchesMaskErr_A +-assert addrSizeAlignedErr_A + +// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after. +-node tb.dut tl_*.a_param +-node tb.dut tl_*.d_param +-node tb.dut tl_*.d_opcode[2:1] + +-moduletree prim_cdc_rand_delay // exclude DV construct. + +// [UNR] these device address bits are always 0 +-node tb.dut tl_rv_dm__regs_o.a_address[20:4] +-node tb.dut tl_rv_dm__regs_o.a_address[23:22] +-node tb.dut tl_rv_dm__regs_o.a_address[28:25] +-node tb.dut tl_rv_dm__regs_o.a_address[31:30] +-node tb.dut tl_rv_dm__mem_o.a_address[17:12] +-node tb.dut tl_rv_dm__mem_o.a_address[31:19] +-node tb.dut tl_rom_ctrl0__rom_o.a_address[31:16] +-node tb.dut tl_rom_ctrl0__regs_o.a_address[16:7] +-node tb.dut tl_rom_ctrl0__regs_o.a_address[23:21] +-node tb.dut tl_rom_ctrl0__regs_o.a_address[28:25] +-node tb.dut tl_rom_ctrl0__regs_o.a_address[31:30] +-node tb.dut tl_rom_ctrl1__rom_o.a_address[16:16] +-node tb.dut tl_rom_ctrl1__rom_o.a_address[31:18] +-node tb.dut tl_rom_ctrl1__regs_o.a_address[11:7] +-node tb.dut tl_rom_ctrl1__regs_o.a_address[16:13] +-node tb.dut tl_rom_ctrl1__regs_o.a_address[23:21] +-node tb.dut tl_rom_ctrl1__regs_o.a_address[28:25] +-node tb.dut tl_rom_ctrl1__regs_o.a_address[31:30] +-node tb.dut tl_peri_o.a_address[27:23] +-node tb.dut tl_peri_o.a_address[31:30] +-node tb.dut tl_soc_proxy__core_o.a_address[15:4] +-node tb.dut tl_soc_proxy__core_o.a_address[24:18] +-node tb.dut tl_soc_proxy__core_o.a_address[28:26] +-node tb.dut tl_soc_proxy__core_o.a_address[31:30] +-node tb.dut tl_soc_proxy__ctn_o.a_address[31:31] +-node tb.dut tl_hmac_o.a_address[15:13] +-node tb.dut tl_hmac_o.a_address[19:17] +-node tb.dut tl_hmac_o.a_address[23:21] +-node tb.dut tl_hmac_o.a_address[28:25] +-node tb.dut tl_hmac_o.a_address[31:30] +-node tb.dut tl_kmac_o.a_address[16:12] +-node tb.dut tl_kmac_o.a_address[19:18] +-node tb.dut tl_kmac_o.a_address[23:21] +-node tb.dut tl_kmac_o.a_address[28:25] +-node tb.dut tl_kmac_o.a_address[31:30] +-node tb.dut tl_aes_o.a_address[19:8] +-node tb.dut tl_aes_o.a_address[23:21] +-node tb.dut tl_aes_o.a_address[28:25] +-node tb.dut tl_aes_o.a_address[31:30] +-node tb.dut tl_csrng_o.a_address[15:7] +-node tb.dut tl_csrng_o.a_address[17:17] +-node tb.dut tl_csrng_o.a_address[19:19] +-node tb.dut tl_csrng_o.a_address[23:21] +-node tb.dut tl_csrng_o.a_address[28:25] +-node tb.dut tl_csrng_o.a_address[31:30] +-node tb.dut tl_edn0_o.a_address[15:7] +-node tb.dut tl_edn0_o.a_address[19:19] +-node tb.dut tl_edn0_o.a_address[23:21] +-node tb.dut tl_edn0_o.a_address[28:25] +-node tb.dut tl_edn0_o.a_address[31:30] +-node tb.dut tl_edn1_o.a_address[18:7] +-node tb.dut tl_edn1_o.a_address[23:21] +-node tb.dut tl_edn1_o.a_address[28:25] +-node tb.dut tl_edn1_o.a_address[31:30] +-node tb.dut tl_rv_plic_o.a_address[28:28] +-node tb.dut tl_rv_plic_o.a_address[31:30] +-node tb.dut tl_otbn_o.a_address[19:18] +-node tb.dut tl_otbn_o.a_address[23:21] +-node tb.dut tl_otbn_o.a_address[28:25] +-node tb.dut tl_otbn_o.a_address[31:30] +-node tb.dut tl_keymgr_dpe_o.a_address[17:8] +-node tb.dut tl_keymgr_dpe_o.a_address[19:19] +-node tb.dut tl_keymgr_dpe_o.a_address[23:21] +-node tb.dut tl_keymgr_dpe_o.a_address[28:25] +-node tb.dut tl_keymgr_dpe_o.a_address[31:30] +-node tb.dut tl_rv_core_ibex__cfg_o.a_address[15:8] +-node tb.dut tl_rv_core_ibex__cfg_o.a_address[23:21] +-node tb.dut tl_rv_core_ibex__cfg_o.a_address[28:25] +-node tb.dut tl_rv_core_ibex__cfg_o.a_address[31:30] +-node tb.dut tl_sram_ctrl_main__regs_o.a_address[17:6] +-node tb.dut tl_sram_ctrl_main__regs_o.a_address[23:21] +-node tb.dut tl_sram_ctrl_main__regs_o.a_address[28:25] +-node tb.dut tl_sram_ctrl_main__regs_o.a_address[31:30] +-node tb.dut tl_sram_ctrl_main__ram_o.a_address[27:16] +-node tb.dut tl_sram_ctrl_main__ram_o.a_address[31:29] +-node tb.dut tl_sram_ctrl_mbox__regs_o.a_address[15:6] +-node tb.dut tl_sram_ctrl_mbox__regs_o.a_address[17:17] +-node tb.dut tl_sram_ctrl_mbox__regs_o.a_address[23:21] +-node tb.dut tl_sram_ctrl_mbox__regs_o.a_address[28:25] +-node tb.dut tl_sram_ctrl_mbox__regs_o.a_address[31:30] +-node tb.dut tl_sram_ctrl_mbox__ram_o.a_address[23:12] +-node tb.dut tl_sram_ctrl_mbox__ram_o.a_address[27:25] +-node tb.dut tl_sram_ctrl_mbox__ram_o.a_address[31:29] +-node tb.dut tl_dma_o.a_address[15:9] +-node tb.dut tl_dma_o.a_address[24:17] +-node tb.dut tl_dma_o.a_address[28:26] +-node tb.dut tl_dma_o.a_address[31:30] +-node tb.dut tl_mbx0__core_o.a_address[24:7] +-node tb.dut tl_mbx0__core_o.a_address[28:26] +-node tb.dut tl_mbx0__core_o.a_address[31:30] +-node tb.dut tl_mbx1__core_o.a_address[7:7] +-node tb.dut tl_mbx1__core_o.a_address[24:9] +-node tb.dut tl_mbx1__core_o.a_address[28:26] +-node tb.dut tl_mbx1__core_o.a_address[31:30] +-node tb.dut tl_mbx2__core_o.a_address[8:7] +-node tb.dut tl_mbx2__core_o.a_address[24:10] +-node tb.dut tl_mbx2__core_o.a_address[28:26] +-node tb.dut tl_mbx2__core_o.a_address[31:30] +-node tb.dut tl_mbx3__core_o.a_address[7:7] +-node tb.dut tl_mbx3__core_o.a_address[24:10] +-node tb.dut tl_mbx3__core_o.a_address[28:26] +-node tb.dut tl_mbx3__core_o.a_address[31:30] +-node tb.dut tl_mbx4__core_o.a_address[9:7] +-node tb.dut tl_mbx4__core_o.a_address[24:11] +-node tb.dut tl_mbx4__core_o.a_address[28:26] +-node tb.dut tl_mbx4__core_o.a_address[31:30] +-node tb.dut tl_mbx5__core_o.a_address[7:7] +-node tb.dut tl_mbx5__core_o.a_address[9:9] +-node tb.dut tl_mbx5__core_o.a_address[24:11] +-node tb.dut tl_mbx5__core_o.a_address[28:26] +-node tb.dut tl_mbx5__core_o.a_address[31:30] +-node tb.dut tl_mbx6__core_o.a_address[8:7] +-node tb.dut tl_mbx6__core_o.a_address[24:11] +-node tb.dut tl_mbx6__core_o.a_address[28:26] +-node tb.dut tl_mbx6__core_o.a_address[31:30] +-node tb.dut tl_mbx_jtag__core_o.a_address[10:7] +-node tb.dut tl_mbx_jtag__core_o.a_address[24:12] +-node tb.dut tl_mbx_jtag__core_o.a_address[28:26] +-node tb.dut tl_mbx_jtag__core_o.a_address[31:30] +-node tb.dut tl_mbx_pcie0__core_o.a_address[17:7] +-node tb.dut tl_mbx_pcie0__core_o.a_address[24:19] +-node tb.dut tl_mbx_pcie0__core_o.a_address[28:26] +-node tb.dut tl_mbx_pcie0__core_o.a_address[31:30] +-node tb.dut tl_mbx_pcie1__core_o.a_address[7:7] +-node tb.dut tl_mbx_pcie1__core_o.a_address[17:9] +-node tb.dut tl_mbx_pcie1__core_o.a_address[24:19] +-node tb.dut tl_mbx_pcie1__core_o.a_address[28:26] +-node tb.dut tl_mbx_pcie1__core_o.a_address[31:30] + +-node tb.dut tl_*.a_source[7:4] +-node tb.dut tl_*.d_source[7:4] +begin tgl + -tree tb + +tree tb.dut 1 + -node tb.dut.scanmode_i +end diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv new file mode 100644 index 0000000000000..cfd48e58f713b --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv @@ -0,0 +1,234 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_env_pkg__params generated by `tlgen.py` tool + + +// List of Xbar device memory map +tl_device_t xbar_devices[$] = '{ + '{"rv_dm__regs", '{ + '{32'h21200000, 32'h2120000f} + }}, + '{"rv_dm__mem", '{ + '{32'h00040000, 32'h00040fff} + }}, + '{"rom_ctrl0__rom", '{ + '{32'h00008000, 32'h0000ffff} + }}, + '{"rom_ctrl0__regs", '{ + '{32'h211e0000, 32'h211e007f} + }}, + '{"rom_ctrl1__rom", '{ + '{32'h00020000, 32'h0002ffff} + }}, + '{"rom_ctrl1__regs", '{ + '{32'h211e1000, 32'h211e107f} + }}, + '{"peri", '{ + '{32'h30000000, 32'h307fffff} + }}, + '{"soc_proxy__core", '{ + '{32'h22030000, 32'h2203000f} + }}, + '{"soc_proxy__ctn", '{ + '{32'h40000000, 32'h7fffffff} + }}, + '{"hmac", '{ + '{32'h21110000, 32'h21111fff} + }}, + '{"kmac", '{ + '{32'h21120000, 32'h21120fff} + }}, + '{"aes", '{ + '{32'h21100000, 32'h211000ff} + }}, + '{"csrng", '{ + '{32'h21150000, 32'h2115007f} + }}, + '{"edn0", '{ + '{32'h21170000, 32'h2117007f} + }}, + '{"edn1", '{ + '{32'h21180000, 32'h2118007f} + }}, + '{"rv_plic", '{ + '{32'h28000000, 32'h2fffffff} + }}, + '{"otbn", '{ + '{32'h21130000, 32'h2113ffff} + }}, + '{"keymgr_dpe", '{ + '{32'h21140000, 32'h211400ff} + }}, + '{"rv_core_ibex__cfg", '{ + '{32'h211f0000, 32'h211f00ff} + }}, + '{"sram_ctrl_main__regs", '{ + '{32'h211c0000, 32'h211c003f} + }}, + '{"sram_ctrl_main__ram", '{ + '{32'h10000000, 32'h1000ffff} + }}, + '{"sram_ctrl_mbox__regs", '{ + '{32'h211d0000, 32'h211d003f} + }}, + '{"sram_ctrl_mbox__ram", '{ + '{32'h11000000, 32'h11000fff} + }}, + '{"dma", '{ + '{32'h22010000, 32'h220101ff} + }}, + '{"mbx0__core", '{ + '{32'h22000000, 32'h2200007f} + }}, + '{"mbx1__core", '{ + '{32'h22000100, 32'h2200017f} + }}, + '{"mbx2__core", '{ + '{32'h22000200, 32'h2200027f} + }}, + '{"mbx3__core", '{ + '{32'h22000300, 32'h2200037f} + }}, + '{"mbx4__core", '{ + '{32'h22000400, 32'h2200047f} + }}, + '{"mbx5__core", '{ + '{32'h22000500, 32'h2200057f} + }}, + '{"mbx6__core", '{ + '{32'h22000600, 32'h2200067f} + }}, + '{"mbx_jtag__core", '{ + '{32'h22000800, 32'h2200087f} + }}, + '{"mbx_pcie0__core", '{ + '{32'h22040000, 32'h2204007f} + }}, + '{"mbx_pcie1__core", '{ + '{32'h22040100, 32'h2204017f} +}}}; + + // List of Xbar hosts +tl_host_t xbar_hosts[$] = '{ + '{"rv_core_ibex__corei", 0, '{ + "rom_ctrl0__rom", + "rom_ctrl1__rom", + "rv_dm__mem", + "sram_ctrl_main__ram", + "soc_proxy__ctn"}} + , + '{"rv_core_ibex__cored", 1, '{ + "rom_ctrl0__rom", + "rom_ctrl0__regs", + "rom_ctrl1__rom", + "rom_ctrl1__regs", + "rv_dm__mem", + "rv_dm__regs", + "sram_ctrl_main__ram", + "peri", + "aes", + "csrng", + "edn0", + "edn1", + "hmac", + "rv_plic", + "otbn", + "keymgr_dpe", + "kmac", + "sram_ctrl_main__regs", + "rv_core_ibex__cfg", + "sram_ctrl_mbox__ram", + "sram_ctrl_mbox__regs", + "soc_proxy__ctn", + "soc_proxy__core", + "dma", + "mbx0__core", + "mbx1__core", + "mbx2__core", + "mbx3__core", + "mbx4__core", + "mbx5__core", + "mbx6__core", + "mbx_jtag__core", + "mbx_pcie0__core", + "mbx_pcie1__core"}} + , + '{"rv_dm__sba", 2, '{ + "rom_ctrl0__rom", + "rom_ctrl0__regs", + "rom_ctrl1__rom", + "rom_ctrl1__regs", + "rv_dm__mem", + "rv_dm__regs", + "sram_ctrl_main__ram", + "peri", + "aes", + "csrng", + "edn0", + "edn1", + "hmac", + "rv_plic", + "otbn", + "keymgr_dpe", + "kmac", + "sram_ctrl_main__regs", + "rv_core_ibex__cfg", + "sram_ctrl_mbox__ram", + "sram_ctrl_mbox__regs", + "soc_proxy__ctn", + "soc_proxy__core", + "dma", + "mbx0__core", + "mbx1__core", + "mbx2__core", + "mbx3__core", + "mbx4__core", + "mbx5__core", + "mbx6__core", + "mbx_jtag__core", + "mbx_pcie0__core", + "mbx_pcie1__core"}} + , + '{"dma__host", 3, '{ + "sram_ctrl_main__ram", + "sram_ctrl_mbox__ram", + "aes", + "hmac", + "otbn", + "keymgr_dpe", + "kmac", + "soc_proxy__ctn", + "peri"}} + , + '{"mbx0__sram", 4, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx1__sram", 5, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx2__sram", 6, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx3__sram", 7, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx4__sram", 8, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx5__sram", 9, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx6__sram", 10, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_jtag__sram", 11, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_pcie0__sram", 12, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_pcie1__sram", 13, '{ + "sram_ctrl_mbox__ram"}} +}; diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_bind.core b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_bind.core new file mode 100644 index 0000000000000..cfa64697792bb --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_bind.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_main_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_xbar_main_bind:0.1" +description: "XBAR main assertion bind" +filesets: + files_dv: + files: + - xbar_main_bind.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_bind.sv new file mode 100644 index 0000000000000..4ce02fbbd1231 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_bind.sv @@ -0,0 +1,300 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main_bind module generated by `tlgen.py` tool for assertions +module xbar_main_bind; +`ifndef GATE_LEVEL + // Host interfaces + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_rv_core_ibex__corei ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rv_core_ibex__corei_i), + .d2h (tl_rv_core_ibex__corei_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_rv_core_ibex__cored ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rv_core_ibex__cored_i), + .d2h (tl_rv_core_ibex__cored_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_rv_dm__sba ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rv_dm__sba_i), + .d2h (tl_rv_dm__sba_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_dma__host ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_dma__host_i), + .d2h (tl_dma__host_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx0__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx0__sram_i), + .d2h (tl_mbx0__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx1__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx1__sram_i), + .d2h (tl_mbx1__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx2__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx2__sram_i), + .d2h (tl_mbx2__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx3__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx3__sram_i), + .d2h (tl_mbx3__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx4__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx4__sram_i), + .d2h (tl_mbx4__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx5__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx5__sram_i), + .d2h (tl_mbx5__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx6__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx6__sram_i), + .d2h (tl_mbx6__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx_jtag__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_jtag__sram_i), + .d2h (tl_mbx_jtag__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx_pcie0__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_pcie0__sram_i), + .d2h (tl_mbx_pcie0__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx_pcie1__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_pcie1__sram_i), + .d2h (tl_mbx_pcie1__sram_o) + ); + + // Device interfaces + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_dm__regs ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rv_dm__regs_o), + .d2h (tl_rv_dm__regs_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_dm__mem ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rv_dm__mem_o), + .d2h (tl_rv_dm__mem_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rom_ctrl0__rom ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rom_ctrl0__rom_o), + .d2h (tl_rom_ctrl0__rom_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rom_ctrl0__regs ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rom_ctrl0__regs_o), + .d2h (tl_rom_ctrl0__regs_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rom_ctrl1__rom ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rom_ctrl1__rom_o), + .d2h (tl_rom_ctrl1__rom_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rom_ctrl1__regs ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rom_ctrl1__regs_o), + .d2h (tl_rom_ctrl1__regs_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_peri ( + .clk_i (clk_fixed_i), + .rst_ni (rst_fixed_ni), + .h2d (tl_peri_o), + .d2h (tl_peri_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_soc_proxy__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_soc_proxy__core_o), + .d2h (tl_soc_proxy__core_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_soc_proxy__ctn ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_soc_proxy__ctn_o), + .d2h (tl_soc_proxy__ctn_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_hmac ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_hmac_o), + .d2h (tl_hmac_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_kmac ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_kmac_o), + .d2h (tl_kmac_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_aes ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_aes_o), + .d2h (tl_aes_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_csrng ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_csrng_o), + .d2h (tl_csrng_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_edn0 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_edn0_o), + .d2h (tl_edn0_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_edn1 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_edn1_o), + .d2h (tl_edn1_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_plic ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rv_plic_o), + .d2h (tl_rv_plic_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_otbn ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_otbn_o), + .d2h (tl_otbn_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_keymgr_dpe ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_keymgr_dpe_o), + .d2h (tl_keymgr_dpe_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_core_ibex__cfg ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rv_core_ibex__cfg_o), + .d2h (tl_rv_core_ibex__cfg_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_main__regs ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_sram_ctrl_main__regs_o), + .d2h (tl_sram_ctrl_main__regs_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_main__ram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_sram_ctrl_main__ram_o), + .d2h (tl_sram_ctrl_main__ram_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_mbox__regs ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_sram_ctrl_mbox__regs_o), + .d2h (tl_sram_ctrl_mbox__regs_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_mbox__ram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_sram_ctrl_mbox__ram_o), + .d2h (tl_sram_ctrl_mbox__ram_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_dma ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_dma_o), + .d2h (tl_dma_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx0__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx0__core_o), + .d2h (tl_mbx0__core_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx1__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx1__core_o), + .d2h (tl_mbx1__core_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx2__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx2__core_o), + .d2h (tl_mbx2__core_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx3__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx3__core_o), + .d2h (tl_mbx3__core_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx4__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx4__core_o), + .d2h (tl_mbx4__core_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx5__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx5__core_o), + .d2h (tl_mbx5__core_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx6__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx6__core_o), + .d2h (tl_mbx6__core_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx_jtag__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_jtag__core_o), + .d2h (tl_mbx_jtag__core_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx_pcie0__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_pcie0__core_o), + .d2h (tl_mbx_pcie0__core_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx_pcie1__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_pcie1__core_o), + .d2h (tl_mbx_pcie1__core_i) + ); +`endif +endmodule diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_sim.core b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_sim.core new file mode 100644 index 0000000000000..bcfda1d8294c6 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_main_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_xbar_main_sim:0.1" +description: "XBAR DV sim target" +filesets: + files_dv: + depend: + - lowrisc:top_darjeeling:xbar_main + - lowrisc:dv:dv_utils + - lowrisc:dv:xbar_tb + - lowrisc:dv:top_darjeeling_xbar_main_bind + files: + - tb__xbar_connect.sv: {is_include_file: true} + - xbar_env_pkg__params.sv: {is_include_file: true} + file_type: systemVerilogSource + + +targets: + sim: &sim_target + toplevel: xbar_tb_top + filesets: + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson new file mode 100644 index 0000000000000..aeb63afdee61e --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main_sim_cfg.hjson file generated by `tlgen.py` tool +{ + name: xbar_main + + // Top level dut name (sv module). + dut: xbar_main + + // The name of the chip this XBAR configuration is made for. + top_chip: top_darjeeling + + // Testplan hjson file. + testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson" + + // Add xbar_main specific exclusion files. + vcs_cov_excl_files: ["{proj_root}/hw/top_darjeeling/ip/{dut}/dv/autogen/xbar_cov_excl.el"] + + // replace common cover.cfg with a generated one, which includes xbar toggle exclusions + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/top_darjeeling/ip/{dut}/dv/autogen/xbar_cover.cfg" + } + ] + // Import additional common sim cfg files. + import_cfgs: [// xbar common sim cfg file + "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"] +} diff --git a/hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv new file mode 100644 index 0000000000000..fe0c10aec794e --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv @@ -0,0 +1,140 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tl_main package generated by `tlgen.py` tool + +package tl_main_pkg; + + localparam logic [31:0] ADDR_SPACE_RV_DM__REGS = 32'h 21200000; + localparam logic [31:0] ADDR_SPACE_RV_DM__MEM = 32'h 00040000; + localparam logic [31:0] ADDR_SPACE_ROM_CTRL0__ROM = 32'h 00008000; + localparam logic [31:0] ADDR_SPACE_ROM_CTRL0__REGS = 32'h 211e0000; + localparam logic [31:0] ADDR_SPACE_ROM_CTRL1__ROM = 32'h 00020000; + localparam logic [31:0] ADDR_SPACE_ROM_CTRL1__REGS = 32'h 211e1000; + localparam logic [0:0][31:0] ADDR_SPACE_PERI = { + 32'h 30000000 + }; + localparam logic [31:0] ADDR_SPACE_SOC_PROXY__CORE = 32'h 22030000; + localparam logic [31:0] ADDR_SPACE_SOC_PROXY__CTN = 32'h 40000000; + localparam logic [31:0] ADDR_SPACE_HMAC = 32'h 21110000; + localparam logic [31:0] ADDR_SPACE_KMAC = 32'h 21120000; + localparam logic [31:0] ADDR_SPACE_AES = 32'h 21100000; + localparam logic [31:0] ADDR_SPACE_CSRNG = 32'h 21150000; + localparam logic [31:0] ADDR_SPACE_EDN0 = 32'h 21170000; + localparam logic [31:0] ADDR_SPACE_EDN1 = 32'h 21180000; + localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 28000000; + localparam logic [31:0] ADDR_SPACE_OTBN = 32'h 21130000; + localparam logic [31:0] ADDR_SPACE_KEYMGR_DPE = 32'h 21140000; + localparam logic [31:0] ADDR_SPACE_RV_CORE_IBEX__CFG = 32'h 211f0000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN__REGS = 32'h 211c0000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN__RAM = 32'h 10000000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MBOX__REGS = 32'h 211d0000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MBOX__RAM = 32'h 11000000; + localparam logic [31:0] ADDR_SPACE_DMA = 32'h 22010000; + localparam logic [31:0] ADDR_SPACE_MBX0__CORE = 32'h 22000000; + localparam logic [31:0] ADDR_SPACE_MBX1__CORE = 32'h 22000100; + localparam logic [31:0] ADDR_SPACE_MBX2__CORE = 32'h 22000200; + localparam logic [31:0] ADDR_SPACE_MBX3__CORE = 32'h 22000300; + localparam logic [31:0] ADDR_SPACE_MBX4__CORE = 32'h 22000400; + localparam logic [31:0] ADDR_SPACE_MBX5__CORE = 32'h 22000500; + localparam logic [31:0] ADDR_SPACE_MBX6__CORE = 32'h 22000600; + localparam logic [31:0] ADDR_SPACE_MBX_JTAG__CORE = 32'h 22000800; + localparam logic [31:0] ADDR_SPACE_MBX_PCIE0__CORE = 32'h 22040000; + localparam logic [31:0] ADDR_SPACE_MBX_PCIE1__CORE = 32'h 22040100; + + localparam logic [31:0] ADDR_MASK_RV_DM__REGS = 32'h 0000000f; + localparam logic [31:0] ADDR_MASK_RV_DM__MEM = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_ROM_CTRL0__ROM = 32'h 00007fff; + localparam logic [31:0] ADDR_MASK_ROM_CTRL0__REGS = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_ROM_CTRL1__ROM = 32'h 0000ffff; + localparam logic [31:0] ADDR_MASK_ROM_CTRL1__REGS = 32'h 0000007f; + localparam logic [0:0][31:0] ADDR_MASK_PERI = { + 32'h 007fffff + }; + localparam logic [31:0] ADDR_MASK_SOC_PROXY__CORE = 32'h 0000000f; + localparam logic [31:0] ADDR_MASK_SOC_PROXY__CTN = 32'h 3fffffff; + localparam logic [31:0] ADDR_MASK_HMAC = 32'h 00001fff; + localparam logic [31:0] ADDR_MASK_KMAC = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_AES = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_CSRNG = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_EDN0 = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_EDN1 = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 07ffffff; + localparam logic [31:0] ADDR_MASK_OTBN = 32'h 0000ffff; + localparam logic [31:0] ADDR_MASK_KEYMGR_DPE = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_RV_CORE_IBEX__CFG = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__REGS = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__RAM = 32'h 0000ffff; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MBOX__REGS = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MBOX__RAM = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_DMA = 32'h 000001ff; + localparam logic [31:0] ADDR_MASK_MBX0__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX1__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX2__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX3__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX4__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX5__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX6__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX_JTAG__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX_PCIE0__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX_PCIE1__CORE = 32'h 0000007f; + + localparam int N_HOST = 14; + localparam int N_DEVICE = 34; + + typedef enum int { + TlRvDmRegs = 0, + TlRvDmMem = 1, + TlRomCtrl0Rom = 2, + TlRomCtrl0Regs = 3, + TlRomCtrl1Rom = 4, + TlRomCtrl1Regs = 5, + TlPeri = 6, + TlSocProxyCore = 7, + TlSocProxyCtn = 8, + TlHmac = 9, + TlKmac = 10, + TlAes = 11, + TlCsrng = 12, + TlEdn0 = 13, + TlEdn1 = 14, + TlRvPlic = 15, + TlOtbn = 16, + TlKeymgrDpe = 17, + TlRvCoreIbexCfg = 18, + TlSramCtrlMainRegs = 19, + TlSramCtrlMainRam = 20, + TlSramCtrlMboxRegs = 21, + TlSramCtrlMboxRam = 22, + TlDma = 23, + TlMbx0Core = 24, + TlMbx1Core = 25, + TlMbx2Core = 26, + TlMbx3Core = 27, + TlMbx4Core = 28, + TlMbx5Core = 29, + TlMbx6Core = 30, + TlMbxJtagCore = 31, + TlMbxPcie0Core = 32, + TlMbxPcie1Core = 33 + } tl_device_e; + + typedef enum int { + TlRvCoreIbexCorei = 0, + TlRvCoreIbexCored = 1, + TlRvDmSba = 2, + TlDmaHost = 3, + TlMbx0Sram = 4, + TlMbx1Sram = 5, + TlMbx2Sram = 6, + TlMbx3Sram = 7, + TlMbx4Sram = 8, + TlMbx5Sram = 9, + TlMbx6Sram = 10, + TlMbxJtagSram = 11, + TlMbxPcie0Sram = 12, + TlMbxPcie1Sram = 13 + } tl_host_e; + +endpackage diff --git a/hw/top_darjeeling/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_darjeeling/ip/xbar_main/rtl/autogen/xbar_main.sv new file mode 100644 index 0000000000000..d7731f35eb9d2 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_main/rtl/autogen/xbar_main.sv @@ -0,0 +1,1909 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main module generated by `tlgen.py` tool +// all reset signals should be generated from one reset signal to not make any deadlock +// +// Interconnect +// rv_core_ibex.corei +// -> s1n_48 +// -> sm1_49 +// -> rom_ctrl0.rom +// -> sm1_50 +// -> rom_ctrl1.rom +// -> sm1_51 +// -> rv_dm.mem +// -> sm1_52 +// -> sram_ctrl_main.ram +// -> sm1_53 +// -> soc_proxy.ctn +// rv_core_ibex.cored +// -> s1n_54 +// -> sm1_49 +// -> rom_ctrl0.rom +// -> sm1_55 +// -> rom_ctrl0.regs +// -> sm1_50 +// -> rom_ctrl1.rom +// -> sm1_56 +// -> rom_ctrl1.regs +// -> sm1_51 +// -> rv_dm.mem +// -> sm1_57 +// -> rv_dm.regs +// -> sm1_52 +// -> sram_ctrl_main.ram +// -> sm1_59 +// -> asf_58 +// -> peri +// -> sm1_60 +// -> aes +// -> sm1_61 +// -> csrng +// -> sm1_62 +// -> edn0 +// -> sm1_63 +// -> edn1 +// -> sm1_64 +// -> hmac +// -> sm1_65 +// -> rv_plic +// -> sm1_66 +// -> otbn +// -> sm1_67 +// -> keymgr_dpe +// -> sm1_68 +// -> kmac +// -> sm1_69 +// -> sram_ctrl_main.regs +// -> sm1_70 +// -> rv_core_ibex.cfg +// -> sm1_71 +// -> sram_ctrl_mbox.ram +// -> sm1_72 +// -> sram_ctrl_mbox.regs +// -> sm1_53 +// -> soc_proxy.ctn +// -> sm1_73 +// -> soc_proxy.core +// -> sm1_74 +// -> dma +// -> sm1_75 +// -> mbx0.core +// -> sm1_76 +// -> mbx1.core +// -> sm1_77 +// -> mbx2.core +// -> sm1_78 +// -> mbx3.core +// -> sm1_79 +// -> mbx4.core +// -> sm1_80 +// -> mbx5.core +// -> sm1_81 +// -> mbx6.core +// -> sm1_82 +// -> mbx_jtag.core +// -> sm1_83 +// -> mbx_pcie0.core +// -> sm1_84 +// -> mbx_pcie1.core +// rv_dm.sba +// -> s1n_85 +// -> sm1_49 +// -> rom_ctrl0.rom +// -> sm1_55 +// -> rom_ctrl0.regs +// -> sm1_50 +// -> rom_ctrl1.rom +// -> sm1_56 +// -> rom_ctrl1.regs +// -> sm1_51 +// -> rv_dm.mem +// -> sm1_57 +// -> rv_dm.regs +// -> sm1_52 +// -> sram_ctrl_main.ram +// -> sm1_59 +// -> asf_58 +// -> peri +// -> sm1_60 +// -> aes +// -> sm1_61 +// -> csrng +// -> sm1_62 +// -> edn0 +// -> sm1_63 +// -> edn1 +// -> sm1_64 +// -> hmac +// -> sm1_65 +// -> rv_plic +// -> sm1_66 +// -> otbn +// -> sm1_67 +// -> keymgr_dpe +// -> sm1_68 +// -> kmac +// -> sm1_69 +// -> sram_ctrl_main.regs +// -> sm1_70 +// -> rv_core_ibex.cfg +// -> sm1_71 +// -> sram_ctrl_mbox.ram +// -> sm1_72 +// -> sram_ctrl_mbox.regs +// -> sm1_53 +// -> soc_proxy.ctn +// -> sm1_73 +// -> soc_proxy.core +// -> sm1_74 +// -> dma +// -> sm1_75 +// -> mbx0.core +// -> sm1_76 +// -> mbx1.core +// -> sm1_77 +// -> mbx2.core +// -> sm1_78 +// -> mbx3.core +// -> sm1_79 +// -> mbx4.core +// -> sm1_80 +// -> mbx5.core +// -> sm1_81 +// -> mbx6.core +// -> sm1_82 +// -> mbx_jtag.core +// -> sm1_83 +// -> mbx_pcie0.core +// -> sm1_84 +// -> mbx_pcie1.core +// dma.host +// -> s1n_86 +// -> sm1_52 +// -> sram_ctrl_main.ram +// -> sm1_71 +// -> sram_ctrl_mbox.ram +// -> sm1_60 +// -> aes +// -> sm1_64 +// -> hmac +// -> sm1_66 +// -> otbn +// -> sm1_67 +// -> keymgr_dpe +// -> sm1_68 +// -> kmac +// -> sm1_53 +// -> soc_proxy.ctn +// -> sm1_59 +// -> asf_58 +// -> peri +// mbx0.sram +// -> sm1_71 +// -> sram_ctrl_mbox.ram +// mbx1.sram +// -> sm1_71 +// -> sram_ctrl_mbox.ram +// mbx2.sram +// -> sm1_71 +// -> sram_ctrl_mbox.ram +// mbx3.sram +// -> sm1_71 +// -> sram_ctrl_mbox.ram +// mbx4.sram +// -> sm1_71 +// -> sram_ctrl_mbox.ram +// mbx5.sram +// -> sm1_71 +// -> sram_ctrl_mbox.ram +// mbx6.sram +// -> sm1_71 +// -> sram_ctrl_mbox.ram +// mbx_jtag.sram +// -> sm1_71 +// -> sram_ctrl_mbox.ram +// mbx_pcie0.sram +// -> sm1_71 +// -> sram_ctrl_mbox.ram +// mbx_pcie1.sram +// -> sm1_71 +// -> sram_ctrl_mbox.ram + +module xbar_main ( + input clk_main_i, + input clk_fixed_i, + input clk_usb_i, + input rst_main_ni, + input rst_fixed_ni, + input rst_usb_ni, + + // Host interfaces + input tlul_pkg::tl_h2d_t tl_rv_core_ibex__corei_i, + output tlul_pkg::tl_d2h_t tl_rv_core_ibex__corei_o, + input tlul_pkg::tl_h2d_t tl_rv_core_ibex__cored_i, + output tlul_pkg::tl_d2h_t tl_rv_core_ibex__cored_o, + input tlul_pkg::tl_h2d_t tl_rv_dm__sba_i, + output tlul_pkg::tl_d2h_t tl_rv_dm__sba_o, + input tlul_pkg::tl_h2d_t tl_dma__host_i, + output tlul_pkg::tl_d2h_t tl_dma__host_o, + input tlul_pkg::tl_h2d_t tl_mbx0__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx0__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx1__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx1__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx2__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx2__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx3__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx3__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx4__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx4__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx5__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx5__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx6__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx6__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx_jtag__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx_jtag__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx_pcie0__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx_pcie0__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx_pcie1__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx_pcie1__sram_o, + + // Device interfaces + output tlul_pkg::tl_h2d_t tl_rv_dm__regs_o, + input tlul_pkg::tl_d2h_t tl_rv_dm__regs_i, + output tlul_pkg::tl_h2d_t tl_rv_dm__mem_o, + input tlul_pkg::tl_d2h_t tl_rv_dm__mem_i, + output tlul_pkg::tl_h2d_t tl_rom_ctrl0__rom_o, + input tlul_pkg::tl_d2h_t tl_rom_ctrl0__rom_i, + output tlul_pkg::tl_h2d_t tl_rom_ctrl0__regs_o, + input tlul_pkg::tl_d2h_t tl_rom_ctrl0__regs_i, + output tlul_pkg::tl_h2d_t tl_rom_ctrl1__rom_o, + input tlul_pkg::tl_d2h_t tl_rom_ctrl1__rom_i, + output tlul_pkg::tl_h2d_t tl_rom_ctrl1__regs_o, + input tlul_pkg::tl_d2h_t tl_rom_ctrl1__regs_i, + output tlul_pkg::tl_h2d_t tl_peri_o, + input tlul_pkg::tl_d2h_t tl_peri_i, + output tlul_pkg::tl_h2d_t tl_soc_proxy__core_o, + input tlul_pkg::tl_d2h_t tl_soc_proxy__core_i, + output tlul_pkg::tl_h2d_t tl_soc_proxy__ctn_o, + input tlul_pkg::tl_d2h_t tl_soc_proxy__ctn_i, + output tlul_pkg::tl_h2d_t tl_hmac_o, + input tlul_pkg::tl_d2h_t tl_hmac_i, + output tlul_pkg::tl_h2d_t tl_kmac_o, + input tlul_pkg::tl_d2h_t tl_kmac_i, + output tlul_pkg::tl_h2d_t tl_aes_o, + input tlul_pkg::tl_d2h_t tl_aes_i, + output tlul_pkg::tl_h2d_t tl_csrng_o, + input tlul_pkg::tl_d2h_t tl_csrng_i, + output tlul_pkg::tl_h2d_t tl_edn0_o, + input tlul_pkg::tl_d2h_t tl_edn0_i, + output tlul_pkg::tl_h2d_t tl_edn1_o, + input tlul_pkg::tl_d2h_t tl_edn1_i, + output tlul_pkg::tl_h2d_t tl_rv_plic_o, + input tlul_pkg::tl_d2h_t tl_rv_plic_i, + output tlul_pkg::tl_h2d_t tl_otbn_o, + input tlul_pkg::tl_d2h_t tl_otbn_i, + output tlul_pkg::tl_h2d_t tl_keymgr_dpe_o, + input tlul_pkg::tl_d2h_t tl_keymgr_dpe_i, + output tlul_pkg::tl_h2d_t tl_rv_core_ibex__cfg_o, + input tlul_pkg::tl_d2h_t tl_rv_core_ibex__cfg_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_main__regs_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_main__regs_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_main__ram_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_main__ram_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_mbox__regs_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_mbox__regs_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_mbox__ram_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_mbox__ram_i, + output tlul_pkg::tl_h2d_t tl_dma_o, + input tlul_pkg::tl_d2h_t tl_dma_i, + output tlul_pkg::tl_h2d_t tl_mbx0__core_o, + input tlul_pkg::tl_d2h_t tl_mbx0__core_i, + output tlul_pkg::tl_h2d_t tl_mbx1__core_o, + input tlul_pkg::tl_d2h_t tl_mbx1__core_i, + output tlul_pkg::tl_h2d_t tl_mbx2__core_o, + input tlul_pkg::tl_d2h_t tl_mbx2__core_i, + output tlul_pkg::tl_h2d_t tl_mbx3__core_o, + input tlul_pkg::tl_d2h_t tl_mbx3__core_i, + output tlul_pkg::tl_h2d_t tl_mbx4__core_o, + input tlul_pkg::tl_d2h_t tl_mbx4__core_i, + output tlul_pkg::tl_h2d_t tl_mbx5__core_o, + input tlul_pkg::tl_d2h_t tl_mbx5__core_i, + output tlul_pkg::tl_h2d_t tl_mbx6__core_o, + input tlul_pkg::tl_d2h_t tl_mbx6__core_i, + output tlul_pkg::tl_h2d_t tl_mbx_jtag__core_o, + input tlul_pkg::tl_d2h_t tl_mbx_jtag__core_i, + output tlul_pkg::tl_h2d_t tl_mbx_pcie0__core_o, + input tlul_pkg::tl_d2h_t tl_mbx_pcie0__core_i, + output tlul_pkg::tl_h2d_t tl_mbx_pcie1__core_o, + input tlul_pkg::tl_d2h_t tl_mbx_pcie1__core_i, + + input prim_mubi_pkg::mubi4_t scanmode_i +); + + import tlul_pkg::*; + import tl_main_pkg::*; + + // scanmode_i is currently not used, but provisioned for future use + // this assignment prevents lint warnings + logic unused_scanmode; + assign unused_scanmode = ^scanmode_i; + + tl_h2d_t tl_s1n_48_us_h2d ; + tl_d2h_t tl_s1n_48_us_d2h ; + + + tl_h2d_t tl_s1n_48_ds_h2d [5]; + tl_d2h_t tl_s1n_48_ds_d2h [5]; + + // Create steering signal + logic [2:0] dev_sel_s1n_48; + + + tl_h2d_t tl_sm1_49_us_h2d [3]; + tl_d2h_t tl_sm1_49_us_d2h [3]; + + tl_h2d_t tl_sm1_49_ds_h2d ; + tl_d2h_t tl_sm1_49_ds_d2h ; + + + tl_h2d_t tl_sm1_50_us_h2d [3]; + tl_d2h_t tl_sm1_50_us_d2h [3]; + + tl_h2d_t tl_sm1_50_ds_h2d ; + tl_d2h_t tl_sm1_50_ds_d2h ; + + + tl_h2d_t tl_sm1_51_us_h2d [3]; + tl_d2h_t tl_sm1_51_us_d2h [3]; + + tl_h2d_t tl_sm1_51_ds_h2d ; + tl_d2h_t tl_sm1_51_ds_d2h ; + + + tl_h2d_t tl_sm1_52_us_h2d [4]; + tl_d2h_t tl_sm1_52_us_d2h [4]; + + tl_h2d_t tl_sm1_52_ds_h2d ; + tl_d2h_t tl_sm1_52_ds_d2h ; + + + tl_h2d_t tl_sm1_53_us_h2d [4]; + tl_d2h_t tl_sm1_53_us_d2h [4]; + + tl_h2d_t tl_sm1_53_ds_h2d ; + tl_d2h_t tl_sm1_53_ds_d2h ; + + tl_h2d_t tl_s1n_54_us_h2d ; + tl_d2h_t tl_s1n_54_us_d2h ; + + + tl_h2d_t tl_s1n_54_ds_h2d [34]; + tl_d2h_t tl_s1n_54_ds_d2h [34]; + + // Create steering signal + logic [5:0] dev_sel_s1n_54; + + + tl_h2d_t tl_sm1_55_us_h2d [2]; + tl_d2h_t tl_sm1_55_us_d2h [2]; + + tl_h2d_t tl_sm1_55_ds_h2d ; + tl_d2h_t tl_sm1_55_ds_d2h ; + + + tl_h2d_t tl_sm1_56_us_h2d [2]; + tl_d2h_t tl_sm1_56_us_d2h [2]; + + tl_h2d_t tl_sm1_56_ds_h2d ; + tl_d2h_t tl_sm1_56_ds_d2h ; + + + tl_h2d_t tl_sm1_57_us_h2d [2]; + tl_d2h_t tl_sm1_57_us_d2h [2]; + + tl_h2d_t tl_sm1_57_ds_h2d ; + tl_d2h_t tl_sm1_57_ds_d2h ; + + tl_h2d_t tl_asf_58_us_h2d ; + tl_d2h_t tl_asf_58_us_d2h ; + tl_h2d_t tl_asf_58_ds_h2d ; + tl_d2h_t tl_asf_58_ds_d2h ; + + + tl_h2d_t tl_sm1_59_us_h2d [3]; + tl_d2h_t tl_sm1_59_us_d2h [3]; + + tl_h2d_t tl_sm1_59_ds_h2d ; + tl_d2h_t tl_sm1_59_ds_d2h ; + + + tl_h2d_t tl_sm1_60_us_h2d [3]; + tl_d2h_t tl_sm1_60_us_d2h [3]; + + tl_h2d_t tl_sm1_60_ds_h2d ; + tl_d2h_t tl_sm1_60_ds_d2h ; + + + tl_h2d_t tl_sm1_61_us_h2d [2]; + tl_d2h_t tl_sm1_61_us_d2h [2]; + + tl_h2d_t tl_sm1_61_ds_h2d ; + tl_d2h_t tl_sm1_61_ds_d2h ; + + + tl_h2d_t tl_sm1_62_us_h2d [2]; + tl_d2h_t tl_sm1_62_us_d2h [2]; + + tl_h2d_t tl_sm1_62_ds_h2d ; + tl_d2h_t tl_sm1_62_ds_d2h ; + + + tl_h2d_t tl_sm1_63_us_h2d [2]; + tl_d2h_t tl_sm1_63_us_d2h [2]; + + tl_h2d_t tl_sm1_63_ds_h2d ; + tl_d2h_t tl_sm1_63_ds_d2h ; + + + tl_h2d_t tl_sm1_64_us_h2d [3]; + tl_d2h_t tl_sm1_64_us_d2h [3]; + + tl_h2d_t tl_sm1_64_ds_h2d ; + tl_d2h_t tl_sm1_64_ds_d2h ; + + + tl_h2d_t tl_sm1_65_us_h2d [2]; + tl_d2h_t tl_sm1_65_us_d2h [2]; + + tl_h2d_t tl_sm1_65_ds_h2d ; + tl_d2h_t tl_sm1_65_ds_d2h ; + + + tl_h2d_t tl_sm1_66_us_h2d [3]; + tl_d2h_t tl_sm1_66_us_d2h [3]; + + tl_h2d_t tl_sm1_66_ds_h2d ; + tl_d2h_t tl_sm1_66_ds_d2h ; + + + tl_h2d_t tl_sm1_67_us_h2d [3]; + tl_d2h_t tl_sm1_67_us_d2h [3]; + + tl_h2d_t tl_sm1_67_ds_h2d ; + tl_d2h_t tl_sm1_67_ds_d2h ; + + + tl_h2d_t tl_sm1_68_us_h2d [3]; + tl_d2h_t tl_sm1_68_us_d2h [3]; + + tl_h2d_t tl_sm1_68_ds_h2d ; + tl_d2h_t tl_sm1_68_ds_d2h ; + + + tl_h2d_t tl_sm1_69_us_h2d [2]; + tl_d2h_t tl_sm1_69_us_d2h [2]; + + tl_h2d_t tl_sm1_69_ds_h2d ; + tl_d2h_t tl_sm1_69_ds_d2h ; + + + tl_h2d_t tl_sm1_70_us_h2d [2]; + tl_d2h_t tl_sm1_70_us_d2h [2]; + + tl_h2d_t tl_sm1_70_ds_h2d ; + tl_d2h_t tl_sm1_70_ds_d2h ; + + + tl_h2d_t tl_sm1_71_us_h2d [13]; + tl_d2h_t tl_sm1_71_us_d2h [13]; + + tl_h2d_t tl_sm1_71_ds_h2d ; + tl_d2h_t tl_sm1_71_ds_d2h ; + + + tl_h2d_t tl_sm1_72_us_h2d [2]; + tl_d2h_t tl_sm1_72_us_d2h [2]; + + tl_h2d_t tl_sm1_72_ds_h2d ; + tl_d2h_t tl_sm1_72_ds_d2h ; + + + tl_h2d_t tl_sm1_73_us_h2d [2]; + tl_d2h_t tl_sm1_73_us_d2h [2]; + + tl_h2d_t tl_sm1_73_ds_h2d ; + tl_d2h_t tl_sm1_73_ds_d2h ; + + + tl_h2d_t tl_sm1_74_us_h2d [2]; + tl_d2h_t tl_sm1_74_us_d2h [2]; + + tl_h2d_t tl_sm1_74_ds_h2d ; + tl_d2h_t tl_sm1_74_ds_d2h ; + + + tl_h2d_t tl_sm1_75_us_h2d [2]; + tl_d2h_t tl_sm1_75_us_d2h [2]; + + tl_h2d_t tl_sm1_75_ds_h2d ; + tl_d2h_t tl_sm1_75_ds_d2h ; + + + tl_h2d_t tl_sm1_76_us_h2d [2]; + tl_d2h_t tl_sm1_76_us_d2h [2]; + + tl_h2d_t tl_sm1_76_ds_h2d ; + tl_d2h_t tl_sm1_76_ds_d2h ; + + + tl_h2d_t tl_sm1_77_us_h2d [2]; + tl_d2h_t tl_sm1_77_us_d2h [2]; + + tl_h2d_t tl_sm1_77_ds_h2d ; + tl_d2h_t tl_sm1_77_ds_d2h ; + + + tl_h2d_t tl_sm1_78_us_h2d [2]; + tl_d2h_t tl_sm1_78_us_d2h [2]; + + tl_h2d_t tl_sm1_78_ds_h2d ; + tl_d2h_t tl_sm1_78_ds_d2h ; + + + tl_h2d_t tl_sm1_79_us_h2d [2]; + tl_d2h_t tl_sm1_79_us_d2h [2]; + + tl_h2d_t tl_sm1_79_ds_h2d ; + tl_d2h_t tl_sm1_79_ds_d2h ; + + + tl_h2d_t tl_sm1_80_us_h2d [2]; + tl_d2h_t tl_sm1_80_us_d2h [2]; + + tl_h2d_t tl_sm1_80_ds_h2d ; + tl_d2h_t tl_sm1_80_ds_d2h ; + + + tl_h2d_t tl_sm1_81_us_h2d [2]; + tl_d2h_t tl_sm1_81_us_d2h [2]; + + tl_h2d_t tl_sm1_81_ds_h2d ; + tl_d2h_t tl_sm1_81_ds_d2h ; + + + tl_h2d_t tl_sm1_82_us_h2d [2]; + tl_d2h_t tl_sm1_82_us_d2h [2]; + + tl_h2d_t tl_sm1_82_ds_h2d ; + tl_d2h_t tl_sm1_82_ds_d2h ; + + + tl_h2d_t tl_sm1_83_us_h2d [2]; + tl_d2h_t tl_sm1_83_us_d2h [2]; + + tl_h2d_t tl_sm1_83_ds_h2d ; + tl_d2h_t tl_sm1_83_ds_d2h ; + + + tl_h2d_t tl_sm1_84_us_h2d [2]; + tl_d2h_t tl_sm1_84_us_d2h [2]; + + tl_h2d_t tl_sm1_84_ds_h2d ; + tl_d2h_t tl_sm1_84_ds_d2h ; + + tl_h2d_t tl_s1n_85_us_h2d ; + tl_d2h_t tl_s1n_85_us_d2h ; + + + tl_h2d_t tl_s1n_85_ds_h2d [34]; + tl_d2h_t tl_s1n_85_ds_d2h [34]; + + // Create steering signal + logic [5:0] dev_sel_s1n_85; + + tl_h2d_t tl_s1n_86_us_h2d ; + tl_d2h_t tl_s1n_86_us_d2h ; + + + tl_h2d_t tl_s1n_86_ds_h2d [9]; + tl_d2h_t tl_s1n_86_ds_d2h [9]; + + // Create steering signal + logic [3:0] dev_sel_s1n_86; + + + + assign tl_sm1_49_us_h2d[0] = tl_s1n_48_ds_h2d[0]; + assign tl_s1n_48_ds_d2h[0] = tl_sm1_49_us_d2h[0]; + + assign tl_sm1_50_us_h2d[0] = tl_s1n_48_ds_h2d[1]; + assign tl_s1n_48_ds_d2h[1] = tl_sm1_50_us_d2h[0]; + + assign tl_sm1_51_us_h2d[0] = tl_s1n_48_ds_h2d[2]; + assign tl_s1n_48_ds_d2h[2] = tl_sm1_51_us_d2h[0]; + + assign tl_sm1_52_us_h2d[0] = tl_s1n_48_ds_h2d[3]; + assign tl_s1n_48_ds_d2h[3] = tl_sm1_52_us_d2h[0]; + + assign tl_sm1_53_us_h2d[0] = tl_s1n_48_ds_h2d[4]; + assign tl_s1n_48_ds_d2h[4] = tl_sm1_53_us_d2h[0]; + + assign tl_sm1_49_us_h2d[1] = tl_s1n_54_ds_h2d[0]; + assign tl_s1n_54_ds_d2h[0] = tl_sm1_49_us_d2h[1]; + + assign tl_sm1_55_us_h2d[0] = tl_s1n_54_ds_h2d[1]; + assign tl_s1n_54_ds_d2h[1] = tl_sm1_55_us_d2h[0]; + + assign tl_sm1_50_us_h2d[1] = tl_s1n_54_ds_h2d[2]; + assign tl_s1n_54_ds_d2h[2] = tl_sm1_50_us_d2h[1]; + + assign tl_sm1_56_us_h2d[0] = tl_s1n_54_ds_h2d[3]; + assign tl_s1n_54_ds_d2h[3] = tl_sm1_56_us_d2h[0]; + + assign tl_sm1_51_us_h2d[1] = tl_s1n_54_ds_h2d[4]; + assign tl_s1n_54_ds_d2h[4] = tl_sm1_51_us_d2h[1]; + + assign tl_sm1_57_us_h2d[0] = tl_s1n_54_ds_h2d[5]; + assign tl_s1n_54_ds_d2h[5] = tl_sm1_57_us_d2h[0]; + + assign tl_sm1_52_us_h2d[1] = tl_s1n_54_ds_h2d[6]; + assign tl_s1n_54_ds_d2h[6] = tl_sm1_52_us_d2h[1]; + + assign tl_sm1_59_us_h2d[0] = tl_s1n_54_ds_h2d[7]; + assign tl_s1n_54_ds_d2h[7] = tl_sm1_59_us_d2h[0]; + + assign tl_sm1_60_us_h2d[0] = tl_s1n_54_ds_h2d[8]; + assign tl_s1n_54_ds_d2h[8] = tl_sm1_60_us_d2h[0]; + + assign tl_sm1_61_us_h2d[0] = tl_s1n_54_ds_h2d[9]; + assign tl_s1n_54_ds_d2h[9] = tl_sm1_61_us_d2h[0]; + + assign tl_sm1_62_us_h2d[0] = tl_s1n_54_ds_h2d[10]; + assign tl_s1n_54_ds_d2h[10] = tl_sm1_62_us_d2h[0]; + + assign tl_sm1_63_us_h2d[0] = tl_s1n_54_ds_h2d[11]; + assign tl_s1n_54_ds_d2h[11] = tl_sm1_63_us_d2h[0]; + + assign tl_sm1_64_us_h2d[0] = tl_s1n_54_ds_h2d[12]; + assign tl_s1n_54_ds_d2h[12] = tl_sm1_64_us_d2h[0]; + + assign tl_sm1_65_us_h2d[0] = tl_s1n_54_ds_h2d[13]; + assign tl_s1n_54_ds_d2h[13] = tl_sm1_65_us_d2h[0]; + + assign tl_sm1_66_us_h2d[0] = tl_s1n_54_ds_h2d[14]; + assign tl_s1n_54_ds_d2h[14] = tl_sm1_66_us_d2h[0]; + + assign tl_sm1_67_us_h2d[0] = tl_s1n_54_ds_h2d[15]; + assign tl_s1n_54_ds_d2h[15] = tl_sm1_67_us_d2h[0]; + + assign tl_sm1_68_us_h2d[0] = tl_s1n_54_ds_h2d[16]; + assign tl_s1n_54_ds_d2h[16] = tl_sm1_68_us_d2h[0]; + + assign tl_sm1_69_us_h2d[0] = tl_s1n_54_ds_h2d[17]; + assign tl_s1n_54_ds_d2h[17] = tl_sm1_69_us_d2h[0]; + + assign tl_sm1_70_us_h2d[0] = tl_s1n_54_ds_h2d[18]; + assign tl_s1n_54_ds_d2h[18] = tl_sm1_70_us_d2h[0]; + + assign tl_sm1_71_us_h2d[0] = tl_s1n_54_ds_h2d[19]; + assign tl_s1n_54_ds_d2h[19] = tl_sm1_71_us_d2h[0]; + + assign tl_sm1_72_us_h2d[0] = tl_s1n_54_ds_h2d[20]; + assign tl_s1n_54_ds_d2h[20] = tl_sm1_72_us_d2h[0]; + + assign tl_sm1_53_us_h2d[1] = tl_s1n_54_ds_h2d[21]; + assign tl_s1n_54_ds_d2h[21] = tl_sm1_53_us_d2h[1]; + + assign tl_sm1_73_us_h2d[0] = tl_s1n_54_ds_h2d[22]; + assign tl_s1n_54_ds_d2h[22] = tl_sm1_73_us_d2h[0]; + + assign tl_sm1_74_us_h2d[0] = tl_s1n_54_ds_h2d[23]; + assign tl_s1n_54_ds_d2h[23] = tl_sm1_74_us_d2h[0]; + + assign tl_sm1_75_us_h2d[0] = tl_s1n_54_ds_h2d[24]; + assign tl_s1n_54_ds_d2h[24] = tl_sm1_75_us_d2h[0]; + + assign tl_sm1_76_us_h2d[0] = tl_s1n_54_ds_h2d[25]; + assign tl_s1n_54_ds_d2h[25] = tl_sm1_76_us_d2h[0]; + + assign tl_sm1_77_us_h2d[0] = tl_s1n_54_ds_h2d[26]; + assign tl_s1n_54_ds_d2h[26] = tl_sm1_77_us_d2h[0]; + + assign tl_sm1_78_us_h2d[0] = tl_s1n_54_ds_h2d[27]; + assign tl_s1n_54_ds_d2h[27] = tl_sm1_78_us_d2h[0]; + + assign tl_sm1_79_us_h2d[0] = tl_s1n_54_ds_h2d[28]; + assign tl_s1n_54_ds_d2h[28] = tl_sm1_79_us_d2h[0]; + + assign tl_sm1_80_us_h2d[0] = tl_s1n_54_ds_h2d[29]; + assign tl_s1n_54_ds_d2h[29] = tl_sm1_80_us_d2h[0]; + + assign tl_sm1_81_us_h2d[0] = tl_s1n_54_ds_h2d[30]; + assign tl_s1n_54_ds_d2h[30] = tl_sm1_81_us_d2h[0]; + + assign tl_sm1_82_us_h2d[0] = tl_s1n_54_ds_h2d[31]; + assign tl_s1n_54_ds_d2h[31] = tl_sm1_82_us_d2h[0]; + + assign tl_sm1_83_us_h2d[0] = tl_s1n_54_ds_h2d[32]; + assign tl_s1n_54_ds_d2h[32] = tl_sm1_83_us_d2h[0]; + + assign tl_sm1_84_us_h2d[0] = tl_s1n_54_ds_h2d[33]; + assign tl_s1n_54_ds_d2h[33] = tl_sm1_84_us_d2h[0]; + + assign tl_sm1_49_us_h2d[2] = tl_s1n_85_ds_h2d[0]; + assign tl_s1n_85_ds_d2h[0] = tl_sm1_49_us_d2h[2]; + + assign tl_sm1_55_us_h2d[1] = tl_s1n_85_ds_h2d[1]; + assign tl_s1n_85_ds_d2h[1] = tl_sm1_55_us_d2h[1]; + + assign tl_sm1_50_us_h2d[2] = tl_s1n_85_ds_h2d[2]; + assign tl_s1n_85_ds_d2h[2] = tl_sm1_50_us_d2h[2]; + + assign tl_sm1_56_us_h2d[1] = tl_s1n_85_ds_h2d[3]; + assign tl_s1n_85_ds_d2h[3] = tl_sm1_56_us_d2h[1]; + + assign tl_sm1_51_us_h2d[2] = tl_s1n_85_ds_h2d[4]; + assign tl_s1n_85_ds_d2h[4] = tl_sm1_51_us_d2h[2]; + + assign tl_sm1_57_us_h2d[1] = tl_s1n_85_ds_h2d[5]; + assign tl_s1n_85_ds_d2h[5] = tl_sm1_57_us_d2h[1]; + + assign tl_sm1_52_us_h2d[2] = tl_s1n_85_ds_h2d[6]; + assign tl_s1n_85_ds_d2h[6] = tl_sm1_52_us_d2h[2]; + + assign tl_sm1_59_us_h2d[1] = tl_s1n_85_ds_h2d[7]; + assign tl_s1n_85_ds_d2h[7] = tl_sm1_59_us_d2h[1]; + + assign tl_sm1_60_us_h2d[1] = tl_s1n_85_ds_h2d[8]; + assign tl_s1n_85_ds_d2h[8] = tl_sm1_60_us_d2h[1]; + + assign tl_sm1_61_us_h2d[1] = tl_s1n_85_ds_h2d[9]; + assign tl_s1n_85_ds_d2h[9] = tl_sm1_61_us_d2h[1]; + + assign tl_sm1_62_us_h2d[1] = tl_s1n_85_ds_h2d[10]; + assign tl_s1n_85_ds_d2h[10] = tl_sm1_62_us_d2h[1]; + + assign tl_sm1_63_us_h2d[1] = tl_s1n_85_ds_h2d[11]; + assign tl_s1n_85_ds_d2h[11] = tl_sm1_63_us_d2h[1]; + + assign tl_sm1_64_us_h2d[1] = tl_s1n_85_ds_h2d[12]; + assign tl_s1n_85_ds_d2h[12] = tl_sm1_64_us_d2h[1]; + + assign tl_sm1_65_us_h2d[1] = tl_s1n_85_ds_h2d[13]; + assign tl_s1n_85_ds_d2h[13] = tl_sm1_65_us_d2h[1]; + + assign tl_sm1_66_us_h2d[1] = tl_s1n_85_ds_h2d[14]; + assign tl_s1n_85_ds_d2h[14] = tl_sm1_66_us_d2h[1]; + + assign tl_sm1_67_us_h2d[1] = tl_s1n_85_ds_h2d[15]; + assign tl_s1n_85_ds_d2h[15] = tl_sm1_67_us_d2h[1]; + + assign tl_sm1_68_us_h2d[1] = tl_s1n_85_ds_h2d[16]; + assign tl_s1n_85_ds_d2h[16] = tl_sm1_68_us_d2h[1]; + + assign tl_sm1_69_us_h2d[1] = tl_s1n_85_ds_h2d[17]; + assign tl_s1n_85_ds_d2h[17] = tl_sm1_69_us_d2h[1]; + + assign tl_sm1_70_us_h2d[1] = tl_s1n_85_ds_h2d[18]; + assign tl_s1n_85_ds_d2h[18] = tl_sm1_70_us_d2h[1]; + + assign tl_sm1_71_us_h2d[1] = tl_s1n_85_ds_h2d[19]; + assign tl_s1n_85_ds_d2h[19] = tl_sm1_71_us_d2h[1]; + + assign tl_sm1_72_us_h2d[1] = tl_s1n_85_ds_h2d[20]; + assign tl_s1n_85_ds_d2h[20] = tl_sm1_72_us_d2h[1]; + + assign tl_sm1_53_us_h2d[2] = tl_s1n_85_ds_h2d[21]; + assign tl_s1n_85_ds_d2h[21] = tl_sm1_53_us_d2h[2]; + + assign tl_sm1_73_us_h2d[1] = tl_s1n_85_ds_h2d[22]; + assign tl_s1n_85_ds_d2h[22] = tl_sm1_73_us_d2h[1]; + + assign tl_sm1_74_us_h2d[1] = tl_s1n_85_ds_h2d[23]; + assign tl_s1n_85_ds_d2h[23] = tl_sm1_74_us_d2h[1]; + + assign tl_sm1_75_us_h2d[1] = tl_s1n_85_ds_h2d[24]; + assign tl_s1n_85_ds_d2h[24] = tl_sm1_75_us_d2h[1]; + + assign tl_sm1_76_us_h2d[1] = tl_s1n_85_ds_h2d[25]; + assign tl_s1n_85_ds_d2h[25] = tl_sm1_76_us_d2h[1]; + + assign tl_sm1_77_us_h2d[1] = tl_s1n_85_ds_h2d[26]; + assign tl_s1n_85_ds_d2h[26] = tl_sm1_77_us_d2h[1]; + + assign tl_sm1_78_us_h2d[1] = tl_s1n_85_ds_h2d[27]; + assign tl_s1n_85_ds_d2h[27] = tl_sm1_78_us_d2h[1]; + + assign tl_sm1_79_us_h2d[1] = tl_s1n_85_ds_h2d[28]; + assign tl_s1n_85_ds_d2h[28] = tl_sm1_79_us_d2h[1]; + + assign tl_sm1_80_us_h2d[1] = tl_s1n_85_ds_h2d[29]; + assign tl_s1n_85_ds_d2h[29] = tl_sm1_80_us_d2h[1]; + + assign tl_sm1_81_us_h2d[1] = tl_s1n_85_ds_h2d[30]; + assign tl_s1n_85_ds_d2h[30] = tl_sm1_81_us_d2h[1]; + + assign tl_sm1_82_us_h2d[1] = tl_s1n_85_ds_h2d[31]; + assign tl_s1n_85_ds_d2h[31] = tl_sm1_82_us_d2h[1]; + + assign tl_sm1_83_us_h2d[1] = tl_s1n_85_ds_h2d[32]; + assign tl_s1n_85_ds_d2h[32] = tl_sm1_83_us_d2h[1]; + + assign tl_sm1_84_us_h2d[1] = tl_s1n_85_ds_h2d[33]; + assign tl_s1n_85_ds_d2h[33] = tl_sm1_84_us_d2h[1]; + + assign tl_sm1_52_us_h2d[3] = tl_s1n_86_ds_h2d[0]; + assign tl_s1n_86_ds_d2h[0] = tl_sm1_52_us_d2h[3]; + + assign tl_sm1_71_us_h2d[2] = tl_s1n_86_ds_h2d[1]; + assign tl_s1n_86_ds_d2h[1] = tl_sm1_71_us_d2h[2]; + + assign tl_sm1_60_us_h2d[2] = tl_s1n_86_ds_h2d[2]; + assign tl_s1n_86_ds_d2h[2] = tl_sm1_60_us_d2h[2]; + + assign tl_sm1_64_us_h2d[2] = tl_s1n_86_ds_h2d[3]; + assign tl_s1n_86_ds_d2h[3] = tl_sm1_64_us_d2h[2]; + + assign tl_sm1_66_us_h2d[2] = tl_s1n_86_ds_h2d[4]; + assign tl_s1n_86_ds_d2h[4] = tl_sm1_66_us_d2h[2]; + + assign tl_sm1_67_us_h2d[2] = tl_s1n_86_ds_h2d[5]; + assign tl_s1n_86_ds_d2h[5] = tl_sm1_67_us_d2h[2]; + + assign tl_sm1_68_us_h2d[2] = tl_s1n_86_ds_h2d[6]; + assign tl_s1n_86_ds_d2h[6] = tl_sm1_68_us_d2h[2]; + + assign tl_sm1_53_us_h2d[3] = tl_s1n_86_ds_h2d[7]; + assign tl_s1n_86_ds_d2h[7] = tl_sm1_53_us_d2h[3]; + + assign tl_sm1_59_us_h2d[2] = tl_s1n_86_ds_h2d[8]; + assign tl_s1n_86_ds_d2h[8] = tl_sm1_59_us_d2h[2]; + + assign tl_sm1_71_us_h2d[3] = tl_mbx0__sram_i; + assign tl_mbx0__sram_o = tl_sm1_71_us_d2h[3]; + + assign tl_sm1_71_us_h2d[4] = tl_mbx1__sram_i; + assign tl_mbx1__sram_o = tl_sm1_71_us_d2h[4]; + + assign tl_sm1_71_us_h2d[5] = tl_mbx2__sram_i; + assign tl_mbx2__sram_o = tl_sm1_71_us_d2h[5]; + + assign tl_sm1_71_us_h2d[6] = tl_mbx3__sram_i; + assign tl_mbx3__sram_o = tl_sm1_71_us_d2h[6]; + + assign tl_sm1_71_us_h2d[7] = tl_mbx4__sram_i; + assign tl_mbx4__sram_o = tl_sm1_71_us_d2h[7]; + + assign tl_sm1_71_us_h2d[8] = tl_mbx5__sram_i; + assign tl_mbx5__sram_o = tl_sm1_71_us_d2h[8]; + + assign tl_sm1_71_us_h2d[9] = tl_mbx6__sram_i; + assign tl_mbx6__sram_o = tl_sm1_71_us_d2h[9]; + + assign tl_sm1_71_us_h2d[10] = tl_mbx_jtag__sram_i; + assign tl_mbx_jtag__sram_o = tl_sm1_71_us_d2h[10]; + + assign tl_sm1_71_us_h2d[11] = tl_mbx_pcie0__sram_i; + assign tl_mbx_pcie0__sram_o = tl_sm1_71_us_d2h[11]; + + assign tl_sm1_71_us_h2d[12] = tl_mbx_pcie1__sram_i; + assign tl_mbx_pcie1__sram_o = tl_sm1_71_us_d2h[12]; + + assign tl_s1n_48_us_h2d = tl_rv_core_ibex__corei_i; + assign tl_rv_core_ibex__corei_o = tl_s1n_48_us_d2h; + + assign tl_rom_ctrl0__rom_o = tl_sm1_49_ds_h2d; + assign tl_sm1_49_ds_d2h = tl_rom_ctrl0__rom_i; + + assign tl_rom_ctrl1__rom_o = tl_sm1_50_ds_h2d; + assign tl_sm1_50_ds_d2h = tl_rom_ctrl1__rom_i; + + assign tl_rv_dm__mem_o = tl_sm1_51_ds_h2d; + assign tl_sm1_51_ds_d2h = tl_rv_dm__mem_i; + + assign tl_sram_ctrl_main__ram_o = tl_sm1_52_ds_h2d; + assign tl_sm1_52_ds_d2h = tl_sram_ctrl_main__ram_i; + + assign tl_soc_proxy__ctn_o = tl_sm1_53_ds_h2d; + assign tl_sm1_53_ds_d2h = tl_soc_proxy__ctn_i; + + assign tl_s1n_54_us_h2d = tl_rv_core_ibex__cored_i; + assign tl_rv_core_ibex__cored_o = tl_s1n_54_us_d2h; + + assign tl_rom_ctrl0__regs_o = tl_sm1_55_ds_h2d; + assign tl_sm1_55_ds_d2h = tl_rom_ctrl0__regs_i; + + assign tl_rom_ctrl1__regs_o = tl_sm1_56_ds_h2d; + assign tl_sm1_56_ds_d2h = tl_rom_ctrl1__regs_i; + + assign tl_rv_dm__regs_o = tl_sm1_57_ds_h2d; + assign tl_sm1_57_ds_d2h = tl_rv_dm__regs_i; + + assign tl_peri_o = tl_asf_58_ds_h2d; + assign tl_asf_58_ds_d2h = tl_peri_i; + + assign tl_asf_58_us_h2d = tl_sm1_59_ds_h2d; + assign tl_sm1_59_ds_d2h = tl_asf_58_us_d2h; + + assign tl_aes_o = tl_sm1_60_ds_h2d; + assign tl_sm1_60_ds_d2h = tl_aes_i; + + assign tl_csrng_o = tl_sm1_61_ds_h2d; + assign tl_sm1_61_ds_d2h = tl_csrng_i; + + assign tl_edn0_o = tl_sm1_62_ds_h2d; + assign tl_sm1_62_ds_d2h = tl_edn0_i; + + assign tl_edn1_o = tl_sm1_63_ds_h2d; + assign tl_sm1_63_ds_d2h = tl_edn1_i; + + assign tl_hmac_o = tl_sm1_64_ds_h2d; + assign tl_sm1_64_ds_d2h = tl_hmac_i; + + assign tl_rv_plic_o = tl_sm1_65_ds_h2d; + assign tl_sm1_65_ds_d2h = tl_rv_plic_i; + + assign tl_otbn_o = tl_sm1_66_ds_h2d; + assign tl_sm1_66_ds_d2h = tl_otbn_i; + + assign tl_keymgr_dpe_o = tl_sm1_67_ds_h2d; + assign tl_sm1_67_ds_d2h = tl_keymgr_dpe_i; + + assign tl_kmac_o = tl_sm1_68_ds_h2d; + assign tl_sm1_68_ds_d2h = tl_kmac_i; + + assign tl_sram_ctrl_main__regs_o = tl_sm1_69_ds_h2d; + assign tl_sm1_69_ds_d2h = tl_sram_ctrl_main__regs_i; + + assign tl_rv_core_ibex__cfg_o = tl_sm1_70_ds_h2d; + assign tl_sm1_70_ds_d2h = tl_rv_core_ibex__cfg_i; + + assign tl_sram_ctrl_mbox__ram_o = tl_sm1_71_ds_h2d; + assign tl_sm1_71_ds_d2h = tl_sram_ctrl_mbox__ram_i; + + assign tl_sram_ctrl_mbox__regs_o = tl_sm1_72_ds_h2d; + assign tl_sm1_72_ds_d2h = tl_sram_ctrl_mbox__regs_i; + + assign tl_soc_proxy__core_o = tl_sm1_73_ds_h2d; + assign tl_sm1_73_ds_d2h = tl_soc_proxy__core_i; + + assign tl_dma_o = tl_sm1_74_ds_h2d; + assign tl_sm1_74_ds_d2h = tl_dma_i; + + assign tl_mbx0__core_o = tl_sm1_75_ds_h2d; + assign tl_sm1_75_ds_d2h = tl_mbx0__core_i; + + assign tl_mbx1__core_o = tl_sm1_76_ds_h2d; + assign tl_sm1_76_ds_d2h = tl_mbx1__core_i; + + assign tl_mbx2__core_o = tl_sm1_77_ds_h2d; + assign tl_sm1_77_ds_d2h = tl_mbx2__core_i; + + assign tl_mbx3__core_o = tl_sm1_78_ds_h2d; + assign tl_sm1_78_ds_d2h = tl_mbx3__core_i; + + assign tl_mbx4__core_o = tl_sm1_79_ds_h2d; + assign tl_sm1_79_ds_d2h = tl_mbx4__core_i; + + assign tl_mbx5__core_o = tl_sm1_80_ds_h2d; + assign tl_sm1_80_ds_d2h = tl_mbx5__core_i; + + assign tl_mbx6__core_o = tl_sm1_81_ds_h2d; + assign tl_sm1_81_ds_d2h = tl_mbx6__core_i; + + assign tl_mbx_jtag__core_o = tl_sm1_82_ds_h2d; + assign tl_sm1_82_ds_d2h = tl_mbx_jtag__core_i; + + assign tl_mbx_pcie0__core_o = tl_sm1_83_ds_h2d; + assign tl_sm1_83_ds_d2h = tl_mbx_pcie0__core_i; + + assign tl_mbx_pcie1__core_o = tl_sm1_84_ds_h2d; + assign tl_sm1_84_ds_d2h = tl_mbx_pcie1__core_i; + + assign tl_s1n_85_us_h2d = tl_rv_dm__sba_i; + assign tl_rv_dm__sba_o = tl_s1n_85_us_d2h; + + assign tl_s1n_86_us_h2d = tl_dma__host_i; + assign tl_dma__host_o = tl_s1n_86_us_d2h; + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_48 = 3'd5; + if ((tl_s1n_48_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL0__ROM)) == ADDR_SPACE_ROM_CTRL0__ROM) begin + dev_sel_s1n_48 = 3'd0; + + end else if ((tl_s1n_48_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL1__ROM)) == ADDR_SPACE_ROM_CTRL1__ROM) begin + dev_sel_s1n_48 = 3'd1; + + end else if ((tl_s1n_48_us_h2d.a_address & + ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin + dev_sel_s1n_48 = 3'd2; + + end else if ((tl_s1n_48_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin + dev_sel_s1n_48 = 3'd3; + + end else if ((tl_s1n_48_us_h2d.a_address & + ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin + dev_sel_s1n_48 = 3'd4; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_54 = 6'd34; + if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL0__ROM)) == ADDR_SPACE_ROM_CTRL0__ROM) begin + dev_sel_s1n_54 = 6'd0; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL0__REGS)) == ADDR_SPACE_ROM_CTRL0__REGS) begin + dev_sel_s1n_54 = 6'd1; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL1__ROM)) == ADDR_SPACE_ROM_CTRL1__ROM) begin + dev_sel_s1n_54 = 6'd2; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL1__REGS)) == ADDR_SPACE_ROM_CTRL1__REGS) begin + dev_sel_s1n_54 = 6'd3; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin + dev_sel_s1n_54 = 6'd4; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin + dev_sel_s1n_54 = 6'd5; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin + dev_sel_s1n_54 = 6'd6; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_PERI)) == ADDR_SPACE_PERI) begin + dev_sel_s1n_54 = 6'd7; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin + dev_sel_s1n_54 = 6'd8; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin + dev_sel_s1n_54 = 6'd9; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin + dev_sel_s1n_54 = 6'd10; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin + dev_sel_s1n_54 = 6'd11; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin + dev_sel_s1n_54 = 6'd12; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin + dev_sel_s1n_54 = 6'd13; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin + dev_sel_s1n_54 = 6'd14; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_KEYMGR_DPE)) == ADDR_SPACE_KEYMGR_DPE) begin + dev_sel_s1n_54 = 6'd15; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin + dev_sel_s1n_54 = 6'd16; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin + dev_sel_s1n_54 = 6'd17; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin + dev_sel_s1n_54 = 6'd18; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_54 = 6'd19; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__REGS)) == ADDR_SPACE_SRAM_CTRL_MBOX__REGS) begin + dev_sel_s1n_54 = 6'd20; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin + dev_sel_s1n_54 = 6'd21; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_SOC_PROXY__CORE)) == ADDR_SPACE_SOC_PROXY__CORE) begin + dev_sel_s1n_54 = 6'd22; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_DMA)) == ADDR_SPACE_DMA) begin + dev_sel_s1n_54 = 6'd23; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_MBX0__CORE)) == ADDR_SPACE_MBX0__CORE) begin + dev_sel_s1n_54 = 6'd24; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_MBX1__CORE)) == ADDR_SPACE_MBX1__CORE) begin + dev_sel_s1n_54 = 6'd25; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_MBX2__CORE)) == ADDR_SPACE_MBX2__CORE) begin + dev_sel_s1n_54 = 6'd26; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_MBX3__CORE)) == ADDR_SPACE_MBX3__CORE) begin + dev_sel_s1n_54 = 6'd27; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_MBX4__CORE)) == ADDR_SPACE_MBX4__CORE) begin + dev_sel_s1n_54 = 6'd28; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_MBX5__CORE)) == ADDR_SPACE_MBX5__CORE) begin + dev_sel_s1n_54 = 6'd29; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_MBX6__CORE)) == ADDR_SPACE_MBX6__CORE) begin + dev_sel_s1n_54 = 6'd30; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_MBX_JTAG__CORE)) == ADDR_SPACE_MBX_JTAG__CORE) begin + dev_sel_s1n_54 = 6'd31; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_MBX_PCIE0__CORE)) == ADDR_SPACE_MBX_PCIE0__CORE) begin + dev_sel_s1n_54 = 6'd32; + + end else if ((tl_s1n_54_us_h2d.a_address & + ~(ADDR_MASK_MBX_PCIE1__CORE)) == ADDR_SPACE_MBX_PCIE1__CORE) begin + dev_sel_s1n_54 = 6'd33; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_85 = 6'd34; + if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL0__ROM)) == ADDR_SPACE_ROM_CTRL0__ROM) begin + dev_sel_s1n_85 = 6'd0; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL0__REGS)) == ADDR_SPACE_ROM_CTRL0__REGS) begin + dev_sel_s1n_85 = 6'd1; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL1__ROM)) == ADDR_SPACE_ROM_CTRL1__ROM) begin + dev_sel_s1n_85 = 6'd2; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL1__REGS)) == ADDR_SPACE_ROM_CTRL1__REGS) begin + dev_sel_s1n_85 = 6'd3; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin + dev_sel_s1n_85 = 6'd4; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin + dev_sel_s1n_85 = 6'd5; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin + dev_sel_s1n_85 = 6'd6; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_PERI)) == ADDR_SPACE_PERI) begin + dev_sel_s1n_85 = 6'd7; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin + dev_sel_s1n_85 = 6'd8; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin + dev_sel_s1n_85 = 6'd9; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin + dev_sel_s1n_85 = 6'd10; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin + dev_sel_s1n_85 = 6'd11; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin + dev_sel_s1n_85 = 6'd12; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin + dev_sel_s1n_85 = 6'd13; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin + dev_sel_s1n_85 = 6'd14; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_KEYMGR_DPE)) == ADDR_SPACE_KEYMGR_DPE) begin + dev_sel_s1n_85 = 6'd15; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin + dev_sel_s1n_85 = 6'd16; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin + dev_sel_s1n_85 = 6'd17; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_RV_CORE_IBEX__CFG)) == ADDR_SPACE_RV_CORE_IBEX__CFG) begin + dev_sel_s1n_85 = 6'd18; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_85 = 6'd19; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__REGS)) == ADDR_SPACE_SRAM_CTRL_MBOX__REGS) begin + dev_sel_s1n_85 = 6'd20; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin + dev_sel_s1n_85 = 6'd21; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_SOC_PROXY__CORE)) == ADDR_SPACE_SOC_PROXY__CORE) begin + dev_sel_s1n_85 = 6'd22; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_DMA)) == ADDR_SPACE_DMA) begin + dev_sel_s1n_85 = 6'd23; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_MBX0__CORE)) == ADDR_SPACE_MBX0__CORE) begin + dev_sel_s1n_85 = 6'd24; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_MBX1__CORE)) == ADDR_SPACE_MBX1__CORE) begin + dev_sel_s1n_85 = 6'd25; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_MBX2__CORE)) == ADDR_SPACE_MBX2__CORE) begin + dev_sel_s1n_85 = 6'd26; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_MBX3__CORE)) == ADDR_SPACE_MBX3__CORE) begin + dev_sel_s1n_85 = 6'd27; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_MBX4__CORE)) == ADDR_SPACE_MBX4__CORE) begin + dev_sel_s1n_85 = 6'd28; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_MBX5__CORE)) == ADDR_SPACE_MBX5__CORE) begin + dev_sel_s1n_85 = 6'd29; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_MBX6__CORE)) == ADDR_SPACE_MBX6__CORE) begin + dev_sel_s1n_85 = 6'd30; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_MBX_JTAG__CORE)) == ADDR_SPACE_MBX_JTAG__CORE) begin + dev_sel_s1n_85 = 6'd31; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_MBX_PCIE0__CORE)) == ADDR_SPACE_MBX_PCIE0__CORE) begin + dev_sel_s1n_85 = 6'd32; + + end else if ((tl_s1n_85_us_h2d.a_address & + ~(ADDR_MASK_MBX_PCIE1__CORE)) == ADDR_SPACE_MBX_PCIE1__CORE) begin + dev_sel_s1n_85 = 6'd33; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_86 = 4'd9; + if ((tl_s1n_86_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin + dev_sel_s1n_86 = 4'd0; + + end else if ((tl_s1n_86_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_86 = 4'd1; + + end else if ((tl_s1n_86_us_h2d.a_address & + ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin + dev_sel_s1n_86 = 4'd2; + + end else if ((tl_s1n_86_us_h2d.a_address & + ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin + dev_sel_s1n_86 = 4'd3; + + end else if ((tl_s1n_86_us_h2d.a_address & + ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin + dev_sel_s1n_86 = 4'd4; + + end else if ((tl_s1n_86_us_h2d.a_address & + ~(ADDR_MASK_KEYMGR_DPE)) == ADDR_SPACE_KEYMGR_DPE) begin + dev_sel_s1n_86 = 4'd5; + + end else if ((tl_s1n_86_us_h2d.a_address & + ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin + dev_sel_s1n_86 = 4'd6; + + end else if ((tl_s1n_86_us_h2d.a_address & + ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin + dev_sel_s1n_86 = 4'd7; + + end else if ((tl_s1n_86_us_h2d.a_address & + ~(ADDR_MASK_PERI)) == ADDR_SPACE_PERI) begin + dev_sel_s1n_86 = 4'd8; +end + end + + + // Instantiation phase + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (20'h0), + .DRspDepth (20'h0), + .N (5) + ) u_s1n_48 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_48_us_h2d), + .tl_h_o (tl_s1n_48_us_d2h), + .tl_d_o (tl_s1n_48_ds_h2d), + .tl_d_i (tl_s1n_48_ds_d2h), + .dev_select_i (dev_sel_s1n_48) + ); + tlul_socket_m1 #( + .HReqDepth (12'h0), + .HRspDepth (12'h0), + .DRspPass (1'b0), + .M (3) + ) u_sm1_49 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_49_us_h2d), + .tl_h_o (tl_sm1_49_us_d2h), + .tl_d_o (tl_sm1_49_ds_h2d), + .tl_d_i (tl_sm1_49_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (12'h0), + .HRspDepth (12'h0), + .DRspPass (1'b0), + .M (3) + ) u_sm1_50 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_50_us_h2d), + .tl_h_o (tl_sm1_50_us_d2h), + .tl_d_o (tl_sm1_50_ds_h2d), + .tl_d_i (tl_sm1_50_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (12'h0), + .HRspDepth (12'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (3) + ) u_sm1_51 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_51_us_h2d), + .tl_h_o (tl_sm1_51_us_d2h), + .tl_d_o (tl_sm1_51_ds_h2d), + .tl_d_i (tl_sm1_51_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (16'h0), + .HRspDepth (16'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (4) + ) u_sm1_52 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_52_us_h2d), + .tl_h_o (tl_sm1_52_us_d2h), + .tl_d_o (tl_sm1_52_ds_h2d), + .tl_d_i (tl_sm1_52_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (16'h0), + .HRspDepth (16'h0), + .DRspPass (1'b0), + .M (4) + ) u_sm1_53 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_53_us_h2d), + .tl_h_o (tl_sm1_53_us_d2h), + .tl_d_o (tl_sm1_53_ds_h2d), + .tl_d_i (tl_sm1_53_ds_d2h) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (136'h0), + .DRspDepth (136'h0), + .N (34) + ) u_s1n_54 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_54_us_h2d), + .tl_h_o (tl_s1n_54_us_d2h), + .tl_d_o (tl_s1n_54_ds_h2d), + .tl_d_i (tl_s1n_54_ds_d2h), + .dev_select_i (dev_sel_s1n_54) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_55 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_55_us_h2d), + .tl_h_o (tl_sm1_55_us_d2h), + .tl_d_o (tl_sm1_55_ds_h2d), + .tl_d_i (tl_sm1_55_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_56 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_56_us_h2d), + .tl_h_o (tl_sm1_56_us_d2h), + .tl_d_o (tl_sm1_56_ds_h2d), + .tl_d_i (tl_sm1_56_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_57 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_57_us_h2d), + .tl_h_o (tl_sm1_57_us_d2h), + .tl_d_o (tl_sm1_57_ds_h2d), + .tl_d_i (tl_sm1_57_ds_d2h) + ); + tlul_fifo_async #( + .ReqDepth (1), + .RspDepth (1) + ) u_asf_58 ( + .clk_h_i (clk_main_i), + .rst_h_ni (rst_main_ni), + .clk_d_i (clk_fixed_i), + .rst_d_ni (rst_fixed_ni), + .tl_h_i (tl_asf_58_us_h2d), + .tl_h_o (tl_asf_58_us_d2h), + .tl_d_o (tl_asf_58_ds_h2d), + .tl_d_i (tl_asf_58_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (12'h0), + .HRspDepth (12'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (3) + ) u_sm1_59 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_59_us_h2d), + .tl_h_o (tl_sm1_59_us_d2h), + .tl_d_o (tl_sm1_59_ds_h2d), + .tl_d_i (tl_sm1_59_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (12'h0), + .HRspDepth (12'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (3) + ) u_sm1_60 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_60_us_h2d), + .tl_h_o (tl_sm1_60_us_d2h), + .tl_d_o (tl_sm1_60_ds_h2d), + .tl_d_i (tl_sm1_60_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_61 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_61_us_h2d), + .tl_h_o (tl_sm1_61_us_d2h), + .tl_d_o (tl_sm1_61_ds_h2d), + .tl_d_i (tl_sm1_61_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_62 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_62_us_h2d), + .tl_h_o (tl_sm1_62_us_d2h), + .tl_d_o (tl_sm1_62_ds_h2d), + .tl_d_i (tl_sm1_62_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_63 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_63_us_h2d), + .tl_h_o (tl_sm1_63_us_d2h), + .tl_d_o (tl_sm1_63_ds_h2d), + .tl_d_i (tl_sm1_63_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (12'h0), + .HRspDepth (12'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (3) + ) u_sm1_64 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_64_us_h2d), + .tl_h_o (tl_sm1_64_us_d2h), + .tl_d_o (tl_sm1_64_ds_h2d), + .tl_d_i (tl_sm1_64_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_65 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_65_us_h2d), + .tl_h_o (tl_sm1_65_us_d2h), + .tl_d_o (tl_sm1_65_ds_h2d), + .tl_d_i (tl_sm1_65_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (12'h0), + .HRspDepth (12'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (3) + ) u_sm1_66 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_66_us_h2d), + .tl_h_o (tl_sm1_66_us_d2h), + .tl_d_o (tl_sm1_66_ds_h2d), + .tl_d_i (tl_sm1_66_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (12'h0), + .HRspDepth (12'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (3) + ) u_sm1_67 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_67_us_h2d), + .tl_h_o (tl_sm1_67_us_d2h), + .tl_d_o (tl_sm1_67_ds_h2d), + .tl_d_i (tl_sm1_67_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (12'h0), + .HRspDepth (12'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (3) + ) u_sm1_68 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_68_us_h2d), + .tl_h_o (tl_sm1_68_us_d2h), + .tl_d_o (tl_sm1_68_ds_h2d), + .tl_d_i (tl_sm1_68_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_69 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_69_us_h2d), + .tl_h_o (tl_sm1_69_us_d2h), + .tl_d_o (tl_sm1_69_ds_h2d), + .tl_d_i (tl_sm1_69_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_70 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_70_us_h2d), + .tl_h_o (tl_sm1_70_us_d2h), + .tl_d_o (tl_sm1_70_ds_h2d), + .tl_d_i (tl_sm1_70_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (52'h0), + .HRspDepth (52'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (13) + ) u_sm1_71 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_71_us_h2d), + .tl_h_o (tl_sm1_71_us_d2h), + .tl_d_o (tl_sm1_71_ds_h2d), + .tl_d_i (tl_sm1_71_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_72 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_72_us_h2d), + .tl_h_o (tl_sm1_72_us_d2h), + .tl_d_o (tl_sm1_72_ds_h2d), + .tl_d_i (tl_sm1_72_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_73 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_73_us_h2d), + .tl_h_o (tl_sm1_73_us_d2h), + .tl_d_o (tl_sm1_73_ds_h2d), + .tl_d_i (tl_sm1_73_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_74 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_74_us_h2d), + .tl_h_o (tl_sm1_74_us_d2h), + .tl_d_o (tl_sm1_74_ds_h2d), + .tl_d_i (tl_sm1_74_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_75 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_75_us_h2d), + .tl_h_o (tl_sm1_75_us_d2h), + .tl_d_o (tl_sm1_75_ds_h2d), + .tl_d_i (tl_sm1_75_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_76 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_76_us_h2d), + .tl_h_o (tl_sm1_76_us_d2h), + .tl_d_o (tl_sm1_76_ds_h2d), + .tl_d_i (tl_sm1_76_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_77 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_77_us_h2d), + .tl_h_o (tl_sm1_77_us_d2h), + .tl_d_o (tl_sm1_77_ds_h2d), + .tl_d_i (tl_sm1_77_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_78 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_78_us_h2d), + .tl_h_o (tl_sm1_78_us_d2h), + .tl_d_o (tl_sm1_78_ds_h2d), + .tl_d_i (tl_sm1_78_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_79 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_79_us_h2d), + .tl_h_o (tl_sm1_79_us_d2h), + .tl_d_o (tl_sm1_79_ds_h2d), + .tl_d_i (tl_sm1_79_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_80 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_80_us_h2d), + .tl_h_o (tl_sm1_80_us_d2h), + .tl_d_o (tl_sm1_80_ds_h2d), + .tl_d_i (tl_sm1_80_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_81 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_81_us_h2d), + .tl_h_o (tl_sm1_81_us_d2h), + .tl_d_o (tl_sm1_81_ds_h2d), + .tl_d_i (tl_sm1_81_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_82 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_82_us_h2d), + .tl_h_o (tl_sm1_82_us_d2h), + .tl_d_o (tl_sm1_82_ds_h2d), + .tl_d_i (tl_sm1_82_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_83 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_83_us_h2d), + .tl_h_o (tl_sm1_83_us_d2h), + .tl_d_o (tl_sm1_83_ds_h2d), + .tl_d_i (tl_sm1_83_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_84 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_84_us_h2d), + .tl_h_o (tl_sm1_84_us_d2h), + .tl_d_o (tl_sm1_84_ds_h2d), + .tl_d_i (tl_sm1_84_ds_d2h) + ); + tlul_socket_1n #( + .HReqPass (1'b0), + .HRspPass (1'b0), + .DReqDepth (136'h0), + .DRspDepth (136'h0), + .N (34) + ) u_s1n_85 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_85_us_h2d), + .tl_h_o (tl_s1n_85_us_d2h), + .tl_d_o (tl_s1n_85_ds_h2d), + .tl_d_i (tl_s1n_85_ds_d2h), + .dev_select_i (dev_sel_s1n_85) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (36'h0), + .DRspDepth (36'h0), + .N (9) + ) u_s1n_86 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_86_us_h2d), + .tl_h_o (tl_s1n_86_us_d2h), + .tl_d_o (tl_s1n_86_ds_h2d), + .tl_d_i (tl_s1n_86_ds_d2h), + .dev_select_i (dev_sel_s1n_86) + ); + +endmodule diff --git a/hw/top_darjeeling/ip/xbar_main/xbar_main.core b/hw/top_darjeeling/ip/xbar_main/xbar_main.core new file mode 100644 index 0000000000000..0b325aa4bf144 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_main/xbar_main.core @@ -0,0 +1,25 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_main core file generated by `tlgen.py` tool +name: "lowrisc:top_darjeeling:xbar_main:0.1" +description: "Generated RTL xbar_main" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:ip:lc_ctrl_pkg + files: + - rtl/autogen/tl_main_pkg.sv + - rtl/autogen/xbar_main.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: xbar_main diff --git a/hw/top_darjeeling/ip/xbar_mbx/data/autogen/xbar_mbx.gen.hjson b/hw/top_darjeeling/ip/xbar_mbx/data/autogen/xbar_mbx.gen.hjson new file mode 100644 index 0000000000000..fbac92796ec80 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_mbx/data/autogen/xbar_mbx.gen.hjson @@ -0,0 +1,268 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson -o hw/top_darjeeling/ + +{ + name: mbx + clock_srcs: + { + clk_mbx_i: main + } + clock_group: infra + reset: rst_mbx_ni + reset_connections: + { + rst_mbx_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_mbx_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + connections: + { + mbx: + [ + mbx0.soc + mbx1.soc + mbx2.soc + mbx3.soc + mbx4.soc + mbx5.soc + mbx6.soc + mbx_pcie0.soc + mbx_pcie1.soc + ] + } + nodes: + [ + { + name: mbx + type: host + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + xbar: true + pipeline: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx0.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx1.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465100 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx2.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465200 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx3.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465300 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx4.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465400 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx5.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465500 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx6.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465600 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie0.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1460100 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie1.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1460200 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + ] + addr_spaces: + [ + soc_mbx + ] + clock: clk_mbx_i + type: xbar +} diff --git a/hw/top_darjeeling/ip/xbar_mbx/data/autogen/xbar_mbx.hjson b/hw/top_darjeeling/ip/xbar_mbx/data/autogen/xbar_mbx.hjson new file mode 100644 index 0000000000000..be093a98291ba --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_mbx/data/autogen/xbar_mbx.hjson @@ -0,0 +1,77 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_mbx comportable IP spec generated by `tlgen.py` tool +{ name: "xbar_mbx" + clock_primary: "" + other_clock_list: [] + reset_primary: "" + other_reset_list: [] + //available_input_list: [] + + inter_signal_list: [ + // host + { struct: "tl" + type: "req_rsp" + name: "tl_mbx" + act: "rsp" + package: "tlul_pkg" + } + // device + { struct: "tl" + type: "req_rsp" + name: "tl_mbx0__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx1__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx2__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx3__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx4__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx5__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx6__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie0__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie1__soc" + act: "req" + package: "tlul_pkg" + } + ] +} diff --git a/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/tb__xbar_connect.sv new file mode 100644 index 0000000000000..b748f39dd3a7c --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/tb__xbar_connect.sv @@ -0,0 +1,28 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__xbar_connect generated by `tlgen.py` tool + +xbar_mbx dut(); + +`DRIVE_CLK(clk_mbx_i) + +initial force dut.clk_mbx_i = clk_mbx_i; + +// TODO, all resets tie together +initial force dut.rst_mbx_ni = rst_n; + +// Host TileLink interface connections +`CONNECT_TL_HOST_IF(mbx, dut, clk_mbx_i, rst_n) + +// Device TileLink interface connections +`CONNECT_TL_DEVICE_IF(mbx0__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx1__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx2__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx3__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx4__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx5__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx6__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx_pcie0__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx_pcie1__soc, dut, clk_mbx_i, rst_n) diff --git a/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_cov_excl.el b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_cov_excl.el new file mode 100644 index 0000000000000..a6c31310191ed --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_cov_excl.el @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cov_excl.el generated by `tlgen.py` tool + +ANNOTATION: "[NON_RTL]" +MODULE: uvm_pkg +Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion" +Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion" + +ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim" +MODULE: xbar_mbx +Block 1 "0" "assign unused_scanmode = scanmode_i;" diff --git a/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_cover.cfg b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_cover.cfg new file mode 100644 index 0000000000000..175c8df9f19f7 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_cover.cfg @@ -0,0 +1,88 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cover.cfg generated by `tlgen.py` tool + ++tree tb.dut +-module pins_if // DV construct. +-module clk_rst_if // DV construct. + +-assert legalAOpcodeErr_A +-assert sizeGTEMaskErr_A +-assert sizeMatchesMaskErr_A +-assert addrSizeAlignedErr_A + +// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after. +-node tb.dut tl_*.a_param +-node tb.dut tl_*.d_param +-node tb.dut tl_*.d_opcode[2:1] + +-moduletree prim_cdc_rand_delay // exclude DV construct. + +// [UNR] these device address bits are always 0 +-node tb.dut tl_mbx0__soc_o.a_address[11:5] +-node tb.dut tl_mbx0__soc_o.a_address[13:13] +-node tb.dut tl_mbx0__soc_o.a_address[16:15] +-node tb.dut tl_mbx0__soc_o.a_address[21:19] +-node tb.dut tl_mbx0__soc_o.a_address[23:23] +-node tb.dut tl_mbx0__soc_o.a_address[31:25] +-node tb.dut tl_mbx1__soc_o.a_address[7:5] +-node tb.dut tl_mbx1__soc_o.a_address[11:9] +-node tb.dut tl_mbx1__soc_o.a_address[13:13] +-node tb.dut tl_mbx1__soc_o.a_address[16:15] +-node tb.dut tl_mbx1__soc_o.a_address[21:19] +-node tb.dut tl_mbx1__soc_o.a_address[23:23] +-node tb.dut tl_mbx1__soc_o.a_address[31:25] +-node tb.dut tl_mbx2__soc_o.a_address[8:5] +-node tb.dut tl_mbx2__soc_o.a_address[11:10] +-node tb.dut tl_mbx2__soc_o.a_address[13:13] +-node tb.dut tl_mbx2__soc_o.a_address[16:15] +-node tb.dut tl_mbx2__soc_o.a_address[21:19] +-node tb.dut tl_mbx2__soc_o.a_address[23:23] +-node tb.dut tl_mbx2__soc_o.a_address[31:25] +-node tb.dut tl_mbx3__soc_o.a_address[7:5] +-node tb.dut tl_mbx3__soc_o.a_address[11:10] +-node tb.dut tl_mbx3__soc_o.a_address[13:13] +-node tb.dut tl_mbx3__soc_o.a_address[16:15] +-node tb.dut tl_mbx3__soc_o.a_address[21:19] +-node tb.dut tl_mbx3__soc_o.a_address[23:23] +-node tb.dut tl_mbx3__soc_o.a_address[31:25] +-node tb.dut tl_mbx4__soc_o.a_address[9:5] +-node tb.dut tl_mbx4__soc_o.a_address[11:11] +-node tb.dut tl_mbx4__soc_o.a_address[13:13] +-node tb.dut tl_mbx4__soc_o.a_address[16:15] +-node tb.dut tl_mbx4__soc_o.a_address[21:19] +-node tb.dut tl_mbx4__soc_o.a_address[23:23] +-node tb.dut tl_mbx4__soc_o.a_address[31:25] +-node tb.dut tl_mbx5__soc_o.a_address[7:5] +-node tb.dut tl_mbx5__soc_o.a_address[9:9] +-node tb.dut tl_mbx5__soc_o.a_address[11:11] +-node tb.dut tl_mbx5__soc_o.a_address[13:13] +-node tb.dut tl_mbx5__soc_o.a_address[16:15] +-node tb.dut tl_mbx5__soc_o.a_address[21:19] +-node tb.dut tl_mbx5__soc_o.a_address[23:23] +-node tb.dut tl_mbx5__soc_o.a_address[31:25] +-node tb.dut tl_mbx6__soc_o.a_address[8:5] +-node tb.dut tl_mbx6__soc_o.a_address[11:11] +-node tb.dut tl_mbx6__soc_o.a_address[13:13] +-node tb.dut tl_mbx6__soc_o.a_address[16:15] +-node tb.dut tl_mbx6__soc_o.a_address[21:19] +-node tb.dut tl_mbx6__soc_o.a_address[23:23] +-node tb.dut tl_mbx6__soc_o.a_address[31:25] +-node tb.dut tl_mbx_pcie0__soc_o.a_address[7:5] +-node tb.dut tl_mbx_pcie0__soc_o.a_address[16:9] +-node tb.dut tl_mbx_pcie0__soc_o.a_address[21:19] +-node tb.dut tl_mbx_pcie0__soc_o.a_address[23:23] +-node tb.dut tl_mbx_pcie0__soc_o.a_address[31:25] +-node tb.dut tl_mbx_pcie1__soc_o.a_address[8:5] +-node tb.dut tl_mbx_pcie1__soc_o.a_address[16:10] +-node tb.dut tl_mbx_pcie1__soc_o.a_address[21:19] +-node tb.dut tl_mbx_pcie1__soc_o.a_address[23:23] +-node tb.dut tl_mbx_pcie1__soc_o.a_address[31:25] + +begin tgl + -tree tb + +tree tb.dut 1 + -node tb.dut.scanmode_i +end diff --git a/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_env_pkg__params.sv new file mode 100644 index 0000000000000..b8201a42d9e91 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_env_pkg__params.sv @@ -0,0 +1,50 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_env_pkg__params generated by `tlgen.py` tool + + +// List of Xbar device memory map +tl_device_t xbar_devices[$] = '{ + '{"mbx0__soc", '{ + '{32'h01465000, 32'h0146501f} + }}, + '{"mbx1__soc", '{ + '{32'h01465100, 32'h0146511f} + }}, + '{"mbx2__soc", '{ + '{32'h01465200, 32'h0146521f} + }}, + '{"mbx3__soc", '{ + '{32'h01465300, 32'h0146531f} + }}, + '{"mbx4__soc", '{ + '{32'h01465400, 32'h0146541f} + }}, + '{"mbx5__soc", '{ + '{32'h01465500, 32'h0146551f} + }}, + '{"mbx6__soc", '{ + '{32'h01465600, 32'h0146561f} + }}, + '{"mbx_pcie0__soc", '{ + '{32'h01460100, 32'h0146011f} + }}, + '{"mbx_pcie1__soc", '{ + '{32'h01460200, 32'h0146021f} +}}}; + + // List of Xbar hosts +tl_host_t xbar_hosts[$] = '{ + '{"mbx", 0, '{ + "mbx0__soc", + "mbx1__soc", + "mbx2__soc", + "mbx3__soc", + "mbx4__soc", + "mbx5__soc", + "mbx6__soc", + "mbx_pcie0__soc", + "mbx_pcie1__soc"}} +}; diff --git a/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_mbx_bind.core b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_mbx_bind.core new file mode 100644 index 0000000000000..c28f2fe3f27f8 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_mbx_bind.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_mbx_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_xbar_mbx_bind:0.1" +description: "XBAR mbx assertion bind" +filesets: + files_dv: + files: + - xbar_mbx_bind.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_mbx_bind.sv b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_mbx_bind.sv new file mode 100644 index 0000000000000..44e691a9c971b --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_mbx_bind.sv @@ -0,0 +1,72 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_mbx_bind module generated by `tlgen.py` tool for assertions +module xbar_mbx_bind; +`ifndef GATE_LEVEL + // Host interfaces + bind xbar_mbx tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx_i), + .d2h (tl_mbx_o) + ); + + // Device interfaces + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx0__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx0__soc_o), + .d2h (tl_mbx0__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx1__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx1__soc_o), + .d2h (tl_mbx1__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx2__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx2__soc_o), + .d2h (tl_mbx2__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx3__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx3__soc_o), + .d2h (tl_mbx3__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx4__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx4__soc_o), + .d2h (tl_mbx4__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx5__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx5__soc_o), + .d2h (tl_mbx5__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx6__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx6__soc_o), + .d2h (tl_mbx6__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx_pcie0__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx_pcie0__soc_o), + .d2h (tl_mbx_pcie0__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx_pcie1__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx_pcie1__soc_o), + .d2h (tl_mbx_pcie1__soc_i) + ); +`endif +endmodule diff --git a/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_mbx_sim.core b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_mbx_sim.core new file mode 100644 index 0000000000000..d9de9cda75f89 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_mbx_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_mbx_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_xbar_mbx_sim:0.1" +description: "XBAR DV sim target" +filesets: + files_dv: + depend: + - lowrisc:top_darjeeling:xbar_mbx + - lowrisc:dv:dv_utils + - lowrisc:dv:xbar_tb + - lowrisc:dv:top_darjeeling_xbar_mbx_bind + files: + - tb__xbar_connect.sv: {is_include_file: true} + - xbar_env_pkg__params.sv: {is_include_file: true} + file_type: systemVerilogSource + + +targets: + sim: &sim_target + toplevel: xbar_tb_top + filesets: + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_mbx_sim_cfg.hjson b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_mbx_sim_cfg.hjson new file mode 100644 index 0000000000000..81fe58b93a662 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_mbx/dv/autogen/xbar_mbx_sim_cfg.hjson @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_mbx_sim_cfg.hjson file generated by `tlgen.py` tool +{ + name: xbar_mbx + + // Top level dut name (sv module). + dut: xbar_mbx + + // The name of the chip this XBAR configuration is made for. + top_chip: top_darjeeling + + // Testplan hjson file. + testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson" + + // Add xbar_main specific exclusion files. + vcs_cov_excl_files: ["{proj_root}/hw/top_darjeeling/ip/{dut}/dv/autogen/xbar_cov_excl.el"] + + // replace common cover.cfg with a generated one, which includes xbar toggle exclusions + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/top_darjeeling/ip/{dut}/dv/autogen/xbar_cover.cfg" + } + ] + // Import additional common sim cfg files. + import_cfgs: [// xbar common sim cfg file + "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"] +} diff --git a/hw/top_darjeeling/ip/xbar_mbx/rtl/autogen/tl_mbx_pkg.sv b/hw/top_darjeeling/ip/xbar_mbx/rtl/autogen/tl_mbx_pkg.sv new file mode 100644 index 0000000000000..355fb61e2d550 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_mbx/rtl/autogen/tl_mbx_pkg.sv @@ -0,0 +1,48 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tl_mbx package generated by `tlgen.py` tool + +package tl_mbx_pkg; + + localparam logic [31:0] ADDR_SPACE_MBX0__SOC = 32'h 01465000; + localparam logic [31:0] ADDR_SPACE_MBX1__SOC = 32'h 01465100; + localparam logic [31:0] ADDR_SPACE_MBX2__SOC = 32'h 01465200; + localparam logic [31:0] ADDR_SPACE_MBX3__SOC = 32'h 01465300; + localparam logic [31:0] ADDR_SPACE_MBX4__SOC = 32'h 01465400; + localparam logic [31:0] ADDR_SPACE_MBX5__SOC = 32'h 01465500; + localparam logic [31:0] ADDR_SPACE_MBX6__SOC = 32'h 01465600; + localparam logic [31:0] ADDR_SPACE_MBX_PCIE0__SOC = 32'h 01460100; + localparam logic [31:0] ADDR_SPACE_MBX_PCIE1__SOC = 32'h 01460200; + + localparam logic [31:0] ADDR_MASK_MBX0__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX1__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX2__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX3__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX4__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX5__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX6__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX_PCIE0__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX_PCIE1__SOC = 32'h 0000001f; + + localparam int N_HOST = 1; + localparam int N_DEVICE = 9; + + typedef enum int { + TlMbx0Soc = 0, + TlMbx1Soc = 1, + TlMbx2Soc = 2, + TlMbx3Soc = 3, + TlMbx4Soc = 4, + TlMbx5Soc = 5, + TlMbx6Soc = 6, + TlMbxPcie0Soc = 7, + TlMbxPcie1Soc = 8 + } tl_device_e; + + typedef enum int { + TlMbx = 0 + } tl_host_e; + +endpackage diff --git a/hw/top_darjeeling/ip/xbar_mbx/rtl/autogen/xbar_mbx.sv b/hw/top_darjeeling/ip/xbar_mbx/rtl/autogen/xbar_mbx.sv new file mode 100644 index 0000000000000..dbfcdb4a0979f --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_mbx/rtl/autogen/xbar_mbx.sv @@ -0,0 +1,161 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_mbx module generated by `tlgen.py` tool +// all reset signals should be generated from one reset signal to not make any deadlock +// +// Interconnect +// mbx +// -> s1n_10 +// -> mbx0.soc +// -> mbx1.soc +// -> mbx2.soc +// -> mbx3.soc +// -> mbx4.soc +// -> mbx5.soc +// -> mbx6.soc +// -> mbx_pcie0.soc +// -> mbx_pcie1.soc + +module xbar_mbx ( + input clk_mbx_i, + input rst_mbx_ni, + + // Host interfaces + input tlul_pkg::tl_h2d_t tl_mbx_i, + output tlul_pkg::tl_d2h_t tl_mbx_o, + + // Device interfaces + output tlul_pkg::tl_h2d_t tl_mbx0__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx0__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx1__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx1__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx2__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx2__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx3__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx3__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx4__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx4__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx5__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx5__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx6__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx6__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx_pcie0__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx_pcie0__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx_pcie1__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx_pcie1__soc_i, + + input prim_mubi_pkg::mubi4_t scanmode_i +); + + import tlul_pkg::*; + import tl_mbx_pkg::*; + + // scanmode_i is currently not used, but provisioned for future use + // this assignment prevents lint warnings + logic unused_scanmode; + assign unused_scanmode = ^scanmode_i; + + tl_h2d_t tl_s1n_10_us_h2d ; + tl_d2h_t tl_s1n_10_us_d2h ; + + + tl_h2d_t tl_s1n_10_ds_h2d [9]; + tl_d2h_t tl_s1n_10_ds_d2h [9]; + + // Create steering signal + logic [3:0] dev_sel_s1n_10; + + + + assign tl_mbx0__soc_o = tl_s1n_10_ds_h2d[0]; + assign tl_s1n_10_ds_d2h[0] = tl_mbx0__soc_i; + + assign tl_mbx1__soc_o = tl_s1n_10_ds_h2d[1]; + assign tl_s1n_10_ds_d2h[1] = tl_mbx1__soc_i; + + assign tl_mbx2__soc_o = tl_s1n_10_ds_h2d[2]; + assign tl_s1n_10_ds_d2h[2] = tl_mbx2__soc_i; + + assign tl_mbx3__soc_o = tl_s1n_10_ds_h2d[3]; + assign tl_s1n_10_ds_d2h[3] = tl_mbx3__soc_i; + + assign tl_mbx4__soc_o = tl_s1n_10_ds_h2d[4]; + assign tl_s1n_10_ds_d2h[4] = tl_mbx4__soc_i; + + assign tl_mbx5__soc_o = tl_s1n_10_ds_h2d[5]; + assign tl_s1n_10_ds_d2h[5] = tl_mbx5__soc_i; + + assign tl_mbx6__soc_o = tl_s1n_10_ds_h2d[6]; + assign tl_s1n_10_ds_d2h[6] = tl_mbx6__soc_i; + + assign tl_mbx_pcie0__soc_o = tl_s1n_10_ds_h2d[7]; + assign tl_s1n_10_ds_d2h[7] = tl_mbx_pcie0__soc_i; + + assign tl_mbx_pcie1__soc_o = tl_s1n_10_ds_h2d[8]; + assign tl_s1n_10_ds_d2h[8] = tl_mbx_pcie1__soc_i; + + assign tl_s1n_10_us_h2d = tl_mbx_i; + assign tl_mbx_o = tl_s1n_10_us_d2h; + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_10 = 4'd9; + if ((tl_s1n_10_us_h2d.a_address & + ~(ADDR_MASK_MBX0__SOC)) == ADDR_SPACE_MBX0__SOC) begin + dev_sel_s1n_10 = 4'd0; + + end else if ((tl_s1n_10_us_h2d.a_address & + ~(ADDR_MASK_MBX1__SOC)) == ADDR_SPACE_MBX1__SOC) begin + dev_sel_s1n_10 = 4'd1; + + end else if ((tl_s1n_10_us_h2d.a_address & + ~(ADDR_MASK_MBX2__SOC)) == ADDR_SPACE_MBX2__SOC) begin + dev_sel_s1n_10 = 4'd2; + + end else if ((tl_s1n_10_us_h2d.a_address & + ~(ADDR_MASK_MBX3__SOC)) == ADDR_SPACE_MBX3__SOC) begin + dev_sel_s1n_10 = 4'd3; + + end else if ((tl_s1n_10_us_h2d.a_address & + ~(ADDR_MASK_MBX4__SOC)) == ADDR_SPACE_MBX4__SOC) begin + dev_sel_s1n_10 = 4'd4; + + end else if ((tl_s1n_10_us_h2d.a_address & + ~(ADDR_MASK_MBX5__SOC)) == ADDR_SPACE_MBX5__SOC) begin + dev_sel_s1n_10 = 4'd5; + + end else if ((tl_s1n_10_us_h2d.a_address & + ~(ADDR_MASK_MBX6__SOC)) == ADDR_SPACE_MBX6__SOC) begin + dev_sel_s1n_10 = 4'd6; + + end else if ((tl_s1n_10_us_h2d.a_address & + ~(ADDR_MASK_MBX_PCIE0__SOC)) == ADDR_SPACE_MBX_PCIE0__SOC) begin + dev_sel_s1n_10 = 4'd7; + + end else if ((tl_s1n_10_us_h2d.a_address & + ~(ADDR_MASK_MBX_PCIE1__SOC)) == ADDR_SPACE_MBX_PCIE1__SOC) begin + dev_sel_s1n_10 = 4'd8; +end + end + + + // Instantiation phase + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (36'h0), + .DRspDepth (36'h0), + .N (9) + ) u_s1n_10 ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .tl_h_i (tl_s1n_10_us_h2d), + .tl_h_o (tl_s1n_10_us_d2h), + .tl_d_o (tl_s1n_10_ds_h2d), + .tl_d_i (tl_s1n_10_ds_d2h), + .dev_select_i (dev_sel_s1n_10) + ); + +endmodule diff --git a/hw/top_darjeeling/ip/xbar_mbx/xbar_mbx.core b/hw/top_darjeeling/ip/xbar_mbx/xbar_mbx.core new file mode 100644 index 0000000000000..ea654951beff0 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_mbx/xbar_mbx.core @@ -0,0 +1,25 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_mbx core file generated by `tlgen.py` tool +name: "lowrisc:top_darjeeling:xbar_mbx:0.1" +description: "Generated RTL xbar_mbx" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:ip:lc_ctrl_pkg + files: + - rtl/autogen/tl_mbx_pkg.sv + - rtl/autogen/xbar_mbx.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: xbar_mbx diff --git a/hw/top_darjeeling/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_darjeeling/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson new file mode 100644 index 0000000000000..ef45d0976984c --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson @@ -0,0 +1,479 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson -o hw/top_darjeeling/ + +{ + name: peri + clock_srcs: + { + clk_peri_i: io_div4 + } + clock_group: infra + reset: rst_peri_ni + reset_connections: + { + rst_peri_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + connections: + { + main: + [ + uart0 + i2c0 + gpio + spi_host0 + spi_device + rv_timer + pwrmgr_aon + rstmgr_aon + clkmgr_aon + pinmux_aon + otp_ctrl.core + otp_ctrl.prim + lc_ctrl.regs + sensor_ctrl + alert_handler + ast + sram_ctrl_ret_aon.ram + sram_ctrl_ret_aon.regs + aon_timer_aon + ] + } + nodes: + [ + { + name: main + type: host + addr_space: hart + clock: clk_peri_i + reset: rst_peri_ni + xbar: true + pipeline: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: uart0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: uart + addr_range: + [ + { + base_addrs: + { + hart: 0x30010000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: i2c0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: i2c + addr_range: + [ + { + base_addrs: + { + hart: 0x30080000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: gpio + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: gpio + addr_range: + [ + { + base_addrs: + { + hart: 0x30000000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: spi_host0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: spi_host + addr_range: + [ + { + base_addrs: + { + hart: 0x30300000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: spi_device + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: spi_device + addr_range: + [ + { + base_addrs: + { + hart: 0x30310000 + } + size_byte: 0x2000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: rv_timer + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: rv_timer + addr_range: + [ + { + base_addrs: + { + hart: 0x30100000 + } + size_byte: 0x200 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: pwrmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: pwrmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30400000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: rstmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: rstmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30410000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: clkmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: clkmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30420000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: pinmux_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: pinmux + addr_range: + [ + { + base_addrs: + { + hart: 0x30460000 + } + size_byte: 0x800 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: otp_ctrl.core + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: otp_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30130000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: otp_ctrl.prim + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: otp_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30138000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: lc_ctrl.regs + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: lc_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30140000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sensor_ctrl + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: sensor_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30020000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: alert_handler + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: alert_handler + addr_range: + [ + { + base_addrs: + { + hart: 0x30150000 + } + size_byte: 0x800 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_ret_aon.regs + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30500000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_ret_aon.ram + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30600000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: aon_timer_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: aon_timer + addr_range: + [ + { + base_addrs: + { + hart: 0x30470000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: ast + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: ast + addr_range: + [ + { + base_addrs: + { + hart: 0x30480000 + } + size_byte: 0x400 + } + ] + xbar: false + stub: true + req_fifo_pass: true + } + ] + addr_spaces: + [ + hart + ] + clock: clk_peri_i + type: xbar +} diff --git a/hw/top_darjeeling/ip/xbar_peri/data/autogen/xbar_peri.hjson b/hw/top_darjeeling/ip/xbar_peri/data/autogen/xbar_peri.hjson new file mode 100644 index 0000000000000..9d6ea0a4d489a --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_peri/data/autogen/xbar_peri.hjson @@ -0,0 +1,137 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri comportable IP spec generated by `tlgen.py` tool +{ name: "xbar_peri" + clock_primary: "" + other_clock_list: [] + reset_primary: "" + other_reset_list: [] + //available_input_list: [] + + inter_signal_list: [ + // host + { struct: "tl" + type: "req_rsp" + name: "tl_main" + act: "rsp" + package: "tlul_pkg" + } + // device + { struct: "tl" + type: "req_rsp" + name: "tl_uart0" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_i2c0" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_gpio" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_spi_host0" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_spi_device" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rv_timer" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_pwrmgr_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rstmgr_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_clkmgr_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_pinmux_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_otp_ctrl__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_otp_ctrl__prim" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_lc_ctrl__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sensor_ctrl" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_alert_handler" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_ret_aon__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_ret_aon__ram" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_aon_timer_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_ast" + act: "req" + package: "tlul_pkg" + } + ] +} diff --git a/hw/top_darjeeling/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv new file mode 100644 index 0000000000000..d9b7b4c329b23 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv @@ -0,0 +1,38 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__xbar_connect generated by `tlgen.py` tool + +xbar_peri dut(); + +`DRIVE_CLK(clk_peri_i) + +initial force dut.clk_peri_i = clk_peri_i; + +// TODO, all resets tie together +initial force dut.rst_peri_ni = rst_n; + +// Host TileLink interface connections +`CONNECT_TL_HOST_IF(main, dut, clk_peri_i, rst_n) + +// Device TileLink interface connections +`CONNECT_TL_DEVICE_IF(uart0, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(i2c0, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(gpio, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(spi_host0, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(spi_device, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(rv_timer, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(pwrmgr_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(rstmgr_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(clkmgr_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(pinmux_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(otp_ctrl__core, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(otp_ctrl__prim, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(lc_ctrl__regs, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(sensor_ctrl, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(alert_handler, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_ret_aon__regs, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_ret_aon__ram, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(aon_timer_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(ast, dut, clk_peri_i, rst_n) diff --git a/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_cov_excl.el b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_cov_excl.el new file mode 100644 index 0000000000000..645d899b062dc --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_cov_excl.el @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cov_excl.el generated by `tlgen.py` tool + +ANNOTATION: "[NON_RTL]" +MODULE: uvm_pkg +Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion" +Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion" + +ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim" +MODULE: xbar_peri +Block 1 "0" "assign unused_scanmode = scanmode_i;" diff --git a/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_cover.cfg b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_cover.cfg new file mode 100644 index 0000000000000..cc5117562b87e --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_cover.cfg @@ -0,0 +1,97 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cover.cfg generated by `tlgen.py` tool + ++tree tb.dut +-module pins_if // DV construct. +-module clk_rst_if // DV construct. + +-assert legalAOpcodeErr_A +-assert sizeGTEMaskErr_A +-assert sizeMatchesMaskErr_A +-assert addrSizeAlignedErr_A + +// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after. +-node tb.dut tl_*.a_param +-node tb.dut tl_*.d_param +-node tb.dut tl_*.d_opcode[2:1] + +-moduletree prim_cdc_rand_delay // exclude DV construct. + +// [UNR] these device address bits are always 0 +-node tb.dut tl_uart0_o.a_address[15:6] +-node tb.dut tl_uart0_o.a_address[27:17] +-node tb.dut tl_uart0_o.a_address[31:30] +-node tb.dut tl_i2c0_o.a_address[18:7] +-node tb.dut tl_i2c0_o.a_address[27:20] +-node tb.dut tl_i2c0_o.a_address[31:30] +-node tb.dut tl_gpio_o.a_address[27:7] +-node tb.dut tl_gpio_o.a_address[31:30] +-node tb.dut tl_spi_host0_o.a_address[19:6] +-node tb.dut tl_spi_host0_o.a_address[27:22] +-node tb.dut tl_spi_host0_o.a_address[31:30] +-node tb.dut tl_spi_device_o.a_address[15:13] +-node tb.dut tl_spi_device_o.a_address[19:17] +-node tb.dut tl_spi_device_o.a_address[27:22] +-node tb.dut tl_spi_device_o.a_address[31:30] +-node tb.dut tl_rv_timer_o.a_address[19:9] +-node tb.dut tl_rv_timer_o.a_address[27:21] +-node tb.dut tl_rv_timer_o.a_address[31:30] +-node tb.dut tl_pwrmgr_aon_o.a_address[21:7] +-node tb.dut tl_pwrmgr_aon_o.a_address[27:23] +-node tb.dut tl_pwrmgr_aon_o.a_address[31:30] +-node tb.dut tl_rstmgr_aon_o.a_address[15:7] +-node tb.dut tl_rstmgr_aon_o.a_address[21:17] +-node tb.dut tl_rstmgr_aon_o.a_address[27:23] +-node tb.dut tl_rstmgr_aon_o.a_address[31:30] +-node tb.dut tl_clkmgr_aon_o.a_address[16:7] +-node tb.dut tl_clkmgr_aon_o.a_address[21:18] +-node tb.dut tl_clkmgr_aon_o.a_address[27:23] +-node tb.dut tl_clkmgr_aon_o.a_address[31:30] +-node tb.dut tl_pinmux_aon_o.a_address[16:11] +-node tb.dut tl_pinmux_aon_o.a_address[21:19] +-node tb.dut tl_pinmux_aon_o.a_address[27:23] +-node tb.dut tl_pinmux_aon_o.a_address[31:30] +-node tb.dut tl_otp_ctrl__core_o.a_address[15:12] +-node tb.dut tl_otp_ctrl__core_o.a_address[19:18] +-node tb.dut tl_otp_ctrl__core_o.a_address[27:21] +-node tb.dut tl_otp_ctrl__core_o.a_address[31:30] +-node tb.dut tl_otp_ctrl__prim_o.a_address[14:5] +-node tb.dut tl_otp_ctrl__prim_o.a_address[19:18] +-node tb.dut tl_otp_ctrl__prim_o.a_address[27:21] +-node tb.dut tl_otp_ctrl__prim_o.a_address[31:30] +-node tb.dut tl_lc_ctrl__regs_o.a_address[17:8] +-node tb.dut tl_lc_ctrl__regs_o.a_address[19:19] +-node tb.dut tl_lc_ctrl__regs_o.a_address[27:21] +-node tb.dut tl_lc_ctrl__regs_o.a_address[31:30] +-node tb.dut tl_sensor_ctrl_o.a_address[16:6] +-node tb.dut tl_sensor_ctrl_o.a_address[27:18] +-node tb.dut tl_sensor_ctrl_o.a_address[31:30] +-node tb.dut tl_alert_handler_o.a_address[15:11] +-node tb.dut tl_alert_handler_o.a_address[17:17] +-node tb.dut tl_alert_handler_o.a_address[19:19] +-node tb.dut tl_alert_handler_o.a_address[27:21] +-node tb.dut tl_alert_handler_o.a_address[31:30] +-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[19:6] +-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[21:21] +-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[27:23] +-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[31:30] +-node tb.dut tl_sram_ctrl_ret_aon__ram_o.a_address[20:12] +-node tb.dut tl_sram_ctrl_ret_aon__ram_o.a_address[27:23] +-node tb.dut tl_sram_ctrl_ret_aon__ram_o.a_address[31:30] +-node tb.dut tl_aon_timer_aon_o.a_address[15:6] +-node tb.dut tl_aon_timer_aon_o.a_address[21:19] +-node tb.dut tl_aon_timer_aon_o.a_address[27:23] +-node tb.dut tl_aon_timer_aon_o.a_address[31:30] +-node tb.dut tl_ast_o.a_address[18:10] +-node tb.dut tl_ast_o.a_address[21:20] +-node tb.dut tl_ast_o.a_address[27:23] +-node tb.dut tl_ast_o.a_address[31:30] + +begin tgl + -tree tb + +tree tb.dut 1 + -node tb.dut.scanmode_i +end diff --git a/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv new file mode 100644 index 0000000000000..463180bb6f06c --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv @@ -0,0 +1,90 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_env_pkg__params generated by `tlgen.py` tool + + +// List of Xbar device memory map +tl_device_t xbar_devices[$] = '{ + '{"uart0", '{ + '{32'h30010000, 32'h3001003f} + }}, + '{"i2c0", '{ + '{32'h30080000, 32'h3008007f} + }}, + '{"gpio", '{ + '{32'h30000000, 32'h3000007f} + }}, + '{"spi_host0", '{ + '{32'h30300000, 32'h3030003f} + }}, + '{"spi_device", '{ + '{32'h30310000, 32'h30311fff} + }}, + '{"rv_timer", '{ + '{32'h30100000, 32'h301001ff} + }}, + '{"pwrmgr_aon", '{ + '{32'h30400000, 32'h3040007f} + }}, + '{"rstmgr_aon", '{ + '{32'h30410000, 32'h3041007f} + }}, + '{"clkmgr_aon", '{ + '{32'h30420000, 32'h3042007f} + }}, + '{"pinmux_aon", '{ + '{32'h30460000, 32'h304607ff} + }}, + '{"otp_ctrl__core", '{ + '{32'h30130000, 32'h30130fff} + }}, + '{"otp_ctrl__prim", '{ + '{32'h30138000, 32'h3013801f} + }}, + '{"lc_ctrl__regs", '{ + '{32'h30140000, 32'h301400ff} + }}, + '{"sensor_ctrl", '{ + '{32'h30020000, 32'h3002003f} + }}, + '{"alert_handler", '{ + '{32'h30150000, 32'h301507ff} + }}, + '{"sram_ctrl_ret_aon__regs", '{ + '{32'h30500000, 32'h3050003f} + }}, + '{"sram_ctrl_ret_aon__ram", '{ + '{32'h30600000, 32'h30600fff} + }}, + '{"aon_timer_aon", '{ + '{32'h30470000, 32'h3047003f} + }}, + '{"ast", '{ + '{32'h30480000, 32'h304803ff} +}}}; + + // List of Xbar hosts +tl_host_t xbar_hosts[$] = '{ + '{"main", 0, '{ + "uart0", + "i2c0", + "gpio", + "spi_host0", + "spi_device", + "rv_timer", + "pwrmgr_aon", + "rstmgr_aon", + "clkmgr_aon", + "pinmux_aon", + "otp_ctrl__core", + "otp_ctrl__prim", + "lc_ctrl__regs", + "sensor_ctrl", + "alert_handler", + "ast", + "sram_ctrl_ret_aon__ram", + "sram_ctrl_ret_aon__regs", + "aon_timer_aon"}} +}; diff --git a/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_peri_bind.core b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_peri_bind.core new file mode 100644 index 0000000000000..1f22eabd9f5b3 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_peri_bind.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_peri_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_xbar_peri_bind:0.1" +description: "XBAR peri assertion bind" +filesets: + files_dv: + files: + - xbar_peri_bind.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv new file mode 100644 index 0000000000000..cd8bd5cb3baee --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv @@ -0,0 +1,132 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri_bind module generated by `tlgen.py` tool for assertions +module xbar_peri_bind; +`ifndef GATE_LEVEL + // Host interfaces + bind xbar_peri tlul_assert #(.EndpointType("Device")) tlul_assert_host_main ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_main_i), + .d2h (tl_main_o) + ); + + // Device interfaces + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart0 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_uart0_o), + .d2h (tl_uart0_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_i2c0 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_i2c0_o), + .d2h (tl_i2c0_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_gpio ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_gpio_o), + .d2h (tl_gpio_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_host0 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_spi_host0_o), + .d2h (tl_spi_host0_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_device ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_spi_device_o), + .d2h (tl_spi_device_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_timer ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_rv_timer_o), + .d2h (tl_rv_timer_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_pwrmgr_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_pwrmgr_aon_o), + .d2h (tl_pwrmgr_aon_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_rstmgr_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_rstmgr_aon_o), + .d2h (tl_rstmgr_aon_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_clkmgr_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_clkmgr_aon_o), + .d2h (tl_clkmgr_aon_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_pinmux_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_pinmux_aon_o), + .d2h (tl_pinmux_aon_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_otp_ctrl__core ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_otp_ctrl__core_o), + .d2h (tl_otp_ctrl__core_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_otp_ctrl__prim ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_otp_ctrl__prim_o), + .d2h (tl_otp_ctrl__prim_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_lc_ctrl__regs ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_lc_ctrl__regs_o), + .d2h (tl_lc_ctrl__regs_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sensor_ctrl ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_sensor_ctrl_o), + .d2h (tl_sensor_ctrl_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_alert_handler ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_alert_handler_o), + .d2h (tl_alert_handler_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_ret_aon__regs ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_sram_ctrl_ret_aon__regs_o), + .d2h (tl_sram_ctrl_ret_aon__regs_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_ret_aon__ram ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_sram_ctrl_ret_aon__ram_o), + .d2h (tl_sram_ctrl_ret_aon__ram_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_aon_timer_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_aon_timer_aon_o), + .d2h (tl_aon_timer_aon_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_ast ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_ast_o), + .d2h (tl_ast_i) + ); +`endif +endmodule diff --git a/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_peri_sim.core b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_peri_sim.core new file mode 100644 index 0000000000000..1a7850b36fa9f --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_peri_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_peri_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_xbar_peri_sim:0.1" +description: "XBAR DV sim target" +filesets: + files_dv: + depend: + - lowrisc:top_darjeeling:xbar_peri + - lowrisc:dv:dv_utils + - lowrisc:dv:xbar_tb + - lowrisc:dv:top_darjeeling_xbar_peri_bind + files: + - tb__xbar_connect.sv: {is_include_file: true} + - xbar_env_pkg__params.sv: {is_include_file: true} + file_type: systemVerilogSource + + +targets: + sim: &sim_target + toplevel: xbar_tb_top + filesets: + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson new file mode 100644 index 0000000000000..8af1f43617a04 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri_sim_cfg.hjson file generated by `tlgen.py` tool +{ + name: xbar_peri + + // Top level dut name (sv module). + dut: xbar_peri + + // The name of the chip this XBAR configuration is made for. + top_chip: top_darjeeling + + // Testplan hjson file. + testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson" + + // Add xbar_main specific exclusion files. + vcs_cov_excl_files: ["{proj_root}/hw/top_darjeeling/ip/{dut}/dv/autogen/xbar_cov_excl.el"] + + // replace common cover.cfg with a generated one, which includes xbar toggle exclusions + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/top_darjeeling/ip/{dut}/dv/autogen/xbar_cover.cfg" + } + ] + // Import additional common sim cfg files. + import_cfgs: [// xbar common sim cfg file + "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"] +} diff --git a/hw/top_darjeeling/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_darjeeling/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv new file mode 100644 index 0000000000000..d0f10527d89a1 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv @@ -0,0 +1,78 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tl_peri package generated by `tlgen.py` tool + +package tl_peri_pkg; + + localparam logic [31:0] ADDR_SPACE_UART0 = 32'h 30010000; + localparam logic [31:0] ADDR_SPACE_I2C0 = 32'h 30080000; + localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 30000000; + localparam logic [31:0] ADDR_SPACE_SPI_HOST0 = 32'h 30300000; + localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 30310000; + localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 30100000; + localparam logic [31:0] ADDR_SPACE_PWRMGR_AON = 32'h 30400000; + localparam logic [31:0] ADDR_SPACE_RSTMGR_AON = 32'h 30410000; + localparam logic [31:0] ADDR_SPACE_CLKMGR_AON = 32'h 30420000; + localparam logic [31:0] ADDR_SPACE_PINMUX_AON = 32'h 30460000; + localparam logic [31:0] ADDR_SPACE_OTP_CTRL__CORE = 32'h 30130000; + localparam logic [31:0] ADDR_SPACE_OTP_CTRL__PRIM = 32'h 30138000; + localparam logic [31:0] ADDR_SPACE_LC_CTRL__REGS = 32'h 30140000; + localparam logic [31:0] ADDR_SPACE_SENSOR_CTRL = 32'h 30020000; + localparam logic [31:0] ADDR_SPACE_ALERT_HANDLER = 32'h 30150000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_RET_AON__REGS = 32'h 30500000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_RET_AON__RAM = 32'h 30600000; + localparam logic [31:0] ADDR_SPACE_AON_TIMER_AON = 32'h 30470000; + localparam logic [31:0] ADDR_SPACE_AST = 32'h 30480000; + + localparam logic [31:0] ADDR_MASK_UART0 = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_I2C0 = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_GPIO = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_SPI_HOST0 = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_SPI_DEVICE = 32'h 00001fff; + localparam logic [31:0] ADDR_MASK_RV_TIMER = 32'h 000001ff; + localparam logic [31:0] ADDR_MASK_PWRMGR_AON = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_RSTMGR_AON = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_CLKMGR_AON = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_PINMUX_AON = 32'h 000007ff; + localparam logic [31:0] ADDR_MASK_OTP_CTRL__CORE = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_OTP_CTRL__PRIM = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_LC_CTRL__REGS = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_SENSOR_CTRL = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_ALERT_HANDLER = 32'h 000007ff; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_RET_AON__REGS = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_RET_AON__RAM = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_AON_TIMER_AON = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_AST = 32'h 000003ff; + + localparam int N_HOST = 1; + localparam int N_DEVICE = 19; + + typedef enum int { + TlUart0 = 0, + TlI2C0 = 1, + TlGpio = 2, + TlSpiHost0 = 3, + TlSpiDevice = 4, + TlRvTimer = 5, + TlPwrmgrAon = 6, + TlRstmgrAon = 7, + TlClkmgrAon = 8, + TlPinmuxAon = 9, + TlOtpCtrlCore = 10, + TlOtpCtrlPrim = 11, + TlLcCtrlRegs = 12, + TlSensorCtrl = 13, + TlAlertHandler = 14, + TlSramCtrlRetAonRegs = 15, + TlSramCtrlRetAonRam = 16, + TlAonTimerAon = 17, + TlAst = 18 + } tl_device_e; + + typedef enum int { + TlMain = 0 + } tl_host_e; + +endpackage diff --git a/hw/top_darjeeling/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_darjeeling/ip/xbar_peri/rtl/autogen/xbar_peri.sv new file mode 100644 index 0000000000000..507a4b34512dd --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_peri/rtl/autogen/xbar_peri.sv @@ -0,0 +1,261 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri module generated by `tlgen.py` tool +// all reset signals should be generated from one reset signal to not make any deadlock +// +// Interconnect +// main +// -> s1n_20 +// -> uart0 +// -> i2c0 +// -> gpio +// -> spi_host0 +// -> spi_device +// -> rv_timer +// -> pwrmgr_aon +// -> rstmgr_aon +// -> clkmgr_aon +// -> pinmux_aon +// -> otp_ctrl.core +// -> otp_ctrl.prim +// -> lc_ctrl.regs +// -> sensor_ctrl +// -> alert_handler +// -> ast +// -> sram_ctrl_ret_aon.ram +// -> sram_ctrl_ret_aon.regs +// -> aon_timer_aon + +module xbar_peri ( + input clk_peri_i, + input rst_peri_ni, + + // Host interfaces + input tlul_pkg::tl_h2d_t tl_main_i, + output tlul_pkg::tl_d2h_t tl_main_o, + + // Device interfaces + output tlul_pkg::tl_h2d_t tl_uart0_o, + input tlul_pkg::tl_d2h_t tl_uart0_i, + output tlul_pkg::tl_h2d_t tl_i2c0_o, + input tlul_pkg::tl_d2h_t tl_i2c0_i, + output tlul_pkg::tl_h2d_t tl_gpio_o, + input tlul_pkg::tl_d2h_t tl_gpio_i, + output tlul_pkg::tl_h2d_t tl_spi_host0_o, + input tlul_pkg::tl_d2h_t tl_spi_host0_i, + output tlul_pkg::tl_h2d_t tl_spi_device_o, + input tlul_pkg::tl_d2h_t tl_spi_device_i, + output tlul_pkg::tl_h2d_t tl_rv_timer_o, + input tlul_pkg::tl_d2h_t tl_rv_timer_i, + output tlul_pkg::tl_h2d_t tl_pwrmgr_aon_o, + input tlul_pkg::tl_d2h_t tl_pwrmgr_aon_i, + output tlul_pkg::tl_h2d_t tl_rstmgr_aon_o, + input tlul_pkg::tl_d2h_t tl_rstmgr_aon_i, + output tlul_pkg::tl_h2d_t tl_clkmgr_aon_o, + input tlul_pkg::tl_d2h_t tl_clkmgr_aon_i, + output tlul_pkg::tl_h2d_t tl_pinmux_aon_o, + input tlul_pkg::tl_d2h_t tl_pinmux_aon_i, + output tlul_pkg::tl_h2d_t tl_otp_ctrl__core_o, + input tlul_pkg::tl_d2h_t tl_otp_ctrl__core_i, + output tlul_pkg::tl_h2d_t tl_otp_ctrl__prim_o, + input tlul_pkg::tl_d2h_t tl_otp_ctrl__prim_i, + output tlul_pkg::tl_h2d_t tl_lc_ctrl__regs_o, + input tlul_pkg::tl_d2h_t tl_lc_ctrl__regs_i, + output tlul_pkg::tl_h2d_t tl_sensor_ctrl_o, + input tlul_pkg::tl_d2h_t tl_sensor_ctrl_i, + output tlul_pkg::tl_h2d_t tl_alert_handler_o, + input tlul_pkg::tl_d2h_t tl_alert_handler_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_ret_aon__regs_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_ret_aon__regs_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_ret_aon__ram_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_ret_aon__ram_i, + output tlul_pkg::tl_h2d_t tl_aon_timer_aon_o, + input tlul_pkg::tl_d2h_t tl_aon_timer_aon_i, + output tlul_pkg::tl_h2d_t tl_ast_o, + input tlul_pkg::tl_d2h_t tl_ast_i, + + input prim_mubi_pkg::mubi4_t scanmode_i +); + + import tlul_pkg::*; + import tl_peri_pkg::*; + + // scanmode_i is currently not used, but provisioned for future use + // this assignment prevents lint warnings + logic unused_scanmode; + assign unused_scanmode = ^scanmode_i; + + tl_h2d_t tl_s1n_20_us_h2d ; + tl_d2h_t tl_s1n_20_us_d2h ; + + + tl_h2d_t tl_s1n_20_ds_h2d [19]; + tl_d2h_t tl_s1n_20_ds_d2h [19]; + + // Create steering signal + logic [4:0] dev_sel_s1n_20; + + + + assign tl_uart0_o = tl_s1n_20_ds_h2d[0]; + assign tl_s1n_20_ds_d2h[0] = tl_uart0_i; + + assign tl_i2c0_o = tl_s1n_20_ds_h2d[1]; + assign tl_s1n_20_ds_d2h[1] = tl_i2c0_i; + + assign tl_gpio_o = tl_s1n_20_ds_h2d[2]; + assign tl_s1n_20_ds_d2h[2] = tl_gpio_i; + + assign tl_spi_host0_o = tl_s1n_20_ds_h2d[3]; + assign tl_s1n_20_ds_d2h[3] = tl_spi_host0_i; + + assign tl_spi_device_o = tl_s1n_20_ds_h2d[4]; + assign tl_s1n_20_ds_d2h[4] = tl_spi_device_i; + + assign tl_rv_timer_o = tl_s1n_20_ds_h2d[5]; + assign tl_s1n_20_ds_d2h[5] = tl_rv_timer_i; + + assign tl_pwrmgr_aon_o = tl_s1n_20_ds_h2d[6]; + assign tl_s1n_20_ds_d2h[6] = tl_pwrmgr_aon_i; + + assign tl_rstmgr_aon_o = tl_s1n_20_ds_h2d[7]; + assign tl_s1n_20_ds_d2h[7] = tl_rstmgr_aon_i; + + assign tl_clkmgr_aon_o = tl_s1n_20_ds_h2d[8]; + assign tl_s1n_20_ds_d2h[8] = tl_clkmgr_aon_i; + + assign tl_pinmux_aon_o = tl_s1n_20_ds_h2d[9]; + assign tl_s1n_20_ds_d2h[9] = tl_pinmux_aon_i; + + assign tl_otp_ctrl__core_o = tl_s1n_20_ds_h2d[10]; + assign tl_s1n_20_ds_d2h[10] = tl_otp_ctrl__core_i; + + assign tl_otp_ctrl__prim_o = tl_s1n_20_ds_h2d[11]; + assign tl_s1n_20_ds_d2h[11] = tl_otp_ctrl__prim_i; + + assign tl_lc_ctrl__regs_o = tl_s1n_20_ds_h2d[12]; + assign tl_s1n_20_ds_d2h[12] = tl_lc_ctrl__regs_i; + + assign tl_sensor_ctrl_o = tl_s1n_20_ds_h2d[13]; + assign tl_s1n_20_ds_d2h[13] = tl_sensor_ctrl_i; + + assign tl_alert_handler_o = tl_s1n_20_ds_h2d[14]; + assign tl_s1n_20_ds_d2h[14] = tl_alert_handler_i; + + assign tl_ast_o = tl_s1n_20_ds_h2d[15]; + assign tl_s1n_20_ds_d2h[15] = tl_ast_i; + + assign tl_sram_ctrl_ret_aon__ram_o = tl_s1n_20_ds_h2d[16]; + assign tl_s1n_20_ds_d2h[16] = tl_sram_ctrl_ret_aon__ram_i; + + assign tl_sram_ctrl_ret_aon__regs_o = tl_s1n_20_ds_h2d[17]; + assign tl_s1n_20_ds_d2h[17] = tl_sram_ctrl_ret_aon__regs_i; + + assign tl_aon_timer_aon_o = tl_s1n_20_ds_h2d[18]; + assign tl_s1n_20_ds_d2h[18] = tl_aon_timer_aon_i; + + assign tl_s1n_20_us_h2d = tl_main_i; + assign tl_main_o = tl_s1n_20_us_d2h; + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_20 = 5'd19; + if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin + dev_sel_s1n_20 = 5'd0; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin + dev_sel_s1n_20 = 5'd1; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin + dev_sel_s1n_20 = 5'd2; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin + dev_sel_s1n_20 = 5'd3; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin + dev_sel_s1n_20 = 5'd4; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin + dev_sel_s1n_20 = 5'd5; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_PWRMGR_AON)) == ADDR_SPACE_PWRMGR_AON) begin + dev_sel_s1n_20 = 5'd6; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_RSTMGR_AON)) == ADDR_SPACE_RSTMGR_AON) begin + dev_sel_s1n_20 = 5'd7; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_CLKMGR_AON)) == ADDR_SPACE_CLKMGR_AON) begin + dev_sel_s1n_20 = 5'd8; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_PINMUX_AON)) == ADDR_SPACE_PINMUX_AON) begin + dev_sel_s1n_20 = 5'd9; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_OTP_CTRL__CORE)) == ADDR_SPACE_OTP_CTRL__CORE) begin + dev_sel_s1n_20 = 5'd10; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_OTP_CTRL__PRIM)) == ADDR_SPACE_OTP_CTRL__PRIM) begin + dev_sel_s1n_20 = 5'd11; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_LC_CTRL__REGS)) == ADDR_SPACE_LC_CTRL__REGS) begin + dev_sel_s1n_20 = 5'd12; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_SENSOR_CTRL)) == ADDR_SPACE_SENSOR_CTRL) begin + dev_sel_s1n_20 = 5'd13; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin + dev_sel_s1n_20 = 5'd14; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_AST)) == ADDR_SPACE_AST) begin + dev_sel_s1n_20 = 5'd15; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_RET_AON__RAM)) == ADDR_SPACE_SRAM_CTRL_RET_AON__RAM) begin + dev_sel_s1n_20 = 5'd16; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_RET_AON__REGS)) == ADDR_SPACE_SRAM_CTRL_RET_AON__REGS) begin + dev_sel_s1n_20 = 5'd17; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_AON_TIMER_AON)) == ADDR_SPACE_AON_TIMER_AON) begin + dev_sel_s1n_20 = 5'd18; +end + end + + + // Instantiation phase + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (76'h0), + .DRspDepth (76'h0), + .N (19) + ) u_s1n_20 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .tl_h_i (tl_s1n_20_us_h2d), + .tl_h_o (tl_s1n_20_us_d2h), + .tl_d_o (tl_s1n_20_ds_h2d), + .tl_d_i (tl_s1n_20_ds_d2h), + .dev_select_i (dev_sel_s1n_20) + ); + +endmodule diff --git a/hw/top_darjeeling/ip/xbar_peri/xbar_peri.core b/hw/top_darjeeling/ip/xbar_peri/xbar_peri.core new file mode 100644 index 0000000000000..8480e2b60ce08 --- /dev/null +++ b/hw/top_darjeeling/ip/xbar_peri/xbar_peri.core @@ -0,0 +1,25 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_peri core file generated by `tlgen.py` tool +name: "lowrisc:top_darjeeling:xbar_peri:0.1" +description: "Generated RTL xbar_peri" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:ip:lc_ctrl_pkg + files: + - rtl/autogen/tl_peri_pkg.sv + - rtl/autogen/xbar_peri.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: xbar_peri diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/README.md b/hw/top_darjeeling/ip_autogen/alert_handler/README.md new file mode 100644 index 0000000000000..a1871a013dc65 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/README.md @@ -0,0 +1,73 @@ +# Alert Handler Technical Specification + +[`alert_handler`](https://reports.opentitan.org/hw/top_earlgrey/ip_autogen/alert_handler/dv/latest/report.html): +![](https://dashboards.lowrisc.org/badges/dv/alert_handler/test.svg) +![](https://dashboards.lowrisc.org/badges/dv/alert_handler/passing.svg) +![](https://dashboards.lowrisc.org/badges/dv/alert_handler/functional.svg) +![](https://dashboards.lowrisc.org/badges/dv/alert_handler/code.svg) + +# Overview + +This document specifies the functionality of the alert handler mechanism. +The alert handler is a module that is a peripheral on the chip interconnect bus, and thus follows the [Comportability Specification](../../../../doc/contributing/hw/comportability/README.md). +It gathers alerts - defined as interrupt-type signals from other peripherals that are designated as potential security threats - throughout the design, and converts them to interrupts that the processor can handle. +If the processor does not handle them, the alert handler mechanism provides hardware responses to handle the threat. + + +## Features + +- Differentially-signaled, asynchronous alert inputs from `NAlerts` peripheral sources, where `NAlerts` is a function of the requirements of the peripherals. + +- Ping testing of alert sources: + - responder module requests periodic alert response from each source to ensure proper wiring. + - reset-asserted and clock-gated information is used to temporarily pause the ping mechanism on alert channels that are in a low-power state. + +- Register locking on all configuration registers. + - Once locked, can not be modified by software until next system reset. + +- Register-based assignment of alert to alert-class. + - Four classes, can be individually disabled. + - Each class generates one interrupt. + - Disambiguation history for software to determine which alert caused the class interrupt. + - Each class has configurable response time for escalation. + - Disable allows for ignoring alerts, should only be used in cases when alerts are faulty. + Undesirable access is enforced by locking the register state after initial configuration. + +- Register-based escalation controls. + - Number of alerts in class before escalation. + - Timeout for unhandled alert IRQs can also trigger escalation. + - Configurable escalation enables for 4 escalation signals. + - Could map to NMI, wipe secrets signal, lower privilege, chip reset, etc. + - Escalation signals differentially-signaled with heartbeat, will trigger response if differential or heartbeat failure at destination. + - Configurable time in cycles between each escalation level. + +- Two locally sourced hardware alerts. + - Differential signaling from a source has failed. + - Ping response from a source has failed. + + +## Description + +The alert handler module manages incoming alerts from throughout the system, classifies them, sends interrupts, and escalates interrupts to hardware responses if the processor does not respond to any interrupts. +The intention is for this module to be a stand-in for security responses in the case where the processor can not handle the security alerts. + +It is first notable that all security alerts are rare events. +Module and top level designers should only designate events as alerts if they are expected to never happen, and if they have potential security consequences. +Examples are parity errors (which might indicate an attack), illegal actions on cryptography or security modules, physical sensors of environmental modification (e.g. voltage, temperature), etc. +Alerts will be routed through this module and initially converted to interrupts for the processor to handle. +The expectation is that the secure operating system has a protocol for handling any such alert interrupt in software. +The operating system should respond, then clear the interrupt. +Since these are possible security attacks, the response is not always obvious, but the response is beyond the scope of this document. + +This module is designed to help the full chip respond to security threats in the case where the processor is not trusted: either it has been attacked, or is not responding. +It does this by escalating alerts beyond a processor interrupt. +It provides four such escalation signals that can be routed to chip functions for attack responses. +This could include such functions as wiping secret chip material, power down, reset, etc. +It is beyond the scope of this document to specify what those escalation responses are at the chip level. + +To ease software management of alerts, classification is provided whereby each alert can be classified into one of four classes. +How the classification is done by software is beyond the scope of this document, but it is suggested that alerts of a similar profile (risk of occurring, level of security concern, frequency of false trigger, etc) are classed together. +For each class a counter of alerts is kept, clearable by software. +If that counter exceeds a programmable maximum value, then the escalation protocol for that class begins. + +The details for alert signaling, classification, and escalation are all given in the Theory of Operations section. diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler.core b/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler.core new file mode 100644 index 0000000000000..0efc94e28679a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler.core @@ -0,0 +1,38 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_alert_handler:0.1 +description: "Alert Handler" +virtual: + - lowrisc:ip_interfaces:alert_handler + +filesets: + files_rtl: + depend: + - lowrisc:ip:alert_handler_component + - lowrisc:opentitan:top_darjeeling_alert_handler_reg:0.1 + file_type: systemVerilogSource + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: alert_handler + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler_component.core b/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler_component.core new file mode 100644 index 0000000000000..b4ed8c072bd18 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler_component.core @@ -0,0 +1,63 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:ip:alert_handler_component:0.1" +description: "Alert Handler component without the CSRs" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:all + - lowrisc:prim:esc + - lowrisc:prim:double_lfsr + - lowrisc:prim:count + - lowrisc:prim:edn_req + - lowrisc:prim:buf + - lowrisc:prim:mubi + - lowrisc:prim:sparse_fsm + - lowrisc:ip_interfaces:alert_handler_reg + files: + - rtl/alert_pkg.sv + - rtl/alert_handler_reg_wrap.sv + - rtl/alert_handler_lpg_ctrl.sv + - rtl/alert_handler_class.sv + - rtl/alert_handler_ping_timer.sv + - rtl/alert_handler_esc_timer.sv + - rtl/alert_handler_accu.sv + - rtl/alert_handler.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/alert_handler.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/alert_handler.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler_reg.core b/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler_reg.core new file mode 100644 index 0000000000000..88d8911a41be6 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/alert_handler_reg.core @@ -0,0 +1,26 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_alert_handler_reg:0.1 +description: "Auto-generated alert handler register sources" +virtual: + - "lowrisc:ip_interfaces:alert_handler_reg" + +filesets: + files_rtl: + depend: + - lowrisc:tlul:headers + - lowrisc:prim:subreg + - lowrisc:ip:tlul + - lowrisc:prim:subreg + files: + - rtl/alert_handler_reg_pkg.sv + - rtl/alert_handler_reg_top.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_rtl diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler.hjson new file mode 100644 index 0000000000000..74923eef5fd95 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler.hjson @@ -0,0 +1,2039 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +# ALERT_HANDLER register template + +{ + name: "alert_handler", + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "32", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_alert_handler" + version: "1.0.1", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + notes: "Use both FPV and DV to perform block level verification.", + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {clock: "clk_edn_i", reset: "rst_edn_ni"} + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device", hier_path: "u_reg_wrap.u_reg" } + ], + regwidth: "32", + param_list: [ + // Random netlist constants + { name: "RndCnstLfsrSeed", + desc: "Compile-time random bits for initial LFSR seed", + type: "alert_pkg::lfsr_seed_t" + randcount: "32", + randtype: "data", // randomize randcount databits + } + { name: "RndCnstLfsrPerm", + desc: "Compile-time random permutation for LFSR output", + type: "alert_pkg::lfsr_perm_t" + randcount: "32", + randtype: "perm", // random permutation for randcount elements + } + // Normal parameters + { name: "NAlerts", + desc: "Number of alert channels.", + type: "int", + default: "99", + local: "true" + }, + { name: "NLpg", + desc: "Number of LPGs.", + type: "int", + default: "19", + local: "true" + }, + { name: "NLpgWidth", + desc: "Width of LPG ID.", + type: "int", + default: "5", + local: "true" + }, + { name: "LpgMap", + desc: ''' + Defines a mapping from alerts to LPGs. + ''' + type: "logic [NAlerts-1:0][NLpgWidth-1:0]", + default: ''' + { + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd14, + 5'd14, + 5'd14, + 5'd14, + 5'd14, + 5'd14, + 5'd14, + 5'd14, + 5'd18, + 5'd18, + 5'd17, + 5'd17, + 5'd16, + 5'd15, + 5'd15, + 5'd14, + 5'd13, + 5'd12, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd10, + 5'd10, + 5'd8, + 5'd7, + 5'd7, + 5'd7, + 5'd7, + 5'd7, + 5'd6, + 5'd5, + 5'd4, + 5'd4, + 5'd4, + 5'd4, + 5'd4, + 5'd4, + 5'd4, + 5'd4, + 5'd3, + 5'd2, + 5'd1, + 5'd0, + 5'd0 + } + ''', + local: "true" + }, + { name: "EscCntDw", + desc: "Width of the escalation timer.", + type: "int", + default: "32", + local: "true" + }, + { name: "AccuCntDw", + desc: "Width of the accumulation counter.", + type: "int", + default: "16", + local: "true" + }, + { name: "AsyncOn", + desc: ''' + Each bit of this parameter corresponds to an escalation channel and + defines whether the protocol is synchronous (0) or asynchronous (1). + ''' + type: "logic [NAlerts-1:0]", + default: ''' + { + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1 + } + ''' + local: "true" + }, + { name: "N_CLASSES", + desc: "Number of classes", + type: "int", + default: "4", + local: "true" + }, + { name: "N_ESC_SEV", + desc: "Number of escalation severities", + type: "int", + default: "4", + local: "true" + }, + { name: "N_PHASES", + desc: "Number of escalation phases", + type: "int", + default: "4", + local: "true" + }, + { name: "N_LOC_ALERT", + desc: "Number of local alerts", + type: "int", + default: "7", + local: "true" + }, + { name: "PING_CNT_DW", + desc: "Width of ping counter", + type: "int", + default: "16", + local: "true" + }, + { name: "PHASE_DW", + desc: "Width of phase ID", + type: "int", + default: "2", + local: "true" + }, + { name: "CLASS_DW", + desc: "Width of class ID", + type: "int", + default: "2", + local: "true" + }, + { name: "LOCAL_ALERT_ID_ALERT_PINGFAIL", + desc: "Local alert ID for alert ping failure.", + type: "int", + default: "0", + local: "true" + }, + { name: "LOCAL_ALERT_ID_ESC_PINGFAIL", + desc: "Local alert ID for escalation ping failure.", + type: "int", + default: "1", + local: "true" + }, + { name: "LOCAL_ALERT_ID_ALERT_INTEGFAIL", + desc: "Local alert ID for alert integrity failure.", + type: "int", + default: "2", + local: "true" + }, + { name: "LOCAL_ALERT_ID_ESC_INTEGFAIL", + desc: "Local alert ID for escalation integrity failure.", + type: "int", + default: "3", + local: "true" + }, + { name: "LOCAL_ALERT_ID_BUS_INTEGFAIL", + desc: "Local alert ID for bus integrity failure.", + type: "int", + default: "4", + local: "true" + }, + { name: "LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR", + desc: "Local alert ID for shadow register update error.", + type: "int", + default: "5", + local: "true" + }, + { name: "LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR", + desc: "Local alert ID for shadow register storage error.", + type: "int", + default: "6", + local: "true" + }, + { name: "LOCAL_ALERT_ID_LAST", + desc: "Last local alert ID.", + type: "int", + default: "6", + local: "true" + }, + ], + + inter_signal_list: [ + { struct: "alert_crashdump", + type: "uni", + name: "crashdump", + act: "req", + package: "alert_pkg" + }, + { struct: "edn" + type: "req_rsp" + name: "edn" + act: "req" + width: "1" + package: "edn_pkg" + }, + { struct: "esc_rx" + type: "uni" + name: "esc_rx" + act: "rcv" + width: "4", // N_ESC_SEV + package: "prim_esc_pkg" + }, + { struct: "esc_tx" + type: "uni" + name: "esc_tx" + act: "req" + width: "4", // N_ESC_SEV + package: "prim_esc_pkg" + }, + ] + + features: [ + { name: "ALERT_HANDLER.ALERT.OBSERVE", + desc: ''' + All incoming alerts can be observed by the alert handler. + ''' + } + { name: "ALERT_HANDLER.ALERT.INTERRUPT", + desc: ''' + All alert classes can raise an interrupt when an alert that is + allocated to them is raised. + ''' + } + { name: "ALERT_HANDLER.ALERT.ESCALATE", + desc: ''' + All incoming alerts can trigger the alert escalation mechanisms + of the classes they are allocated to + ''' + } + { + name: "ALERT_HANDLER.PING_TIMER", + desc: ''' + The alert handler periodically pings all alert receivers and + will raise an alert if the ping isn't responded to in good time + ''' + } + { name: "ALERT_HANDLER.ESCALATION.COUNT", + desc: ''' + An escalation can be triggered when the number of alerts seen in + a particular class exceeds a software programmable threshold + ''' + } + { name: "ALERT_HANDLER.ESCALATION.TIMEOUT", + desc: ''' + An escalation can be triggered when an interrupt from a class + isn't acknowledged after a software programmable timeout + ''' + } + { name: "ALERT_HANDLER.ESCALATION.PHASES", + desc: ''' + Each alert class can trigger the same 4 escalation phases. A + programmable timer specifies the delay between each of the + escalation phases. The actions taken on each of the escalation + signals are specific to the top-level integration. + ''' + } + { + name: "ALERT_HANDLER.CRASH_DUMP", + desc: ''' + A crashdump with the state of CSRs and alert handler state bits + is made available. When a programmable latching trigger condition + is met the crashdump is held constant at its value on that + trigger condition so it can be recorded and made available for + later analysis + ''' + } + ] + + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "CONFIG.SHADOW", + desc: "Important CSRs are shadowed." + } + { name: "PING_TIMER.CONFIG.REGWEN", + desc: "The ping timer configuration registers are REGWEN protected." + } + { name: "ALERT.CONFIG.REGWEN", + desc: "The individual alert enables are REGWEN protected." + } + { name: "ALERT_LOC.CONFIG.REGWEN", + desc: "The individual local alert enables are REGWEN protected." + } + { name: "CLASS.CONFIG.REGWEN", + desc: "The class configuration registers are REGWEN protected." + } + { name: "ALERT.INTERSIG.DIFF", + desc: "Differentially encoded alert channels." + } + { name: "LPG.INTERSIG.MUBI", + desc: "LPG signals are encoded with MUBI types." + } + { name: "ESC.INTERSIG.DIFF", + desc: "Differentially encoded escalation channels." + } + { name: "ALERT_RX.INTERSIG.BKGN_CHK", + desc: "Periodic background checks on alert channels (ping mechanism)." + } + { name: "ESC_TX.INTERSIG.BKGN_CHK", + desc: "Periodic background checks on escalation channels (ping mechanism)." + } + { name: "ESC_RX.INTERSIG.BKGN_CHK", + desc: "Escalation receivers can detect absence of periodic ping requests." + } + { name: "ESC_TIMER.FSM.SPARSE", + desc: "Escalation timer FSMs are sparsely encoded." + } + { name: "PING_TIMER.FSM.SPARSE", + desc: "Ping timer FSM is sparsely encoded." + } + { name: "ESC_TIMER.FSM.LOCAL_ESC", + desc: "Escalation timer FSMs move into an invalid state upon local escalation." + } + { name: "PING_TIMER.FSM.LOCAL_ESC", + desc: "Ping timer FSM moves into an invalid state upon local escalation." + } + { name: "ESC_TIMER.FSM.GLOBAL_ESC", + desc: ''' + The escalation timer FSMs are the root of global escalation, + hence if any of them moves into an invalid state by virtue of + ESC_TIMER.FSM.LOCAL_ESC, this will trigger all escalation actions + and thereby global escalation as well. + ''' + } + { name: "ACCU.CTR.REDUN", + desc: "Accumulator counters employ a cross-counter implementation." + } + { name: "ESC_TIMER.CTR.REDUN", + desc: "Escalation timer counters employ a duplicated counter implementation." + } + { name: "PING_TIMER.CTR.REDUN", + desc: "Ping timer counters employ a duplicated counter implementation." + } + { name: "PING_TIMER.LFSR.REDUN", + desc: "Ping timer LFSR is redundant." + } + ] + +# interrupt registers for the classes + interrupt_list: [ + { name: "classa", + desc: ''' + Interrupt state bit of Class A. Set by HW in case an alert within this class triggered. Defaults true, write one to clear. + ''', + }, + { name: "classb", + desc: ''' + Interrupt state bit of Class B. Set by HW in case an alert within this class triggered. Defaults true, write one to clear. + ''', + }, + { name: "classc", + desc: ''' + Interrupt state bit of Class C. Set by HW in case an alert within this class triggered. Defaults true, write one to clear. + ''', + }, + { name: "classd", + desc: ''' + Interrupt state bit of Class D. Set by HW in case an alert within this class triggered. Defaults true, write one to clear. + ''', + }, + ], + + registers: [ +# register lock for ping timeout counter + { name: "PING_TIMER_REGWEN", + desc: ''' + Register write enable for !!PING_TIMEOUT_CYC_SHADOWED and !!PING_TIMER_EN_SHADOWED. + ''', + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { + bits: "0", + desc: ''' + When true, the !!PING_TIMEOUT_CYC_SHADOWED and !!PING_TIMER_EN_SHADOWED registers can be modified. + When false, they become read-only. Defaults true, write one to clear. + This should be cleared once the alert handler has been configured and the ping + timer mechanism has been kicked off. + ''' + resval: 1, + }, + ] + }, + { name: "PING_TIMEOUT_CYC_SHADOWED", + desc: ''' + Ping timeout cycle count. + ''' + shadowed: "true", + swaccess: "rw", + hwaccess: "hro", + regwen: "PING_TIMER_REGWEN", + fields: [ + { + bits: "PING_CNT_DW-1:0", + resval: 256, + desc: ''' + Timeout value in cycles. + If an alert receiver or an escalation sender does not respond to a ping within this timeout window, a pingfail alert will be raised. + It is recommended to set this value to the equivalent of 256 cycles of the slowest alert sender clock domain in the system (or greater). + ''' + } + ] + } + { name: "PING_TIMER_EN_SHADOWED", + desc: ''' + Ping timer enable. + ''' + shadowed: "true", + swaccess: "rw1s", + hwaccess: "hro", + regwen: "PING_TIMER_REGWEN", + fields: [ + { + bits: "0", + resval: 0, + desc: ''' + Setting this to 1 enables the ping timer mechanism. + This bit cannot be cleared to 0 once it has been set to 1. + + Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. + ''' + } + ] + } +# all alerts + { multireg: { name: "ALERT_REGWEN", + desc: "Register write enable for alert enable bits.", + count: "NAlerts", + compact: "false", + swaccess: "rw0c", + hwaccess: "hro", + hwqe: "false", + cname: "alert", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Alert configuration write enable bit. + If this is cleared to 0, the corresponding !!ALERT_EN_SHADOWED + and !!ALERT_CLASS_SHADOWED bits are not writable anymore. + + Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "ALERT_EN_SHADOWED", + desc: '''Enable register for alerts. + ''', + count: "NAlerts", + shadowed: "true", + swaccess: "rw", + hwaccess: "hro", + regwen: "ALERT_REGWEN", + regwen_multi: "true", + cname: "alert", + tags: [// Enable `alert_en` might cause top-level escalators to trigger + // unexpected reset + "excl:CsrAllTests:CsrExclWrite"] + fields: [ + { bits: "0", + name: "EN_A", + resval: 0 + desc: ''' + Alert enable bit. + + Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. + ''' + } + ] + } + }, + { multireg: { name: "ALERT_CLASS_SHADOWED", + desc: '''Class assignment of alerts. + ''', + count: "NAlerts", + shadowed: "true", + swaccess: "rw", + hwaccess: "hro", + regwen: "ALERT_REGWEN", + regwen_multi: "true", + cname: "alert", + fields: [ + { + bits: "CLASS_DW-1:0", + name: "CLASS_A", + resval: 0 + desc: "Classification ", + enum: [ + { value: "0", name: "ClassA", desc: "" }, + { value: "1", name: "ClassB", desc: "" }, + { value: "2", name: "ClassC", desc: "" }, + { value: "3", name: "ClassD", desc: "" }, + ] + } + ] + } + }, + { multireg: { + name: "ALERT_CAUSE", + desc: "Alert Cause Register", + count: "NAlerts", + compact: "false", + cname: "ALERT", + swaccess: "rw1c", + hwaccess: "hrw", + fields: [ + { bits: "0", name: "A", desc: "Cause bit ", resval: 0} + ], + } + }, +# local alerts + { multireg: { name: "LOC_ALERT_REGWEN", + desc: "Register write enable for alert enable bits.", + count: "N_LOC_ALERT", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "LOC_ALERT", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Alert configuration write enable bit. + If this is cleared to 0, the corresponding !!LOC_ALERT_EN_SHADOWED + and !!LOC_ALERT_CLASS_SHADOWED bits are not writable anymore. + + Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "LOC_ALERT_EN_SHADOWED", + desc: + ''' + Enable register for the local alerts + "alert pingfail" (0), "escalation pingfail" (1), + "alert integfail" (2), "escalation integfail" (3), + "bus integrity failure" (4), "shadow reg update error" (5) + and "shadow reg storage error" (6). + ''', + count: "N_LOC_ALERT", + shadowed: "true", + swaccess: "rw", + hwaccess: "hro", + regwen: "LOC_ALERT_REGWEN", + regwen_multi: "true", + cname: "LOC_ALERT", + fields: [ + { bits: "0", + name: "EN_LA", + resval: 0 + desc: ''' + Alert enable bit. + + Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. + ''' + } + ] + } + }, + { multireg: { name: "LOC_ALERT_CLASS_SHADOWED", + desc: ''' + Class assignment of the local alerts + "alert pingfail" (0), "escalation pingfail" (1), + "alert integfail" (2), "escalation integfail" (3), + "bus integrity failure" (4), "shadow reg update error" (5) + and "shadow reg storage error" (6). + ''', + count: "N_LOC_ALERT", + shadowed: "true", + swaccess: "rw", + hwaccess: "hro", + regwen: "LOC_ALERT_REGWEN", + regwen_multi: "true", + cname: "LOC_ALERT", + fields: [ + { + bits: "CLASS_DW-1:0", + name: "CLASS_LA", + resval: 0 + desc: "Classification ", + enum: [ + { value: "0", name: "ClassA", desc: "" }, + { value: "1", name: "ClassB", desc: "" }, + { value: "2", name: "ClassC", desc: "" }, + { value: "3", name: "ClassD", desc: "" }, + ] + } + ] + } + }, + { multireg: { + name: "LOC_ALERT_CAUSE", + desc: '''Alert Cause Register for the local alerts + "alert pingfail" (0), "escalation pingfail" (1), + "alert integfail" (2), "escalation integfail" (3), + "bus integrity failure" (4), "shadow reg update error" (5) + and "shadow reg storage error" (6). + ''', + count: "N_LOC_ALERT", + compact: "false", + cname: "LOC_ALERT", + swaccess: "rw1c", + hwaccess: "hrw", + tags: [// Top level CSR automation test, CPU clock is disabled, so escalation response will + // not send back to alert handler. This will set loc_alert_cause and could not predict + // automatically. + "excl:CsrNonInitTests:CsrExclCheck"], + fields: [ + { bits: "0", name: "LA", desc: "Cause bit ", resval: 0} + ] + } + }, +# classes + + { name: "CLASSA_REGWEN", + desc: ''' + Lock bit for Class A configuration. + ''' + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + Class configuration enable bit. + If this is cleared to 0, the corresponding class configuration + registers cannot be written anymore. + ''', + resval: 1, + } + ] + }, + { name: "CLASSA_CTRL_SHADOWED", + desc: "Escalation control register for alert Class A. Can not be modified if !!CLASSA_REGWEN is false." + swaccess: "rw", + hwaccess: "hro", + regwen: "CLASSA_REGWEN", + shadowed: "true", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Enable escalation mechanisms (accumulation and + interrupt timeout) for Class A. Note that interrupts can fire + regardless of whether the escalation mechanisms are enabled for + this class or not. + ''', + } + { bits: "1", + name: "LOCK", + desc: ''' + Enable automatic locking of escalation counter for class A. + If true, there is no way to stop the escalation protocol for class A + once it has been triggered. + ''' + } + { bits: "2", + name: "EN_E0", + resval: 1, + desc: "Enable escalation signal 0 for Class A", + } + { bits: "3", + name: "EN_E1", + resval: 1, + desc: "Enable escalation signal 1 for Class A", + } + { bits: "4", + name: "EN_E2", + resval: 1, + desc: "Enable escalation signal 2 for Class A", + } + { bits: "5", + name: "EN_E3", + resval: 1, + desc: "Enable escalation signal 3 for Class A", + } + { bits: "7:6", + name: "MAP_E0", + resval: 0, + desc: "Determines in which escalation phase escalation signal 0 shall be asserted.", + } + { bits: "9:8", + name: "MAP_E1", + resval: 1, + desc: "Determines in which escalation phase escalation signal 1 shall be asserted.", + } + { bits: "11:10", + name: "MAP_E2", + resval: 2, + desc: "Determines in which escalation phase escalation signal 2 shall be asserted.", + } + { bits: "13:12", + name: "MAP_E3", + resval: 3, + desc: "Determines in which escalation phase escalation signal 3 shall be asserted.", + } + ] + }, + { name: "CLASSA_CLR_REGWEN", + desc: ''' + Clear enable for escalation protocol of Class A alerts. + ''' + swaccess: "rw0c", + hwaccess: "hwo", + fields: [ + { bits: "0", + desc: '''Register defaults to true, can only be cleared. This register is set + to false by the hardware if the escalation protocol has been triggered and the bit + !!CLASSA_CTRL_SHADOWED.LOCK is true. + ''', + resval: 1, + } + ], + tags: [// The value of this register is set to false only by hardware, under the condition + // that escalation is triggered and the corresponding lock bit is true + // Cannot not be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSA_CLR_SHADOWED", + desc: ''' + Clear for escalation protocol of Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + hwqe: "true", + shadowed: "true", + regwen: "CLASSA_CLR_REGWEN", + fields: [ + { bits: "0", + desc: '''Writing 1 to this register clears the accumulator and aborts escalation + (if it has been triggered). This clear is disabled if !!CLASSA_CLR_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSA_ACCUM_CNT", + desc: ''' + Current accumulation value for alert Class A. Software can clear this register + with a write to !!CLASSA_CLR_SHADOWED register unless !!CLASSA_CLR_REGWEN is false. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "AccuCntDw-1:0" } + ], + tags: [// The value of this register is determined by how many alerts have been triggered + // Cannot be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSA_ACCUM_THRESH_SHADOWED", + desc: ''' + Accumulation threshold value for alert Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + fields: [ + { bits: "AccuCntDw-1:0", + desc: '''Once the accumulation value register is equal to the threshold escalation will + be triggered on the next alert occurrence within this class A begins. Note that this + register can not be modified if !!CLASSA_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSA_TIMEOUT_CYC_SHADOWED", + desc: ''' + Interrupt timeout in cycles. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''If the interrupt corresponding to this class is not + handled within the specified amount of cycles, escalation will be triggered. + Set to a positive value to enable the interrupt timeout for Class A. The timeout is set to zero + by default, which disables this feature. Note that this register can not be modified if + !!CLASSA_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSA_CRASHDUMP_TRIGGER_SHADOWED", + desc: ''' + Crashdump trigger configuration for Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + resval: "0", + fields: [ + { bits: "PHASE_DW-1:0", + desc: ''' + Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation + timer states. It is recommended to capture the crashdump upon entering the first escalation phase + that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order + to prevent spurious alert events from masking the original alert causes. + Note that this register can not be modified if !!CLASSA_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSA_PHASE0_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 0 for Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSA_REGWEN is false.''' + } + ] + } + { name: "CLASSA_PHASE1_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 1 for Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSA_REGWEN is false.''' + } + ] + } + { name: "CLASSA_PHASE2_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 2 for Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSA_REGWEN is false.''' + } + ] + } + { name: "CLASSA_PHASE3_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 3 for Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSA_REGWEN is false.''' + } + ] + } + { name: "CLASSA_ESC_CNT", + desc: ''' + Escalation counter in cycles for Class A. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''Returns the current timeout or escalation count (depending on !!CLASSA_STATE). + This register can not be directly cleared. However, SW can indirectly clear as follows. + + If the class is in the Timeout state, the timeout can be aborted by clearing the + corresponding interrupt bit. + + If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be + aborted by writing to !!CLASSA_CLR_SHADOWED. Note however that has no effect if !!CLASSA_REGWEN + is set to false (either by SW or by HW via the !!CLASSA_CTRL_SHADOWED.LOCK feature). + ''' + } + ], + tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted + // Cannot be auto-predicted so excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSA_STATE", + desc: ''' + Current escalation state of Class A. See also !!CLASSA_ESC_CNT. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "2:0", + enum: [ + { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." }, + { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." }, + { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." }, + { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." }, + { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." }, + { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." }, + { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." }, + { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." } + ] + } + ], + tags: [// The current escalation state cannot be auto-predicted + // so this register is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + + { name: "CLASSB_REGWEN", + desc: ''' + Lock bit for Class B configuration. + ''' + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + Class configuration enable bit. + If this is cleared to 0, the corresponding class configuration + registers cannot be written anymore. + ''', + resval: 1, + } + ] + }, + { name: "CLASSB_CTRL_SHADOWED", + desc: "Escalation control register for alert Class B. Can not be modified if !!CLASSB_REGWEN is false." + swaccess: "rw", + hwaccess: "hro", + regwen: "CLASSB_REGWEN", + shadowed: "true", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Enable escalation mechanisms (accumulation and + interrupt timeout) for Class B. Note that interrupts can fire + regardless of whether the escalation mechanisms are enabled for + this class or not. + ''', + } + { bits: "1", + name: "LOCK", + desc: ''' + Enable automatic locking of escalation counter for class B. + If true, there is no way to stop the escalation protocol for class B + once it has been triggered. + ''' + } + { bits: "2", + name: "EN_E0", + resval: 1, + desc: "Enable escalation signal 0 for Class B", + } + { bits: "3", + name: "EN_E1", + resval: 1, + desc: "Enable escalation signal 1 for Class B", + } + { bits: "4", + name: "EN_E2", + resval: 1, + desc: "Enable escalation signal 2 for Class B", + } + { bits: "5", + name: "EN_E3", + resval: 1, + desc: "Enable escalation signal 3 for Class B", + } + { bits: "7:6", + name: "MAP_E0", + resval: 0, + desc: "Determines in which escalation phase escalation signal 0 shall be asserted.", + } + { bits: "9:8", + name: "MAP_E1", + resval: 1, + desc: "Determines in which escalation phase escalation signal 1 shall be asserted.", + } + { bits: "11:10", + name: "MAP_E2", + resval: 2, + desc: "Determines in which escalation phase escalation signal 2 shall be asserted.", + } + { bits: "13:12", + name: "MAP_E3", + resval: 3, + desc: "Determines in which escalation phase escalation signal 3 shall be asserted.", + } + ] + }, + { name: "CLASSB_CLR_REGWEN", + desc: ''' + Clear enable for escalation protocol of Class B alerts. + ''' + swaccess: "rw0c", + hwaccess: "hwo", + fields: [ + { bits: "0", + desc: '''Register defaults to true, can only be cleared. This register is set + to false by the hardware if the escalation protocol has been triggered and the bit + !!CLASSB_CTRL_SHADOWED.LOCK is true. + ''', + resval: 1, + } + ], + tags: [// The value of this register is set to false only by hardware, under the condition + // that escalation is triggered and the corresponding lock bit is true + // Cannot not be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSB_CLR_SHADOWED", + desc: ''' + Clear for escalation protocol of Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + hwqe: "true", + shadowed: "true", + regwen: "CLASSB_CLR_REGWEN", + fields: [ + { bits: "0", + desc: '''Writing 1 to this register clears the accumulator and aborts escalation + (if it has been triggered). This clear is disabled if !!CLASSB_CLR_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSB_ACCUM_CNT", + desc: ''' + Current accumulation value for alert Class B. Software can clear this register + with a write to !!CLASSB_CLR_SHADOWED register unless !!CLASSB_CLR_REGWEN is false. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "AccuCntDw-1:0" } + ], + tags: [// The value of this register is determined by how many alerts have been triggered + // Cannot be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSB_ACCUM_THRESH_SHADOWED", + desc: ''' + Accumulation threshold value for alert Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + fields: [ + { bits: "AccuCntDw-1:0", + desc: '''Once the accumulation value register is equal to the threshold escalation will + be triggered on the next alert occurrence within this class B begins. Note that this + register can not be modified if !!CLASSB_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSB_TIMEOUT_CYC_SHADOWED", + desc: ''' + Interrupt timeout in cycles. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''If the interrupt corresponding to this class is not + handled within the specified amount of cycles, escalation will be triggered. + Set to a positive value to enable the interrupt timeout for Class B. The timeout is set to zero + by default, which disables this feature. Note that this register can not be modified if + !!CLASSB_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSB_CRASHDUMP_TRIGGER_SHADOWED", + desc: ''' + Crashdump trigger configuration for Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + resval: "0", + fields: [ + { bits: "PHASE_DW-1:0", + desc: ''' + Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation + timer states. It is recommended to capture the crashdump upon entering the first escalation phase + that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order + to prevent spurious alert events from masking the original alert causes. + Note that this register can not be modified if !!CLASSB_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSB_PHASE0_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 0 for Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSB_REGWEN is false.''' + } + ] + } + { name: "CLASSB_PHASE1_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 1 for Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSB_REGWEN is false.''' + } + ] + } + { name: "CLASSB_PHASE2_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 2 for Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSB_REGWEN is false.''' + } + ] + } + { name: "CLASSB_PHASE3_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 3 for Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSB_REGWEN is false.''' + } + ] + } + { name: "CLASSB_ESC_CNT", + desc: ''' + Escalation counter in cycles for Class B. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''Returns the current timeout or escalation count (depending on !!CLASSB_STATE). + This register can not be directly cleared. However, SW can indirectly clear as follows. + + If the class is in the Timeout state, the timeout can be aborted by clearing the + corresponding interrupt bit. + + If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be + aborted by writing to !!CLASSB_CLR_SHADOWED. Note however that has no effect if !!CLASSB_REGWEN + is set to false (either by SW or by HW via the !!CLASSB_CTRL_SHADOWED.LOCK feature). + ''' + } + ], + tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted + // Cannot be auto-predicted so excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSB_STATE", + desc: ''' + Current escalation state of Class B. See also !!CLASSB_ESC_CNT. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "2:0", + enum: [ + { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." }, + { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." }, + { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." }, + { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." }, + { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." }, + { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." }, + { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." }, + { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." } + ] + } + ], + tags: [// The current escalation state cannot be auto-predicted + // so this register is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + + { name: "CLASSC_REGWEN", + desc: ''' + Lock bit for Class C configuration. + ''' + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + Class configuration enable bit. + If this is cleared to 0, the corresponding class configuration + registers cannot be written anymore. + ''', + resval: 1, + } + ] + }, + { name: "CLASSC_CTRL_SHADOWED", + desc: "Escalation control register for alert Class C. Can not be modified if !!CLASSC_REGWEN is false." + swaccess: "rw", + hwaccess: "hro", + regwen: "CLASSC_REGWEN", + shadowed: "true", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Enable escalation mechanisms (accumulation and + interrupt timeout) for Class C. Note that interrupts can fire + regardless of whether the escalation mechanisms are enabled for + this class or not. + ''', + } + { bits: "1", + name: "LOCK", + desc: ''' + Enable automatic locking of escalation counter for class C. + If true, there is no way to stop the escalation protocol for class C + once it has been triggered. + ''' + } + { bits: "2", + name: "EN_E0", + resval: 1, + desc: "Enable escalation signal 0 for Class C", + } + { bits: "3", + name: "EN_E1", + resval: 1, + desc: "Enable escalation signal 1 for Class C", + } + { bits: "4", + name: "EN_E2", + resval: 1, + desc: "Enable escalation signal 2 for Class C", + } + { bits: "5", + name: "EN_E3", + resval: 1, + desc: "Enable escalation signal 3 for Class C", + } + { bits: "7:6", + name: "MAP_E0", + resval: 0, + desc: "Determines in which escalation phase escalation signal 0 shall be asserted.", + } + { bits: "9:8", + name: "MAP_E1", + resval: 1, + desc: "Determines in which escalation phase escalation signal 1 shall be asserted.", + } + { bits: "11:10", + name: "MAP_E2", + resval: 2, + desc: "Determines in which escalation phase escalation signal 2 shall be asserted.", + } + { bits: "13:12", + name: "MAP_E3", + resval: 3, + desc: "Determines in which escalation phase escalation signal 3 shall be asserted.", + } + ] + }, + { name: "CLASSC_CLR_REGWEN", + desc: ''' + Clear enable for escalation protocol of Class C alerts. + ''' + swaccess: "rw0c", + hwaccess: "hwo", + fields: [ + { bits: "0", + desc: '''Register defaults to true, can only be cleared. This register is set + to false by the hardware if the escalation protocol has been triggered and the bit + !!CLASSC_CTRL_SHADOWED.LOCK is true. + ''', + resval: 1, + } + ], + tags: [// The value of this register is set to false only by hardware, under the condition + // that escalation is triggered and the corresponding lock bit is true + // Cannot not be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSC_CLR_SHADOWED", + desc: ''' + Clear for escalation protocol of Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + hwqe: "true", + shadowed: "true", + regwen: "CLASSC_CLR_REGWEN", + fields: [ + { bits: "0", + desc: '''Writing 1 to this register clears the accumulator and aborts escalation + (if it has been triggered). This clear is disabled if !!CLASSC_CLR_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSC_ACCUM_CNT", + desc: ''' + Current accumulation value for alert Class C. Software can clear this register + with a write to !!CLASSC_CLR_SHADOWED register unless !!CLASSC_CLR_REGWEN is false. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "AccuCntDw-1:0" } + ], + tags: [// The value of this register is determined by how many alerts have been triggered + // Cannot be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSC_ACCUM_THRESH_SHADOWED", + desc: ''' + Accumulation threshold value for alert Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + fields: [ + { bits: "AccuCntDw-1:0", + desc: '''Once the accumulation value register is equal to the threshold escalation will + be triggered on the next alert occurrence within this class C begins. Note that this + register can not be modified if !!CLASSC_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSC_TIMEOUT_CYC_SHADOWED", + desc: ''' + Interrupt timeout in cycles. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''If the interrupt corresponding to this class is not + handled within the specified amount of cycles, escalation will be triggered. + Set to a positive value to enable the interrupt timeout for Class C. The timeout is set to zero + by default, which disables this feature. Note that this register can not be modified if + !!CLASSC_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSC_CRASHDUMP_TRIGGER_SHADOWED", + desc: ''' + Crashdump trigger configuration for Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + resval: "0", + fields: [ + { bits: "PHASE_DW-1:0", + desc: ''' + Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation + timer states. It is recommended to capture the crashdump upon entering the first escalation phase + that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order + to prevent spurious alert events from masking the original alert causes. + Note that this register can not be modified if !!CLASSC_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSC_PHASE0_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 0 for Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSC_REGWEN is false.''' + } + ] + } + { name: "CLASSC_PHASE1_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 1 for Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSC_REGWEN is false.''' + } + ] + } + { name: "CLASSC_PHASE2_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 2 for Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSC_REGWEN is false.''' + } + ] + } + { name: "CLASSC_PHASE3_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 3 for Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSC_REGWEN is false.''' + } + ] + } + { name: "CLASSC_ESC_CNT", + desc: ''' + Escalation counter in cycles for Class C. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''Returns the current timeout or escalation count (depending on !!CLASSC_STATE). + This register can not be directly cleared. However, SW can indirectly clear as follows. + + If the class is in the Timeout state, the timeout can be aborted by clearing the + corresponding interrupt bit. + + If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be + aborted by writing to !!CLASSC_CLR_SHADOWED. Note however that has no effect if !!CLASSC_REGWEN + is set to false (either by SW or by HW via the !!CLASSC_CTRL_SHADOWED.LOCK feature). + ''' + } + ], + tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted + // Cannot be auto-predicted so excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSC_STATE", + desc: ''' + Current escalation state of Class C. See also !!CLASSC_ESC_CNT. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "2:0", + enum: [ + { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." }, + { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." }, + { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." }, + { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." }, + { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." }, + { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." }, + { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." }, + { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." } + ] + } + ], + tags: [// The current escalation state cannot be auto-predicted + // so this register is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + + { name: "CLASSD_REGWEN", + desc: ''' + Lock bit for Class D configuration. + ''' + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + Class configuration enable bit. + If this is cleared to 0, the corresponding class configuration + registers cannot be written anymore. + ''', + resval: 1, + } + ] + }, + { name: "CLASSD_CTRL_SHADOWED", + desc: "Escalation control register for alert Class D. Can not be modified if !!CLASSD_REGWEN is false." + swaccess: "rw", + hwaccess: "hro", + regwen: "CLASSD_REGWEN", + shadowed: "true", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Enable escalation mechanisms (accumulation and + interrupt timeout) for Class D. Note that interrupts can fire + regardless of whether the escalation mechanisms are enabled for + this class or not. + ''', + } + { bits: "1", + name: "LOCK", + desc: ''' + Enable automatic locking of escalation counter for class D. + If true, there is no way to stop the escalation protocol for class D + once it has been triggered. + ''' + } + { bits: "2", + name: "EN_E0", + resval: 1, + desc: "Enable escalation signal 0 for Class D", + } + { bits: "3", + name: "EN_E1", + resval: 1, + desc: "Enable escalation signal 1 for Class D", + } + { bits: "4", + name: "EN_E2", + resval: 1, + desc: "Enable escalation signal 2 for Class D", + } + { bits: "5", + name: "EN_E3", + resval: 1, + desc: "Enable escalation signal 3 for Class D", + } + { bits: "7:6", + name: "MAP_E0", + resval: 0, + desc: "Determines in which escalation phase escalation signal 0 shall be asserted.", + } + { bits: "9:8", + name: "MAP_E1", + resval: 1, + desc: "Determines in which escalation phase escalation signal 1 shall be asserted.", + } + { bits: "11:10", + name: "MAP_E2", + resval: 2, + desc: "Determines in which escalation phase escalation signal 2 shall be asserted.", + } + { bits: "13:12", + name: "MAP_E3", + resval: 3, + desc: "Determines in which escalation phase escalation signal 3 shall be asserted.", + } + ] + }, + { name: "CLASSD_CLR_REGWEN", + desc: ''' + Clear enable for escalation protocol of Class D alerts. + ''' + swaccess: "rw0c", + hwaccess: "hwo", + fields: [ + { bits: "0", + desc: '''Register defaults to true, can only be cleared. This register is set + to false by the hardware if the escalation protocol has been triggered and the bit + !!CLASSD_CTRL_SHADOWED.LOCK is true. + ''', + resval: 1, + } + ], + tags: [// The value of this register is set to false only by hardware, under the condition + // that escalation is triggered and the corresponding lock bit is true + // Cannot not be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSD_CLR_SHADOWED", + desc: ''' + Clear for escalation protocol of Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + hwqe: "true", + shadowed: "true", + regwen: "CLASSD_CLR_REGWEN", + fields: [ + { bits: "0", + desc: '''Writing 1 to this register clears the accumulator and aborts escalation + (if it has been triggered). This clear is disabled if !!CLASSD_CLR_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSD_ACCUM_CNT", + desc: ''' + Current accumulation value for alert Class D. Software can clear this register + with a write to !!CLASSD_CLR_SHADOWED register unless !!CLASSD_CLR_REGWEN is false. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "AccuCntDw-1:0" } + ], + tags: [// The value of this register is determined by how many alerts have been triggered + // Cannot be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSD_ACCUM_THRESH_SHADOWED", + desc: ''' + Accumulation threshold value for alert Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + fields: [ + { bits: "AccuCntDw-1:0", + desc: '''Once the accumulation value register is equal to the threshold escalation will + be triggered on the next alert occurrence within this class D begins. Note that this + register can not be modified if !!CLASSD_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSD_TIMEOUT_CYC_SHADOWED", + desc: ''' + Interrupt timeout in cycles. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''If the interrupt corresponding to this class is not + handled within the specified amount of cycles, escalation will be triggered. + Set to a positive value to enable the interrupt timeout for Class D. The timeout is set to zero + by default, which disables this feature. Note that this register can not be modified if + !!CLASSD_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSD_CRASHDUMP_TRIGGER_SHADOWED", + desc: ''' + Crashdump trigger configuration for Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + resval: "0", + fields: [ + { bits: "PHASE_DW-1:0", + desc: ''' + Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation + timer states. It is recommended to capture the crashdump upon entering the first escalation phase + that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order + to prevent spurious alert events from masking the original alert causes. + Note that this register can not be modified if !!CLASSD_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSD_PHASE0_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 0 for Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSD_REGWEN is false.''' + } + ] + } + { name: "CLASSD_PHASE1_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 1 for Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSD_REGWEN is false.''' + } + ] + } + { name: "CLASSD_PHASE2_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 2 for Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSD_REGWEN is false.''' + } + ] + } + { name: "CLASSD_PHASE3_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 3 for Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSD_REGWEN is false.''' + } + ] + } + { name: "CLASSD_ESC_CNT", + desc: ''' + Escalation counter in cycles for Class D. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''Returns the current timeout or escalation count (depending on !!CLASSD_STATE). + This register can not be directly cleared. However, SW can indirectly clear as follows. + + If the class is in the Timeout state, the timeout can be aborted by clearing the + corresponding interrupt bit. + + If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be + aborted by writing to !!CLASSD_CLR_SHADOWED. Note however that has no effect if !!CLASSD_REGWEN + is set to false (either by SW or by HW via the !!CLASSD_CTRL_SHADOWED.LOCK feature). + ''' + } + ], + tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted + // Cannot be auto-predicted so excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSD_STATE", + desc: ''' + Current escalation state of Class D. See also !!CLASSD_ESC_CNT. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "2:0", + enum: [ + { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." }, + { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." }, + { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." }, + { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." }, + { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." }, + { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." }, + { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." }, + { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." } + ] + } + ], + tags: [// The current escalation state cannot be auto-predicted + // so this register is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + ], +} diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler_sec_cm_testplan.hjson b/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler_sec_cm_testplan.hjson new file mode 100644 index 0000000000000..08b11bc5ec990 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler_sec_cm_testplan.hjson @@ -0,0 +1,156 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../alert_handler/data/alert_handler.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../alert_handler/data/alert_handler_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: "Verify the countermeasure(s) BUS.INTEGRITY." + stage: V2S + tests: ["alert_handler_tl_intg_err"] + } + { + name: sec_cm_config_shadow + desc: "Verify the countermeasure(s) CONFIG.SHADOW." + stage: V2S + tests: ["alert_handler_shadow_reg_errors"] + } + { + name: sec_cm_ping_timer_config_regwen + desc: "Verify the countermeasure(s) PING_TIMER.CONFIG.REGWEN." + stage: V2S + tests: ["alert_handler_smoke"] + } + { + name: sec_cm_alert_config_regwen + desc: "Verify the countermeasure(s) ALERT.CONFIG.REGWEN." + stage: V2S + tests: ["alert_handler_smoke"] + } + { + name: sec_cm_alert_loc_config_regwen + desc: "Verify the countermeasure(s) ALERT_LOC.CONFIG.REGWEN." + stage: V2S + tests: ["alert_handler_smoke"] + } + { + name: sec_cm_class_config_regwen + desc: "Verify the countermeasure(s) CLASS.CONFIG.REGWEN." + stage: V2S + tests: ["alert_handler_smoke"] + } + { + name: sec_cm_alert_intersig_diff + desc: "Verify the countermeasure(s) ALERT.INTERSIG.DIFF." + stage: V2S + tests: ["alert_handler_sig_int_fail"] + } + { + name: sec_cm_lpg_intersig_mubi + desc: "Verify the countermeasure(s) LPG.INTERSIG.MUBI." + stage: V2S + tests: ["alert_handler_lpg"] + } + { + name: sec_cm_esc_intersig_diff + desc: "Verify the countermeasure(s) ESC.INTERSIG.DIFF." + stage: V2S + tests: ["alert_handler_sig_int_fail"] + } + { + name: sec_cm_alert_rx_intersig_bkgn_chk + desc: "Verify the countermeasure(s) ALERT_RX.INTERSIG.BKGN_CHK." + stage: V2S + tests: ["alert_handler_entropy"] + } + { + name: sec_cm_esc_tx_intersig_bkgn_chk + desc: "Verify the countermeasure(s) ESC_TX.INTERSIG.BKGN_CHK." + stage: V2S + tests: ["alert_handler_entropy"] + } + { + name: sec_cm_esc_rx_intersig_bkgn_chk + desc: "Verify the countermeasure(s) ESC_RX.INTERSIG.BKGN_CHK." + stage: V2S + // This test entry is only valid with prim_esc_receiver module, which is not included in the + // alert_handler testbench. Thus this test point will be checked in `prim_esc` testbench and + // top-level testbench. + tests: ["N/A"] + } + { + name: sec_cm_esc_timer_fsm_sparse + desc: "Verify the countermeasure(s) ESC_TIMER.FSM.SPARSE." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_ping_timer_fsm_sparse + desc: "Verify the countermeasure(s) PING_TIMER.FSM.SPARSE." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_esc_timer_fsm_local_esc + desc: "Verify the countermeasure(s) ESC_TIMER.FSM.LOCAL_ESC." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_ping_timer_fsm_local_esc + desc: "Verify the countermeasure(s) PING_TIMER.FSM.LOCAL_ESC." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_esc_timer_fsm_global_esc + desc: "Verify the countermeasure(s) ESC_TIMER.FSM.GLOBAL_ESC." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_accu_ctr_redun + desc: "Verify the countermeasure(s) ACCU.CTR.REDUN." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_esc_timer_ctr_redun + desc: "Verify the countermeasure(s) ESC_TIMER.CTR.REDUN." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_ping_timer_ctr_redun + desc: "Verify the countermeasure(s) PING_TIMER.CTR.REDUN." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_ping_timer_lfsr_redun + desc: "Verify the countermeasure(s) PING_TIMER.LFSR.REDUN." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler_testplan.hjson b/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler_testplan.hjson new file mode 100644 index 0000000000000..7de5a99b8fdb8 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/data/alert_handler_testplan.hjson @@ -0,0 +1,285 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "alert_handler" + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson", + "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + "hw/dv/sv/alert_esc_agent/data/alert_agent_basic_testplan.hjson", + "hw/dv/sv/alert_esc_agent/data/alert_agent_additional_testplan.hjson", + "hw/dv/sv/alert_esc_agent/data/esc_agent_basic_testplan.hjson", + "hw/dv/sv/alert_esc_agent/data/esc_agent_additional_testplan.hjson", + // Generated in IP gen area (hw/{top}/ip_autogen). + "alert_handler_sec_cm_testplan.hjson"] + testpoints: [ + { + name: smoke + desc: ''' + - Alert_handler smoke test with one class configured that escalates through all + phases after one alert has been triggered + - Check interrupt pins, alert cause CSR values, escalation pings, and crashdump_o + output values + - Support both synchronous and asynchronous settings + ''' + stage: V1 + tests: ["alert_handler_smoke"] + } + { + name: esc_accum + desc: ''' + Based on the smoke test, this test will focus on testing the escalation accumulation + feature. So all the escalations in the test will be triggered by alert accumulation. + ''' + stage: V2 + tests: ["alert_handler_esc_alert_accum"] + } + { + name: esc_timeout + desc: ''' + Based on the smoke test, this test will focus on testing the escalation timeout + feature. So all the escalations in the test will be triggered by interrupt timeout. + ''' + stage: V2 + tests: ["alert_handler_esc_intr_timeout"] + } + { + name: entropy + desc: ''' + Based on the smoke test, this test enables ping testing, and check if the ping feature + correctly pings all devices within certain period of time. + ''' + stage: V2 + tests: ["alert_handler_entropy"] + } + { + name: sig_int_fail + desc: ''' + This test will randomly inject differential pair failures on alert tx/rx pairs and the + escalator tx/rx pairs. Then check if integrity failure alert is triggered and + escalated. + ''' + stage: V2 + tests: ["alert_handler_sig_int_fail"] + } + { + name: clk_skew + desc: ''' + This test will randomly inject clock skew within the differential pairs. Then check no + alert is raised. + ''' + stage: V2 + tests: ["alert_handler_smoke"] + } + { + name: random_alerts + desc: "Input random alerts and randomly write phase cycles." + stage: V2 + tests: ["alert_handler_random_alerts"] + } + { + name: random_classes + desc: "Based on random_alerts test, this test will also randomly enable interrupt classes." + stage: V2 + tests: ["alert_handler_random_classes"] + } + { + name: ping_timeout + desc: ''' + Based on entropy test, this test request alert_sender and esc_receiver drivers to + randomly create ping requests timeout stimulus. + + Checks: + - Verify interrupt pin and states. + - Verify alert and local alert causes. + - Verify escalation states and counts. + ''' + stage: V2 + tests: ["alert_handler_ping_timeout"] + } + { + name: lpg + desc: ''' + Test alert_handler low_power_group(lpg) request. + + Stimulus: + - Randomly enabled alert_receivers' `alert_en` but disable their ping response. + - Turn on their low-power control by either set `lpg_cg_en_i` or `lpg_rst_en_i`. + Or pause the alert_handler's clk input for a random period of time. + - Enable alert ping timeout local alert. + - Run alert_handler_entropy_vseq. + + Checks: + - Expect no ping timeout error because the alert_receivers are disabled via low-power + group, or because alert_handler's clk input is paused due to sleep mode. + ''' + stage: V2 + tests: ["alert_handler_lpg", "alert_handler_lpg_stub_clk"] + } + { + name: stress_all + desc: ''' + Combine above sequences in one test to run sequentially with the following exclusions: + - CSR sequences: scoreboard disabled + - Ping_corner_cases sequence: included reset in the sequence + ''' + stage: V2 + tests: ["alert_handler_stress_all"] + } + { + name: alert_handler_entropy_stress_test + desc: ''' + Stress the alert_handler's entropy request and make sure there is no spurious alert. + + Stimulus: + - Randomly force the `wait_cyc_mask_i` to a legal value to stress the ping requests. + - Wait for all alerts at least being pinged for a few times. + Checks: + - Check alert_cause and loc_alert_cause registers to make sure there is no spurious + alert being fired. + ''' + stage: V2 + tests: ["alert_handler_entropy_stress"] + } + + { + name: alert_handler_alert_accum_saturation + desc: ''' + This sequence forces all four alert classes' accumulate counters to a large value that + is close to the max saturation value. + Then the sequence triggers alerts until the count saturates. + + Checks: + - Check `accum_cnt` register does not overflow, but stays at the max value. + - Check the correct interrupt fires if even the count saturates. + ''' + stage: V2 + tests: ["alert_handler_alert_accum_saturation"] + } + ] + + covergroups: [ + { + name: accum_cnt_cg + desc: '''Covers escalation due to accumulated alerts. + + - Collect the threshold of accumulated alerts. + - Collect which alert_class exceeds the accumulated count. + - Cross the above coverpoints. + ''' + } + { + name: intr_timeout_cnt_cg + desc: '''Covers escalation due to interrupt timeout. + + - Collect the threshold of interrupt timeout cycles. + - Collect which alert_class exceeds the timeout threshold. + - Cross the above coverpoints. + ''' + } + { + name: esc_sig_length_cg + desc: '''Covers escalation signal length for each escalation signal.''' + } + { + name: clear_intr_cnt_cg + desc: '''Covers interrupt counter being cleared by class_clr_shadowed register.''' + } + { + name: clear_esc_cnt_cg + desc: '''Covers escalation counter being cleared by class_clr_shadowed register.''' + } + { + name: alert_cause_cg + desc: '''Covers alert_cause register and related items. + + - Collect which alert causes the alert_cause register to set. + - Collect the alert_class that this alert belongs to. + - Cross the above coverpoints. + ''' + } + { + name: alert_loc_alert_cause_cg + desc: '''Covers loc_alert_cause register regarding alert. + + - Collect two loc_alert causes: alert_ping_fail and alert_integrity_fail. + - Collect which alert triggers this loc_alert. + - Collect the alert_class that this local alert belongs to. + - Cross the first coverpoint with the rest of the coverpoints. + ''' + } + { + name: esc_loc_alert_cause_cg + desc: '''Covers loc_alert_cause register regarding escalation. + + - Collect two loc_alert causes: esc_ping_fail and esc_integrity_fail. + - Collect which escalation triggers this loc_alert. + - Collect the alert_class that this local alert belongs to. + - Cross the first coverpoint with the rest of the coverpoints. + ''' + } + { + name: crashdump_trigger_cg + desc: '''Covers which phase triggers crashdump.''' + } + { + name: alert_en_regwen_cg + desc: '''Covers if regwen is locked for alert_en registers.''' + } + { + name: alert_class_regwen_cg + desc: '''Covers if regwen is locked for alert_class registers.''' + } + { + name: loc_alert_en_regwen_cg + desc: '''Covers if regwen is locked for loc_alert_en registers.''' + } + { + name: loc_alert_class_regwen_cg + desc: '''Covers if regwen is locked for loc_alert_class registers.''' + } + { + name: class_ctrl_regwen_cg + desc: '''Covers if regwen is locked for class_ctrl registers.''' + } + { + name: class_clr_regwen_cg + desc: '''Covers if regwen is locked for class_clr registers.''' + } + { + name: class_accum_thresh_regwen_cg + desc: '''Covers if regwen is locked for class_accum_thresh registers.''' + } + { + name: class_timeout_cyc_regwen_cg + desc: '''Covers if regwen is locked for class_timeout_cyc registers.''' + } + { + name: class_crashdump_trigger_regwen_cg + desc: '''Covers if regwen is locked for class_crashdump_trigger registers.''' + } + { + name: class_phase_cyc_regwen_cg + desc: '''Covers if regwen is locked for class_phase_cyc registers.''' + } + { + name: num_edn_reqs_cg + desc: '''Covers if simulation runs long enough to capture more than five EDN requests.''' + } + { + name: num_checked_pings_cg + desc: '''Covers if simulation runs long enough to capture more than twenty ping requests.''' + } + { + name: cycles_bwtween_pings_cg + desc: '''Covers how many cycles are there between two ping requests.''' + } + { + name: alert_ping_with_lpg_wrap_cg + desc: '''Covers ping requests are initiated with LPG enabled or disabled.''' + } + + ] +} diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/data/top_darjeeling_alert_handler.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/alert_handler/data/top_darjeeling_alert_handler.ipconfig.hjson new file mode 100644 index 0000000000000..388972533ea29 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/data/top_darjeeling_alert_handler.ipconfig.hjson @@ -0,0 +1,219 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_alert_handler + param_values: + { + n_alerts: 99 + esc_cnt_dw: 32 + accu_cnt_dw: 16 + async_on: + [ + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + ] + n_classes: 4 + n_lpg: 19 + lpg_map: + [ + 5'd0 + 5'd0 + 5'd1 + 5'd2 + 5'd3 + 5'd4 + 5'd4 + 5'd4 + 5'd4 + 5'd4 + 5'd4 + 5'd4 + 5'd4 + 5'd5 + 5'd6 + 5'd7 + 5'd7 + 5'd7 + 5'd7 + 5'd7 + 5'd8 + 5'd10 + 5'd10 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd12 + 5'd13 + 5'd14 + 5'd15 + 5'd15 + 5'd16 + 5'd17 + 5'd17 + 5'd18 + 5'd18 + 5'd14 + 5'd14 + 5'd14 + 5'd14 + 5'd14 + 5'd14 + 5'd14 + 5'd14 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + ] + topname: darjeeling + } +} diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_alert_rxtx.svg b/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_alert_rxtx.svg new file mode 100644 index 0000000000000..d851d503f36b3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_alert_rxtx.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_block_diagram.svg b/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_block_diagram.svg new file mode 100644 index 0000000000000..1976ea10fb97e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_block_diagram.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_escalation_rxtx.svg b/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_escalation_rxtx.svg new file mode 100644 index 0000000000000..9012f2c0d2934 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_escalation_rxtx.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_lp_overview.svg b/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_lp_overview.svg new file mode 100644 index 0000000000000..0278ad8baa114 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_lp_overview.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_lpg_ctrl.svg b/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_lpg_ctrl.svg new file mode 100644 index 0000000000000..d524dacae9399 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_lpg_ctrl.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_receiver_fsm.svg b/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_receiver_fsm.svg new file mode 100644 index 0000000000000..840987ade9a6b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/doc/alert_handler_receiver_fsm.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/doc/checklist.md b/hw/top_darjeeling/ip_autogen/alert_handler/doc/checklist.md new file mode 100644 index 0000000000000..d398772f97776 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/doc/checklist.md @@ -0,0 +1,266 @@ +# Alert Handler Checklist + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [Alert Handler peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|----------------------- |-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done | [Alert Handler spec](../README.md) +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | Done | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Done | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. +Documentation | [MISSING_FUNC][] | Done | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | +RTL | [STYLE_X][] | Done | +RTL | [CDC_SYNCMACRO][] | Done | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [AREA_CHECK][] | Done | +Code Quality | [TIMING_CHECK][] | Done | +Security | [SEC_CM_DOCUMENTED][] | Done | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | Done | +Security | [SEC_CM_NON_RESET_FLOPS][] | Done | +Security | [SEC_CM_SHADOW_REGS][] | Done | +Security | [SEC_CM_RTL_REVIEWED][] | Done | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Done | + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Done | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_RTL][] | Done | +Review | [REVIEW_DELETED_FF][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | adk@ vogelpi@ +Review | Signoff date | Done | 2024-08-08 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | +Documentation | [TESTPLAN_COMPLETED][] | Done | +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | Done | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | N/A | +Tests | [SIM_SMOKE_TEST_PASSING][] | Done | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done | +Regression | [FPV_REGRESSION_SETUP][] | N/A | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Done | prim_alert_receiver and prim_esc_sender. +Review | [DESIGN_SPEC_REVIEWED][] | Done | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Done | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | Done | +Tests | [SIM_ALL_TESTS_PASSING][] | Done | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | N/A | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | N/A | +Tests | [SIM_FW_SIMULATED][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Done | +Coverage | [SIM_CODE_COVERAGE_V2][] | Done | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Done | +Coverage | [FPV_CODE_COVERAGE_V2][] | N/A | +Coverage | [FPV_COI_COVERAGE_V2][] | N/A | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Done | prim_alert_receiver and prim_esc_sender. +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]: ../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done | +Tests | [FPV_SEC_CM_PROVEN][] | Done | +Tests | [SIM_SEC_CM_VERIFIED][] | Done | +Coverage | [SIM_COVERAGE_REVIEWED][] | Done | +Review | [SEC_CM_DV_REVIEWED][] | Done | + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_proven +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/doc/programmers_guide.md b/hw/top_darjeeling/ip_autogen/alert_handler/doc/programmers_guide.md new file mode 100644 index 0000000000000..7f6f368b40e57 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/doc/programmers_guide.md @@ -0,0 +1,122 @@ +# Programmer's Guide + + +## Power-up and Reset Considerations + +False alerts during power-up and reset are not possible since the alerts are disabled by default, and need to be configured and locked in by the firmware. +The ping timer won't start until initial configuration is over and the registers are locked in. + +The low-power state management of alert channels is handled entirely by hardware and hence this is transparent to software. +Note however that the LPGs inherit the security properties of the associated clock groups and resets. +This means that the low-power state of certain alerts can be controlled by SW by means of clock gating or block reset. +For example, certain crypto blocks are located in a transactional clock group which can be clock gated by SW - and this also affects the associated alerts of these crypto blocks. +See [clock](../../clkmgr/README.md) and [reset managers](../../rstmgr/README.md) for more detail. + + +## Initialization + +To initialize the block, software running at a high privilege levels (early in the security settings process) should do the following: + +1. For each alert and each local alert: + + - Determine if alert is enabled (should only be false if alert is known to be faulty). + Set [`ALERT_EN_SHADOWED_0.EN_A_0`](../data/alert_handler.hjson#alert_en_shadowed_0) and [`LOC_ALERT_EN_SHADOWED_0.EN_LA_0`](../data/alert_handler.hjson#loc_alert_en_shadowed_0) accordingly. + + - Determine which class (A..D) the alert is associated with. + Set [`ALERT_CLASS_SHADOWED_0.CLASS_A_0`](../data/alert_handler.hjson#alert_class_shadowed_0) and [`LOC_ALERT_CLASS_SHADOWED_0.CLASS_LA_0`](../data/alert_handler.hjson#loc_alert_class_shadowed_0) accordingly. + + - Optionally lock each alert configuration by writing 0 to [`ALERT_REGWEN_0.EN_0`](../data/alert_handler.hjson#alert_regwen_0) or [`LOC_ALERT_REGWEN_0.EN_0`](../data/alert_handler.hjson#loc_alert_regwen_0). + Note however that only **locked and enabled** alerts are going to be pinged using the ping mechanism. + This ensures that spurious ping failures cannot occur when previously enabled alerts are being disabled again (before locking). + + +2. Set the ping timeout value [`PING_TIMEOUT_CYC_SHADOWED`](../data/alert_handler.hjson#ping_timeout_cyc_shadowed). + This value is dependent on the clock ratios present in the system. + +3. For each class (A..D): + + - Determine whether to enable escalation mechanisms (accumulation / interrupt timeout) for this particular class. Set [`CLASSA_CTRL_SHADOWED.EN`](../data/alert_handler.hjson#classa_ctrl_shadowed) accordingly. + + - Determine if this class of alerts allows clearing of escalation once it has begun. + Set [`CLASSA_CTRL_SHADOWED.LOCK`](../data/alert_handler.hjson#classa_ctrl_shadowed) to true if clearing should be disabled. + If true, once escalation protocol begins, it can not be stopped, the assumption being that it ends in a chip reset else it will be rendered useless thenceforth. + + - Determine the number of alerts required to be accumulated before escalation protocol kicks in. Set [`CLASSA_ACCUM_THRESH`](../data/alert_handler.hjson#classa_accum_thresh) accordingly. + + - Determine whether the interrupt associated with that class needs a timeout. + If yes, set [`CLASSA_TIMEOUT_CYC_SHADOWED`](../data/alert_handler.hjson#classa_timeout_cyc_shadowed) to an appropriate value greater than zero (zero corresponds to an infinite timeout and disables the mechanism). + + - For each escalation phase (0..3): + - Determine length of each escalation phase by setting [`CLASSA_PHASE0_CYC`](../data/alert_handler.hjson#classa_phase0_cyc) accordingly + + - For each escalation signal (0..3): + - Determine whether to enable the escalation signal, and set the [`CLASSA_CTRL_SHADOWED.E0_EN`](../data/alert_handler.hjson#classa_ctrl_shadowed) bit accordingly (default is enabled). + Note that setting all of the `E*_EN` bits to 0 within a class has the same effect of disabling the entire class by setting [`CLASSA_CTRL_SHADOWED.EN`](../data/alert_handler.hjson#classa_ctrl_shadowed) to zero. + - Determine the phase -> escalation mapping of this class and program it via the [`CLASSA_CTRL_SHADOWED.E0_MAP`](../data/alert_handler.hjson#classa_ctrl_shadowed) values if it needs to be changed from the default mapping (0->0, 1->1, 2->2, 3->3). + + - Optionally lock the class configuration by writing 0 to [`CLASSA_CTRL_SHADOWED.REGWEN`](../data/alert_handler.hjson#classa_ctrl_shadowed). + +4. After initial configuration at startup, enable the ping timer mechanism by writing 1 to [`PING_TIMER_EN`](../data/alert_handler.hjson#ping_timer_en). +It is also recommended to lock the ping timer configuration by clearing [`PING_TIMER_REGWEN`](../data/alert_handler.hjson#ping_timer_regwen). +Note that only **locked and enabled** alerts are going to be pinged using the ping mechanism. +This ensures that spurious ping failures cannot occur when previously enabled alerts are being disabled again (before locking). + +## Interrupt Handling + +For every alert that is enabled, an interrupt will be triggered on class A, B, C, or D. +To handle an interrupt of a particular class, software should execute the following steps: + +1. If needed, check the escalation state of this class by reading [`CLASSA_STATE`](../data/alert_handler.hjson#classa_state). + This reveals whether escalation protocol has been triggered and in which escalation phase the class is. + In case interrupt timeouts are enabled the class will be in timeout state unless escalation has already been triggered. + The current interrupt or escalation cycle counter can be read via [`CLASSA_ESC_CNT`](../data/alert_handler.hjson#classa_esc_cnt). + +2. Since the interrupt does not indicate which alert triggered, SW must read the cause registers [`LOC_ALERT_CAUSE`](../data/alert_handler.hjson#loc_alert_cause) and [`ALERT_CAUSE`](../data/alert_handler.hjson#alert_cause) etc. + The cause bits of all alerts are concatenated and chunked into 32bit words. + Hence the register file contains as many cause words as needed to cover all alerts present in the system. + Each cause register contains a sticky bit that is set by the incoming alert, and is clearable with a write by software. + This should only be cleared after software has cleared the event trigger, if applicable. + It is possible that the event requires no clearing (e.g. a parity error), or can't be cleared (a breach in the metal mesh protecting the chip). + + Note that in the rare case when multiple events are triggered at or about the same time, all events should be cleared before proceeding. + +3. After the event is cleared (if needed or possible), software should handle the interrupt as follows: + + - Resetting the accumulation register for the class by writing [`CLASSA_CLR`](../data/alert_handler.hjson#classa_clr). + This also aborts the escalation protocol if it has been triggered. + If for some reason it is desired to never allow the accumulator or escalation to be cleared, software can initialize the [`CLASSA_CLR_REGWEN`](../data/alert_handler.hjson#classa_clr_regwen) register to zero. + If [`CLASSA_CLR_REGWEN`](../data/alert_handler.hjson#classa_clr_regwen) is already false when an alert interrupt is detected (either due to software control or hardware trigger via [`CLASSA_CTRL_SHADOWED.LOCK`](../data/alert_handler.hjson#classa_ctrl_shadowed)), then the accumulation counter can not be cleared and this step has no effect. + + - After the accumulation counter is reset (if applicable), software should clear the class A interrupt state bit [`INTR_STATE.CLASSA`](../data/alert_handler.hjson#intr_state). + Clearing the class A interrupt state bit also clears and stops the interrupt timeout counter (if enabled). + +Note that testing interrupts by writing to the interrupt test registers does also trigger the internal interrupt timeout (if enabled), since the interrupt state is used as enable signal for the timer. +However, alert accumulation will not be triggered by this testing mechanism. + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_alert_handler.h) + +## Register Table + +* [Register Table](../data/alert_handler.hjson#registers) + + +# Additional Notes + +## Timing Constraints + +The skew within all differential signal pairs must be constrained to be smaller than the period of the fastest clock operating the alert handler receivers. +The maximum propagation delay of differential pair should also be constrained (although it may be longer than the clock periods involved). + + +## Fast-track Alerts + +Note that it is possible to program a certain class to provide a fast-track response for critical alerts by setting its accumulation trigger value to 1, and configuring the escalation protocol such that the appropriate escalation measure is triggered within escalation phase 0. +This results in a minimal escalation latency of 4 clock cycles from alert sender input to escalation receiver output in the case where all involved signaling modules are completely synchronous with the alert handler. +In case the alert sender is asynchronous w.r.t. to the alert handler, the actual latency depends on the clock periods involved. +Assuming both clocks have the same frequency alert propagation takes at least 6-8 clock alert handler clock cycles. + +For alerts that mandate an asynchronous response (i.e. without requiring a clock to be active), it is highly recommended to build a separate network at the top-level. +That network should OR' the critical sources together and route the asynchronous alert signal directly to the highest severity countermeasure device. +Examples for alert conditions of this sort would be attacks on the secure clock. diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/doc/theory_of_operation.md b/hw/top_darjeeling/ip_autogen/alert_handler/doc/theory_of_operation.md new file mode 100644 index 0000000000000..1e375feae9f2f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/doc/theory_of_operation.md @@ -0,0 +1,785 @@ +# Theory of Operation + +## Block Diagram + +The figure below shows a block diagram of the alert handler module, as well as a few examples of alert senders in other peripheral modules. +In this diagram, there are seven sources of alerts: three sources from external modules (two from `periph0` and one from `periph1`), and four local sources (`alert_ping_fail`, `alert_sig_int`, `esc_ping_fail`, `esc_sig_int`). +The local sources represent alerts that are created by this module itself. See the later section on special local alerts. + +![Alert Handler Block Diagram](alert_handler_block_diagram.svg) + +Also shown are internal modules for classification, interrupt generation, accumulation, escalation, ping generation and alert-channel low-power control. +These are described later in the document. +Note that the differential alert sender and receiver blocks used for alert signaling support both _asynchronous_ and _synchronous_ clocking schemes, and hence peripherals able to raise alerts may be placed in clock domains different from that of the alert handler (Jittered clock domains are also supported in the asynchronous clocking scheme). +Proper care must however be taken when formulating the timing constraints for the diff pairs, and when determining clock-dependent parameters (such as the ping timeout) of the design. +On the escalation sender / receiver side, the differential signaling blocks employ a fully synchronous clocking scheme throughout. + +## Hardware Interfaces + +### Parameters + +The following table lists the main parameters used throughout the alert handler design. +Note that the alert handler is generated based on the system configuration, and hence these parameters are placed into a package as "localparams". +The parameterization rules are explained in more detail in the architectural description. + +Localparam | Default (Max) | This Core | Description +---------------|-----------------------|----------------|--------------- +`NAlerts` | 8 (248) | 99 | Number of alert instances. Maximum number bounded by LFSR implementation that generates ping timing. +`NLpg` | 1 | 19 | Number of unique low-power groups as determined by topgen. +`LpgMap` | {0} | see RTL | Array mapping each alert to a unique low-power group as determined by topgen. +`EscCntWidth` | 32 (32) | 32 | Width of the escalation counters in bit. +`AccuCntWidth` | 16 (32) | 16 | Width of the alert accumulation counters in bit. +`AsyncOn` | '0 (2^`NAlerts`-1) | see RTL | This is a bit array specifying whether a certain alert sender / receiver pair goes across an asynchronous boundary or not. + +The next table lists free parameters in the `prim_alert_sender` and +`prim_alert receiver` submodules. + +Parameter | Default (Max) | Description +---------------|------------------|--------------- +`AsyncOn` | `1'b0` (`1'b1`) | 0: Synchronous, 1: Asynchronous, determines whether additional synchronizer flops and logic need to be instantiated. + + +### Signals + +* [Interface Tables](../data/alert_handler.hjson#interfaces) + +The table below lists other alert handler module signals. +The number of alert instances is parametric and hence alert and ping diff pairs are grouped together in packed arrays. +The diff pair signals are indexed with the corresponding alert instance ``. + +Signal | Direction | Type | Description +-------------------------|------------------|---------------- |--------------- +`edn_o` | `output` | `otp_edn_req_t` | Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation. +`edn_i` | `input` | `otp_edn_rsp_t` | Entropy acknowledgment to the entropy distribution network for LFSR reseeding and ephemeral key derivation. +`alert_tx_i[]` | `input` | packed `alert_tx_t` array | Incoming alert or ping response(s), differentially encoded. Index range: `[NAlerts-1:0]` +`alert_rx_o[]` | `output` | packed `alert_rx_t` array | Outgoing alert acknowledgment and ping requests, differentially encoded. Index range: `[NAlerts-1:0]` +`esc_tx_o[]` | `output` | packed `esc_tx_t` array | Escalation or ping request, differentially encoded. Index corresponds to severity level, and ranges from 0 to 3. +`esc_rx_i[]` | `input` | packed `esc_rx_t` array | Escalation ping response, differentially encoded. Index corresponds to severity level, and ranges from 0 to 3. +`lpg_cg_en_i[]` | `input` | packed `mubi4_t` array | Incoming clock gated indication from clock manager. Index range: `[NLpg-1:0]` +`lpg_rst_en_i[]` | `input` | packed `mubi4_t` array | Incoming reset asserted indication from reset manager. Index range: `[NLpg-1:0]` +`crashdump_o` | `output` | packed `struct` | This is a collection of alert handler state registers that can be latched by hardware debugging circuitry, if needed. + +#### Entropy Network Connections + +The LFSR ping timer needs to be periodically reseeded. +Therefore, the alert handler is connected to the entropy distribution network via the `edn_i/o` signals. + +#### Alert Channels + +For each alert, there is a pair of input and two pairs of output signals. +These signals are connected to a differential sender module within the source, and a differential receiver module within the alert handler. +Both of these modules are described in more detail in the following section. +These signal pairs carry differentially encoded messages that enable two types of signaling: a native alert and a ping/response test of the alert mechanism. +The latter is to ensure that all alert senders are always active and have not been the target of an attack. + +#### Escalation Channels + +For each escalation action in the system, there is a pair of input and a pair of output signals, encapsulated in the `esc_rx_t` and `esc_tx_t` types. +These signals are connected to a differential sender module within the alert handler, and a differential receiver module within the module that performs a particular escalation action (for example the reset manager or life cycle controllers). +The signal pairs carry differentially encoded messages that enable two types of signaling: a native escalation and a ping/response test of the escalation mechanism. +The latter is to ensure that all escalation receivers are always active and have not been the target of an attack. + +#### Low-power Indication Signals + +The `lpg_cg_en_i` and `lpg_rst_en_i` are two arrays with multibit indication signals from the [clock](../../clkmgr/README.md) and [reset managers](../../rstmgr/README.md). +These indication signals convey whether a specific group of alert senders are either clock gated or in reset. +As explained in [more detail below](#low-power-management-of-alert-channels), this information is used to temporarily halt the ping timer mechanism on channels that are in a low-power state in order to prevent false positives. + +#### Crashdump Output + +The `crashdump_o` struct outputs a snapshot of CSRs and alert handler state bits that can be read by hardware debugging circuitry: + +```systemverilog + typedef struct packed { + // alerts + logic [NAlerts-1:0] alert_cause; // alert cause bits + logic [6:0] loc_alert_cause; // local alert cause bits + // class state + logic [3:0][15:0] class_accum_cnt; // current accumulator value + logic [3:0][31:0] class_esc_cnt; // current escalation counter value + cstate_e [3:0] class_esc_state; // current escalation protocol state + } alert_crashdump_t; +``` + +This can be useful for extracting more information about possible failures or bugs without having to use the tile-link bus interface (which may become unresponsive under certain circumstances). +It is recommended for the top level to store this information in an always-on location. + +Note that the crashdump state is continuously output via `crashdump_o` until the latching trigger condition is true for the first time (see [`CLASSA_CRASHDUMP_TRIGGER_SHADOWED`](../data/alert_handler.hjson#classa_crashdump_trigger_shadowed)). +After that, the `crashdump_o` is held constant until all classes that have escalated are cleared. +This is done so that it is possible to capture the true alert cause before spurious alert events start to pop up due to escalation countermeasures with excessive side effects (like life cycle scrapping for example). +If classes that have escalated are not configured as clearable, then it is not possible to re-arm the crashdump latching mechanism at runtime and the alert handler has to be reset. + +## Design Details + +This section gives the full design details of the alert handler module and its submodules. + + +### Alert Definition + +Alerts are defined as events that have security implications, and should be handled by the main processor, or escalated to other hardware modules to take action. +Each peripheral has the option to define one or more alert signals. +Those peripherals should instantiate one module (`prim_alert_sender`) to convert the event associated with that alert into a signal to the alert handler module. +The alert handler instantiates one receiver module (`prim_alert_receiver`) per alert, then handles the classification, accumulation, and escalation of the received signal. +The differential signaling submodules may either use a synchronous or asynchronous clocking scheme, since the message type to be transferred is a single discrete event. + + +### Differential Alert Signaling + +Each alert sender is connected to the corresponding alert receiver via the 3 differential pairs `alert_tx_i/o.alert_p/n`, `alert_rx_i/o.ack_p/n` and `alert_rx_i/o.ping_p/n`, as illustrated below: + +![Alert Handler Alert RXTX](alert_handler_alert_rxtx.svg) + +Alerts are encoded differentially and signaled using a full handshake on the `alert_tx_i/o.alert_p/n` and `alert_rx_i/o.ack_p/n` wires. +The use of a full handshake protocol allows this mechanism to be used with an asynchronous clocking strategy, where peripherals may reside in a different clock domain than the alert handler. +The full handshake guarantees that alert messages are correctly back-pressured and no alert is "lost" at the asynchronous boundary due to (possibly variable) clock ratios greater or less than 1.0. +The "native alert message" will be repeated on the output wires as long as the alert event is still true within the peripheral. + +The wave pattern below illustrates differential full handshake mechanism. + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p...............' }, + { name: 'alert_req_i', wave: '01.|..|..|...|..' }, + { name: 'alert_ack_o', wave: '0..|..|..|10.|..' }, + { name: 'alert_tx_o/i.alert_p', wave: '01.|..|0.|..1|..' , node: '.a.....c....e'}, + { name: 'alert_tx_o/i.alert_n', wave: '10.|..|1.|..0|..' }, + { name: 'alert_rx_i/o.ack_p', wave: '0..|1.|..|0..|1.' , node: '....b.....d..'}, + { name: 'alert_rx_i/o.ack_n', wave: '1..|0.|..|1..|0.' }, + { name: 'alert_o', wave: '0..|10|..|...|10' }, + ], + edge: [ + 'a~>b Phase 0/1', + 'b~>c Phase 1/2', + 'c~>d Phase 2/3', + 'd~>e 2 Pause Cycles', + ], + head: { + text: 'Alert signaling and repeat pattern', + }, + foot: { + text: 'Native alert at time 1 with 4-phase handshake; repeated alert at time 12;', + tick: 0, + } +} +``` + +The handshake pattern is repeated as long as the alert is true. +The sender will wait for 2 cycles between handshakes. + +Note that the alert is immediately propagated to `alert_o` once the initial level change on `alert_tx_i.alert_p/n` has been received and synchronized to the local clock on the receiver side. +This ensures that the first occurrence of an alert is always propagated - even if the handshake lines have been manipulated to emulate backpressure. +(In such a scenario, all subsequent alerts would be back-pressured and eventually the ping testing mechanism described in the next subsection would detect that the wires have been tampered with.) + +The alert sender and receiver modules can either be used synchronously or asynchronously. +The signaling protocol remains the same in both cases, but the additional synchronizer flops at the diff pair inputs may be omitted, which results in lower signaling latency. + +### Ping Testing + +In order to ensure that the event sending modules have not been compromised, the alert receiver module `prim_alert_receiver` will "ping" or line-test the senders periodically every few microseconds. +Pings timing is randomized so their appearance can not be predicted. + + +The ping timing is generated by a central LFSR-based timer within the alert handler that randomly asserts the `ping_req_i` signal of a particular `prim_alert_receiver` module. +Once `ping_req_i` is asserted, the receiver module encodes the ping message as a level change on the differential `alert_rx_o.ping_p/n` output, and waits until the sender responds with a full handshake on the `alert_tx_i.alert_p/n` and `alert_rx_o.ack_p/n` lines. +Once that handshake is complete, the `ping_ok_o` signal is asserted. +The LFSR timer has a programmable ping timeout, after which it will automatically assert a "pingfail" alert. +That timeout is a function of the clock ratios present in the system, and has to be programmed accordingly at system startup (as explained later in the LFSR timer subsection). + +The following wave diagram illustrates a correct ping sequence, viewed from the receiver side: + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p..............' }, + { name: 'ping_req_i', wave: '01.|..|..|..|.0' }, + { name: 'ping_ok_o', wave: '0..|..|..|..|10' , node: '.............e'}, + { name: 'alert_rx_o.ping_p', wave: '01.|..|..|..|..' , node: '.a'}, + { name: 'alert_rx_o.ping_n', wave: '10.|..|..|..|..' , node: '.b'}, + { name: 'alert_tx_i.alert_p', wave: '0..|1.|..|0.|..' , node: '....c'}, + { name: 'alert_tx_i.alert_n', wave: '1..|0.|..|1.|..' }, + { name: 'alert_rx_o.ack_p', wave: '0..|..|1.|..|0.' , node: '.............d'}, + { name: 'alert_rx_o.ack_n', wave: '1..|..|0.|..|1.' }, + ], + edge: [ + 'a-b', + 'b~>c ping response', + 'd->e response complete', + ], + head: { + text: 'Ping testing', + }, + foot: { + text: 'Level change at time 1 triggers a full handshake (ping response) at time 4', + tick: 0, + } +} +``` + +In the unlikely case that a ping request collides with a native alert at the sender side, the native alert is held back until the ping handshake has been completed. +This slightly delays the transmission of a native alert, but the alert will eventually be signaled. +Further, if an alert is sent out right before a ping requests comes in at the sender side, the receiver will treat the alert as a ping response. +However, the "true" ping response will be returned right after the alert handshake completed, and thus the alert will eventually be signaled with a slight delay. + +Note that in both collision cases mentioned, the delay will be in the order of the handshake length, plus the constant amount of pause cycles between handshakes (2 sender cycles). + + +### Monitoring of Signal Integrity Issues + +All differential pairs are monitored for signal integrity issues, and if an encoding failure is detected, the receiver module asserts a signal integrity alert via `integ_fail_o`. In particular, this covers the following failure cases: + +1. The `alert_tx_i.alert_p/n` pair is not correctly encoded on the receiver side. +This can be directly flagged as an integrity failure on the receiver side. + +2. The `alert_rx_i.ping_p/n` or the `alert_rx_i.ack_p/n` pairs are not correctly encoded on the sender side. +This is signaled to the receiver by setting the `alert_tx_o.alert_p/n` wires to the same value, and that value will be continuously toggled. +This implicitly triggers a signal integrity alert on the receiver side. + +Some of these failure patterns are illustrated in the wave diagram below: + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p..............' }, + { name: 'alert_tx_o.alert_p', wave: '0.1...|0..10101' , node: '..a.......d'}, + { name: 'alert_tx_o.alert_n', wave: '1.....|....0101' }, + { name: 'alert_rx_i.ack_p', wave: '0.....|.1......' , node: '........c'}, + { name: 'alert_rx_i.ack_n', wave: '1.....|........' }, + { name: 'integ_fail_o', wave: '0...1.|0....1..' , node: '....b.......e'}, + ], + edge: [ + 'a~>b sigint issue detected', + 'c~>d', + 'd~>e indirect sigint issue detected', + ], + head: { + text: 'Detection of Signal Integrity Issues', + }, + foot: { + text: 'signal integrity issues occur at times 2 and 8; synchronizer latency is 2 cycles.', + tick: 0, + } +} +``` + +Note that if signal integrity failures occur during ping or alert handshaking, it is possible that the protocol state-machines lock up and the alert sender and receiver modules become unresponsive. However, the above mechanisms ensure that this will always trigger either a signal integrity alert or eventually a "pingfail" alert. + +### Skew on Asynchronous Differential Pairs + +Note that there is likely a (small) skew present within each differential pair of the signaling mechanism above. Since these pairs cross clock domain boundaries, it may thus happen that a level change appears in staggered manner after resynchronization, as illustrated below: + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p...........' }, + { name: 'diff_p', wave: '0.1.|.0.|..1' , node: '......a....d' }, + { name: 'diff_n', wave: '1.0.|..1|.0.' , node: '.......b..c.' }, + ], + edge: [ + 'a-~>b skew', + 'c-~>d skew' + ], + head: { + text: 'Skewed diff pair', + }, + foot: { + text: 'Correctly sampled diff pair at time 2; staggered samples at time 6-7 and 10-11', + tick: 0, + } +} +``` + +This behavior is permissible, but needs to be accounted for in the protocol logic. +Further, the skew within the differential pair should be constrained to be smaller than the shortest clock period in the system. +This ensures that the staggered level changes appear at most 1 cycle apart from each other. + + +### LFSR Timer + +The `ping_req_i` inputs of all signaling modules (`prim_alert_receiver`, `prim_esc_sender`) instantiated within the alert handler are connected to a central ping timer that alternatingly pings either an alert line or an escalation line after waiting for a pseudo-random amount of clock cycles. +Further, this ping timer also randomly selects a particular alert line to be pinged (escalation senders are always pinged in-order due to the [ping monitoring mechanism](#monitoring-of-pings-at-the-escalation-receiver-side) on the escalation side). +That should make it more difficult to predict the next ping occurrence based on past observations. + +The ping timer is implemented using an [LFSR-based PRNG of Galois type](../../../../ip/prim/doc/prim_lfsr.md). +This ping timer is reseeded with fresh entropy from EDN roughly every 500k cycles which corresponds to around 16 ping operations on average. +The LFSR is 32bits wide, but only 24bits of its state are actually being used to generate the random timer count and select the alert line to be pinged. +I.e., the 32bits first go through a fixed permutation function, and then bits `[23:16]` are used to determine which alert line to ping. +The random cycle count is created by OR'ing bits `[15:0]` with the constant `3'b100` as follows: + +``` +cycle_cnt = permuted[15:0] | 3'b100; +``` + +This constant DC offset introduces a minimum ping spacing of 4 cycles (1 cycle + margin) to ensure that the handshake protocols of the sender/receiver pairs work. + +After selecting one of the peripherals to ping, the LFSR timer waits until either the corresponding `*_ping_ok[]` signal is asserted, or until the programmable ping timeout value is reached. +In both cases, the LFSR timer proceeds with the next ping, but in the second case it will additionally raise a "pingfail" alert. +The ping enable signal remains asserted during the time where the LFSR counter waits. + +The timeout value is a function of the ratios between the alert handler clock and peripheral clocks present in the system, and can be programmed at startup time via the register [`PING_TIMEOUT_CYC_SHADOWED`](../data/alert_handler.hjson#ping_timeout_cyc_shadowed). + +Note that the ping timer directly flags a "pingfail" alert if a spurious "ping ok" message comes in that has not been requested. + + +As described in the programmers guide below, the ping timer has to be enabled explicitly. +Only alerts that have been *enabled and locked* will be pinged in order to avoid spurious alerts. +Escalation channels are always enabled, and hence will always be pinged once this mechanism has been turned on. + +In addition to the ping timer mechanism described above, the escalation receivers contain monitoring counters that monitor the liveness of the alert handler (described in more detail in [this section](#monitoring-of-pings-at-the-escalation-receiver-side). +This mechanism requires that the maximum wait time between escalation receiver pings is bounded. +To that end, escalation senders are pinged in-order every second ping operation (i.e., the wait time is randomized, but the selection of the escalation line is not). + +### Alert Receiving + +The alert handler module contains one alert receiver module (`prim_alert_receiver`) per sending module. +This receiver module has three outputs based upon the signaling of the input alert. +Primary is the signal of a received native alert, shown in the top-level diagram as `alert_triggered[]`. +Also generated are two other outputs, one that signals a differential encoding error (`alert_integ_fail[]`), and one that signals the receipt of a ping response (`alert_ping_ok[]`). +Each "triggered" alert received is sent into the classification block for individual configuration. +All of the `integ_fail` signals are OR'ed together to create one alert for classification. +The ping responses are fed to the LFSR timer, which determines whether a ping has correctly completed within the timeout window or not. + + +### Alert Classification and Interrupts + +Each of the incoming and local alert signals can be classified generically to one of four classes, or disabled for no classification at all. +These are the classes A, B, C, and D. +There is no pre-determined definition of a class, that is left to software. +But for guidance, software can consider that some alert types are similar to others; some alert types are more "noisy" than others (i.e. when triggered they stay on for long periods of time); some are more critical than others, etc. + +For each alert class (A-D), an interrupt is generally sent. +Like all other peripheral interrupts, there is a triad of registers: enable, status, test. +Thus like all other interrupts, software should handle the source of the interrupt (in this case, the original alert), then clear the state. +Since the interrupt class is disassociated with the original alert (due to the classification process), software can access cause registers to determine which alerts have fired since the last clearing. +Since alerts are expected to be rare (if ever) events, the complexity of dealing with multiple interrupts per class firing during the same time period should not be of concern. See the programming section on interrupt clearing. + +Each of the four interrupts can optionally trigger a timeout counter that triggers escalation if the interrupt is not handled and cleared within a certain time frame. +This feature is explained in more detail in the next subsection about escalation mechanisms. + +Note that an interrupt always fires once an alert has been registered in the corresponding class. +Interrupts are not dependent on escalation mechanisms like alert accumulation or timeout as described in the next subsection. + + +### Escalation Mechanisms + +There are two mechanisms per class that can trigger the corresponding escalation +protocol: + +1. The first consists of an accumulation counter that counts the amount of alert occurrences within a particular class. + An alert classified to class A indicates that on every received alert trigger, the accumulation counter for class A is incremented. + Note: since alerts are expected to be rare or never occur, the module does not attempt to count every alert per cycle, but rather all triggers per class are ORd before sending to the accumulation counter as an increment signal. + Once the threshold has been reached, the next occurrence triggers the escalation escalation protocol for this particular class. + The counter is a saturation counter, meaning that it will not wrap around once it hits the maximum representable count. + This mechanism has two associated CSRs: + + - Accumulation max value. + This is the total number (sum of all alerts classified in this group) of alerts required to enter escalation phase (see below). + Example register is [`CLASSA_ACCUM_THRESH_SHADOWED`](../data/alert_handler.hjson#classa_accum_thresh_shadowed). + - Current accumulation register. + This clearable register indicates how many alerts have been accumulated to date. + Software should clear before it reaches the accumulation setting to avoid escalation. + Example register is [`CLASSA_ACCUM_CNT`](../data/alert_handler.hjson#classa_accum_cnt). + +2. The second way is an interrupt timeout counter which triggers escalation if an alert interrupt is not handled within the programmable timeout window. + Once the counter hits the timeout threshold, the escalation protocol is triggered. + The corresponding CSRs are: + + - Interrupt timeout value in cycles [`CLASSA_TIMEOUT_CYC_SHADOWED`](../data/alert_handler.hjson#classa_timeout_cyc_shadowed). + The interrupt timeout is disabled if this is set to 0 (default). + - The current interrupt timeout value can be read via [`CLASSA_ESC_CNT`](../data/alert_handler.hjson#classa_esc_cnt) if [`CLASSA_STATE`](../data/alert_handler.hjson#classa_state) is in the `Timeout` state. + Software should clear the corresponding interrupt state bit [`INTR_STATE.CLASSA`](../data/alert_handler.hjson#intr_state) before the timeout expires to avoid escalation. + +Technically, the interrupt timeout feature (2. above) is implemented using the same counter used to time the escalation phases. +This is possible since escalation phases or interrupt timeout periods are non-overlapping (escalation always takes precedence should it be triggered). + + +### Programmable Escalation Protocol + +There are four output escalation signals, 0, 1, 2, and 3. +There is no predetermined definition of an escalation signal, that is left to the top-level integration. +Examples could be processor Non Maskable Interrupt (NMI), privilege lowering, secret wiping, chip reset, etc. +Typically the assumption is that escalation level 0 is the first to trigger, followed by 1, 2, and then 3, emulating a "fuse" that is lit that can't be stopped once the first triggers (this is however not a requirement). +See register section for discussion of counter clearing and register locking to determine the finality of accumulation +triggers. + +Each class can be programmed with its own escalation protocol. +If one of the two mechanisms described above fires, a timer for that particular class is started. +The timer can be programmed with up to 4 delays (e.g., [`CLASSA_PHASE0_CYC`](../data/alert_handler.hjson#classa_phase0_cyc)), each representing a distinct escalation phase (0 - 3). +Each of the four escalation severity outputs (0 - 3) are by default configured to be asserted during the corresponding phase, e.g., severity 0 in phase 0, severity 1 in phase 1, etc. +However, this mapping can be freely reassigned by modifying the corresponding enable/phase mappings (e.g., [`CLASSA_CTRL_SHADOWED.E0_MAP`](../data/alert_handler.hjson#classa_ctrl_shadowed) for enable bit 0 of class A). +This mapping will be locked in together with the alert enable configuration after initial configuration. + +SW can stop a triggered escalation protocol by clearing the corresponding escalation counter (e.g., [`CLASSA_ESC_CNT`](../data/alert_handler.hjson#classa_esc_cnt)). +Protection of this clearing is up to software, see the register control section that follows for [`CLASSA_CTRL_SHADOWED.LOCK`](../data/alert_handler.hjson#classa_ctrl_shadowed). + +It should be noted that each of the escalation phases have a duration of at least 1 clock cycle, even if the cycle count of a particular phase has been +set to 0. + +The next waveform shows the gathering of alerts of one class until eventually the escalation protocol is engaged. +In this diagram, two different alerts are shown for class A, and the gathering and escalation configuration values are shown. + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p...................' }, + { name: 'CLASSA_ACCUM_THRESH_SHADOWED', wave: '2...................', data: ['15'] }, + { name: 'CLASSA_PHASE0_CYC_SHADOWED', wave: '2...................', data: ['1e3 cycles'] }, + { name: 'CLASSA_PHASE1_CYC_SHADOWED', wave: '2...................', data: ['1e4 cycles'] }, + { name: 'CLASSA_PHASE2_CYC_SHADOWED', wave: '2...................', data: ['1e5 cycles'] }, + { name: 'CLASSA_PHASE3_CYC_SHADOWED', wave: '2...................', data: ['1e6 cycles'] }, + { name: 'alert_triggered[0]', wave: '010|.10.............' }, + { name: 'alert_triggered[1]', wave: '0..|10..............' }, + { name: 'CLASSA_ACCUM_CNT', wave: '33.|33..............', data: ['0', '1','15','16'] }, + { name: 'irq_o[0]', wave: '01.|................' }, + { name: 'CLASSA_STATE', wave: '3..|.3|3.|3..|3..|3.', data: ['Idle', ' Phase0','Phase1','Phase2','Phase3','Terminal'] }, + { name: 'CLASSA_ESC_CNT', wave: '3..|.3|33|333|333|3.', data: ['0','1','1','2','1','2','3','1','2','3','0'] }, + { name: 'esc_tx_o.esc_p[0]', wave: '0..|.1|.0...........', node: '.....a..b' }, + { name: 'esc_tx_o.esc_n[0]', wave: '1..|.0|.1...........' }, + { name: 'esc_tx_o.esc_p[1]', wave: '0..|..|1.|.0........', node: '.......c...d' }, + { name: 'esc_tx_o.esc_n[1]', wave: '1..|..|0.|.1........' }, + { name: 'esc_tx_o.esc_p[2]', wave: '0..|.....|1..|.0....', node: '..........e....f' }, + { name: 'esc_tx_o.esc_n[2]', wave: '1..|.....|0..|.1....' }, + { name: 'esc_tx_o.esc_p[3]', wave: '0..|.........|1..|.0', node: '..............g....h' }, + { name: 'esc_tx_o.esc_n[3]', wave: '1..|.........|0..|.1' }, + ], + edge: [ + 'a->b 1e3 + 1 cycles', + 'c->d 1e4 + 1 cycles', + 'e->f 1e5 + 1 cycles', + 'g->h 1e6 + 1 cycles', + ], + head: { + text: 'Alert class gathering and escalation triggers (fully synchronous case)', + }, + foot: { + text: 'alert class A gathers 16 alerts, triggers first escalation, followed by three more', + tick: 0, + } +} +``` + +In this diagram, the first alert triggers an interrupt to class A. +The assumption is that the processor is wedged or taken over, in which case it does not handle the interrupt. +Once enough interrupts gather (16 in this case), the first escalation phase is entered, followed by three more (each phase has its own programmable length). +Note that the accumulator threshold is set to 15 in order to trigger on the 16th occurrence. +If escalation shall be triggered on the first occurrence within an alert class, the accumulation threshold shall be set to 0. +Also note that it takes one cycle to activate escalation and enter phase 0. + +The next wave shows a case where an interrupt remains unhandled and hence the interrupt timeout counter triggers escalation. + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p.....................' }, + { name: 'CLASSA_TIMEOUT_CYC_SHADOWED', wave: '2.....................', data: ['1e4 cycles'] }, + { name: 'alert_triggered[0]', wave: '010.|.................' }, + { name: 'irq_o[0]', wave: '01..|.................', node: '.a..|.b' }, + { name: 'CLASSA_ESC_STATE', wave: '33..|.3|3.|3..|3...|3.', data: ['Idle', 'Timeout',' Phase0','Phase1','Phase2','Phase3','Terminal'] }, + { name: 'CLASSA_ESC_CNT', wave: '3333|33|33|333|3333|3.', data: ['0', '1','2','3','1e4','1','1','2','1','2','3','1','2','3','4','0'] }, + { name: 'esc_tx_o.esc_p[0]', wave: '0...|.1|.0............' }, + { name: 'esc_tx_o.esc_n[0]', wave: '1...|.0|.1............' }, + { name: 'esc_tx_o.esc_p[1]', wave: '0...|..|1.|.0.........' }, + { name: 'esc_tx_o.esc_n[1]', wave: '1...|..|0.|.1.........' }, + { name: 'esc_tx_o.esc_p[2]', wave: '0...|.....|1..|.0.....' }, + { name: 'esc_tx_o.esc_n[2]', wave: '1...|.....|0..|.1.....' }, + { name: 'esc_tx_o.esc_p[3]', wave: '0...|.........|1...|.0' }, + { name: 'esc_tx_o.esc_n[3]', wave: '1...|.........|0...|.1' }, + ], + edge: [ + 'a->b 1e4 cycles', + ], + head: { + text: 'Escalation due to an interrupt timeout (fully synchronous case)', + }, + foot: { + text: 'alert class A triggers an interrupt and the timeout counter, which eventually triggers escalation after 1e4 cycles.', + tick: 0, + } +} +``` + +It should be noted here that the differential escalation signaling protocol distinguishes 'true' escalation conditions from mere pings by encoding them as pulses that are N + 1 cycles long. +This is reflected in the two wave diagrams above. +Refer to the subsequent section on escalation signaling for more details. + +### Escalation Signaling + +For each of the four escalation severities, the alert handler instantiates a `prim_esc_sender` module and each of the four escalation countermeasures instantiates an `prim_esc_receiver` module. +The signaling mechanism has similarities with the alert signaling mechanism - but it is a fully synchronous protocol. +Hence, it must be ensured at the top-level that all escalation sender and receiver modules are using the same clock and reset +signals. + +As illustrated in the following block diagram, a sender-receiver pair is connected with two differential lines, one going from sender to receiver and the other going from receiver to sender. + +![Alert Handler Escalation RXTX](alert_handler_escalation_rxtx.svg) + +Upon receiving an escalation enable pulse of width N > 0 at the `esc_req_i` input, the escalation sender encodes that signal as a differential pulse of width N+1 on `esc_tx.esc_p/n`. +The receiver decodes that message and asserts the `esc_req_o` output after one cycle of delay. +Further, it acknowledges the receipt of that message by continuously toggling the `esc_rx.resp_p/n` signals as long as the escalation signal is asserted. +Any failure to respond correctly will trigger a `integ_fail_o` alert, as illustrated below: + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p..................' }, + { name: 'ping_req_i', wave: '0........|.........' }, + { name: 'ping_ok_o', wave: '0........|.........' }, + { name: 'integ_fail_o', wave: '0........|..1010...' , node: '............b.d' }, + { name: 'ping_fail_o', wave: '0........|.........' }, + { name: 'esc_req_i', wave: '01....0..|.1....0..' }, + { name: 'esc_rx_i/o.resp_p', wave: '0.101010.|.........', node: '............a.c' }, + { name: 'esc_rx_i/o.resp_n', wave: '1.010101.|.........' }, + { name: 'esc_tx_o/i.esc_p', wave: '01.....0.|.1.....0.' }, + { name: 'esc_tx_o/i.esc_n', wave: '10.....1.|.0.....1.' }, + { name: 'esc_req_o', wave: '0.1....0.|..?....0.'}, + ], + edge: [ + 'a~>b missing response', + 'c~>d', + ], + head: { + text: 'Escalation signaling and response', + }, + foot: { + text: 'escalation enable pulse shown at input sender at time 1 and 11; missing response and repeated integfail at time 12 and 14', + tick: 0, + } +} +``` + +Further, any differential signal mismatch on both the `esc_tx_i.esc_p/n` and `esc_rx_i.resp_p/n` lines will trigger an `integ_fail_o` alert. +Mismatches on `esc_rx_i.resp_p/n` can be directly detected at the sender. +Mismatches on the `esc_tx_i.esc_p/n` line will be signaled back to the sender by setting both the positive and negative response wires to the same value - and that value is being toggled each cycle. +This implicitly triggers a signal integrity alert on the sender side. +In addition to that, a signal integrity error on the `esc_tx_i.esc_p/n` lines will lead to assertion of the `esc_req_o` output, since it cannot be guaranteed that the back signalling mechanism always works when the sender / receiver pair is being tampered with. + +This back-signaling mechanism can be leveraged to fast-track escalation and use another countermeasure in case it is detected that a particular escalation signaling path has been tampered with. + +Some signal integrity failure cases are illustrated in the wave diagram below: + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p...........' }, + { name: 'ping_req_i', wave: '0....|......' }, + { name: 'ping_ok_o', wave: '0....|......' }, + { name: 'integ_fail_o', wave: '0.1.0|.1....' , node: '..b....e' }, + { name: 'esc_req_i', wave: '0....|......' }, + { name: 'esc_rx_i.resp_p', wave: '0.1.0|..1010', node: '..a..' }, + { name: 'esc_rx_i.resp_n', wave: '1....|.01010', node: '.......d' }, + { name: 'esc_tx_i.esc_p', wave: '0....|1.....', node: '......c..' }, + { name: 'esc_tx_i.esc_n', wave: '1....|......' }, + { name: 'esc_req_o', wave: '0....|1.....'}, + ], + edge: [ + 'a~>b', + 'c->d', + 'd->e', + ], + head: { + text: 'possible signal integrity failure cases', + }, + foot: { + text: 'direct signal integrity failure at time 2; indirect failure at time 6', + tick: 0, + } +} +``` + + +### Ping Testing of the Escalation Signals + + +Similarly to the alert signaling scheme, the escalation signaling lines can be pinged / line tested in order to test whether the escalation receiver has been tampered with. +This is achieved by asserting `ping_req_i` at the escalation sender module. +A ping request is encoded as a single cycle pulse on the `esc_tx_o.esc_p/n` outputs. +Hence, the receiver module will not decode this single cycle pulse as an escalation enable message, but it will respond to it with a "1010" pattern on the `esc_rx_i.resp_p/n` lines. +The escalation sender module will assert `ping_ok_o` if that pattern is received correctly after one cycle of latency. +Otherwise, the escalation sender will first assert `integ_fail_o` later, after the programmable ping timeout is reached, the LFSR timer will raise a "pingfail" alert. +The `integ_fail_o` triggers in this case since "no ping response" and "wrong ping response" are ambiguous in this setting, and it has been decided to not suppress integrity failures when expecting a ping response. + +This mechanism is illustrated below from the viewpoint of the sender module. + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p..............' }, + { name: 'ping_req_i', wave: '01....0|.1.....' , node: '.a'}, + { name: 'ping_ok_o', wave: '0....10|.......' , node: '.....e....g'}, + { name: 'integ_fail_o', wave: '0......|..10101' }, + { name: 'esc_req_i', wave: '0......|.......' }, + { name: 'esc_rx_i.resp_p', wave: '0.1010.|.......' , node: '..c..d....f'}, + { name: 'esc_rx_i.resp_n', wave: '1.0101.|.......' }, + { name: 'esc_tx_o.esc_p', wave: '010....|.10....' , node: '.b'}, + { name: 'esc_tx_o.esc_n', wave: '101....|.01....' }, + ], + edge: [ + 'a->b', + 'b->c', + 'd->e correct response', + 'f->g missing response', + ], + head: { + text: 'ping testing of escalation lines', + }, + foot: { + text: 'ping trig at sender input at time 1 and 9; correct response at time 5; missing response at time 10', + tick: 0, + } +} +``` + +Note that the escalation signal always takes precedence, and the `ping_req_i` will just be acknowledged with `ping_ok_o` in case `esc_req_i` is already asserted. +An ongoing ping sequence will be aborted immediately. + +Another thing to note is that the ping and escalation response sequences have to start _exactly_ one cycle after either a ping or escalation event has been signaled. +Otherwise the escalation sender will assert `integ_fail_o` immediately. + +### Monitoring of Pings at the Escalation Receiver Side + +Escalation receivers contain a mechanism to monitor the liveness of the alert handler itself. +In particular, the receivers passively monitor the ping requests sent out by the alert handler using a timeout counter. +If ping requests are absent for too long, the corresponding escalation action will be automatically asserted until reset. + +The monitoring mechanism builds on top of the following properties of the alert handler system: +1. the ping mechanism can only be enabled, but not disabled. +This allows us to start the timeout counter once the first ping request arrives at a particular escalation receiver. + +2. the escalation receivers are in the same clock/reset domain as the alert handler. +This ensures that we are seeing the same clock frequency, and the mechanism is properly reset together with the alert handler logic. + +3. the maximum cycle count between subsequent pings on the same escalation line is bounded, even though the wait counts are randomized. +This allows us to compute a safe and fixed timeout threshold based on design constants. + + +### Low-power Management of Alert Channels + +Due to the various clock and reset domains in the OpenTitan system, the alert handler ping mechanism needs to have additional logic to deal with alert senders that are either held in reset, or that are clock gated. +This is needed to ensure that no false alarms are produced by the ping mechanism when an alert channel (sender / receiver pair) does not respond due to the sender being either in reset or clock gated. + +Since the FSMs associated with an alert channel may end up in an inconsistent state when the sender is reset or gated while an asynchronous event handshake is in progress, this logic also needs to be able to re-initialize affected alert channels whenever the channels comes back from reset / clock gated state. + +#### Assumptions + +The following diagram shows a typical arrangement of alert sender (TX) and receiver (RX) pairs. + +![Alert Handler Low-Power Overview](alert_handler_lp_overview.svg) + +It is assumed that: + +1. The alert handler clock domain cannot be gated by SW. + This means that this clock domain is only ever disabled as part of the power-down sequence of the corresponding power domain. +2. The alert senders are in general located within different clock and reset domains than the alert receivers within the alert handler, and thus use the asynchronous event handshake mode. +3. Some alert senders may be located in an always-on (AON) power domain, within different clock and reset groups than the alert handler. +4. The alert handler may be located in an non-AON power domain, and may thus undergo a reset cycle where it cannot be guaranteed that all alert senders are reset as well (i.e., some alert senders may retain their state). + +Further, we assume that we can get the following side-band information from the clock and reset managers in the system: + +- All relevant reset signals pertaining to alert sender domains +- All relevant clock enable signals pertaining to alert sender domains + +#### Scenarios + +With the assumptions above, the following two problematic scenarios can occur. + +##### Alert Handler in Reset + +It may happen that the alert handler is reset while some alert senders (e.g. those located in the AON domain) are not. +In general, if the associated alert channels are idle during an alert handler reset cycle, no problems arise. + +However, if an alert channel is reset while it is handling a ping request or an alert event, the sender / receiver FSMs may end up in an inconsistent state upon deassertion of the alert handler reset. +This can either lead to spurious alert or ping events, or a completely locked up alert channel which will be flagged eventually by the ping mechanism. + +##### Alert Sender in Reset or Clock-gated + +If any of the alert senders is either put into reset or its clock is disabled while the alert handler is operational, the ping mechanism inside the alert handler will eventually report a ping failure because of missing ping responses from the affected alert channel(s). + +Further, if the alert sender is reset while the corresponding alert channel is handling a ping request or an alert event, the sender / receiver FSMs may end up in an inconsistent state after reset deassertion. + +#### Employed Solution + +As elaborated before, the side effects of resetting / clock gating either the alert handler or any of the alert senders are inconsistent FSM states, leading to locked up alert channels, or spurious alert or ping events. +To address these issues, we have to: + +1. make sure spurious events (alert and ping_ok outputs of the alert receivers) are suppressed if an alert channel is clock gated or in reset, +2. provide a mechanism for resetting an alert channel to an operational state once the associated clock is re-enabled, or the associated reset is released, +3. trigger this reset mechanism on all alert channels whenever the alert handler itself has been reset. + +To attain this, the idea is to make use of side-band information available from the clock and reset managers to detect whether an alert channel (or a group of alert channels with the same clock and reset on the sender side) has to be put into a low-power state. +In the following we will refer to such a clock / reset domain grouping as a low-power group (LPG). + +The mechanism is illustrated below for a single LPG (in practice, this logic is replicated for each LPG that is identified in the system): + +![Alert Handler LPG Ctrl](alert_handler_lpg_ctrl.svg) + +The clock gating enable (`lpg_cg_en`) and reset enable (`lpg_rst_en`) indications are routed as multibit signals to the alert handler, where they are synchronized to the alert handler clock and logically combined using an OR function to form a combined low-power indication signal that is multibit encoded. + +This multibit indication signal is then routed to all alert receivers, where it is used to trigger re-initialization of each alert channel, and bypass the ping requests from the ping mechanism. + +To that end, two extra *init states* are added to the alert receiver FSMs to perform this in-band reset, as indicated in the state diagram below: + +![Alert Handler Receiver FSM](alert_handler_receiver_fsm.svg) + +Whenever the `init_trig` multibit signal of an LPG is asserted, all corresponding sender FSMs are moved into the `InitReq` state. +In that state, the alert receivers immediately acknowledge ping requests from the ping mechanism, and ignore alert events from the sender side. +In addition to that, the receivers intentionally place a signal integrity error onto the `ping_p` / `ping_n`, `ack_p` / `ack_n` lines going from receivers to the senders. +This causes the senders to 1) move into the signal integrity error state, and 2) respond by placing a signal integrity error onto the `alert_p` / `alert_n` lines, which serves as an initialization "acknowledge" signal in this case. +Since the sender FSMs fall back into the `Idle` state once the signal integrity error disappears, this procedure essentially implements an in-band reset mechanism with an acknowledgement handshake that can be used to determine whether the reset has been successful. + +#### Implementation Aspects + +##### Ping Mechanism Bypass + +Note that the ping bypass mechanism is to be implemented in a way that pings are only ack'ed immediately if 1) the FSM is in the `InitReq` state, and 2) the `init_trig` signal is still asserted. + +This allows to subject the initialization process of each alert channel to the ping mechanism for channels that are recovering from a reset or clock gated cycle on the sender side. +I.e., alert channels that get stuck during the initialization process can be detected by the ping mechanism since ping requests are not immediately ack'ed anymore once `init_trig` is deasserted. + +##### FSM Encoding + +Since there are many alert channels in the design, the receiver and sender FSMs themselves are not sparsely encoded. +Instead, we rely on the ping mechanism to detect alert channels that are in a bad state. +The specific implementation of the ping bypass mentioned in the previous subsection ensures that the ping mechanism can also be used to monitor the initialization sequence of alert channels. + +##### Latency / Skew Considerations + +Due to asynchronous transitions and different path latencies in the system, a change in reset or clock gating state will experience a different latency through the alert channels than through the indication signals (`rst_n` and `clk_en`) that are connected to the low-power control logic. + +It is consequently possible for a group of alert senders to already be in reset or clock gated state, while the corresponding LPG logic does not yet know about this state change - and vice versa. + +In practice, this means that ping requests may be pending for several cycles until the LPG logic detects a reset or clock-gated condition and disables the corresponding alert channel(s). +Fortunately, such delay can be tolerated by setting the ping timeout to a sufficiently large value (see [`CLASSA_TIMEOUT_CYC_SHADOWED`](../data/alert_handler.hjson#classa_timeout_cyc_shadowed)). + +As for alert events, this latency difference should not pose a problem. +Alert events may get stuck in the alert sender due to a reset or clock-gated condition - but this is to be expected. + +##### Integration Considerations + +Note that due to the aforementioned latency tolerance built into the ping timer, it is permissible to connect **any** reset or clock enable indication signal from the relevant clock group to the LPG logic. +I.e., the only requirement is that the indication signals are logically related to the resets and clocks routed to the alert senders, and that the skew between reset / clock state changes and the indication signals is bounded. + +The topgen script is extended so that it can identify all LPGs and the associated alert channels. +This information is then used to parameterize the alert handler design, and make the necessary top-level connections from the reset and clock management controllers to the alert handler. + +### Hardening Against Glitch Attacks + +In addition to the differential alert and escalation signalling scheme, the internal state machines and counters are hardened against glitch attacks as described bellow: + +1. Ping Timer: + - The FSM is sparsely encoded. + - The LFSR and the counter are duplicated. + - If the FSM or counter are glitched into an invalid state, all internal ping fail alerts will be permanently asserted. + +2. Escalation Timers: + - The escalation timer FSMs are sparsely encoded. + - The escalation timer counters are duplicated. + - The escalation accumulators are duplicated. + - If one of these FSMs, counters or accumulators are glitched into an invalid state, all escalation actions will be triggered and the affected FSM goes into a terminal `FsmError` state. + +3. CSRs: + - Critical configuration CSRs are shadowed. + - The shadow CSRs can trigger additional internal alerts for CSR storage and update failures. + These internal alerts are fed back into the alert classifier in the same manner as the ping and integrity failure alerts. + +4. LPGs: + - Clock-gated and reset-asserted indication signals that are routed from clock and reset managers to the alert handler are encoded with multibit signals. diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/README.md b/hw/top_darjeeling/ip_autogen/alert_handler/dv/README.md new file mode 100644 index 0000000000000..f747f76b52c60 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/README.md @@ -0,0 +1,119 @@ +# ALERT_HANDLER DV document + +## Goals +* **DV** + * Verify all ALERT_HANDLER IP features by running dynamic simulations with a SV/UVM based testbench + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules + * Verify transmitter and receiver pairs for alert (/hw/ip/prim/dv/prim_alert) and escalation (/hw/ip/prim/dv/prim_esc) via direct stimulus. +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench + * Verify transmitter and receiver pairs for alert and escalator + * Verify alert_handler_esc_timer and alert_handler_ping_timer + +## Current status +* [Design & verification stage](../../../README.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/top_earlgrey/ip_autogen/alert_handler/dv/latest/report.html) + +## Design features +For detailed information on ALERT_HANDLER design features, please see the [ALERT_HANDLER HWIP technical specification](../README.md). + +## Testbench architecture +ALERT_HANDLER testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +### Block diagram +![Block diagram](./doc/tb.svg) + +### Top level testbench +Top level testbench is located at `hw/ip/alert_handler/dv/tb/tb.sv`. It instantiates the ALERT_HANDLER DUT module `hw/ip/alert_handler/rtl/alert_handler.sv`. +In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [TileLink host interface](../../../../dv/sv/tl_agent/README.md) +* ALERT_HANDLER IOs +* Alerts and escalations([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md)) +* Interrupts ([`pins_if`](../../../../dv/sv/common_ifs/README.md#pins_if)) + +The alert_handler testbench environment can be reused in chip level testing. + +### Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +### Global types & methods +All common types and methods defined at the package level can be found in +`alert_handler_env_pkg`. Some of them in use are: +```systemverilog + parameter uint NUM_MAX_ESC_SEV = 8; +``` + +### TL_agent +ALERT_HANDLER testbench instantiates (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md) +which provides the ability to drive and independently monitor random traffic via +TL host interface into ALERT_HANDLER device. + +### ALERT_ESC Agent +[ALERT_ESC agent](../../../../dv/sv/alert_esc_agent/README.md) is used to drive and monitor transmitter and receiver pairs for the alerts and escalators. +Alert_handler DUT includes alert_receivers and esc_senders, so the alert_esc agent will drive output signals of the alert_senders and esc_receivers. + +### UVM RAL Model +The ALERT_HANDLER RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md). + +### Stimulus strategy +#### Test sequences +All test sequences reside in `hw/ip/alert_handler/dv/env/seq_lib`. +The `alert_handler_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. +All test sequences are extended from `alert_handler_base_vseq`. +It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. +Some of the most commonly used tasks / functions are as follows: +* alert_handler_init: Configure alert_handler DUT by writing to `intr_en`, `alert_en_shadowed_*`, `alert_class_shadowed_*`, `loc_alert_en_shadowed_*`, `loc_alert_class_shadowed_*` registers. +* drive_alert: Drive alert_tx signal pairs through `alert_sender_driver`. +* drive_esc_rsp: Drive esc_rx signal pairs through `esc_receiver_driver`. +* read_ecs_status: Readout registers that reflect escalation status, including `classa/b/c/d_accum_cnt`, `classa/b/c/d_esc_cnt`, and `classa/b/c/d_state`. +* wait_alert_handshake_done: Wait for alert_rx/tx handshake to finish. If the alert's low-power-group(LPG) is enabled, immediately return. +* wait_esc_handshake_done: Wait for esc_rx/tx handshake to finish by reading `class*_state` registers and check esc_rx/tx signals. +* set_alert_lpg: Given alert index, find the linked LPG group and enabled the LPG group by driving `lpg_cg_en` or `lpg_rst_en` to Mubi4True. +* run_esc_rsp_seq_nonblocking: A non-blocking sequence to drive `esc_tx` when received escalation or escalation-ping requests. +* run_alert_ping_rsp_seq_nonblocking: A non-blocking sequence to drive `alert_rx` when received alert-ping requests. + +#### Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The detailed covergroups are documented under alert_handler [testplan](#testplan). + +### Self-checking strategy +#### Scoreboard +The `alert_handler_scoreboard` is primarily used for end to end checking. +It creates the following analysis ports to retrieve the data monitored by corresponding interface agents: +* tl_a_chan_fifo: tl address channel +* tl_d_chan_fifo: tl data channel +* alert_fifo: An array of `alert_fifo` that connects to corresponding alert_monitors +* esc_fifo: An array of `esc_fifo` that connects to corresponding esc_monitors + +Alert_handler scoreboard monitors all valid CSR registers, alert handshakes, and escalation handshakes. +To ensure certain alert, interrupt, or escalation signals are triggered at the expected time, the alert_handler scoreboard implemented a few counters: +* intr_cnter_per_class[NUM_ALERT_HANDLER_CLASSES]: Count number of clock cycles that the interrupt bit stays high. + If the stored number is larger than the `timeout_cyc` registers, the corresponding escalation is expected to be triggered +* accum_cnter_per_class[NUM_ALERT_HANDLER_CLASSES]: Count number of alerts triggered under the same class. + If the stored number is larger than the `accum_threshold` registers, the corresponding escalation is expected to be triggered +* esc_cnter_per_signal[NUM_ESC_SIGNALS]: Count number of clock cycles that each escalation signal stays high. + Compare the counter against `phase_cyc` registers + +The alert_handler scoreboard is parameterized to support different number of classes, alert pairs, and escalation pairs. + +#### Assertions +* TLUL assertions: The `tb/alert_handler_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. +* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. + +## Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/$CHIP/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson -i alert_handler_smoke +``` +In this run command, $CHIP can be top_earlgrey, etc. + +## Testplan +[Testplan](../data/alert_handler_testplan.hjson) diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim.core b/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim.core new file mode 100644 index 0000000000000..702f7bb9f0d81 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim.core @@ -0,0 +1,39 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_alert_handler_sim:0.1 +description: "ALERT_HANDLER DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:opentitan:top_darjeeling_alert_handler:0.1 + file_type: systemVerilogSource + + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:alert_handler_tb + - lowrisc:dv:alert_handler_cov + - lowrisc:opentitan:top_darjeeling_alert_handler_sva:0.1 + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: alert_handler + ip_hjson: ../data/alert_handler.hjson + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + generate: + - ral + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson b/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson new file mode 100644 index 0000000000000..fa7e5390710ae --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson @@ -0,0 +1,153 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: alert_handler + + // Top level dut name (sv module). + dut: alert_handler + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:opentitan:top_darjeeling_alert_handler_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/alert_handler_testplan.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"] + + // Add additional tops for simulation. + sim_tops: ["alert_handler_bind", + "alert_handler_cov_bind", + "sec_cm_prim_sparse_fsm_flop_bind", + "sec_cm_prim_count_bind", + "sec_cm_prim_double_lfsr_bind", + "sec_cm_prim_onehot_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + overrides: [ + { + name: cover_reg_top_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/top_earlgrey/ip_autogen/alert_handler/dv/cov/alert_handler_cover_reg_top.cfg+{dv_root}/tools/vcs/common_cov_excl.cfg" + } + ] + + // Add ALERT_HANDLER specific exclusion files. + vcs_cov_excl_files: ["{self_dir}/cov/alert_handler_cov_excl.el", + "{self_dir}/cov/alert_handler_cov_unr.el"] + + // Default UVM test and seq class name. + uvm_test: alert_handler_base_test + uvm_test_seq: alert_handler_base_vseq + + // List of test specifications. + tests: [ + { + name: alert_handler_smoke + uvm_test_seq: alert_handler_smoke_vseq + } + + { + name: alert_handler_random_alerts + uvm_test_seq: alert_handler_random_alerts_vseq + } + + { + name: alert_handler_random_classes + uvm_test_seq: alert_handler_random_classes_vseq + } + + { + name: alert_handler_esc_intr_timeout + uvm_test_seq: alert_handler_esc_intr_timeout_vseq + } + + { + name: alert_handler_esc_alert_accum + uvm_test_seq: alert_handler_esc_alert_accum_vseq + } + + { + name: alert_handler_sig_int_fail + uvm_test_seq: alert_handler_sig_int_fail_vseq + } + + { + name: alert_handler_entropy + uvm_test_seq: alert_handler_entropy_vseq + run_opts: ["+test_timeout_ns=1_000_000_000"] + } + + { + name: alert_handler_ping_timeout + uvm_test_seq: alert_handler_ping_timeout_vseq + run_opts: ["+test_timeout_ns=1_000_000_000"] + } + + { + name: alert_handler_lpg + uvm_test_seq: alert_handler_lpg_vseq + run_opts: ["+test_timeout_ns=1_000_000_000"] + } + + { + name: alert_handler_lpg_stub_clk + uvm_test_seq: alert_handler_lpg_stub_clk_vseq + run_opts: ["+test_timeout_ns=1_000_000_000"] + } + + { + name: alert_handler_entropy_stress + uvm_test_seq: alert_handler_entropy_stress_vseq + // This sequence forces signal `wait_cyc_mask_i` to a much smaller value. + // So all the timings are not accurate and we need to disable the scb. + run_opts: ["+en_scb=0"] + reseed: 20 + } + + { + name: alert_handler_stress_all + run_opts: ["+test_timeout_ns=15_000_000_000"] + } + + { + name: alert_handler_shadow_reg_errors_with_csr_rw + run_opts: ["+test_timeout_ns=500_000_000"] + run_timeout_mins: 120 + } + + { + name: alert_handler_alert_accum_saturation + uvm_test_seq: alert_handler_alert_accum_saturation_vseq + // This is a direct sequence that forces the accum_cnt to a large number, so does not support + // scb checkings. + run_opts: ["+en_scb=0"] + reseed: 20 + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["alert_handler_smoke"] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cov.core b/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cov.core new file mode 100644 index 0000000000000..332e19dd13b16 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cov.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:alert_handler_cov" +description: "ALERT_HANDLER cov bind files" +filesets: + files_dv: + depend: + - lowrisc:ip:alert_handler_component # import alert_pkg + - lowrisc:dv:dv_utils + files: + - alert_handler_cov_bind.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cov_bind.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cov_bind.sv new file mode 100644 index 0000000000000..892a57c22da91 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cov_bind.sv @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Binds ALERT_HANDLER functional coverage interafaces to the top level ALERT_HANDLER module. + +module alert_handler_cov_bind; + import alert_pkg::*; + + bind alert_handler cip_mubi_cov_wrapper#(.NumMubis(NLpg)) u_lpg_cg_en_cov_if ( + .rst_ni (rst_ni), + .mubis (lpg_cg_en_i) + ); + + bind alert_handler cip_mubi_cov_wrapper#(.NumMubis(NLpg)) u_lpg_rst_en_cov_if ( + .rst_ni (rst_ni), + .mubis (lpg_rst_en_i) + ); +endmodule : alert_handler_cov_bind diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cov_excl.el b/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cov_excl.el new file mode 100644 index 0000000000000..fb759d630740d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cov_excl.el @@ -0,0 +1,163 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//================================================== +// This file contains the Excluded objects +// Generated By User: chencindy +// Format Version: 2 +// Date: Wed Nov 30 12:30:55 2022 +// ExclMode: default +//================================================== +CHECKSUM: "951561765 3328643058" +INSTANCE: tb.dut.u_ping_timer +Fsm state_q "2842986776" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition AlertPingSt->FsmErrorSt "369->366" +Fsm state_q "2842986776" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition EscWaitSt->FsmErrorSt "182->366" +Fsm state_q "2842986776" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition EscPingSt->FsmErrorSt "29->366" +Fsm state_q "2842986776" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition InitSt->FsmErrorSt "203->366" +CHECKSUM: "3358687906 2811042798" +INSTANCE: tb.dut.gen_classes[0].u_esc_timer +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase1St->FsmErrorSt "340->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase2St->FsmErrorSt "25->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase3St->FsmErrorSt "609->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TerminalSt->FsmErrorSt "895->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TimeoutSt->FsmErrorSt "38->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase0St->FsmErrorSt "901->488" +CHECKSUM: "3358687906 2811042798" +INSTANCE: tb.dut.gen_classes[1].u_esc_timer +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase0St->FsmErrorSt "901->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TerminalSt->FsmErrorSt "895->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TimeoutSt->FsmErrorSt "38->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase3St->FsmErrorSt "609->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase2St->FsmErrorSt "25->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase1St->FsmErrorSt "340->488" +CHECKSUM: "3358687906 2811042798" +INSTANCE: tb.dut.gen_classes[2].u_esc_timer +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase0St->FsmErrorSt "901->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TimeoutSt->FsmErrorSt "38->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TerminalSt->FsmErrorSt "895->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase3St->FsmErrorSt "609->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase2St->FsmErrorSt "25->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase1St->FsmErrorSt "340->488" +CHECKSUM: "3358687906 2811042798" +INSTANCE: tb.dut.gen_classes[3].u_esc_timer +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase1St->FsmErrorSt "340->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase2St->FsmErrorSt "25->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase3St->FsmErrorSt "609->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TerminalSt->FsmErrorSt "895->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TimeoutSt->FsmErrorSt "38->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase0St->FsmErrorSt "901->488" +CHECKSUM: "1268953672 3214085926" +INSTANCE: tb.dut +ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000." +Toggle crashdump_o.class_esc_cnt [1][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt" +ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000." +Toggle crashdump_o.class_esc_cnt [2][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt" +ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000." +Toggle crashdump_o.class_esc_cnt [3][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt" +ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000." +Toggle crashdump_o.class_esc_cnt [0][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt" +CHECKSUM: "2301929872 1403235006" +INSTANCE: tb.dut.u_ping_timer.u_prim_count_esc_cnt +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[15:0]" +CHECKSUM: "2301929872 1403235006" +INSTANCE: tb.dut.u_ping_timer.u_prim_count_cnt +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[15:0]" +CHECKSUM: "2301929872 1403235006" +INSTANCE: tb.dut.gen_classes[0].u_accu.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[15:0]" +CHECKSUM: "2301929872 1403235006" +INSTANCE: tb.dut.gen_classes[1].u_accu.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[15:0]" +CHECKSUM: "2301929872 1403235006" +INSTANCE: tb.dut.gen_classes[2].u_accu.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[15:0]" +CHECKSUM: "2301929872 1403235006" +INSTANCE: tb.dut.gen_classes[3].u_accu.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[15:0]" +CHECKSUM: "2301929872 277894862" +INSTANCE: tb.dut.gen_classes[0].u_esc_timer.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle set_cnt_i "net set_cnt_i[31:0]" +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[31:0]" +CHECKSUM: "2301929872 277894862" +INSTANCE: tb.dut.gen_classes[1].u_esc_timer.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle set_cnt_i "net set_cnt_i[31:0]" +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[31:0]" +CHECKSUM: "2301929872 277894862" +INSTANCE: tb.dut.gen_classes[2].u_esc_timer.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle set_cnt_i "net set_cnt_i[31:0]" +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[31:0]" +CHECKSUM: "2301929872 277894862" +INSTANCE: tb.dut.gen_classes[3].u_esc_timer.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[31:0]" +ANNOTATION: "[UNR]: Tied off to 1." +Toggle set_cnt_i "net set_cnt_i[31:0]" diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cov_unr.el b/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cov_unr.el new file mode 100644 index 0000000000000..392540ba67cdb --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cov_unr.el @@ -0,0 +1,933 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//================================================== +// This file contains the Excluded objects +// Generated By User: miguelosorio +// Format Version: 2 +// Date: Fri Aug 16 16:37:33 2024 +// ExclMode: default +//================================================== +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_4 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_5 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_6 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_7 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_8 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_9 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_10 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_11 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_12 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_13 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_14 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_15 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_16 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_17 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_18 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_19 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_20 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_21 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_22 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37 +ANNOTATION: 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((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_50 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_51 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_52 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_53 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_54 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_55 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_56 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_57 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_58 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_59 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_60 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_61 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_62 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_63 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_64 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_4 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_5 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_6 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_4 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_5 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_6 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_lock +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_clr_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_accum_thresh_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_timeout_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_crashdump_trigger_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_phase0_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_phase1_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_phase2_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_phase3_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_lock +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1549052440 1514362506" +INSTANCE: tb.dut.u_alert_handler_lpg_ctrl +ANNOTATION: "VC_COV_UNR" +Block 30 "3894967986" "unused_lpg_init_trig ^= (^lpg_init_trig[k]);" +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_ping_timeout_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_clr_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_accum_thresh_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_timeout_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_crashdump_trigger_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_phase0_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_phase1_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_phase2_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_phase3_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_lock +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_clr_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_accum_thresh_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_timeout_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_crashdump_trigger_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_phase0_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_phase1_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_phase2_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_phase3_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_lock +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_clr_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_accum_thresh_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_timeout_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_crashdump_trigger_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_phase0_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_phase1_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_phase2_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_phase3_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "74367784 3785313510" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_reg_if +ANNOTATION: "VC_COV_UNR" +Condition 18 "3340270436" "(addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error) 1 -1" (5 "01000") +CHECKSUM: "3655552781 2169403375" +INSTANCE: tb.dut.u_edn_req.u_prim_packer_fifo +ANNOTATION: "VC_COV_UNR" +Condition 9 "2531947712" "(gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 11 "1372743715" "(gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 16 "1428458034" "(( ! (depth_q == '0) ) && ((!clr_q))) 1 -1" (2 "10") +CHECKSUM: "571876547 4131299725" +INSTANCE: tb.dut.gen_classes[0].u_esc_timer +ANNOTATION: "VC_COV_UNR" +Condition 1 "1114111443" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 4 "687068015" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +CHECKSUM: "571876547 4131299725" +INSTANCE: tb.dut.gen_classes[1].u_esc_timer +ANNOTATION: "VC_COV_UNR" +Condition 1 "1114111443" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 4 "687068015" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +CHECKSUM: "571876547 4131299725" +INSTANCE: tb.dut.gen_classes[2].u_esc_timer +ANNOTATION: "VC_COV_UNR" +Condition 1 "1114111443" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 4 "687068015" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +CHECKSUM: "571876547 4131299725" +INSTANCE: tb.dut.gen_classes[3].u_esc_timer +ANNOTATION: "VC_COV_UNR" +Condition 1 "1114111443" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 4 "687068015" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +CHECKSUM: "3655552781 749591850" +INSTANCE: tb.dut.u_edn_req.u_prim_packer_fifo +ANNOTATION: "VC_COV_UNR" +Branch 0 "3339891226" "clear_status" (2) "clear_status 0,0,1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "3667320634" "clear_status" (1) "clear_status 0,1" +CHECKSUM: "1549052440 851307434" +INSTANCE: tb.dut.u_alert_handler_lpg_ctrl +ANNOTATION: "VC_COV_UNR" +Branch 0 "3440992731" "(!lpg_used)" (0) "(!lpg_used) 1" diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cover_reg_top.cfg b/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cover_reg_top.cfg new file mode 100644 index 0000000000000..33d5c073ced07 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/cov/alert_handler_cover_reg_top.cfg @@ -0,0 +1,26 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Limits coverage collection only to the *_reg_top module and the TL interface +// of the DUT. +// Alert_handler wraps alert_handler_reg_top with alert_handler_reg_wrap, so this overwrites the +// common cfg file to include the alert_handler_reg_wrap module. + ++moduletree *_reg_wrap ++node tb.dut tl_* +-module prim_cdc_rand_delay // DV construct. +-module prim_onehot_check // FPV verified + +begin assert + +moduletree *csr_assert_fpv + +moduletree tlul_assert +end + +// Remove everything else from toggle coverage except: +// - `prim_alert_sender`: the `alert_test` task under `cip_base_vseq` drives `alert_test_i` and +// verifies `alert_rx/tx` handshake in each IP. +begin tgl + -tree tb + +module prim_alert_sender +end diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/doc/tb.svg b/hw/top_darjeeling/ip_autogen/alert_handler/dv/doc/tb.svg new file mode 100644 index 0000000000000..e02634731aa6c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/doc/tb.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env.core b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env.core new file mode 100644 index 0000000000000..8103212c1975f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env.core @@ -0,0 +1,42 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:alert_handler_env:0.1" +description: "ALERT_HANDLER DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:cip_lib + - lowrisc:ip:alert_handler_component # import alert_pkg + - lowrisc:prim:mubi # import prim_mubi_pkg + files: + - alert_handler_env_pkg.sv + - alert_handler_if.sv + - alert_handler_env_cfg.sv: {is_include_file: true} + - alert_handler_env_cov.sv: {is_include_file: true} + - alert_handler_virtual_sequencer.sv: {is_include_file: true} + - alert_handler_scoreboard.sv: {is_include_file: true} + - alert_handler_env.sv: {is_include_file: true} + - seq_lib/alert_handler_vseq_list.sv: {is_include_file: true} + - seq_lib/alert_handler_base_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_common_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_smoke_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_random_alerts_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_random_classes_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_esc_intr_timeout_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_esc_alert_accum_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_sig_int_fail_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_entropy_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_ping_timeout_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_lpg_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_lpg_stub_clk_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_entropy_stress_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_stress_all_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_alert_accum_saturation_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env.sv new file mode 100644 index 0000000000000..a98944894edf4 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env.sv @@ -0,0 +1,80 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_handler_env extends cip_base_env #( + .CFG_T (alert_handler_env_cfg), + .COV_T (alert_handler_env_cov), + .VIRTUAL_SEQUENCER_T(alert_handler_virtual_sequencer), + .SCOREBOARD_T (alert_handler_scoreboard) + ); + `uvm_component_utils(alert_handler_env) + + `uvm_component_new + + alert_esc_agent alert_host_agent[]; + alert_esc_agent esc_device_agent[]; + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + // build alert agents + alert_host_agent = new[NUM_ALERTS]; + virtual_sequencer.alert_host_seqr_h = new[NUM_ALERTS]; + foreach (alert_host_agent[i]) begin + alert_host_agent[i] = alert_esc_agent::type_id::create( + $sformatf("alert_host_agent[%0d]", i), this); + uvm_config_db#(alert_esc_agent_cfg)::set(this, + $sformatf("alert_host_agent[%0d]", i), "cfg", cfg.alert_host_cfg[i]); + cfg.alert_host_cfg[i].en_cov = cfg.en_cov; + cfg.alert_host_cfg[i].clk_freq_mhz = int'(cfg.clk_freq_mhz); + end + + // build escalator agents + esc_device_agent = new[NUM_ESCS]; + virtual_sequencer.esc_device_seqr_h = new[NUM_ESCS]; + foreach (esc_device_agent[i]) begin + esc_device_agent[i] = alert_esc_agent::type_id::create( + $sformatf("esc_device_agent[%0d]", i), this); + uvm_config_db#(alert_esc_agent_cfg)::set(this, + $sformatf("esc_device_agent[%0d]", i), "cfg", cfg.esc_device_cfg[i]); + cfg.esc_device_cfg[i].en_cov = cfg.en_cov; + end + + // get vifs + if (!uvm_config_db#(crashdump_vif)::get(this, "", "crashdump_vif", cfg.crashdump_vif)) begin + `uvm_fatal(get_full_name(), "failed to get crashdump_vif from uvm_config_db") + end + if (!uvm_config_db#(alert_handler_vif)::get(this, "", "alert_handler_vif", + cfg.alert_handler_vif)) begin + `uvm_fatal(`gfn, "failed to get alert_handler_vif from uvm_config_db") + end + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + if (cfg.en_scb) begin + foreach (alert_host_agent[i]) begin + alert_host_agent[i].monitor.alert_esc_port.connect( + scoreboard.alert_fifo[i].analysis_export); + end + foreach (esc_device_agent[i]) begin + esc_device_agent[i].monitor.alert_esc_port.connect( + scoreboard.esc_fifo[i].analysis_export); + end + end + if (cfg.is_active) begin + foreach (alert_host_agent[i]) begin + if (cfg.alert_host_cfg[i].is_active) begin + virtual_sequencer.alert_host_seqr_h[i] = alert_host_agent[i].sequencer; + end + end + end + foreach (esc_device_agent[i]) begin + if (cfg.esc_device_cfg[i].is_active) begin + virtual_sequencer.esc_device_seqr_h[i] = esc_device_agent[i].sequencer; + end + end + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env_cfg.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env_cfg.sv new file mode 100644 index 0000000000000..cb1aeb71034d7 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env_cfg.sv @@ -0,0 +1,54 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_handler_env_cfg extends cip_base_env_cfg #(.RAL_T(alert_handler_reg_block)); + + // ext component cfgs + esc_en_vif esc_en_vif; + crashdump_vif crashdump_vif; + alert_handler_vif alert_handler_vif; + rand alert_esc_agent_cfg alert_host_cfg[]; + rand alert_esc_agent_cfg esc_device_cfg[]; + + `uvm_object_utils_begin(alert_handler_env_cfg) + `uvm_field_array_object(alert_host_cfg, UVM_DEFAULT) + `uvm_field_array_object(esc_device_cfg, UVM_DEFAULT) + `uvm_object_utils_end + + `uvm_object_new + + virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1); + num_edn = 1; + super.initialize(csr_base_addr); + shadow_update_err_status_fields[ral.loc_alert_cause[LocalShadowRegUpdateErr].la] = 1; + shadow_storage_err_status_fields[ral.loc_alert_cause[LocalShadowRegStorageErr].la] = 1; + + // set num_interrupts & num_alerts + num_interrupts = ral.intr_state.get_n_used_bits(); + + alert_host_cfg = new[NUM_ALERTS]; + esc_device_cfg = new[NUM_ESCS]; + foreach (alert_host_cfg[i]) begin + alert_host_cfg[i] = + alert_esc_agent_cfg::type_id::create($sformatf("alert_host_cfg[%0d]", i)); + alert_host_cfg[i].if_mode = dv_utils_pkg::Host; + alert_host_cfg[i].is_async = ASYNC_ON[i]; + end + foreach (esc_device_cfg[i]) begin + esc_device_cfg[i] = + alert_esc_agent_cfg::type_id::create($sformatf("esc_device_cfg[%0d]", i)); + esc_device_cfg[i].if_mode = dv_utils_pkg::Device; + esc_device_cfg[i].is_alert = 0; + end + // only support 1 outstanding TL items in tlul_adapter + m_tl_agent_cfg.max_outstanding_req = 1; + endfunction + + // Override shadow register naming checks. The alert handler does not expose any alert signals, + // hence no alerts are defined in Hjson. + virtual function void check_shadow_reg_alerts(); + // Nothing to check. + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env_cov.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env_cov.sv new file mode 100644 index 0000000000000..ac55448d73e9b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env_cov.sv @@ -0,0 +1,184 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_ping_with_lpg_cg_wrap; + covergroup alert_ping_with_lpg_cg(string name) with function sample (bit lpg_en); + option.per_instance = 1; + option.name = name; + lpg_cg: coverpoint lpg_en { + bins lpg_en = {1}; + bins lpg_dis = {0}; + } + endgroup + + function new(string name); + alert_ping_with_lpg_cg = new(name); + endfunction +endclass + +class alert_handler_env_cov extends cip_base_env_cov #(.CFG_T(alert_handler_env_cfg)); + `uvm_component_utils(alert_handler_env_cov) + + alert_ping_with_lpg_cg_wrap ping_with_lpg_cg_wrap[NUM_ALERTS]; + + // covergroups + covergroup accum_cnt_cg with function sample(int class_index, int cnt); + class_index_cp: coverpoint class_index { + bins class_index[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + } + // Due to the limited simulation time, this only collect accum coverage until 2000. For the + // saturation case, design has assertions to cover that. + accum_cnt_cp: coverpoint cnt { + bins accum_cnt_0 = {0}; + bins accum_cnt_10 = {[1:10]}; + bins accum_cnt_50 = {[11:50]}; + bins accum_cnt_100 = {[51:100]}; + bins accum_cnt_1000 = {[101:1000]}; + bins accum_cnt_2000 = {[1001:2000]}; + } + class_cnt_cross: cross class_index_cp, accum_cnt_cp; + endgroup : accum_cnt_cg + + covergroup intr_timeout_cnt_cg with function sample(int class_index, int cnt); + class_index_cp: coverpoint class_index { + bins class_index[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + } + intr_timeout_cnt_cp: coverpoint cnt { + bins intr_timeout_cnt[10] = {[0:1000]}; + } + class_cnt_cross: cross class_index_cp, intr_timeout_cnt_cp; + endgroup + + covergroup esc_sig_length_cg with function sample(int sig_index, int sig_len); + esc_sig_index_cp: coverpoint sig_index { + bins index[NUM_ESC_SIGNALS] = {[0:NUM_ESC_SIGNALS-1]}; + } + esc_sig_len_cp: coverpoint sig_len { + bins len_2 = {2}; + bins lens_less_than_1000[10] = {[3:1000]}; + } + len_per_esc_sig: cross esc_sig_index_cp, esc_sig_len_cp; + endgroup : esc_sig_length_cg + + covergroup clear_intr_cnt_cg with function sample(int class_index); + clear_intr_cnt_cp: coverpoint class_index { + bins class_index[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + } + endgroup + + covergroup clear_esc_cnt_cg with function sample(int class_index); + clear_esc_cnt_cp: coverpoint class_index { + bins class_index[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + } + endgroup + + covergroup alert_cause_cg with function sample(int alert_index, int class_index); + alert_cause_cp: coverpoint alert_index { + bins alert[NUM_ALERTS] = {[0:NUM_ALERTS-1]}; + illegal_bins il = default; + } + class_index_cp: coverpoint class_index { + bins class_i[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + illegal_bins il = default; + } + alert_cause_cross_class_index: cross alert_cause_cp, class_index_cp; + endgroup + + covergroup alert_loc_alert_cause_cg with function sample(local_alert_type_e local_alert, + int alert_index, + int class_index); + loc_alert_cause_cp: coverpoint local_alert { + bins alert_ping_fail = {LocalAlertPingFail}; + bins alert_integrity_fail = {LocalAlertIntFail}; + illegal_bins il = default; + } + alert_index_cp: coverpoint alert_index { + bins alert[NUM_ALERTS] = {[0:NUM_ALERTS-1]}; + illegal_bins il = default; + } + class_index_cp: coverpoint class_index { + bins class_i[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + illegal_bins il = default; + } + loc_alert_cause_cross_alert_index: cross loc_alert_cause_cp, alert_index_cp; + loc_alert_cause_cross_class_index: cross loc_alert_cause_cp, class_index_cp; + endgroup + + covergroup esc_loc_alert_cause_cg with function sample(local_alert_type_e local_alert, + int esc_index, + int class_index); + loc_alert_cause_cp: coverpoint local_alert { + bins esc_ping_fail = {LocalEscPingFail}; + bins esc_integrity_fail = {LocalEscIntFail}; + illegal_bins il = default; + } + esc_index_cp: coverpoint esc_index { + bins alert[NUM_ESCS] = {[0:NUM_ESCS-1]}; + illegal_bins il = default; + } + class_index_cp: coverpoint class_index { + bins class_i[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + illegal_bins il = default; + } + loc_alert_cause_cross_alert_index: cross loc_alert_cause_cp, esc_index_cp; + loc_alert_cause_cross_class_index: cross loc_alert_cause_cp, class_index_cp; + endgroup + + covergroup crashdump_trigger_cg with function sample(bit [1:0] phase); + crashdump_trigger_phase_cp: coverpoint phase { + bins phase_0 = {0}; + bins phase_1 = {1}; + bins phase_2 = {2}; + bins phase_3 = {3}; + } + endgroup + + // Covergroup to make sure simulation is long enough to fetch more than five EDN requests. + covergroup num_edn_reqs_cg with function sample(int num_edn_reqs); + num_edn_reqs_cp: coverpoint num_edn_reqs { + bins less_than_five_reqs = {[1:4]}; + bins five_or_more_reqs = {[5:$]}; + } + endgroup + + covergroup num_checked_pings_cg with function sample (int num_pings); + num_pings_cp: coverpoint num_pings { + bins less_than_ten_pings = {[1:9]}; + bins ten_to_twenty_pings = {[10:19]}; + bins more_than_twenty_pings = {[20:$]}; + } + endgroup + + covergroup cycles_between_pings_cg with function sample (int num_cycles_between_pings); + num_cycles_cp: coverpoint num_cycles_between_pings{ + bins less_than_5000_cycs = {[1:4_999]}; + bins less_than_100k_cycs = {[5_000:99_999]}; + bins less_than_150k_cycs = {[5_000:149_999]}; + bins less_than_200k_cycs = {[150_000:199_999]}; + bins more_than_200k_cycs = {[200_000:$]}; + } + endgroup + + function new(string name, uvm_component parent); + super.new(name, parent); + accum_cnt_cg = new(); + intr_timeout_cnt_cg = new(); + esc_sig_length_cg = new(); + clear_intr_cnt_cg = new(); + clear_esc_cnt_cg = new(); + alert_cause_cg = new(); + alert_loc_alert_cause_cg = new(); + esc_loc_alert_cause_cg = new(); + crashdump_trigger_cg = new(); + + num_edn_reqs_cg = new(); + num_checked_pings_cg = new(); + cycles_between_pings_cg = new(); + + foreach (ping_with_lpg_cg_wrap[i]) begin + ping_with_lpg_cg_wrap[i] = new($sformatf("ping_with_lpg_cg_wrap[%0d]", i)); + end + endfunction : new + +endclass diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env_pkg.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env_pkg.sv new file mode 100644 index 0000000000000..54afee0f00884 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_env_pkg.sv @@ -0,0 +1,106 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package alert_handler_env_pkg; + // dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import csr_utils_pkg::*; + import tl_agent_pkg::*; + import alert_esc_agent_pkg::*; + import alert_handler_ral_pkg::*; + import dv_base_reg_pkg::*; + import cip_base_pkg::*; + import push_pull_agent_pkg::*; + import sec_cm_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // parameters + parameter uint NUM_ALERTS = alert_handler_reg_pkg::NAlerts; + parameter uint NUM_EDN = 1; + parameter uint NUM_ESCS = 4; + parameter uint NUM_MAX_ESC_SEV = 8; + parameter uint NUM_ESC_SIGNALS = 4; + parameter uint NUM_ALERT_CLASSES = 4; + parameter uint NUM_ESC_PHASES = 4; + parameter uint NUM_ALERT_CLASS_MSB = $clog2(NUM_ALERT_CLASSES) - 1; + parameter uint MIN_CYCLE_PER_PHASE = 2; + parameter uint NUM_LOCAL_ALERTS = 7; + parameter bit [NUM_ALERTS-1:0] ASYNC_ON = alert_handler_reg_pkg::AsyncOn; + // ignore esc signal cycle count after ping occurs - as ping response might ended up adding one + // extra cycle to the calculated cnt, or even combine two signals into one. + parameter uint IGNORE_CNT_CHECK_NS = 100_000_000; + // set the max ping timeout cycle to constrain the simulation run time + parameter uint MAX_PING_TIMEOUT_CYCLE = 300; + + // Alert_handler ping timer design should automatically fetch EDN entropy every 500k clock + // cycles. We set the threshold to 600k clock cycles. + parameter uint MAX_EDN_REQ_WAIT_CYCLES = 600_000; + + parameter uint NUM_CRASHDUMP = NUM_ALERT_CLASSES * (alert_handler_reg_pkg::AccuCntDw + + alert_handler_reg_pkg::EscCntDw + 3) + + NUM_ALERTS + NUM_LOCAL_ALERTS; + parameter bit[15:0] MAX_PING_WAIT_CYCLES = '1; + + // types + typedef enum { + EscPhase0, + EscPhase1, + EscPhase2, + EscPhase3 + } esc_phase_e; + + typedef enum { + AlertClassCtrlEn, + AlertClassCtrlLock, + AlertClassCtrlEnE0, + AlertClassCtrlEnE1, + AlertClassCtrlEnE2, + AlertClassCtrlEnE3, + AlertClassCtrlMapE0, + AlertClassCtrlMapE1, + AlertClassCtrlMapE2, + AlertClassCtrlMapE3 + } alert_class_ctrl_e; + + typedef enum { + EscStateIdle = 'b000, + EscStateTimeout = 'b001, + EscStateTerminal = 'b011, + EscStatePhase0 = 'b100, + EscStatePhase1 = 'b101, + EscStatePhase2 = 'b110, + EscStatePhase3 = 'b111 + } esc_state_e; + + typedef enum { + LocalAlertPingFail, + LocalEscPingFail, + LocalAlertIntFail, + LocalEscIntFail, + LocalBusIntgFail, + LocalShadowRegUpdateErr, + LocalShadowRegStorageErr + } local_alert_type_e; + + // forward declare classes to allow typedefs below + typedef virtual pins_if #(NUM_MAX_ESC_SEV) esc_en_vif; + typedef virtual pins_if #(NUM_CRASHDUMP) crashdump_vif; + typedef virtual alert_handler_if alert_handler_vif; + + // functions + + // package sources + `include "alert_handler_env_cfg.sv" + `include "alert_handler_env_cov.sv" + `include "alert_handler_virtual_sequencer.sv" + `include "alert_handler_scoreboard.sv" + `include "alert_handler_env.sv" + `include "alert_handler_vseq_list.sv" + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_if.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_if.sv new file mode 100644 index 0000000000000..fe8f3e4644fe3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_if.sv @@ -0,0 +1,60 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Interface for LPG and crashdump output. +interface alert_handler_if(input clk, input rst_n); + import uvm_pkg::*; + import alert_pkg::*; + import prim_mubi_pkg::*; + import cip_base_pkg::*; + import alert_handler_env_pkg::*; + + mubi4_t [NLpg-1:0] lpg_cg_en; + mubi4_t [NLpg-1:0] lpg_rst_en; + + logic [NUM_ALERTS-1:0] alert_ping_reqs; + logic [NUM_ESCS-1:0] esc_ping_reqs; + + string msg_id = "alert_handler_if"; + + function automatic void init(); + mubi4_t mubi_false_val = get_rand_mubi4_val(0, 1, 1); + lpg_cg_en = '{default: mubi_false_val}; + lpg_rst_en = '{default: mubi_false_val}; + endfunction + + function automatic bit get_lpg_status(int index); + check_lpg_index(index); + return (lpg_cg_en[index] == MuBi4True || lpg_rst_en[index] == MuBi4True); + endfunction + + function automatic void set_lpg_cg_en(int index); + check_lpg_index(index); + lpg_cg_en[index] = MuBi4True; + endfunction + + function automatic void set_lpg_rst_en(int index); + check_lpg_index(index); + lpg_rst_en[index] = MuBi4True; + endfunction + + function automatic void check_lpg_index(int index); + if (index >= NLpg) begin + `uvm_fatal(msg_id, $sformatf("Alert_handler has %0d LPGs but attempts to set index %0d", + NLpg, index)) + end + endfunction + + task automatic set_wait_cyc_mask(logic [PING_CNT_DW-1:0] val); + static logic [PING_CNT_DW-1:0] val_static; + begin + val_static = val; + force tb.dut.u_ping_timer.wait_cyc_mask_i = val_static; + end + endtask + + task automatic release_wait_cyc_mask(); + release tb.dut.u_ping_timer.wait_cyc_mask_i; + endtask +endinterface diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_scoreboard.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_scoreboard.sv new file mode 100644 index 0000000000000..6b7c1c00fce1e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_scoreboard.sv @@ -0,0 +1,785 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`define ASSIGN_CLASS_PHASE_REGS(index, i) \ + reg_esc_phase_cycs_per_class_q[``index``] = \ + {ral.class``i``_phase0_cyc_shadowed, ral.class``i``_phase1_cyc_shadowed, \ + ral.class``i``_phase2_cyc_shadowed, ral.class``i``_phase3_cyc_shadowed}; + +class alert_handler_scoreboard extends cip_base_scoreboard #( + .CFG_T(alert_handler_env_cfg), + .RAL_T(alert_handler_reg_block), + .COV_T(alert_handler_env_cov) + ); + `uvm_component_utils(alert_handler_scoreboard) + + // esc_phase_cyc_per_class_q: each class has four phase cycles, stores each cycle length + // --- class --- phase0_cyc --- phase1_cyc --- phase2_cyc --- phase3_cyc --- + // --- A -classa_phase0_cyc - classa_phase1_cyc - classa_phase2_cyc - classa_phase3_cyc -- + // --- B -classb_phase0_cyc - classb_phase1_cyc - classb_phase2_cyc - classb_phase3_cyc -- + // --- C -classc_phase0_cyc - classc_phase1_cyc - classc_phase2_cyc - classc_phase3_cyc -- + // --- D -classd_phase0_cyc - classd_phase1_cyc - classd_phase2_cyc - classd_phase3_cyc -- + dv_base_reg reg_esc_phase_cycs_per_class_q[NUM_ALERT_CLASSES][$]; + + uvm_reg_field intr_state_fields[$]; + uvm_reg_field intr_state_field; + // once escalation triggers, no alerts can trigger another escalation in the same class + // until the class esc is cleared + bit [NUM_ALERT_CLASSES-1:0] under_esc_classes; + bit [NUM_ALERT_CLASSES-1:0] under_intr_classes; + bit [NUM_ALERT_CLASSES-1:0] clr_esc_under_intr; + int intr_cnter_per_class [NUM_ALERT_CLASSES]; + int accum_cnter_per_class [NUM_ALERT_CLASSES]; + esc_state_e state_per_class [NUM_ALERT_CLASSES]; + int esc_signal_release [NUM_ESC_SIGNALS]; + int esc_sig_class [NUM_ESC_SIGNALS]; // one class can increment one esc signal at a time + // For different alert classify in the same class and trigger at the same cycle, design only + // count once. So record the alert triggered timing here + realtime last_triggered_alert_per_class[NUM_ALERT_CLASSES]; + + string class_name[] = {"a", "b", "c", "d"}; + bit [TL_DW-1:0] intr_state_val; + + bit [NUM_ALERT_CLASSES-1:0] crashdump_triggered = 0; + + bit ping_timer_en; + + // TLM agent fifos + uvm_tlm_analysis_fifo #(alert_esc_seq_item) alert_fifo[NUM_ALERTS]; + uvm_tlm_analysis_fifo #(alert_esc_seq_item) esc_fifo[NUM_ESCS]; + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + ral.intr_state.get_fields(intr_state_fields); + `ASSIGN_CLASS_PHASE_REGS(0, a) + `ASSIGN_CLASS_PHASE_REGS(1, b) + `ASSIGN_CLASS_PHASE_REGS(2, c) + `ASSIGN_CLASS_PHASE_REGS(3, d) + + foreach (alert_fifo[i]) alert_fifo[i] = new($sformatf("alert_fifo[%0d]", i), this); + foreach (esc_fifo[i]) esc_fifo[i] = new($sformatf("esc_fifo[%0d]" , i), this); + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + fork + process_alert_fifo(); + process_esc_fifo(); + process_edn_fifos(); + check_ping_timer(); + check_crashdump(); + check_intr_timeout_trigger_esc(); + esc_phase_signal_cnter(); + release_esc_signal(); + join_none + endtask + + virtual task process_alert_fifo(); + foreach (alert_fifo[i]) begin + automatic int index = i; + automatic int lpg_index = alert_handler_reg_pkg::LpgMap[index]; + fork + forever begin + bit alert_en, loc_alert_en; + alert_esc_seq_item act_item; + alert_fifo[index].get(act_item); + alert_en = ral.alert_en_shadowed[index].get_mirrored_value() && + prim_mubi_pkg::mubi4_test_false_loose(cfg.alert_handler_vif.lpg_cg_en[lpg_index]) && + prim_mubi_pkg::mubi4_test_false_loose(cfg.alert_handler_vif.lpg_rst_en[lpg_index]); + + // Check that ping mechanism will only ping alerts that have been enabled and locked. + if (act_item.alert_esc_type == AlertEscPingTrans) begin + `DV_CHECK(alert_en, $sformatf("alert %0s ping triggered but not enabled", index)) + `DV_CHECK((`gmv(ral.alert_regwen[index]) == 0), + $sformatf("alert %0s ping triggered but not locked", index)) + end + + if (alert_en) begin + // alert detected + if (act_item.alert_esc_type == AlertEscSigTrans && !act_item.ping_timeout && + act_item.alert_handshake_sta == AlertReceived) begin + process_alert_sig(index, 0); + // alert integrity fail + end else if (act_item.alert_esc_type == AlertEscIntFail) begin + loc_alert_en = ral.loc_alert_en_shadowed[LocalAlertIntFail].get_mirrored_value(); + if (loc_alert_en) process_alert_sig(index, 1, LocalAlertIntFail); + end else if (act_item.alert_esc_type == AlertEscPingTrans && + act_item.ping_timeout) begin + loc_alert_en = ral.loc_alert_en_shadowed[LocalAlertPingFail].get_mirrored_value(); + if (loc_alert_en) begin + process_alert_sig(index, 1, LocalAlertPingFail); + `uvm_info(`gfn, $sformatf("alert %0d ping timeout, timeout_cyc reg is %0d", + index, ral.ping_timeout_cyc_shadowed.get_mirrored_value()), UVM_LOW); + end + end + end + end + join_none + end + endtask : process_alert_fifo + + virtual task process_esc_fifo(); + foreach (esc_fifo[i]) begin + automatic int index = i; + fork + forever begin + alert_esc_seq_item act_item; + esc_fifo[index].get(act_item); + // escalation triggered, check signal length + if (act_item.alert_esc_type == AlertEscSigTrans && + act_item.esc_handshake_sta == EscRespComplete) begin + check_esc_signal(act_item.sig_cycle_cnt, index); + // escalation integrity fail + end else if (act_item.alert_esc_type == AlertEscIntFail || + (act_item.esc_handshake_sta == EscIntFail && !act_item.ping_timeout)) begin + bit loc_alert_en = ral.loc_alert_en_shadowed[LocalEscIntFail].get_mirrored_value(); + if (loc_alert_en) process_alert_sig(index, 1, LocalEscIntFail); + // escalation ping timeout + end else if (act_item.alert_esc_type == AlertEscPingTrans) begin + if (act_item.ping_timeout) begin + bit loc_alert_en = ral.loc_alert_en_shadowed[LocalEscPingFail].get_mirrored_value(); + if (loc_alert_en) begin + process_alert_sig(index, 1, LocalEscPingFail); + `uvm_info(`gfn, $sformatf("esc %0d ping timeout, timeout_cyc reg is %0d", + index, ral.ping_timeout_cyc_shadowed.get_mirrored_value()), UVM_LOW); + end + end + end + end + join_none + end + endtask : process_esc_fifo + + // Alert_handler ping timer is designed to fetch EDN value periodically. + virtual task process_edn_fifos(); + fork begin: isolation_fork + int num_edn_reqs; + forever begin + wait (cfg.under_reset == 0); + fork + begin + check_edn_request_cycles(); + num_edn_reqs++; + if (cfg.en_cov) cov.num_edn_reqs_cg.sample(num_edn_reqs); + end + begin + wait (cfg.under_reset == 1); + num_edn_reqs = 0; + end + join_any + disable fork; + end + end join + endtask + + virtual task check_edn_request_cycles(); + int edn_wait_cycles; + fork + begin : isolation_fork + fork + begin + while (edn_wait_cycles < MAX_EDN_REQ_WAIT_CYCLES) begin + cfg.clk_rst_vif.wait_clks(1); + edn_wait_cycles++; + end + `uvm_error(`gfn, "Timeout occured waiting for an EDN request!"); + end + begin + push_pull_item#(.DeviceDataWidth(EDN_DATA_WIDTH)) edn_item; + edn_fifos[0].get(edn_item); + end + join_any + disable fork; + end + join + endtask + + // this task process alert signal by checking if intergrity fail, then classify it to the + // mapping classes, then check if escalation is triggered by accumulation + // this task delayed to a negedge clk to avoid updating and checking regs at the same time + virtual task process_alert_sig(int alert_i, bit is_int_err, + local_alert_type_e local_alert_type = LocalAlertIntFail); + fork + begin + cfg.clk_rst_vif.wait_n_clks(1); + if (!under_reset) begin + bit [TL_DW-1:0] intr_en, class_ctrl; + bit [NUM_ALERT_CLASS_MSB:0] class_i; + if (!is_int_err) begin + class_i = `gmv(ral.alert_class_shadowed[alert_i]); + void'(ral.alert_cause[alert_i].predict(1)); + if (cfg.en_cov) cov.alert_cause_cg.sample(alert_i, class_i); + end else begin + class_i = `gmv(ral.loc_alert_class_shadowed[int'(local_alert_type)]); + void'(ral.loc_alert_cause[int'(local_alert_type)].predict( + .value(1), .kind(UVM_PREDICT_READ))); + if (cfg.en_cov) begin + if (local_alert_type inside {LocalAlertPingFail, LocalAlertIntFail}) begin + cov.alert_loc_alert_cause_cg.sample(local_alert_type, alert_i, class_i); + end else begin + cov.esc_loc_alert_cause_cg.sample(local_alert_type, alert_i, class_i); + end + end + end + + intr_state_field = intr_state_fields[class_i]; + void'(intr_state_field.predict(.value(1), .kind(UVM_PREDICT_READ))); + intr_en = ral.intr_enable.get_mirrored_value(); + + // calculate escalation + class_ctrl = get_class_ctrl(class_i); + `uvm_info(`gfn, $sformatf("class %0d is triggered, class ctrl=%0h, under_esc=%0b", + class_i, class_ctrl, under_esc_classes[class_i]), UVM_DEBUG) + // if class escalation is enabled, add alert to accumulation count + if (class_ctrl[AlertClassCtrlEn] && + (class_ctrl[AlertClassCtrlEnE3:AlertClassCtrlEnE0] > 0)) begin + alert_accum_cal(class_i); + end + + // according to issue #841, interrupt will have one clock cycle delay + // add an extra cycle for synchronizers from clk_edn to clk + cfg.clk_rst_vif.wait_n_clks(1); + if (!under_reset) begin + `DV_CHECK_CASE_EQ(cfg.intr_vif.pins[class_i], intr_en[class_i], + $sformatf("Interrupt class_%s, is_local_err %0b, local_alert_type %s", + class_name[class_i],is_int_err, local_alert_type)); + if (!under_intr_classes[class_i] && intr_en[class_i]) under_intr_classes[class_i] = 1; + end + end + end + join_none + endtask + + // calculate alert accumulation count per class, if accumulation exceeds the threshold, + // and if current class is not under escalation, then predict escalation + // note: if more than one alerts triggered on the same clk cycle, only accumulates one + virtual function void alert_accum_cal(int class_i); + bit [TL_DW-1:0] accum_thresh = get_class_accum_thresh(class_i); + realtime curr_time = $realtime(); + if (curr_time != last_triggered_alert_per_class[class_i] && !cfg.under_reset) begin + last_triggered_alert_per_class[class_i] = curr_time; + // avoid accum_cnt saturate + if (accum_cnter_per_class[class_i] < 'hffff) begin + accum_cnter_per_class[class_i] += 1; + if (accum_cnter_per_class[class_i] > accum_thresh && !under_esc_classes[class_i]) begin + predict_esc(class_i); + end + end + end + `uvm_info(`gfn, + $sformatf("alert_accum: class=%0d, alert_cnt=%0d, thresh=%0d, under_esc=%0b", + class_i, accum_cnter_per_class[class_i], accum_thresh, + under_esc_classes[class_i]), UVM_DEBUG) + endfunction + + // if clren register is disabled, predict escalation signals by setting the corresponding + // under_esc_classes bit based on class_ctrl's lock bit + virtual function void predict_esc(int class_i); + bit [TL_DW-1:0] class_ctrl = get_class_ctrl(class_i); + if (class_ctrl[AlertClassCtrlLock]) begin + uvm_reg clren_rg; + clren_rg = ral.get_reg_by_name($sformatf("class%s_clr_regwen", class_name[class_i])); + `DV_CHECK_NE_FATAL(clren_rg, null) + void'(clren_rg.predict(0)); + end + under_esc_classes[class_i] = 1; + endfunction + + // check if escalation signal's duration length is correct + virtual function void check_esc_signal(int cycle_cnt, int esc_sig_i); + int class_a = `gmv(ral.classa_ctrl_shadowed); + int class_b = `gmv(ral.classb_ctrl_shadowed); + int class_c = `gmv(ral.classc_ctrl_shadowed); + int class_d = `gmv(ral.classd_ctrl_shadowed); + int sig_index = AlertClassCtrlEnE0+esc_sig_i; + bit [NUM_ALERT_CLASSES-1:0] select_class = {class_d[sig_index], class_c[sig_index], + class_b[sig_index], class_a[sig_index]}; + + + // Only compare the escalation signal length if exactly one class is assigned to this signal. + // Otherwise scb cannot predict the accurate cycle length if multiple classes are merged. + if ($countones(select_class) == 1) begin + int exp_cycle, phase, class_i; + // Find the class that triggers the escalation, and find which phase the escalation signal is + // reflecting. + for (class_i = 0; class_i < NUM_ALERT_CLASSES; class_i++) begin + if (select_class[class_i] == 1) begin + phase = `gmv(ral.get_reg_by_name($sformatf("class%0s_ctrl_shadowed", + class_name[class_i]))); + break; + end + end + phase = phase[(AlertClassCtrlMapE0 + esc_sig_i * 2) +: 2]; + exp_cycle = `gmv(ral.get_reg_by_name($sformatf("class%0s_phase%0d_cyc_shadowed", + class_name[class_i], phase))) + 1; + // Minimal phase length is 2 cycles. + exp_cycle = exp_cycle < 2 ? 2 : exp_cycle; + `uvm_info(`gfn, $sformatf("esc_signal_%0d, esc phase %0d, esc class %0d", + esc_sig_i, phase, class_i), UVM_HIGH); + + // If the escalation signal is interrupted by reset or esc_clear, we expect the signal length + // to be shorter than the phase_cycle_length. + if (cfg.under_reset || under_esc_classes[class_i] == 0) begin + `DV_CHECK_LE(cycle_cnt, exp_cycle) + end else begin + `DV_CHECK_EQ(cycle_cnt, exp_cycle) + end + if (cfg.en_cov) cov.esc_sig_length_cg.sample(esc_sig_i, cycle_cnt); + end + esc_sig_class[esc_sig_i] = 0; + endfunction + + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + uvm_reg csr; + dv_base_reg dv_base_csr; + bit do_read_check = 1'b1; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = {item.a_addr[TL_AW-1:2], 2'b00}; + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = ral.default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + `downcast(dv_base_csr, csr) + end + if (csr == null) begin + // we hit an oob addr - expect error response and return + `DV_CHECK_EQ(item.d_error, 1'b1) + return; + end + + if (channel == AddrChannel) begin + // if incoming access is a write to a valid csr, then make updates right away + if (write) begin + string csr_name = csr.get_name(); + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + // process the csr req + // for write, update local variable and fifo at address phase + case (csr_name) + // add individual case item for each csr + "intr_test": begin + bit [TL_DW-1:0] intr_state_exp = item.a_data | ral.intr_state.get_mirrored_value(); + if (cfg.en_cov) begin + bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value(); + for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin + cov.intr_test_cg.sample(i, item.a_data[i], intr_en[i], intr_state_exp[i]); + end + end + void'(ral.intr_state.predict(.value(intr_state_exp), .kind(UVM_PREDICT_DIRECT))); + end + // disable intr_enable or clear intr_state will clear the interrupt timeout cnter + "intr_state": begin + fork + begin + // after interrupt is set, it needs one clock cycle to update the value and stop + // the intr_timeout counter + cfg.clk_rst_vif.wait_clks(1); + if (!cfg.under_reset) begin + foreach (under_intr_classes[i]) begin + if (item.a_data[i]) begin + under_intr_classes[i] = 0; + clr_esc_under_intr[i] = 0; + if (!under_esc_classes[i]) state_per_class[i] = EscStateIdle; + end + end + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), + .be(item.a_mask))); + end + end + join_none + end + "intr_enable": begin + foreach (under_intr_classes[i]) begin + if (item.a_data[i] == 0) under_intr_classes[i] = 0; + end + end + "classa_clr_shadowed": begin + if (!dv_base_csr.is_staged() && ral.classa_clr_regwen.get_mirrored_value()) begin + clr_reset_esc_class(0); + end + end + "classb_clr_shadowed": begin + if (!dv_base_csr.is_staged() && ral.classb_clr_regwen.get_mirrored_value()) begin + clr_reset_esc_class(1); + end + end + "classc_clr_shadowed": begin + if (!dv_base_csr.is_staged() && ral.classc_clr_regwen.get_mirrored_value()) begin + clr_reset_esc_class(2); + end + end + "classd_clr_shadowed": begin + if (!dv_base_csr.is_staged() && ral.classd_clr_regwen.get_mirrored_value()) begin + clr_reset_esc_class(3); + end + end + "ping_timer_en_shadowed": begin + if (shadowed_reg_wr_completed(dv_base_csr) && + item.a_data && + `gmv(ral.ping_timer_regwen)) begin + ping_timer_en = 1; + end + end + "alert_test", "ping_timeout_cyc_shadowed", "ping_timer_regwen": begin + // Do nothing. Already auto update mirrored value. + end + default: begin + // The following regs only need to auto update mirrored value. + if (!uvm_re_match("*alert_en_shadowed*", csr_name) || + !uvm_re_match("*alert_class_shadowed*", csr_name) || + !uvm_re_match("class*_ctrl_shadowed", csr_name) || + !uvm_re_match("class*_crashdump_trigger_shadowed", csr_name) || + !uvm_re_match("class*_phase*_cyc_shadowed", csr_name) || + !uvm_re_match("class*_timeout_cyc_shadowed", csr_name) || + !uvm_re_match("class*_accum_thresh_shadowed", csr_name) || + !uvm_re_match("class*_clr_regwen", csr_name) || + !uvm_re_match("class*_regwen", csr_name) || + !uvm_re_match("*alert_regwen_*", csr_name)) begin + end else begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + end + endcase + end + end + + // process the csr req + // for read, update predication at address phase and compare at data phase + + if (!write) begin + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (channel == DataChannel) begin + if (cfg.en_cov) begin + if (csr.get_name() == "intr_state") begin + bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value(); + for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin + cov.intr_cg.sample(i, intr_en[i], item.d_data[i]); + cov.intr_pins_cg.sample(i, cfg.intr_vif.pins[i]); + end + end else begin + for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin + if (csr.get_name() == $sformatf("class%s_accum_cnt", class_name[i])) begin + cov.accum_cnt_cg.sample(i, item.d_data); + end + end + end + end + if (csr.get_name == "intr_state") begin + `DV_CHECK_EQ(intr_state_val, item.d_data, $sformatf("reg name: %0s", "intr_state")) + do_read_check = 0; + end + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, + $sformatf("reg name: %0s", csr.get_full_name())) + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end else begin + // predict in address phase to avoid the register's value changed during the read + for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin + if (csr.get_name() == $sformatf("class%s_esc_cnt", class_name[i])) begin + void'(csr.predict(.value(intr_cnter_per_class[i]), .kind(UVM_PREDICT_READ))); + end else if (csr.get_name() == $sformatf("class%s_accum_cnt", class_name[i])) begin + void'(csr.predict(.value(accum_cnter_per_class[i]), .kind(UVM_PREDICT_READ))); + end else if (csr.get_name() == $sformatf("class%s_state", class_name[i])) begin + void'(csr.predict(.value(state_per_class[i]), .kind(UVM_PREDICT_READ))); + end + end + if (csr.get_name() == "intr_state") intr_state_val = csr.get_mirrored_value(); + end + end + endtask + + virtual task check_ping_timer(); + int num_checked_pings; + fork begin : isolation_fork + forever begin + wait (ping_timer_en == 1); + fork + begin + wait (cfg.under_reset == 1); + ping_timer_en = 0; + num_checked_pings = 0; + end + begin + check_ping_triggered_cycles(); + num_checked_pings++; + if (cfg.en_cov) cov.num_checked_pings_cg.sample(num_checked_pings); + end + join_any + disable fork; + end + end join + endtask + + // This task checks if pings are triggered within the expected time. + // + // The ping timer is 16 bits so ideally we should see alert_ping -> esc_ping -> alert_ping ... + // with the max length of 16'hFFFF clock cycle. However alert_ping is randomly selected so we + // can not guarantee the random alert index is valid (exists), enabld, and locked. + // However, esc ping timer should are always expected to trigger. + // So the max wait time is 'hFFFF*2. + // This task also used the probed design signal instead of detected ping requests from monitor. + // Because if esc ping request and real esc request come at the same time, design will ignore the + // ping requests. But the probed signal will still set to 1. + virtual task check_ping_triggered_cycles(); + int ping_wait_cycs; + while (ping_wait_cycs <= MAX_PING_WAIT_CYCLES * 2) begin + if (cfg.alert_handler_vif.alert_ping_reqs > 0) begin + if (cfg.en_cov) begin + int alert_id = $clog2(cfg.alert_handler_vif.alert_ping_reqs); + cov.ping_with_lpg_cg_wrap[alert_id].alert_ping_with_lpg_cg.sample( + cfg.alert_host_cfg[alert_id].en_alert_lpg); + end + break; + end + if (cfg.alert_handler_vif.esc_ping_reqs > 0) break; + cfg.clk_rst_vif.wait_clks(1); + ping_wait_cycs++; + end + if (ping_wait_cycs > MAX_PING_WAIT_CYCLES * 2) begin + `uvm_error(`gfn, "Timeout occured waiting for a ping."); + end + if (cfg.en_cov) cov.cycles_between_pings_cg.sample(ping_wait_cycs); + + // Wait for ping request to finish to avoid infinite loop. + wait (cfg.alert_handler_vif.alert_ping_reqs == 0 && cfg.alert_handler_vif.esc_ping_reqs == 0); + endtask + + virtual task check_crashdump(); + forever begin + wait (cfg.under_reset == 0 && cfg.en_scb == 1); + @(cfg.crashdump_vif.pins) begin + alert_pkg::alert_crashdump_t crashdump_val = + alert_pkg::alert_crashdump_t'(cfg.crashdump_vif.sample()); + + // Wait two negedge clock cycles to make sure csr mirrored values are updated. + `DV_SPINWAIT_EXIT(cfg.clk_rst_vif.wait_n_clks(2);, wait (cfg.under_reset == 1);) + + if (!cfg.under_reset) begin + // If crashdump reached the phase programmed at `crashdump_trigger_shadowed`, + // `crashdump_o` value should keep stable until reset. + if (crashdump_triggered) begin + `uvm_fatal(`gfn, + "crashdump value should not change after trigger condition is reached!") + end + + foreach (crashdump_val.class_esc_state[i]) begin + uvm_reg crashdump_trigger_csr = ral.get_reg_by_name( + $sformatf("class%0s_crashdump_trigger_shadowed", class_name[i])); + if (crashdump_val.class_esc_state[i] == (`gmv(crashdump_trigger_csr) + 3'b100)) begin + crashdump_triggered[i] = 1; + if (cfg.en_cov) cov.crashdump_trigger_cg.sample(`gmv(crashdump_trigger_csr)); + break; + end + end + + for (int i = 0; i < NUM_ALERTS; i++) begin + `DV_CHECK_EQ(crashdump_val.alert_cause[i], `gmv(ral.alert_cause[i])) + end + for (int i = 0; i < NUM_LOCAL_ALERTS; i++) begin + `DV_CHECK_EQ(crashdump_val.loc_alert_cause[i], `gmv(ral.loc_alert_cause[i])) + end + end + end + end + endtask + + // a counter to count how long each interrupt pins stay high until it is being reset + // if counter exceeds threshold, call predict_esc() function to calculate related esc + virtual task check_intr_timeout_trigger_esc(); + for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin + fork + automatic int class_i = i; + begin : intr_sig_counter + forever @(under_intr_classes[class_i] && !under_esc_classes[class_i]) begin + fork + begin + bit [TL_DW-1:0] timeout_cyc, class_ctrl; + // if escalation cleared but interrupt not cleared, wait one more clk cycle for the + // FSM to reset to Idle, then start to count + if (clr_esc_under_intr[class_i]) cfg.clk_rst_vif.wait_n_clks(1); + clr_esc_under_intr[class_i] = 0; + // wait a clk for esc signal to go high + cfg.clk_rst_vif.wait_n_clks(1); + class_ctrl = get_class_ctrl(class_i); + if (class_ctrl[AlertClassCtrlEn] && + class_ctrl[AlertClassCtrlEnE3:AlertClassCtrlEnE0] > 0) begin + intr_cnter_per_class[class_i] = 1; + `uvm_info(`gfn, $sformatf("Class %0d start counter", class_i), UVM_HIGH) + timeout_cyc = get_class_timeout_cyc(class_i); + if (timeout_cyc > 0) begin + state_per_class[class_i] = EscStateTimeout; + while (under_intr_classes[class_i]) begin + @(cfg.clk_rst_vif.cbn); + if (intr_cnter_per_class[class_i] >= timeout_cyc) begin + predict_esc(class_i); + if (cfg.en_cov) cov.intr_timeout_cnt_cg.sample(class_i, timeout_cyc); + end + intr_cnter_per_class[class_i] += 1; + `uvm_info(`gfn, $sformatf("counter_%0d value: %0d", class_i, + intr_cnter_per_class[class_i]), UVM_HIGH) + end + end + intr_cnter_per_class[class_i] = 0; + end + end + begin + wait(under_esc_classes[class_i]); + end + join_any + disable fork; + end // end forever + end + join_none + end + endtask + + // two counters for phases cycle length and esc signals cycle length + // phase cycle cnter: "intr_cnter_per_class" is used to check "esc_cnt" registers + virtual task esc_phase_signal_cnter(); + for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin + fork + automatic int class_i = i; + begin : esc_phases_counter + forever @(!cfg.under_reset && under_esc_classes[class_i]) begin + fork + begin : inc_esc_cnt + for (int phase_i = 0; phase_i < NUM_ESC_PHASES; phase_i++) begin + int phase_thresh = `gmv(reg_esc_phase_cycs_per_class_q[class_i][phase_i]); + bit[TL_DW-1:0] class_ctrl = get_class_ctrl(class_i); + int enabled_sig_q[$]; + for (int sig_i = 0; sig_i < NUM_ESC_SIGNALS; sig_i++) begin + if (class_ctrl[sig_i*2+7 -: 2] == phase_i && class_ctrl[sig_i+2]) begin + enabled_sig_q.push_back(sig_i); + end + end + if (under_esc_classes[class_i]) begin + intr_cnter_per_class[class_i] = 1; + state_per_class[class_i] = esc_state_e'(phase_i + int'(EscStatePhase0)); + cfg.clk_rst_vif.wait_n_clks(1); + while (under_esc_classes[class_i] && + intr_cnter_per_class[class_i] < phase_thresh) begin + intr_cnter_per_class[class_i]++; + cfg.clk_rst_vif.wait_n_clks(1); + end + foreach (enabled_sig_q[i]) begin + int index = enabled_sig_q[i]; + if (esc_sig_class[index] == (class_i + 1)) esc_signal_release[index] = 1; + end + end + end // end four phases + intr_cnter_per_class[class_i] = 0; + if (under_esc_classes[class_i]) state_per_class[class_i] = EscStateTerminal; + end + begin + wait(cfg.under_reset || !under_esc_classes[class_i]); + if (!under_esc_classes[class_i]) begin + // wait 1 clk cycles until esc_signal_release is set + cfg.clk_rst_vif.wait_clks(1); + end + end + join_any + disable fork; + intr_cnter_per_class[class_i] = 0; + end // end forever + end + join_none + end + endtask + + // release escalation signal after one clock cycle, to ensure happens at the end of the clock + // cycle, waited 1 clks here + virtual task release_esc_signal(); + for (int i = 0; i < NUM_ESC_SIGNALS; i++) begin + fork + automatic int sig_i = i; + forever @ (esc_signal_release[sig_i]) begin + cfg.clk_rst_vif.wait_clks(1); + esc_sig_class[sig_i] = 0; + esc_signal_release[sig_i] = 0; + end + join_none + end + endtask + + virtual function void reset(string kind = "HARD"); + super.reset(kind); + under_intr_classes = '{default:0}; + intr_cnter_per_class = '{default:0}; + under_esc_classes = '{default:0}; + esc_sig_class = '{default:0}; + accum_cnter_per_class = '{default:0}; + state_per_class = '{default:EscStateIdle}; + clr_esc_under_intr = 0; + crashdump_triggered = 0; + ping_timer_en = 0; + last_triggered_alert_per_class = '{default:$realtime}; + endfunction + + // clear accumulative counters, and escalation counters if they are under escalation + // interrupt timeout counters cannot be cleared by this + task clr_reset_esc_class(int i); + fork + automatic int class_i = i; + begin + cfg.clk_rst_vif.wait_clks(1); + crashdump_triggered[class_i] = 0; + if (under_intr_classes[class_i]) begin + if (cfg.en_cov) cov.clear_intr_cnt_cg.sample(class_i); + clr_esc_under_intr[class_i] = 1; + end + if (under_esc_classes [class_i]) begin + if (cfg.en_cov) cov.clear_esc_cnt_cg.sample(class_i); + intr_cnter_per_class[class_i] = 0; + end + under_esc_classes[class_i] = 0; + cfg.clk_rst_vif.wait_n_clks(1); + last_triggered_alert_per_class[class_i] = $realtime; + accum_cnter_per_class[class_i] = 0; + if (state_per_class[class_i] != EscStateTimeout) state_per_class[class_i] = EscStateIdle; + end + join_none + endtask + + function void check_phase(uvm_phase phase); + super.check_phase(phase); + endfunction + + // get class_ctrl register mirrored value by class + function bit [TL_DW-1:0] get_class_ctrl(int class_i); + uvm_reg class_ctrl_rg; + class_ctrl_rg = ral.get_reg_by_name($sformatf("class%s_ctrl_shadowed", class_name[class_i])); + `DV_CHECK_NE_FATAL(class_ctrl_rg, null) + return class_ctrl_rg.get_mirrored_value(); + endfunction + + // get class_accum_thresh register mirrored value by class + function bit [TL_DW-1:0] get_class_accum_thresh(int class_i); + uvm_reg class_thresh_rg; + class_thresh_rg = ral.get_reg_by_name($sformatf("class%s_accum_thresh_shadowed", + class_name[class_i])); + `DV_CHECK_NE_FATAL(class_thresh_rg, null) + return class_thresh_rg.get_mirrored_value(); + endfunction + + // get class_timeout_cyc register mirrored value by class + function bit [TL_DW-1:0] get_class_timeout_cyc(int class_i); + dv_base_reg class_timeout_rg = + ral.get_dv_base_reg_by_name($sformatf("class%s_timeout_cyc_shadowed", + class_name[class_i])); + return class_timeout_rg.get_mirrored_value(); + endfunction + + function bit shadowed_reg_wr_completed(dv_base_reg dv_base_reg); + return (!dv_base_reg.is_staged() && !dv_base_reg.get_shadow_update_err()); + endfunction + +endclass +`undef ASSIGN_CLASS_PHASE_REGS diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_virtual_sequencer.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_virtual_sequencer.sv new file mode 100644 index 0000000000000..431f2a660cd34 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/alert_handler_virtual_sequencer.sv @@ -0,0 +1,16 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_handler_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(alert_handler_env_cfg), + .COV_T(alert_handler_env_cov) + ); + alert_esc_sequencer alert_host_seqr_h[]; + alert_esc_sequencer esc_device_seqr_h[]; + + `uvm_component_utils(alert_handler_virtual_sequencer) + + `uvm_component_new + +endclass diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_alert_accum_saturation_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_alert_accum_saturation_vseq.sv new file mode 100644 index 0000000000000..7420b13e35376 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_alert_accum_saturation_vseq.sv @@ -0,0 +1,108 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This sequence force the alert accumulation count to large value, then check if the accum count +// will saturate and won't overflow. + +`define CLASS_CNT_PATH(class_i, i) \ + string class_``class_i``_path_0 = \ + "tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[0]"; \ + string class_``class_i``_path_1 = \ + "tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[1]"; + +`define CHECK_ALERT_ACCUM_CNT(class_i, i) \ + csr_rd_check(.ptr(ral.class``class_i``_accum_cnt), \ + .compare_value(saturated_class == ``i`` ? \ + MAX_ACCUM_CNT : MAX_ACCUM_CNT - num_alerts_to_saturate)); + +class alert_handler_alert_accum_saturation_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_alert_accum_saturation_vseq) + + `uvm_object_new + + parameter uint MAX_ACCUM_CNT = 'hffff; + rand int num_alerts_to_saturate; + rand bit [1:0] saturated_class; // only 4 classes: a, b, c, d + + `CLASS_CNT_PATH(a, 0) + `CLASS_CNT_PATH(b, 1) + `CLASS_CNT_PATH(c, 2) + `CLASS_CNT_PATH(d, 3) + + constraint num_alerts_to_saturate_c { + num_alerts_to_saturate inside {[1 : 10]}; + $countones(alert_trigger) == 1; + } + + function void pre_randomize(); + this.enable_one_alert_c.constraint_mode(0); + this.enable_classa_only_c.constraint_mode(0); + endfunction + + virtual task pre_start(); + // Force accum counts to a large value. + `DV_CHECK(uvm_hdl_force(class_a_path_0, (MAX_ACCUM_CNT - num_alerts_to_saturate))); + `DV_CHECK(uvm_hdl_force(class_a_path_1, (num_alerts_to_saturate))); + + `DV_CHECK(uvm_hdl_force(class_b_path_0, (MAX_ACCUM_CNT - num_alerts_to_saturate))); + `DV_CHECK(uvm_hdl_force(class_b_path_1, (num_alerts_to_saturate))); + + `DV_CHECK(uvm_hdl_force(class_c_path_0, (MAX_ACCUM_CNT - num_alerts_to_saturate))); + `DV_CHECK(uvm_hdl_force(class_c_path_1, (num_alerts_to_saturate))); + + `DV_CHECK(uvm_hdl_force(class_d_path_0, (MAX_ACCUM_CNT - num_alerts_to_saturate))); + `DV_CHECK(uvm_hdl_force(class_d_path_1, (num_alerts_to_saturate))); + + super.pre_start(); + endtask + + virtual task body(); + // Assign all alerts to one class. + foreach (alert_class_map[i]) alert_class_map[i] = saturated_class; + alert_handler_init(.intr_en('1), + .alert_en('1), + .alert_class(alert_class_map), + .loc_alert_en(0), + .loc_alert_class(0)); + csr_wr(ral.classa_accum_thresh_shadowed, '1); + csr_wr(ral.classb_accum_thresh_shadowed, '1); + csr_wr(ral.classc_accum_thresh_shadowed, '1); + csr_wr(ral.classd_accum_thresh_shadowed, '1); + + // Enable and lock all alert classes. + csr_wr(ral.classa_ctrl_shadowed.en, 1); + csr_wr(ral.classb_ctrl_shadowed.en, 1); + csr_wr(ral.classc_ctrl_shadowed.en, 1); + csr_wr(ral.classd_ctrl_shadowed.en, 1); + + `DV_CHECK(uvm_hdl_release(class_a_path_0)); + `DV_CHECK(uvm_hdl_release(class_a_path_1)); + `DV_CHECK(uvm_hdl_release(class_b_path_0)); + `DV_CHECK(uvm_hdl_release(class_b_path_1)); + `DV_CHECK(uvm_hdl_release(class_c_path_0)); + `DV_CHECK(uvm_hdl_release(class_c_path_1)); + `DV_CHECK(uvm_hdl_release(class_d_path_0)); + `DV_CHECK(uvm_hdl_release(class_d_path_1)); + + `uvm_info(`gfn, $sformatf("Saturate class %0d, alerts to saturate %0d", saturated_class, + num_alerts_to_saturate), UVM_LOW) + + // First round will reach the max count value, afterwards check if the max value saturates and + // won't overflow. + repeat ($urandom_range(2, 5)) begin + repeat (num_alerts_to_saturate) begin + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(alert_trigger) + drive_alert(alert_trigger, alert_int_err); + csr_rd_check(.ptr(ral.intr_state), .compare_value(1 << saturated_class)); + csr_wr(.ptr(ral.intr_state), .value(1 << saturated_class)); + end + + `CHECK_ALERT_ACCUM_CNT(a, 0) + `CHECK_ALERT_ACCUM_CNT(b, 1) + `CHECK_ALERT_ACCUM_CNT(c, 2) + `CHECK_ALERT_ACCUM_CNT(d, 3) + end + endtask + +endclass : alert_handler_alert_accum_saturation_vseq diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv new file mode 100644 index 0000000000000..58f6f549f3e65 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv @@ -0,0 +1,353 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`define RAND_AND_WR_CLASS_PHASES_CYCLE(i) \ + `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_phase0_cyc_shadowed, \ + class``i``_phase0_cyc_shadowed.value inside {[0: max_phase_cyc]};); \ + `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_phase1_cyc_shadowed, \ + class``i``_phase1_cyc_shadowed.value inside {[0: max_phase_cyc]};); \ + `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_phase2_cyc_shadowed, \ + class``i``_phase2_cyc_shadowed.value inside {[0: max_phase_cyc]};); \ + `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_phase3_cyc_shadowed, \ + class``i``_phase3_cyc_shadowed.value inside {[0: max_phase_cyc]};); \ + csr_update(ral.class``i``_phase0_cyc_shadowed); \ + csr_update(ral.class``i``_phase1_cyc_shadowed); \ + csr_update(ral.class``i``_phase2_cyc_shadowed); \ + csr_update(ral.class``i``_phase3_cyc_shadowed); + +`define RAND_WRITE_CLASS_CTRL(i, en_bit, lock_bit) \ + `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_ctrl_shadowed, \ + en.value == en_bit; lock.value == lock_bit;) \ + csr_wr(.ptr(ral.class``i``_ctrl_shadowed), .value(ral.class``i``_ctrl_shadowed.get())); + +class alert_handler_base_vseq extends cip_base_vseq #( + .CFG_T (alert_handler_env_cfg), + .RAL_T (alert_handler_reg_block), + .COV_T (alert_handler_env_cov), + .VIRTUAL_SEQUENCER_T (alert_handler_virtual_sequencer) + ); + `uvm_object_utils(alert_handler_base_vseq) + + // various knobs to enable certain routines + bit do_alert_handler_init = 1'b0; + bit config_locked = 1'b0; + + `uvm_object_new + + virtual task dut_init(string reset_kind = "HARD"); + cfg.alert_handler_vif.init(); + super.dut_init(); + if (do_alert_handler_init) alert_handler_init(); + config_locked = 0; + endtask + + virtual task dut_shutdown(); + // nothing special yet + endtask + + // setup basic alert_handler features + // alert_class default 0 -> all alert will trigger interrupt classA + virtual task alert_handler_init( + bit [NUM_ALERT_CLASSES-1:0] intr_en = '1, + bit [NUM_ALERTS-1:0] alert_en = '1, + bit [NUM_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] alert_class = 'h0, + bit [NUM_LOCAL_ALERTS-1:0] loc_alert_en = '1, + bit [NUM_LOCAL_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] loc_alert_class = 'h0); + + csr_wr(.ptr(ral.intr_enable), .value(intr_en)); + foreach (alert_en[i]) csr_wr(.ptr(ral.alert_en_shadowed[i]), + .value(alert_en[i])); + foreach (alert_class[i]) csr_wr(.ptr(ral.alert_class_shadowed[i]), + .value(alert_class[i])); + foreach (loc_alert_en[i]) csr_wr(.ptr(ral.loc_alert_en_shadowed[i]), + .value(loc_alert_en[i])); + foreach (loc_alert_class[i]) csr_wr(.ptr(ral.loc_alert_class_shadowed[i]), + .value(loc_alert_class[i])); + endtask + + virtual task alert_handler_rand_wr_class_ctrl(bit [NUM_ALERT_CLASSES-1:0] lock_bit, + bit [NUM_ALERT_CLASSES-1:0] class_en); + `RAND_WRITE_CLASS_CTRL(a, class_en[0], lock_bit[0]) + `RAND_WRITE_CLASS_CTRL(b, class_en[1], lock_bit[1]) + `RAND_WRITE_CLASS_CTRL(c, class_en[2], lock_bit[2]) + `RAND_WRITE_CLASS_CTRL(d, class_en[3], lock_bit[3]) + endtask + + virtual task alert_handler_wr_regwen_regs(bit [NUM_ALERT_CLASSES-1:0] regwen = 0, + bit [NUM_ALERTS-1:0] alert_regwen = 0, + bit [NUM_LOCAL_ALERTS-1:0] loc_alert_regwen = 0, + bit ping_timer_regwen = 0, + bit [NUM_ALERT_CLASSES-1:0] class_regwen = 0); + + csr_wr(.ptr(ral.classa_clr_regwen), .value(regwen[0])); + csr_wr(.ptr(ral.classb_clr_regwen), .value(regwen[1])); + csr_wr(.ptr(ral.classc_clr_regwen), .value(regwen[2])); + csr_wr(.ptr(ral.classd_clr_regwen), .value(regwen[3])); + + foreach (alert_regwen[i]) csr_wr(.ptr(ral.alert_regwen[i]), .value(alert_regwen[i])); + + foreach (loc_alert_regwen[i]) begin + csr_wr(.ptr(ral.loc_alert_regwen[i]), .value(loc_alert_regwen[i])); + end + + csr_wr(.ptr(ral.ping_timer_regwen), .value(ping_timer_regwen)); + + csr_wr(.ptr(ral.classa_regwen), .value(class_regwen[0])); + csr_wr(.ptr(ral.classb_regwen), .value(class_regwen[1])); + csr_wr(.ptr(ral.classc_regwen), .value(class_regwen[2])); + csr_wr(.ptr(ral.classd_regwen), .value(class_regwen[3])); + endtask + + // If do_lock_config is set, write value 1 to ping_timer_en register. + // If not set, this task has 50% of chance to write value 1 to ping_timer_en register. + virtual task lock_config(bit do_lock_config); + if (do_lock_config || $urandom_range(0, 1)) begin + csr_wr(.ptr(ral.ping_timer_en_shadowed), .value(do_lock_config)); + end + endtask + + virtual task drive_alert(bit[NUM_ALERTS-1:0] alert_trigger, bit[NUM_ALERTS-1:0] alert_int_err); + fork + begin : isolation_fork + foreach (alert_trigger[i]) begin + if (alert_trigger[i]) begin + automatic int index = i; + fork + begin + alert_sender_seq alert_seq; + `uvm_create_on(alert_seq, p_sequencer.alert_host_seqr_h[index]); + `DV_CHECK_RANDOMIZE_WITH_FATAL(alert_seq, int_err == alert_int_err[index];) + `uvm_send(alert_seq) + end + join_none + end + end + wait fork; + end + join + endtask + + // This sequence will drive standalone esc_resp_p/n without esc_p/n + virtual task drive_esc_rsp(bit [NUM_ESCS-1:0] esc_int_errs); + fork + begin : isolation_fork + foreach (cfg.esc_device_cfg[i]) begin + automatic int index = i; + if (esc_int_errs[index]) begin + fork + begin + esc_receiver_esc_rsp_seq esc_seq = + esc_receiver_esc_rsp_seq::type_id::create("esc_seq"); + `DV_CHECK_RANDOMIZE_WITH_FATAL(esc_seq, int_err == 1; standalone_int_err == 1; + ping_timeout == 0;) + esc_seq.start(p_sequencer.esc_device_seqr_h[index]); + end + join_none + end + end + wait fork; + end + join + endtask + + // alert_handler scb will compare the read value with expected value + // Not using "clear_all_interrupts" function in cip_base_vseq because of the signal interity + // error: after clearing intr_state, intr_state might come back to 1 in the next cycle. + virtual task check_alert_interrupts(); + bit [TL_DW-1:0] intr; + // Wait until there is no ping handshake. + // This will avoid the case where interrupt is set and cleared at the same cycle. + `DV_WAIT((cfg.alert_handler_vif.alert_ping_reqs || cfg.alert_handler_vif.esc_ping_reqs) == 0) + csr_rd(.ptr(ral.intr_state), .value(intr)); + `DV_WAIT((cfg.alert_handler_vif.alert_ping_reqs || cfg.alert_handler_vif.esc_ping_reqs) == 0) + csr_wr(.ptr(ral.intr_state), .value('1)); + endtask + + virtual task clear_esc(); + csr_wr(.ptr(ral.classa_clr_shadowed), .value(1)); + csr_wr(.ptr(ral.classb_clr_shadowed), .value(1)); + csr_wr(.ptr(ral.classc_clr_shadowed), .value(1)); + csr_wr(.ptr(ral.classd_clr_shadowed), .value(1)); + endtask + + // checking for csr_rd is done in scb + virtual task read_alert_cause(); + bit [TL_DW-1:0] alert_cause; + foreach (ral.alert_cause[i]) begin + if ($urandom_range(0, 1)) begin + csr_rd(.ptr(ral.alert_cause[i]), .value(alert_cause)); + end + end + foreach (ral.loc_alert_cause[i]) begin + if ($urandom_range(0, 1)) begin + csr_rd(.ptr(ral.loc_alert_cause[i]), .value(alert_cause)); + end + end + endtask + + virtual task read_esc_status(); + bit [TL_DW-1:0] csr_val; + csr_rd(.ptr(ral.classa_accum_cnt), .value(csr_val)); + csr_rd(.ptr(ral.classb_accum_cnt), .value(csr_val)); + csr_rd(.ptr(ral.classc_accum_cnt), .value(csr_val)); + csr_rd(.ptr(ral.classd_accum_cnt), .value(csr_val)); + + csr_rd(.ptr(ral.classa_state), .value(csr_val)); + csr_rd(.ptr(ral.classb_state), .value(csr_val)); + csr_rd(.ptr(ral.classc_state), .value(csr_val)); + csr_rd(.ptr(ral.classd_state), .value(csr_val)); + + csr_rd(.ptr(ral.classa_esc_cnt), .value(csr_val)); + csr_rd(.ptr(ral.classb_esc_cnt), .value(csr_val)); + csr_rd(.ptr(ral.classc_esc_cnt), .value(csr_val)); + csr_rd(.ptr(ral.classd_esc_cnt), .value(csr_val)); + endtask + + virtual task wait_alert_handshake_done(); + cfg.clk_rst_vif.wait_clks(2); + foreach (cfg.alert_host_cfg[i]) begin + if (!cfg.alert_host_cfg[i].en_alert_lpg) cfg.alert_host_cfg[i].vif.wait_ack_complete(); + end + endtask + + virtual function bit check_esc_done(bit[TL_DW-1:0] vals[$]); + foreach (vals[i]) begin + esc_state_e val = esc_state_e'(vals[i]); + if (val inside {EscStatePhase0, EscStatePhase1, EscStatePhase2, EscStatePhase3}) return 0; + end + return 1; + endfunction + + virtual task wait_esc_handshake_done(); + bit [TL_DW-1:0] csr_vals[4]; + do begin + csr_rd(.ptr(ral.classa_state), .value(csr_vals[0])); + csr_rd(.ptr(ral.classb_state), .value(csr_vals[1])); + csr_rd(.ptr(ral.classc_state), .value(csr_vals[2])); + csr_rd(.ptr(ral.classd_state), .value(csr_vals[3])); + end while (!check_esc_done(csr_vals)); + // check if there is any esc ping + foreach (cfg.esc_device_cfg[i]) cfg.esc_device_cfg[i].vif.wait_esc_complete(); + endtask + + // This task wait until any alert or esc protocol received a ping from LFSR. + // This task will also return the protocol index: + // alert index starts from 1; esc index stats from NUM_ALERTS + virtual task wait_alert_esc_ping(ref int ping_index); + int ping_i; + fork + begin : isolation_fork + foreach (cfg.alert_host_cfg[i]) begin + automatic int index = i; + fork + begin + cfg.alert_host_cfg[index].vif.wait_alert_ping(); + ping_i = index + 1; + end + join_none + end + foreach (cfg.esc_device_cfg[i]) begin + automatic int index = i; + fork + begin + cfg.esc_device_cfg[index].vif.wait_esc_ping(); + ping_i = index + NUM_ALERTS + 1; + end + join_none + end + wait (ping_i > 0); + disable fork; + ping_index = ping_i; + end + join + endtask + + function void enable_lpg_group(bit [NUM_ALERTS-1:0] alert_en_i); + foreach (alert_en_i[i]) begin + if (alert_en_i[i]) set_alert_lpg(i); + end + endfunction + + // Enable alert's LPG based on alert_i input. + // + // Only enable this alert's LPG if the lgp input `lpg_cg_en` or `lpg_rst_en` if not Mubi4True. + // Because one LPG will turn off a set of alert sensers. So this task will also set all LPG's + // alert_host_cfgs' `en_alert_lpg` to 1. + virtual function void set_alert_lpg(int alert_i); + int lpg_i = alert_handler_reg_pkg::LpgMap[alert_i]; + bit [1:0] set_lpg; + + if (cfg.alert_handler_vif.get_lpg_status(lpg_i) == 0) begin + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(set_lpg, set_lpg > 0;); + if (set_lpg[0]) cfg.alert_handler_vif.set_lpg_cg_en(lpg_i); + if (set_lpg[1]) cfg.alert_handler_vif.set_lpg_rst_en(lpg_i); + foreach (alert_handler_reg_pkg::LpgMap[i]) begin + if (alert_handler_reg_pkg::LpgMap[i] == lpg_i) cfg.alert_host_cfg[i].en_alert_lpg = 1; + end + end + endfunction + + virtual task alert_handler_crashdump_phases(bit [1:0] classa_phase = $urandom(), + bit [1:0] classb_phase = $urandom(), + bit [1:0] classc_phase = $urandom(), + bit [1:0] classd_phase = $urandom()); + csr_wr(.ptr(ral.classa_crashdump_trigger_shadowed), .value(classa_phase)); + csr_wr(.ptr(ral.classb_crashdump_trigger_shadowed), .value(classb_phase)); + csr_wr(.ptr(ral.classc_crashdump_trigger_shadowed), .value(classc_phase)); + csr_wr(.ptr(ral.classd_crashdump_trigger_shadowed), .value(classd_phase)); + endtask + + virtual task wr_phases_cycle(int max_phase_cyc); + `RAND_AND_WR_CLASS_PHASES_CYCLE(a); + `RAND_AND_WR_CLASS_PHASES_CYCLE(b); + `RAND_AND_WR_CLASS_PHASES_CYCLE(c); + `RAND_AND_WR_CLASS_PHASES_CYCLE(d); + endtask + + virtual task wr_intr_timeout_cycle(bit[TL_DW-1:0] intr_timeout_cyc[NUM_ALERT_CLASSES]); + csr_wr(.ptr(ral.classa_timeout_cyc_shadowed), .value(intr_timeout_cyc[0])); + csr_wr(.ptr(ral.classb_timeout_cyc_shadowed), .value(intr_timeout_cyc[1])); + csr_wr(.ptr(ral.classc_timeout_cyc_shadowed), .value(intr_timeout_cyc[2])); + csr_wr(.ptr(ral.classd_timeout_cyc_shadowed), .value(intr_timeout_cyc[3])); + endtask + + virtual task wr_class_accum_threshold(bit[TL_DW-1:0] accum_thresh[NUM_ALERT_CLASSES]); + csr_wr(.ptr(ral.classa_accum_thresh_shadowed), .value(accum_thresh[0])); + csr_wr(.ptr(ral.classb_accum_thresh_shadowed), .value(accum_thresh[1])); + csr_wr(.ptr(ral.classc_accum_thresh_shadowed), .value(accum_thresh[2])); + csr_wr(.ptr(ral.classd_accum_thresh_shadowed), .value(accum_thresh[3])); + endtask + + virtual task wr_ping_timeout_cycle(bit[TL_DW-1:0] timeout_val); + csr_wr(.ptr(ral.ping_timeout_cyc_shadowed), .value(timeout_val)); + if (`gmv(ral.ping_timer_regwen)) begin + if (timeout_val == 0) timeout_val = 1; + foreach (cfg.alert_host_cfg[i]) cfg.alert_host_cfg[i].ping_timeout_cycle = timeout_val; + foreach (cfg.esc_device_cfg[i]) cfg.esc_device_cfg[i].ping_timeout_cycle = timeout_val; + end + endtask + + // This sequence will automatically response to all escalation ping and esc responses + virtual task run_esc_rsp_seq_nonblocking(bit [NUM_ESCS-1:0] esc_int_errs = '0, + bit [NUM_ESCS-1:0] ping_timeout_errs = '0); + foreach (cfg.esc_device_cfg[i]) begin + automatic int index = i; + fork + forever begin + bit esc_int_err = esc_int_errs[index] ? $urandom_range(0, 1) : 0; + bit ping_timeout_err = ping_timeout_errs[index] ? $urandom_range(0, 1) : 0; + esc_receiver_esc_rsp_seq esc_seq = + esc_receiver_esc_rsp_seq::type_id::create("esc_seq"); + `DV_CHECK_RANDOMIZE_WITH_FATAL(esc_seq, int_err == esc_int_err; standalone_int_err == 0; + ping_timeout == ping_timeout_err;) + esc_seq.start(p_sequencer.esc_device_seqr_h[index]); + end + join_none + end + endtask + +endclass : alert_handler_base_vseq + +`undef RAND_AND_WR_CLASS_PHASES_CYCLE +`undef RAND_WRITE_CLASS_CTRL diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_common_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_common_vseq.sv new file mode 100644 index 0000000000000..fc76795637a3e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_common_vseq.sv @@ -0,0 +1,172 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_handler_common_vseq extends alert_handler_base_vseq; + `uvm_object_utils(alert_handler_common_vseq) + + constraint num_trans_c { + num_trans inside {[1:2]}; + } + + `uvm_object_new + + virtual task pre_start(); + super.pre_start(); + if (common_seq_type == "tl_intg_err") begin + // If `en_csr_vseq_w_tl_intg = 1`, this vseq will check tl intg error won't affect any other + // tl transaction. + // If `en_csr_vseq_w_tl_intg = 0`, this vseq will check status, interrupts, and class_count + // registers are updated correctly by DUT. + en_csr_vseq_w_tl_intg = $urandom_range(0, 1); + `uvm_info(`gfn, $sformatf("en_csr_vseq_w_tl_intg = %0b", en_csr_vseq_w_tl_intg), UVM_MEDIUM) + end + endtask + + virtual task body(); + // run alert/esc ping response sequences without error or timeout to prevent triggering local + // alert failure + run_esc_rsp_seq_nonblocking(0); + run_common_vseq_wrapper(num_trans); + endtask : body + + // If the tl_intg_err sequence does not run csr_rw in parallel, enable loc_alert error and enable + // interrupts. + // If the tl_intg_err sequence runs with csr_rw, do not enable loc_alert because it might trigger + // escalation and affect register predications. + virtual task run_tl_intg_err_vseq_sub(string ral_name); + if (en_csr_vseq_w_tl_intg == 0) begin + csr_wr(.ptr(ral.loc_alert_en_shadowed[LocalBusIntgFail]), + .value($urandom_range(0, 1)), + .predict(1)); + csr_wr(.ptr(ral.loc_alert_class_shadowed[LocalBusIntgFail]), + .value($urandom_range(0, 3)), + .predict(1)); + csr_wr(.ptr(ral.classa_ctrl_shadowed.en), .value(1)); + csr_wr(.ptr(ral.classb_ctrl_shadowed.en), .value(1)); + csr_wr(.ptr(ral.classc_ctrl_shadowed.en), .value(1)); + csr_wr(.ptr(ral.classd_ctrl_shadowed.en), .value(1)); + end + super.run_tl_intg_err_vseq_sub(ral_name); + endtask + + // Override the task to check corresponding CSR status is updated correctly. + virtual task check_tl_intg_error_response(); + bit exp_val = `gmv(ral.loc_alert_en_shadowed[LocalBusIntgFail]); + csr_rd_check(.ptr(ral.loc_alert_cause[LocalBusIntgFail]), .compare_value(exp_val)); + + // Only check interrupt, accumlate count, and alert_cause registers if the local alert is + // enabled. + // However, this task does not check escalation port because the common escalation path is + // checked in other tests that enabled scb. + if (exp_val == 1) begin + bit [TL_DW-1:0] class_i = `gmv(ral.loc_alert_class_shadowed[LocalBusIntgFail]); + bit [TL_DW-1:0] accum_cnt; + csr_rd_check(.ptr(ral.intr_state), .compare_value(1'b1 << class_i)); + case (class_i) + 0: csr_rd(.ptr(ral.classa_accum_cnt), .value(accum_cnt)); + 1: csr_rd(.ptr(ral.classb_accum_cnt), .value(accum_cnt)); + 2: csr_rd(.ptr(ral.classc_accum_cnt), .value(accum_cnt)); + 3: csr_rd(.ptr(ral.classd_accum_cnt), .value(accum_cnt)); + default: `uvm_fatal(`gfn, $sformatf("Invalid class index %0d", class_i)) + endcase + // Once tl_intg_err triggered, the error will be set to 1 until reset, so the counter will + // continuously increment. + `DV_CHECK_LT(0, accum_cnt, "Accumulated count should be larger than 0"); + end + endtask + + // If the common sequence is tl integrity error sequence, we override this task to disable local + // alert for tl_intg_err and lock this register. Because tl_intg_err can trigger local alert and + // eventually triggers escalation. Then the auto predications for escalation related registers + // such as `class_clr` and `clr_regwen` registers are not correct. + virtual task run_csr_vseq(string csr_test_type, + int num_test_csrs = 0, + bit do_rand_wr_and_reset = 1, + dv_base_reg_block models[$] = {}, + string ral_name = ""); + if (common_seq_type == "tl_intg_err") begin + csr_wr(.ptr(ral.loc_alert_regwen[LocalBusIntgFail]), .value(0), .predict(1)); + end + super.run_csr_vseq(csr_test_type, num_test_csrs, do_rand_wr_and_reset, models, ral_name); + endtask + + virtual function void predict_shadow_reg_status(bit predict_update_err = 0, + bit predict_storage_err = 0); + if (predict_update_err) begin + foreach (cfg.shadow_update_err_status_fields[status_field]) begin + if (`gmv(ral.loc_alert_en_shadowed[LocalShadowRegUpdateErr])) begin + void'(status_field.predict(cfg.shadow_update_err_status_fields[status_field])); + end + end + end + if (predict_storage_err) begin + foreach (cfg.shadow_storage_err_status_fields[status_field]) begin + if (`gmv(ral.loc_alert_en_shadowed[LocalShadowRegStorageErr])) begin + void'(status_field.predict(cfg.shadow_storage_err_status_fields[status_field])); + end + end + end + endfunction + + virtual task check_sec_cm_fi_resp(sec_cm_base_if_proxy if_proxy); + if (!uvm_re_match("tb.dut.u_ping_timer.*", if_proxy.path)) begin + bit val; + csr_rd(.ptr(ral.loc_alert_cause[LocalAlertPingFail]), .value(val)); + `DV_CHECK_EQ(val, 1, "local alert ping fail mismatch") + csr_rd(.ptr(ral.loc_alert_cause[LocalEscPingFail]), .value(val)); + `DV_CHECK_EQ(val, 1, "local escalation ping fail mismatch") + end else begin + foreach (cfg.esc_device_cfg[i]) begin + `DV_CHECK_EQ(cfg.esc_device_cfg[i].vif.esc_tx.esc_p, 1, + $sformatf("escalation protocol_%0d is not set", i)); + end + end + // Let the simulation wait a few clock cycles before reset to make sure assertions are checked. + cfg.clk_rst_vif.wait_clks($urandom_range(2, 10)); + endtask + + virtual task sec_cm_inject_fault(sec_cm_base_if_proxy if_proxy); + if (!uvm_re_match("tb.dut.u_ping_timer.*", if_proxy.path)) begin + // Enable ping timer to get ping counter error + csr_wr(ral.ping_timer_en_shadowed, 1); + + // Enable loc_alerts + foreach (ral.loc_alert_en_shadowed[i]) csr_wr(ral.loc_alert_en_shadowed[i], 1); + end + super.sec_cm_inject_fault(if_proxy); + endtask : sec_cm_inject_fault + + virtual task pre_run_sec_cm_fi_vseq(); + // Disable prim_sparse_fsm assertions. + $assertoff(0, "tb.dut.gen_classes[0].u_esc_timer.CheckEn_A"); + $assertoff(0, "tb.dut.gen_classes[1].u_esc_timer.CheckEn_A"); + $assertoff(0, "tb.dut.gen_classes[2].u_esc_timer.CheckEn_A"); + $assertoff(0, "tb.dut.gen_classes[3].u_esc_timer.CheckEn_A"); + + // Disable the EscStateOut_A assertion while we do FI checks. This assertion checks that an FSM + // state matches an output signal, but this can totally fail to be true if we're forcing either + // side. + $assertoff(0, "tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A"); + $assertoff(0, "tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A"); + $assertoff(0, "tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A"); + $assertoff(0, "tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A"); + + // Because the assertion contains `=>` statement. + // Wait one clock cycle until the assertions are fully disabled. + cfg.clk_rst_vif.wait_clks(1); + endtask : pre_run_sec_cm_fi_vseq + + virtual task post_run_sec_cm_fi_vseq(); + // Enable all the assertions that pre_run_sec_cm_fi_vseq disabled + $asserton(0, "tb.dut.gen_classes[0].u_esc_timer.CheckEn_A"); + $asserton(0, "tb.dut.gen_classes[1].u_esc_timer.CheckEn_A"); + $asserton(0, "tb.dut.gen_classes[2].u_esc_timer.CheckEn_A"); + $asserton(0, "tb.dut.gen_classes[3].u_esc_timer.CheckEn_A"); + $assertoff(0, "tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A"); + $assertoff(0, "tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A"); + $assertoff(0, "tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A"); + $assertoff(0, "tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A"); + endtask : post_run_sec_cm_fi_vseq + +endclass diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_stress_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_stress_vseq.sv new file mode 100644 index 0000000000000..b36e43178b82d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_stress_vseq.sv @@ -0,0 +1,103 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This sequence uses a fixed setting to enable all alerts and locks them to class A. +// Then enable all local alerts and locks them to class B. +// Randomly force the `wait_cyc_mask_i` from design to a valid small number to fasten the ping +// request mechanism. +// Finally this sequence wait until alerts are pinged certain times. +class alert_handler_entropy_stress_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_entropy_stress_vseq) + + `uvm_object_new + + rand bit [7:0] forced_mask_val; + rand int num_pings; + + constraint valid_mask_val_c { + forced_mask_val >= 'h7; + $onehot(32'(forced_mask_val) + 1) == 1; + } + + constraint num_pings_c { + if (forced_mask_val > 'hf0) { + num_pings inside {[1 : 2]}; + } else { + num_pings inside {[1 : 3]}; + } + } + + virtual task pre_start(); + `DV_CHECK_RANDOMIZE_FATAL(this) + cfg.alert_handler_vif.set_wait_cyc_mask(forced_mask_val); + + foreach (cfg.alert_host_cfg[i]) begin + cfg.alert_host_cfg[i].alert_delay_max = 0; + cfg.alert_host_cfg[i].ping_delay_max = 0; + end + super.pre_start(); + endtask + + task body(); + bit [NUM_LOCAL_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] loc_alert_class; + + foreach (loc_alert_class[i]) loc_alert_class[i] = 1; + + `uvm_info(`gfn, "Test started", UVM_LOW) + + run_esc_rsp_seq_nonblocking(); + + alert_handler_init(.intr_en('1), // Enable all interrupts + .alert_en('1), // Enable all alerts + .alert_class(0), // Set all alerts to class A + .loc_alert_en('1), // Enable all local alerts + .loc_alert_class(loc_alert_class)); // Set all local alerts to class B + + // Enable all classes and lock them. + alert_handler_rand_wr_class_ctrl('1, '1); + + // Enable ping timer. + csr_wr(.ptr(ral.ping_timer_en_shadowed), .value(1)); + + // Lock alerts and configurations. + alert_handler_wr_regwen_regs(.regwen(0), + .alert_regwen(0), + .loc_alert_regwen(0), + .ping_timer_regwen(0), + .class_regwen(0)); + + // Wait for all alerts to be pinged at least once. + fork begin : isolation_fork + int num_alerts = NUM_ALERTS; + for (int i = 0; i < NUM_ALERTS; i++) begin + automatic int index = i; + fork begin + repeat (num_pings) cfg.alert_host_cfg[index].vif.wait_alert_ping(); + num_alerts--; + `uvm_info(`gfn, $sformatf("alert %0d received %0d ping request.\n %0d alerts remaining.", + index, num_pings, num_alerts), UVM_LOW); + end join_none + end + wait fork; + end join + + cfg.clk_rst_vif.wait_clks($urandom_range(50, 500)); + + // Check no error or local alerts triggered. + foreach (ral.alert_cause[i]) begin + csr_rd_check(.ptr(ral.alert_cause[i]), .compare_value(0)); + end + foreach (ral.loc_alert_cause[i]) begin + csr_rd_check(.ptr(ral.loc_alert_cause[i]), .compare_value(0)); + end + + // Wait some random delays, then release the force signal, issue reset. + // This will allow the test to pass ok_to_end check from alert/esc_monitors and + // push_pull_agent. + cfg.clk_rst_vif.wait_clks($urandom_range(0, 5)); + cfg.alert_handler_vif.release_wait_cyc_mask(); + dut_init(); + endtask + +endclass : alert_handler_entropy_stress_vseq diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_vseq.sv new file mode 100644 index 0000000000000..11a45e2954360 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_vseq.sv @@ -0,0 +1,41 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence enable entropy by writing 1 to the lock_regen register. + +class alert_handler_entropy_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_entropy_vseq) + + `uvm_object_new + + // large number of num_trans to make sure covers all alerts and escalation pings + constraint num_trans_c { + num_trans inside {[400:1000]}; + } + + // increase the possibility to enable more alerts, because alert_handler only sends ping on + // enabled alerts + constraint enable_one_alert_c { + alert_en dist {'1 :/ 9, [0:('1-1'b1)] :/ 1}; + (~alert_regwen) dist {'1 :/ 9, [0:('1-1'b1)] :/ 1}; + } + + constraint sig_int_c { + esc_int_err == 0; + } + + constraint lock_bit_c { + do_lock_config == 1; + } + + constraint esc_accum_thresh_c { + foreach (accum_thresh[i]) {accum_thresh[i] dist {[0:1] :/ 5, [2:10] :/ 5};} + } + + function void pre_randomize(); + this.enable_classa_only_c.constraint_mode(0); + verbosity = UVM_HIGH; + endfunction + +endclass : alert_handler_entropy_vseq diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_alert_accum_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_alert_accum_vseq.sv new file mode 100644 index 0000000000000..612d0389ff660 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_alert_accum_vseq.sv @@ -0,0 +1,34 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence triggers escalation by accumulating alerts in the same class. +// difference from smoke test, this sequence set the threshold to larger numbers. + +class alert_handler_esc_alert_accum_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_esc_alert_accum_vseq) + + `uvm_object_new + + constraint disable_clr_esc_c { + do_clr_esc == 0; + } + + constraint enable_alert_accum_esc_only_c { + do_esc_intr_timeout == 0; // disable interrupt timeout triggered escalation + } + + constraint num_trans_c { + num_trans inside {[1:100]}; + } + + constraint esc_accum_thresh_c { + foreach (accum_thresh[i]) {accum_thresh[i] inside {[0:100]};} + } + + function void pre_randomize(); + this.enable_one_alert_c.constraint_mode(0); + this.enable_classa_only_c.constraint_mode(0); + endfunction + +endclass : alert_handler_esc_alert_accum_vseq diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_intr_timeout_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_intr_timeout_vseq.sv new file mode 100644 index 0000000000000..01df28d4c76e7 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_intr_timeout_vseq.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence triggers escalation by the interrupt timeout + +class alert_handler_esc_intr_timeout_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_esc_intr_timeout_vseq) + + `uvm_object_new + + constraint esc_due_to_intr_timeout_only_c { + foreach (accum_thresh[i]) {accum_thresh[i] > 1;} // prevent alert accumulation triggers esc + do_esc_intr_timeout == 1; + } + + function void pre_randomize(); + this.enable_one_alert_c.constraint_mode(0); + this.enable_classa_only_c.constraint_mode(0); + endfunction + +endclass : alert_handler_esc_intr_timeout_vseq diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_stub_clk_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_stub_clk_vseq.sv new file mode 100644 index 0000000000000..9abddcf286136 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_stub_clk_vseq.sv @@ -0,0 +1,43 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This sequence check LPG by randomly turn off alert_handler's clock, and check if ping timer can +// resume correctly without sending some spurious ping errors. +class alert_handler_lpg_stub_clk_vseq extends alert_handler_lpg_vseq; + `uvm_object_utils(alert_handler_lpg_stub_clk_vseq) + + `uvm_object_new + + constraint loc_alert_en_c { + local_alert_en[LocalAlertPingFail] == 1; + local_alert_en[LocalEscPingFail] == 1; + } + + constraint ping_fail_c { + alert_ping_timeout == 0; + esc_ping_timeout == 0; + } + + task body(); + fork begin : isolation_fork + trigger_non_blocking_seqs(); + fork + rand_stub_clk(); + run_smoke_seq(); + join + disable fork; // disable non-blocking seqs for stress_all tests + end join + endtask : body + + virtual task rand_stub_clk(); + repeat($urandom_range(1, 5)) begin + int clk_stub_ps = cfg.clk_rst_vif.clk_period_ps * $urandom_range(2, 1_000); + cfg.clk_rst_vif.wait_clks($urandom_range(0, 100_000)); + cfg.clk_rst_vif.stop_clk(); + #((clk_stub_ps)*1ps); + cfg.clk_rst_vif.start_clk(); + end + endtask + +endclass : alert_handler_lpg_stub_clk_vseq diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_vseq.sv new file mode 100644 index 0000000000000..8444bc880299c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_vseq.sv @@ -0,0 +1,48 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_handler_lpg_vseq extends alert_handler_entropy_vseq; + `uvm_object_utils(alert_handler_lpg_vseq) + + `uvm_object_new + + constraint sig_int_c { + alert_int_err == 0; + esc_int_err == 0; + esc_standalone_int_err == 0; + } + + constraint loc_alert_en_c { + local_alert_en[LocalAlertPingFail] > 0; + } + + constraint ping_fail_c { + alert_ping_timeout == alert_en; + esc_ping_timeout == 0; + } + + // disable interrupt timeout + constraint esc_intr_timeout_c { + foreach (intr_timeout_cyc[i]) {intr_timeout_cyc[i] == 0;} + } + + function void pre_randomize(); + this.enable_classa_only_c.constraint_mode(0); + this.enable_one_alert_c.constraint_mode(0); + verbosity = UVM_HIGH; + endfunction + + task body(); + fork + begin : isolation_fork + trigger_non_blocking_seqs(); + fork + enable_lpg_group(alert_en); + run_smoke_seq(); + join + disable fork; // disable non-blocking seqs for stress_all tests + end // end isolation_fork + join + endtask : body +endclass : alert_handler_lpg_vseq diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv new file mode 100644 index 0000000000000..00237f42fed20 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv @@ -0,0 +1,79 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence test corner cases for alert or escalation pings: +// 1). ping integrity fail or timeout +// 2). ping interrupted by a reset signal +// 3). escalation ping interrupted by real escalation signal (this could happen because escalation +// ping and real escalation share the same esc_p/n signals) + +class alert_handler_ping_timeout_vseq extends alert_handler_entropy_vseq; + `uvm_object_utils(alert_handler_ping_timeout_vseq) + + `uvm_object_new + + constraint num_trans_c { + num_trans inside {[5:30]}; + } + + constraint alert_trigger_c { + alert_trigger == 0; + } + + constraint intr_en_c { + intr_en == '1; + } + + constraint sig_int_c { + alert_int_err == 0; + esc_int_err == 0; + esc_standalone_int_err == 0; + } + + constraint loc_alert_en_c { + local_alert_en[LocalEscPingFail] == 1; + local_alert_en[LocalAlertPingFail] == 1; + } + + constraint ping_fail_c { + alert_ping_timeout == '1; + esc_ping_timeout == '1; + } + + // At least enable and lock `NUM_ALERTS-4` alerts to avoid this sequence running too long. + // This constraint also ensures at least one alert is locked and enabled so that we can ensure at + // least one alert ping will fire. + constraint enable_one_alert_c { + $countones(alert_en) dist {NUM_ALERTS :/ 8, [NUM_ALERTS-4 : NUM_ALERTS-1] :/ 2}; + $countones(~alert_regwen) dist {NUM_ALERTS :/ 5, [NUM_ALERTS-4 : NUM_ALERTS-1] :/ 5}; + (~alert_regwen) & alert_en > 0; + } + + constraint ping_timeout_cyc_c { + ping_timeout_cyc inside {[1:MAX_PING_TIMEOUT_CYCLE]}; + } + + // disable interrupt timeout + constraint esc_intr_timeout_c { + foreach (intr_timeout_cyc[i]) {intr_timeout_cyc[i] == 0;} + } + + function void pre_randomize(); + this.enable_classa_only_c.constraint_mode(0); + endfunction + + // In this sequence, because we disable all external alerts, so to ensure local alerts are + // triggerd, we wait for interrupt pins to fire then wait for alert and escalation handshake + // to finish. + virtual task wait_alert_esc_done(); + wait (cfg.intr_vif.pins[NUM_ALERT_CLASSES-1:0]); + // Wait two clock cycles to avoid building a cycle-accurate scb. + cfg.clk_rst_vif.wait_clks(2); + `uvm_info(`gfn, $sformatf("Interrupt pin = %0h", cfg.intr_vif.pins[NUM_ALERT_CLASSES-1:0]), + UVM_LOW) + check_alert_interrupts(); + super.wait_alert_esc_done(); + endtask + +endclass : alert_handler_ping_timeout_vseq diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_alerts_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_alerts_vseq.sv new file mode 100644 index 0000000000000..f8276a1d7ca4d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_alerts_vseq.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence enable random alert inputs, and rand wr phase cycles + +class alert_handler_random_alerts_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_random_alerts_vseq) + + `uvm_object_new + + constraint esc_accum_thresh_c { + foreach (accum_thresh[i]) {accum_thresh[i] dist {[0:1] :/ 5, [2:5] :/ 5};} + } + + function void pre_randomize(); + this.enable_one_alert_c.constraint_mode(0); + endfunction + +endclass : alert_handler_random_alerts_vseq diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_classes_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_classes_vseq.sv new file mode 100644 index 0000000000000..b6d726000621c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_classes_vseq.sv @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence enable random classes, and rand wr phase cycles + +class alert_handler_random_classes_vseq extends alert_handler_random_alerts_vseq; + `uvm_object_utils(alert_handler_random_classes_vseq) + + `uvm_object_new + + function void pre_randomize(); + super.pre_randomize(); + this.enable_classa_only_c.constraint_mode(0); + endfunction + +endclass : alert_handler_random_classes_vseq diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_sig_int_fail_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_sig_int_fail_vseq.sv new file mode 100644 index 0000000000000..5012d457a01d7 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_sig_int_fail_vseq.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence enable signal intergrity fail. + +class alert_handler_sig_int_fail_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_sig_int_fail_vseq) + + `uvm_object_new + + constraint esc_accum_thresh_c { + foreach (accum_thresh[i]) {accum_thresh[i] dist {[0:1] :/ 5, [2:10] :/ 5};} + } + + function void pre_randomize(); + this.enable_one_alert_c.constraint_mode(0); + this.enable_classa_only_c.constraint_mode(0); + this.sig_int_c.constraint_mode(0); + endfunction + +endclass : alert_handler_sig_int_fail_vseq diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv new file mode 100644 index 0000000000000..5845638e9938c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv @@ -0,0 +1,221 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// basic smoke test vseq +class alert_handler_smoke_vseq extends alert_handler_base_vseq; + `uvm_object_utils(alert_handler_smoke_vseq) + + `uvm_object_new + + rand bit [NUM_ALERT_CLASSES-1:0] intr_en; + rand bit [NUM_ALERT_CLASSES-1:0] clr_regwen; + rand bit [NUM_ALERT_CLASSES-1:0] class_regwen; + rand bit [NUM_ALERT_CLASSES-1:0] clr_en; + rand bit [NUM_ALERT_CLASSES-1:0] lock_bit_en; + rand bit [NUM_ALERT_CLASSES-1:0] class_en; + rand bit [NUM_ALERTS-1:0] alert_regwen; + rand bit [NUM_ALERTS-1:0] alert_trigger; + rand bit [NUM_ALERTS-1:0] alert_int_err; + rand bit [NUM_ALERTS-1:0] alert_en; + rand bit [NUM_ALERTS-1:0] alert_ping_timeout; + rand bit [NUM_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] alert_class_map; + rand bit [NUM_LOCAL_ALERTS-1:0] local_alert_regwen; + rand bit [NUM_LOCAL_ALERTS-1:0] local_alert_en; + rand bit [NUM_LOCAL_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] local_alert_class_map; + rand bit [NUM_ESCS-1:0] esc_int_err; + rand bit [NUM_ESCS-1:0] esc_standalone_int_err; + rand bit [NUM_ESCS-1:0] esc_ping_timeout; + + rand bit ping_timer_regwen; + rand bit do_clr_esc; + rand bit do_wr_phases_cyc; + rand bit do_esc_intr_timeout; + rand bit do_lock_config; + rand bit [TL_DW-1:0] ping_timeout_cyc; + rand bit [TL_DW-1:0] max_phase_cyc; + rand bit [TL_DW-1:0] intr_timeout_cyc [NUM_ALERT_CLASSES]; + rand bit [TL_DW-1:0] accum_thresh [NUM_ALERT_CLASSES]; + + int max_wait_phases_cyc = MIN_CYCLE_PER_PHASE * NUM_ESC_PHASES; + int max_intr_timeout_cyc; + + uvm_verbosity verbosity = UVM_LOW; + + constraint lock_bit_c { + do_lock_config dist {1 := 1, 0 := 49}; + } + + constraint clr_and_lock_en_c { + lock_bit_en dist {0 :/ 6, [1:'b1111] :/ 4}; + } + + constraint regwen_c { + clr_regwen dist {[0:'1-1'b1] :/ 4, '1 :/ 6}; + class_regwen dist {[0:'1-1'b1] :/ 4, '1 :/ 6}; + alert_regwen dist {[0:'1-1'b1] :/ 4, '1 :/ 6}; + local_alert_regwen dist {[0:'1-1'b1] :/ 4, '1 :/ 6}; + ping_timer_regwen dist { 0 :/ 4 , 1 :/ 6}; + } + + constraint enable_one_alert_c { + $onehot(alert_en); + } + + constraint max_phase_cyc_c { + max_phase_cyc inside {[0:1_000]}; + } + + // Set min to 120 cycles to avoid alert ping timeout due to random delay. + // The max delay after ping request is 10 cycles plus 2 cycles async delay. + // Also the alert_sender and alert_handlers are in different clock domains, with a max 10 times + // difference in clock frequency. + constraint ping_timeout_cyc_c { + ping_timeout_cyc inside {[120:MAX_PING_TIMEOUT_CYCLE]}; + } + + constraint enable_classa_only_c { + alert_class_map == 0; // all the alerts assign to classa + local_alert_class_map == 0; // all local alerts assign to classa + class_en dist {1 :/ 8, 0 :/ 1, [2:'1-1'b1] :/ 1}; + } + + // constraint to trigger escalation + constraint esc_accum_thresh_c { + foreach (accum_thresh[i]) {soft accum_thresh[i] inside {[0:1]};} + } + + constraint esc_intr_timeout_c { + foreach (intr_timeout_cyc[i]) {intr_timeout_cyc[i] inside {[1:1_000]};} + } + + constraint sig_int_c { + alert_int_err == 0; + esc_int_err == 0; + esc_standalone_int_err == 0; + } + + constraint ping_fail_c { + alert_ping_timeout == 0; + esc_ping_timeout == 0; + } + + task pre_start(); + super.pre_start(); + // This is the input for a nonblocking sequence. The value won't be changed until the + // nonblockings sequence end. + esc_ping_timeout.rand_mode(0); + esc_int_err.rand_mode(0); + endtask + + task body(); + fork + begin : isolation_fork + trigger_non_blocking_seqs(); + run_smoke_seq(); + disable fork; // disable non-blocking seqs for stress_all tests + end // end fork + join + endtask : body + + virtual task trigger_non_blocking_seqs(); + `uvm_info(`gfn, $sformatf("esc_int_err %0h esc_ping_timeout %0h", + esc_int_err, esc_ping_timeout), UVM_LOW); + run_esc_rsp_seq_nonblocking(esc_int_err, esc_ping_timeout); + endtask + + virtual task run_smoke_seq(); + `uvm_info(`gfn, $sformatf("num_trans=%0d", num_trans), UVM_LOW) + if (verbosity != UVM_LOW) begin + `uvm_info(`gfn, + $sformatf("Config: intr_en=%0b, alert=%0b, alert_en=%0b, loc_alert_en=%0b", + intr_en, alert_trigger, alert_en, local_alert_en), UVM_LOW) + end + + for (int i = 1; i <= num_trans; i++) begin + `DV_CHECK_RANDOMIZE_FATAL(this) + + // Assign ping timeout value to each alert agent. + foreach (cfg.alert_host_cfg[i]) cfg.alert_host_cfg[i].ping_timeout = alert_ping_timeout[i]; + + `uvm_info(`gfn, $sformatf( + "start seq %0d/%0d: intr_en=0x%0h, alert=0x%0h, alert_en=0x%0h, loc_alert_en=0x%0h", + i, num_trans, intr_en, alert_trigger, alert_en, local_alert_en), verbosity) + + // write initial settings (enable and mapping csrs) + alert_handler_init(.intr_en(intr_en), + .alert_en(alert_en), + .alert_class(alert_class_map), + .loc_alert_en(local_alert_en), + .loc_alert_class(local_alert_class_map)); + + // write class_ctrl + alert_handler_rand_wr_class_ctrl(lock_bit_en, class_en); + + // randomize crashdump triggered phases + alert_handler_crashdump_phases(); + + // randomly write phase cycle registers + // always set phase_cycle for the first iteration, in order to pass stress_all test + if (do_wr_phases_cyc || i == 1) wr_phases_cycle(max_phase_cyc); + + // randomly write interrupt timeout resigers and accumulative threshold registers + if (do_esc_intr_timeout) wr_intr_timeout_cycle(intr_timeout_cyc); + wr_class_accum_threshold(accum_thresh); + wr_ping_timeout_cycle(ping_timeout_cyc); + + // when all configuration registers are set, write lock register + lock_config(do_lock_config); + + // once all above configs are written, lock them with regwen + alert_handler_wr_regwen_regs(clr_regwen, alert_regwen, local_alert_regwen, ping_timer_regwen, + class_regwen); + + // if config is not locked, update max_intr_timeout and max_wait_phases cycles + if (!config_locked) begin + bit [TL_DW-1:0] max_intr_timeout_cyc; + bit [TL_DW-1:0] max_q[$] = intr_timeout_cyc.max(); + max_intr_timeout_cyc = max_q[0]; + max_wait_phases_cyc = max2(max_wait_phases_cyc, max_phase_cyc * NUM_ESC_PHASES); + if (do_lock_config) config_locked = 1; + end + + // drive esc standalone responses and alerts + if (esc_standalone_int_err) drive_esc_rsp(esc_standalone_int_err); + drive_alert(alert_trigger, alert_int_err); + + if (do_esc_intr_timeout) begin + cfg.clk_rst_vif.wait_clks(max_intr_timeout_cyc); + // this task checks three sets of registers related to alert/esc status: + // alert_accum_cnt, esc_cnt, class_state + read_esc_status(); + end + // only check interrupt when no esc_int_err, otherwise clear interrupt might happen the + // same cycle as interrupt triggered by esc_int_err + if ((esc_int_err == 0) && (esc_ping_timeout == 0)) check_alert_interrupts(); + + // if ping timeout enabled, wait for ping timeout done before checking escalation phases + if ((esc_int_err | alert_ping_timeout) > 0) begin + cfg.clk_rst_vif.wait_clks(MAX_PING_TIMEOUT_CYCLE); + end + + // wait escalation done, and random interrupt with clear_esc + wait_alert_esc_done(); + + read_alert_cause(); + read_esc_status(); + if (do_clr_esc) clear_esc(); + check_alert_interrupts(); + end + endtask + + virtual task wait_alert_esc_done(); + wait_alert_handshake_done(); + if ($urandom_range(0, 1) && (esc_int_err == 0)) begin + cfg.clk_rst_vif.wait_clks($urandom_range(0, max_wait_phases_cyc)); + clear_esc(); + end + wait_esc_handshake_done(); + endtask + +endclass : alert_handler_smoke_vseq diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_stress_all_vseq.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_stress_all_vseq.sv new file mode 100644 index 0000000000000..0dd261d7deaac --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_stress_all_vseq.sv @@ -0,0 +1,55 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// combine all alert_handler seqs (except below seqs) in one seq to run sequentially +// 1. csr seq, which requires scb to be disabled +class alert_handler_stress_all_vseq extends alert_handler_base_vseq; + `uvm_object_utils(alert_handler_stress_all_vseq) + + `uvm_object_new + + task body(); + bit entropy_test_flag; // this flag ensures entropy test only runs once due to its long runtime + string seq_names[] = {"alert_handler_smoke_vseq", + "alert_handler_random_alerts_vseq", + "alert_handler_random_classes_vseq", + "alert_handler_esc_intr_timeout_vseq", + "alert_handler_esc_alert_accum_vseq", + "alert_handler_sig_int_fail_vseq", + "alert_handler_entropy_vseq"}; + for (int i = 1; i <= num_trans; i++) begin + uvm_sequence seq; + alert_handler_base_vseq alert_vseq; + uint seq_idx = entropy_test_flag ? $urandom_range(0, seq_names.size - 2) : + $urandom_range(0, seq_names.size - 1); + if (seq_names[seq_idx] == "alert_handler_entropy_vseq") entropy_test_flag = 1; + + seq = create_seq_by_name(seq_names[seq_idx]); + `downcast(alert_vseq, seq) + + // if upper seq disables do_apply_reset for this seq, then can't issue reset + // as upper seq may drive reset + if (do_apply_reset) begin + alert_vseq.do_apply_reset = $urandom_range(0, 1); + // config_locked will be set unless reset is issued + alert_vseq.config_locked = alert_vseq.do_apply_reset ? 0 : config_locked; + end else begin + alert_vseq.do_apply_reset = 0; + alert_vseq.config_locked = config_locked; + end + + alert_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(alert_vseq) + if (seq_names[seq_idx] == "alert_common_vseq") begin + alert_handler_common_vseq common_vseq; + `downcast(common_vseq, alert_vseq); + common_vseq.common_seq_type = "intr_test"; + end + + alert_vseq.start(p_sequencer); + config_locked = alert_vseq.config_locked; + end + endtask : body + +endclass diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_vseq_list.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_vseq_list.sv new file mode 100644 index 0000000000000..99814127148d3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_vseq_list.sv @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "alert_handler_base_vseq.sv" +`include "alert_handler_smoke_vseq.sv" +`include "alert_handler_common_vseq.sv" +`include "alert_handler_random_alerts_vseq.sv" +`include "alert_handler_random_classes_vseq.sv" +`include "alert_handler_esc_intr_timeout_vseq.sv" +`include "alert_handler_esc_alert_accum_vseq.sv" +`include "alert_handler_sig_int_fail_vseq.sv" +`include "alert_handler_entropy_vseq.sv" +`include "alert_handler_ping_timeout_vseq.sv" +`include "alert_handler_lpg_vseq.sv" +`include "alert_handler_lpg_stub_clk_vseq.sv" +`include "alert_handler_entropy_stress_vseq.sv" +`include "alert_handler_stress_all_vseq.sv" +`include "alert_handler_alert_accum_saturation_vseq.sv" diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/sva/alert_handler_bind.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/sva/alert_handler_bind.sv new file mode 100644 index 0000000000000..dd69d9571e75b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/sva/alert_handler_bind.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module alert_handler_bind; + + bind alert_handler tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + + bind alert_handler alert_handler_csr_assert_fpv alert_handler_csr_assert ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/sva/alert_handler_sva.core b/hw/top_darjeeling/ip_autogen/alert_handler/dv/sva/alert_handler_sva.core new file mode 100644 index 0000000000000..57a7e7749bd6f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/sva/alert_handler_sva.core @@ -0,0 +1,38 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_alert_handler_sva:0.1 +description: "ALERT_HANDLER assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + files: + - alert_handler_bind.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:opentitan:top_darjeeling_alert_handler:0.1 + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/alert_handler.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: alert_handler diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core new file mode 100644 index 0000000000000..bbf6842a74308 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core @@ -0,0 +1,18 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:alert_handler_tb:0.1" +description: "ALERT_HANDLER UVM TB environment" +filesets: + files_dv: + depend: + - lowrisc:dv:alert_handler_test:0.1 + files: + - tb.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/tb/tb.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tb/tb.sv new file mode 100644 index 0000000000000..f0375e74e43d6 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tb/tb.sv @@ -0,0 +1,112 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module tb; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import alert_handler_env_pkg::*; + import alert_handler_test_pkg::*; + import alert_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk, rst_n, rst_shadowed_n; + wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + wire [NUM_MAX_ESC_SEV-1:0] esc_en; + wire [NUM_CRASHDUMP-1:0] crashdump; + + // interfaces + clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n)); + rst_shadowed_if rst_shadowed_if(.rst_n(rst_n), .rst_shadowed_n(rst_shadowed_n)); + pins_if #(NUM_MAX_INTERRUPTS) intr_if(interrupts); + pins_if #(NUM_CRASHDUMP) crashdump_if(crashdump); + tl_if tl_if(.clk(clk), .rst_n(rst_n)); + alert_handler_if alert_handler_if(.clk(clk), .rst_n(rst_n)); + alert_esc_if esc_device_if [NUM_ESCS](.clk(clk), .rst_n(rst_n)); + alert_esc_if alert_host_if [NUM_ALERTS](.clk(clk), .rst_n(rst_n)); + alert_esc_probe_if probe_if[NUM_ESCS](.clk(clk), .rst_n(rst_n)); + + // dut signals + prim_alert_pkg::alert_rx_t [NUM_ALERTS-1:0] alert_rx; + prim_alert_pkg::alert_tx_t [NUM_ALERTS-1:0] alert_tx; + + prim_esc_pkg::esc_rx_t [NUM_ESCS-1:0] esc_rx; + prim_esc_pkg::esc_tx_t [NUM_ESCS-1:0] esc_tx; + + for (genvar k = 0; k < NUM_ALERTS; k++) begin : gen_alert_if + assign alert_tx[k].alert_p = alert_host_if[k].alert_tx.alert_p; + assign alert_tx[k].alert_n = alert_host_if[k].alert_tx.alert_n; + assign alert_host_if[k].alert_rx.ack_p = alert_rx[k].ack_p; + assign alert_host_if[k].alert_rx.ack_n = alert_rx[k].ack_n; + assign alert_host_if[k].alert_rx.ping_p = alert_rx[k].ping_p; + assign alert_host_if[k].alert_rx.ping_n = alert_rx[k].ping_n; + assign alert_handler_if.alert_ping_reqs[k] = dut.gen_alerts[k].u_alert_receiver.ping_req_i; + initial begin + uvm_config_db#(virtual alert_esc_if)::set(null, $sformatf("*.env.alert_host_agent[%0d]", k), + "vif", alert_host_if[k]); + end + end + + + for (genvar k = 0; k < NUM_ESCS; k++) begin : gen_esc_if + assign esc_rx[k].resp_p = esc_device_if[k].esc_rx.resp_p; + assign esc_rx[k].resp_n = esc_device_if[k].esc_rx.resp_n; + assign esc_device_if[k].esc_tx.esc_p = esc_tx[k].esc_p; + assign esc_device_if[k].esc_tx.esc_n = esc_tx[k].esc_n; + assign probe_if[k].esc_en = dut.esc_sig_req[k]; + assign alert_handler_if.esc_ping_reqs[k] = dut.gen_esc_sev[k].u_esc_sender.ping_req_i; + initial begin + uvm_config_db#(virtual alert_esc_if)::set(null, $sformatf("*.env.esc_device_agent[%0d]", k), + "vif", esc_device_if[k]); + uvm_config_db#(virtual alert_esc_probe_if)::set(null, + $sformatf("*.env.esc_device_agent[%0d]", k), "probe_vif", probe_if[k]); + end + end + + // edn_clk, edn_rst_n and edn_if are defined and driven in below macro + `DV_EDN_IF_CONNECT + + // main dut + alert_handler dut ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .rst_shadowed_ni ( rst_shadowed_n), + .clk_edn_i ( edn_clk ), + .rst_edn_ni ( edn_rst_n ), + .tl_i ( tl_if.h2d ), + .tl_o ( tl_if.d2h ), + .intr_classa_o ( interrupts[0] ), + .intr_classb_o ( interrupts[1] ), + .intr_classc_o ( interrupts[2] ), + .intr_classd_o ( interrupts[3] ), + .lpg_cg_en_i ( alert_handler_if.lpg_cg_en ), + .lpg_rst_en_i ( alert_handler_if.lpg_rst_en ), + .crashdump_o ( crashdump ), + .edn_o ( edn_if[0].req ), + .edn_i ( {edn_if[0].ack, edn_if[0].d_data} ), + .alert_rx_o ( alert_rx ), + .alert_tx_i ( alert_tx ), + .esc_rx_i ( esc_rx ), + .esc_tx_o ( esc_tx ) + ); + + initial begin + // drive clk and rst_n from clk_if + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", + rst_shadowed_if); + uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + uvm_config_db#(crashdump_vif)::set(null, "*.env", "crashdump_vif", crashdump_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); + uvm_config_db#(virtual alert_handler_if)::set(null, "*.env", "alert_handler_vif", + alert_handler_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/tests/alert_handler_base_test.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tests/alert_handler_base_test.sv new file mode 100644 index 0000000000000..32cc5b33d680e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tests/alert_handler_base_test.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_handler_base_test extends cip_base_test #( + .ENV_T(alert_handler_env), + .CFG_T(alert_handler_env_cfg) + ); + + `uvm_component_utils(alert_handler_base_test) + `uvm_component_new + + // the base class dv_base_test creates the following instances: + // alert_handler_env_cfg: cfg + // alert_handler_env: env + + // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in + // the run_phase; as such, nothing more needs to be done + +endclass : alert_handler_base_test diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/tests/alert_handler_test.core b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tests/alert_handler_test.core new file mode 100644 index 0000000000000..767c0654f1c6d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tests/alert_handler_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:alert_handler_test:0.1" +description: "ALERT_HANDLER DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:dv:alert_handler_env + files: + - alert_handler_test_pkg.sv + - alert_handler_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/dv/tests/alert_handler_test_pkg.sv b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tests/alert_handler_test_pkg.sv new file mode 100644 index 0000000000000..357417515cf52 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/dv/tests/alert_handler_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package alert_handler_test_pkg; + // dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import alert_handler_env_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // local types + + // functions + + // package sources + `include "alert_handler_base_test.sv" + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core new file mode 100644 index 0000000000000..721b801f11f0d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core @@ -0,0 +1,31 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_alert_handler_esc_timer_fpv:0.1 +description: "alert_handler_esc_timer FPV target" +filesets: + files_formal: + depend: + - lowrisc:prim:all + - lowrisc:opentitan:top_darjeeling_alert_handler + files: + - vip/alert_handler_esc_timer_assert_fpv.sv + - tb/alert_handler_esc_timer_bind_fpv.sv + - tb/alert_handler_esc_timer_tb.sv + file_type: systemVerilogSource + +targets: + default: &default_target + # note, this setting is just used + # to generate a file list for jg + default_tool: icarus + filesets: + - files_formal + toplevel: alert_handler_esc_timer_tb + + formal: + <<: *default_target + + lint: + <<: *default_target diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core new file mode 100644 index 0000000000000..60f051f50e2e1 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core @@ -0,0 +1,31 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_alert_handler_ping_timer_fpv:0.1 +description: "ALERT_HANDLER FPV target" +filesets: + files_formal: + depend: + - lowrisc:prim:all + - lowrisc:opentitan:top_darjeeling_alert_handler + files: + - vip/alert_handler_ping_timer_assert_fpv.sv + - tb/alert_handler_ping_timer_bind_fpv.sv + - tb/alert_handler_ping_timer_tb.sv + file_type: systemVerilogSource + +targets: + default: &default_target + # note, this setting is just used + # to generate a file list for jg + default_tool: icarus + filesets: + - files_formal + toplevel: alert_handler_ping_timer_tb + + formal: + <<: *default_target + + lint: + <<: *default_target diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_bind_fpv.sv b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_bind_fpv.sv new file mode 100644 index 0000000000000..4bcbb1e19f60c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_bind_fpv.sv @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +module alert_handler_esc_timer_bind_fpv; + + + bind alert_handler_esc_timer + alert_handler_esc_timer_assert_fpv i_alert_handler_esc_timer_assert_fpv ( + .clk_i, + .rst_ni, + .en_i, + .clr_i, + .accu_trig_i, + .accu_fail_i, + .timeout_en_i, + .timeout_cyc_i, + .esc_en_i, + .esc_map_i, + .phase_cyc_i, + .crashdump_phase_i, + .latch_crashdump_o, + .esc_trig_o, + .esc_cnt_o, + .esc_sig_req_o, + .esc_state_o + ); + + +endmodule : alert_handler_esc_timer_bind_fpv diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv new file mode 100644 index 0000000000000..312e91bff28af --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Testbench module for alert_handler_esc_timer. +// Intended to be used with a formal tool. + +module alert_handler_esc_timer_tb import alert_pkg::*; ( + input clk_i, + input rst_ni, + input en_i, + input clr_i, + input accu_trig_i, + input accu_fail_i, + input timeout_en_i, + input [EscCntDw-1:0] timeout_cyc_i, + input [N_ESC_SEV-1:0] esc_en_i, + input [N_ESC_SEV-1:0][PHASE_DW-1:0] esc_map_i, + input [N_PHASES-1:0][EscCntDw-1:0] phase_cyc_i, + input [PHASE_DW-1:0] crashdump_phase_i, + output logic latch_crashdump_o, + output logic esc_trig_o, + output logic[EscCntDw-1:0] esc_cnt_o, + output logic[N_ESC_SEV-1:0] esc_sig_req_o, + output cstate_e esc_state_o +); + + alert_handler_esc_timer i_alert_handler_esc_timer ( + .clk_i, + .rst_ni, + .en_i, + .clr_i, + .accu_trig_i, + .accu_fail_i, + .timeout_en_i, + .timeout_cyc_i, + .esc_en_i, + .esc_map_i, + .phase_cyc_i, + .crashdump_phase_i, + .latch_crashdump_o, + .esc_trig_o, + .esc_cnt_o, + .esc_sig_req_o, + .esc_state_o + ); + + +endmodule : alert_handler_esc_timer_tb diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_bind_fpv.sv b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_bind_fpv.sv new file mode 100644 index 0000000000000..59ee6e403e254 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_bind_fpv.sv @@ -0,0 +1,29 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +module alert_handler_ping_timer_bind_fpv; + + + bind alert_handler_ping_timer + alert_handler_ping_timer_assert_fpv i_alert_handler_ping_timer_assert_fpv ( + .clk_i, + .rst_ni, + .edn_req_o, + .edn_ack_i, + .edn_data_i, + .en_i, + .alert_ping_en_i, + .ping_timeout_cyc_i, + .wait_cyc_mask_i, + .alert_ping_req_o, + .esc_ping_req_o, + .alert_ping_ok_i, + .esc_ping_ok_i, + .alert_ping_fail_o, + .esc_ping_fail_o + ); + + +endmodule : alert_handler_ping_timer_bind_fpv diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv new file mode 100644 index 0000000000000..cb439a3829212 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv @@ -0,0 +1,48 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Testbench module for ping timer in alert handler. Intended to use with +// a formal tool. + +module alert_handler_ping_timer_tb import alert_pkg::*; ( + input clk_i, + input rst_ni, + output logic edn_req_o, + input edn_ack_i, + input [LfsrWidth-1:0] edn_data_i, + input en_i, + input [NAlerts-1:0] alert_ping_en_i, + input [PING_CNT_DW-1:0] ping_timeout_cyc_i, + input [PING_CNT_DW-1:0] wait_cyc_mask_i, + output logic [NAlerts-1:0] alert_ping_req_o, + output logic [N_ESC_SEV-1:0] esc_ping_req_o, + input [NAlerts-1:0] alert_ping_ok_i, + input [N_ESC_SEV-1:0] esc_ping_ok_i, + output logic alert_ping_fail_o, + output logic esc_ping_fail_o +); + + alert_handler_ping_timer #( + // disable max length check in FPV, otherwise this + // will not converge within acceptable compute time + .MaxLenSVA ( 1'b0 ) + ) i_alert_handler_ping_timer ( + .clk_i , + .rst_ni , + .edn_req_o , + .edn_ack_i , + .edn_data_i , + .en_i , + .alert_ping_en_i , + .ping_timeout_cyc_i, + .wait_cyc_mask_i , + .alert_ping_req_o , + .esc_ping_req_o , + .alert_ping_ok_i , + .esc_ping_ok_i , + .alert_ping_fail_o , + .esc_ping_fail_o + ); + +endmodule : alert_handler_ping_timer_tb diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/esc_after_load.tcl b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/esc_after_load.tcl new file mode 100644 index 0000000000000..bc38fee3a77a6 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/esc_after_load.tcl @@ -0,0 +1,10 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# The UpCntIncrStable_A and DnCntIncrStable_A assertions are vacuous +# in this test because we can never get to the situation where the +# counter would saturate: it only be set to 1 and incremented, but it +# is reasonably wide (EscCntDw=32). +cover -disable -regexp ".*\.g_check_incr\.UpCntIncrStable_A:precondition1" +cover -disable -regexp ".*\.g_check_incr\.DnCntIncrStable_A:precondition1" diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/ping_after_load.tcl b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/ping_after_load.tcl new file mode 100644 index 0000000000000..0026b5e6cfc06 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/tb/ping_after_load.tcl @@ -0,0 +1,11 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# In the ping timer, there is a counter called u_prim_count_esc_cnt. The FSM that drives this uses +# the prim_count to count through the N_ESC_SEV senders and then clears it back to zero. As a +# result, it never tries to increment the counter at maximum value (N_ESC_SEV-1), so we will never +# see the precondition for the *CntIncrStable_A assertions. Waive the cover property for each +# assertion. +cover -disable -regexp ".*\.u_prim_count_esc_cnt\..*\.UpCntIncrStable_A:precondition1" +cover -disable -regexp ".*\.u_prim_count_esc_cnt\..*\.DnCntIncrStable_A:precondition1" diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/vip/alert_handler_esc_timer_assert_fpv.sv b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/vip/alert_handler_esc_timer_assert_fpv.sv new file mode 100644 index 0000000000000..265f1359f4719 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/vip/alert_handler_esc_timer_assert_fpv.sv @@ -0,0 +1,139 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Assertions for alert_handler_esc_timer. +// Intended to be used with a formal tool. + +`include "prim_assert.sv" + +module alert_handler_esc_timer_assert_fpv import alert_pkg::*; ( + input clk_i, + input rst_ni, + input en_i, + input clr_i, + input accu_trig_i, + input accu_fail_i, + input timeout_en_i, + input [EscCntDw-1:0] timeout_cyc_i, + input [N_ESC_SEV-1:0] esc_en_i, + input [N_ESC_SEV-1:0][PHASE_DW-1:0] esc_map_i, + input [N_PHASES-1:0][EscCntDw-1:0] phase_cyc_i, + input [PHASE_DW-1:0] crashdump_phase_i, + input logic latch_crashdump_o, + input logic esc_trig_o, + input logic[EscCntDw-1:0] esc_cnt_o, + input logic[N_ESC_SEV-1:0] esc_sig_req_o, + input cstate_e esc_state_o +); + + /////////////////////////////// + // Declarations & Parameters // + /////////////////////////////// + + // constrain the state-spaces + localparam int unsigned MAX_TIMEOUT_CYCLES = 10; + localparam int unsigned MAX_PHASE_CYCLES = 10; + + // symbolic vars for phase map check + logic [1:0] esc_sel; + logic [1:0] phase_sel; + localparam cstate_e Phases [4] = {Phase0, Phase1, Phase2, Phase3}; + + // set regs + logic esc_has_triggered_q; + + + ///////////////// + // Assumptions // + ///////////////// + + `ASSUME(TimeoutCycles_M, timeout_cyc_i < MAX_TIMEOUT_CYCLES) + `ASSUME(TimeoutCyclesConst_M, ##1 $stable(timeout_cyc_i)) + + `ASSUME(PhaseCycles_M, phase_cyc_i < MAX_PHASE_CYCLES) + `ASSUME(PhaseCyclesConst_M, ##1 $stable(phase_cyc_i)) + + `ASSUME(CrashdumpPhaseConst_M, ##1 $stable(crashdump_phase_i)) + + `ASSUME(EscSelConst_M, ##1 $stable(esc_sel)) + `ASSUME(PhaseSelConst_M, ##1 $stable(phase_sel)) + + //////////////////////// + // Forward Assertions // + //////////////////////// + + // if the class is not enabled and we are in IDLE state, + // neither of the two escalation mechanisms shall fire + `ASSERT(ClassDisabledNoEscTrig_A, esc_state_o == Idle && !en_i |-> !esc_trig_o) + `ASSERT(ClassDisabledNoEsc_A, esc_state_o == Idle && !en_i && !alert_handler_esc_timer.fsm_error + |-> !esc_sig_req_o) + `ASSERT(EscDisabledNoEsc_A, !esc_en_i[esc_sel] && !alert_handler_esc_timer.fsm_error |-> + !esc_sig_req_o[esc_sel]) + + // if timeout counter is enabled due to a pending interrupt, check escalation + // assume accumulation trigger is not asserted during this sequence + `ASSERT(TimeoutEscTrig_A, esc_state_o == Idle ##1 en_i && $rose(timeout_en_i) && + (timeout_cyc_i > 0) ##1 timeout_en_i [*MAX_TIMEOUT_CYCLES] |=> esc_has_triggered_q, + clk_i, !rst_ni || accu_trig_i || clr_i || accu_fail_i) + + // check whether an accum trig leads to escalation if enabled + `ASSERT(AccumEscTrig_A, ##1 en_i && accu_trig_i && esc_state_o inside {Idle, Timeout} |=> + esc_has_triggered_q, clk_i, !rst_ni || clr_i || accu_fail_i) + + // check escalation cnt and state out + `ASSERT(EscCntOut_A, alert_handler_esc_timer.u_prim_count.cnt_q[0] == esc_cnt_o) + + // check clr input + // we cannot use clr to exit from the timeout state + `ASSERT(ClrCheck_A, clr_i && !(esc_state_o inside {Idle, Timeout, FsmError}) && !accu_fail_i |=> + esc_state_o == Idle) + + // check escalation map + `ASSERT(PhaseEscMap_A, esc_state_o == Phases[phase_sel] && esc_map_i[esc_sel] == phase_sel && + esc_en_i[esc_sel] |-> esc_sig_req_o[esc_sel]) + + // check terminal state is reached eventually if triggered and not cleared + `ASSERT(TerminalState_A, esc_trig_o |-> strong(##[1:$] esc_state_o == Terminal), + clk_i, !rst_ni || clr_i || accu_fail_i) + + // check that the crashdump capture trigger is asserted correctly + `ASSERT(CrashdumpTrigger_A, + ##1 $changed(esc_state_o) && + esc_state_o == cstate_e'(4 + crashdump_phase_i) + <-> + $past(latch_crashdump_o), esc_state_o == FsmError) + + ///////////////////////// + // Backward Assertions // + ///////////////////////// + + // escalation can only be triggered when in Idle or Timeout state. Trigger mechanisms are either + // the accumulation trigger or a timeout trigger + `ASSERT(EscTrigBkwd_A, esc_trig_o |-> esc_state_o inside {Idle, Timeout} && accu_trig_i || + esc_state_o == Timeout && esc_cnt_o >= timeout_cyc_i) + `ASSERT(NoEscTrigBkwd_A, !esc_trig_o |-> !(esc_state_o inside {Idle, Timeout}) || + !en_i || !accu_trig_i || !timeout_en_i || clr_i) + + // escalation signals can only be asserted in the escalation phase states, or + // if we are in the terminal FsmError state + `ASSERT(EscBkwd_A, esc_sig_req_o[esc_sel] |-> esc_en_i[esc_sel] && + esc_has_triggered_q || alert_handler_esc_timer.fsm_error) + `ASSERT(NoEscBkwd_A, !esc_sig_req_o[esc_sel] |-> !esc_en_i[esc_sel] || + esc_state_o != Phases[esc_map_i[esc_sel]] && esc_state_o != FsmError, + clk_i, !rst_ni || clr_i) + + ////////////////////// + // Helper Processes // + ////////////////////// + + // set registers + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + esc_has_triggered_q <= 1'b0; + end else begin + esc_has_triggered_q <= esc_has_triggered_q & ~clr_i | esc_trig_o; + end + end + +endmodule : alert_handler_esc_timer_assert_fpv diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/fpv/vip/alert_handler_ping_timer_assert_fpv.sv b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/vip/alert_handler_ping_timer_assert_fpv.sv new file mode 100644 index 0000000000000..abc687d65fb65 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/fpv/vip/alert_handler_ping_timer_assert_fpv.sv @@ -0,0 +1,132 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Assertions for ping timer in alert handler. Intended to use with +// a formal tool. + +`include "prim_assert.sv" + +module alert_handler_ping_timer_assert_fpv import alert_pkg::*; ( + input clk_i, + input rst_ni, + input edn_req_o, + input edn_ack_i, + input [LfsrWidth-1:0] edn_data_i, + input en_i, + input [NAlerts-1:0] alert_ping_en_i, + input [PING_CNT_DW-1:0] ping_timeout_cyc_i, + input [PING_CNT_DW-1:0] wait_cyc_mask_i, + input [NAlerts-1:0] alert_ping_req_o, + input [N_ESC_SEV-1:0] esc_ping_req_o, + input [NAlerts-1:0] alert_ping_ok_i, + input [N_ESC_SEV-1:0] esc_ping_ok_i, + input alert_ping_fail_o, + input esc_ping_fail_o +); + + localparam int unsigned PingEnDw = N_ESC_SEV + NAlerts; + logic [PingEnDw-1:0] ping_en_vector, ping_en_mask, ping_ok_vector; + + assign ping_en_vector = {esc_ping_req_o, alert_ping_req_o}; + assign ping_en_mask = {N_ESC_SEV'('1), alert_ping_en_i}; + assign ping_ok_vector = {esc_ping_ok_i, alert_ping_ok_i}; + + ///////////////// + // Assumptions // + ///////////////// + + localparam int MaxWaitCntDw = 3; + + // symbolic variables. we want to assess all valid indices + logic [$clog2(PingEnDw)-1:0] ping_en_sel; + logic [$clog2(N_ESC_SEV)-1:0] esc_idx; + `ASSUME_FPV(PingEnSelRange_M, ping_en_sel < PingEnDw) + `ASSUME_FPV(PingEnSelStable_M, ##1 $stable(ping_en_sel)) + `ASSUME_FPV(EscIdxRange_M, esc_idx < N_ESC_SEV) + `ASSUME_FPV(EscIdxStable_M, ##1 $stable(esc_idx)) + // assume that the alert enable configuration is locked once en_i is high + // this is ensured by the CSR regfile on the outside + `ASSUME_FPV(ConfigLocked0_M, en_i |-> $stable(alert_ping_en_i)) + `ASSUME_FPV(ConfigLocked1_M, en_i |-> $stable(ping_timeout_cyc_i)) + // enable stays high forever, once it has been asserted + `ASSUME(ConfigLocked2_M, en_i |=> en_i) + // reduce state space by reducing length of wait period + `ASSUME_FPV(WaitPeriod0_M, wait_cyc_mask_i == {MaxWaitCntDw{1'b1}}) + `ASSUME_FPV(WaitPeriod1_M, ping_timeout_cyc_i <= {MaxWaitCntDw{1'b1}}) + + //////////////////////// + // Forward Assertions // + //////////////////////// + + // no pings on disabled alerts + `ASSERT(DisabledNoAlertPings_A, ((~alert_ping_en_i) & alert_ping_req_o) == 0) + // no pings when not enabled + `ASSERT(NoPingsWhenDisabled0_A, !en_i |-> !alert_ping_req_o) + `ASSERT(NoPingsWhenDisabled1_A, !en_i |-> !esc_ping_req_o) + `ASSERT(NoPingsWhenDisabled2_A, en_i && !ping_en_mask[ping_en_sel] |-> + !ping_en_vector[ping_en_sel]) + + // spurious pings (i.e. pings that where not requested) + // on alert channels + `ASSERT(SpuriousPingsDetected0_A, en_i && !ping_en_vector[ping_en_sel] && + ping_ok_vector[ping_en_sel] && ping_en_sel < NAlerts |-> + alert_ping_fail_o) + // on escalation channels + `ASSERT(SpuriousPingsDetected1_A, en_i && !ping_en_vector[ping_en_sel] && + ping_ok_vector[ping_en_sel] && ping_en_sel >= NAlerts |-> + esc_ping_fail_o) + // response must be one hot + `ASSERT(SpuriousPingsDetected2_A, en_i && !$onehot0(ping_ok_vector) |-> + esc_ping_fail_o || alert_ping_fail_o) + + // ensure that the number of cycles between pings on a specific escalation channel + // are within bounds. we try to prove this property with a margin of 2x here, whereas + // the ping receivers actually work with a margin of 4x to stay on the safe side. + localparam int MarginFactor = 2; + localparam int NumWaitCounts = 2; + localparam int NumTimeoutCounts = 2; + localparam int PingPeriodBound = MarginFactor * // margin to apply + N_ESC_SEV * // number of escalation channels to ping + (NumWaitCounts + // 1 alert and 1 esc wait count + NumTimeoutCounts) * // 1 alert and 1 esc timeout count + 2**MaxWaitCntDw; // maximum counter value + + `ASSERT(EscalationPingPeriodWithinBounds_A, + $rose(esc_ping_req_o[esc_idx]) + |-> + ##[1 : PingPeriodBound] + $rose(esc_ping_req_o[esc_idx])) + + ///////////////////////// + // Backward Assertions // + ///////////////////////// + + // no pings when not enabled + `ASSERT(NoPingsWhenDisabledBkwd0_A, alert_ping_req_o |-> en_i) + `ASSERT(NoPingsWhenDisabledBkwd1_A, esc_ping_req_o |-> en_i) + + // spurious pings (i.e. pings that where not requested) + // on alert channels + `ASSERT(SpuriousPingsDetectedBkwd0_A, !alert_ping_fail_o |-> + !en_i || ping_en_vector[ping_en_sel] || + !ping_ok_vector[ping_en_sel] || ping_en_sel >= NAlerts) + // on escalation channels + `ASSERT(SpuriousPingsDetectedBkwd1_A, !esc_ping_fail_o |-> + !en_i || ping_en_vector[ping_en_sel] || + !ping_ok_vector[ping_en_sel] || ping_en_sel < NAlerts) + // response must be one hot + `ASSERT(SpuriousPingsDetectedBkwd2_A, !esc_ping_fail_o && !alert_ping_fail_o |-> + !en_i || $onehot0(ping_ok_vector)) + + ////////////////////////////////////////////////////////// + // Currently not Tested in FPV due to large state space // + ////////////////////////////////////////////////////////// + + // 1) if an alert is enabled, it should be pinged eventually + // when entropy input is disabled + // 2) ping ok within timeout -> ok + // 3) ping ok after timeout -> alert + // 4) no ping response -> alert + +endmodule : alert_handler_ping_timer_assert_fpv diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/lint/alert_handler.vlt b/hw/top_darjeeling/ip_autogen/alert_handler/lint/alert_handler.vlt new file mode 100644 index 0000000000000..b2bafa9c6dfd6 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/lint/alert_handler.vlt @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`verilator_config + +// Tell the Verilator scheduler to split up hw2reg_wrap into separate fields +// when scheduling processes. This structure is used (among other things) to +// communicate between alert_handler_accu and alert_handler_esc_timer instances +// and tracking it as one big blob causes spurious apparent circular +// dependencies. +split_var -module "alert_handler" -var "hw2reg_wrap" diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/lint/alert_handler.waiver b/hw/top_darjeeling/ip_autogen/alert_handler/lint/alert_handler.waiver new file mode 100644 index 0000000000000..b34560b25677a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/lint/alert_handler.waiver @@ -0,0 +1,44 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for alert handler + +waive -rules ENUM_RANGE -location {alert_handler_esc_timer.sv} -regexp {state_q} \ + -comment "State is used to index timeout cycle counts" + +waive -rules NOT_READ -location {alert_handler_ping_timer.sv} -regexp {perm_state} \ + -comment "Upper bits of permuted array are not read" + +waive -rules HIER_NET_NOT_READ -location {alert_handler_ping_timer.sv} -regexp {perm_state} \ + -comment "Upper bits of permuted array are not read" + +waive -rules HIER_NET_NOT_READ -location {alert_handler.sv} -regexp {[Nn]et 'tl_[io]\.[ad]_(address|param|user)} \ + -comment "Register interface doesn't use upper address and param, user filed" + +waive -rules INSIDE_OP_CONTEXT -location {prim_esc_sender.sv} -regexp {inside} \ + -comment "Inside operator is used within SVA" + +waive -rules CASE_INC -location {alert_handler_esc_timer.sv} -regexp {'b010} \ + -comment "Not all case tags are required." + +waive -rules CASE_INC -location {alert_handler_ping_timer.sv} -regexp {'b11} \ + -comment "Not all case tags are required." + +waive -rules CASE_INC -location {prim_esc_sender.sv} -regexp {'b111} \ + -comment "Not all case tags are required." + +waive -rules ONE_BIT_VEC -location {prim_lfsr.sv} -regexp {InDw - 1:0} \ + -comment "Data input may be one bit wide." + +waive -rules VAR_INDEX -location {alert_handler_esc_timer.sv} -regexp {phase_cyc_i\[phase_idx\]} \ + -comment "This indexing expression is correct." + +waive -rules VAR_INDEX -location {alert_handler_ping_timer.sv} -regexp {enable_mask\[id_to_ping\]} \ + -comment "This indexing expression is correct." + +waive -rules CLOCK_USE -location {alert_handler_lpg_ctrl.sv} -msg {'clk_i' is connected to 'prim_lc_sync' port 'clk_i', and used as} \ + -comment "This clock connection is only used for assertions internal to the prim module." + +waive -rules RESET_USE -location {alert_handler_lpg_ctrl.sv} -msg {'rst_ni' is connected to 'prim_lc_sync' port 'rst_ni', and used as} \ + -comment "This reset connection is only used for assertions internal to the prim module." diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler.sv b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler.sv new file mode 100644 index 0000000000000..a3e9bd9599d3c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler.sv @@ -0,0 +1,334 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Alert handler top + +`include "prim_assert.sv" + +module alert_handler + import alert_pkg::*; + import prim_alert_pkg::*; + import prim_esc_pkg::*; +#( + // Compile time random constants, to be overriden by topgen. + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault +) ( + input clk_i, + input rst_ni, + input rst_shadowed_ni, + input clk_edn_i, + input rst_edn_ni, + // Bus Interface (device) + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // Interrupt Requests + output logic intr_classa_o, + output logic intr_classb_o, + output logic intr_classc_o, + output logic intr_classd_o, + // Clock gating and reset info from rstmgr and clkmgr + // SEC_CM: LPG.INTERSIG.MUBI + input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_cg_en_i, + input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_rst_en_i, + // State information for HW crashdump + output alert_crashdump_t crashdump_o, + // Entropy Input + output edn_pkg::edn_req_t edn_o, + input edn_pkg::edn_rsp_t edn_i, + // Alert Sources + // SEC_CM: ALERT.INTERSIG.DIFF + input alert_tx_t [NAlerts-1:0] alert_tx_i, + output alert_rx_t [NAlerts-1:0] alert_rx_o, + // Escalation outputs + // SEC_CM: ESC.INTERSIG.DIFF + input esc_rx_t [N_ESC_SEV-1:0] esc_rx_i, + output esc_tx_t [N_ESC_SEV-1:0] esc_tx_o +); + + ////////////////////////////////// + // Regfile Breakout and Mapping // + ////////////////////////////////// + + logic [N_CLASSES-1:0] latch_crashdump; + logic [N_LOC_ALERT-1:0] loc_alert_trig; + logic [N_CLASSES-1:0] irq; + hw2reg_wrap_t hw2reg_wrap; + reg2hw_wrap_t reg2hw_wrap; + + assign {intr_classd_o, + intr_classc_o, + intr_classb_o, + intr_classa_o} = irq; + + // SEC_CM: CONFIG.SHADOW + // SEC_CM: PING_TIMER.CONFIG.REGWEN + // SEC_CM: ALERT.CONFIG.REGWEN + // SEC_CM: ALERT_LOC.CONFIG.REGWEN + // SEC_CM: CLASS.CONFIG.REGWEN + alert_handler_reg_wrap u_reg_wrap ( + .clk_i, + .rst_ni, + .rst_shadowed_ni, + .tl_i, + .tl_o, + .irq_o ( irq ), + .latch_crashdump_i ( latch_crashdump ), + .crashdump_o, + .hw2reg_wrap, + .reg2hw_wrap, + // SEC_CM: BUS.INTEGRITY + .fatal_integ_alert_o(loc_alert_trig[4]) + ); + + // SEC_CM: CONFIG.SHADOW + assign loc_alert_trig[5] = reg2hw_wrap.shadowed_err_update; + assign loc_alert_trig[6] = reg2hw_wrap.shadowed_err_storage; + + //////////////// + // Ping Timer // + //////////////// + + logic [NAlerts-1:0] alert_ping_req; + logic [NAlerts-1:0] alert_ping_ok; + logic [N_ESC_SEV-1:0] esc_ping_req; + logic [N_ESC_SEV-1:0] esc_ping_ok; + + logic edn_req, edn_ack; + logic [LfsrWidth-1:0] edn_data; + + prim_edn_req #( + .OutWidth(LfsrWidth) + ) u_edn_req ( + // Alert handler side + .clk_i, + .rst_ni, + .req_chk_i ( 1'b1 ), + .req_i ( edn_req ), + .ack_o ( edn_ack ), + .data_o ( edn_data ), + .fips_o ( ), + .err_o ( ), + // EDN side + .clk_edn_i, + .rst_edn_ni, + .edn_o ( edn_o ), + .edn_i ( edn_i ) + ); + + alert_handler_ping_timer #( + .RndCnstLfsrSeed(RndCnstLfsrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm) + ) u_ping_timer ( + .clk_i, + .rst_ni, + .edn_req_o ( edn_req ), + .edn_ack_i ( edn_ack ), + .edn_data_i ( edn_data ), + .en_i ( reg2hw_wrap.ping_enable ), + .alert_ping_en_i ( reg2hw_wrap.alert_ping_en ), + .ping_timeout_cyc_i ( reg2hw_wrap.ping_timeout_cyc ), + // set this to the maximum width in the design. + // can be overridden in DV and FPV to shorten the wait periods. + // note however that this needs to be a right-aligned mask. + // also, do not set this to a value lower than 0x7. + .wait_cyc_mask_i ( {PING_CNT_DW{1'b1}} ), + // SEC_CM: ALERT_RX.INTERSIG.BKGN_CHK + .alert_ping_req_o ( alert_ping_req ), + // SEC_CM: ESC_TX.INTERSIG.BKGN_CHK + .esc_ping_req_o ( esc_ping_req ), + .alert_ping_ok_i ( alert_ping_ok ), + .esc_ping_ok_i ( esc_ping_ok ), + .alert_ping_fail_o ( loc_alert_trig[0] ), + .esc_ping_fail_o ( loc_alert_trig[1] ) + ); + + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(PingTimerEscCnterCheck_A, + u_ping_timer.u_prim_count_esc_cnt, + loc_alert_trig[0] & loc_alert_trig[1], + (reg2hw_wrap.ping_enable == 0)) + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(PingTimerCnterCheck_A, + u_ping_timer.u_prim_count_cnt, + loc_alert_trig[0] & loc_alert_trig[1], + (reg2hw_wrap.ping_enable == 0)) + `ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR(PingTimerDoubleLfsrCheck_A, + u_ping_timer.u_prim_double_lfsr, + loc_alert_trig[0] & loc_alert_trig[1], + (reg2hw_wrap.ping_enable == 0)) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(PingTimerFsmCheck_A, + u_ping_timer.u_state_regs, + loc_alert_trig[0] & loc_alert_trig[1], + (reg2hw_wrap.ping_enable == 0)) + + ///////////////////////////// + // Low-power group control // + ///////////////////////////// + + prim_mubi_pkg::mubi4_t [NAlerts-1:0] alert_init_trig; + alert_handler_lpg_ctrl u_alert_handler_lpg_ctrl ( + .clk_i, + .rst_ni, + // SEC_CM: LPG.INTERSIG.MUBI + .lpg_cg_en_i, + .lpg_rst_en_i, + .alert_init_trig_o ( alert_init_trig ) + ); + + ///////////////////// + // Alert Receivers // + ///////////////////// + + logic [NAlerts-1:0] alert_integfail; + logic [NAlerts-1:0] alert_trig; + + // Target interrupt notification + for (genvar k = 0 ; k < NAlerts ; k++) begin : gen_alerts + prim_alert_receiver #( + .AsyncOn(AsyncOn[k]) + ) u_alert_receiver ( + .clk_i, + .rst_ni, + .init_trig_i ( alert_init_trig[k] ), + .ping_req_i ( alert_ping_req[k] ), + .ping_ok_o ( alert_ping_ok[k] ), + .integ_fail_o ( alert_integfail[k] ), + .alert_o ( alert_trig[k] ), + // SEC_CM: ALERT.INTERSIG.DIFF + .alert_rx_o ( alert_rx_o[k] ), + .alert_tx_i ( alert_tx_i[k] ) + ); + end + + assign loc_alert_trig[2] = |(reg2hw_wrap.alert_en & alert_integfail); + + /////////////////////////////////////// + // Set alert cause bits and classify // + /////////////////////////////////////// + + alert_handler_class u_class ( + .alert_trig_i ( alert_trig ), + .loc_alert_trig_i ( loc_alert_trig ), + .alert_en_i ( reg2hw_wrap.alert_en ), + .loc_alert_en_i ( reg2hw_wrap.loc_alert_en ), + .alert_class_i ( reg2hw_wrap.alert_class ), + .loc_alert_class_i ( reg2hw_wrap.loc_alert_class ), + .alert_cause_o ( hw2reg_wrap.alert_cause ), + .loc_alert_cause_o ( hw2reg_wrap.loc_alert_cause ), + .class_trig_o ( hw2reg_wrap.class_trig ) + ); + + //////////////////////////////////// + // Escalation Handling of Classes // + //////////////////////////////////// + + logic [N_CLASSES-1:0][N_ESC_SEV-1:0] class_esc_sig_req; + + for (genvar k = 0; k < N_CLASSES; k++) begin : gen_classes + logic class_accu_fail, class_accu_trig; + alert_handler_accu u_accu ( + .clk_i, + .rst_ni, + .class_en_i ( reg2hw_wrap.class_en[k] ), + .clr_i ( reg2hw_wrap.class_clr[k] ), + .class_trig_i ( hw2reg_wrap.class_trig[k] ), + .thresh_i ( reg2hw_wrap.class_accum_thresh[k] ), + .accu_cnt_o ( hw2reg_wrap.class_accum_cnt[k] ), + .accu_trig_o ( class_accu_trig ), + .accu_fail_o ( class_accu_fail ) + ); + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(AccuCnterCheck_A, + u_accu.u_prim_count, + esc_tx_o[0].esc_p & esc_tx_o[1].esc_p & esc_tx_o[2].esc_p & esc_tx_o[3].esc_p) + + alert_handler_esc_timer u_esc_timer ( + .clk_i, + .rst_ni, + .en_i ( reg2hw_wrap.class_en[k] ), + // this clear does not apply to interrupts + .clr_i ( reg2hw_wrap.class_clr[k] ), + // an interrupt enables the timeout + .timeout_en_i ( irq[k] ), + .accu_trig_i ( class_accu_trig ), + .accu_fail_i ( class_accu_fail ), + .timeout_cyc_i ( reg2hw_wrap.class_timeout_cyc[k] ), + .esc_en_i ( reg2hw_wrap.class_esc_en[k] ), + .esc_map_i ( reg2hw_wrap.class_esc_map[k] ), + .phase_cyc_i ( reg2hw_wrap.class_phase_cyc[k] ), + .crashdump_phase_i ( reg2hw_wrap.class_crashdump_phase[k] ), + .latch_crashdump_o ( latch_crashdump[k] ), + .esc_trig_o ( hw2reg_wrap.class_esc_trig[k] ), + .esc_cnt_o ( hw2reg_wrap.class_esc_cnt[k] ), + .esc_state_o ( hw2reg_wrap.class_esc_state[k] ), + .esc_sig_req_o ( class_esc_sig_req[k] ) + ); + + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(EscTimerCnterCheck_A, + u_esc_timer.u_prim_count, + esc_tx_o[0].esc_p & esc_tx_o[1].esc_p & esc_tx_o[2].esc_p & esc_tx_o[3].esc_p) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(EscTimerFsmCheck_A, + u_esc_timer.u_state_regs, + esc_tx_o[0].esc_p & esc_tx_o[1].esc_p & esc_tx_o[2].esc_p & esc_tx_o[3].esc_p) + end + + //////////////////////// + // Escalation Senders // + //////////////////////// + + logic [N_ESC_SEV-1:0] esc_sig_req; + logic [N_ESC_SEV-1:0] esc_integfail; + logic [N_ESC_SEV-1:0][N_CLASSES-1:0] esc_sig_req_trsp; + + for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_esc_sev + for (genvar j = 0; j < N_CLASSES; j++) begin : gen_transp + assign esc_sig_req_trsp[k][j] = class_esc_sig_req[j][k]; + end + + assign esc_sig_req[k] = |esc_sig_req_trsp[k]; + // SEC_CM: ESC_RX.INTERSIG.BKGN_CHK + // Note: This countermeasure is actually implemented on the receiver side. We currently cannot + // put this RTL label inside that module due to the way our countermeasure annotation check + // script discovers the RTL files. The label is thus put here. Please refer to + // prim_esc_receiver.sv for the actual implementation of this mechanism. + prim_esc_sender u_esc_sender ( + .clk_i, + .rst_ni, + .ping_req_i ( esc_ping_req[k] ), + .ping_ok_o ( esc_ping_ok[k] ), + .integ_fail_o ( esc_integfail[k] ), + .esc_req_i ( esc_sig_req[k] ), + // SEC_CM: ESC.INTERSIG.DIFF + .esc_rx_i ( esc_rx_i[k] ), + .esc_tx_o ( esc_tx_o[k] ) + ); + end + + assign loc_alert_trig[3] = |esc_integfail; + + //////////////// + // Assertions // + //////////////// + + // check whether all outputs have a good known state after reset + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready) + `ASSERT_KNOWN(IrqAKnownO_A, intr_classa_o) + `ASSERT_KNOWN(IrqBKnownO_A, intr_classb_o) + `ASSERT_KNOWN(IrqCKnownO_A, intr_classc_o) + `ASSERT_KNOWN(IrqDKnownO_A, intr_classd_o) + `ASSERT_KNOWN(CrashdumpKnownO_A, crashdump_o) + `ASSERT_KNOWN(AckPKnownO_A, alert_rx_o) + `ASSERT_KNOWN(EscPKnownO_A, esc_tx_o) + `ASSERT_KNOWN(EdnKnownO_A, edn_o) + + // this restriction is due to specifics in the ping selection mechanism + `ASSERT_INIT(CheckNAlerts, NAlerts < (256 - N_CLASSES)) + `ASSERT_INIT(CheckEscCntDw, EscCntDw <= 32) + `ASSERT_INIT(CheckAccuCntDw, AccuCntDw <= 32) + `ASSERT_INIT(CheckNClasses, N_CLASSES <= 8) + `ASSERT_INIT(CheckNEscSev, N_ESC_SEV <= 8) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(RegWeOnehotCheck_A, + u_reg_wrap.u_reg, loc_alert_trig[4]) +endmodule diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_accu.sv b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_accu.sv new file mode 100644 index 0000000000000..e1eb6ad23b7e2 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_accu.sv @@ -0,0 +1,65 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module accumulates incoming alert triggers. Once the current accumulator +// value is greater or equal the accumulator threshold, the next occurence of +// class_trig_i will trigger escalation. +// +// Note that the accumulator is implemented using a saturation counter which +// does not wrap around. +// + +`include "prim_assert.sv" + +module alert_handler_accu import alert_pkg::*; ( + input clk_i, + input rst_ni, + input class_en_i, // class enable + input clr_i, // clear the accumulator + input class_trig_i, // increments the accu + input [AccuCntDw-1:0] thresh_i, // escalation trigger threshold + output logic [AccuCntDw-1:0] accu_cnt_o, // output of current accu value + output logic accu_trig_o, // escalation trigger output + output logic accu_fail_o // asserted if the tandem accu counters are not equal +); + + logic trig_gated, accu_en; + assign trig_gated = class_trig_i & class_en_i; + assign accu_en = trig_gated && !(&accu_cnt_o); + + // SEC_CM: ACCU.CTR.REDUN + // We employ two redundant counters to guard against FI attacks. + // If any of the two is glitched and the two counter states do not agree, + // the check_fail_o signal is asserted which will move the corresponding escalation + // FSM into a terminal error state where all escalation actions will be permanently asserted. + prim_count #( + .Width(AccuCntDw), + // The alert handler behaves differently than other comportable IP. I.e., instead of sending out + // an alert signal, this condition is handled internally in the alert handler. + .EnableAlertTriggerSVA(0) + ) u_prim_count ( + .clk_i, + .rst_ni, + .clr_i, + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(accu_en), + .decr_en_i(1'b0), + .step_i(AccuCntDw'(1)), + .cnt_o(accu_cnt_o), + .commit_i(1'b1), + .cnt_after_commit_o(), + .err_o(accu_fail_o) + ); + + assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated; + + //////////////// + // Assertions // + //////////////// + + `ASSERT(DisabledNoTrigFwd_A, !class_en_i |-> !accu_trig_o) + `ASSERT(DisabledNoTrigBkwd_A, accu_trig_o |-> class_en_i) + `ASSERT(CountSaturateStable_A, accu_cnt_o == {AccuCntDw{1'b1}} |=> $stable(accu_cnt_o)) +endmodule : alert_handler_accu diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_class.sv b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_class.sv new file mode 100644 index 0000000000000..598db384a4737 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_class.sv @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module gates the alert triggers with their enable bits, and correctly bins +// the enabled alerts into the class that they have been assigned to. The module +// produces the alert cause and class trigger signals. +// + +module alert_handler_class import alert_pkg::*; ( + input [NAlerts-1:0] alert_trig_i, // alert trigger + input [N_LOC_ALERT-1:0] loc_alert_trig_i, // alert trigger + input [NAlerts-1:0] alert_en_i, // alert enable + input [N_LOC_ALERT-1:0] loc_alert_en_i, // alert enable + input [NAlerts-1:0] [CLASS_DW-1:0] alert_class_i, // class assignment + input [N_LOC_ALERT-1:0][CLASS_DW-1:0] loc_alert_class_i, // class assignment + + output logic [NAlerts-1:0] alert_cause_o, // alert cause + output logic [N_LOC_ALERT-1:0] loc_alert_cause_o, // alert cause + output logic [N_CLASSES-1:0] class_trig_o // class triggered +); + + // assign alert cause + assign alert_cause_o = alert_en_i & alert_trig_i; + assign loc_alert_cause_o = loc_alert_en_i & loc_alert_trig_i; + + // classification mapping + logic [N_CLASSES-1:0][NAlerts-1:0] class_masks; + logic [N_CLASSES-1:0][N_LOC_ALERT-1:0] loc_class_masks; + + // this is basically an address to onehot0 decoder + always_comb begin : p_class_mask + class_masks = '0; + loc_class_masks = '0; + for (int unsigned kk = 0; kk < NAlerts; kk++) begin + class_masks[alert_class_i[kk]][kk] = 1'b1; + end + for (int unsigned kk = 0; kk < N_LOC_ALERT; kk++) begin + loc_class_masks[loc_alert_class_i[kk]][kk] = 1'b1; + end + end + + // mask and OR reduction, followed by class enable gating + for (genvar k = 0; k < N_CLASSES; k++) begin : gen_classifier + assign class_trig_o[k] = (|{ alert_cause_o & class_masks[k], + loc_alert_cause_o & loc_class_masks[k] }); + end + +endmodule : alert_handler_class diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_esc_timer.sv b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_esc_timer.sv new file mode 100644 index 0000000000000..20abbed882709 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_esc_timer.sv @@ -0,0 +1,432 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module implements the escalation timer, which times the four escalation +// phases. There are two mechanisms that can trigger the escalation protocol: +// +// 1) via accum_trigger_i, which will be asserted once the accumulator value +// exceeds a programmable amount of alert occurences. +// +// 2) via an interrupt timeout, if this is enabled. If this functionality is +// enabled, the internal escalation counter is reused to check whether the +// interrupt times out. If it does time out, the outcome is the same as if +// accum_trigger_i where asserted. +// +// Note that escalation always takes precedence over the interrupt timeout. +// + +`include "prim_assert.sv" + +module alert_handler_esc_timer import alert_pkg::*; ( + input clk_i, + input rst_ni, + input en_i, // enables timeout/escalation + input clr_i, // aborts escalation + input accu_trig_i, // this triggers escalation + input accu_fail_i, // this moves the FSM into a terminal error state + input timeout_en_i, // enables timeout + input [EscCntDw-1:0] timeout_cyc_i, // interrupt timeout. 0 = disabled + input [N_ESC_SEV-1:0] esc_en_i, // escalation signal enables + input [N_ESC_SEV-1:0] + [PHASE_DW-1:0] esc_map_i, // escalation signal / phase map + input [N_PHASES-1:0] + [EscCntDw-1:0] phase_cyc_i, // cycle counts of individual phases + input [PHASE_DW-1:0] crashdump_phase_i, // determines when to assert latch_crashdump_o + output logic latch_crashdump_o, // asserted when entering escalation + output logic esc_trig_o, // asserted if escalation triggers + output logic [EscCntDw-1:0] esc_cnt_o, // current timeout / escalation count + output logic [N_ESC_SEV-1:0] esc_sig_req_o, // escalation signal outputs + // current state output + // 000: idle, 001: irq timeout counting 100: phase0, 101: phase1, 110: phase2, 111: phase3 + output cstate_e esc_state_o +); + + //////////////////// + // Tandem Counter // + //////////////////// + + // We employ two redundant counters to guard against FI attacks. + // If any of the two is glitched and the two counter states do not agree, + // the FSM below is moved into a terminal error state and escalation actions + // are permanently asserted. + logic cnt_en, cnt_clr, cnt_error; + + // SEC_CM: ESC_TIMER.CTR.REDUN + prim_count #( + .Width(EscCntDw), + // The alert handler behaves differently than other comportable IP. I.e., instead of sending out + // an alert signal, this condition is handled internally in the alert handler. + .EnableAlertTriggerSVA(0), + // Pass a parameter to disable coverage for some assertions that are unreachable because + // decr_en_i is tied to zero. + .PossibleActions(prim_count_pkg::Clr | + prim_count_pkg::Set | + prim_count_pkg::Incr) + ) u_prim_count ( + .clk_i, + .rst_ni, + .clr_i(cnt_clr && !cnt_en), + .set_i(cnt_clr && cnt_en), + .set_cnt_i(EscCntDw'(1)), + .incr_en_i(cnt_en), + .decr_en_i(1'b0), + .step_i(EscCntDw'(1)), + .commit_i(1'b1), + .cnt_o(esc_cnt_o), + .cnt_after_commit_o(), + .err_o(cnt_error) + ); + + // threshold test, the thresholds are muxed further below + // depending on the current state + logic cnt_ge; + logic [EscCntDw-1:0] thresh; + assign cnt_ge = (esc_cnt_o >= thresh); + + ////////////// + // Main FSM // + ////////////// + + logic [N_PHASES-1:0] phase_oh; + + // SEC_CM: ESC_TIMER.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \ + // -s 784905746 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (46.43%) + // 6: |||||||||||||||||||| (46.43%) + // 7: ||| (7.14%) + // 8: -- + // 9: -- + // 10: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 7 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 9 + // + localparam int StateWidth = 10; + typedef enum logic [StateWidth-1:0] { + IdleSt = 10'b1011011010, + TimeoutSt = 10'b0000100110, + Phase0St = 10'b1110000101, + Phase1St = 10'b0101010100, + Phase2St = 10'b0000011001, + Phase3St = 10'b1001100001, + TerminalSt = 10'b1101111111, + FsmErrorSt = 10'b0111101000 + } state_e; + + logic fsm_error; + state_e state_d, state_q; + + always_comb begin : p_fsm + // default + state_d = state_q; + esc_state_o = Idle; + cnt_en = 1'b0; + cnt_clr = 1'b0; + esc_trig_o = 1'b0; + phase_oh = '0; + thresh = timeout_cyc_i; + fsm_error = 1'b0; + latch_crashdump_o = 1'b0; + + unique case (state_q) + // wait for an escalation trigger or an alert trigger + // the latter will trigger an interrupt timeout + IdleSt: begin + cnt_clr = 1'b1; + esc_state_o = Idle; + + if (accu_trig_i && en_i && !clr_i) begin + state_d = Phase0St; + cnt_en = 1'b1; + esc_trig_o = 1'b1; + // the counter is zero in this state. so if the + // timeout count is zero (==disabled), cnt_ge will be true. + end else if (timeout_en_i && !cnt_ge && en_i) begin + cnt_en = 1'b1; + state_d = TimeoutSt; + end + end + // we are in interrupt timeout state + // in case an escalation comes in, we immediately have to + // switch over to the first escalation phase. + // in case the interrupt timeout hits it's cycle count, we + // also enter escalation phase0. + // ongoing timeouts can always be cleared. + TimeoutSt: begin + esc_state_o = Timeout; + + if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin + state_d = Phase0St; + cnt_en = 1'b1; + cnt_clr = 1'b1; + esc_trig_o = 1'b1; + // the timeout enable is connected to the irq state + // if that is cleared, stop the timeout counter + end else if (timeout_en_i) begin + cnt_en = 1'b1; + end else begin + state_d = IdleSt; + cnt_clr = 1'b1; + end + end + // note: autolocking the clear signal is done in the regfile + Phase0St: begin + cnt_en = 1'b1; + phase_oh[0] = 1'b1; + thresh = phase_cyc_i[0]; + esc_state_o = Phase0; + latch_crashdump_o = (crashdump_phase_i == 2'b00); + + if (clr_i) begin + state_d = IdleSt; + cnt_clr = 1'b1; + cnt_en = 1'b0; + end else if (cnt_ge) begin + state_d = Phase1St; + cnt_clr = 1'b1; + cnt_en = 1'b1; + end + end + Phase1St: begin + cnt_en = 1'b1; + phase_oh[1] = 1'b1; + thresh = phase_cyc_i[1]; + esc_state_o = Phase1; + latch_crashdump_o = (crashdump_phase_i == 2'b01); + + if (clr_i) begin + state_d = IdleSt; + cnt_clr = 1'b1; + cnt_en = 1'b0; + end else if (cnt_ge) begin + state_d = Phase2St; + cnt_clr = 1'b1; + cnt_en = 1'b1; + end + end + Phase2St: begin + cnt_en = 1'b1; + phase_oh[2] = 1'b1; + thresh = phase_cyc_i[2]; + esc_state_o = Phase2; + latch_crashdump_o = (crashdump_phase_i == 2'b10); + + + if (clr_i) begin + state_d = IdleSt; + cnt_clr = 1'b1; + cnt_en = 1'b0; + end else if (cnt_ge) begin + state_d = Phase3St; + cnt_clr = 1'b1; + end + end + Phase3St: begin + cnt_en = 1'b1; + phase_oh[3] = 1'b1; + thresh = phase_cyc_i[3]; + esc_state_o = Phase3; + latch_crashdump_o = (crashdump_phase_i == 2'b11); + + if (clr_i) begin + state_d = IdleSt; + cnt_clr = 1'b1; + cnt_en = 1'b0; + end else if (cnt_ge) begin + state_d = TerminalSt; + cnt_clr = 1'b1; + cnt_en = 1'b0; + end + end + // final, terminal state after escalation. + // if clr is locked down, only a system reset + // will get us out of this state + TerminalSt: begin + cnt_clr = 1'b1; + esc_state_o = Terminal; + if (clr_i) begin + state_d = IdleSt; + end + end + // error state, only reached if the FSM has been + // glitched. in this state, we trigger all escalation + // actions at once. + FsmErrorSt: begin + esc_state_o = FsmError; + fsm_error = 1'b1; + end + // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC + // catch glitches. + default: begin + state_d = FsmErrorSt; + esc_state_o = FsmError; + fsm_error = 1'b1; + end + endcase + + // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC + // if any of the duplicate counter pairs has an inconsistent state + // we move into the terminal FSM error state. + if (accu_fail_i || cnt_error) begin + state_d = FsmErrorSt; + fsm_error = 1'b1; + end + end + + logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh; + for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map + // generate configuration mask for escalation enable signals + assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k]; + // mask reduce current phase state vector + // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC + assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error; + end + + /////////////////// + // FSM Registers // + /////////////////// + + // The alert handler behaves differently than other comportable IP. I.e., instead of sending out + // an alert signal, this condition is handled internally in the alert handler. The + // EnableAlertTriggerSVA parameter is therefore set to 0. + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0) + + //////////////// + // Assertions // + //////////////// + + // a clear should always bring us back to idle + `ASSERT(CheckClr_A, + !accu_fail_i && + clr_i && + !(state_q inside {IdleSt, TimeoutSt, FsmErrorSt}) + |=> + state_q == IdleSt) + // if currently in idle and not enabled, must remain here + `ASSERT(CheckEn_A, + !accu_fail_i && + state_q == IdleSt && + !en_i + |=> + state_q == IdleSt) + // Check if accumulation trigger correctly captured + `ASSERT(CheckAccumTrig0_A, + !accu_fail_i && + accu_trig_i && + state_q == IdleSt && + en_i && + !clr_i + |=> + state_q == Phase0St) + `ASSERT(CheckAccumTrig1_A, + !accu_fail_i && + accu_trig_i && + state_q == TimeoutSt && + en_i && + !clr_i + |=> + state_q == Phase0St) + // Check if timeout correctly captured + `ASSERT(CheckTimeout0_A, + !accu_fail_i && + state_q == IdleSt && + timeout_en_i && + en_i && + timeout_cyc_i != 0 && + !accu_trig_i + |=> + state_q == TimeoutSt) + `ASSERT(CheckTimeoutSt1_A, + !accu_fail_i && + state_q == TimeoutSt && + timeout_en_i && + esc_cnt_o < timeout_cyc_i && + !accu_trig_i + |=> + state_q == TimeoutSt) + `ASSERT(CheckTimeoutSt2_A, + !accu_fail_i && + state_q == TimeoutSt && + !timeout_en_i && + !accu_trig_i + |=> + state_q == IdleSt) + // Check if timeout correctly triggers escalation + `ASSERT(CheckTimeoutStTrig_A, + !accu_fail_i && + state_q == TimeoutSt && + timeout_en_i && + esc_cnt_o == timeout_cyc_i + |=> + state_q == Phase0St) + // Check whether escalation phases are correctly switched + `ASSERT(CheckPhase0_A, + !accu_fail_i && + state_q == Phase0St && + !clr_i && + esc_cnt_o >= phase_cyc_i[0] + |=> + state_q == Phase1St) + `ASSERT(CheckPhase1_A, + !accu_fail_i && + state_q == Phase1St && + !clr_i && + esc_cnt_o >= phase_cyc_i[1] + |=> + state_q == Phase2St) + `ASSERT(CheckPhase2_A, + !accu_fail_i && + state_q == Phase2St && + !clr_i && + esc_cnt_o >= phase_cyc_i[2] + |=> + state_q == Phase3St) + `ASSERT(CheckPhase3_A, + !accu_fail_i && + state_q == Phase3St && + !clr_i && + esc_cnt_o >= phase_cyc_i[3] + |=> + state_q == TerminalSt) + `ASSERT(AccuFailToFsmError_A, + accu_fail_i + |=> + state_q == FsmErrorSt) + `ASSERT(ErrorStIsTerminal_A, + state_q == FsmErrorSt + |=> + state_q == FsmErrorSt) + `ASSERT(ErrorStAllEscAsserted_A, + state_q == FsmErrorSt + |-> + esc_sig_req_o == '1) + +`ifdef INC_ASSERT + // Check that our internal FSM matches the state index that we're exposing with esc_state_o. The + // StateEncodings parameter does the mapping to match. (Practically speaking, this is just adding + // "St" to each name so e.g. Idle gets mapped to IdleSt). + parameter logic [StateWidth-1:0] StateEncodings [8] = '{IdleSt, + TimeoutSt, + FsmErrorSt, + TerminalSt, + Phase0St, + Phase1St, + Phase2St, + Phase3St}; + `ASSERT(EscStateOut_A, state_q == StateEncodings[esc_state_o]) +`endif + +endmodule : alert_handler_esc_timer diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_lpg_ctrl.sv b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_lpg_ctrl.sv new file mode 100644 index 0000000000000..18da953d2a567 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_lpg_ctrl.sv @@ -0,0 +1,90 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module gathers and synchronizes the clock gating and reset indication signals for all +// low-power groups (LPGs), synchronizes them to the alert handler clock domain. The clock gating +// and reset indication signals are then logically OR'ed to produce one multibit value for each +// LPG. The LPG multibit values are then mapped to the alert channels using the LpgMap parameter, +// and each multibit output value is buffered independently. +// + +`include "prim_assert.sv" + +module alert_handler_lpg_ctrl import alert_pkg::*; ( + input clk_i, + input rst_ni, + // Low power clk and rst indication signals. + input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_cg_en_i, + input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_rst_en_i, + // Init requests going to the individual alert channels. + output prim_mubi_pkg::mubi4_t [NAlerts-1:0] alert_init_trig_o +); + + import prim_mubi_pkg::mubi4_t; + import prim_mubi_pkg::mubi4_or_hi; + import prim_mubi_pkg::MuBi4True; + + /////////////////////////////////////////////////// + // Aggregate multibit indication signals per LPG // + /////////////////////////////////////////////////// + + mubi4_t [NLpg-1:0] synced_lpg_cg_en, synced_lpg_rst_en, lpg_init_trig; + for (genvar k = 0; k < NLpg; k++) begin : gen_lpgs + prim_mubi4_sync #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sync_cg_en ( + .clk_i, + .rst_ni, + .mubi_i(lpg_cg_en_i[k]), + .mubi_o(synced_lpg_cg_en[k:k]) + ); + prim_mubi4_sync #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sync_rst_en ( + .clk_i, + .rst_ni, + .mubi_i(lpg_rst_en_i[k]), + .mubi_o(synced_lpg_rst_en[k:k]) + ); + + // Perform a logical OR operation of the multibit life cycle signals. + // I.e., if any of the incoming multibit signals is On, the output will also be On. + // Otherwise, the output may have any value other than On. + assign lpg_init_trig[k] = mubi4_or_hi(synced_lpg_cg_en[k], synced_lpg_rst_en[k]); + end + + ////////////////////////////////// + // LPG to Alert Channel Mapping // + ////////////////////////////////// + + // select the correct lpg for the alert channel at index j and buffer the multibit signal for each + // alert channel. + for (genvar j=0; j < NAlerts; j++) begin : gen_alert_map + prim_mubi4_sync #( + .AsyncOn(0) // no sync flops + ) u_prim_mubi4_sync_lpg_en ( + .clk_i, + .rst_ni, + .mubi_i(lpg_init_trig[LpgMap[j]]), + .mubi_o({alert_init_trig_o[j]}) + ); + end + + // explicitly read all unused lpg triggers to avoid lint errors. + logic [NLpg-1:0] lpg_used; + logic unused_lpg_init_trig; + always_comb begin + lpg_used = '0; + unused_lpg_init_trig = 1'b0; + for (int j=0; j < NAlerts; j++) begin + lpg_used[LpgMap[j]] |= 1'b1; + end + for (int k=0; k < NLpg; k++) begin + if (!lpg_used) begin + unused_lpg_init_trig ^= ^lpg_init_trig[k]; + end + end + end + +endmodule : alert_handler_lpg_ctrl diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_ping_timer.sv b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_ping_timer.sv new file mode 100644 index 0000000000000..bd9326b911639 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_ping_timer.sv @@ -0,0 +1,442 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module implements the ping mechanism. Once enabled, this module uses an +// LFSR-based PRNG to +// +// a) determine the next peripheral index to be pinged (can be an alert receiver or an +// escalation sender). it is detected that this particular peripheral is disabled, +// another index will be drawn from the PRNG. +// +// b) determine the amount of pause cycles to wait before pinging the peripheral selected in a). +// +// Once the ping timer waited for the amount of pause cycles determined in b), it asserts +// the ping enable signal of the peripheral determined in a). If that peripheral does +// not respond within the ping timeout window, an internal alert will be raised. +// +// Further, if a spurious ping_ok signal is detected (i.e., a ping ok that has not been +// requested), the ping timer will also raise an internal alert. +// + +`include "prim_assert.sv" + +module alert_handler_ping_timer import alert_pkg::*; #( + // Compile time random constants, to be overriden by topgen. + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault, + // Enable this for DV, disable this for long LFSRs in FPV + parameter bit MaxLenSVA = 1'b1, + // Can be disabled in cases where entropy + // inputs are unused in order to not distort coverage + // (the SVA will be unreachable in such cases) + parameter bit LockupSVA = 1'b1 +) ( + input clk_i, + input rst_ni, + output logic edn_req_o, // request to EDN + input edn_ack_i, // ack from EDN + input [LfsrWidth-1:0] edn_data_i, // from EDN + input en_i, // enable ping testing + input [NAlerts-1:0] alert_ping_en_i, // determines which alerts to ping + input [PING_CNT_DW-1:0] ping_timeout_cyc_i, // timeout in cycles + input [PING_CNT_DW-1:0] wait_cyc_mask_i, // mask to shorten the counters in DV / FPV + output logic [NAlerts-1:0] alert_ping_req_o, // request to alert receivers + output logic [N_ESC_SEV-1:0] esc_ping_req_o, // enable to esc senders + input [NAlerts-1:0] alert_ping_ok_i, // response from alert receivers + input [N_ESC_SEV-1:0] esc_ping_ok_i, // response from esc senders + output logic alert_ping_fail_o, // any of the alert receivers failed + output logic esc_ping_fail_o // any of the esc senders failed +); + + localparam int unsigned IdDw = $clog2(NAlerts); + + // Entropy reseeding is triggered every time this counter expires. + // The expected wait time between pings is 2**(PING_CNT_DW-1) on average. + // We do not need to reseed the LFSR very often, and the constant below is chosen + // such that on average the LFSR is reseeded every 16th ping. + localparam int unsigned ReseedLfsrExtraBits = 3; + localparam int unsigned ReseedLfsrWidth = PING_CNT_DW + ReseedLfsrExtraBits; + + // The number of bits needed for an index into the esc senders + localparam int unsigned EscSenderIdxWidth = $clog2(N_ESC_SEV); + + // A few smoke checks for the DV mask: + // 1) make sure the value is a right-aligned mask. + // this can be done by checking that mask+1 is a power of 2. + // 2) also make sure that the value is always >= 0x7. + `ASSERT(WaitCycMaskMin_A, wait_cyc_mask_i >= 'h7) + `ASSERT(WaitCycMaskIsRightAlignedMask_A, $onehot(32'(wait_cyc_mask_i) + 1)) + + //////////////////// + // Reseed counter // + //////////////////// + + logic reseed_en; + logic [ReseedLfsrWidth-1:0] reseed_timer_d, reseed_timer_q; + + assign reseed_timer_d = (reseed_timer_q > '0) ? reseed_timer_q - 1'b1 : + (reseed_en) ? {wait_cyc_mask_i, + {ReseedLfsrExtraBits{1'b1}}} : '0; + assign edn_req_o = (reseed_timer_q == '0); + assign reseed_en = edn_req_o & edn_ack_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + reseed_timer_q <= '0; + end else begin + reseed_timer_q <= reseed_timer_d; + end + end + + /////////////////////////// + // Tandem LFSR Instances // + /////////////////////////// + + logic cnt_set, lfsr_err; + logic [LfsrWidth-1:0] entropy; + logic [PING_CNT_DW + IdDw - 1:0] lfsr_state; + assign entropy = (reseed_en) ? edn_data_i[LfsrWidth-1:0] : '0; + + // SEC_CM: PING_TIMER.LFSR.REDUN + // We employ two redundant LFSRs to guard against FI attacks. + // If any of the two is glitched and the two LFSR states do not agree, + // the FSM below is moved into a terminal error state and all ping alerts + // are permanently asserted. + prim_double_lfsr #( + .LfsrDw ( LfsrWidth ), + .EntropyDw ( LfsrWidth ), + .StateOutDw ( PING_CNT_DW + IdDw ), + .DefaultSeed ( RndCnstLfsrSeed ), + .StatePermEn ( 1'b1 ), + .StatePerm ( RndCnstLfsrPerm ), + .MaxLenSVA ( MaxLenSVA ), + .LockupSVA ( LockupSVA ), + .ExtSeedSVA ( 1'b0 ), // ext seed is unused + .EnableAlertTriggerSVA ( 1'b0 ) + ) u_prim_double_lfsr ( + .clk_i, + .rst_ni, + .seed_en_i ( 1'b0 ), + .seed_i ( '0 ), + .lfsr_en_i ( reseed_en || cnt_set ), + .entropy_i ( entropy ), + .state_o ( lfsr_state ), + .err_o ( lfsr_err ) + ); + + logic [IdDw-1:0] id_to_ping_d, id_to_ping_q; + // The subtraction below ensures that the alert ID is always in range. If + // all alerts are enabled, an alert ID drawn in this way will always be + // valid. This comes at the cost of a bias towards certain alert IDs that + // will be pinged twice as often on average - but it ensures that we have + // less alert IDs that need to be skipped since they are invalid. + assign id_to_ping_d = (lfsr_state[PING_CNT_DW +: IdDw] >= NAlerts) ? + lfsr_state[PING_CNT_DW +: IdDw] - NAlerts : + lfsr_state[PING_CNT_DW +: IdDw]; + + // we need to hold the ID stable while the ping is ongoing since this will result in + // spurious ping responses otherwise. + always_ff @(posedge clk_i or negedge rst_ni) begin : p_id_reg + if (!rst_ni) begin + id_to_ping_q <= '0; + end else begin + if (cnt_set) begin + id_to_ping_q <= id_to_ping_d; + end + end + end + + // align the enable mask with powers of two for the indexing operation below. + logic [2**IdDw-1:0] enable_mask; + assign enable_mask = (2**IdDw)'(alert_ping_en_i); + + // check if the randomly drawn alert ID is actually valid and the alert is enabled + logic id_vld; + assign id_vld = enable_mask[id_to_ping_q]; + + ////////////////////////////////// + // Escalation Counter Instances // + ////////////////////////////////// + + // As opposed to the alert ID, the escalation sender ID to be pinged is not drawn at random. + // Rather, we cycle through the escalation senders one by one in a deterministic fashion. + // This allows us to provide guarantees needed for the ping timeout / auto escalation feature + // implemented at the escalation receiver side. + // + // In particular, with N_ESC_SEV escalation senders in the design, we can guarantee + // that each escalation channel will be pinged at least once every + // + // N_ESC_SEV x (NUM_WAIT_COUNT + NUM_TIMEOUT_COUNT) x 2**PING_CNT_DW + // + // cycles - independently of the reseeding operation. + // + // - N_ESC_SEV: # escalation channels to ping. + // - NUM_WAIT_COUNT: # wait counts between subsequent escalation channel pings. + // - NUM_TIMEOUT_COUNT: # timeout counts between subsequent escalation channel pings. + // - 2**PING_CNT_DW: # maximum counter value. + // + // This guarantee is used inside the escalation receivers to monitor the pings sent out by the + // alert handler. I.e., once the alert handler has started to send out pings, each escalation + // receiver employs a timeout window within which it expects the next ping to arrive. If + // escalation pings cease to arrive at an escalation receiver for any reason, this will + // automatically trigger the associated escalation countermeasure. + // + // In order to have enough margin, the escalation receiver timeout counters use a threshold that + // is 4x higher than the value calculated above. With N_ESC_SEV = 4, PING_CNT_DW = 16 and + // NUM_WAIT_COUNT = NUM_TIMEOUT_COUNT = 2 this amounts to a 22bit timeout threshold. + // + // We employ two redundant counters to guard against FI attacks. + // If any of the two is glitched and the two counter states do not agree, + // the FSM below is moved into a terminal error state and all ping alerts + // are permanently asserted. + + logic esc_cnt_en, esc_cnt_clr, esc_cnt_error; + logic [EscSenderIdxWidth-1:0] esc_cnt; + assign esc_cnt_clr = (esc_cnt >= EscSenderIdxWidth'(N_ESC_SEV-1)) && esc_cnt_en; + + // SEC_CM: PING_TIMER.CTR.REDUN + prim_count #( + .Width(EscSenderIdxWidth), + // The alert handler behaves differently than other comportable IP. I.e., instead of sending out + // an alert signal, this condition is handled internally in the alert handler. + .EnableAlertTriggerSVA(0), + // Pass a parameter to disable coverage for some assertions that are unreachable because set_i + // and decr_en_i are tied to zero. + .PossibleActions(prim_count_pkg::Clr | + prim_count_pkg::Incr) + ) u_prim_count_esc_cnt ( + .clk_i, + .rst_ni, + .clr_i(esc_cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(esc_cnt_en), + .decr_en_i(1'b0), + .step_i(EscSenderIdxWidth'(1)), + .commit_i(1'b1), + .cnt_o(esc_cnt), + .cnt_after_commit_o(), + .err_o(esc_cnt_error) + ); + + ///////////////////////////// + // Timer Counter Instances // + ///////////////////////////// + + // We employ two redundant counters to guard against FI attacks. + // If any of the two is glitched and the two counter states do not agree, + // the FSM below is moved into a terminal error state and all ping alerts + // are permanently asserted. + logic [PING_CNT_DW-1:0] cnt, cnt_setval; + logic wait_cnt_set, timeout_cnt_set, timer_expired, cnt_error; + assign timer_expired = (cnt == '0); + assign cnt_set = wait_cnt_set || timeout_cnt_set; + + // SEC_CM: PING_TIMER.CTR.REDUN + prim_count #( + .Width(PING_CNT_DW), + // The alert handler behaves differently than other comportable IP. I.e., instead of sending out + // an alert signal, this condition is handled internally in the alert handler. + .EnableAlertTriggerSVA(0), + // Pass a parameter to disable coverage for some assertions that are unreachable because clr_i + // and incr_en_i are tied to zero. + .PossibleActions(prim_count_pkg::Set | + prim_count_pkg::Decr) + ) u_prim_count_cnt ( + .clk_i, + .rst_ni, + .clr_i(1'b0), + .set_i(cnt_set), + .set_cnt_i(cnt_setval), + .incr_en_i(1'b0), + .decr_en_i(1'b1), // we are counting down here. + .step_i(PING_CNT_DW'(1'b1)), + .commit_i(1'b1), + .cnt_o(cnt), + .cnt_after_commit_o(), + .err_o(cnt_error) + ); + + // the constant offset ensures a minimum cycle spacing between pings. + logic unused_bits; + logic [PING_CNT_DW-1:0] wait_cyc; + assign wait_cyc = (lfsr_state[PING_CNT_DW-1:0] | PING_CNT_DW'(3'b100)); + assign unused_bits = lfsr_state[2]; + + // note that the masks are used for DV/FPV only in order to reduce the state space. + assign cnt_setval = (wait_cnt_set) ? (wait_cyc & wait_cyc_mask_i) : ping_timeout_cyc_i; + + //////////////////////////// + // Ping and Timeout Logic // + //////////////////////////// + + logic alert_ping_en, esc_ping_en; + logic spurious_alert_ping, spurious_esc_ping; + + // generate ping enable vector + assign alert_ping_req_o = NAlerts'(alert_ping_en) << id_to_ping_q; + assign esc_ping_req_o = EscSenderIdxWidth'(esc_ping_en) << esc_cnt; + + // under normal operation, these signals should never be asserted. + // we place hand instantiated buffers here such that these signals are not + // optimized away during synthesis (these buffers will receive a keep or size_only + // attribute in our Vivado and DC synthesis flows). + prim_buf u_prim_buf_spurious_alert_ping ( + .in_i(|(alert_ping_ok_i & ~alert_ping_req_o)), + .out_o(spurious_alert_ping) + ); + prim_buf u_prim_buf_spurious_esc_ping ( + .in_i(|(esc_ping_ok_i & ~esc_ping_req_o)), + .out_o(spurious_esc_ping) + ); + + // SEC_CM: PING_TIMER.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 6 -n 9 \ + // -s 728582219 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (60.00%) + // 6: ||||||||||||| (40.00%) + // 7: -- + // 8: -- + // 9: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 6 + // + localparam int StateWidth = 9; + typedef enum logic [StateWidth-1:0] { + InitSt = 9'b011001011, + AlertWaitSt = 9'b110000000, + AlertPingSt = 9'b101110001, + EscWaitSt = 9'b010110110, + EscPingSt = 9'b000011101, + FsmErrorSt = 9'b101101110 + } state_e; + + state_e state_d, state_q; + + always_comb begin : p_fsm + // default + state_d = state_q; + wait_cnt_set = 1'b0; + timeout_cnt_set = 1'b0; + esc_cnt_en = 1'b0; + alert_ping_en = 1'b0; + esc_ping_en = 1'b0; + // this captures spurious ping responses + alert_ping_fail_o = spurious_alert_ping; + esc_ping_fail_o = spurious_esc_ping; + + unique case (state_q) + // wait until activated + // we never return to this state + // once activated! + InitSt: begin + if (en_i) begin + state_d = AlertWaitSt; + wait_cnt_set = 1'b1; + end + end + // wait for random amount of cycles + AlertWaitSt: begin + if (timer_expired) begin + state_d = AlertPingSt; + timeout_cnt_set = 1'b1; + end + end + // SEC_CM: ALERT_RX.INTERSIG.BKGN_CHK + // send out an alert ping request and wait for a ping + // response or a ping timeout (whatever comes first). + // if the alert ID is not valid, we drop the request and + // proceed to the next ping. + AlertPingSt: begin + alert_ping_en = id_vld; + if (timer_expired || |(alert_ping_ok_i & alert_ping_req_o) || !id_vld) begin + state_d = EscWaitSt; + wait_cnt_set = 1'b1; + if (timer_expired) begin + alert_ping_fail_o = 1'b1; + end + end + end + // wait for random amount of cycles + EscWaitSt: begin + if (timer_expired) begin + state_d = EscPingSt; + timeout_cnt_set = 1'b1; + end + end + // SEC_CM: ESC_TX.INTERSIG.BKGN_CHK + // send out an escalation ping request and wait for a ping + // response or a ping timeout (whatever comes first) + EscPingSt: begin + esc_ping_en = 1'b1; + if (timer_expired || |(esc_ping_ok_i & esc_ping_req_o)) begin + state_d = AlertWaitSt; + wait_cnt_set = 1'b1; + esc_cnt_en = 1'b1; + if (timer_expired) begin + esc_ping_fail_o = 1'b1; + end + end + end + // SEC_CM: PING_TIMER.FSM.LOCAL_ESC + // terminal FSM error state. + // if we for some reason end up in this state (e.g. malicious glitching) + // we are going to assert both ping fails continuously + FsmErrorSt: begin + alert_ping_fail_o = 1'b1; + esc_ping_fail_o = 1'b1; + end + default: begin + state_d = FsmErrorSt; + alert_ping_fail_o = 1'b1; + esc_ping_fail_o = 1'b1; + end + endcase + + // SEC_CM: PING_TIMER.FSM.LOCAL_ESC + // if the two LFSR or counter states do not agree, + // we move into the terminal state. + if (lfsr_err || cnt_error || esc_cnt_error) begin + state_d = FsmErrorSt; + alert_ping_fail_o = 1'b1; + esc_ping_fail_o = 1'b1; + end + end + + /////////////////// + // FSM Registers // + /////////////////// + + // The alert handler behaves differently than other comportable IP. I.e., instead of sending out + // an alert signal, this condition is handled internally in the alert handler. The + // EnableAlertTriggerSVA parameter is therefore set to 0. + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, InitSt, clk_i, rst_ni, 0) + + //////////////// + // Assertions // + //////////////// + + // make sure the ID width is within bounds. + `ASSERT_INIT(MaxIdDw_A, IdDw <= (LfsrWidth - PING_CNT_DW)) + + // only one module is pinged at a time. + `ASSERT(PingOH0_A, $onehot0({alert_ping_req_o, esc_ping_req_o})) + + // we should never get into the ping state without knowing which module to ping. + `ASSERT(AlertPingOH_A, alert_ping_en |-> $onehot(alert_ping_req_o)) + `ASSERT(EscPingOH_A, esc_ping_en |-> $onehot(esc_ping_req_o)) + +endmodule : alert_handler_ping_timer diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv new file mode 100644 index 0000000000000..c8c0fcf23ec49 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv @@ -0,0 +1,2257 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package alert_handler_reg_pkg; + + // Param list + parameter int NAlerts = 99; + parameter int NLpg = 19; + parameter int NLpgWidth = 5; + parameter logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = { + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd14, + 5'd14, + 5'd14, + 5'd14, + 5'd14, + 5'd14, + 5'd14, + 5'd14, + 5'd18, + 5'd18, + 5'd17, + 5'd17, + 5'd16, + 5'd15, + 5'd15, + 5'd14, + 5'd13, + 5'd12, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd10, + 5'd10, + 5'd8, + 5'd7, + 5'd7, + 5'd7, + 5'd7, + 5'd7, + 5'd6, + 5'd5, + 5'd4, + 5'd4, + 5'd4, + 5'd4, + 5'd4, + 5'd4, + 5'd4, + 5'd4, + 5'd3, + 5'd2, + 5'd1, + 5'd0, + 5'd0 +}; + parameter int EscCntDw = 32; + parameter int AccuCntDw = 16; + parameter logic [NAlerts-1:0] AsyncOn = { + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1 +}; + parameter int N_CLASSES = 4; + parameter int N_ESC_SEV = 4; + parameter int N_PHASES = 4; + parameter int N_LOC_ALERT = 7; + parameter int PING_CNT_DW = 16; + parameter int PHASE_DW = 2; + parameter int CLASS_DW = 2; + parameter int LOCAL_ALERT_ID_ALERT_PINGFAIL = 0; + parameter int LOCAL_ALERT_ID_ESC_PINGFAIL = 1; + parameter int LOCAL_ALERT_ID_ALERT_INTEGFAIL = 2; + parameter int LOCAL_ALERT_ID_ESC_INTEGFAIL = 3; + parameter int LOCAL_ALERT_ID_BUS_INTEGFAIL = 4; + parameter int LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR = 5; + parameter int LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR = 6; + parameter int LOCAL_ALERT_ID_LAST = 6; + + // Address widths within the block + parameter int BlockAw = 11; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic q; + } classd; + struct packed { + logic q; + } classc; + struct packed { + logic q; + } classb; + struct packed { + logic q; + } classa; + } alert_handler_reg2hw_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic q; + } classd; + struct packed { + logic q; + } classc; + struct packed { + logic q; + } classb; + struct packed { + logic q; + } classa; + } alert_handler_reg2hw_intr_enable_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } classd; + struct packed { + logic q; + logic qe; + } classc; + struct packed { + logic q; + logic qe; + } classb; + struct packed { + logic q; + logic qe; + } classa; + } alert_handler_reg2hw_intr_test_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_ping_timer_en_shadowed_reg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_alert_regwen_mreg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_alert_en_shadowed_mreg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_alert_class_shadowed_mreg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_alert_cause_mreg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_loc_alert_cause_mreg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } map_e3; + struct packed { + logic [1:0] q; + } map_e2; + struct packed { + logic [1:0] q; + } map_e1; + struct packed { + logic [1:0] q; + } map_e0; + struct packed { + logic q; + } en_e3; + struct packed { + logic q; + } en_e2; + struct packed { + logic q; + } en_e1; + struct packed { + logic q; + } en_e0; + struct packed { + logic q; + } lock; + struct packed { + logic q; + } en; + } alert_handler_reg2hw_classa_ctrl_shadowed_reg_t; + + typedef struct packed { + logic q; + logic qe; + } alert_handler_reg2hw_classa_clr_shadowed_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_classa_accum_thresh_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_classa_crashdump_trigger_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_phase0_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_phase1_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_phase2_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_phase3_cyc_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } map_e3; + struct packed { + logic [1:0] q; + } map_e2; + struct packed { + logic [1:0] q; + } map_e1; + struct packed { + logic [1:0] q; + } map_e0; + struct packed { + logic q; + } en_e3; + struct packed { + logic q; + } en_e2; + struct packed { + logic q; + } en_e1; + struct packed { + logic q; + } en_e0; + struct packed { + logic q; + } lock; + struct packed { + logic q; + } en; + } alert_handler_reg2hw_classb_ctrl_shadowed_reg_t; + + typedef struct packed { + logic q; + logic qe; + } alert_handler_reg2hw_classb_clr_shadowed_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_classb_accum_thresh_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_classb_crashdump_trigger_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_phase0_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_phase1_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_phase2_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_phase3_cyc_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } map_e3; + struct packed { + logic [1:0] q; + } map_e2; + struct packed { + logic [1:0] q; + } map_e1; + struct packed { + logic [1:0] q; + } map_e0; + struct packed { + logic q; + } en_e3; + struct packed { + logic q; + } en_e2; + struct packed { + logic q; + } en_e1; + struct packed { + logic q; + } en_e0; + struct packed { + logic q; + } lock; + struct packed { + logic q; + } en; + } alert_handler_reg2hw_classc_ctrl_shadowed_reg_t; + + typedef struct packed { + logic q; + logic qe; + } alert_handler_reg2hw_classc_clr_shadowed_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_classc_accum_thresh_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_classc_crashdump_trigger_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_phase0_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_phase1_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_phase2_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_phase3_cyc_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } map_e3; + struct packed { + logic [1:0] q; + } map_e2; + struct packed { + logic [1:0] q; + } map_e1; + struct packed { + logic [1:0] q; + } map_e0; + struct packed { + logic q; + } en_e3; + struct packed { + logic q; + } en_e2; + struct packed { + logic q; + } en_e1; + struct packed { + logic q; + } en_e0; + struct packed { + logic q; + } lock; + struct packed { + logic q; + } en; + } alert_handler_reg2hw_classd_ctrl_shadowed_reg_t; + + typedef struct packed { + logic q; + logic qe; + } alert_handler_reg2hw_classd_clr_shadowed_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_classd_accum_thresh_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_classd_crashdump_trigger_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_phase0_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_phase1_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_phase2_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_phase3_cyc_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } classa; + struct packed { + logic d; + logic de; + } classb; + struct packed { + logic d; + logic de; + } classc; + struct packed { + logic d; + logic de; + } classd; + } alert_handler_hw2reg_intr_state_reg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_alert_cause_mreg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_loc_alert_cause_mreg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_classa_clr_regwen_reg_t; + + typedef struct packed { + logic [15:0] d; + } alert_handler_hw2reg_classa_accum_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } alert_handler_hw2reg_classa_esc_cnt_reg_t; + + typedef struct packed { + logic [2:0] d; + } alert_handler_hw2reg_classa_state_reg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_classb_clr_regwen_reg_t; + + typedef struct packed { + logic [15:0] d; + } alert_handler_hw2reg_classb_accum_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } alert_handler_hw2reg_classb_esc_cnt_reg_t; + + typedef struct packed { + logic [2:0] d; + } alert_handler_hw2reg_classb_state_reg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_classc_clr_regwen_reg_t; + + typedef struct packed { + logic [15:0] d; + } alert_handler_hw2reg_classc_accum_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } alert_handler_hw2reg_classc_esc_cnt_reg_t; + + typedef struct packed { + logic [2:0] d; + } alert_handler_hw2reg_classc_state_reg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_classd_clr_regwen_reg_t; + + typedef struct packed { + logic [15:0] d; + } alert_handler_hw2reg_classd_accum_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } alert_handler_hw2reg_classd_esc_cnt_reg_t; + + typedef struct packed { + logic [2:0] d; + } alert_handler_hw2reg_classd_state_reg_t; + + // Register -> HW type + typedef struct packed { + alert_handler_reg2hw_intr_state_reg_t intr_state; // [1331:1328] + alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1327:1324] + alert_handler_reg2hw_intr_test_reg_t intr_test; // [1323:1316] + alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1315:1300] + alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1299:1299] + alert_handler_reg2hw_alert_regwen_mreg_t [98:0] alert_regwen; // [1298:1200] + alert_handler_reg2hw_alert_en_shadowed_mreg_t [98:0] alert_en_shadowed; // [1199:1101] + alert_handler_reg2hw_alert_class_shadowed_mreg_t [98:0] alert_class_shadowed; // [1100:903] + alert_handler_reg2hw_alert_cause_mreg_t [98:0] alert_cause; // [902:804] + alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t [6:0] loc_alert_en_shadowed; // [803:797] + alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t [6:0] + loc_alert_class_shadowed; // [796:783] + alert_handler_reg2hw_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [782:776] + alert_handler_reg2hw_classa_ctrl_shadowed_reg_t classa_ctrl_shadowed; // [775:762] + alert_handler_reg2hw_classa_clr_shadowed_reg_t classa_clr_shadowed; // [761:760] + alert_handler_reg2hw_classa_accum_thresh_shadowed_reg_t + classa_accum_thresh_shadowed; // [759:744] + alert_handler_reg2hw_classa_timeout_cyc_shadowed_reg_t classa_timeout_cyc_shadowed; // [743:712] + alert_handler_reg2hw_classa_crashdump_trigger_shadowed_reg_t + classa_crashdump_trigger_shadowed; // [711:710] + alert_handler_reg2hw_classa_phase0_cyc_shadowed_reg_t classa_phase0_cyc_shadowed; // [709:678] + alert_handler_reg2hw_classa_phase1_cyc_shadowed_reg_t classa_phase1_cyc_shadowed; // [677:646] + alert_handler_reg2hw_classa_phase2_cyc_shadowed_reg_t classa_phase2_cyc_shadowed; // [645:614] + alert_handler_reg2hw_classa_phase3_cyc_shadowed_reg_t classa_phase3_cyc_shadowed; // [613:582] + alert_handler_reg2hw_classb_ctrl_shadowed_reg_t classb_ctrl_shadowed; // [581:568] + alert_handler_reg2hw_classb_clr_shadowed_reg_t classb_clr_shadowed; // [567:566] + alert_handler_reg2hw_classb_accum_thresh_shadowed_reg_t + classb_accum_thresh_shadowed; // [565:550] + alert_handler_reg2hw_classb_timeout_cyc_shadowed_reg_t classb_timeout_cyc_shadowed; // [549:518] + alert_handler_reg2hw_classb_crashdump_trigger_shadowed_reg_t + classb_crashdump_trigger_shadowed; // [517:516] + alert_handler_reg2hw_classb_phase0_cyc_shadowed_reg_t classb_phase0_cyc_shadowed; // [515:484] + alert_handler_reg2hw_classb_phase1_cyc_shadowed_reg_t classb_phase1_cyc_shadowed; // [483:452] + alert_handler_reg2hw_classb_phase2_cyc_shadowed_reg_t classb_phase2_cyc_shadowed; // [451:420] + alert_handler_reg2hw_classb_phase3_cyc_shadowed_reg_t classb_phase3_cyc_shadowed; // [419:388] + alert_handler_reg2hw_classc_ctrl_shadowed_reg_t classc_ctrl_shadowed; // [387:374] + alert_handler_reg2hw_classc_clr_shadowed_reg_t classc_clr_shadowed; // [373:372] + alert_handler_reg2hw_classc_accum_thresh_shadowed_reg_t + classc_accum_thresh_shadowed; // [371:356] + alert_handler_reg2hw_classc_timeout_cyc_shadowed_reg_t classc_timeout_cyc_shadowed; // [355:324] + alert_handler_reg2hw_classc_crashdump_trigger_shadowed_reg_t + classc_crashdump_trigger_shadowed; // [323:322] + alert_handler_reg2hw_classc_phase0_cyc_shadowed_reg_t classc_phase0_cyc_shadowed; // [321:290] + alert_handler_reg2hw_classc_phase1_cyc_shadowed_reg_t classc_phase1_cyc_shadowed; // [289:258] + alert_handler_reg2hw_classc_phase2_cyc_shadowed_reg_t classc_phase2_cyc_shadowed; // [257:226] + alert_handler_reg2hw_classc_phase3_cyc_shadowed_reg_t classc_phase3_cyc_shadowed; // [225:194] + alert_handler_reg2hw_classd_ctrl_shadowed_reg_t classd_ctrl_shadowed; // [193:180] + alert_handler_reg2hw_classd_clr_shadowed_reg_t classd_clr_shadowed; // [179:178] + alert_handler_reg2hw_classd_accum_thresh_shadowed_reg_t + classd_accum_thresh_shadowed; // [177:162] + alert_handler_reg2hw_classd_timeout_cyc_shadowed_reg_t classd_timeout_cyc_shadowed; // [161:130] + alert_handler_reg2hw_classd_crashdump_trigger_shadowed_reg_t + classd_crashdump_trigger_shadowed; // [129:128] + alert_handler_reg2hw_classd_phase0_cyc_shadowed_reg_t classd_phase0_cyc_shadowed; // [127:96] + alert_handler_reg2hw_classd_phase1_cyc_shadowed_reg_t classd_phase1_cyc_shadowed; // [95:64] + alert_handler_reg2hw_classd_phase2_cyc_shadowed_reg_t classd_phase2_cyc_shadowed; // [63:32] + alert_handler_reg2hw_classd_phase3_cyc_shadowed_reg_t classd_phase3_cyc_shadowed; // [31:0] + } alert_handler_reg2hw_t; + + // HW -> register type + typedef struct packed { + alert_handler_hw2reg_intr_state_reg_t intr_state; // [431:424] + alert_handler_hw2reg_alert_cause_mreg_t [98:0] alert_cause; // [423:226] + alert_handler_hw2reg_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [225:212] + alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210] + alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194] + alert_handler_hw2reg_classa_esc_cnt_reg_t classa_esc_cnt; // [193:162] + alert_handler_hw2reg_classa_state_reg_t classa_state; // [161:159] + alert_handler_hw2reg_classb_clr_regwen_reg_t classb_clr_regwen; // [158:157] + alert_handler_hw2reg_classb_accum_cnt_reg_t classb_accum_cnt; // [156:141] + alert_handler_hw2reg_classb_esc_cnt_reg_t classb_esc_cnt; // [140:109] + alert_handler_hw2reg_classb_state_reg_t classb_state; // [108:106] + alert_handler_hw2reg_classc_clr_regwen_reg_t classc_clr_regwen; // [105:104] + alert_handler_hw2reg_classc_accum_cnt_reg_t classc_accum_cnt; // [103:88] + alert_handler_hw2reg_classc_esc_cnt_reg_t classc_esc_cnt; // [87:56] + alert_handler_hw2reg_classc_state_reg_t classc_state; // [55:53] + alert_handler_hw2reg_classd_clr_regwen_reg_t classd_clr_regwen; // [52:51] + alert_handler_hw2reg_classd_accum_cnt_reg_t classd_accum_cnt; // [50:35] + alert_handler_hw2reg_classd_esc_cnt_reg_t classd_esc_cnt; // [34:3] + alert_handler_hw2reg_classd_state_reg_t classd_state; // [2:0] + } alert_handler_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_STATE_OFFSET = 11'h 0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_ENABLE_OFFSET = 11'h 4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_TEST_OFFSET = 11'h 8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_REGWEN_OFFSET = 11'h c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 10; + parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_EN_SHADOWED_OFFSET = 11'h 14; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_0_OFFSET = 11'h 18; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_1_OFFSET = 11'h 1c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_2_OFFSET = 11'h 20; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_3_OFFSET = 11'h 24; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_4_OFFSET = 11'h 28; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_5_OFFSET = 11'h 2c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_6_OFFSET = 11'h 30; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_7_OFFSET = 11'h 34; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_8_OFFSET = 11'h 38; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_9_OFFSET = 11'h 3c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_10_OFFSET = 11'h 40; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_11_OFFSET = 11'h 44; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_12_OFFSET = 11'h 48; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_13_OFFSET = 11'h 4c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_14_OFFSET = 11'h 50; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_15_OFFSET = 11'h 54; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_16_OFFSET = 11'h 58; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_17_OFFSET = 11'h 5c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_18_OFFSET = 11'h 60; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_19_OFFSET = 11'h 64; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_20_OFFSET = 11'h 68; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_21_OFFSET = 11'h 6c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_22_OFFSET = 11'h 70; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_23_OFFSET = 11'h 74; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_24_OFFSET = 11'h 78; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_25_OFFSET = 11'h 7c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_26_OFFSET = 11'h 80; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_27_OFFSET = 11'h 84; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_28_OFFSET = 11'h 88; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_29_OFFSET = 11'h 8c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_30_OFFSET = 11'h 90; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_31_OFFSET = 11'h 94; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_32_OFFSET = 11'h 98; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_33_OFFSET = 11'h 9c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_34_OFFSET = 11'h a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_35_OFFSET = 11'h a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_36_OFFSET = 11'h a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_37_OFFSET = 11'h ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_38_OFFSET = 11'h b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_39_OFFSET = 11'h b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_40_OFFSET = 11'h b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_41_OFFSET = 11'h bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_42_OFFSET = 11'h c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_43_OFFSET = 11'h c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_44_OFFSET = 11'h c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_45_OFFSET = 11'h cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_46_OFFSET = 11'h d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_47_OFFSET = 11'h d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_48_OFFSET = 11'h d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_49_OFFSET = 11'h dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_50_OFFSET = 11'h e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_51_OFFSET = 11'h e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_52_OFFSET = 11'h e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_53_OFFSET = 11'h ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_54_OFFSET = 11'h f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_55_OFFSET = 11'h f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_56_OFFSET = 11'h f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_57_OFFSET = 11'h fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_58_OFFSET = 11'h 100; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_59_OFFSET = 11'h 104; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_60_OFFSET = 11'h 108; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_61_OFFSET = 11'h 10c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_62_OFFSET = 11'h 110; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_63_OFFSET = 11'h 114; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_64_OFFSET = 11'h 118; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_65_OFFSET = 11'h 11c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_66_OFFSET = 11'h 120; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_67_OFFSET = 11'h 124; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_68_OFFSET = 11'h 128; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_69_OFFSET = 11'h 12c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_70_OFFSET = 11'h 130; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_71_OFFSET = 11'h 134; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_72_OFFSET = 11'h 138; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_73_OFFSET = 11'h 13c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_74_OFFSET = 11'h 140; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_75_OFFSET = 11'h 144; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_76_OFFSET = 11'h 148; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_77_OFFSET = 11'h 14c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_78_OFFSET = 11'h 150; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_79_OFFSET = 11'h 154; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_80_OFFSET = 11'h 158; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_81_OFFSET = 11'h 15c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_82_OFFSET = 11'h 160; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_83_OFFSET = 11'h 164; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_84_OFFSET = 11'h 168; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_85_OFFSET = 11'h 16c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_86_OFFSET = 11'h 170; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_87_OFFSET = 11'h 174; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_88_OFFSET = 11'h 178; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_89_OFFSET = 11'h 17c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_90_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_91_OFFSET = 11'h 184; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_92_OFFSET = 11'h 188; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_93_OFFSET = 11'h 18c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_94_OFFSET = 11'h 190; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_95_OFFSET = 11'h 194; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_96_OFFSET = 11'h 198; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_97_OFFSET = 11'h 19c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_98_OFFSET = 11'h 1a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 1a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 1a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 1ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 1b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 1b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 1b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 1bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 1c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 1c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 1c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 1cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 1d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 1d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 1d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 1dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 1e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 1e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 1e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 1ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 1f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 1f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 1f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 1fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 204; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 208; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 20c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 210; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 214; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 218; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 21c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 220; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 224; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 228; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 22c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 230; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 234; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 238; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 23c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 240; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 244; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_65_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_66_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_67_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_68_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_69_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_70_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_71_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_72_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_73_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_74_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_75_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_76_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_77_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_78_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_79_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_80_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_81_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_82_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_83_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_84_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_85_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_86_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_87_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_88_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_89_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_90_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_91_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_92_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_93_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_94_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_95_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_96_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_97_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_98_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_OFFSET = 11'h 444; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_OFFSET = 11'h 448; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_OFFSET = 11'h 44c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_OFFSET = 11'h 450; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_OFFSET = 11'h 454; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_OFFSET = 11'h 458; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_75_OFFSET = 11'h 45c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_76_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_77_OFFSET = 11'h 464; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_78_OFFSET = 11'h 468; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_79_OFFSET = 11'h 46c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_80_OFFSET = 11'h 470; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_81_OFFSET = 11'h 474; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_82_OFFSET = 11'h 478; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_83_OFFSET = 11'h 47c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_84_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_85_OFFSET = 11'h 484; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_86_OFFSET = 11'h 488; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_87_OFFSET = 11'h 48c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_88_OFFSET = 11'h 490; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_89_OFFSET = 11'h 494; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_90_OFFSET = 11'h 498; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_91_OFFSET = 11'h 49c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_92_OFFSET = 11'h 4a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_93_OFFSET = 11'h 4a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_94_OFFSET = 11'h 4a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_95_OFFSET = 11'h 4ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_96_OFFSET = 11'h 4b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_97_OFFSET = 11'h 4b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_98_OFFSET = 11'h 4b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 4bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 4c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 4c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 4c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 4cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 4d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 4d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 4d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 4dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 4e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 4e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 4e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 4ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 4f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 4f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 4f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 4fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 504; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 508; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 50c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 510; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 514; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 518; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 51c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 520; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 524; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 528; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 52c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 530; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 534; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 538; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 53c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 540; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 544; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 548; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 54c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 550; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 558; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 55c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 560; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 564; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 568; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 56c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 570; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 574; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 578; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 57c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 580; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 584; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 588; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 58c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 590; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 594; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 598; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 59c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 5a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 5a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 5a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 5ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 5b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 5b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 5b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 5bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_65_OFFSET = 11'h 5c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_66_OFFSET = 11'h 5c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_67_OFFSET = 11'h 5c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_68_OFFSET = 11'h 5cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_69_OFFSET = 11'h 5d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_70_OFFSET = 11'h 5d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_71_OFFSET = 11'h 5d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_72_OFFSET = 11'h 5dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_73_OFFSET = 11'h 5e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_74_OFFSET = 11'h 5e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_75_OFFSET = 11'h 5e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_76_OFFSET = 11'h 5ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_77_OFFSET = 11'h 5f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_78_OFFSET = 11'h 5f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_79_OFFSET = 11'h 5f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_80_OFFSET = 11'h 5fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_81_OFFSET = 11'h 600; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_82_OFFSET = 11'h 604; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_83_OFFSET = 11'h 608; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_84_OFFSET = 11'h 60c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_85_OFFSET = 11'h 610; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_86_OFFSET = 11'h 614; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_87_OFFSET = 11'h 618; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_88_OFFSET = 11'h 61c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_89_OFFSET = 11'h 620; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_90_OFFSET = 11'h 624; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_91_OFFSET = 11'h 628; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_92_OFFSET = 11'h 62c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_93_OFFSET = 11'h 630; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_94_OFFSET = 11'h 634; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_95_OFFSET = 11'h 638; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_96_OFFSET = 11'h 63c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_97_OFFSET = 11'h 640; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_98_OFFSET = 11'h 644; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 648; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 64c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 650; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 654; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 658; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 65c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 660; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 664; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 668; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 66c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 670; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 674; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 678; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 67c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 680; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 684; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 688; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 68c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 690; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 694; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 698; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 69c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 6a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 6a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 6a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 6ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 6b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 6b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 6b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 6bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 6c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 6c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 6c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 6cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 6d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 6d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 6d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 6dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 6e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 6e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 6e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 6ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 6f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 6f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 6f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 6fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 700; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 704; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 708; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 70c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 710; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 714; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 718; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 71c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 720; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 724; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 728; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 72c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 730; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 734; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 738; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 73c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 740; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 744; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 748; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 74c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 750; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 754; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 758; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 75c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 760; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 764; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 768; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 76c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 770; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 774; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 778; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 77c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 780; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 784; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 788; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 78c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 790; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 794; + + // Reset values for hwext registers and their fields + parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0; + parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSA_RESVAL = 1'h 0; + parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSB_RESVAL = 1'h 0; + parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSC_RESVAL = 1'h 0; + parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSD_RESVAL = 1'h 0; + parameter logic [15:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_RESVAL = 16'h 0; + parameter logic [31:0] ALERT_HANDLER_CLASSA_ESC_CNT_RESVAL = 32'h 0; + parameter logic [2:0] ALERT_HANDLER_CLASSA_STATE_RESVAL = 3'h 0; + parameter logic [15:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_RESVAL = 16'h 0; + parameter logic [31:0] ALERT_HANDLER_CLASSB_ESC_CNT_RESVAL = 32'h 0; + parameter logic [2:0] ALERT_HANDLER_CLASSB_STATE_RESVAL = 3'h 0; + parameter logic [15:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_RESVAL = 16'h 0; + parameter logic [31:0] ALERT_HANDLER_CLASSC_ESC_CNT_RESVAL = 32'h 0; + parameter logic [2:0] ALERT_HANDLER_CLASSC_STATE_RESVAL = 3'h 0; + parameter logic [15:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_RESVAL = 16'h 0; + parameter logic [31:0] ALERT_HANDLER_CLASSD_ESC_CNT_RESVAL = 32'h 0; + parameter logic [2:0] ALERT_HANDLER_CLASSD_STATE_RESVAL = 3'h 0; + + // Register index + typedef enum int { + ALERT_HANDLER_INTR_STATE, + ALERT_HANDLER_INTR_ENABLE, + ALERT_HANDLER_INTR_TEST, + ALERT_HANDLER_PING_TIMER_REGWEN, + ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_PING_TIMER_EN_SHADOWED, + ALERT_HANDLER_ALERT_REGWEN_0, + ALERT_HANDLER_ALERT_REGWEN_1, + ALERT_HANDLER_ALERT_REGWEN_2, + ALERT_HANDLER_ALERT_REGWEN_3, + ALERT_HANDLER_ALERT_REGWEN_4, + ALERT_HANDLER_ALERT_REGWEN_5, + ALERT_HANDLER_ALERT_REGWEN_6, + ALERT_HANDLER_ALERT_REGWEN_7, + ALERT_HANDLER_ALERT_REGWEN_8, + ALERT_HANDLER_ALERT_REGWEN_9, + ALERT_HANDLER_ALERT_REGWEN_10, + ALERT_HANDLER_ALERT_REGWEN_11, + ALERT_HANDLER_ALERT_REGWEN_12, + ALERT_HANDLER_ALERT_REGWEN_13, + ALERT_HANDLER_ALERT_REGWEN_14, + ALERT_HANDLER_ALERT_REGWEN_15, + ALERT_HANDLER_ALERT_REGWEN_16, + ALERT_HANDLER_ALERT_REGWEN_17, + ALERT_HANDLER_ALERT_REGWEN_18, + ALERT_HANDLER_ALERT_REGWEN_19, + ALERT_HANDLER_ALERT_REGWEN_20, + ALERT_HANDLER_ALERT_REGWEN_21, + ALERT_HANDLER_ALERT_REGWEN_22, + ALERT_HANDLER_ALERT_REGWEN_23, + ALERT_HANDLER_ALERT_REGWEN_24, + ALERT_HANDLER_ALERT_REGWEN_25, + ALERT_HANDLER_ALERT_REGWEN_26, + ALERT_HANDLER_ALERT_REGWEN_27, + ALERT_HANDLER_ALERT_REGWEN_28, + ALERT_HANDLER_ALERT_REGWEN_29, + ALERT_HANDLER_ALERT_REGWEN_30, + ALERT_HANDLER_ALERT_REGWEN_31, + ALERT_HANDLER_ALERT_REGWEN_32, + ALERT_HANDLER_ALERT_REGWEN_33, + ALERT_HANDLER_ALERT_REGWEN_34, + ALERT_HANDLER_ALERT_REGWEN_35, + ALERT_HANDLER_ALERT_REGWEN_36, + ALERT_HANDLER_ALERT_REGWEN_37, + ALERT_HANDLER_ALERT_REGWEN_38, + ALERT_HANDLER_ALERT_REGWEN_39, + ALERT_HANDLER_ALERT_REGWEN_40, + ALERT_HANDLER_ALERT_REGWEN_41, + ALERT_HANDLER_ALERT_REGWEN_42, + ALERT_HANDLER_ALERT_REGWEN_43, + ALERT_HANDLER_ALERT_REGWEN_44, + ALERT_HANDLER_ALERT_REGWEN_45, + ALERT_HANDLER_ALERT_REGWEN_46, + ALERT_HANDLER_ALERT_REGWEN_47, + ALERT_HANDLER_ALERT_REGWEN_48, + ALERT_HANDLER_ALERT_REGWEN_49, + ALERT_HANDLER_ALERT_REGWEN_50, + ALERT_HANDLER_ALERT_REGWEN_51, + ALERT_HANDLER_ALERT_REGWEN_52, + ALERT_HANDLER_ALERT_REGWEN_53, + ALERT_HANDLER_ALERT_REGWEN_54, + ALERT_HANDLER_ALERT_REGWEN_55, + ALERT_HANDLER_ALERT_REGWEN_56, + ALERT_HANDLER_ALERT_REGWEN_57, + ALERT_HANDLER_ALERT_REGWEN_58, + ALERT_HANDLER_ALERT_REGWEN_59, + ALERT_HANDLER_ALERT_REGWEN_60, + ALERT_HANDLER_ALERT_REGWEN_61, + ALERT_HANDLER_ALERT_REGWEN_62, + ALERT_HANDLER_ALERT_REGWEN_63, + ALERT_HANDLER_ALERT_REGWEN_64, + ALERT_HANDLER_ALERT_REGWEN_65, + ALERT_HANDLER_ALERT_REGWEN_66, + ALERT_HANDLER_ALERT_REGWEN_67, + ALERT_HANDLER_ALERT_REGWEN_68, + ALERT_HANDLER_ALERT_REGWEN_69, + ALERT_HANDLER_ALERT_REGWEN_70, + ALERT_HANDLER_ALERT_REGWEN_71, + ALERT_HANDLER_ALERT_REGWEN_72, + ALERT_HANDLER_ALERT_REGWEN_73, + ALERT_HANDLER_ALERT_REGWEN_74, + ALERT_HANDLER_ALERT_REGWEN_75, + ALERT_HANDLER_ALERT_REGWEN_76, + ALERT_HANDLER_ALERT_REGWEN_77, + ALERT_HANDLER_ALERT_REGWEN_78, + ALERT_HANDLER_ALERT_REGWEN_79, + ALERT_HANDLER_ALERT_REGWEN_80, + ALERT_HANDLER_ALERT_REGWEN_81, + ALERT_HANDLER_ALERT_REGWEN_82, + ALERT_HANDLER_ALERT_REGWEN_83, + ALERT_HANDLER_ALERT_REGWEN_84, + ALERT_HANDLER_ALERT_REGWEN_85, + ALERT_HANDLER_ALERT_REGWEN_86, + ALERT_HANDLER_ALERT_REGWEN_87, + ALERT_HANDLER_ALERT_REGWEN_88, + ALERT_HANDLER_ALERT_REGWEN_89, + ALERT_HANDLER_ALERT_REGWEN_90, + ALERT_HANDLER_ALERT_REGWEN_91, + ALERT_HANDLER_ALERT_REGWEN_92, + ALERT_HANDLER_ALERT_REGWEN_93, + ALERT_HANDLER_ALERT_REGWEN_94, + ALERT_HANDLER_ALERT_REGWEN_95, + ALERT_HANDLER_ALERT_REGWEN_96, + ALERT_HANDLER_ALERT_REGWEN_97, + ALERT_HANDLER_ALERT_REGWEN_98, + ALERT_HANDLER_ALERT_EN_SHADOWED_0, + ALERT_HANDLER_ALERT_EN_SHADOWED_1, + ALERT_HANDLER_ALERT_EN_SHADOWED_2, + ALERT_HANDLER_ALERT_EN_SHADOWED_3, + ALERT_HANDLER_ALERT_EN_SHADOWED_4, + ALERT_HANDLER_ALERT_EN_SHADOWED_5, + ALERT_HANDLER_ALERT_EN_SHADOWED_6, + ALERT_HANDLER_ALERT_EN_SHADOWED_7, + ALERT_HANDLER_ALERT_EN_SHADOWED_8, + ALERT_HANDLER_ALERT_EN_SHADOWED_9, + ALERT_HANDLER_ALERT_EN_SHADOWED_10, + ALERT_HANDLER_ALERT_EN_SHADOWED_11, + ALERT_HANDLER_ALERT_EN_SHADOWED_12, + ALERT_HANDLER_ALERT_EN_SHADOWED_13, + ALERT_HANDLER_ALERT_EN_SHADOWED_14, + ALERT_HANDLER_ALERT_EN_SHADOWED_15, + ALERT_HANDLER_ALERT_EN_SHADOWED_16, + ALERT_HANDLER_ALERT_EN_SHADOWED_17, + ALERT_HANDLER_ALERT_EN_SHADOWED_18, + ALERT_HANDLER_ALERT_EN_SHADOWED_19, + ALERT_HANDLER_ALERT_EN_SHADOWED_20, + ALERT_HANDLER_ALERT_EN_SHADOWED_21, + ALERT_HANDLER_ALERT_EN_SHADOWED_22, + ALERT_HANDLER_ALERT_EN_SHADOWED_23, + ALERT_HANDLER_ALERT_EN_SHADOWED_24, + ALERT_HANDLER_ALERT_EN_SHADOWED_25, + ALERT_HANDLER_ALERT_EN_SHADOWED_26, + ALERT_HANDLER_ALERT_EN_SHADOWED_27, + ALERT_HANDLER_ALERT_EN_SHADOWED_28, + ALERT_HANDLER_ALERT_EN_SHADOWED_29, + ALERT_HANDLER_ALERT_EN_SHADOWED_30, + ALERT_HANDLER_ALERT_EN_SHADOWED_31, + ALERT_HANDLER_ALERT_EN_SHADOWED_32, + ALERT_HANDLER_ALERT_EN_SHADOWED_33, + ALERT_HANDLER_ALERT_EN_SHADOWED_34, + ALERT_HANDLER_ALERT_EN_SHADOWED_35, + ALERT_HANDLER_ALERT_EN_SHADOWED_36, + ALERT_HANDLER_ALERT_EN_SHADOWED_37, + ALERT_HANDLER_ALERT_EN_SHADOWED_38, + ALERT_HANDLER_ALERT_EN_SHADOWED_39, + ALERT_HANDLER_ALERT_EN_SHADOWED_40, + ALERT_HANDLER_ALERT_EN_SHADOWED_41, + ALERT_HANDLER_ALERT_EN_SHADOWED_42, + ALERT_HANDLER_ALERT_EN_SHADOWED_43, + ALERT_HANDLER_ALERT_EN_SHADOWED_44, + ALERT_HANDLER_ALERT_EN_SHADOWED_45, + ALERT_HANDLER_ALERT_EN_SHADOWED_46, + ALERT_HANDLER_ALERT_EN_SHADOWED_47, + ALERT_HANDLER_ALERT_EN_SHADOWED_48, + ALERT_HANDLER_ALERT_EN_SHADOWED_49, + ALERT_HANDLER_ALERT_EN_SHADOWED_50, + ALERT_HANDLER_ALERT_EN_SHADOWED_51, + ALERT_HANDLER_ALERT_EN_SHADOWED_52, + ALERT_HANDLER_ALERT_EN_SHADOWED_53, + ALERT_HANDLER_ALERT_EN_SHADOWED_54, + ALERT_HANDLER_ALERT_EN_SHADOWED_55, + ALERT_HANDLER_ALERT_EN_SHADOWED_56, + ALERT_HANDLER_ALERT_EN_SHADOWED_57, + ALERT_HANDLER_ALERT_EN_SHADOWED_58, + ALERT_HANDLER_ALERT_EN_SHADOWED_59, + ALERT_HANDLER_ALERT_EN_SHADOWED_60, + ALERT_HANDLER_ALERT_EN_SHADOWED_61, + ALERT_HANDLER_ALERT_EN_SHADOWED_62, + ALERT_HANDLER_ALERT_EN_SHADOWED_63, + ALERT_HANDLER_ALERT_EN_SHADOWED_64, + ALERT_HANDLER_ALERT_EN_SHADOWED_65, + ALERT_HANDLER_ALERT_EN_SHADOWED_66, + ALERT_HANDLER_ALERT_EN_SHADOWED_67, + ALERT_HANDLER_ALERT_EN_SHADOWED_68, + ALERT_HANDLER_ALERT_EN_SHADOWED_69, + ALERT_HANDLER_ALERT_EN_SHADOWED_70, + ALERT_HANDLER_ALERT_EN_SHADOWED_71, + ALERT_HANDLER_ALERT_EN_SHADOWED_72, + ALERT_HANDLER_ALERT_EN_SHADOWED_73, + ALERT_HANDLER_ALERT_EN_SHADOWED_74, + ALERT_HANDLER_ALERT_EN_SHADOWED_75, + ALERT_HANDLER_ALERT_EN_SHADOWED_76, + ALERT_HANDLER_ALERT_EN_SHADOWED_77, + ALERT_HANDLER_ALERT_EN_SHADOWED_78, + ALERT_HANDLER_ALERT_EN_SHADOWED_79, + ALERT_HANDLER_ALERT_EN_SHADOWED_80, + ALERT_HANDLER_ALERT_EN_SHADOWED_81, + ALERT_HANDLER_ALERT_EN_SHADOWED_82, + ALERT_HANDLER_ALERT_EN_SHADOWED_83, + ALERT_HANDLER_ALERT_EN_SHADOWED_84, + ALERT_HANDLER_ALERT_EN_SHADOWED_85, + ALERT_HANDLER_ALERT_EN_SHADOWED_86, + ALERT_HANDLER_ALERT_EN_SHADOWED_87, + ALERT_HANDLER_ALERT_EN_SHADOWED_88, + ALERT_HANDLER_ALERT_EN_SHADOWED_89, + ALERT_HANDLER_ALERT_EN_SHADOWED_90, + ALERT_HANDLER_ALERT_EN_SHADOWED_91, + ALERT_HANDLER_ALERT_EN_SHADOWED_92, + ALERT_HANDLER_ALERT_EN_SHADOWED_93, + ALERT_HANDLER_ALERT_EN_SHADOWED_94, + ALERT_HANDLER_ALERT_EN_SHADOWED_95, + ALERT_HANDLER_ALERT_EN_SHADOWED_96, + ALERT_HANDLER_ALERT_EN_SHADOWED_97, + ALERT_HANDLER_ALERT_EN_SHADOWED_98, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_1, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_2, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_3, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_4, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_5, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_6, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_7, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_8, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_9, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_10, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_11, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_12, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_13, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_14, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_15, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_16, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_17, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_18, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_19, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_20, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_21, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_22, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_23, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_24, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_25, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_26, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_27, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_28, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_29, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_30, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_31, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_32, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_33, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_34, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_35, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_36, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_37, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_38, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_39, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_40, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_41, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_42, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_43, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_44, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_45, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_46, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_47, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_48, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_49, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_50, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_51, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_52, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_53, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_54, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_55, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_56, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_57, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_58, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_59, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_60, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_61, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_62, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_63, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_64, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_65, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_66, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_67, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_68, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_69, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_70, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_71, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_72, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_73, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_74, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_75, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_76, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_77, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_78, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_79, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_80, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_81, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_82, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_83, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_84, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_85, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_86, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_87, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_88, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_89, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_90, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_91, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_92, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_93, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_94, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_95, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_96, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_97, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_98, + ALERT_HANDLER_ALERT_CAUSE_0, + ALERT_HANDLER_ALERT_CAUSE_1, + ALERT_HANDLER_ALERT_CAUSE_2, + ALERT_HANDLER_ALERT_CAUSE_3, + ALERT_HANDLER_ALERT_CAUSE_4, + ALERT_HANDLER_ALERT_CAUSE_5, + ALERT_HANDLER_ALERT_CAUSE_6, + ALERT_HANDLER_ALERT_CAUSE_7, + ALERT_HANDLER_ALERT_CAUSE_8, + ALERT_HANDLER_ALERT_CAUSE_9, + ALERT_HANDLER_ALERT_CAUSE_10, + ALERT_HANDLER_ALERT_CAUSE_11, + ALERT_HANDLER_ALERT_CAUSE_12, + ALERT_HANDLER_ALERT_CAUSE_13, + ALERT_HANDLER_ALERT_CAUSE_14, + ALERT_HANDLER_ALERT_CAUSE_15, + ALERT_HANDLER_ALERT_CAUSE_16, + ALERT_HANDLER_ALERT_CAUSE_17, + ALERT_HANDLER_ALERT_CAUSE_18, + ALERT_HANDLER_ALERT_CAUSE_19, + ALERT_HANDLER_ALERT_CAUSE_20, + ALERT_HANDLER_ALERT_CAUSE_21, + ALERT_HANDLER_ALERT_CAUSE_22, + ALERT_HANDLER_ALERT_CAUSE_23, + ALERT_HANDLER_ALERT_CAUSE_24, + ALERT_HANDLER_ALERT_CAUSE_25, + ALERT_HANDLER_ALERT_CAUSE_26, + ALERT_HANDLER_ALERT_CAUSE_27, + ALERT_HANDLER_ALERT_CAUSE_28, + ALERT_HANDLER_ALERT_CAUSE_29, + ALERT_HANDLER_ALERT_CAUSE_30, + ALERT_HANDLER_ALERT_CAUSE_31, + ALERT_HANDLER_ALERT_CAUSE_32, + ALERT_HANDLER_ALERT_CAUSE_33, + ALERT_HANDLER_ALERT_CAUSE_34, + ALERT_HANDLER_ALERT_CAUSE_35, + ALERT_HANDLER_ALERT_CAUSE_36, + ALERT_HANDLER_ALERT_CAUSE_37, + ALERT_HANDLER_ALERT_CAUSE_38, + ALERT_HANDLER_ALERT_CAUSE_39, + ALERT_HANDLER_ALERT_CAUSE_40, + ALERT_HANDLER_ALERT_CAUSE_41, + ALERT_HANDLER_ALERT_CAUSE_42, + ALERT_HANDLER_ALERT_CAUSE_43, + ALERT_HANDLER_ALERT_CAUSE_44, + ALERT_HANDLER_ALERT_CAUSE_45, + ALERT_HANDLER_ALERT_CAUSE_46, + ALERT_HANDLER_ALERT_CAUSE_47, + ALERT_HANDLER_ALERT_CAUSE_48, + ALERT_HANDLER_ALERT_CAUSE_49, + ALERT_HANDLER_ALERT_CAUSE_50, + ALERT_HANDLER_ALERT_CAUSE_51, + ALERT_HANDLER_ALERT_CAUSE_52, + ALERT_HANDLER_ALERT_CAUSE_53, + ALERT_HANDLER_ALERT_CAUSE_54, + ALERT_HANDLER_ALERT_CAUSE_55, + ALERT_HANDLER_ALERT_CAUSE_56, + ALERT_HANDLER_ALERT_CAUSE_57, + ALERT_HANDLER_ALERT_CAUSE_58, + ALERT_HANDLER_ALERT_CAUSE_59, + ALERT_HANDLER_ALERT_CAUSE_60, + ALERT_HANDLER_ALERT_CAUSE_61, + ALERT_HANDLER_ALERT_CAUSE_62, + ALERT_HANDLER_ALERT_CAUSE_63, + ALERT_HANDLER_ALERT_CAUSE_64, + ALERT_HANDLER_ALERT_CAUSE_65, + ALERT_HANDLER_ALERT_CAUSE_66, + ALERT_HANDLER_ALERT_CAUSE_67, + ALERT_HANDLER_ALERT_CAUSE_68, + ALERT_HANDLER_ALERT_CAUSE_69, + ALERT_HANDLER_ALERT_CAUSE_70, + ALERT_HANDLER_ALERT_CAUSE_71, + ALERT_HANDLER_ALERT_CAUSE_72, + ALERT_HANDLER_ALERT_CAUSE_73, + ALERT_HANDLER_ALERT_CAUSE_74, + ALERT_HANDLER_ALERT_CAUSE_75, + ALERT_HANDLER_ALERT_CAUSE_76, + ALERT_HANDLER_ALERT_CAUSE_77, + ALERT_HANDLER_ALERT_CAUSE_78, + ALERT_HANDLER_ALERT_CAUSE_79, + ALERT_HANDLER_ALERT_CAUSE_80, + ALERT_HANDLER_ALERT_CAUSE_81, + ALERT_HANDLER_ALERT_CAUSE_82, + ALERT_HANDLER_ALERT_CAUSE_83, + ALERT_HANDLER_ALERT_CAUSE_84, + ALERT_HANDLER_ALERT_CAUSE_85, + ALERT_HANDLER_ALERT_CAUSE_86, + ALERT_HANDLER_ALERT_CAUSE_87, + ALERT_HANDLER_ALERT_CAUSE_88, + ALERT_HANDLER_ALERT_CAUSE_89, + ALERT_HANDLER_ALERT_CAUSE_90, + ALERT_HANDLER_ALERT_CAUSE_91, + ALERT_HANDLER_ALERT_CAUSE_92, + ALERT_HANDLER_ALERT_CAUSE_93, + ALERT_HANDLER_ALERT_CAUSE_94, + ALERT_HANDLER_ALERT_CAUSE_95, + ALERT_HANDLER_ALERT_CAUSE_96, + ALERT_HANDLER_ALERT_CAUSE_97, + ALERT_HANDLER_ALERT_CAUSE_98, + ALERT_HANDLER_LOC_ALERT_REGWEN_0, + ALERT_HANDLER_LOC_ALERT_REGWEN_1, + ALERT_HANDLER_LOC_ALERT_REGWEN_2, + ALERT_HANDLER_LOC_ALERT_REGWEN_3, + ALERT_HANDLER_LOC_ALERT_REGWEN_4, + ALERT_HANDLER_LOC_ALERT_REGWEN_5, + ALERT_HANDLER_LOC_ALERT_REGWEN_6, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6, + ALERT_HANDLER_LOC_ALERT_CAUSE_0, + ALERT_HANDLER_LOC_ALERT_CAUSE_1, + ALERT_HANDLER_LOC_ALERT_CAUSE_2, + ALERT_HANDLER_LOC_ALERT_CAUSE_3, + ALERT_HANDLER_LOC_ALERT_CAUSE_4, + ALERT_HANDLER_LOC_ALERT_CAUSE_5, + ALERT_HANDLER_LOC_ALERT_CAUSE_6, + ALERT_HANDLER_CLASSA_REGWEN, + ALERT_HANDLER_CLASSA_CTRL_SHADOWED, + ALERT_HANDLER_CLASSA_CLR_REGWEN, + ALERT_HANDLER_CLASSA_CLR_SHADOWED, + ALERT_HANDLER_CLASSA_ACCUM_CNT, + ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED, + ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED, + ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_ESC_CNT, + ALERT_HANDLER_CLASSA_STATE, + ALERT_HANDLER_CLASSB_REGWEN, + ALERT_HANDLER_CLASSB_CTRL_SHADOWED, + ALERT_HANDLER_CLASSB_CLR_REGWEN, + ALERT_HANDLER_CLASSB_CLR_SHADOWED, + ALERT_HANDLER_CLASSB_ACCUM_CNT, + ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED, + ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED, + ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_ESC_CNT, + ALERT_HANDLER_CLASSB_STATE, + ALERT_HANDLER_CLASSC_REGWEN, + ALERT_HANDLER_CLASSC_CTRL_SHADOWED, + ALERT_HANDLER_CLASSC_CLR_REGWEN, + ALERT_HANDLER_CLASSC_CLR_SHADOWED, + ALERT_HANDLER_CLASSC_ACCUM_CNT, + ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED, + ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED, + ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_ESC_CNT, + ALERT_HANDLER_CLASSC_STATE, + ALERT_HANDLER_CLASSD_REGWEN, + ALERT_HANDLER_CLASSD_CTRL_SHADOWED, + ALERT_HANDLER_CLASSD_CLR_REGWEN, + ALERT_HANDLER_CLASSD_CLR_SHADOWED, + ALERT_HANDLER_CLASSD_ACCUM_CNT, + ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED, + ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED, + ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_ESC_CNT, + ALERT_HANDLER_CLASSD_STATE + } alert_handler_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] ALERT_HANDLER_PERMIT [486] = '{ + 4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE + 4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE + 4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST + 4'b 0001, // index[ 3] ALERT_HANDLER_PING_TIMER_REGWEN + 4'b 0011, // index[ 4] ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[ 5] ALERT_HANDLER_PING_TIMER_EN_SHADOWED + 4'b 0001, // index[ 6] ALERT_HANDLER_ALERT_REGWEN_0 + 4'b 0001, // index[ 7] ALERT_HANDLER_ALERT_REGWEN_1 + 4'b 0001, // index[ 8] ALERT_HANDLER_ALERT_REGWEN_2 + 4'b 0001, // index[ 9] ALERT_HANDLER_ALERT_REGWEN_3 + 4'b 0001, // index[ 10] ALERT_HANDLER_ALERT_REGWEN_4 + 4'b 0001, // index[ 11] ALERT_HANDLER_ALERT_REGWEN_5 + 4'b 0001, // index[ 12] ALERT_HANDLER_ALERT_REGWEN_6 + 4'b 0001, // index[ 13] ALERT_HANDLER_ALERT_REGWEN_7 + 4'b 0001, // index[ 14] ALERT_HANDLER_ALERT_REGWEN_8 + 4'b 0001, // index[ 15] ALERT_HANDLER_ALERT_REGWEN_9 + 4'b 0001, // index[ 16] ALERT_HANDLER_ALERT_REGWEN_10 + 4'b 0001, // index[ 17] ALERT_HANDLER_ALERT_REGWEN_11 + 4'b 0001, // index[ 18] ALERT_HANDLER_ALERT_REGWEN_12 + 4'b 0001, // index[ 19] ALERT_HANDLER_ALERT_REGWEN_13 + 4'b 0001, // index[ 20] ALERT_HANDLER_ALERT_REGWEN_14 + 4'b 0001, // index[ 21] ALERT_HANDLER_ALERT_REGWEN_15 + 4'b 0001, // index[ 22] ALERT_HANDLER_ALERT_REGWEN_16 + 4'b 0001, // index[ 23] ALERT_HANDLER_ALERT_REGWEN_17 + 4'b 0001, // index[ 24] ALERT_HANDLER_ALERT_REGWEN_18 + 4'b 0001, // index[ 25] ALERT_HANDLER_ALERT_REGWEN_19 + 4'b 0001, // index[ 26] ALERT_HANDLER_ALERT_REGWEN_20 + 4'b 0001, // index[ 27] ALERT_HANDLER_ALERT_REGWEN_21 + 4'b 0001, // index[ 28] ALERT_HANDLER_ALERT_REGWEN_22 + 4'b 0001, // index[ 29] ALERT_HANDLER_ALERT_REGWEN_23 + 4'b 0001, // index[ 30] ALERT_HANDLER_ALERT_REGWEN_24 + 4'b 0001, // index[ 31] ALERT_HANDLER_ALERT_REGWEN_25 + 4'b 0001, // index[ 32] ALERT_HANDLER_ALERT_REGWEN_26 + 4'b 0001, // index[ 33] ALERT_HANDLER_ALERT_REGWEN_27 + 4'b 0001, // index[ 34] ALERT_HANDLER_ALERT_REGWEN_28 + 4'b 0001, // index[ 35] ALERT_HANDLER_ALERT_REGWEN_29 + 4'b 0001, // index[ 36] ALERT_HANDLER_ALERT_REGWEN_30 + 4'b 0001, // index[ 37] ALERT_HANDLER_ALERT_REGWEN_31 + 4'b 0001, // index[ 38] ALERT_HANDLER_ALERT_REGWEN_32 + 4'b 0001, // index[ 39] ALERT_HANDLER_ALERT_REGWEN_33 + 4'b 0001, // index[ 40] ALERT_HANDLER_ALERT_REGWEN_34 + 4'b 0001, // index[ 41] ALERT_HANDLER_ALERT_REGWEN_35 + 4'b 0001, // index[ 42] ALERT_HANDLER_ALERT_REGWEN_36 + 4'b 0001, // index[ 43] ALERT_HANDLER_ALERT_REGWEN_37 + 4'b 0001, // index[ 44] ALERT_HANDLER_ALERT_REGWEN_38 + 4'b 0001, // index[ 45] ALERT_HANDLER_ALERT_REGWEN_39 + 4'b 0001, // index[ 46] ALERT_HANDLER_ALERT_REGWEN_40 + 4'b 0001, // index[ 47] ALERT_HANDLER_ALERT_REGWEN_41 + 4'b 0001, // index[ 48] ALERT_HANDLER_ALERT_REGWEN_42 + 4'b 0001, // index[ 49] ALERT_HANDLER_ALERT_REGWEN_43 + 4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_REGWEN_44 + 4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_REGWEN_45 + 4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_REGWEN_46 + 4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_REGWEN_47 + 4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_REGWEN_48 + 4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_REGWEN_49 + 4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_REGWEN_50 + 4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_REGWEN_51 + 4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_REGWEN_52 + 4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_REGWEN_53 + 4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_REGWEN_54 + 4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_REGWEN_55 + 4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_REGWEN_56 + 4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_REGWEN_57 + 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_REGWEN_58 + 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_REGWEN_59 + 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_REGWEN_60 + 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_REGWEN_61 + 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_REGWEN_62 + 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_REGWEN_63 + 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_REGWEN_64 + 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_REGWEN_65 + 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_REGWEN_66 + 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_REGWEN_67 + 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_REGWEN_68 + 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_REGWEN_69 + 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_REGWEN_70 + 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_REGWEN_71 + 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_REGWEN_72 + 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_REGWEN_73 + 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_REGWEN_74 + 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_REGWEN_75 + 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_REGWEN_76 + 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_REGWEN_77 + 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_REGWEN_78 + 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_REGWEN_79 + 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_REGWEN_80 + 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_REGWEN_81 + 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_REGWEN_82 + 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_REGWEN_83 + 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_REGWEN_84 + 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_REGWEN_85 + 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_REGWEN_86 + 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_REGWEN_87 + 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_REGWEN_88 + 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_REGWEN_89 + 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_REGWEN_90 + 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_REGWEN_91 + 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_REGWEN_92 + 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_REGWEN_93 + 4'b 0001, // index[100] ALERT_HANDLER_ALERT_REGWEN_94 + 4'b 0001, // index[101] ALERT_HANDLER_ALERT_REGWEN_95 + 4'b 0001, // index[102] ALERT_HANDLER_ALERT_REGWEN_96 + 4'b 0001, // index[103] ALERT_HANDLER_ALERT_REGWEN_97 + 4'b 0001, // index[104] ALERT_HANDLER_ALERT_REGWEN_98 + 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_7 + 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_8 + 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_9 + 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_10 + 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_11 + 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_12 + 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_13 + 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_14 + 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_15 + 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_16 + 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_17 + 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_18 + 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_19 + 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_20 + 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_21 + 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_22 + 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_23 + 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_24 + 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_25 + 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_26 + 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_SHADOWED_27 + 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_SHADOWED_28 + 4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_SHADOWED_29 + 4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_SHADOWED_30 + 4'b 0001, // index[136] ALERT_HANDLER_ALERT_EN_SHADOWED_31 + 4'b 0001, // index[137] ALERT_HANDLER_ALERT_EN_SHADOWED_32 + 4'b 0001, // index[138] ALERT_HANDLER_ALERT_EN_SHADOWED_33 + 4'b 0001, // index[139] ALERT_HANDLER_ALERT_EN_SHADOWED_34 + 4'b 0001, // index[140] ALERT_HANDLER_ALERT_EN_SHADOWED_35 + 4'b 0001, // index[141] ALERT_HANDLER_ALERT_EN_SHADOWED_36 + 4'b 0001, // index[142] ALERT_HANDLER_ALERT_EN_SHADOWED_37 + 4'b 0001, // index[143] ALERT_HANDLER_ALERT_EN_SHADOWED_38 + 4'b 0001, // index[144] ALERT_HANDLER_ALERT_EN_SHADOWED_39 + 4'b 0001, // index[145] ALERT_HANDLER_ALERT_EN_SHADOWED_40 + 4'b 0001, // index[146] ALERT_HANDLER_ALERT_EN_SHADOWED_41 + 4'b 0001, // index[147] ALERT_HANDLER_ALERT_EN_SHADOWED_42 + 4'b 0001, // index[148] ALERT_HANDLER_ALERT_EN_SHADOWED_43 + 4'b 0001, // index[149] ALERT_HANDLER_ALERT_EN_SHADOWED_44 + 4'b 0001, // index[150] ALERT_HANDLER_ALERT_EN_SHADOWED_45 + 4'b 0001, // index[151] ALERT_HANDLER_ALERT_EN_SHADOWED_46 + 4'b 0001, // index[152] ALERT_HANDLER_ALERT_EN_SHADOWED_47 + 4'b 0001, // index[153] ALERT_HANDLER_ALERT_EN_SHADOWED_48 + 4'b 0001, // index[154] ALERT_HANDLER_ALERT_EN_SHADOWED_49 + 4'b 0001, // index[155] ALERT_HANDLER_ALERT_EN_SHADOWED_50 + 4'b 0001, // index[156] ALERT_HANDLER_ALERT_EN_SHADOWED_51 + 4'b 0001, // index[157] ALERT_HANDLER_ALERT_EN_SHADOWED_52 + 4'b 0001, // index[158] ALERT_HANDLER_ALERT_EN_SHADOWED_53 + 4'b 0001, // index[159] ALERT_HANDLER_ALERT_EN_SHADOWED_54 + 4'b 0001, // index[160] ALERT_HANDLER_ALERT_EN_SHADOWED_55 + 4'b 0001, // index[161] ALERT_HANDLER_ALERT_EN_SHADOWED_56 + 4'b 0001, // index[162] ALERT_HANDLER_ALERT_EN_SHADOWED_57 + 4'b 0001, // index[163] ALERT_HANDLER_ALERT_EN_SHADOWED_58 + 4'b 0001, // index[164] ALERT_HANDLER_ALERT_EN_SHADOWED_59 + 4'b 0001, // index[165] ALERT_HANDLER_ALERT_EN_SHADOWED_60 + 4'b 0001, // index[166] ALERT_HANDLER_ALERT_EN_SHADOWED_61 + 4'b 0001, // index[167] ALERT_HANDLER_ALERT_EN_SHADOWED_62 + 4'b 0001, // index[168] ALERT_HANDLER_ALERT_EN_SHADOWED_63 + 4'b 0001, // index[169] ALERT_HANDLER_ALERT_EN_SHADOWED_64 + 4'b 0001, // index[170] ALERT_HANDLER_ALERT_EN_SHADOWED_65 + 4'b 0001, // index[171] ALERT_HANDLER_ALERT_EN_SHADOWED_66 + 4'b 0001, // index[172] ALERT_HANDLER_ALERT_EN_SHADOWED_67 + 4'b 0001, // index[173] ALERT_HANDLER_ALERT_EN_SHADOWED_68 + 4'b 0001, // index[174] ALERT_HANDLER_ALERT_EN_SHADOWED_69 + 4'b 0001, // index[175] ALERT_HANDLER_ALERT_EN_SHADOWED_70 + 4'b 0001, // index[176] ALERT_HANDLER_ALERT_EN_SHADOWED_71 + 4'b 0001, // index[177] ALERT_HANDLER_ALERT_EN_SHADOWED_72 + 4'b 0001, // index[178] ALERT_HANDLER_ALERT_EN_SHADOWED_73 + 4'b 0001, // index[179] ALERT_HANDLER_ALERT_EN_SHADOWED_74 + 4'b 0001, // index[180] ALERT_HANDLER_ALERT_EN_SHADOWED_75 + 4'b 0001, // index[181] ALERT_HANDLER_ALERT_EN_SHADOWED_76 + 4'b 0001, // index[182] ALERT_HANDLER_ALERT_EN_SHADOWED_77 + 4'b 0001, // index[183] ALERT_HANDLER_ALERT_EN_SHADOWED_78 + 4'b 0001, // index[184] ALERT_HANDLER_ALERT_EN_SHADOWED_79 + 4'b 0001, // index[185] ALERT_HANDLER_ALERT_EN_SHADOWED_80 + 4'b 0001, // index[186] ALERT_HANDLER_ALERT_EN_SHADOWED_81 + 4'b 0001, // index[187] ALERT_HANDLER_ALERT_EN_SHADOWED_82 + 4'b 0001, // index[188] ALERT_HANDLER_ALERT_EN_SHADOWED_83 + 4'b 0001, // index[189] ALERT_HANDLER_ALERT_EN_SHADOWED_84 + 4'b 0001, // index[190] ALERT_HANDLER_ALERT_EN_SHADOWED_85 + 4'b 0001, // index[191] ALERT_HANDLER_ALERT_EN_SHADOWED_86 + 4'b 0001, // index[192] ALERT_HANDLER_ALERT_EN_SHADOWED_87 + 4'b 0001, // index[193] ALERT_HANDLER_ALERT_EN_SHADOWED_88 + 4'b 0001, // index[194] ALERT_HANDLER_ALERT_EN_SHADOWED_89 + 4'b 0001, // index[195] ALERT_HANDLER_ALERT_EN_SHADOWED_90 + 4'b 0001, // index[196] ALERT_HANDLER_ALERT_EN_SHADOWED_91 + 4'b 0001, // index[197] ALERT_HANDLER_ALERT_EN_SHADOWED_92 + 4'b 0001, // index[198] ALERT_HANDLER_ALERT_EN_SHADOWED_93 + 4'b 0001, // index[199] ALERT_HANDLER_ALERT_EN_SHADOWED_94 + 4'b 0001, // index[200] ALERT_HANDLER_ALERT_EN_SHADOWED_95 + 4'b 0001, // index[201] ALERT_HANDLER_ALERT_EN_SHADOWED_96 + 4'b 0001, // index[202] ALERT_HANDLER_ALERT_EN_SHADOWED_97 + 4'b 0001, // index[203] ALERT_HANDLER_ALERT_EN_SHADOWED_98 + 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7 + 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8 + 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9 + 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10 + 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11 + 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12 + 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13 + 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14 + 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15 + 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16 + 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17 + 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18 + 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19 + 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20 + 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21 + 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22 + 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23 + 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24 + 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25 + 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26 + 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27 + 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28 + 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29 + 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30 + 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31 + 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32 + 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33 + 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34 + 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35 + 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36 + 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37 + 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38 + 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39 + 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40 + 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41 + 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42 + 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43 + 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44 + 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45 + 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46 + 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47 + 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48 + 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49 + 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50 + 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51 + 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52 + 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53 + 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54 + 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55 + 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56 + 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57 + 4'b 0001, // index[262] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58 + 4'b 0001, // index[263] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59 + 4'b 0001, // index[264] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60 + 4'b 0001, // index[265] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61 + 4'b 0001, // index[266] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62 + 4'b 0001, // index[267] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63 + 4'b 0001, // index[268] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64 + 4'b 0001, // index[269] ALERT_HANDLER_ALERT_CLASS_SHADOWED_65 + 4'b 0001, // index[270] ALERT_HANDLER_ALERT_CLASS_SHADOWED_66 + 4'b 0001, // index[271] ALERT_HANDLER_ALERT_CLASS_SHADOWED_67 + 4'b 0001, // index[272] ALERT_HANDLER_ALERT_CLASS_SHADOWED_68 + 4'b 0001, // index[273] ALERT_HANDLER_ALERT_CLASS_SHADOWED_69 + 4'b 0001, // index[274] ALERT_HANDLER_ALERT_CLASS_SHADOWED_70 + 4'b 0001, // index[275] ALERT_HANDLER_ALERT_CLASS_SHADOWED_71 + 4'b 0001, // index[276] ALERT_HANDLER_ALERT_CLASS_SHADOWED_72 + 4'b 0001, // index[277] ALERT_HANDLER_ALERT_CLASS_SHADOWED_73 + 4'b 0001, // index[278] ALERT_HANDLER_ALERT_CLASS_SHADOWED_74 + 4'b 0001, // index[279] ALERT_HANDLER_ALERT_CLASS_SHADOWED_75 + 4'b 0001, // index[280] ALERT_HANDLER_ALERT_CLASS_SHADOWED_76 + 4'b 0001, // index[281] ALERT_HANDLER_ALERT_CLASS_SHADOWED_77 + 4'b 0001, // index[282] ALERT_HANDLER_ALERT_CLASS_SHADOWED_78 + 4'b 0001, // index[283] ALERT_HANDLER_ALERT_CLASS_SHADOWED_79 + 4'b 0001, // index[284] ALERT_HANDLER_ALERT_CLASS_SHADOWED_80 + 4'b 0001, // index[285] ALERT_HANDLER_ALERT_CLASS_SHADOWED_81 + 4'b 0001, // index[286] ALERT_HANDLER_ALERT_CLASS_SHADOWED_82 + 4'b 0001, // index[287] ALERT_HANDLER_ALERT_CLASS_SHADOWED_83 + 4'b 0001, // index[288] ALERT_HANDLER_ALERT_CLASS_SHADOWED_84 + 4'b 0001, // index[289] ALERT_HANDLER_ALERT_CLASS_SHADOWED_85 + 4'b 0001, // index[290] ALERT_HANDLER_ALERT_CLASS_SHADOWED_86 + 4'b 0001, // index[291] ALERT_HANDLER_ALERT_CLASS_SHADOWED_87 + 4'b 0001, // index[292] ALERT_HANDLER_ALERT_CLASS_SHADOWED_88 + 4'b 0001, // index[293] ALERT_HANDLER_ALERT_CLASS_SHADOWED_89 + 4'b 0001, // index[294] ALERT_HANDLER_ALERT_CLASS_SHADOWED_90 + 4'b 0001, // index[295] ALERT_HANDLER_ALERT_CLASS_SHADOWED_91 + 4'b 0001, // index[296] ALERT_HANDLER_ALERT_CLASS_SHADOWED_92 + 4'b 0001, // index[297] ALERT_HANDLER_ALERT_CLASS_SHADOWED_93 + 4'b 0001, // index[298] ALERT_HANDLER_ALERT_CLASS_SHADOWED_94 + 4'b 0001, // index[299] ALERT_HANDLER_ALERT_CLASS_SHADOWED_95 + 4'b 0001, // index[300] ALERT_HANDLER_ALERT_CLASS_SHADOWED_96 + 4'b 0001, // index[301] ALERT_HANDLER_ALERT_CLASS_SHADOWED_97 + 4'b 0001, // index[302] ALERT_HANDLER_ALERT_CLASS_SHADOWED_98 + 4'b 0001, // index[303] ALERT_HANDLER_ALERT_CAUSE_0 + 4'b 0001, // index[304] ALERT_HANDLER_ALERT_CAUSE_1 + 4'b 0001, // index[305] ALERT_HANDLER_ALERT_CAUSE_2 + 4'b 0001, // index[306] ALERT_HANDLER_ALERT_CAUSE_3 + 4'b 0001, // index[307] ALERT_HANDLER_ALERT_CAUSE_4 + 4'b 0001, // index[308] ALERT_HANDLER_ALERT_CAUSE_5 + 4'b 0001, // index[309] ALERT_HANDLER_ALERT_CAUSE_6 + 4'b 0001, // index[310] ALERT_HANDLER_ALERT_CAUSE_7 + 4'b 0001, // index[311] ALERT_HANDLER_ALERT_CAUSE_8 + 4'b 0001, // index[312] ALERT_HANDLER_ALERT_CAUSE_9 + 4'b 0001, // index[313] ALERT_HANDLER_ALERT_CAUSE_10 + 4'b 0001, // index[314] ALERT_HANDLER_ALERT_CAUSE_11 + 4'b 0001, // index[315] ALERT_HANDLER_ALERT_CAUSE_12 + 4'b 0001, // index[316] ALERT_HANDLER_ALERT_CAUSE_13 + 4'b 0001, // index[317] ALERT_HANDLER_ALERT_CAUSE_14 + 4'b 0001, // index[318] ALERT_HANDLER_ALERT_CAUSE_15 + 4'b 0001, // index[319] ALERT_HANDLER_ALERT_CAUSE_16 + 4'b 0001, // index[320] ALERT_HANDLER_ALERT_CAUSE_17 + 4'b 0001, // index[321] ALERT_HANDLER_ALERT_CAUSE_18 + 4'b 0001, // index[322] ALERT_HANDLER_ALERT_CAUSE_19 + 4'b 0001, // index[323] ALERT_HANDLER_ALERT_CAUSE_20 + 4'b 0001, // index[324] ALERT_HANDLER_ALERT_CAUSE_21 + 4'b 0001, // index[325] ALERT_HANDLER_ALERT_CAUSE_22 + 4'b 0001, // index[326] ALERT_HANDLER_ALERT_CAUSE_23 + 4'b 0001, // index[327] ALERT_HANDLER_ALERT_CAUSE_24 + 4'b 0001, // index[328] ALERT_HANDLER_ALERT_CAUSE_25 + 4'b 0001, // index[329] ALERT_HANDLER_ALERT_CAUSE_26 + 4'b 0001, // index[330] ALERT_HANDLER_ALERT_CAUSE_27 + 4'b 0001, // index[331] ALERT_HANDLER_ALERT_CAUSE_28 + 4'b 0001, // index[332] ALERT_HANDLER_ALERT_CAUSE_29 + 4'b 0001, // index[333] ALERT_HANDLER_ALERT_CAUSE_30 + 4'b 0001, // index[334] ALERT_HANDLER_ALERT_CAUSE_31 + 4'b 0001, // index[335] ALERT_HANDLER_ALERT_CAUSE_32 + 4'b 0001, // index[336] ALERT_HANDLER_ALERT_CAUSE_33 + 4'b 0001, // index[337] ALERT_HANDLER_ALERT_CAUSE_34 + 4'b 0001, // index[338] ALERT_HANDLER_ALERT_CAUSE_35 + 4'b 0001, // index[339] ALERT_HANDLER_ALERT_CAUSE_36 + 4'b 0001, // index[340] ALERT_HANDLER_ALERT_CAUSE_37 + 4'b 0001, // index[341] ALERT_HANDLER_ALERT_CAUSE_38 + 4'b 0001, // index[342] ALERT_HANDLER_ALERT_CAUSE_39 + 4'b 0001, // index[343] ALERT_HANDLER_ALERT_CAUSE_40 + 4'b 0001, // index[344] ALERT_HANDLER_ALERT_CAUSE_41 + 4'b 0001, // index[345] ALERT_HANDLER_ALERT_CAUSE_42 + 4'b 0001, // index[346] ALERT_HANDLER_ALERT_CAUSE_43 + 4'b 0001, // index[347] ALERT_HANDLER_ALERT_CAUSE_44 + 4'b 0001, // index[348] ALERT_HANDLER_ALERT_CAUSE_45 + 4'b 0001, // index[349] ALERT_HANDLER_ALERT_CAUSE_46 + 4'b 0001, // index[350] ALERT_HANDLER_ALERT_CAUSE_47 + 4'b 0001, // index[351] ALERT_HANDLER_ALERT_CAUSE_48 + 4'b 0001, // index[352] ALERT_HANDLER_ALERT_CAUSE_49 + 4'b 0001, // index[353] ALERT_HANDLER_ALERT_CAUSE_50 + 4'b 0001, // index[354] ALERT_HANDLER_ALERT_CAUSE_51 + 4'b 0001, // index[355] ALERT_HANDLER_ALERT_CAUSE_52 + 4'b 0001, // index[356] ALERT_HANDLER_ALERT_CAUSE_53 + 4'b 0001, // index[357] ALERT_HANDLER_ALERT_CAUSE_54 + 4'b 0001, // index[358] ALERT_HANDLER_ALERT_CAUSE_55 + 4'b 0001, // index[359] ALERT_HANDLER_ALERT_CAUSE_56 + 4'b 0001, // index[360] ALERT_HANDLER_ALERT_CAUSE_57 + 4'b 0001, // index[361] ALERT_HANDLER_ALERT_CAUSE_58 + 4'b 0001, // index[362] ALERT_HANDLER_ALERT_CAUSE_59 + 4'b 0001, // index[363] ALERT_HANDLER_ALERT_CAUSE_60 + 4'b 0001, // index[364] ALERT_HANDLER_ALERT_CAUSE_61 + 4'b 0001, // index[365] ALERT_HANDLER_ALERT_CAUSE_62 + 4'b 0001, // index[366] ALERT_HANDLER_ALERT_CAUSE_63 + 4'b 0001, // index[367] ALERT_HANDLER_ALERT_CAUSE_64 + 4'b 0001, // index[368] ALERT_HANDLER_ALERT_CAUSE_65 + 4'b 0001, // index[369] ALERT_HANDLER_ALERT_CAUSE_66 + 4'b 0001, // index[370] ALERT_HANDLER_ALERT_CAUSE_67 + 4'b 0001, // index[371] ALERT_HANDLER_ALERT_CAUSE_68 + 4'b 0001, // index[372] ALERT_HANDLER_ALERT_CAUSE_69 + 4'b 0001, // index[373] ALERT_HANDLER_ALERT_CAUSE_70 + 4'b 0001, // index[374] ALERT_HANDLER_ALERT_CAUSE_71 + 4'b 0001, // index[375] ALERT_HANDLER_ALERT_CAUSE_72 + 4'b 0001, // index[376] ALERT_HANDLER_ALERT_CAUSE_73 + 4'b 0001, // index[377] ALERT_HANDLER_ALERT_CAUSE_74 + 4'b 0001, // index[378] ALERT_HANDLER_ALERT_CAUSE_75 + 4'b 0001, // index[379] ALERT_HANDLER_ALERT_CAUSE_76 + 4'b 0001, // index[380] ALERT_HANDLER_ALERT_CAUSE_77 + 4'b 0001, // index[381] ALERT_HANDLER_ALERT_CAUSE_78 + 4'b 0001, // index[382] ALERT_HANDLER_ALERT_CAUSE_79 + 4'b 0001, // index[383] ALERT_HANDLER_ALERT_CAUSE_80 + 4'b 0001, // index[384] ALERT_HANDLER_ALERT_CAUSE_81 + 4'b 0001, // index[385] ALERT_HANDLER_ALERT_CAUSE_82 + 4'b 0001, // index[386] ALERT_HANDLER_ALERT_CAUSE_83 + 4'b 0001, // index[387] ALERT_HANDLER_ALERT_CAUSE_84 + 4'b 0001, // index[388] ALERT_HANDLER_ALERT_CAUSE_85 + 4'b 0001, // index[389] ALERT_HANDLER_ALERT_CAUSE_86 + 4'b 0001, // index[390] ALERT_HANDLER_ALERT_CAUSE_87 + 4'b 0001, // index[391] ALERT_HANDLER_ALERT_CAUSE_88 + 4'b 0001, // index[392] ALERT_HANDLER_ALERT_CAUSE_89 + 4'b 0001, // index[393] ALERT_HANDLER_ALERT_CAUSE_90 + 4'b 0001, // index[394] ALERT_HANDLER_ALERT_CAUSE_91 + 4'b 0001, // index[395] ALERT_HANDLER_ALERT_CAUSE_92 + 4'b 0001, // index[396] ALERT_HANDLER_ALERT_CAUSE_93 + 4'b 0001, // index[397] ALERT_HANDLER_ALERT_CAUSE_94 + 4'b 0001, // index[398] ALERT_HANDLER_ALERT_CAUSE_95 + 4'b 0001, // index[399] ALERT_HANDLER_ALERT_CAUSE_96 + 4'b 0001, // index[400] ALERT_HANDLER_ALERT_CAUSE_97 + 4'b 0001, // index[401] ALERT_HANDLER_ALERT_CAUSE_98 + 4'b 0001, // index[402] ALERT_HANDLER_LOC_ALERT_REGWEN_0 + 4'b 0001, // index[403] ALERT_HANDLER_LOC_ALERT_REGWEN_1 + 4'b 0001, // index[404] ALERT_HANDLER_LOC_ALERT_REGWEN_2 + 4'b 0001, // index[405] ALERT_HANDLER_LOC_ALERT_REGWEN_3 + 4'b 0001, // index[406] ALERT_HANDLER_LOC_ALERT_REGWEN_4 + 4'b 0001, // index[407] ALERT_HANDLER_LOC_ALERT_REGWEN_5 + 4'b 0001, // index[408] ALERT_HANDLER_LOC_ALERT_REGWEN_6 + 4'b 0001, // index[409] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[410] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[411] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[412] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[413] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[414] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[415] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[416] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[417] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[418] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[419] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[420] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[421] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[422] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[423] ALERT_HANDLER_LOC_ALERT_CAUSE_0 + 4'b 0001, // index[424] ALERT_HANDLER_LOC_ALERT_CAUSE_1 + 4'b 0001, // index[425] ALERT_HANDLER_LOC_ALERT_CAUSE_2 + 4'b 0001, // index[426] ALERT_HANDLER_LOC_ALERT_CAUSE_3 + 4'b 0001, // index[427] ALERT_HANDLER_LOC_ALERT_CAUSE_4 + 4'b 0001, // index[428] ALERT_HANDLER_LOC_ALERT_CAUSE_5 + 4'b 0001, // index[429] ALERT_HANDLER_LOC_ALERT_CAUSE_6 + 4'b 0001, // index[430] ALERT_HANDLER_CLASSA_REGWEN + 4'b 0011, // index[431] ALERT_HANDLER_CLASSA_CTRL_SHADOWED + 4'b 0001, // index[432] ALERT_HANDLER_CLASSA_CLR_REGWEN + 4'b 0001, // index[433] ALERT_HANDLER_CLASSA_CLR_SHADOWED + 4'b 0011, // index[434] ALERT_HANDLER_CLASSA_ACCUM_CNT + 4'b 0011, // index[435] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[436] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[437] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[438] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED + 4'b 1111, // index[439] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED + 4'b 1111, // index[440] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED + 4'b 1111, // index[441] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED + 4'b 1111, // index[442] ALERT_HANDLER_CLASSA_ESC_CNT + 4'b 0001, // index[443] ALERT_HANDLER_CLASSA_STATE + 4'b 0001, // index[444] ALERT_HANDLER_CLASSB_REGWEN + 4'b 0011, // index[445] ALERT_HANDLER_CLASSB_CTRL_SHADOWED + 4'b 0001, // index[446] ALERT_HANDLER_CLASSB_CLR_REGWEN + 4'b 0001, // index[447] ALERT_HANDLER_CLASSB_CLR_SHADOWED + 4'b 0011, // index[448] ALERT_HANDLER_CLASSB_ACCUM_CNT + 4'b 0011, // index[449] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[450] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[451] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[452] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED + 4'b 1111, // index[453] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED + 4'b 1111, // index[454] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED + 4'b 1111, // index[455] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED + 4'b 1111, // index[456] ALERT_HANDLER_CLASSB_ESC_CNT + 4'b 0001, // index[457] ALERT_HANDLER_CLASSB_STATE + 4'b 0001, // index[458] ALERT_HANDLER_CLASSC_REGWEN + 4'b 0011, // index[459] ALERT_HANDLER_CLASSC_CTRL_SHADOWED + 4'b 0001, // index[460] ALERT_HANDLER_CLASSC_CLR_REGWEN + 4'b 0001, // index[461] ALERT_HANDLER_CLASSC_CLR_SHADOWED + 4'b 0011, // index[462] ALERT_HANDLER_CLASSC_ACCUM_CNT + 4'b 0011, // index[463] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[464] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[465] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[466] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED + 4'b 1111, // index[467] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED + 4'b 1111, // index[468] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED + 4'b 1111, // index[469] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED + 4'b 1111, // index[470] ALERT_HANDLER_CLASSC_ESC_CNT + 4'b 0001, // index[471] ALERT_HANDLER_CLASSC_STATE + 4'b 0001, // index[472] ALERT_HANDLER_CLASSD_REGWEN + 4'b 0011, // index[473] ALERT_HANDLER_CLASSD_CTRL_SHADOWED + 4'b 0001, // index[474] ALERT_HANDLER_CLASSD_CLR_REGWEN + 4'b 0001, // index[475] ALERT_HANDLER_CLASSD_CLR_SHADOWED + 4'b 0011, // index[476] ALERT_HANDLER_CLASSD_ACCUM_CNT + 4'b 0011, // index[477] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[478] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[479] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[480] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED + 4'b 1111, // index[481] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED + 4'b 1111, // index[482] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED + 4'b 1111, // index[483] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED + 4'b 1111, // index[484] ALERT_HANDLER_CLASSD_ESC_CNT + 4'b 0001 // index[485] ALERT_HANDLER_CLASSD_STATE + }; + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv new file mode 100644 index 0000000000000..677a4c5347f71 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv @@ -0,0 +1,26812 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module alert_handler_reg_top ( + input clk_i, + input rst_ni, + input rst_shadowed_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw, // Write + input alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg, // Read + + output logic shadowed_storage_err_o, + output logic shadowed_update_err_o, + + // Integrity check errors + output logic intg_err_o +); + + import alert_handler_reg_pkg::* ; + + localparam int AW = 11; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [485:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(486) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic intr_state_we; + logic intr_state_classa_qs; + logic intr_state_classa_wd; + logic intr_state_classb_qs; + logic intr_state_classb_wd; + logic intr_state_classc_qs; + logic intr_state_classc_wd; + logic intr_state_classd_qs; + logic intr_state_classd_wd; + logic intr_enable_we; + logic intr_enable_classa_qs; + logic intr_enable_classa_wd; + logic intr_enable_classb_qs; + logic intr_enable_classb_wd; + logic intr_enable_classc_qs; + logic intr_enable_classc_wd; + logic intr_enable_classd_qs; + logic intr_enable_classd_wd; + logic intr_test_we; + logic intr_test_classa_wd; + logic intr_test_classb_wd; + logic intr_test_classc_wd; + logic intr_test_classd_wd; + logic ping_timer_regwen_we; + logic ping_timer_regwen_qs; + logic ping_timer_regwen_wd; + logic ping_timeout_cyc_shadowed_re; + logic ping_timeout_cyc_shadowed_we; + logic [15:0] ping_timeout_cyc_shadowed_qs; + logic [15:0] ping_timeout_cyc_shadowed_wd; + logic ping_timeout_cyc_shadowed_storage_err; + logic ping_timeout_cyc_shadowed_update_err; + logic ping_timer_en_shadowed_re; + logic ping_timer_en_shadowed_we; + logic ping_timer_en_shadowed_qs; + logic ping_timer_en_shadowed_wd; + logic ping_timer_en_shadowed_storage_err; + logic ping_timer_en_shadowed_update_err; + logic alert_regwen_0_we; + logic alert_regwen_0_qs; + logic alert_regwen_0_wd; + logic alert_regwen_1_we; + logic alert_regwen_1_qs; + logic alert_regwen_1_wd; + logic alert_regwen_2_we; + logic alert_regwen_2_qs; + logic alert_regwen_2_wd; + logic alert_regwen_3_we; + logic alert_regwen_3_qs; + logic alert_regwen_3_wd; + logic alert_regwen_4_we; + logic alert_regwen_4_qs; + logic alert_regwen_4_wd; + logic alert_regwen_5_we; + logic alert_regwen_5_qs; + logic alert_regwen_5_wd; + logic alert_regwen_6_we; + logic alert_regwen_6_qs; + logic alert_regwen_6_wd; + logic alert_regwen_7_we; + logic alert_regwen_7_qs; + logic alert_regwen_7_wd; + logic alert_regwen_8_we; + logic alert_regwen_8_qs; + logic alert_regwen_8_wd; + logic alert_regwen_9_we; + logic alert_regwen_9_qs; + logic alert_regwen_9_wd; + logic alert_regwen_10_we; + logic alert_regwen_10_qs; + logic alert_regwen_10_wd; + logic alert_regwen_11_we; + logic alert_regwen_11_qs; + logic alert_regwen_11_wd; + logic alert_regwen_12_we; + logic alert_regwen_12_qs; + logic alert_regwen_12_wd; + logic alert_regwen_13_we; + logic alert_regwen_13_qs; + logic alert_regwen_13_wd; + logic alert_regwen_14_we; + logic alert_regwen_14_qs; + logic alert_regwen_14_wd; + logic alert_regwen_15_we; + logic alert_regwen_15_qs; + logic alert_regwen_15_wd; + logic alert_regwen_16_we; + logic alert_regwen_16_qs; + logic alert_regwen_16_wd; + logic alert_regwen_17_we; + logic alert_regwen_17_qs; + logic alert_regwen_17_wd; + logic alert_regwen_18_we; + logic alert_regwen_18_qs; + logic alert_regwen_18_wd; + logic alert_regwen_19_we; + logic alert_regwen_19_qs; + logic alert_regwen_19_wd; + logic alert_regwen_20_we; + logic alert_regwen_20_qs; + logic alert_regwen_20_wd; + logic alert_regwen_21_we; + logic alert_regwen_21_qs; + logic alert_regwen_21_wd; + logic alert_regwen_22_we; + logic alert_regwen_22_qs; + logic alert_regwen_22_wd; + logic alert_regwen_23_we; + logic alert_regwen_23_qs; + logic alert_regwen_23_wd; + logic alert_regwen_24_we; + logic alert_regwen_24_qs; + logic alert_regwen_24_wd; + logic alert_regwen_25_we; + logic alert_regwen_25_qs; + logic alert_regwen_25_wd; + logic alert_regwen_26_we; + logic alert_regwen_26_qs; + logic alert_regwen_26_wd; + logic alert_regwen_27_we; + logic alert_regwen_27_qs; + logic alert_regwen_27_wd; + logic alert_regwen_28_we; + logic alert_regwen_28_qs; + logic alert_regwen_28_wd; + logic alert_regwen_29_we; + logic alert_regwen_29_qs; + logic alert_regwen_29_wd; + logic alert_regwen_30_we; + logic alert_regwen_30_qs; + logic alert_regwen_30_wd; + logic alert_regwen_31_we; + logic alert_regwen_31_qs; + logic alert_regwen_31_wd; + logic alert_regwen_32_we; + logic alert_regwen_32_qs; + logic alert_regwen_32_wd; + logic alert_regwen_33_we; + logic alert_regwen_33_qs; + logic alert_regwen_33_wd; + logic alert_regwen_34_we; + logic alert_regwen_34_qs; + logic alert_regwen_34_wd; + logic alert_regwen_35_we; + logic alert_regwen_35_qs; + logic alert_regwen_35_wd; + logic alert_regwen_36_we; + logic alert_regwen_36_qs; + logic alert_regwen_36_wd; + logic alert_regwen_37_we; + logic alert_regwen_37_qs; + logic alert_regwen_37_wd; + logic alert_regwen_38_we; + logic alert_regwen_38_qs; + logic alert_regwen_38_wd; + logic alert_regwen_39_we; + logic alert_regwen_39_qs; + logic alert_regwen_39_wd; + logic alert_regwen_40_we; + logic alert_regwen_40_qs; + logic alert_regwen_40_wd; + logic alert_regwen_41_we; + logic alert_regwen_41_qs; + logic alert_regwen_41_wd; + logic alert_regwen_42_we; + logic alert_regwen_42_qs; + logic alert_regwen_42_wd; + logic alert_regwen_43_we; + logic alert_regwen_43_qs; + logic alert_regwen_43_wd; + logic alert_regwen_44_we; + logic alert_regwen_44_qs; + logic alert_regwen_44_wd; + logic alert_regwen_45_we; + logic alert_regwen_45_qs; + logic alert_regwen_45_wd; + logic alert_regwen_46_we; + logic alert_regwen_46_qs; + logic alert_regwen_46_wd; + logic alert_regwen_47_we; + logic alert_regwen_47_qs; + logic alert_regwen_47_wd; + logic alert_regwen_48_we; + logic alert_regwen_48_qs; + logic alert_regwen_48_wd; + logic alert_regwen_49_we; + logic alert_regwen_49_qs; + logic alert_regwen_49_wd; + logic alert_regwen_50_we; + logic alert_regwen_50_qs; + logic alert_regwen_50_wd; + logic alert_regwen_51_we; + logic alert_regwen_51_qs; + logic alert_regwen_51_wd; + logic alert_regwen_52_we; + logic alert_regwen_52_qs; + logic alert_regwen_52_wd; + logic alert_regwen_53_we; + logic alert_regwen_53_qs; + logic alert_regwen_53_wd; + logic alert_regwen_54_we; + logic alert_regwen_54_qs; + logic alert_regwen_54_wd; + logic alert_regwen_55_we; + logic alert_regwen_55_qs; + logic alert_regwen_55_wd; + logic alert_regwen_56_we; + logic alert_regwen_56_qs; + logic alert_regwen_56_wd; + logic alert_regwen_57_we; + logic alert_regwen_57_qs; + logic alert_regwen_57_wd; + logic alert_regwen_58_we; + logic alert_regwen_58_qs; + logic alert_regwen_58_wd; + logic alert_regwen_59_we; + logic alert_regwen_59_qs; + logic alert_regwen_59_wd; + logic alert_regwen_60_we; + logic alert_regwen_60_qs; + logic alert_regwen_60_wd; + logic alert_regwen_61_we; + logic alert_regwen_61_qs; + logic alert_regwen_61_wd; + logic alert_regwen_62_we; + logic alert_regwen_62_qs; + logic alert_regwen_62_wd; + logic alert_regwen_63_we; + logic alert_regwen_63_qs; + logic alert_regwen_63_wd; + logic alert_regwen_64_we; + logic alert_regwen_64_qs; + logic alert_regwen_64_wd; + logic alert_regwen_65_we; + logic alert_regwen_65_qs; + logic alert_regwen_65_wd; + logic alert_regwen_66_we; + logic alert_regwen_66_qs; + logic alert_regwen_66_wd; + logic alert_regwen_67_we; + logic alert_regwen_67_qs; + logic alert_regwen_67_wd; + logic alert_regwen_68_we; + logic alert_regwen_68_qs; + logic alert_regwen_68_wd; + logic alert_regwen_69_we; + logic alert_regwen_69_qs; + logic alert_regwen_69_wd; + logic alert_regwen_70_we; + logic alert_regwen_70_qs; + logic alert_regwen_70_wd; + logic alert_regwen_71_we; + logic alert_regwen_71_qs; + logic alert_regwen_71_wd; + logic alert_regwen_72_we; + logic alert_regwen_72_qs; + logic alert_regwen_72_wd; + logic alert_regwen_73_we; + logic alert_regwen_73_qs; + logic alert_regwen_73_wd; + logic alert_regwen_74_we; + logic alert_regwen_74_qs; + logic alert_regwen_74_wd; + logic alert_regwen_75_we; + logic alert_regwen_75_qs; + logic alert_regwen_75_wd; + logic alert_regwen_76_we; + logic alert_regwen_76_qs; + logic alert_regwen_76_wd; + logic alert_regwen_77_we; + logic alert_regwen_77_qs; + logic alert_regwen_77_wd; + logic alert_regwen_78_we; + logic alert_regwen_78_qs; + logic alert_regwen_78_wd; + logic alert_regwen_79_we; + logic alert_regwen_79_qs; + logic alert_regwen_79_wd; + logic alert_regwen_80_we; + logic alert_regwen_80_qs; + logic alert_regwen_80_wd; + logic alert_regwen_81_we; + logic alert_regwen_81_qs; + logic alert_regwen_81_wd; + logic alert_regwen_82_we; + logic alert_regwen_82_qs; + logic alert_regwen_82_wd; + logic alert_regwen_83_we; + logic alert_regwen_83_qs; + logic alert_regwen_83_wd; + logic alert_regwen_84_we; + logic alert_regwen_84_qs; + logic alert_regwen_84_wd; + logic alert_regwen_85_we; + logic alert_regwen_85_qs; + logic alert_regwen_85_wd; + logic alert_regwen_86_we; + logic alert_regwen_86_qs; + logic alert_regwen_86_wd; + logic alert_regwen_87_we; + logic alert_regwen_87_qs; + logic alert_regwen_87_wd; + logic alert_regwen_88_we; + logic alert_regwen_88_qs; + logic alert_regwen_88_wd; + logic alert_regwen_89_we; + logic alert_regwen_89_qs; + logic alert_regwen_89_wd; + logic alert_regwen_90_we; + logic alert_regwen_90_qs; + logic alert_regwen_90_wd; + logic alert_regwen_91_we; + logic alert_regwen_91_qs; + logic alert_regwen_91_wd; + logic alert_regwen_92_we; + logic alert_regwen_92_qs; + logic alert_regwen_92_wd; + logic alert_regwen_93_we; + logic alert_regwen_93_qs; + logic alert_regwen_93_wd; + logic alert_regwen_94_we; + logic alert_regwen_94_qs; + logic alert_regwen_94_wd; + logic alert_regwen_95_we; + logic alert_regwen_95_qs; + logic alert_regwen_95_wd; + logic alert_regwen_96_we; + logic alert_regwen_96_qs; + logic alert_regwen_96_wd; + logic alert_regwen_97_we; + logic alert_regwen_97_qs; + logic alert_regwen_97_wd; + logic alert_regwen_98_we; + logic alert_regwen_98_qs; + logic alert_regwen_98_wd; + logic alert_en_shadowed_0_re; + logic alert_en_shadowed_0_we; + logic alert_en_shadowed_0_qs; + logic alert_en_shadowed_0_wd; + logic alert_en_shadowed_0_storage_err; + logic alert_en_shadowed_0_update_err; + logic alert_en_shadowed_1_re; + logic alert_en_shadowed_1_we; + logic alert_en_shadowed_1_qs; + logic alert_en_shadowed_1_wd; + logic alert_en_shadowed_1_storage_err; + logic alert_en_shadowed_1_update_err; + logic alert_en_shadowed_2_re; + logic alert_en_shadowed_2_we; + logic alert_en_shadowed_2_qs; + logic alert_en_shadowed_2_wd; + logic alert_en_shadowed_2_storage_err; + logic alert_en_shadowed_2_update_err; + logic alert_en_shadowed_3_re; + logic alert_en_shadowed_3_we; + logic alert_en_shadowed_3_qs; + logic alert_en_shadowed_3_wd; + logic alert_en_shadowed_3_storage_err; + logic alert_en_shadowed_3_update_err; + logic alert_en_shadowed_4_re; + logic alert_en_shadowed_4_we; + logic alert_en_shadowed_4_qs; + logic alert_en_shadowed_4_wd; + logic alert_en_shadowed_4_storage_err; + logic alert_en_shadowed_4_update_err; + logic alert_en_shadowed_5_re; + logic alert_en_shadowed_5_we; + logic alert_en_shadowed_5_qs; + logic alert_en_shadowed_5_wd; + logic alert_en_shadowed_5_storage_err; + logic alert_en_shadowed_5_update_err; + logic alert_en_shadowed_6_re; + logic alert_en_shadowed_6_we; + logic alert_en_shadowed_6_qs; + logic alert_en_shadowed_6_wd; + logic alert_en_shadowed_6_storage_err; + logic alert_en_shadowed_6_update_err; + logic alert_en_shadowed_7_re; + logic alert_en_shadowed_7_we; + logic alert_en_shadowed_7_qs; + logic alert_en_shadowed_7_wd; + logic alert_en_shadowed_7_storage_err; + logic alert_en_shadowed_7_update_err; + logic alert_en_shadowed_8_re; + logic alert_en_shadowed_8_we; + logic alert_en_shadowed_8_qs; + logic alert_en_shadowed_8_wd; + logic alert_en_shadowed_8_storage_err; + logic alert_en_shadowed_8_update_err; + logic alert_en_shadowed_9_re; + logic alert_en_shadowed_9_we; + logic alert_en_shadowed_9_qs; + logic alert_en_shadowed_9_wd; + logic alert_en_shadowed_9_storage_err; + logic alert_en_shadowed_9_update_err; + logic alert_en_shadowed_10_re; + logic alert_en_shadowed_10_we; + logic alert_en_shadowed_10_qs; + logic alert_en_shadowed_10_wd; + logic alert_en_shadowed_10_storage_err; + logic alert_en_shadowed_10_update_err; + logic alert_en_shadowed_11_re; + logic alert_en_shadowed_11_we; + logic alert_en_shadowed_11_qs; + logic alert_en_shadowed_11_wd; + logic alert_en_shadowed_11_storage_err; + logic alert_en_shadowed_11_update_err; + logic alert_en_shadowed_12_re; + logic alert_en_shadowed_12_we; + logic alert_en_shadowed_12_qs; + logic alert_en_shadowed_12_wd; + logic alert_en_shadowed_12_storage_err; + logic alert_en_shadowed_12_update_err; + logic alert_en_shadowed_13_re; + logic alert_en_shadowed_13_we; + logic alert_en_shadowed_13_qs; + logic alert_en_shadowed_13_wd; + logic alert_en_shadowed_13_storage_err; + logic alert_en_shadowed_13_update_err; + logic alert_en_shadowed_14_re; + logic alert_en_shadowed_14_we; + logic alert_en_shadowed_14_qs; + logic alert_en_shadowed_14_wd; + logic alert_en_shadowed_14_storage_err; + logic alert_en_shadowed_14_update_err; + logic alert_en_shadowed_15_re; + logic alert_en_shadowed_15_we; + logic alert_en_shadowed_15_qs; + logic alert_en_shadowed_15_wd; + logic alert_en_shadowed_15_storage_err; + logic alert_en_shadowed_15_update_err; + logic alert_en_shadowed_16_re; + logic alert_en_shadowed_16_we; + logic alert_en_shadowed_16_qs; + logic alert_en_shadowed_16_wd; + logic alert_en_shadowed_16_storage_err; + logic alert_en_shadowed_16_update_err; + logic alert_en_shadowed_17_re; + logic alert_en_shadowed_17_we; + logic alert_en_shadowed_17_qs; + logic alert_en_shadowed_17_wd; + logic alert_en_shadowed_17_storage_err; + logic alert_en_shadowed_17_update_err; + logic alert_en_shadowed_18_re; + logic alert_en_shadowed_18_we; + logic alert_en_shadowed_18_qs; + logic alert_en_shadowed_18_wd; + logic alert_en_shadowed_18_storage_err; + logic alert_en_shadowed_18_update_err; + logic alert_en_shadowed_19_re; + logic alert_en_shadowed_19_we; + logic alert_en_shadowed_19_qs; + logic alert_en_shadowed_19_wd; + logic alert_en_shadowed_19_storage_err; + logic alert_en_shadowed_19_update_err; + logic alert_en_shadowed_20_re; + logic alert_en_shadowed_20_we; + logic alert_en_shadowed_20_qs; + logic alert_en_shadowed_20_wd; + logic alert_en_shadowed_20_storage_err; + logic alert_en_shadowed_20_update_err; + logic alert_en_shadowed_21_re; + logic alert_en_shadowed_21_we; + logic alert_en_shadowed_21_qs; + logic alert_en_shadowed_21_wd; + logic alert_en_shadowed_21_storage_err; + logic alert_en_shadowed_21_update_err; + logic alert_en_shadowed_22_re; + logic alert_en_shadowed_22_we; + logic alert_en_shadowed_22_qs; + logic alert_en_shadowed_22_wd; + logic alert_en_shadowed_22_storage_err; + logic alert_en_shadowed_22_update_err; + logic alert_en_shadowed_23_re; + logic alert_en_shadowed_23_we; + logic alert_en_shadowed_23_qs; + logic alert_en_shadowed_23_wd; + logic alert_en_shadowed_23_storage_err; + logic alert_en_shadowed_23_update_err; + logic alert_en_shadowed_24_re; + logic alert_en_shadowed_24_we; + logic alert_en_shadowed_24_qs; + logic alert_en_shadowed_24_wd; + logic alert_en_shadowed_24_storage_err; + logic alert_en_shadowed_24_update_err; + logic alert_en_shadowed_25_re; + logic alert_en_shadowed_25_we; + logic alert_en_shadowed_25_qs; + logic alert_en_shadowed_25_wd; + logic alert_en_shadowed_25_storage_err; + logic alert_en_shadowed_25_update_err; + logic alert_en_shadowed_26_re; + logic alert_en_shadowed_26_we; + logic alert_en_shadowed_26_qs; + logic alert_en_shadowed_26_wd; + logic alert_en_shadowed_26_storage_err; + logic alert_en_shadowed_26_update_err; + logic alert_en_shadowed_27_re; + logic alert_en_shadowed_27_we; + logic alert_en_shadowed_27_qs; + logic alert_en_shadowed_27_wd; + logic alert_en_shadowed_27_storage_err; + logic alert_en_shadowed_27_update_err; + logic alert_en_shadowed_28_re; + logic alert_en_shadowed_28_we; + logic alert_en_shadowed_28_qs; + logic alert_en_shadowed_28_wd; + logic alert_en_shadowed_28_storage_err; + logic alert_en_shadowed_28_update_err; + logic alert_en_shadowed_29_re; + logic alert_en_shadowed_29_we; + logic alert_en_shadowed_29_qs; + logic alert_en_shadowed_29_wd; + logic alert_en_shadowed_29_storage_err; + logic alert_en_shadowed_29_update_err; + logic alert_en_shadowed_30_re; + logic alert_en_shadowed_30_we; + logic alert_en_shadowed_30_qs; + logic alert_en_shadowed_30_wd; + logic alert_en_shadowed_30_storage_err; + logic alert_en_shadowed_30_update_err; + logic alert_en_shadowed_31_re; + logic alert_en_shadowed_31_we; + logic alert_en_shadowed_31_qs; + logic alert_en_shadowed_31_wd; + logic alert_en_shadowed_31_storage_err; + logic alert_en_shadowed_31_update_err; + logic alert_en_shadowed_32_re; + logic alert_en_shadowed_32_we; + logic alert_en_shadowed_32_qs; + logic alert_en_shadowed_32_wd; + logic alert_en_shadowed_32_storage_err; + logic alert_en_shadowed_32_update_err; + logic alert_en_shadowed_33_re; + logic alert_en_shadowed_33_we; + logic alert_en_shadowed_33_qs; + logic alert_en_shadowed_33_wd; + logic alert_en_shadowed_33_storage_err; + logic alert_en_shadowed_33_update_err; + logic alert_en_shadowed_34_re; + logic alert_en_shadowed_34_we; + logic alert_en_shadowed_34_qs; + logic alert_en_shadowed_34_wd; + logic alert_en_shadowed_34_storage_err; + logic alert_en_shadowed_34_update_err; + logic alert_en_shadowed_35_re; + logic alert_en_shadowed_35_we; + logic alert_en_shadowed_35_qs; + logic alert_en_shadowed_35_wd; + logic alert_en_shadowed_35_storage_err; + logic alert_en_shadowed_35_update_err; + logic alert_en_shadowed_36_re; + logic alert_en_shadowed_36_we; + logic alert_en_shadowed_36_qs; + logic alert_en_shadowed_36_wd; + logic alert_en_shadowed_36_storage_err; + logic alert_en_shadowed_36_update_err; + logic alert_en_shadowed_37_re; + logic alert_en_shadowed_37_we; + logic alert_en_shadowed_37_qs; + logic alert_en_shadowed_37_wd; + logic alert_en_shadowed_37_storage_err; + logic alert_en_shadowed_37_update_err; + logic alert_en_shadowed_38_re; + logic alert_en_shadowed_38_we; + logic alert_en_shadowed_38_qs; + logic alert_en_shadowed_38_wd; + logic alert_en_shadowed_38_storage_err; + logic alert_en_shadowed_38_update_err; + logic alert_en_shadowed_39_re; + logic alert_en_shadowed_39_we; + logic alert_en_shadowed_39_qs; + logic alert_en_shadowed_39_wd; + logic alert_en_shadowed_39_storage_err; + logic alert_en_shadowed_39_update_err; + logic alert_en_shadowed_40_re; + logic alert_en_shadowed_40_we; + logic alert_en_shadowed_40_qs; + logic alert_en_shadowed_40_wd; + logic alert_en_shadowed_40_storage_err; + logic alert_en_shadowed_40_update_err; + logic alert_en_shadowed_41_re; + logic alert_en_shadowed_41_we; + logic alert_en_shadowed_41_qs; + logic alert_en_shadowed_41_wd; + logic alert_en_shadowed_41_storage_err; + logic alert_en_shadowed_41_update_err; + logic alert_en_shadowed_42_re; + logic alert_en_shadowed_42_we; + logic alert_en_shadowed_42_qs; + logic alert_en_shadowed_42_wd; + logic alert_en_shadowed_42_storage_err; + logic alert_en_shadowed_42_update_err; + logic alert_en_shadowed_43_re; + logic alert_en_shadowed_43_we; + logic alert_en_shadowed_43_qs; + logic alert_en_shadowed_43_wd; + logic alert_en_shadowed_43_storage_err; + logic alert_en_shadowed_43_update_err; + logic alert_en_shadowed_44_re; + logic alert_en_shadowed_44_we; + logic alert_en_shadowed_44_qs; + logic alert_en_shadowed_44_wd; + logic alert_en_shadowed_44_storage_err; + logic alert_en_shadowed_44_update_err; + logic alert_en_shadowed_45_re; + logic alert_en_shadowed_45_we; + logic alert_en_shadowed_45_qs; + logic alert_en_shadowed_45_wd; + logic alert_en_shadowed_45_storage_err; + logic alert_en_shadowed_45_update_err; + logic alert_en_shadowed_46_re; + logic alert_en_shadowed_46_we; + logic alert_en_shadowed_46_qs; + logic alert_en_shadowed_46_wd; + logic alert_en_shadowed_46_storage_err; + logic alert_en_shadowed_46_update_err; + logic alert_en_shadowed_47_re; + logic alert_en_shadowed_47_we; + logic alert_en_shadowed_47_qs; + logic alert_en_shadowed_47_wd; + logic alert_en_shadowed_47_storage_err; + logic alert_en_shadowed_47_update_err; + logic alert_en_shadowed_48_re; + logic alert_en_shadowed_48_we; + logic alert_en_shadowed_48_qs; + logic alert_en_shadowed_48_wd; + logic alert_en_shadowed_48_storage_err; + logic alert_en_shadowed_48_update_err; + logic alert_en_shadowed_49_re; + logic alert_en_shadowed_49_we; + logic alert_en_shadowed_49_qs; + logic alert_en_shadowed_49_wd; + logic alert_en_shadowed_49_storage_err; + logic alert_en_shadowed_49_update_err; + logic alert_en_shadowed_50_re; + logic alert_en_shadowed_50_we; + logic alert_en_shadowed_50_qs; + logic alert_en_shadowed_50_wd; + logic alert_en_shadowed_50_storage_err; + logic alert_en_shadowed_50_update_err; + logic alert_en_shadowed_51_re; + logic alert_en_shadowed_51_we; + logic alert_en_shadowed_51_qs; + logic alert_en_shadowed_51_wd; + logic alert_en_shadowed_51_storage_err; + logic alert_en_shadowed_51_update_err; + logic alert_en_shadowed_52_re; + logic alert_en_shadowed_52_we; + logic alert_en_shadowed_52_qs; + logic alert_en_shadowed_52_wd; + logic alert_en_shadowed_52_storage_err; + logic alert_en_shadowed_52_update_err; + logic alert_en_shadowed_53_re; + logic alert_en_shadowed_53_we; + logic alert_en_shadowed_53_qs; + logic alert_en_shadowed_53_wd; + logic alert_en_shadowed_53_storage_err; + logic alert_en_shadowed_53_update_err; + logic alert_en_shadowed_54_re; + logic alert_en_shadowed_54_we; + logic alert_en_shadowed_54_qs; + logic alert_en_shadowed_54_wd; + logic alert_en_shadowed_54_storage_err; + logic alert_en_shadowed_54_update_err; + logic alert_en_shadowed_55_re; + logic alert_en_shadowed_55_we; + logic alert_en_shadowed_55_qs; + logic alert_en_shadowed_55_wd; + logic alert_en_shadowed_55_storage_err; + logic alert_en_shadowed_55_update_err; + logic alert_en_shadowed_56_re; + logic alert_en_shadowed_56_we; + logic alert_en_shadowed_56_qs; + logic alert_en_shadowed_56_wd; + logic alert_en_shadowed_56_storage_err; + logic alert_en_shadowed_56_update_err; + logic alert_en_shadowed_57_re; + logic alert_en_shadowed_57_we; + logic alert_en_shadowed_57_qs; + logic alert_en_shadowed_57_wd; + logic alert_en_shadowed_57_storage_err; + logic alert_en_shadowed_57_update_err; + logic alert_en_shadowed_58_re; + logic alert_en_shadowed_58_we; + logic alert_en_shadowed_58_qs; + logic alert_en_shadowed_58_wd; + logic alert_en_shadowed_58_storage_err; + logic alert_en_shadowed_58_update_err; + logic alert_en_shadowed_59_re; + logic alert_en_shadowed_59_we; + logic alert_en_shadowed_59_qs; + logic alert_en_shadowed_59_wd; + logic alert_en_shadowed_59_storage_err; + logic alert_en_shadowed_59_update_err; + logic alert_en_shadowed_60_re; + logic alert_en_shadowed_60_we; + logic alert_en_shadowed_60_qs; + logic alert_en_shadowed_60_wd; + logic alert_en_shadowed_60_storage_err; + logic alert_en_shadowed_60_update_err; + logic alert_en_shadowed_61_re; + logic alert_en_shadowed_61_we; + logic alert_en_shadowed_61_qs; + logic alert_en_shadowed_61_wd; + logic alert_en_shadowed_61_storage_err; + logic alert_en_shadowed_61_update_err; + logic alert_en_shadowed_62_re; + logic alert_en_shadowed_62_we; + logic alert_en_shadowed_62_qs; + logic alert_en_shadowed_62_wd; + logic alert_en_shadowed_62_storage_err; + logic alert_en_shadowed_62_update_err; + logic alert_en_shadowed_63_re; + logic alert_en_shadowed_63_we; + logic alert_en_shadowed_63_qs; + logic alert_en_shadowed_63_wd; + logic alert_en_shadowed_63_storage_err; + logic alert_en_shadowed_63_update_err; + logic alert_en_shadowed_64_re; + logic alert_en_shadowed_64_we; + logic alert_en_shadowed_64_qs; + logic alert_en_shadowed_64_wd; + logic alert_en_shadowed_64_storage_err; + logic alert_en_shadowed_64_update_err; + logic alert_en_shadowed_65_re; + logic alert_en_shadowed_65_we; + logic alert_en_shadowed_65_qs; + logic alert_en_shadowed_65_wd; + logic alert_en_shadowed_65_storage_err; + logic alert_en_shadowed_65_update_err; + logic alert_en_shadowed_66_re; + logic alert_en_shadowed_66_we; + logic alert_en_shadowed_66_qs; + logic alert_en_shadowed_66_wd; + logic alert_en_shadowed_66_storage_err; + logic alert_en_shadowed_66_update_err; + logic alert_en_shadowed_67_re; + logic alert_en_shadowed_67_we; + logic alert_en_shadowed_67_qs; + logic alert_en_shadowed_67_wd; + logic alert_en_shadowed_67_storage_err; + logic alert_en_shadowed_67_update_err; + logic alert_en_shadowed_68_re; + logic alert_en_shadowed_68_we; + logic alert_en_shadowed_68_qs; + logic alert_en_shadowed_68_wd; + logic alert_en_shadowed_68_storage_err; + logic alert_en_shadowed_68_update_err; + logic alert_en_shadowed_69_re; + logic alert_en_shadowed_69_we; + logic alert_en_shadowed_69_qs; + logic alert_en_shadowed_69_wd; + logic alert_en_shadowed_69_storage_err; + logic alert_en_shadowed_69_update_err; + logic alert_en_shadowed_70_re; + logic alert_en_shadowed_70_we; + logic alert_en_shadowed_70_qs; + logic alert_en_shadowed_70_wd; + logic alert_en_shadowed_70_storage_err; + logic alert_en_shadowed_70_update_err; + logic alert_en_shadowed_71_re; + logic alert_en_shadowed_71_we; + logic alert_en_shadowed_71_qs; + logic alert_en_shadowed_71_wd; + logic alert_en_shadowed_71_storage_err; + logic alert_en_shadowed_71_update_err; + logic alert_en_shadowed_72_re; + logic alert_en_shadowed_72_we; + logic alert_en_shadowed_72_qs; + logic alert_en_shadowed_72_wd; + logic alert_en_shadowed_72_storage_err; + logic alert_en_shadowed_72_update_err; + logic alert_en_shadowed_73_re; + logic alert_en_shadowed_73_we; + logic alert_en_shadowed_73_qs; + logic alert_en_shadowed_73_wd; + logic alert_en_shadowed_73_storage_err; + logic alert_en_shadowed_73_update_err; + logic alert_en_shadowed_74_re; + logic alert_en_shadowed_74_we; + logic alert_en_shadowed_74_qs; + logic alert_en_shadowed_74_wd; + logic alert_en_shadowed_74_storage_err; + logic alert_en_shadowed_74_update_err; + logic alert_en_shadowed_75_re; + logic alert_en_shadowed_75_we; + logic alert_en_shadowed_75_qs; + logic alert_en_shadowed_75_wd; + logic alert_en_shadowed_75_storage_err; + logic alert_en_shadowed_75_update_err; + logic alert_en_shadowed_76_re; + logic alert_en_shadowed_76_we; + logic alert_en_shadowed_76_qs; + logic alert_en_shadowed_76_wd; + logic alert_en_shadowed_76_storage_err; + logic alert_en_shadowed_76_update_err; + logic alert_en_shadowed_77_re; + logic alert_en_shadowed_77_we; + logic alert_en_shadowed_77_qs; + logic alert_en_shadowed_77_wd; + logic alert_en_shadowed_77_storage_err; + logic alert_en_shadowed_77_update_err; + logic alert_en_shadowed_78_re; + logic alert_en_shadowed_78_we; + logic alert_en_shadowed_78_qs; + logic alert_en_shadowed_78_wd; + logic alert_en_shadowed_78_storage_err; + logic alert_en_shadowed_78_update_err; + logic alert_en_shadowed_79_re; + logic alert_en_shadowed_79_we; + logic alert_en_shadowed_79_qs; + logic alert_en_shadowed_79_wd; + logic alert_en_shadowed_79_storage_err; + logic alert_en_shadowed_79_update_err; + logic alert_en_shadowed_80_re; + logic alert_en_shadowed_80_we; + logic alert_en_shadowed_80_qs; + logic alert_en_shadowed_80_wd; + logic alert_en_shadowed_80_storage_err; + logic alert_en_shadowed_80_update_err; + logic alert_en_shadowed_81_re; + logic alert_en_shadowed_81_we; + logic alert_en_shadowed_81_qs; + logic alert_en_shadowed_81_wd; + logic alert_en_shadowed_81_storage_err; + logic alert_en_shadowed_81_update_err; + logic alert_en_shadowed_82_re; + logic alert_en_shadowed_82_we; + logic alert_en_shadowed_82_qs; + logic alert_en_shadowed_82_wd; + logic alert_en_shadowed_82_storage_err; + logic alert_en_shadowed_82_update_err; + logic alert_en_shadowed_83_re; + logic alert_en_shadowed_83_we; + logic alert_en_shadowed_83_qs; + logic alert_en_shadowed_83_wd; + logic alert_en_shadowed_83_storage_err; + logic alert_en_shadowed_83_update_err; + logic alert_en_shadowed_84_re; + logic alert_en_shadowed_84_we; + logic alert_en_shadowed_84_qs; + logic alert_en_shadowed_84_wd; + logic alert_en_shadowed_84_storage_err; + logic alert_en_shadowed_84_update_err; + logic alert_en_shadowed_85_re; + logic alert_en_shadowed_85_we; + logic alert_en_shadowed_85_qs; + logic alert_en_shadowed_85_wd; + logic alert_en_shadowed_85_storage_err; + logic alert_en_shadowed_85_update_err; + logic alert_en_shadowed_86_re; + logic alert_en_shadowed_86_we; + logic alert_en_shadowed_86_qs; + logic alert_en_shadowed_86_wd; + logic alert_en_shadowed_86_storage_err; + logic alert_en_shadowed_86_update_err; + logic alert_en_shadowed_87_re; + logic alert_en_shadowed_87_we; + logic alert_en_shadowed_87_qs; + logic alert_en_shadowed_87_wd; + logic alert_en_shadowed_87_storage_err; + logic alert_en_shadowed_87_update_err; + logic alert_en_shadowed_88_re; + logic alert_en_shadowed_88_we; + logic alert_en_shadowed_88_qs; + logic alert_en_shadowed_88_wd; + logic alert_en_shadowed_88_storage_err; + logic alert_en_shadowed_88_update_err; + logic alert_en_shadowed_89_re; + logic alert_en_shadowed_89_we; + logic alert_en_shadowed_89_qs; + logic alert_en_shadowed_89_wd; + logic alert_en_shadowed_89_storage_err; + logic alert_en_shadowed_89_update_err; + logic alert_en_shadowed_90_re; + logic alert_en_shadowed_90_we; + logic alert_en_shadowed_90_qs; + logic alert_en_shadowed_90_wd; + logic alert_en_shadowed_90_storage_err; + logic alert_en_shadowed_90_update_err; + logic alert_en_shadowed_91_re; + logic alert_en_shadowed_91_we; + logic alert_en_shadowed_91_qs; + logic alert_en_shadowed_91_wd; + logic alert_en_shadowed_91_storage_err; + logic alert_en_shadowed_91_update_err; + logic alert_en_shadowed_92_re; + logic alert_en_shadowed_92_we; + logic alert_en_shadowed_92_qs; + logic alert_en_shadowed_92_wd; + logic alert_en_shadowed_92_storage_err; + logic alert_en_shadowed_92_update_err; + logic alert_en_shadowed_93_re; + logic alert_en_shadowed_93_we; + logic alert_en_shadowed_93_qs; + logic alert_en_shadowed_93_wd; + logic alert_en_shadowed_93_storage_err; + logic alert_en_shadowed_93_update_err; + logic alert_en_shadowed_94_re; + logic alert_en_shadowed_94_we; + logic alert_en_shadowed_94_qs; + logic alert_en_shadowed_94_wd; + logic alert_en_shadowed_94_storage_err; + logic alert_en_shadowed_94_update_err; + logic alert_en_shadowed_95_re; + logic alert_en_shadowed_95_we; + logic alert_en_shadowed_95_qs; + logic alert_en_shadowed_95_wd; + logic alert_en_shadowed_95_storage_err; + logic alert_en_shadowed_95_update_err; + logic alert_en_shadowed_96_re; + logic alert_en_shadowed_96_we; + logic alert_en_shadowed_96_qs; + logic alert_en_shadowed_96_wd; + logic alert_en_shadowed_96_storage_err; + logic alert_en_shadowed_96_update_err; + logic alert_en_shadowed_97_re; + logic alert_en_shadowed_97_we; + logic alert_en_shadowed_97_qs; + logic alert_en_shadowed_97_wd; + logic alert_en_shadowed_97_storage_err; + logic alert_en_shadowed_97_update_err; + logic alert_en_shadowed_98_re; + logic alert_en_shadowed_98_we; + logic alert_en_shadowed_98_qs; + logic alert_en_shadowed_98_wd; + logic alert_en_shadowed_98_storage_err; + logic alert_en_shadowed_98_update_err; + logic alert_class_shadowed_0_re; + logic alert_class_shadowed_0_we; + logic [1:0] alert_class_shadowed_0_qs; + logic [1:0] alert_class_shadowed_0_wd; + logic alert_class_shadowed_0_storage_err; + logic alert_class_shadowed_0_update_err; + logic alert_class_shadowed_1_re; + logic alert_class_shadowed_1_we; + logic [1:0] alert_class_shadowed_1_qs; + logic [1:0] alert_class_shadowed_1_wd; + logic alert_class_shadowed_1_storage_err; + logic alert_class_shadowed_1_update_err; + logic alert_class_shadowed_2_re; + logic alert_class_shadowed_2_we; + logic [1:0] alert_class_shadowed_2_qs; + logic [1:0] alert_class_shadowed_2_wd; + logic alert_class_shadowed_2_storage_err; + logic alert_class_shadowed_2_update_err; + logic alert_class_shadowed_3_re; + logic alert_class_shadowed_3_we; + logic [1:0] alert_class_shadowed_3_qs; + logic [1:0] alert_class_shadowed_3_wd; + logic alert_class_shadowed_3_storage_err; + logic alert_class_shadowed_3_update_err; + logic alert_class_shadowed_4_re; + logic alert_class_shadowed_4_we; + logic [1:0] alert_class_shadowed_4_qs; + logic [1:0] alert_class_shadowed_4_wd; + logic alert_class_shadowed_4_storage_err; + logic alert_class_shadowed_4_update_err; + logic alert_class_shadowed_5_re; + logic alert_class_shadowed_5_we; + logic [1:0] alert_class_shadowed_5_qs; + logic [1:0] alert_class_shadowed_5_wd; + logic alert_class_shadowed_5_storage_err; + logic alert_class_shadowed_5_update_err; + logic alert_class_shadowed_6_re; + logic alert_class_shadowed_6_we; + logic [1:0] alert_class_shadowed_6_qs; + logic [1:0] alert_class_shadowed_6_wd; + logic alert_class_shadowed_6_storage_err; + logic alert_class_shadowed_6_update_err; + logic alert_class_shadowed_7_re; + logic alert_class_shadowed_7_we; + logic [1:0] alert_class_shadowed_7_qs; + logic [1:0] alert_class_shadowed_7_wd; + logic alert_class_shadowed_7_storage_err; + logic alert_class_shadowed_7_update_err; + logic alert_class_shadowed_8_re; + logic alert_class_shadowed_8_we; + logic [1:0] alert_class_shadowed_8_qs; + logic [1:0] alert_class_shadowed_8_wd; + logic alert_class_shadowed_8_storage_err; + logic alert_class_shadowed_8_update_err; + logic alert_class_shadowed_9_re; + logic alert_class_shadowed_9_we; + logic [1:0] alert_class_shadowed_9_qs; + logic [1:0] alert_class_shadowed_9_wd; + logic alert_class_shadowed_9_storage_err; + logic alert_class_shadowed_9_update_err; + logic alert_class_shadowed_10_re; + logic alert_class_shadowed_10_we; + logic [1:0] alert_class_shadowed_10_qs; + logic [1:0] alert_class_shadowed_10_wd; + logic alert_class_shadowed_10_storage_err; + logic alert_class_shadowed_10_update_err; + logic alert_class_shadowed_11_re; + logic alert_class_shadowed_11_we; + logic [1:0] alert_class_shadowed_11_qs; + logic [1:0] alert_class_shadowed_11_wd; + logic alert_class_shadowed_11_storage_err; + logic alert_class_shadowed_11_update_err; + logic alert_class_shadowed_12_re; + logic alert_class_shadowed_12_we; + logic [1:0] alert_class_shadowed_12_qs; + logic [1:0] alert_class_shadowed_12_wd; + logic alert_class_shadowed_12_storage_err; + logic alert_class_shadowed_12_update_err; + logic alert_class_shadowed_13_re; + logic alert_class_shadowed_13_we; + logic [1:0] alert_class_shadowed_13_qs; + logic [1:0] alert_class_shadowed_13_wd; + logic alert_class_shadowed_13_storage_err; + logic alert_class_shadowed_13_update_err; + logic alert_class_shadowed_14_re; + logic alert_class_shadowed_14_we; + logic [1:0] alert_class_shadowed_14_qs; + logic [1:0] alert_class_shadowed_14_wd; + logic alert_class_shadowed_14_storage_err; + logic alert_class_shadowed_14_update_err; + logic alert_class_shadowed_15_re; + logic alert_class_shadowed_15_we; + logic [1:0] alert_class_shadowed_15_qs; + logic [1:0] alert_class_shadowed_15_wd; + logic alert_class_shadowed_15_storage_err; + logic alert_class_shadowed_15_update_err; + logic alert_class_shadowed_16_re; + logic alert_class_shadowed_16_we; + logic [1:0] alert_class_shadowed_16_qs; + logic [1:0] alert_class_shadowed_16_wd; + logic alert_class_shadowed_16_storage_err; + logic alert_class_shadowed_16_update_err; + logic alert_class_shadowed_17_re; + logic alert_class_shadowed_17_we; + logic [1:0] alert_class_shadowed_17_qs; + logic [1:0] alert_class_shadowed_17_wd; + logic alert_class_shadowed_17_storage_err; + logic alert_class_shadowed_17_update_err; + logic alert_class_shadowed_18_re; + logic alert_class_shadowed_18_we; + logic [1:0] alert_class_shadowed_18_qs; + logic [1:0] alert_class_shadowed_18_wd; + logic alert_class_shadowed_18_storage_err; + logic alert_class_shadowed_18_update_err; + logic alert_class_shadowed_19_re; + logic alert_class_shadowed_19_we; + logic [1:0] alert_class_shadowed_19_qs; + logic [1:0] alert_class_shadowed_19_wd; + logic alert_class_shadowed_19_storage_err; + logic alert_class_shadowed_19_update_err; + logic alert_class_shadowed_20_re; + logic alert_class_shadowed_20_we; + logic [1:0] alert_class_shadowed_20_qs; + logic [1:0] alert_class_shadowed_20_wd; + logic alert_class_shadowed_20_storage_err; + logic alert_class_shadowed_20_update_err; + logic alert_class_shadowed_21_re; + logic alert_class_shadowed_21_we; + logic [1:0] alert_class_shadowed_21_qs; + logic [1:0] alert_class_shadowed_21_wd; + logic alert_class_shadowed_21_storage_err; + logic alert_class_shadowed_21_update_err; + logic alert_class_shadowed_22_re; + logic alert_class_shadowed_22_we; + logic [1:0] alert_class_shadowed_22_qs; + logic [1:0] alert_class_shadowed_22_wd; + logic alert_class_shadowed_22_storage_err; + logic alert_class_shadowed_22_update_err; + logic alert_class_shadowed_23_re; + logic alert_class_shadowed_23_we; + logic [1:0] alert_class_shadowed_23_qs; + logic [1:0] alert_class_shadowed_23_wd; + logic alert_class_shadowed_23_storage_err; + logic alert_class_shadowed_23_update_err; + logic alert_class_shadowed_24_re; + logic alert_class_shadowed_24_we; + logic [1:0] alert_class_shadowed_24_qs; + logic [1:0] alert_class_shadowed_24_wd; + logic alert_class_shadowed_24_storage_err; + logic alert_class_shadowed_24_update_err; + logic alert_class_shadowed_25_re; + logic alert_class_shadowed_25_we; + logic [1:0] alert_class_shadowed_25_qs; + logic [1:0] alert_class_shadowed_25_wd; + logic alert_class_shadowed_25_storage_err; + logic alert_class_shadowed_25_update_err; + logic alert_class_shadowed_26_re; + logic alert_class_shadowed_26_we; + logic [1:0] alert_class_shadowed_26_qs; + logic [1:0] alert_class_shadowed_26_wd; + logic alert_class_shadowed_26_storage_err; + logic alert_class_shadowed_26_update_err; + logic alert_class_shadowed_27_re; + logic alert_class_shadowed_27_we; + logic [1:0] alert_class_shadowed_27_qs; + logic [1:0] alert_class_shadowed_27_wd; + logic alert_class_shadowed_27_storage_err; + logic alert_class_shadowed_27_update_err; + logic alert_class_shadowed_28_re; + logic alert_class_shadowed_28_we; + logic [1:0] alert_class_shadowed_28_qs; + logic [1:0] alert_class_shadowed_28_wd; + logic alert_class_shadowed_28_storage_err; + logic alert_class_shadowed_28_update_err; + logic alert_class_shadowed_29_re; + logic alert_class_shadowed_29_we; + logic [1:0] alert_class_shadowed_29_qs; + logic [1:0] alert_class_shadowed_29_wd; + logic alert_class_shadowed_29_storage_err; + logic alert_class_shadowed_29_update_err; + logic alert_class_shadowed_30_re; + logic alert_class_shadowed_30_we; + logic [1:0] alert_class_shadowed_30_qs; + logic [1:0] alert_class_shadowed_30_wd; + logic alert_class_shadowed_30_storage_err; + logic alert_class_shadowed_30_update_err; + logic alert_class_shadowed_31_re; + logic alert_class_shadowed_31_we; + logic [1:0] alert_class_shadowed_31_qs; + logic [1:0] alert_class_shadowed_31_wd; + logic alert_class_shadowed_31_storage_err; + logic alert_class_shadowed_31_update_err; + logic alert_class_shadowed_32_re; + logic alert_class_shadowed_32_we; + logic [1:0] alert_class_shadowed_32_qs; + logic [1:0] alert_class_shadowed_32_wd; + logic alert_class_shadowed_32_storage_err; + logic alert_class_shadowed_32_update_err; + logic alert_class_shadowed_33_re; + logic alert_class_shadowed_33_we; + logic [1:0] alert_class_shadowed_33_qs; + logic [1:0] alert_class_shadowed_33_wd; + logic alert_class_shadowed_33_storage_err; + logic alert_class_shadowed_33_update_err; + logic alert_class_shadowed_34_re; + logic alert_class_shadowed_34_we; + logic [1:0] alert_class_shadowed_34_qs; + logic [1:0] alert_class_shadowed_34_wd; + logic alert_class_shadowed_34_storage_err; + logic alert_class_shadowed_34_update_err; + logic alert_class_shadowed_35_re; + logic alert_class_shadowed_35_we; + logic [1:0] alert_class_shadowed_35_qs; + logic [1:0] alert_class_shadowed_35_wd; + logic alert_class_shadowed_35_storage_err; + logic alert_class_shadowed_35_update_err; + logic alert_class_shadowed_36_re; + logic alert_class_shadowed_36_we; + logic [1:0] alert_class_shadowed_36_qs; + logic [1:0] alert_class_shadowed_36_wd; + logic alert_class_shadowed_36_storage_err; + logic alert_class_shadowed_36_update_err; + logic alert_class_shadowed_37_re; + logic alert_class_shadowed_37_we; + logic [1:0] alert_class_shadowed_37_qs; + logic [1:0] alert_class_shadowed_37_wd; + logic alert_class_shadowed_37_storage_err; + logic alert_class_shadowed_37_update_err; + logic alert_class_shadowed_38_re; + logic alert_class_shadowed_38_we; + logic [1:0] alert_class_shadowed_38_qs; + logic [1:0] alert_class_shadowed_38_wd; + logic alert_class_shadowed_38_storage_err; + logic alert_class_shadowed_38_update_err; + logic alert_class_shadowed_39_re; + logic alert_class_shadowed_39_we; + logic [1:0] alert_class_shadowed_39_qs; + logic [1:0] alert_class_shadowed_39_wd; + logic alert_class_shadowed_39_storage_err; + logic alert_class_shadowed_39_update_err; + logic alert_class_shadowed_40_re; + logic alert_class_shadowed_40_we; + logic [1:0] alert_class_shadowed_40_qs; + logic [1:0] alert_class_shadowed_40_wd; + logic alert_class_shadowed_40_storage_err; + logic alert_class_shadowed_40_update_err; + logic alert_class_shadowed_41_re; + logic alert_class_shadowed_41_we; + logic [1:0] alert_class_shadowed_41_qs; + logic [1:0] alert_class_shadowed_41_wd; + logic alert_class_shadowed_41_storage_err; + logic alert_class_shadowed_41_update_err; + logic alert_class_shadowed_42_re; + logic alert_class_shadowed_42_we; + logic [1:0] alert_class_shadowed_42_qs; + logic [1:0] alert_class_shadowed_42_wd; + logic alert_class_shadowed_42_storage_err; + logic alert_class_shadowed_42_update_err; + logic alert_class_shadowed_43_re; + logic alert_class_shadowed_43_we; + logic [1:0] alert_class_shadowed_43_qs; + logic [1:0] alert_class_shadowed_43_wd; + logic alert_class_shadowed_43_storage_err; + logic alert_class_shadowed_43_update_err; + logic alert_class_shadowed_44_re; + logic alert_class_shadowed_44_we; + logic [1:0] alert_class_shadowed_44_qs; + logic [1:0] alert_class_shadowed_44_wd; + logic alert_class_shadowed_44_storage_err; + logic alert_class_shadowed_44_update_err; + logic alert_class_shadowed_45_re; + logic alert_class_shadowed_45_we; + logic [1:0] alert_class_shadowed_45_qs; + logic [1:0] alert_class_shadowed_45_wd; + logic alert_class_shadowed_45_storage_err; + logic alert_class_shadowed_45_update_err; + logic alert_class_shadowed_46_re; + logic alert_class_shadowed_46_we; + logic [1:0] alert_class_shadowed_46_qs; + logic [1:0] alert_class_shadowed_46_wd; + logic alert_class_shadowed_46_storage_err; + logic alert_class_shadowed_46_update_err; + logic alert_class_shadowed_47_re; + logic alert_class_shadowed_47_we; + logic [1:0] alert_class_shadowed_47_qs; + logic [1:0] alert_class_shadowed_47_wd; + logic alert_class_shadowed_47_storage_err; + logic alert_class_shadowed_47_update_err; + logic alert_class_shadowed_48_re; + logic alert_class_shadowed_48_we; + logic [1:0] alert_class_shadowed_48_qs; + logic [1:0] alert_class_shadowed_48_wd; + logic alert_class_shadowed_48_storage_err; + logic alert_class_shadowed_48_update_err; + logic alert_class_shadowed_49_re; + logic alert_class_shadowed_49_we; + logic [1:0] alert_class_shadowed_49_qs; + logic [1:0] alert_class_shadowed_49_wd; + logic alert_class_shadowed_49_storage_err; + logic alert_class_shadowed_49_update_err; + logic alert_class_shadowed_50_re; + logic alert_class_shadowed_50_we; + logic [1:0] alert_class_shadowed_50_qs; + logic [1:0] alert_class_shadowed_50_wd; + logic alert_class_shadowed_50_storage_err; + logic alert_class_shadowed_50_update_err; + logic alert_class_shadowed_51_re; + logic alert_class_shadowed_51_we; + logic [1:0] alert_class_shadowed_51_qs; + logic [1:0] alert_class_shadowed_51_wd; + logic alert_class_shadowed_51_storage_err; + logic alert_class_shadowed_51_update_err; + logic alert_class_shadowed_52_re; + logic alert_class_shadowed_52_we; + logic [1:0] alert_class_shadowed_52_qs; + logic [1:0] alert_class_shadowed_52_wd; + logic alert_class_shadowed_52_storage_err; + logic alert_class_shadowed_52_update_err; + logic alert_class_shadowed_53_re; + logic alert_class_shadowed_53_we; + logic [1:0] alert_class_shadowed_53_qs; + logic [1:0] alert_class_shadowed_53_wd; + logic alert_class_shadowed_53_storage_err; + logic alert_class_shadowed_53_update_err; + logic alert_class_shadowed_54_re; + logic alert_class_shadowed_54_we; + logic [1:0] alert_class_shadowed_54_qs; + logic [1:0] alert_class_shadowed_54_wd; + logic alert_class_shadowed_54_storage_err; + logic alert_class_shadowed_54_update_err; + logic alert_class_shadowed_55_re; + logic alert_class_shadowed_55_we; + logic [1:0] alert_class_shadowed_55_qs; + logic [1:0] alert_class_shadowed_55_wd; + logic alert_class_shadowed_55_storage_err; + logic alert_class_shadowed_55_update_err; + logic alert_class_shadowed_56_re; + logic alert_class_shadowed_56_we; + logic [1:0] alert_class_shadowed_56_qs; + logic [1:0] alert_class_shadowed_56_wd; + logic alert_class_shadowed_56_storage_err; + logic alert_class_shadowed_56_update_err; + logic alert_class_shadowed_57_re; + logic alert_class_shadowed_57_we; + logic [1:0] alert_class_shadowed_57_qs; + logic [1:0] alert_class_shadowed_57_wd; + logic alert_class_shadowed_57_storage_err; + logic alert_class_shadowed_57_update_err; + logic alert_class_shadowed_58_re; + logic alert_class_shadowed_58_we; + logic [1:0] alert_class_shadowed_58_qs; + logic [1:0] alert_class_shadowed_58_wd; + logic alert_class_shadowed_58_storage_err; + logic alert_class_shadowed_58_update_err; + logic alert_class_shadowed_59_re; + logic alert_class_shadowed_59_we; + logic [1:0] alert_class_shadowed_59_qs; + logic [1:0] alert_class_shadowed_59_wd; + logic alert_class_shadowed_59_storage_err; + logic alert_class_shadowed_59_update_err; + logic alert_class_shadowed_60_re; + logic alert_class_shadowed_60_we; + logic [1:0] alert_class_shadowed_60_qs; + logic [1:0] alert_class_shadowed_60_wd; + logic alert_class_shadowed_60_storage_err; + logic alert_class_shadowed_60_update_err; + logic alert_class_shadowed_61_re; + logic alert_class_shadowed_61_we; + logic [1:0] alert_class_shadowed_61_qs; + logic [1:0] alert_class_shadowed_61_wd; + logic alert_class_shadowed_61_storage_err; + logic alert_class_shadowed_61_update_err; + logic alert_class_shadowed_62_re; + logic alert_class_shadowed_62_we; + logic [1:0] alert_class_shadowed_62_qs; + logic [1:0] alert_class_shadowed_62_wd; + logic alert_class_shadowed_62_storage_err; + logic alert_class_shadowed_62_update_err; + logic alert_class_shadowed_63_re; + logic alert_class_shadowed_63_we; + logic [1:0] alert_class_shadowed_63_qs; + logic [1:0] alert_class_shadowed_63_wd; + logic alert_class_shadowed_63_storage_err; + logic alert_class_shadowed_63_update_err; + logic alert_class_shadowed_64_re; + logic alert_class_shadowed_64_we; + logic [1:0] alert_class_shadowed_64_qs; + logic [1:0] alert_class_shadowed_64_wd; + logic alert_class_shadowed_64_storage_err; + logic alert_class_shadowed_64_update_err; + logic alert_class_shadowed_65_re; + logic alert_class_shadowed_65_we; + logic [1:0] alert_class_shadowed_65_qs; + logic [1:0] alert_class_shadowed_65_wd; + logic alert_class_shadowed_65_storage_err; + logic alert_class_shadowed_65_update_err; + logic alert_class_shadowed_66_re; + logic alert_class_shadowed_66_we; + logic [1:0] alert_class_shadowed_66_qs; + logic [1:0] alert_class_shadowed_66_wd; + logic alert_class_shadowed_66_storage_err; + logic alert_class_shadowed_66_update_err; + logic alert_class_shadowed_67_re; + logic alert_class_shadowed_67_we; + logic [1:0] alert_class_shadowed_67_qs; + logic [1:0] alert_class_shadowed_67_wd; + logic alert_class_shadowed_67_storage_err; + logic alert_class_shadowed_67_update_err; + logic alert_class_shadowed_68_re; + logic alert_class_shadowed_68_we; + logic [1:0] alert_class_shadowed_68_qs; + logic [1:0] alert_class_shadowed_68_wd; + logic alert_class_shadowed_68_storage_err; + logic alert_class_shadowed_68_update_err; + logic alert_class_shadowed_69_re; + logic alert_class_shadowed_69_we; + logic [1:0] alert_class_shadowed_69_qs; + logic [1:0] alert_class_shadowed_69_wd; + logic alert_class_shadowed_69_storage_err; + logic alert_class_shadowed_69_update_err; + logic alert_class_shadowed_70_re; + logic alert_class_shadowed_70_we; + logic [1:0] alert_class_shadowed_70_qs; + logic [1:0] alert_class_shadowed_70_wd; + logic alert_class_shadowed_70_storage_err; + logic alert_class_shadowed_70_update_err; + logic alert_class_shadowed_71_re; + logic alert_class_shadowed_71_we; + logic [1:0] alert_class_shadowed_71_qs; + logic [1:0] alert_class_shadowed_71_wd; + logic alert_class_shadowed_71_storage_err; + logic alert_class_shadowed_71_update_err; + logic alert_class_shadowed_72_re; + logic alert_class_shadowed_72_we; + logic [1:0] alert_class_shadowed_72_qs; + logic [1:0] alert_class_shadowed_72_wd; + logic alert_class_shadowed_72_storage_err; + logic alert_class_shadowed_72_update_err; + logic alert_class_shadowed_73_re; + logic alert_class_shadowed_73_we; + logic [1:0] alert_class_shadowed_73_qs; + logic [1:0] alert_class_shadowed_73_wd; + logic alert_class_shadowed_73_storage_err; + logic alert_class_shadowed_73_update_err; + logic alert_class_shadowed_74_re; + logic alert_class_shadowed_74_we; + logic [1:0] alert_class_shadowed_74_qs; + logic [1:0] alert_class_shadowed_74_wd; + logic alert_class_shadowed_74_storage_err; + logic alert_class_shadowed_74_update_err; + logic alert_class_shadowed_75_re; + logic alert_class_shadowed_75_we; + logic [1:0] alert_class_shadowed_75_qs; + logic [1:0] alert_class_shadowed_75_wd; + logic alert_class_shadowed_75_storage_err; + logic alert_class_shadowed_75_update_err; + logic alert_class_shadowed_76_re; + logic alert_class_shadowed_76_we; + logic [1:0] alert_class_shadowed_76_qs; + logic [1:0] alert_class_shadowed_76_wd; + logic alert_class_shadowed_76_storage_err; + logic alert_class_shadowed_76_update_err; + logic alert_class_shadowed_77_re; + logic alert_class_shadowed_77_we; + logic [1:0] alert_class_shadowed_77_qs; + logic [1:0] alert_class_shadowed_77_wd; + logic alert_class_shadowed_77_storage_err; + logic alert_class_shadowed_77_update_err; + logic alert_class_shadowed_78_re; + logic alert_class_shadowed_78_we; + logic [1:0] alert_class_shadowed_78_qs; + logic [1:0] alert_class_shadowed_78_wd; + logic alert_class_shadowed_78_storage_err; + logic alert_class_shadowed_78_update_err; + logic alert_class_shadowed_79_re; + logic alert_class_shadowed_79_we; + logic [1:0] alert_class_shadowed_79_qs; + logic [1:0] alert_class_shadowed_79_wd; + logic alert_class_shadowed_79_storage_err; + logic alert_class_shadowed_79_update_err; + logic alert_class_shadowed_80_re; + logic alert_class_shadowed_80_we; + logic [1:0] alert_class_shadowed_80_qs; + logic [1:0] alert_class_shadowed_80_wd; + logic alert_class_shadowed_80_storage_err; + logic alert_class_shadowed_80_update_err; + logic alert_class_shadowed_81_re; + logic alert_class_shadowed_81_we; + logic [1:0] alert_class_shadowed_81_qs; + logic [1:0] alert_class_shadowed_81_wd; + logic alert_class_shadowed_81_storage_err; + logic alert_class_shadowed_81_update_err; + logic alert_class_shadowed_82_re; + logic alert_class_shadowed_82_we; + logic [1:0] alert_class_shadowed_82_qs; + logic [1:0] alert_class_shadowed_82_wd; + logic alert_class_shadowed_82_storage_err; + logic alert_class_shadowed_82_update_err; + logic alert_class_shadowed_83_re; + logic alert_class_shadowed_83_we; + logic [1:0] alert_class_shadowed_83_qs; + logic [1:0] alert_class_shadowed_83_wd; + logic alert_class_shadowed_83_storage_err; + logic alert_class_shadowed_83_update_err; + logic alert_class_shadowed_84_re; + logic alert_class_shadowed_84_we; + logic [1:0] alert_class_shadowed_84_qs; + logic [1:0] alert_class_shadowed_84_wd; + logic alert_class_shadowed_84_storage_err; + logic alert_class_shadowed_84_update_err; + logic alert_class_shadowed_85_re; + logic alert_class_shadowed_85_we; + logic [1:0] alert_class_shadowed_85_qs; + logic [1:0] alert_class_shadowed_85_wd; + logic alert_class_shadowed_85_storage_err; + logic alert_class_shadowed_85_update_err; + logic alert_class_shadowed_86_re; + logic alert_class_shadowed_86_we; + logic [1:0] alert_class_shadowed_86_qs; + logic [1:0] alert_class_shadowed_86_wd; + logic alert_class_shadowed_86_storage_err; + logic alert_class_shadowed_86_update_err; + logic alert_class_shadowed_87_re; + logic alert_class_shadowed_87_we; + logic [1:0] alert_class_shadowed_87_qs; + logic [1:0] alert_class_shadowed_87_wd; + logic alert_class_shadowed_87_storage_err; + logic alert_class_shadowed_87_update_err; + logic alert_class_shadowed_88_re; + logic alert_class_shadowed_88_we; + logic [1:0] alert_class_shadowed_88_qs; + logic [1:0] alert_class_shadowed_88_wd; + logic alert_class_shadowed_88_storage_err; + logic alert_class_shadowed_88_update_err; + logic alert_class_shadowed_89_re; + logic alert_class_shadowed_89_we; + logic [1:0] alert_class_shadowed_89_qs; + logic [1:0] alert_class_shadowed_89_wd; + logic alert_class_shadowed_89_storage_err; + logic alert_class_shadowed_89_update_err; + logic alert_class_shadowed_90_re; + logic alert_class_shadowed_90_we; + logic [1:0] alert_class_shadowed_90_qs; + logic [1:0] alert_class_shadowed_90_wd; + logic alert_class_shadowed_90_storage_err; + logic alert_class_shadowed_90_update_err; + logic alert_class_shadowed_91_re; + logic alert_class_shadowed_91_we; + logic [1:0] alert_class_shadowed_91_qs; + logic [1:0] alert_class_shadowed_91_wd; + logic alert_class_shadowed_91_storage_err; + logic alert_class_shadowed_91_update_err; + logic alert_class_shadowed_92_re; + logic alert_class_shadowed_92_we; + logic [1:0] alert_class_shadowed_92_qs; + logic [1:0] alert_class_shadowed_92_wd; + logic alert_class_shadowed_92_storage_err; + logic alert_class_shadowed_92_update_err; + logic alert_class_shadowed_93_re; + logic alert_class_shadowed_93_we; + logic [1:0] alert_class_shadowed_93_qs; + logic [1:0] alert_class_shadowed_93_wd; + logic alert_class_shadowed_93_storage_err; + logic alert_class_shadowed_93_update_err; + logic alert_class_shadowed_94_re; + logic alert_class_shadowed_94_we; + logic [1:0] alert_class_shadowed_94_qs; + logic [1:0] alert_class_shadowed_94_wd; + logic alert_class_shadowed_94_storage_err; + logic alert_class_shadowed_94_update_err; + logic alert_class_shadowed_95_re; + logic alert_class_shadowed_95_we; + logic [1:0] alert_class_shadowed_95_qs; + logic [1:0] alert_class_shadowed_95_wd; + logic alert_class_shadowed_95_storage_err; + logic alert_class_shadowed_95_update_err; + logic alert_class_shadowed_96_re; + logic alert_class_shadowed_96_we; + logic [1:0] alert_class_shadowed_96_qs; + logic [1:0] alert_class_shadowed_96_wd; + logic alert_class_shadowed_96_storage_err; + logic alert_class_shadowed_96_update_err; + logic alert_class_shadowed_97_re; + logic alert_class_shadowed_97_we; + logic [1:0] alert_class_shadowed_97_qs; + logic [1:0] alert_class_shadowed_97_wd; + logic alert_class_shadowed_97_storage_err; + logic alert_class_shadowed_97_update_err; + logic alert_class_shadowed_98_re; + logic alert_class_shadowed_98_we; + logic [1:0] alert_class_shadowed_98_qs; + logic [1:0] alert_class_shadowed_98_wd; + logic alert_class_shadowed_98_storage_err; + logic alert_class_shadowed_98_update_err; + logic alert_cause_0_we; + logic alert_cause_0_qs; + logic alert_cause_0_wd; + logic alert_cause_1_we; + logic alert_cause_1_qs; + logic alert_cause_1_wd; + logic alert_cause_2_we; + logic alert_cause_2_qs; + logic alert_cause_2_wd; + logic alert_cause_3_we; + logic alert_cause_3_qs; + logic alert_cause_3_wd; + logic alert_cause_4_we; + logic alert_cause_4_qs; + logic alert_cause_4_wd; + logic alert_cause_5_we; + logic alert_cause_5_qs; + logic alert_cause_5_wd; + logic alert_cause_6_we; + logic alert_cause_6_qs; + logic alert_cause_6_wd; + logic alert_cause_7_we; + logic alert_cause_7_qs; + logic alert_cause_7_wd; + logic alert_cause_8_we; + logic alert_cause_8_qs; + logic alert_cause_8_wd; + logic alert_cause_9_we; + logic alert_cause_9_qs; + logic alert_cause_9_wd; + logic alert_cause_10_we; + logic alert_cause_10_qs; + logic alert_cause_10_wd; + logic alert_cause_11_we; + logic alert_cause_11_qs; + logic alert_cause_11_wd; + logic alert_cause_12_we; + logic alert_cause_12_qs; + logic alert_cause_12_wd; + logic alert_cause_13_we; + logic alert_cause_13_qs; + logic alert_cause_13_wd; + logic alert_cause_14_we; + logic alert_cause_14_qs; + logic alert_cause_14_wd; + logic alert_cause_15_we; + logic alert_cause_15_qs; + logic alert_cause_15_wd; + logic alert_cause_16_we; + logic alert_cause_16_qs; + logic alert_cause_16_wd; + logic alert_cause_17_we; + logic alert_cause_17_qs; + logic alert_cause_17_wd; + logic alert_cause_18_we; + logic alert_cause_18_qs; + logic alert_cause_18_wd; + logic alert_cause_19_we; + logic alert_cause_19_qs; + logic alert_cause_19_wd; + logic alert_cause_20_we; + logic alert_cause_20_qs; + logic alert_cause_20_wd; + logic alert_cause_21_we; + logic alert_cause_21_qs; + logic alert_cause_21_wd; + logic alert_cause_22_we; + logic alert_cause_22_qs; + logic alert_cause_22_wd; + logic alert_cause_23_we; + logic alert_cause_23_qs; + logic alert_cause_23_wd; + logic alert_cause_24_we; + logic alert_cause_24_qs; + logic alert_cause_24_wd; + logic alert_cause_25_we; + logic alert_cause_25_qs; + logic alert_cause_25_wd; + logic alert_cause_26_we; + logic alert_cause_26_qs; + logic alert_cause_26_wd; + logic alert_cause_27_we; + logic alert_cause_27_qs; + logic alert_cause_27_wd; + logic alert_cause_28_we; + logic alert_cause_28_qs; + logic alert_cause_28_wd; + logic alert_cause_29_we; + logic alert_cause_29_qs; + logic alert_cause_29_wd; + logic alert_cause_30_we; + logic alert_cause_30_qs; + logic alert_cause_30_wd; + logic alert_cause_31_we; + logic alert_cause_31_qs; + logic alert_cause_31_wd; + logic alert_cause_32_we; + logic alert_cause_32_qs; + logic alert_cause_32_wd; + logic alert_cause_33_we; + logic alert_cause_33_qs; + logic alert_cause_33_wd; + logic alert_cause_34_we; + logic alert_cause_34_qs; + logic alert_cause_34_wd; + logic alert_cause_35_we; + logic alert_cause_35_qs; + logic alert_cause_35_wd; + logic alert_cause_36_we; + logic alert_cause_36_qs; + logic alert_cause_36_wd; + logic alert_cause_37_we; + logic alert_cause_37_qs; + logic alert_cause_37_wd; + logic alert_cause_38_we; + logic alert_cause_38_qs; + logic alert_cause_38_wd; + logic alert_cause_39_we; + logic alert_cause_39_qs; + logic alert_cause_39_wd; + logic alert_cause_40_we; + logic alert_cause_40_qs; + logic alert_cause_40_wd; + logic alert_cause_41_we; + logic alert_cause_41_qs; + logic alert_cause_41_wd; + logic alert_cause_42_we; + logic alert_cause_42_qs; + logic alert_cause_42_wd; + logic alert_cause_43_we; + logic alert_cause_43_qs; + logic alert_cause_43_wd; + logic alert_cause_44_we; + logic alert_cause_44_qs; + logic alert_cause_44_wd; + logic alert_cause_45_we; + logic alert_cause_45_qs; + logic alert_cause_45_wd; + logic alert_cause_46_we; + logic alert_cause_46_qs; + logic alert_cause_46_wd; + logic alert_cause_47_we; + logic alert_cause_47_qs; + logic alert_cause_47_wd; + logic alert_cause_48_we; + logic alert_cause_48_qs; + logic alert_cause_48_wd; + logic alert_cause_49_we; + logic alert_cause_49_qs; + logic alert_cause_49_wd; + logic alert_cause_50_we; + logic alert_cause_50_qs; + logic alert_cause_50_wd; + logic alert_cause_51_we; + logic alert_cause_51_qs; + logic alert_cause_51_wd; + logic alert_cause_52_we; + logic alert_cause_52_qs; + logic alert_cause_52_wd; + logic alert_cause_53_we; + logic alert_cause_53_qs; + logic alert_cause_53_wd; + logic alert_cause_54_we; + logic alert_cause_54_qs; + logic alert_cause_54_wd; + logic alert_cause_55_we; + logic alert_cause_55_qs; + logic alert_cause_55_wd; + logic alert_cause_56_we; + logic alert_cause_56_qs; + logic alert_cause_56_wd; + logic alert_cause_57_we; + logic alert_cause_57_qs; + logic alert_cause_57_wd; + logic alert_cause_58_we; + logic alert_cause_58_qs; + logic alert_cause_58_wd; + logic alert_cause_59_we; + logic alert_cause_59_qs; + logic alert_cause_59_wd; + logic alert_cause_60_we; + logic alert_cause_60_qs; + logic alert_cause_60_wd; + logic alert_cause_61_we; + logic alert_cause_61_qs; + logic alert_cause_61_wd; + logic alert_cause_62_we; + logic alert_cause_62_qs; + logic alert_cause_62_wd; + logic alert_cause_63_we; + logic alert_cause_63_qs; + logic alert_cause_63_wd; + logic alert_cause_64_we; + logic alert_cause_64_qs; + logic alert_cause_64_wd; + logic alert_cause_65_we; + logic alert_cause_65_qs; + logic alert_cause_65_wd; + logic alert_cause_66_we; + logic alert_cause_66_qs; + logic alert_cause_66_wd; + logic alert_cause_67_we; + logic alert_cause_67_qs; + logic alert_cause_67_wd; + logic alert_cause_68_we; + logic alert_cause_68_qs; + logic alert_cause_68_wd; + logic alert_cause_69_we; + logic alert_cause_69_qs; + logic alert_cause_69_wd; + logic alert_cause_70_we; + logic alert_cause_70_qs; + logic alert_cause_70_wd; + logic alert_cause_71_we; + logic alert_cause_71_qs; + logic alert_cause_71_wd; + logic alert_cause_72_we; + logic alert_cause_72_qs; + logic alert_cause_72_wd; + logic alert_cause_73_we; + logic alert_cause_73_qs; + logic alert_cause_73_wd; + logic alert_cause_74_we; + logic alert_cause_74_qs; + logic alert_cause_74_wd; + logic alert_cause_75_we; + logic alert_cause_75_qs; + logic alert_cause_75_wd; + logic alert_cause_76_we; + logic alert_cause_76_qs; + logic alert_cause_76_wd; + logic alert_cause_77_we; + logic alert_cause_77_qs; + logic alert_cause_77_wd; + logic alert_cause_78_we; + logic alert_cause_78_qs; + logic alert_cause_78_wd; + logic alert_cause_79_we; + logic alert_cause_79_qs; + logic alert_cause_79_wd; + logic alert_cause_80_we; + logic alert_cause_80_qs; + logic alert_cause_80_wd; + logic alert_cause_81_we; + logic alert_cause_81_qs; + logic alert_cause_81_wd; + logic alert_cause_82_we; + logic alert_cause_82_qs; + logic alert_cause_82_wd; + logic alert_cause_83_we; + logic alert_cause_83_qs; + logic alert_cause_83_wd; + logic alert_cause_84_we; + logic alert_cause_84_qs; + logic alert_cause_84_wd; + logic alert_cause_85_we; + logic alert_cause_85_qs; + logic alert_cause_85_wd; + logic alert_cause_86_we; + logic alert_cause_86_qs; + logic alert_cause_86_wd; + logic alert_cause_87_we; + logic alert_cause_87_qs; + logic alert_cause_87_wd; + logic alert_cause_88_we; + logic alert_cause_88_qs; + logic alert_cause_88_wd; + logic alert_cause_89_we; + logic alert_cause_89_qs; + logic alert_cause_89_wd; + logic alert_cause_90_we; + logic alert_cause_90_qs; + logic alert_cause_90_wd; + logic alert_cause_91_we; + logic alert_cause_91_qs; + logic alert_cause_91_wd; + logic alert_cause_92_we; + logic alert_cause_92_qs; + logic alert_cause_92_wd; + logic alert_cause_93_we; + logic alert_cause_93_qs; + logic alert_cause_93_wd; + logic alert_cause_94_we; + logic alert_cause_94_qs; + logic alert_cause_94_wd; + logic alert_cause_95_we; + logic alert_cause_95_qs; + logic alert_cause_95_wd; + logic alert_cause_96_we; + logic alert_cause_96_qs; + logic alert_cause_96_wd; + logic alert_cause_97_we; + logic alert_cause_97_qs; + logic alert_cause_97_wd; + logic alert_cause_98_we; + logic alert_cause_98_qs; + logic alert_cause_98_wd; + logic loc_alert_regwen_0_we; + logic loc_alert_regwen_0_qs; + logic loc_alert_regwen_0_wd; + logic loc_alert_regwen_1_we; + logic loc_alert_regwen_1_qs; + logic loc_alert_regwen_1_wd; + logic loc_alert_regwen_2_we; + logic loc_alert_regwen_2_qs; + logic loc_alert_regwen_2_wd; + logic loc_alert_regwen_3_we; + logic loc_alert_regwen_3_qs; + logic loc_alert_regwen_3_wd; + logic loc_alert_regwen_4_we; + logic loc_alert_regwen_4_qs; + logic loc_alert_regwen_4_wd; + logic loc_alert_regwen_5_we; + logic loc_alert_regwen_5_qs; + logic loc_alert_regwen_5_wd; + logic loc_alert_regwen_6_we; + logic loc_alert_regwen_6_qs; + logic loc_alert_regwen_6_wd; + logic loc_alert_en_shadowed_0_re; + logic loc_alert_en_shadowed_0_we; + logic loc_alert_en_shadowed_0_qs; + logic loc_alert_en_shadowed_0_wd; + logic loc_alert_en_shadowed_0_storage_err; + logic loc_alert_en_shadowed_0_update_err; + logic loc_alert_en_shadowed_1_re; + logic loc_alert_en_shadowed_1_we; + logic loc_alert_en_shadowed_1_qs; + logic loc_alert_en_shadowed_1_wd; + logic loc_alert_en_shadowed_1_storage_err; + logic loc_alert_en_shadowed_1_update_err; + logic loc_alert_en_shadowed_2_re; + logic loc_alert_en_shadowed_2_we; + logic loc_alert_en_shadowed_2_qs; + logic loc_alert_en_shadowed_2_wd; + logic loc_alert_en_shadowed_2_storage_err; + logic loc_alert_en_shadowed_2_update_err; + logic loc_alert_en_shadowed_3_re; + logic loc_alert_en_shadowed_3_we; + logic loc_alert_en_shadowed_3_qs; + logic loc_alert_en_shadowed_3_wd; + logic loc_alert_en_shadowed_3_storage_err; + logic loc_alert_en_shadowed_3_update_err; + logic loc_alert_en_shadowed_4_re; + logic loc_alert_en_shadowed_4_we; + logic loc_alert_en_shadowed_4_qs; + logic loc_alert_en_shadowed_4_wd; + logic loc_alert_en_shadowed_4_storage_err; + logic loc_alert_en_shadowed_4_update_err; + logic loc_alert_en_shadowed_5_re; + logic loc_alert_en_shadowed_5_we; + logic loc_alert_en_shadowed_5_qs; + logic loc_alert_en_shadowed_5_wd; + logic loc_alert_en_shadowed_5_storage_err; + logic loc_alert_en_shadowed_5_update_err; + logic loc_alert_en_shadowed_6_re; + logic loc_alert_en_shadowed_6_we; + logic loc_alert_en_shadowed_6_qs; + logic loc_alert_en_shadowed_6_wd; + logic loc_alert_en_shadowed_6_storage_err; + logic loc_alert_en_shadowed_6_update_err; + logic loc_alert_class_shadowed_0_re; + logic loc_alert_class_shadowed_0_we; + logic [1:0] loc_alert_class_shadowed_0_qs; + logic [1:0] loc_alert_class_shadowed_0_wd; + logic loc_alert_class_shadowed_0_storage_err; + logic loc_alert_class_shadowed_0_update_err; + logic loc_alert_class_shadowed_1_re; + logic loc_alert_class_shadowed_1_we; + logic [1:0] loc_alert_class_shadowed_1_qs; + logic [1:0] loc_alert_class_shadowed_1_wd; + logic loc_alert_class_shadowed_1_storage_err; + logic loc_alert_class_shadowed_1_update_err; + logic loc_alert_class_shadowed_2_re; + logic loc_alert_class_shadowed_2_we; + logic [1:0] loc_alert_class_shadowed_2_qs; + logic [1:0] loc_alert_class_shadowed_2_wd; + logic loc_alert_class_shadowed_2_storage_err; + logic loc_alert_class_shadowed_2_update_err; + logic loc_alert_class_shadowed_3_re; + logic loc_alert_class_shadowed_3_we; + logic [1:0] loc_alert_class_shadowed_3_qs; + logic [1:0] loc_alert_class_shadowed_3_wd; + logic loc_alert_class_shadowed_3_storage_err; + logic loc_alert_class_shadowed_3_update_err; + logic loc_alert_class_shadowed_4_re; + logic loc_alert_class_shadowed_4_we; + logic [1:0] loc_alert_class_shadowed_4_qs; + logic [1:0] loc_alert_class_shadowed_4_wd; + logic loc_alert_class_shadowed_4_storage_err; + logic loc_alert_class_shadowed_4_update_err; + logic loc_alert_class_shadowed_5_re; + logic loc_alert_class_shadowed_5_we; + logic [1:0] loc_alert_class_shadowed_5_qs; + logic [1:0] loc_alert_class_shadowed_5_wd; + logic loc_alert_class_shadowed_5_storage_err; + logic loc_alert_class_shadowed_5_update_err; + logic loc_alert_class_shadowed_6_re; + logic loc_alert_class_shadowed_6_we; + logic [1:0] loc_alert_class_shadowed_6_qs; + logic [1:0] loc_alert_class_shadowed_6_wd; + logic loc_alert_class_shadowed_6_storage_err; + logic loc_alert_class_shadowed_6_update_err; + logic loc_alert_cause_0_we; + logic loc_alert_cause_0_qs; + logic loc_alert_cause_0_wd; + logic loc_alert_cause_1_we; + logic loc_alert_cause_1_qs; + logic loc_alert_cause_1_wd; + logic loc_alert_cause_2_we; + logic loc_alert_cause_2_qs; + logic loc_alert_cause_2_wd; + logic loc_alert_cause_3_we; + logic loc_alert_cause_3_qs; + logic loc_alert_cause_3_wd; + logic loc_alert_cause_4_we; + logic loc_alert_cause_4_qs; + logic loc_alert_cause_4_wd; + logic loc_alert_cause_5_we; + logic loc_alert_cause_5_qs; + logic loc_alert_cause_5_wd; + logic loc_alert_cause_6_we; + logic loc_alert_cause_6_qs; + logic loc_alert_cause_6_wd; + logic classa_regwen_we; + logic classa_regwen_qs; + logic classa_regwen_wd; + logic classa_ctrl_shadowed_re; + logic classa_ctrl_shadowed_we; + logic classa_ctrl_shadowed_en_qs; + logic classa_ctrl_shadowed_en_wd; + logic classa_ctrl_shadowed_en_storage_err; + logic classa_ctrl_shadowed_en_update_err; + logic classa_ctrl_shadowed_lock_qs; + logic classa_ctrl_shadowed_lock_wd; + logic classa_ctrl_shadowed_lock_storage_err; + logic classa_ctrl_shadowed_lock_update_err; + logic classa_ctrl_shadowed_en_e0_qs; + logic classa_ctrl_shadowed_en_e0_wd; + logic classa_ctrl_shadowed_en_e0_storage_err; + logic classa_ctrl_shadowed_en_e0_update_err; + logic classa_ctrl_shadowed_en_e1_qs; + logic classa_ctrl_shadowed_en_e1_wd; + logic classa_ctrl_shadowed_en_e1_storage_err; + logic classa_ctrl_shadowed_en_e1_update_err; + logic classa_ctrl_shadowed_en_e2_qs; + logic classa_ctrl_shadowed_en_e2_wd; + logic classa_ctrl_shadowed_en_e2_storage_err; + logic classa_ctrl_shadowed_en_e2_update_err; + logic classa_ctrl_shadowed_en_e3_qs; + logic classa_ctrl_shadowed_en_e3_wd; + logic classa_ctrl_shadowed_en_e3_storage_err; + logic classa_ctrl_shadowed_en_e3_update_err; + logic [1:0] classa_ctrl_shadowed_map_e0_qs; + logic [1:0] classa_ctrl_shadowed_map_e0_wd; + logic classa_ctrl_shadowed_map_e0_storage_err; + logic classa_ctrl_shadowed_map_e0_update_err; + logic [1:0] classa_ctrl_shadowed_map_e1_qs; + logic [1:0] classa_ctrl_shadowed_map_e1_wd; + logic classa_ctrl_shadowed_map_e1_storage_err; + logic classa_ctrl_shadowed_map_e1_update_err; + logic [1:0] classa_ctrl_shadowed_map_e2_qs; + logic [1:0] classa_ctrl_shadowed_map_e2_wd; + logic classa_ctrl_shadowed_map_e2_storage_err; + logic classa_ctrl_shadowed_map_e2_update_err; + logic [1:0] classa_ctrl_shadowed_map_e3_qs; + logic [1:0] classa_ctrl_shadowed_map_e3_wd; + logic classa_ctrl_shadowed_map_e3_storage_err; + logic classa_ctrl_shadowed_map_e3_update_err; + logic classa_clr_regwen_we; + logic classa_clr_regwen_qs; + logic classa_clr_regwen_wd; + logic classa_clr_shadowed_re; + logic classa_clr_shadowed_we; + logic classa_clr_shadowed_qs; + logic classa_clr_shadowed_wd; + logic classa_clr_shadowed_storage_err; + logic classa_clr_shadowed_update_err; + logic classa_accum_cnt_re; + logic [15:0] classa_accum_cnt_qs; + logic classa_accum_thresh_shadowed_re; + logic classa_accum_thresh_shadowed_we; + logic [15:0] classa_accum_thresh_shadowed_qs; + logic [15:0] classa_accum_thresh_shadowed_wd; + logic classa_accum_thresh_shadowed_storage_err; + logic classa_accum_thresh_shadowed_update_err; + logic classa_timeout_cyc_shadowed_re; + logic classa_timeout_cyc_shadowed_we; + logic [31:0] classa_timeout_cyc_shadowed_qs; + logic [31:0] classa_timeout_cyc_shadowed_wd; + logic classa_timeout_cyc_shadowed_storage_err; + logic classa_timeout_cyc_shadowed_update_err; + logic classa_crashdump_trigger_shadowed_re; + logic classa_crashdump_trigger_shadowed_we; + logic [1:0] classa_crashdump_trigger_shadowed_qs; + logic [1:0] classa_crashdump_trigger_shadowed_wd; + logic classa_crashdump_trigger_shadowed_storage_err; + logic classa_crashdump_trigger_shadowed_update_err; + logic classa_phase0_cyc_shadowed_re; + logic classa_phase0_cyc_shadowed_we; + logic [31:0] classa_phase0_cyc_shadowed_qs; + logic [31:0] classa_phase0_cyc_shadowed_wd; + logic classa_phase0_cyc_shadowed_storage_err; + logic classa_phase0_cyc_shadowed_update_err; + logic classa_phase1_cyc_shadowed_re; + logic classa_phase1_cyc_shadowed_we; + logic [31:0] classa_phase1_cyc_shadowed_qs; + logic [31:0] classa_phase1_cyc_shadowed_wd; + logic classa_phase1_cyc_shadowed_storage_err; + logic classa_phase1_cyc_shadowed_update_err; + logic classa_phase2_cyc_shadowed_re; + logic classa_phase2_cyc_shadowed_we; + logic [31:0] classa_phase2_cyc_shadowed_qs; + logic [31:0] classa_phase2_cyc_shadowed_wd; + logic classa_phase2_cyc_shadowed_storage_err; + logic classa_phase2_cyc_shadowed_update_err; + logic classa_phase3_cyc_shadowed_re; + logic classa_phase3_cyc_shadowed_we; + logic [31:0] classa_phase3_cyc_shadowed_qs; + logic [31:0] classa_phase3_cyc_shadowed_wd; + logic classa_phase3_cyc_shadowed_storage_err; + logic classa_phase3_cyc_shadowed_update_err; + logic classa_esc_cnt_re; + logic [31:0] classa_esc_cnt_qs; + logic classa_state_re; + logic [2:0] classa_state_qs; + logic classb_regwen_we; + logic classb_regwen_qs; + logic classb_regwen_wd; + logic classb_ctrl_shadowed_re; + logic classb_ctrl_shadowed_we; + logic classb_ctrl_shadowed_en_qs; + logic classb_ctrl_shadowed_en_wd; + logic classb_ctrl_shadowed_en_storage_err; + logic classb_ctrl_shadowed_en_update_err; + logic classb_ctrl_shadowed_lock_qs; + logic classb_ctrl_shadowed_lock_wd; + logic classb_ctrl_shadowed_lock_storage_err; + logic classb_ctrl_shadowed_lock_update_err; + logic classb_ctrl_shadowed_en_e0_qs; + logic classb_ctrl_shadowed_en_e0_wd; + logic classb_ctrl_shadowed_en_e0_storage_err; + logic classb_ctrl_shadowed_en_e0_update_err; + logic classb_ctrl_shadowed_en_e1_qs; + logic classb_ctrl_shadowed_en_e1_wd; + logic classb_ctrl_shadowed_en_e1_storage_err; + logic classb_ctrl_shadowed_en_e1_update_err; + logic classb_ctrl_shadowed_en_e2_qs; + logic classb_ctrl_shadowed_en_e2_wd; + logic classb_ctrl_shadowed_en_e2_storage_err; + logic classb_ctrl_shadowed_en_e2_update_err; + logic classb_ctrl_shadowed_en_e3_qs; + logic classb_ctrl_shadowed_en_e3_wd; + logic classb_ctrl_shadowed_en_e3_storage_err; + logic classb_ctrl_shadowed_en_e3_update_err; + logic [1:0] classb_ctrl_shadowed_map_e0_qs; + logic [1:0] classb_ctrl_shadowed_map_e0_wd; + logic classb_ctrl_shadowed_map_e0_storage_err; + logic classb_ctrl_shadowed_map_e0_update_err; + logic [1:0] classb_ctrl_shadowed_map_e1_qs; + logic [1:0] classb_ctrl_shadowed_map_e1_wd; + logic classb_ctrl_shadowed_map_e1_storage_err; + logic classb_ctrl_shadowed_map_e1_update_err; + logic [1:0] classb_ctrl_shadowed_map_e2_qs; + logic [1:0] classb_ctrl_shadowed_map_e2_wd; + logic classb_ctrl_shadowed_map_e2_storage_err; + logic classb_ctrl_shadowed_map_e2_update_err; + logic [1:0] classb_ctrl_shadowed_map_e3_qs; + logic [1:0] classb_ctrl_shadowed_map_e3_wd; + logic classb_ctrl_shadowed_map_e3_storage_err; + logic classb_ctrl_shadowed_map_e3_update_err; + logic classb_clr_regwen_we; + logic classb_clr_regwen_qs; + logic classb_clr_regwen_wd; + logic classb_clr_shadowed_re; + logic classb_clr_shadowed_we; + logic classb_clr_shadowed_qs; + logic classb_clr_shadowed_wd; + logic classb_clr_shadowed_storage_err; + logic classb_clr_shadowed_update_err; + logic classb_accum_cnt_re; + logic [15:0] classb_accum_cnt_qs; + logic classb_accum_thresh_shadowed_re; + logic classb_accum_thresh_shadowed_we; + logic [15:0] classb_accum_thresh_shadowed_qs; + logic [15:0] classb_accum_thresh_shadowed_wd; + logic classb_accum_thresh_shadowed_storage_err; + logic classb_accum_thresh_shadowed_update_err; + logic classb_timeout_cyc_shadowed_re; + logic classb_timeout_cyc_shadowed_we; + logic [31:0] classb_timeout_cyc_shadowed_qs; + logic [31:0] classb_timeout_cyc_shadowed_wd; + logic classb_timeout_cyc_shadowed_storage_err; + logic classb_timeout_cyc_shadowed_update_err; + logic classb_crashdump_trigger_shadowed_re; + logic classb_crashdump_trigger_shadowed_we; + logic [1:0] classb_crashdump_trigger_shadowed_qs; + logic [1:0] classb_crashdump_trigger_shadowed_wd; + logic classb_crashdump_trigger_shadowed_storage_err; + logic classb_crashdump_trigger_shadowed_update_err; + logic classb_phase0_cyc_shadowed_re; + logic classb_phase0_cyc_shadowed_we; + logic [31:0] classb_phase0_cyc_shadowed_qs; + logic [31:0] classb_phase0_cyc_shadowed_wd; + logic classb_phase0_cyc_shadowed_storage_err; + logic classb_phase0_cyc_shadowed_update_err; + logic classb_phase1_cyc_shadowed_re; + logic classb_phase1_cyc_shadowed_we; + logic [31:0] classb_phase1_cyc_shadowed_qs; + logic [31:0] classb_phase1_cyc_shadowed_wd; + logic classb_phase1_cyc_shadowed_storage_err; + logic classb_phase1_cyc_shadowed_update_err; + logic classb_phase2_cyc_shadowed_re; + logic classb_phase2_cyc_shadowed_we; + logic [31:0] classb_phase2_cyc_shadowed_qs; + logic [31:0] classb_phase2_cyc_shadowed_wd; + logic classb_phase2_cyc_shadowed_storage_err; + logic classb_phase2_cyc_shadowed_update_err; + logic classb_phase3_cyc_shadowed_re; + logic classb_phase3_cyc_shadowed_we; + logic [31:0] classb_phase3_cyc_shadowed_qs; + logic [31:0] classb_phase3_cyc_shadowed_wd; + logic classb_phase3_cyc_shadowed_storage_err; + logic classb_phase3_cyc_shadowed_update_err; + logic classb_esc_cnt_re; + logic [31:0] classb_esc_cnt_qs; + logic classb_state_re; + logic [2:0] classb_state_qs; + logic classc_regwen_we; + logic classc_regwen_qs; + logic classc_regwen_wd; + logic classc_ctrl_shadowed_re; + logic classc_ctrl_shadowed_we; + logic classc_ctrl_shadowed_en_qs; + logic classc_ctrl_shadowed_en_wd; + logic classc_ctrl_shadowed_en_storage_err; + logic classc_ctrl_shadowed_en_update_err; + logic classc_ctrl_shadowed_lock_qs; + logic classc_ctrl_shadowed_lock_wd; + logic classc_ctrl_shadowed_lock_storage_err; + logic classc_ctrl_shadowed_lock_update_err; + logic classc_ctrl_shadowed_en_e0_qs; + logic classc_ctrl_shadowed_en_e0_wd; + logic classc_ctrl_shadowed_en_e0_storage_err; + logic classc_ctrl_shadowed_en_e0_update_err; + logic classc_ctrl_shadowed_en_e1_qs; + logic classc_ctrl_shadowed_en_e1_wd; + logic classc_ctrl_shadowed_en_e1_storage_err; + logic classc_ctrl_shadowed_en_e1_update_err; + logic classc_ctrl_shadowed_en_e2_qs; + logic classc_ctrl_shadowed_en_e2_wd; + logic classc_ctrl_shadowed_en_e2_storage_err; + logic classc_ctrl_shadowed_en_e2_update_err; + logic classc_ctrl_shadowed_en_e3_qs; + logic classc_ctrl_shadowed_en_e3_wd; + logic classc_ctrl_shadowed_en_e3_storage_err; + logic classc_ctrl_shadowed_en_e3_update_err; + logic [1:0] classc_ctrl_shadowed_map_e0_qs; + logic [1:0] classc_ctrl_shadowed_map_e0_wd; + logic classc_ctrl_shadowed_map_e0_storage_err; + logic classc_ctrl_shadowed_map_e0_update_err; + logic [1:0] classc_ctrl_shadowed_map_e1_qs; + logic [1:0] classc_ctrl_shadowed_map_e1_wd; + logic classc_ctrl_shadowed_map_e1_storage_err; + logic classc_ctrl_shadowed_map_e1_update_err; + logic [1:0] classc_ctrl_shadowed_map_e2_qs; + logic [1:0] classc_ctrl_shadowed_map_e2_wd; + logic classc_ctrl_shadowed_map_e2_storage_err; + logic classc_ctrl_shadowed_map_e2_update_err; + logic [1:0] classc_ctrl_shadowed_map_e3_qs; + logic [1:0] classc_ctrl_shadowed_map_e3_wd; + logic classc_ctrl_shadowed_map_e3_storage_err; + logic classc_ctrl_shadowed_map_e3_update_err; + logic classc_clr_regwen_we; + logic classc_clr_regwen_qs; + logic classc_clr_regwen_wd; + logic classc_clr_shadowed_re; + logic classc_clr_shadowed_we; + logic classc_clr_shadowed_qs; + logic classc_clr_shadowed_wd; + logic classc_clr_shadowed_storage_err; + logic classc_clr_shadowed_update_err; + logic classc_accum_cnt_re; + logic [15:0] classc_accum_cnt_qs; + logic classc_accum_thresh_shadowed_re; + logic classc_accum_thresh_shadowed_we; + logic [15:0] classc_accum_thresh_shadowed_qs; + logic [15:0] classc_accum_thresh_shadowed_wd; + logic classc_accum_thresh_shadowed_storage_err; + logic classc_accum_thresh_shadowed_update_err; + logic classc_timeout_cyc_shadowed_re; + logic classc_timeout_cyc_shadowed_we; + logic [31:0] classc_timeout_cyc_shadowed_qs; + logic [31:0] classc_timeout_cyc_shadowed_wd; + logic classc_timeout_cyc_shadowed_storage_err; + logic classc_timeout_cyc_shadowed_update_err; + logic classc_crashdump_trigger_shadowed_re; + logic classc_crashdump_trigger_shadowed_we; + logic [1:0] classc_crashdump_trigger_shadowed_qs; + logic [1:0] classc_crashdump_trigger_shadowed_wd; + logic classc_crashdump_trigger_shadowed_storage_err; + logic classc_crashdump_trigger_shadowed_update_err; + logic classc_phase0_cyc_shadowed_re; + logic classc_phase0_cyc_shadowed_we; + logic [31:0] classc_phase0_cyc_shadowed_qs; + logic [31:0] classc_phase0_cyc_shadowed_wd; + logic classc_phase0_cyc_shadowed_storage_err; + logic classc_phase0_cyc_shadowed_update_err; + logic classc_phase1_cyc_shadowed_re; + logic classc_phase1_cyc_shadowed_we; + logic [31:0] classc_phase1_cyc_shadowed_qs; + logic [31:0] classc_phase1_cyc_shadowed_wd; + logic classc_phase1_cyc_shadowed_storage_err; + logic classc_phase1_cyc_shadowed_update_err; + logic classc_phase2_cyc_shadowed_re; + logic classc_phase2_cyc_shadowed_we; + logic [31:0] classc_phase2_cyc_shadowed_qs; + logic [31:0] classc_phase2_cyc_shadowed_wd; + logic classc_phase2_cyc_shadowed_storage_err; + logic classc_phase2_cyc_shadowed_update_err; + logic classc_phase3_cyc_shadowed_re; + logic classc_phase3_cyc_shadowed_we; + logic [31:0] classc_phase3_cyc_shadowed_qs; + logic [31:0] classc_phase3_cyc_shadowed_wd; + logic classc_phase3_cyc_shadowed_storage_err; + logic classc_phase3_cyc_shadowed_update_err; + logic classc_esc_cnt_re; + logic [31:0] classc_esc_cnt_qs; + logic classc_state_re; + logic [2:0] classc_state_qs; + logic classd_regwen_we; + logic classd_regwen_qs; + logic classd_regwen_wd; + logic classd_ctrl_shadowed_re; + logic classd_ctrl_shadowed_we; + logic classd_ctrl_shadowed_en_qs; + logic classd_ctrl_shadowed_en_wd; + logic classd_ctrl_shadowed_en_storage_err; + logic classd_ctrl_shadowed_en_update_err; + logic classd_ctrl_shadowed_lock_qs; + logic classd_ctrl_shadowed_lock_wd; + logic classd_ctrl_shadowed_lock_storage_err; + logic classd_ctrl_shadowed_lock_update_err; + logic classd_ctrl_shadowed_en_e0_qs; + logic classd_ctrl_shadowed_en_e0_wd; + logic classd_ctrl_shadowed_en_e0_storage_err; + logic classd_ctrl_shadowed_en_e0_update_err; + logic classd_ctrl_shadowed_en_e1_qs; + logic classd_ctrl_shadowed_en_e1_wd; + logic classd_ctrl_shadowed_en_e1_storage_err; + logic classd_ctrl_shadowed_en_e1_update_err; + logic classd_ctrl_shadowed_en_e2_qs; + logic classd_ctrl_shadowed_en_e2_wd; + logic classd_ctrl_shadowed_en_e2_storage_err; + logic classd_ctrl_shadowed_en_e2_update_err; + logic classd_ctrl_shadowed_en_e3_qs; + logic classd_ctrl_shadowed_en_e3_wd; + logic classd_ctrl_shadowed_en_e3_storage_err; + logic classd_ctrl_shadowed_en_e3_update_err; + logic [1:0] classd_ctrl_shadowed_map_e0_qs; + logic [1:0] classd_ctrl_shadowed_map_e0_wd; + logic classd_ctrl_shadowed_map_e0_storage_err; + logic classd_ctrl_shadowed_map_e0_update_err; + logic [1:0] classd_ctrl_shadowed_map_e1_qs; + logic [1:0] classd_ctrl_shadowed_map_e1_wd; + logic classd_ctrl_shadowed_map_e1_storage_err; + logic classd_ctrl_shadowed_map_e1_update_err; + logic [1:0] classd_ctrl_shadowed_map_e2_qs; + logic [1:0] classd_ctrl_shadowed_map_e2_wd; + logic classd_ctrl_shadowed_map_e2_storage_err; + logic classd_ctrl_shadowed_map_e2_update_err; + logic [1:0] classd_ctrl_shadowed_map_e3_qs; + logic [1:0] classd_ctrl_shadowed_map_e3_wd; + logic classd_ctrl_shadowed_map_e3_storage_err; + logic classd_ctrl_shadowed_map_e3_update_err; + logic classd_clr_regwen_we; + logic classd_clr_regwen_qs; + logic classd_clr_regwen_wd; + logic classd_clr_shadowed_re; + logic classd_clr_shadowed_we; + logic classd_clr_shadowed_qs; + logic classd_clr_shadowed_wd; + logic classd_clr_shadowed_storage_err; + logic classd_clr_shadowed_update_err; + logic classd_accum_cnt_re; + logic [15:0] classd_accum_cnt_qs; + logic classd_accum_thresh_shadowed_re; + logic classd_accum_thresh_shadowed_we; + logic [15:0] classd_accum_thresh_shadowed_qs; + logic [15:0] classd_accum_thresh_shadowed_wd; + logic classd_accum_thresh_shadowed_storage_err; + logic classd_accum_thresh_shadowed_update_err; + logic classd_timeout_cyc_shadowed_re; + logic classd_timeout_cyc_shadowed_we; + logic [31:0] classd_timeout_cyc_shadowed_qs; + logic [31:0] classd_timeout_cyc_shadowed_wd; + logic classd_timeout_cyc_shadowed_storage_err; + logic classd_timeout_cyc_shadowed_update_err; + logic classd_crashdump_trigger_shadowed_re; + logic classd_crashdump_trigger_shadowed_we; + logic [1:0] classd_crashdump_trigger_shadowed_qs; + logic [1:0] classd_crashdump_trigger_shadowed_wd; + logic classd_crashdump_trigger_shadowed_storage_err; + logic classd_crashdump_trigger_shadowed_update_err; + logic classd_phase0_cyc_shadowed_re; + logic classd_phase0_cyc_shadowed_we; + logic [31:0] classd_phase0_cyc_shadowed_qs; + logic [31:0] classd_phase0_cyc_shadowed_wd; + logic classd_phase0_cyc_shadowed_storage_err; + logic classd_phase0_cyc_shadowed_update_err; + logic classd_phase1_cyc_shadowed_re; + logic classd_phase1_cyc_shadowed_we; + logic [31:0] classd_phase1_cyc_shadowed_qs; + logic [31:0] classd_phase1_cyc_shadowed_wd; + logic classd_phase1_cyc_shadowed_storage_err; + logic classd_phase1_cyc_shadowed_update_err; + logic classd_phase2_cyc_shadowed_re; + logic classd_phase2_cyc_shadowed_we; + logic [31:0] classd_phase2_cyc_shadowed_qs; + logic [31:0] classd_phase2_cyc_shadowed_wd; + logic classd_phase2_cyc_shadowed_storage_err; + logic classd_phase2_cyc_shadowed_update_err; + logic classd_phase3_cyc_shadowed_re; + logic classd_phase3_cyc_shadowed_we; + logic [31:0] classd_phase3_cyc_shadowed_qs; + logic [31:0] classd_phase3_cyc_shadowed_wd; + logic classd_phase3_cyc_shadowed_storage_err; + logic classd_phase3_cyc_shadowed_update_err; + logic classd_esc_cnt_re; + logic [31:0] classd_esc_cnt_qs; + logic classd_state_re; + logic [2:0] classd_state_qs; + + // Register instances + // R[intr_state]: V(False) + // F[classa]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_classa ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_classa_wd), + + // from internal hardware + .de (hw2reg.intr_state.classa.de), + .d (hw2reg.intr_state.classa.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.classa.q), + .ds (), + + // to register interface (read) + .qs (intr_state_classa_qs) + ); + + // F[classb]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_classb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_classb_wd), + + // from internal hardware + .de (hw2reg.intr_state.classb.de), + .d (hw2reg.intr_state.classb.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.classb.q), + .ds (), + + // to register interface (read) + .qs (intr_state_classb_qs) + ); + + // F[classc]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_classc ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_classc_wd), + + // from internal hardware + .de (hw2reg.intr_state.classc.de), + .d (hw2reg.intr_state.classc.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.classc.q), + .ds (), + + // to register interface (read) + .qs (intr_state_classc_qs) + ); + + // F[classd]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_classd ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_classd_wd), + + // from internal hardware + .de (hw2reg.intr_state.classd.de), + .d (hw2reg.intr_state.classd.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.classd.q), + .ds (), + + // to register interface (read) + .qs (intr_state_classd_qs) + ); + + + // R[intr_enable]: V(False) + // F[classa]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_classa ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_classa_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.classa.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_classa_qs) + ); + + // F[classb]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_classb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_classb_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.classb.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_classb_qs) + ); + + // F[classc]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_classc ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_classc_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.classc.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_classc_qs) + ); + + // F[classd]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_classd ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_classd_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.classd.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_classd_qs) + ); + + + // R[intr_test]: V(True) + logic intr_test_qe; + logic [3:0] intr_test_flds_we; + assign intr_test_qe = &intr_test_flds_we; + // F[classa]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_classa ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_classa_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[0]), + .q (reg2hw.intr_test.classa.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.classa.qe = intr_test_qe; + + // F[classb]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_classb ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_classb_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[1]), + .q (reg2hw.intr_test.classb.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.classb.qe = intr_test_qe; + + // F[classc]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_classc ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_classc_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[2]), + .q (reg2hw.intr_test.classc.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.classc.qe = intr_test_qe; + + // F[classd]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_classd ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_classd_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[3]), + .q (reg2hw.intr_test.classd.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.classd.qe = intr_test_qe; + + + // R[ping_timer_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_ping_timer_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ping_timer_regwen_we), + .wd (ping_timer_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ping_timer_regwen_qs) + ); + + + // R[ping_timeout_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic ping_timeout_cyc_shadowed_gated_we; + assign ping_timeout_cyc_shadowed_gated_we = ping_timeout_cyc_shadowed_we & ping_timer_regwen_qs; + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h100), + .Mubi (1'b0) + ) u_ping_timeout_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (ping_timeout_cyc_shadowed_re), + .we (ping_timeout_cyc_shadowed_gated_we), + .wd (ping_timeout_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ping_timeout_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (ping_timeout_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (ping_timeout_cyc_shadowed_update_err), + .err_storage (ping_timeout_cyc_shadowed_storage_err) + ); + + + // R[ping_timer_en_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic ping_timer_en_shadowed_gated_we; + assign ping_timer_en_shadowed_gated_we = ping_timer_en_shadowed_we & ping_timer_regwen_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1S), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ping_timer_en_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (ping_timer_en_shadowed_re), + .we (ping_timer_en_shadowed_gated_we), + .wd (ping_timer_en_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ping_timer_en_shadowed.q), + .ds (), + + // to register interface (read) + .qs (ping_timer_en_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (ping_timer_en_shadowed_update_err), + .err_storage (ping_timer_en_shadowed_storage_err) + ); + + + // Subregister 0 of Multireg alert_regwen + // R[alert_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_0_we), + .wd (alert_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[0].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_0_qs) + ); + + + // Subregister 1 of Multireg alert_regwen + // R[alert_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_1_we), + .wd (alert_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[1].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_1_qs) + ); + + + // Subregister 2 of Multireg alert_regwen + // R[alert_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_2_we), + .wd (alert_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[2].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_2_qs) + ); + + + // Subregister 3 of Multireg alert_regwen + // R[alert_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_3_we), + .wd (alert_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[3].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_3_qs) + ); + + + // Subregister 4 of Multireg alert_regwen + // R[alert_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_4_we), + .wd (alert_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[4].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_4_qs) + ); + + + // Subregister 5 of Multireg alert_regwen + // R[alert_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_5_we), + .wd (alert_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[5].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_5_qs) + ); + + + // Subregister 6 of Multireg alert_regwen + // R[alert_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_6_we), + .wd (alert_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[6].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_6_qs) + ); + + + // Subregister 7 of Multireg alert_regwen + // R[alert_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_7_we), + .wd (alert_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[7].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_7_qs) + ); + + + // Subregister 8 of Multireg alert_regwen + // R[alert_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_8_we), + .wd (alert_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[8].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_8_qs) + ); + + + // Subregister 9 of Multireg alert_regwen + // R[alert_regwen_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_9_we), + .wd (alert_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[9].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_9_qs) + ); + + + // Subregister 10 of Multireg alert_regwen + // R[alert_regwen_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_10_we), + .wd (alert_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[10].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_10_qs) + ); + + + // Subregister 11 of Multireg alert_regwen + // R[alert_regwen_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_11_we), + .wd (alert_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[11].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_11_qs) + ); + + + // Subregister 12 of Multireg alert_regwen + // R[alert_regwen_12]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_12_we), + .wd (alert_regwen_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[12].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_12_qs) + ); + + + // Subregister 13 of Multireg alert_regwen + // R[alert_regwen_13]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_13_we), + .wd (alert_regwen_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[13].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_13_qs) + ); + + + // Subregister 14 of Multireg alert_regwen + // R[alert_regwen_14]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_14_we), + .wd (alert_regwen_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[14].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_14_qs) + ); + + + // Subregister 15 of Multireg alert_regwen + // R[alert_regwen_15]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_15_we), + .wd (alert_regwen_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[15].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_15_qs) + ); + + + // Subregister 16 of Multireg alert_regwen + // R[alert_regwen_16]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_16_we), + .wd (alert_regwen_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[16].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_16_qs) + ); + + + // Subregister 17 of Multireg alert_regwen + // R[alert_regwen_17]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_17_we), + .wd (alert_regwen_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[17].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_17_qs) + ); + + + // Subregister 18 of Multireg alert_regwen + // R[alert_regwen_18]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_18_we), + .wd (alert_regwen_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[18].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_18_qs) + ); + + + // Subregister 19 of Multireg alert_regwen + // R[alert_regwen_19]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_19_we), + .wd (alert_regwen_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[19].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_19_qs) + ); + + + // Subregister 20 of Multireg alert_regwen + // R[alert_regwen_20]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_20_we), + .wd (alert_regwen_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[20].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_20_qs) + ); + + + // Subregister 21 of Multireg alert_regwen + // R[alert_regwen_21]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_21_we), + .wd (alert_regwen_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[21].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_21_qs) + ); + + + // Subregister 22 of Multireg alert_regwen + // R[alert_regwen_22]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_22_we), + .wd (alert_regwen_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[22].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_22_qs) + ); + + + // Subregister 23 of Multireg alert_regwen + // R[alert_regwen_23]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_23_we), + .wd (alert_regwen_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[23].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_23_qs) + ); + + + // Subregister 24 of Multireg alert_regwen + // R[alert_regwen_24]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_24_we), + .wd (alert_regwen_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[24].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_24_qs) + ); + + + // Subregister 25 of Multireg alert_regwen + // R[alert_regwen_25]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_25_we), + .wd (alert_regwen_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[25].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_25_qs) + ); + + + // Subregister 26 of Multireg alert_regwen + // R[alert_regwen_26]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_26_we), + .wd (alert_regwen_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[26].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_26_qs) + ); + + + // Subregister 27 of Multireg alert_regwen + // R[alert_regwen_27]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_27_we), + .wd (alert_regwen_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[27].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_27_qs) + ); + + + // Subregister 28 of Multireg alert_regwen + // R[alert_regwen_28]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_28_we), + .wd (alert_regwen_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[28].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_28_qs) + ); + + + // Subregister 29 of Multireg alert_regwen + // R[alert_regwen_29]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_29_we), + .wd (alert_regwen_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[29].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_29_qs) + ); + + + // Subregister 30 of Multireg alert_regwen + // R[alert_regwen_30]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_30_we), + .wd (alert_regwen_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[30].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_30_qs) + ); + + + // Subregister 31 of Multireg alert_regwen + // R[alert_regwen_31]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_31_we), + .wd (alert_regwen_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[31].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_31_qs) + ); + + + // Subregister 32 of Multireg alert_regwen + // R[alert_regwen_32]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_32_we), + .wd (alert_regwen_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[32].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_32_qs) + ); + + + // Subregister 33 of Multireg alert_regwen + // R[alert_regwen_33]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_33_we), + .wd (alert_regwen_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[33].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_33_qs) + ); + + + // Subregister 34 of Multireg alert_regwen + // R[alert_regwen_34]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_34_we), + .wd (alert_regwen_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[34].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_34_qs) + ); + + + // Subregister 35 of Multireg alert_regwen + // R[alert_regwen_35]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_35_we), + .wd (alert_regwen_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[35].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_35_qs) + ); + + + // Subregister 36 of Multireg alert_regwen + // R[alert_regwen_36]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_36_we), + .wd (alert_regwen_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[36].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_36_qs) + ); + + + // Subregister 37 of Multireg alert_regwen + // R[alert_regwen_37]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_37_we), + .wd (alert_regwen_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[37].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_37_qs) + ); + + + // Subregister 38 of Multireg alert_regwen + // R[alert_regwen_38]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_38_we), + .wd (alert_regwen_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[38].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_38_qs) + ); + + + // Subregister 39 of Multireg alert_regwen + // R[alert_regwen_39]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_39_we), + .wd (alert_regwen_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[39].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_39_qs) + ); + + + // Subregister 40 of Multireg alert_regwen + // R[alert_regwen_40]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_40_we), + .wd (alert_regwen_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[40].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_40_qs) + ); + + + // Subregister 41 of Multireg alert_regwen + // R[alert_regwen_41]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_41_we), + .wd (alert_regwen_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[41].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_41_qs) + ); + + + // Subregister 42 of Multireg alert_regwen + // R[alert_regwen_42]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_42_we), + .wd (alert_regwen_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[42].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_42_qs) + ); + + + // Subregister 43 of Multireg alert_regwen + // R[alert_regwen_43]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_43_we), + .wd (alert_regwen_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[43].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_43_qs) + ); + + + // Subregister 44 of Multireg alert_regwen + // R[alert_regwen_44]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_44_we), + .wd (alert_regwen_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[44].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_44_qs) + ); + + + // Subregister 45 of Multireg alert_regwen + // R[alert_regwen_45]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_45_we), + .wd (alert_regwen_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[45].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_45_qs) + ); + + + // Subregister 46 of Multireg alert_regwen + // R[alert_regwen_46]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_46_we), + .wd (alert_regwen_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[46].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_46_qs) + ); + + + // Subregister 47 of Multireg alert_regwen + // R[alert_regwen_47]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_47_we), + .wd (alert_regwen_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[47].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_47_qs) + ); + + + // Subregister 48 of Multireg alert_regwen + // R[alert_regwen_48]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_48_we), + .wd (alert_regwen_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[48].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_48_qs) + ); + + + // Subregister 49 of Multireg alert_regwen + // R[alert_regwen_49]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_49_we), + .wd (alert_regwen_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[49].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_49_qs) + ); + + + // Subregister 50 of Multireg alert_regwen + // R[alert_regwen_50]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_50_we), + .wd (alert_regwen_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[50].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_50_qs) + ); + + + // Subregister 51 of Multireg alert_regwen + // R[alert_regwen_51]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_51_we), + .wd (alert_regwen_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[51].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_51_qs) + ); + + + // Subregister 52 of Multireg alert_regwen + // R[alert_regwen_52]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_52_we), + .wd (alert_regwen_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[52].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_52_qs) + ); + + + // Subregister 53 of Multireg alert_regwen + // R[alert_regwen_53]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_53_we), + .wd (alert_regwen_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[53].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_53_qs) + ); + + + // Subregister 54 of Multireg alert_regwen + // R[alert_regwen_54]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_54_we), + .wd (alert_regwen_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[54].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_54_qs) + ); + + + // Subregister 55 of Multireg alert_regwen + // R[alert_regwen_55]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_55_we), + .wd (alert_regwen_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[55].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_55_qs) + ); + + + // Subregister 56 of Multireg alert_regwen + // R[alert_regwen_56]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_56_we), + .wd (alert_regwen_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[56].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_56_qs) + ); + + + // Subregister 57 of Multireg alert_regwen + // R[alert_regwen_57]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_57_we), + .wd (alert_regwen_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[57].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_57_qs) + ); + + + // Subregister 58 of Multireg alert_regwen + // R[alert_regwen_58]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_58_we), + .wd (alert_regwen_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[58].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_58_qs) + ); + + + // Subregister 59 of Multireg alert_regwen + // R[alert_regwen_59]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_59_we), + .wd (alert_regwen_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[59].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_59_qs) + ); + + + // Subregister 60 of Multireg alert_regwen + // R[alert_regwen_60]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_60_we), + .wd (alert_regwen_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[60].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_60_qs) + ); + + + // Subregister 61 of Multireg alert_regwen + // R[alert_regwen_61]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_61_we), + .wd (alert_regwen_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[61].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_61_qs) + ); + + + // Subregister 62 of Multireg alert_regwen + // R[alert_regwen_62]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_62_we), + .wd (alert_regwen_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[62].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_62_qs) + ); + + + // Subregister 63 of Multireg alert_regwen + // R[alert_regwen_63]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_63_we), + .wd (alert_regwen_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[63].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_63_qs) + ); + + + // Subregister 64 of Multireg alert_regwen + // R[alert_regwen_64]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_64_we), + .wd (alert_regwen_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[64].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_64_qs) + ); + + + // Subregister 65 of Multireg alert_regwen + // R[alert_regwen_65]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_65_we), + .wd (alert_regwen_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[65].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_65_qs) + ); + + + // Subregister 66 of Multireg alert_regwen + // R[alert_regwen_66]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_66_we), + .wd (alert_regwen_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[66].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_66_qs) + ); + + + // Subregister 67 of Multireg alert_regwen + // R[alert_regwen_67]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_67_we), + .wd (alert_regwen_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[67].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_67_qs) + ); + + + // Subregister 68 of Multireg alert_regwen + // R[alert_regwen_68]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_68_we), + .wd (alert_regwen_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[68].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_68_qs) + ); + + + // Subregister 69 of Multireg alert_regwen + // R[alert_regwen_69]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_69_we), + .wd (alert_regwen_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[69].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_69_qs) + ); + + + // Subregister 70 of Multireg alert_regwen + // R[alert_regwen_70]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_70_we), + .wd (alert_regwen_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[70].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_70_qs) + ); + + + // Subregister 71 of Multireg alert_regwen + // R[alert_regwen_71]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_71_we), + .wd (alert_regwen_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[71].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_71_qs) + ); + + + // Subregister 72 of Multireg alert_regwen + // R[alert_regwen_72]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_72_we), + .wd (alert_regwen_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[72].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_72_qs) + ); + + + // Subregister 73 of Multireg alert_regwen + // R[alert_regwen_73]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_73_we), + .wd (alert_regwen_73_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[73].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_73_qs) + ); + + + // Subregister 74 of Multireg alert_regwen + // R[alert_regwen_74]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_74_we), + .wd (alert_regwen_74_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[74].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_74_qs) + ); + + + // Subregister 75 of Multireg alert_regwen + // R[alert_regwen_75]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_75_we), + .wd (alert_regwen_75_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[75].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_75_qs) + ); + + + // Subregister 76 of Multireg alert_regwen + // R[alert_regwen_76]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_76_we), + .wd (alert_regwen_76_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[76].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_76_qs) + ); + + + // Subregister 77 of Multireg alert_regwen + // R[alert_regwen_77]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_77_we), + .wd (alert_regwen_77_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[77].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_77_qs) + ); + + + // Subregister 78 of Multireg alert_regwen + // R[alert_regwen_78]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_78_we), + .wd (alert_regwen_78_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[78].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_78_qs) + ); + + + // Subregister 79 of Multireg alert_regwen + // R[alert_regwen_79]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_79_we), + .wd (alert_regwen_79_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[79].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_79_qs) + ); + + + // Subregister 80 of Multireg alert_regwen + // R[alert_regwen_80]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_80_we), + .wd (alert_regwen_80_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[80].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_80_qs) + ); + + + // Subregister 81 of Multireg alert_regwen + // R[alert_regwen_81]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_81_we), + .wd (alert_regwen_81_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[81].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_81_qs) + ); + + + // Subregister 82 of Multireg alert_regwen + // R[alert_regwen_82]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_82_we), + .wd (alert_regwen_82_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[82].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_82_qs) + ); + + + // Subregister 83 of Multireg alert_regwen + // R[alert_regwen_83]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_83_we), + .wd (alert_regwen_83_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[83].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_83_qs) + ); + + + // Subregister 84 of Multireg alert_regwen + // R[alert_regwen_84]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_84_we), + .wd (alert_regwen_84_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[84].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_84_qs) + ); + + + // Subregister 85 of Multireg alert_regwen + // R[alert_regwen_85]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_85_we), + .wd (alert_regwen_85_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[85].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_85_qs) + ); + + + // Subregister 86 of Multireg alert_regwen + // R[alert_regwen_86]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_86_we), + .wd (alert_regwen_86_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[86].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_86_qs) + ); + + + // Subregister 87 of Multireg alert_regwen + // R[alert_regwen_87]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_87_we), + .wd (alert_regwen_87_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[87].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_87_qs) + ); + + + // Subregister 88 of Multireg alert_regwen + // R[alert_regwen_88]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_88_we), + .wd (alert_regwen_88_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[88].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_88_qs) + ); + + + // Subregister 89 of Multireg alert_regwen + // R[alert_regwen_89]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_89_we), + .wd (alert_regwen_89_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[89].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_89_qs) + ); + + + // Subregister 90 of Multireg alert_regwen + // R[alert_regwen_90]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_90_we), + .wd (alert_regwen_90_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[90].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_90_qs) + ); + + + // Subregister 91 of Multireg alert_regwen + // R[alert_regwen_91]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_91_we), + .wd (alert_regwen_91_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[91].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_91_qs) + ); + + + // Subregister 92 of Multireg alert_regwen + // R[alert_regwen_92]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_92_we), + .wd (alert_regwen_92_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[92].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_92_qs) + ); + + + // Subregister 93 of Multireg alert_regwen + // R[alert_regwen_93]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_93_we), + .wd (alert_regwen_93_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[93].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_93_qs) + ); + + + // Subregister 94 of Multireg alert_regwen + // R[alert_regwen_94]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_94_we), + .wd (alert_regwen_94_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[94].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_94_qs) + ); + + + // Subregister 95 of Multireg alert_regwen + // R[alert_regwen_95]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_95_we), + .wd (alert_regwen_95_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[95].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_95_qs) + ); + + + // Subregister 96 of Multireg alert_regwen + // R[alert_regwen_96]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_96_we), + .wd (alert_regwen_96_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[96].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_96_qs) + ); + + + // Subregister 97 of Multireg alert_regwen + // R[alert_regwen_97]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_97_we), + .wd (alert_regwen_97_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[97].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_97_qs) + ); + + + // Subregister 98 of Multireg alert_regwen + // R[alert_regwen_98]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_98_we), + .wd (alert_regwen_98_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[98].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_98_qs) + ); + + + // Subregister 0 of Multireg alert_en_shadowed + // R[alert_en_shadowed_0]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_0_gated_we; + assign alert_en_shadowed_0_gated_we = alert_en_shadowed_0_we & alert_regwen_0_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_0_re), + .we (alert_en_shadowed_0_gated_we), + .wd (alert_en_shadowed_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[0].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_0_update_err), + .err_storage (alert_en_shadowed_0_storage_err) + ); + + + // Subregister 1 of Multireg alert_en_shadowed + // R[alert_en_shadowed_1]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_1_gated_we; + assign alert_en_shadowed_1_gated_we = alert_en_shadowed_1_we & alert_regwen_1_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_1_re), + .we (alert_en_shadowed_1_gated_we), + .wd (alert_en_shadowed_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[1].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_1_update_err), + .err_storage (alert_en_shadowed_1_storage_err) + ); + + + // Subregister 2 of Multireg alert_en_shadowed + // R[alert_en_shadowed_2]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_2_gated_we; + assign alert_en_shadowed_2_gated_we = alert_en_shadowed_2_we & alert_regwen_2_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_2_re), + .we (alert_en_shadowed_2_gated_we), + .wd (alert_en_shadowed_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[2].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_2_update_err), + .err_storage (alert_en_shadowed_2_storage_err) + ); + + + // Subregister 3 of Multireg alert_en_shadowed + // R[alert_en_shadowed_3]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_3_gated_we; + assign alert_en_shadowed_3_gated_we = alert_en_shadowed_3_we & alert_regwen_3_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_3_re), + .we (alert_en_shadowed_3_gated_we), + .wd (alert_en_shadowed_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[3].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_3_update_err), + .err_storage (alert_en_shadowed_3_storage_err) + ); + + + // Subregister 4 of Multireg alert_en_shadowed + // R[alert_en_shadowed_4]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_4_gated_we; + assign alert_en_shadowed_4_gated_we = alert_en_shadowed_4_we & alert_regwen_4_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_4_re), + .we (alert_en_shadowed_4_gated_we), + .wd (alert_en_shadowed_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[4].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_4_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_4_update_err), + .err_storage (alert_en_shadowed_4_storage_err) + ); + + + // Subregister 5 of Multireg alert_en_shadowed + // R[alert_en_shadowed_5]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_5_gated_we; + assign alert_en_shadowed_5_gated_we = alert_en_shadowed_5_we & alert_regwen_5_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_5_re), + .we (alert_en_shadowed_5_gated_we), + .wd (alert_en_shadowed_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[5].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_5_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_5_update_err), + .err_storage (alert_en_shadowed_5_storage_err) + ); + + + // Subregister 6 of Multireg alert_en_shadowed + // R[alert_en_shadowed_6]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_6_gated_we; + assign alert_en_shadowed_6_gated_we = alert_en_shadowed_6_we & alert_regwen_6_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_6_re), + .we (alert_en_shadowed_6_gated_we), + .wd (alert_en_shadowed_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[6].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_6_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_6_update_err), + .err_storage (alert_en_shadowed_6_storage_err) + ); + + + // Subregister 7 of Multireg alert_en_shadowed + // R[alert_en_shadowed_7]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_7_gated_we; + assign alert_en_shadowed_7_gated_we = alert_en_shadowed_7_we & alert_regwen_7_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_7_re), + .we (alert_en_shadowed_7_gated_we), + .wd (alert_en_shadowed_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[7].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_7_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_7_update_err), + .err_storage (alert_en_shadowed_7_storage_err) + ); + + + // Subregister 8 of Multireg alert_en_shadowed + // R[alert_en_shadowed_8]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_8_gated_we; + assign alert_en_shadowed_8_gated_we = alert_en_shadowed_8_we & alert_regwen_8_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_8_re), + .we (alert_en_shadowed_8_gated_we), + .wd (alert_en_shadowed_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[8].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_8_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_8_update_err), + .err_storage (alert_en_shadowed_8_storage_err) + ); + + + // Subregister 9 of Multireg alert_en_shadowed + // R[alert_en_shadowed_9]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_9_gated_we; + assign alert_en_shadowed_9_gated_we = alert_en_shadowed_9_we & alert_regwen_9_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_9_re), + .we (alert_en_shadowed_9_gated_we), + .wd (alert_en_shadowed_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[9].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_9_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_9_update_err), + .err_storage (alert_en_shadowed_9_storage_err) + ); + + + // Subregister 10 of Multireg alert_en_shadowed + // R[alert_en_shadowed_10]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_10_gated_we; + assign alert_en_shadowed_10_gated_we = alert_en_shadowed_10_we & alert_regwen_10_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_10_re), + .we (alert_en_shadowed_10_gated_we), + .wd (alert_en_shadowed_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[10].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_10_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_10_update_err), + .err_storage (alert_en_shadowed_10_storage_err) + ); + + + // Subregister 11 of Multireg alert_en_shadowed + // R[alert_en_shadowed_11]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_11_gated_we; + assign alert_en_shadowed_11_gated_we = alert_en_shadowed_11_we & alert_regwen_11_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_11_re), + .we (alert_en_shadowed_11_gated_we), + .wd (alert_en_shadowed_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[11].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_11_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_11_update_err), + .err_storage (alert_en_shadowed_11_storage_err) + ); + + + // Subregister 12 of Multireg alert_en_shadowed + // R[alert_en_shadowed_12]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_12_gated_we; + assign alert_en_shadowed_12_gated_we = alert_en_shadowed_12_we & alert_regwen_12_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_12_re), + .we (alert_en_shadowed_12_gated_we), + .wd (alert_en_shadowed_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[12].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_12_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_12_update_err), + .err_storage (alert_en_shadowed_12_storage_err) + ); + + + // Subregister 13 of Multireg alert_en_shadowed + // R[alert_en_shadowed_13]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_13_gated_we; + assign alert_en_shadowed_13_gated_we = alert_en_shadowed_13_we & alert_regwen_13_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_13_re), + .we (alert_en_shadowed_13_gated_we), + .wd (alert_en_shadowed_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[13].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_13_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_13_update_err), + .err_storage (alert_en_shadowed_13_storage_err) + ); + + + // Subregister 14 of Multireg alert_en_shadowed + // R[alert_en_shadowed_14]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_14_gated_we; + assign alert_en_shadowed_14_gated_we = alert_en_shadowed_14_we & alert_regwen_14_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_14_re), + .we (alert_en_shadowed_14_gated_we), + .wd (alert_en_shadowed_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[14].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_14_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_14_update_err), + .err_storage (alert_en_shadowed_14_storage_err) + ); + + + // Subregister 15 of Multireg alert_en_shadowed + // R[alert_en_shadowed_15]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_15_gated_we; + assign alert_en_shadowed_15_gated_we = alert_en_shadowed_15_we & alert_regwen_15_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_15_re), + .we (alert_en_shadowed_15_gated_we), + .wd (alert_en_shadowed_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[15].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_15_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_15_update_err), + .err_storage (alert_en_shadowed_15_storage_err) + ); + + + // Subregister 16 of Multireg alert_en_shadowed + // R[alert_en_shadowed_16]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_16_gated_we; + assign alert_en_shadowed_16_gated_we = alert_en_shadowed_16_we & alert_regwen_16_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_16_re), + .we (alert_en_shadowed_16_gated_we), + .wd (alert_en_shadowed_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[16].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_16_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_16_update_err), + .err_storage (alert_en_shadowed_16_storage_err) + ); + + + // Subregister 17 of Multireg alert_en_shadowed + // R[alert_en_shadowed_17]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_17_gated_we; + assign alert_en_shadowed_17_gated_we = alert_en_shadowed_17_we & alert_regwen_17_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_17_re), + .we (alert_en_shadowed_17_gated_we), + .wd (alert_en_shadowed_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[17].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_17_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_17_update_err), + .err_storage (alert_en_shadowed_17_storage_err) + ); + + + // Subregister 18 of Multireg alert_en_shadowed + // R[alert_en_shadowed_18]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_18_gated_we; + assign alert_en_shadowed_18_gated_we = alert_en_shadowed_18_we & alert_regwen_18_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_18_re), + .we (alert_en_shadowed_18_gated_we), + .wd (alert_en_shadowed_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[18].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_18_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_18_update_err), + .err_storage (alert_en_shadowed_18_storage_err) + ); + + + // Subregister 19 of Multireg alert_en_shadowed + // R[alert_en_shadowed_19]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_19_gated_we; + assign alert_en_shadowed_19_gated_we = alert_en_shadowed_19_we & alert_regwen_19_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_19_re), + .we (alert_en_shadowed_19_gated_we), + .wd (alert_en_shadowed_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[19].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_19_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_19_update_err), + .err_storage (alert_en_shadowed_19_storage_err) + ); + + + // Subregister 20 of Multireg alert_en_shadowed + // R[alert_en_shadowed_20]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_20_gated_we; + assign alert_en_shadowed_20_gated_we = alert_en_shadowed_20_we & alert_regwen_20_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_20_re), + .we (alert_en_shadowed_20_gated_we), + .wd (alert_en_shadowed_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[20].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_20_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_20_update_err), + .err_storage (alert_en_shadowed_20_storage_err) + ); + + + // Subregister 21 of Multireg alert_en_shadowed + // R[alert_en_shadowed_21]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_21_gated_we; + assign alert_en_shadowed_21_gated_we = alert_en_shadowed_21_we & alert_regwen_21_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_21_re), + .we (alert_en_shadowed_21_gated_we), + .wd (alert_en_shadowed_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[21].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_21_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_21_update_err), + .err_storage (alert_en_shadowed_21_storage_err) + ); + + + // Subregister 22 of Multireg alert_en_shadowed + // R[alert_en_shadowed_22]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_22_gated_we; + assign alert_en_shadowed_22_gated_we = alert_en_shadowed_22_we & alert_regwen_22_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_22_re), + .we (alert_en_shadowed_22_gated_we), + .wd (alert_en_shadowed_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[22].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_22_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_22_update_err), + .err_storage (alert_en_shadowed_22_storage_err) + ); + + + // Subregister 23 of Multireg alert_en_shadowed + // R[alert_en_shadowed_23]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_23_gated_we; + assign alert_en_shadowed_23_gated_we = alert_en_shadowed_23_we & alert_regwen_23_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_23_re), + .we (alert_en_shadowed_23_gated_we), + .wd (alert_en_shadowed_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[23].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_23_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_23_update_err), + .err_storage (alert_en_shadowed_23_storage_err) + ); + + + // Subregister 24 of Multireg alert_en_shadowed + // R[alert_en_shadowed_24]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_24_gated_we; + assign alert_en_shadowed_24_gated_we = alert_en_shadowed_24_we & alert_regwen_24_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_24_re), + .we (alert_en_shadowed_24_gated_we), + .wd (alert_en_shadowed_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[24].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_24_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_24_update_err), + .err_storage (alert_en_shadowed_24_storage_err) + ); + + + // Subregister 25 of Multireg alert_en_shadowed + // R[alert_en_shadowed_25]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_25_gated_we; + assign alert_en_shadowed_25_gated_we = alert_en_shadowed_25_we & alert_regwen_25_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_25_re), + .we (alert_en_shadowed_25_gated_we), + .wd (alert_en_shadowed_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[25].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_25_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_25_update_err), + .err_storage (alert_en_shadowed_25_storage_err) + ); + + + // Subregister 26 of Multireg alert_en_shadowed + // R[alert_en_shadowed_26]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_26_gated_we; + assign alert_en_shadowed_26_gated_we = alert_en_shadowed_26_we & alert_regwen_26_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_26_re), + .we (alert_en_shadowed_26_gated_we), + .wd (alert_en_shadowed_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[26].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_26_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_26_update_err), + .err_storage (alert_en_shadowed_26_storage_err) + ); + + + // Subregister 27 of Multireg alert_en_shadowed + // R[alert_en_shadowed_27]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_27_gated_we; + assign alert_en_shadowed_27_gated_we = alert_en_shadowed_27_we & alert_regwen_27_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_27_re), + .we (alert_en_shadowed_27_gated_we), + .wd (alert_en_shadowed_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[27].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_27_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_27_update_err), + .err_storage (alert_en_shadowed_27_storage_err) + ); + + + // Subregister 28 of Multireg alert_en_shadowed + // R[alert_en_shadowed_28]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_28_gated_we; + assign alert_en_shadowed_28_gated_we = alert_en_shadowed_28_we & alert_regwen_28_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_28_re), + .we (alert_en_shadowed_28_gated_we), + .wd (alert_en_shadowed_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[28].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_28_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_28_update_err), + .err_storage (alert_en_shadowed_28_storage_err) + ); + + + // Subregister 29 of Multireg alert_en_shadowed + // R[alert_en_shadowed_29]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_29_gated_we; + assign alert_en_shadowed_29_gated_we = alert_en_shadowed_29_we & alert_regwen_29_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_29_re), + .we (alert_en_shadowed_29_gated_we), + .wd (alert_en_shadowed_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[29].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_29_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_29_update_err), + .err_storage (alert_en_shadowed_29_storage_err) + ); + + + // Subregister 30 of Multireg alert_en_shadowed + // R[alert_en_shadowed_30]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_30_gated_we; + assign alert_en_shadowed_30_gated_we = alert_en_shadowed_30_we & alert_regwen_30_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_30_re), + .we (alert_en_shadowed_30_gated_we), + .wd (alert_en_shadowed_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[30].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_30_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_30_update_err), + .err_storage (alert_en_shadowed_30_storage_err) + ); + + + // Subregister 31 of Multireg alert_en_shadowed + // R[alert_en_shadowed_31]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_31_gated_we; + assign alert_en_shadowed_31_gated_we = alert_en_shadowed_31_we & alert_regwen_31_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_31_re), + .we (alert_en_shadowed_31_gated_we), + .wd (alert_en_shadowed_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[31].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_31_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_31_update_err), + .err_storage (alert_en_shadowed_31_storage_err) + ); + + + // Subregister 32 of Multireg alert_en_shadowed + // R[alert_en_shadowed_32]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_32_gated_we; + assign alert_en_shadowed_32_gated_we = alert_en_shadowed_32_we & alert_regwen_32_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_32_re), + .we (alert_en_shadowed_32_gated_we), + .wd (alert_en_shadowed_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[32].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_32_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_32_update_err), + .err_storage (alert_en_shadowed_32_storage_err) + ); + + + // Subregister 33 of Multireg alert_en_shadowed + // R[alert_en_shadowed_33]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_33_gated_we; + assign alert_en_shadowed_33_gated_we = alert_en_shadowed_33_we & alert_regwen_33_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_33_re), + .we (alert_en_shadowed_33_gated_we), + .wd (alert_en_shadowed_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[33].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_33_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_33_update_err), + .err_storage (alert_en_shadowed_33_storage_err) + ); + + + // Subregister 34 of Multireg alert_en_shadowed + // R[alert_en_shadowed_34]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_34_gated_we; + assign alert_en_shadowed_34_gated_we = alert_en_shadowed_34_we & alert_regwen_34_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_34_re), + .we (alert_en_shadowed_34_gated_we), + .wd (alert_en_shadowed_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[34].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_34_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_34_update_err), + .err_storage (alert_en_shadowed_34_storage_err) + ); + + + // Subregister 35 of Multireg alert_en_shadowed + // R[alert_en_shadowed_35]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_35_gated_we; + assign alert_en_shadowed_35_gated_we = alert_en_shadowed_35_we & alert_regwen_35_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_35_re), + .we (alert_en_shadowed_35_gated_we), + .wd (alert_en_shadowed_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[35].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_35_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_35_update_err), + .err_storage (alert_en_shadowed_35_storage_err) + ); + + + // Subregister 36 of Multireg alert_en_shadowed + // R[alert_en_shadowed_36]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_36_gated_we; + assign alert_en_shadowed_36_gated_we = alert_en_shadowed_36_we & alert_regwen_36_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_36_re), + .we (alert_en_shadowed_36_gated_we), + .wd (alert_en_shadowed_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[36].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_36_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_36_update_err), + .err_storage (alert_en_shadowed_36_storage_err) + ); + + + // Subregister 37 of Multireg alert_en_shadowed + // R[alert_en_shadowed_37]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_37_gated_we; + assign alert_en_shadowed_37_gated_we = alert_en_shadowed_37_we & alert_regwen_37_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_37_re), + .we (alert_en_shadowed_37_gated_we), + .wd (alert_en_shadowed_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[37].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_37_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_37_update_err), + .err_storage (alert_en_shadowed_37_storage_err) + ); + + + // Subregister 38 of Multireg alert_en_shadowed + // R[alert_en_shadowed_38]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_38_gated_we; + assign alert_en_shadowed_38_gated_we = alert_en_shadowed_38_we & alert_regwen_38_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_38_re), + .we (alert_en_shadowed_38_gated_we), + .wd (alert_en_shadowed_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[38].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_38_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_38_update_err), + .err_storage (alert_en_shadowed_38_storage_err) + ); + + + // Subregister 39 of Multireg alert_en_shadowed + // R[alert_en_shadowed_39]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_39_gated_we; + assign alert_en_shadowed_39_gated_we = alert_en_shadowed_39_we & alert_regwen_39_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_39_re), + .we (alert_en_shadowed_39_gated_we), + .wd (alert_en_shadowed_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[39].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_39_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_39_update_err), + .err_storage (alert_en_shadowed_39_storage_err) + ); + + + // Subregister 40 of Multireg alert_en_shadowed + // R[alert_en_shadowed_40]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_40_gated_we; + assign alert_en_shadowed_40_gated_we = alert_en_shadowed_40_we & alert_regwen_40_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_40_re), + .we (alert_en_shadowed_40_gated_we), + .wd (alert_en_shadowed_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[40].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_40_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_40_update_err), + .err_storage (alert_en_shadowed_40_storage_err) + ); + + + // Subregister 41 of Multireg alert_en_shadowed + // R[alert_en_shadowed_41]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_41_gated_we; + assign alert_en_shadowed_41_gated_we = alert_en_shadowed_41_we & alert_regwen_41_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_41_re), + .we (alert_en_shadowed_41_gated_we), + .wd (alert_en_shadowed_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[41].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_41_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_41_update_err), + .err_storage (alert_en_shadowed_41_storage_err) + ); + + + // Subregister 42 of Multireg alert_en_shadowed + // R[alert_en_shadowed_42]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_42_gated_we; + assign alert_en_shadowed_42_gated_we = alert_en_shadowed_42_we & alert_regwen_42_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_42_re), + .we (alert_en_shadowed_42_gated_we), + .wd (alert_en_shadowed_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[42].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_42_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_42_update_err), + .err_storage (alert_en_shadowed_42_storage_err) + ); + + + // Subregister 43 of Multireg alert_en_shadowed + // R[alert_en_shadowed_43]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_43_gated_we; + assign alert_en_shadowed_43_gated_we = alert_en_shadowed_43_we & alert_regwen_43_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_43_re), + .we (alert_en_shadowed_43_gated_we), + .wd (alert_en_shadowed_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[43].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_43_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_43_update_err), + .err_storage (alert_en_shadowed_43_storage_err) + ); + + + // Subregister 44 of Multireg alert_en_shadowed + // R[alert_en_shadowed_44]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_44_gated_we; + assign alert_en_shadowed_44_gated_we = alert_en_shadowed_44_we & alert_regwen_44_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_44_re), + .we (alert_en_shadowed_44_gated_we), + .wd (alert_en_shadowed_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[44].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_44_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_44_update_err), + .err_storage (alert_en_shadowed_44_storage_err) + ); + + + // Subregister 45 of Multireg alert_en_shadowed + // R[alert_en_shadowed_45]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_45_gated_we; + assign alert_en_shadowed_45_gated_we = alert_en_shadowed_45_we & alert_regwen_45_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_45_re), + .we (alert_en_shadowed_45_gated_we), + .wd (alert_en_shadowed_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[45].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_45_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_45_update_err), + .err_storage (alert_en_shadowed_45_storage_err) + ); + + + // Subregister 46 of Multireg alert_en_shadowed + // R[alert_en_shadowed_46]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_46_gated_we; + assign alert_en_shadowed_46_gated_we = alert_en_shadowed_46_we & alert_regwen_46_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_46_re), + .we (alert_en_shadowed_46_gated_we), + .wd (alert_en_shadowed_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[46].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_46_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_46_update_err), + .err_storage (alert_en_shadowed_46_storage_err) + ); + + + // Subregister 47 of Multireg alert_en_shadowed + // R[alert_en_shadowed_47]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_47_gated_we; + assign alert_en_shadowed_47_gated_we = alert_en_shadowed_47_we & alert_regwen_47_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_47_re), + .we (alert_en_shadowed_47_gated_we), + .wd (alert_en_shadowed_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[47].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_47_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_47_update_err), + .err_storage (alert_en_shadowed_47_storage_err) + ); + + + // Subregister 48 of Multireg alert_en_shadowed + // R[alert_en_shadowed_48]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_48_gated_we; + assign alert_en_shadowed_48_gated_we = alert_en_shadowed_48_we & alert_regwen_48_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_48_re), + .we (alert_en_shadowed_48_gated_we), + .wd (alert_en_shadowed_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[48].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_48_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_48_update_err), + .err_storage (alert_en_shadowed_48_storage_err) + ); + + + // Subregister 49 of Multireg alert_en_shadowed + // R[alert_en_shadowed_49]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_49_gated_we; + assign alert_en_shadowed_49_gated_we = alert_en_shadowed_49_we & alert_regwen_49_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_49_re), + .we (alert_en_shadowed_49_gated_we), + .wd (alert_en_shadowed_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[49].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_49_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_49_update_err), + .err_storage (alert_en_shadowed_49_storage_err) + ); + + + // Subregister 50 of Multireg alert_en_shadowed + // R[alert_en_shadowed_50]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_50_gated_we; + assign alert_en_shadowed_50_gated_we = alert_en_shadowed_50_we & alert_regwen_50_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_50_re), + .we (alert_en_shadowed_50_gated_we), + .wd (alert_en_shadowed_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[50].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_50_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_50_update_err), + .err_storage (alert_en_shadowed_50_storage_err) + ); + + + // Subregister 51 of Multireg alert_en_shadowed + // R[alert_en_shadowed_51]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_51_gated_we; + assign alert_en_shadowed_51_gated_we = alert_en_shadowed_51_we & alert_regwen_51_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_51_re), + .we (alert_en_shadowed_51_gated_we), + .wd (alert_en_shadowed_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[51].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_51_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_51_update_err), + .err_storage (alert_en_shadowed_51_storage_err) + ); + + + // Subregister 52 of Multireg alert_en_shadowed + // R[alert_en_shadowed_52]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_52_gated_we; + assign alert_en_shadowed_52_gated_we = alert_en_shadowed_52_we & alert_regwen_52_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_52_re), + .we (alert_en_shadowed_52_gated_we), + .wd (alert_en_shadowed_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[52].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_52_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_52_update_err), + .err_storage (alert_en_shadowed_52_storage_err) + ); + + + // Subregister 53 of Multireg alert_en_shadowed + // R[alert_en_shadowed_53]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_53_gated_we; + assign alert_en_shadowed_53_gated_we = alert_en_shadowed_53_we & alert_regwen_53_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_53_re), + .we (alert_en_shadowed_53_gated_we), + .wd (alert_en_shadowed_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[53].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_53_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_53_update_err), + .err_storage (alert_en_shadowed_53_storage_err) + ); + + + // Subregister 54 of Multireg alert_en_shadowed + // R[alert_en_shadowed_54]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_54_gated_we; + assign alert_en_shadowed_54_gated_we = alert_en_shadowed_54_we & alert_regwen_54_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_54_re), + .we (alert_en_shadowed_54_gated_we), + .wd (alert_en_shadowed_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[54].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_54_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_54_update_err), + .err_storage (alert_en_shadowed_54_storage_err) + ); + + + // Subregister 55 of Multireg alert_en_shadowed + // R[alert_en_shadowed_55]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_55_gated_we; + assign alert_en_shadowed_55_gated_we = alert_en_shadowed_55_we & alert_regwen_55_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_55_re), + .we (alert_en_shadowed_55_gated_we), + .wd (alert_en_shadowed_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[55].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_55_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_55_update_err), + .err_storage (alert_en_shadowed_55_storage_err) + ); + + + // Subregister 56 of Multireg alert_en_shadowed + // R[alert_en_shadowed_56]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_56_gated_we; + assign alert_en_shadowed_56_gated_we = alert_en_shadowed_56_we & alert_regwen_56_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_56_re), + .we (alert_en_shadowed_56_gated_we), + .wd (alert_en_shadowed_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[56].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_56_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_56_update_err), + .err_storage (alert_en_shadowed_56_storage_err) + ); + + + // Subregister 57 of Multireg alert_en_shadowed + // R[alert_en_shadowed_57]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_57_gated_we; + assign alert_en_shadowed_57_gated_we = alert_en_shadowed_57_we & alert_regwen_57_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_57_re), + .we (alert_en_shadowed_57_gated_we), + .wd (alert_en_shadowed_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[57].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_57_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_57_update_err), + .err_storage (alert_en_shadowed_57_storage_err) + ); + + + // Subregister 58 of Multireg alert_en_shadowed + // R[alert_en_shadowed_58]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_58_gated_we; + assign alert_en_shadowed_58_gated_we = alert_en_shadowed_58_we & alert_regwen_58_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_58_re), + .we (alert_en_shadowed_58_gated_we), + .wd (alert_en_shadowed_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[58].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_58_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_58_update_err), + .err_storage (alert_en_shadowed_58_storage_err) + ); + + + // Subregister 59 of Multireg alert_en_shadowed + // R[alert_en_shadowed_59]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_59_gated_we; + assign alert_en_shadowed_59_gated_we = alert_en_shadowed_59_we & alert_regwen_59_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_59_re), + .we (alert_en_shadowed_59_gated_we), + .wd (alert_en_shadowed_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[59].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_59_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_59_update_err), + .err_storage (alert_en_shadowed_59_storage_err) + ); + + + // Subregister 60 of Multireg alert_en_shadowed + // R[alert_en_shadowed_60]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_60_gated_we; + assign alert_en_shadowed_60_gated_we = alert_en_shadowed_60_we & alert_regwen_60_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_60_re), + .we (alert_en_shadowed_60_gated_we), + .wd (alert_en_shadowed_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[60].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_60_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_60_update_err), + .err_storage (alert_en_shadowed_60_storage_err) + ); + + + // Subregister 61 of Multireg alert_en_shadowed + // R[alert_en_shadowed_61]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_61_gated_we; + assign alert_en_shadowed_61_gated_we = alert_en_shadowed_61_we & alert_regwen_61_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_61_re), + .we (alert_en_shadowed_61_gated_we), + .wd (alert_en_shadowed_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[61].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_61_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_61_update_err), + .err_storage (alert_en_shadowed_61_storage_err) + ); + + + // Subregister 62 of Multireg alert_en_shadowed + // R[alert_en_shadowed_62]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_62_gated_we; + assign alert_en_shadowed_62_gated_we = alert_en_shadowed_62_we & alert_regwen_62_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_62_re), + .we (alert_en_shadowed_62_gated_we), + .wd (alert_en_shadowed_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[62].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_62_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_62_update_err), + .err_storage (alert_en_shadowed_62_storage_err) + ); + + + // Subregister 63 of Multireg alert_en_shadowed + // R[alert_en_shadowed_63]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_63_gated_we; + assign alert_en_shadowed_63_gated_we = alert_en_shadowed_63_we & alert_regwen_63_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_63_re), + .we (alert_en_shadowed_63_gated_we), + .wd (alert_en_shadowed_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[63].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_63_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_63_update_err), + .err_storage (alert_en_shadowed_63_storage_err) + ); + + + // Subregister 64 of Multireg alert_en_shadowed + // R[alert_en_shadowed_64]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_64_gated_we; + assign alert_en_shadowed_64_gated_we = alert_en_shadowed_64_we & alert_regwen_64_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_64_re), + .we (alert_en_shadowed_64_gated_we), + .wd (alert_en_shadowed_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[64].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_64_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_64_update_err), + .err_storage (alert_en_shadowed_64_storage_err) + ); + + + // Subregister 65 of Multireg alert_en_shadowed + // R[alert_en_shadowed_65]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_65_gated_we; + assign alert_en_shadowed_65_gated_we = alert_en_shadowed_65_we & alert_regwen_65_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_65_re), + .we (alert_en_shadowed_65_gated_we), + .wd (alert_en_shadowed_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[65].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_65_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_65_update_err), + .err_storage (alert_en_shadowed_65_storage_err) + ); + + + // Subregister 66 of Multireg alert_en_shadowed + // R[alert_en_shadowed_66]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_66_gated_we; + assign alert_en_shadowed_66_gated_we = alert_en_shadowed_66_we & alert_regwen_66_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_66_re), + .we (alert_en_shadowed_66_gated_we), + .wd (alert_en_shadowed_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[66].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_66_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_66_update_err), + .err_storage (alert_en_shadowed_66_storage_err) + ); + + + // Subregister 67 of Multireg alert_en_shadowed + // R[alert_en_shadowed_67]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_67_gated_we; + assign alert_en_shadowed_67_gated_we = alert_en_shadowed_67_we & alert_regwen_67_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_67_re), + .we (alert_en_shadowed_67_gated_we), + .wd (alert_en_shadowed_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[67].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_67_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_67_update_err), + .err_storage (alert_en_shadowed_67_storage_err) + ); + + + // Subregister 68 of Multireg alert_en_shadowed + // R[alert_en_shadowed_68]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_68_gated_we; + assign alert_en_shadowed_68_gated_we = alert_en_shadowed_68_we & alert_regwen_68_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_68_re), + .we (alert_en_shadowed_68_gated_we), + .wd (alert_en_shadowed_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[68].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_68_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_68_update_err), + .err_storage (alert_en_shadowed_68_storage_err) + ); + + + // Subregister 69 of Multireg alert_en_shadowed + // R[alert_en_shadowed_69]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_69_gated_we; + assign alert_en_shadowed_69_gated_we = alert_en_shadowed_69_we & alert_regwen_69_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_69_re), + .we (alert_en_shadowed_69_gated_we), + .wd (alert_en_shadowed_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[69].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_69_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_69_update_err), + .err_storage (alert_en_shadowed_69_storage_err) + ); + + + // Subregister 70 of Multireg alert_en_shadowed + // R[alert_en_shadowed_70]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_70_gated_we; + assign alert_en_shadowed_70_gated_we = alert_en_shadowed_70_we & alert_regwen_70_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_70_re), + .we (alert_en_shadowed_70_gated_we), + .wd (alert_en_shadowed_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[70].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_70_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_70_update_err), + .err_storage (alert_en_shadowed_70_storage_err) + ); + + + // Subregister 71 of Multireg alert_en_shadowed + // R[alert_en_shadowed_71]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_71_gated_we; + assign alert_en_shadowed_71_gated_we = alert_en_shadowed_71_we & alert_regwen_71_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_71_re), + .we (alert_en_shadowed_71_gated_we), + .wd (alert_en_shadowed_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[71].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_71_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_71_update_err), + .err_storage (alert_en_shadowed_71_storage_err) + ); + + + // Subregister 72 of Multireg alert_en_shadowed + // R[alert_en_shadowed_72]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_72_gated_we; + assign alert_en_shadowed_72_gated_we = alert_en_shadowed_72_we & alert_regwen_72_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_72_re), + .we (alert_en_shadowed_72_gated_we), + .wd (alert_en_shadowed_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[72].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_72_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_72_update_err), + .err_storage (alert_en_shadowed_72_storage_err) + ); + + + // Subregister 73 of Multireg alert_en_shadowed + // R[alert_en_shadowed_73]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_73_gated_we; + assign alert_en_shadowed_73_gated_we = alert_en_shadowed_73_we & alert_regwen_73_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_73_re), + .we (alert_en_shadowed_73_gated_we), + .wd (alert_en_shadowed_73_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[73].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_73_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_73_update_err), + .err_storage (alert_en_shadowed_73_storage_err) + ); + + + // Subregister 74 of Multireg alert_en_shadowed + // R[alert_en_shadowed_74]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_74_gated_we; + assign alert_en_shadowed_74_gated_we = alert_en_shadowed_74_we & alert_regwen_74_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_74_re), + .we (alert_en_shadowed_74_gated_we), + .wd (alert_en_shadowed_74_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[74].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_74_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_74_update_err), + .err_storage (alert_en_shadowed_74_storage_err) + ); + + + // Subregister 75 of Multireg alert_en_shadowed + // R[alert_en_shadowed_75]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_75_gated_we; + assign alert_en_shadowed_75_gated_we = alert_en_shadowed_75_we & alert_regwen_75_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_75_re), + .we (alert_en_shadowed_75_gated_we), + .wd (alert_en_shadowed_75_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[75].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_75_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_75_update_err), + .err_storage (alert_en_shadowed_75_storage_err) + ); + + + // Subregister 76 of Multireg alert_en_shadowed + // R[alert_en_shadowed_76]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_76_gated_we; + assign alert_en_shadowed_76_gated_we = alert_en_shadowed_76_we & alert_regwen_76_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_76_re), + .we (alert_en_shadowed_76_gated_we), + .wd (alert_en_shadowed_76_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[76].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_76_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_76_update_err), + .err_storage (alert_en_shadowed_76_storage_err) + ); + + + // Subregister 77 of Multireg alert_en_shadowed + // R[alert_en_shadowed_77]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_77_gated_we; + assign alert_en_shadowed_77_gated_we = alert_en_shadowed_77_we & alert_regwen_77_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_77_re), + .we (alert_en_shadowed_77_gated_we), + .wd (alert_en_shadowed_77_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[77].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_77_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_77_update_err), + .err_storage (alert_en_shadowed_77_storage_err) + ); + + + // Subregister 78 of Multireg alert_en_shadowed + // R[alert_en_shadowed_78]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_78_gated_we; + assign alert_en_shadowed_78_gated_we = alert_en_shadowed_78_we & alert_regwen_78_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_78_re), + .we (alert_en_shadowed_78_gated_we), + .wd (alert_en_shadowed_78_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[78].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_78_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_78_update_err), + .err_storage (alert_en_shadowed_78_storage_err) + ); + + + // Subregister 79 of Multireg alert_en_shadowed + // R[alert_en_shadowed_79]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_79_gated_we; + assign alert_en_shadowed_79_gated_we = alert_en_shadowed_79_we & alert_regwen_79_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_79_re), + .we (alert_en_shadowed_79_gated_we), + .wd (alert_en_shadowed_79_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[79].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_79_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_79_update_err), + .err_storage (alert_en_shadowed_79_storage_err) + ); + + + // Subregister 80 of Multireg alert_en_shadowed + // R[alert_en_shadowed_80]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_80_gated_we; + assign alert_en_shadowed_80_gated_we = alert_en_shadowed_80_we & alert_regwen_80_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_80_re), + .we (alert_en_shadowed_80_gated_we), + .wd (alert_en_shadowed_80_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[80].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_80_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_80_update_err), + .err_storage (alert_en_shadowed_80_storage_err) + ); + + + // Subregister 81 of Multireg alert_en_shadowed + // R[alert_en_shadowed_81]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_81_gated_we; + assign alert_en_shadowed_81_gated_we = alert_en_shadowed_81_we & alert_regwen_81_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_81_re), + .we (alert_en_shadowed_81_gated_we), + .wd (alert_en_shadowed_81_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[81].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_81_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_81_update_err), + .err_storage (alert_en_shadowed_81_storage_err) + ); + + + // Subregister 82 of Multireg alert_en_shadowed + // R[alert_en_shadowed_82]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_82_gated_we; + assign alert_en_shadowed_82_gated_we = alert_en_shadowed_82_we & alert_regwen_82_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_82_re), + .we (alert_en_shadowed_82_gated_we), + .wd (alert_en_shadowed_82_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[82].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_82_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_82_update_err), + .err_storage (alert_en_shadowed_82_storage_err) + ); + + + // Subregister 83 of Multireg alert_en_shadowed + // R[alert_en_shadowed_83]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_83_gated_we; + assign alert_en_shadowed_83_gated_we = alert_en_shadowed_83_we & alert_regwen_83_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_83_re), + .we (alert_en_shadowed_83_gated_we), + .wd (alert_en_shadowed_83_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[83].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_83_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_83_update_err), + .err_storage (alert_en_shadowed_83_storage_err) + ); + + + // Subregister 84 of Multireg alert_en_shadowed + // R[alert_en_shadowed_84]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_84_gated_we; + assign alert_en_shadowed_84_gated_we = alert_en_shadowed_84_we & alert_regwen_84_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_84_re), + .we (alert_en_shadowed_84_gated_we), + .wd (alert_en_shadowed_84_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[84].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_84_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_84_update_err), + .err_storage (alert_en_shadowed_84_storage_err) + ); + + + // Subregister 85 of Multireg alert_en_shadowed + // R[alert_en_shadowed_85]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_85_gated_we; + assign alert_en_shadowed_85_gated_we = alert_en_shadowed_85_we & alert_regwen_85_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_85_re), + .we (alert_en_shadowed_85_gated_we), + .wd (alert_en_shadowed_85_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[85].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_85_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_85_update_err), + .err_storage (alert_en_shadowed_85_storage_err) + ); + + + // Subregister 86 of Multireg alert_en_shadowed + // R[alert_en_shadowed_86]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_86_gated_we; + assign alert_en_shadowed_86_gated_we = alert_en_shadowed_86_we & alert_regwen_86_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_86_re), + .we (alert_en_shadowed_86_gated_we), + .wd (alert_en_shadowed_86_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[86].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_86_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_86_update_err), + .err_storage (alert_en_shadowed_86_storage_err) + ); + + + // Subregister 87 of Multireg alert_en_shadowed + // R[alert_en_shadowed_87]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_87_gated_we; + assign alert_en_shadowed_87_gated_we = alert_en_shadowed_87_we & alert_regwen_87_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_87_re), + .we (alert_en_shadowed_87_gated_we), + .wd (alert_en_shadowed_87_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[87].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_87_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_87_update_err), + .err_storage (alert_en_shadowed_87_storage_err) + ); + + + // Subregister 88 of Multireg alert_en_shadowed + // R[alert_en_shadowed_88]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_88_gated_we; + assign alert_en_shadowed_88_gated_we = alert_en_shadowed_88_we & alert_regwen_88_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_88_re), + .we (alert_en_shadowed_88_gated_we), + .wd (alert_en_shadowed_88_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[88].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_88_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_88_update_err), + .err_storage (alert_en_shadowed_88_storage_err) + ); + + + // Subregister 89 of Multireg alert_en_shadowed + // R[alert_en_shadowed_89]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_89_gated_we; + assign alert_en_shadowed_89_gated_we = alert_en_shadowed_89_we & alert_regwen_89_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_89_re), + .we (alert_en_shadowed_89_gated_we), + .wd (alert_en_shadowed_89_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[89].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_89_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_89_update_err), + .err_storage (alert_en_shadowed_89_storage_err) + ); + + + // Subregister 90 of Multireg alert_en_shadowed + // R[alert_en_shadowed_90]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_90_gated_we; + assign alert_en_shadowed_90_gated_we = alert_en_shadowed_90_we & alert_regwen_90_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_90_re), + .we (alert_en_shadowed_90_gated_we), + .wd (alert_en_shadowed_90_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[90].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_90_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_90_update_err), + .err_storage (alert_en_shadowed_90_storage_err) + ); + + + // Subregister 91 of Multireg alert_en_shadowed + // R[alert_en_shadowed_91]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_91_gated_we; + assign alert_en_shadowed_91_gated_we = alert_en_shadowed_91_we & alert_regwen_91_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_91_re), + .we (alert_en_shadowed_91_gated_we), + .wd (alert_en_shadowed_91_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[91].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_91_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_91_update_err), + .err_storage (alert_en_shadowed_91_storage_err) + ); + + + // Subregister 92 of Multireg alert_en_shadowed + // R[alert_en_shadowed_92]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_92_gated_we; + assign alert_en_shadowed_92_gated_we = alert_en_shadowed_92_we & alert_regwen_92_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_92_re), + .we (alert_en_shadowed_92_gated_we), + .wd (alert_en_shadowed_92_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[92].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_92_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_92_update_err), + .err_storage (alert_en_shadowed_92_storage_err) + ); + + + // Subregister 93 of Multireg alert_en_shadowed + // R[alert_en_shadowed_93]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_93_gated_we; + assign alert_en_shadowed_93_gated_we = alert_en_shadowed_93_we & alert_regwen_93_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_93_re), + .we (alert_en_shadowed_93_gated_we), + .wd (alert_en_shadowed_93_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[93].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_93_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_93_update_err), + .err_storage (alert_en_shadowed_93_storage_err) + ); + + + // Subregister 94 of Multireg alert_en_shadowed + // R[alert_en_shadowed_94]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_94_gated_we; + assign alert_en_shadowed_94_gated_we = alert_en_shadowed_94_we & alert_regwen_94_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_94_re), + .we (alert_en_shadowed_94_gated_we), + .wd (alert_en_shadowed_94_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[94].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_94_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_94_update_err), + .err_storage (alert_en_shadowed_94_storage_err) + ); + + + // Subregister 95 of Multireg alert_en_shadowed + // R[alert_en_shadowed_95]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_95_gated_we; + assign alert_en_shadowed_95_gated_we = alert_en_shadowed_95_we & alert_regwen_95_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_95_re), + .we (alert_en_shadowed_95_gated_we), + .wd (alert_en_shadowed_95_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[95].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_95_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_95_update_err), + .err_storage (alert_en_shadowed_95_storage_err) + ); + + + // Subregister 96 of Multireg alert_en_shadowed + // R[alert_en_shadowed_96]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_96_gated_we; + assign alert_en_shadowed_96_gated_we = alert_en_shadowed_96_we & alert_regwen_96_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_96_re), + .we (alert_en_shadowed_96_gated_we), + .wd (alert_en_shadowed_96_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[96].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_96_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_96_update_err), + .err_storage (alert_en_shadowed_96_storage_err) + ); + + + // Subregister 97 of Multireg alert_en_shadowed + // R[alert_en_shadowed_97]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_97_gated_we; + assign alert_en_shadowed_97_gated_we = alert_en_shadowed_97_we & alert_regwen_97_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_97_re), + .we (alert_en_shadowed_97_gated_we), + .wd (alert_en_shadowed_97_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[97].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_97_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_97_update_err), + .err_storage (alert_en_shadowed_97_storage_err) + ); + + + // Subregister 98 of Multireg alert_en_shadowed + // R[alert_en_shadowed_98]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_98_gated_we; + assign alert_en_shadowed_98_gated_we = alert_en_shadowed_98_we & alert_regwen_98_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_98_re), + .we (alert_en_shadowed_98_gated_we), + .wd (alert_en_shadowed_98_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[98].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_98_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_98_update_err), + .err_storage (alert_en_shadowed_98_storage_err) + ); + + + // Subregister 0 of Multireg alert_class_shadowed + // R[alert_class_shadowed_0]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_0_gated_we; + assign alert_class_shadowed_0_gated_we = alert_class_shadowed_0_we & alert_regwen_0_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_0_re), + .we (alert_class_shadowed_0_gated_we), + .wd (alert_class_shadowed_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[0].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_0_update_err), + .err_storage (alert_class_shadowed_0_storage_err) + ); + + + // Subregister 1 of Multireg alert_class_shadowed + // R[alert_class_shadowed_1]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_1_gated_we; + assign alert_class_shadowed_1_gated_we = alert_class_shadowed_1_we & alert_regwen_1_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_1_re), + .we (alert_class_shadowed_1_gated_we), + .wd (alert_class_shadowed_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[1].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_1_update_err), + .err_storage (alert_class_shadowed_1_storage_err) + ); + + + // Subregister 2 of Multireg alert_class_shadowed + // R[alert_class_shadowed_2]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_2_gated_we; + assign alert_class_shadowed_2_gated_we = alert_class_shadowed_2_we & alert_regwen_2_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_2_re), + .we (alert_class_shadowed_2_gated_we), + .wd (alert_class_shadowed_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[2].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_2_update_err), + .err_storage (alert_class_shadowed_2_storage_err) + ); + + + // Subregister 3 of Multireg alert_class_shadowed + // R[alert_class_shadowed_3]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_3_gated_we; + assign alert_class_shadowed_3_gated_we = alert_class_shadowed_3_we & alert_regwen_3_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_3_re), + .we (alert_class_shadowed_3_gated_we), + .wd (alert_class_shadowed_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[3].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_3_update_err), + .err_storage (alert_class_shadowed_3_storage_err) + ); + + + // Subregister 4 of Multireg alert_class_shadowed + // R[alert_class_shadowed_4]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_4_gated_we; + assign alert_class_shadowed_4_gated_we = alert_class_shadowed_4_we & alert_regwen_4_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_4_re), + .we (alert_class_shadowed_4_gated_we), + .wd (alert_class_shadowed_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[4].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_4_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_4_update_err), + .err_storage (alert_class_shadowed_4_storage_err) + ); + + + // Subregister 5 of Multireg alert_class_shadowed + // R[alert_class_shadowed_5]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_5_gated_we; + assign alert_class_shadowed_5_gated_we = alert_class_shadowed_5_we & alert_regwen_5_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_5_re), + .we (alert_class_shadowed_5_gated_we), + .wd (alert_class_shadowed_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[5].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_5_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_5_update_err), + .err_storage (alert_class_shadowed_5_storage_err) + ); + + + // Subregister 6 of Multireg alert_class_shadowed + // R[alert_class_shadowed_6]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_6_gated_we; + assign alert_class_shadowed_6_gated_we = alert_class_shadowed_6_we & alert_regwen_6_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_6_re), + .we (alert_class_shadowed_6_gated_we), + .wd (alert_class_shadowed_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[6].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_6_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_6_update_err), + .err_storage (alert_class_shadowed_6_storage_err) + ); + + + // Subregister 7 of Multireg alert_class_shadowed + // R[alert_class_shadowed_7]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_7_gated_we; + assign alert_class_shadowed_7_gated_we = alert_class_shadowed_7_we & alert_regwen_7_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_7_re), + .we (alert_class_shadowed_7_gated_we), + .wd (alert_class_shadowed_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[7].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_7_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_7_update_err), + .err_storage (alert_class_shadowed_7_storage_err) + ); + + + // Subregister 8 of Multireg alert_class_shadowed + // R[alert_class_shadowed_8]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_8_gated_we; + assign alert_class_shadowed_8_gated_we = alert_class_shadowed_8_we & alert_regwen_8_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_8_re), + .we (alert_class_shadowed_8_gated_we), + .wd (alert_class_shadowed_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[8].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_8_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_8_update_err), + .err_storage (alert_class_shadowed_8_storage_err) + ); + + + // Subregister 9 of Multireg alert_class_shadowed + // R[alert_class_shadowed_9]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_9_gated_we; + assign alert_class_shadowed_9_gated_we = alert_class_shadowed_9_we & alert_regwen_9_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_9_re), + .we (alert_class_shadowed_9_gated_we), + .wd (alert_class_shadowed_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[9].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_9_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_9_update_err), + .err_storage (alert_class_shadowed_9_storage_err) + ); + + + // Subregister 10 of Multireg alert_class_shadowed + // R[alert_class_shadowed_10]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_10_gated_we; + assign alert_class_shadowed_10_gated_we = alert_class_shadowed_10_we & alert_regwen_10_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_10_re), + .we (alert_class_shadowed_10_gated_we), + .wd (alert_class_shadowed_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[10].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_10_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_10_update_err), + .err_storage (alert_class_shadowed_10_storage_err) + ); + + + // Subregister 11 of Multireg alert_class_shadowed + // R[alert_class_shadowed_11]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_11_gated_we; + assign alert_class_shadowed_11_gated_we = alert_class_shadowed_11_we & alert_regwen_11_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_11_re), + .we (alert_class_shadowed_11_gated_we), + .wd (alert_class_shadowed_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[11].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_11_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_11_update_err), + .err_storage (alert_class_shadowed_11_storage_err) + ); + + + // Subregister 12 of Multireg alert_class_shadowed + // R[alert_class_shadowed_12]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_12_gated_we; + assign alert_class_shadowed_12_gated_we = alert_class_shadowed_12_we & alert_regwen_12_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_12_re), + .we (alert_class_shadowed_12_gated_we), + .wd (alert_class_shadowed_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[12].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_12_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_12_update_err), + .err_storage (alert_class_shadowed_12_storage_err) + ); + + + // Subregister 13 of Multireg alert_class_shadowed + // R[alert_class_shadowed_13]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_13_gated_we; + assign alert_class_shadowed_13_gated_we = alert_class_shadowed_13_we & alert_regwen_13_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_13_re), + .we (alert_class_shadowed_13_gated_we), + .wd (alert_class_shadowed_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[13].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_13_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_13_update_err), + .err_storage (alert_class_shadowed_13_storage_err) + ); + + + // Subregister 14 of Multireg alert_class_shadowed + // R[alert_class_shadowed_14]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_14_gated_we; + assign alert_class_shadowed_14_gated_we = alert_class_shadowed_14_we & alert_regwen_14_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_14_re), + .we (alert_class_shadowed_14_gated_we), + .wd (alert_class_shadowed_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[14].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_14_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_14_update_err), + .err_storage (alert_class_shadowed_14_storage_err) + ); + + + // Subregister 15 of Multireg alert_class_shadowed + // R[alert_class_shadowed_15]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_15_gated_we; + assign alert_class_shadowed_15_gated_we = alert_class_shadowed_15_we & alert_regwen_15_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_15_re), + .we (alert_class_shadowed_15_gated_we), + .wd (alert_class_shadowed_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[15].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_15_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_15_update_err), + .err_storage (alert_class_shadowed_15_storage_err) + ); + + + // Subregister 16 of Multireg alert_class_shadowed + // R[alert_class_shadowed_16]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_16_gated_we; + assign alert_class_shadowed_16_gated_we = alert_class_shadowed_16_we & alert_regwen_16_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_16_re), + .we (alert_class_shadowed_16_gated_we), + .wd (alert_class_shadowed_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[16].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_16_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_16_update_err), + .err_storage (alert_class_shadowed_16_storage_err) + ); + + + // Subregister 17 of Multireg alert_class_shadowed + // R[alert_class_shadowed_17]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_17_gated_we; + assign alert_class_shadowed_17_gated_we = alert_class_shadowed_17_we & alert_regwen_17_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_17_re), + .we (alert_class_shadowed_17_gated_we), + .wd (alert_class_shadowed_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[17].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_17_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_17_update_err), + .err_storage (alert_class_shadowed_17_storage_err) + ); + + + // Subregister 18 of Multireg alert_class_shadowed + // R[alert_class_shadowed_18]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_18_gated_we; + assign alert_class_shadowed_18_gated_we = alert_class_shadowed_18_we & alert_regwen_18_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_18_re), + .we (alert_class_shadowed_18_gated_we), + .wd (alert_class_shadowed_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[18].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_18_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_18_update_err), + .err_storage (alert_class_shadowed_18_storage_err) + ); + + + // Subregister 19 of Multireg alert_class_shadowed + // R[alert_class_shadowed_19]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_19_gated_we; + assign alert_class_shadowed_19_gated_we = alert_class_shadowed_19_we & alert_regwen_19_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_19_re), + .we (alert_class_shadowed_19_gated_we), + .wd (alert_class_shadowed_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[19].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_19_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_19_update_err), + .err_storage (alert_class_shadowed_19_storage_err) + ); + + + // Subregister 20 of Multireg alert_class_shadowed + // R[alert_class_shadowed_20]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_20_gated_we; + assign alert_class_shadowed_20_gated_we = alert_class_shadowed_20_we & alert_regwen_20_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_20_re), + .we (alert_class_shadowed_20_gated_we), + .wd (alert_class_shadowed_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[20].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_20_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_20_update_err), + .err_storage (alert_class_shadowed_20_storage_err) + ); + + + // Subregister 21 of Multireg alert_class_shadowed + // R[alert_class_shadowed_21]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_21_gated_we; + assign alert_class_shadowed_21_gated_we = alert_class_shadowed_21_we & alert_regwen_21_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_21_re), + .we (alert_class_shadowed_21_gated_we), + .wd (alert_class_shadowed_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[21].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_21_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_21_update_err), + .err_storage (alert_class_shadowed_21_storage_err) + ); + + + // Subregister 22 of Multireg alert_class_shadowed + // R[alert_class_shadowed_22]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_22_gated_we; + assign alert_class_shadowed_22_gated_we = alert_class_shadowed_22_we & alert_regwen_22_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_22_re), + .we (alert_class_shadowed_22_gated_we), + .wd (alert_class_shadowed_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[22].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_22_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_22_update_err), + .err_storage (alert_class_shadowed_22_storage_err) + ); + + + // Subregister 23 of Multireg alert_class_shadowed + // R[alert_class_shadowed_23]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_23_gated_we; + assign alert_class_shadowed_23_gated_we = alert_class_shadowed_23_we & alert_regwen_23_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_23_re), + .we (alert_class_shadowed_23_gated_we), + .wd (alert_class_shadowed_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[23].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_23_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_23_update_err), + .err_storage (alert_class_shadowed_23_storage_err) + ); + + + // Subregister 24 of Multireg alert_class_shadowed + // R[alert_class_shadowed_24]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_24_gated_we; + assign alert_class_shadowed_24_gated_we = alert_class_shadowed_24_we & alert_regwen_24_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_24_re), + .we (alert_class_shadowed_24_gated_we), + .wd (alert_class_shadowed_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[24].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_24_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_24_update_err), + .err_storage (alert_class_shadowed_24_storage_err) + ); + + + // Subregister 25 of Multireg alert_class_shadowed + // R[alert_class_shadowed_25]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_25_gated_we; + assign alert_class_shadowed_25_gated_we = alert_class_shadowed_25_we & alert_regwen_25_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_25_re), + .we (alert_class_shadowed_25_gated_we), + .wd (alert_class_shadowed_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[25].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_25_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_25_update_err), + .err_storage (alert_class_shadowed_25_storage_err) + ); + + + // Subregister 26 of Multireg alert_class_shadowed + // R[alert_class_shadowed_26]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_26_gated_we; + assign alert_class_shadowed_26_gated_we = alert_class_shadowed_26_we & alert_regwen_26_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_26_re), + .we (alert_class_shadowed_26_gated_we), + .wd (alert_class_shadowed_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[26].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_26_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_26_update_err), + .err_storage (alert_class_shadowed_26_storage_err) + ); + + + // Subregister 27 of Multireg alert_class_shadowed + // R[alert_class_shadowed_27]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_27_gated_we; + assign alert_class_shadowed_27_gated_we = alert_class_shadowed_27_we & alert_regwen_27_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_27_re), + .we (alert_class_shadowed_27_gated_we), + .wd (alert_class_shadowed_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[27].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_27_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_27_update_err), + .err_storage (alert_class_shadowed_27_storage_err) + ); + + + // Subregister 28 of Multireg alert_class_shadowed + // R[alert_class_shadowed_28]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_28_gated_we; + assign alert_class_shadowed_28_gated_we = alert_class_shadowed_28_we & alert_regwen_28_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_28_re), + .we (alert_class_shadowed_28_gated_we), + .wd (alert_class_shadowed_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[28].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_28_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_28_update_err), + .err_storage (alert_class_shadowed_28_storage_err) + ); + + + // Subregister 29 of Multireg alert_class_shadowed + // R[alert_class_shadowed_29]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_29_gated_we; + assign alert_class_shadowed_29_gated_we = alert_class_shadowed_29_we & alert_regwen_29_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_29_re), + .we (alert_class_shadowed_29_gated_we), + .wd (alert_class_shadowed_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[29].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_29_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_29_update_err), + .err_storage (alert_class_shadowed_29_storage_err) + ); + + + // Subregister 30 of Multireg alert_class_shadowed + // R[alert_class_shadowed_30]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_30_gated_we; + assign alert_class_shadowed_30_gated_we = alert_class_shadowed_30_we & alert_regwen_30_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_30_re), + .we (alert_class_shadowed_30_gated_we), + .wd (alert_class_shadowed_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[30].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_30_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_30_update_err), + .err_storage (alert_class_shadowed_30_storage_err) + ); + + + // Subregister 31 of Multireg alert_class_shadowed + // R[alert_class_shadowed_31]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_31_gated_we; + assign alert_class_shadowed_31_gated_we = alert_class_shadowed_31_we & alert_regwen_31_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_31_re), + .we (alert_class_shadowed_31_gated_we), + .wd (alert_class_shadowed_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[31].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_31_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_31_update_err), + .err_storage (alert_class_shadowed_31_storage_err) + ); + + + // Subregister 32 of Multireg alert_class_shadowed + // R[alert_class_shadowed_32]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_32_gated_we; + assign alert_class_shadowed_32_gated_we = alert_class_shadowed_32_we & alert_regwen_32_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_32_re), + .we (alert_class_shadowed_32_gated_we), + .wd (alert_class_shadowed_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[32].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_32_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_32_update_err), + .err_storage (alert_class_shadowed_32_storage_err) + ); + + + // Subregister 33 of Multireg alert_class_shadowed + // R[alert_class_shadowed_33]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_33_gated_we; + assign alert_class_shadowed_33_gated_we = alert_class_shadowed_33_we & alert_regwen_33_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_33_re), + .we (alert_class_shadowed_33_gated_we), + .wd (alert_class_shadowed_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[33].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_33_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_33_update_err), + .err_storage (alert_class_shadowed_33_storage_err) + ); + + + // Subregister 34 of Multireg alert_class_shadowed + // R[alert_class_shadowed_34]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_34_gated_we; + assign alert_class_shadowed_34_gated_we = alert_class_shadowed_34_we & alert_regwen_34_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_34_re), + .we (alert_class_shadowed_34_gated_we), + .wd (alert_class_shadowed_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[34].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_34_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_34_update_err), + .err_storage (alert_class_shadowed_34_storage_err) + ); + + + // Subregister 35 of Multireg alert_class_shadowed + // R[alert_class_shadowed_35]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_35_gated_we; + assign alert_class_shadowed_35_gated_we = alert_class_shadowed_35_we & alert_regwen_35_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_35_re), + .we (alert_class_shadowed_35_gated_we), + .wd (alert_class_shadowed_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[35].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_35_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_35_update_err), + .err_storage (alert_class_shadowed_35_storage_err) + ); + + + // Subregister 36 of Multireg alert_class_shadowed + // R[alert_class_shadowed_36]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_36_gated_we; + assign alert_class_shadowed_36_gated_we = alert_class_shadowed_36_we & alert_regwen_36_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_36_re), + .we (alert_class_shadowed_36_gated_we), + .wd (alert_class_shadowed_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[36].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_36_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_36_update_err), + .err_storage (alert_class_shadowed_36_storage_err) + ); + + + // Subregister 37 of Multireg alert_class_shadowed + // R[alert_class_shadowed_37]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_37_gated_we; + assign alert_class_shadowed_37_gated_we = alert_class_shadowed_37_we & alert_regwen_37_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_37_re), + .we (alert_class_shadowed_37_gated_we), + .wd (alert_class_shadowed_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[37].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_37_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_37_update_err), + .err_storage (alert_class_shadowed_37_storage_err) + ); + + + // Subregister 38 of Multireg alert_class_shadowed + // R[alert_class_shadowed_38]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_38_gated_we; + assign alert_class_shadowed_38_gated_we = alert_class_shadowed_38_we & alert_regwen_38_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_38_re), + .we (alert_class_shadowed_38_gated_we), + .wd (alert_class_shadowed_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[38].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_38_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_38_update_err), + .err_storage (alert_class_shadowed_38_storage_err) + ); + + + // Subregister 39 of Multireg alert_class_shadowed + // R[alert_class_shadowed_39]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_39_gated_we; + assign alert_class_shadowed_39_gated_we = alert_class_shadowed_39_we & alert_regwen_39_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_39_re), + .we (alert_class_shadowed_39_gated_we), + .wd (alert_class_shadowed_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[39].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_39_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_39_update_err), + .err_storage (alert_class_shadowed_39_storage_err) + ); + + + // Subregister 40 of Multireg alert_class_shadowed + // R[alert_class_shadowed_40]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_40_gated_we; + assign alert_class_shadowed_40_gated_we = alert_class_shadowed_40_we & alert_regwen_40_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_40_re), + .we (alert_class_shadowed_40_gated_we), + .wd (alert_class_shadowed_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[40].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_40_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_40_update_err), + .err_storage (alert_class_shadowed_40_storage_err) + ); + + + // Subregister 41 of Multireg alert_class_shadowed + // R[alert_class_shadowed_41]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_41_gated_we; + assign alert_class_shadowed_41_gated_we = alert_class_shadowed_41_we & alert_regwen_41_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_41_re), + .we (alert_class_shadowed_41_gated_we), + .wd (alert_class_shadowed_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[41].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_41_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_41_update_err), + .err_storage (alert_class_shadowed_41_storage_err) + ); + + + // Subregister 42 of Multireg alert_class_shadowed + // R[alert_class_shadowed_42]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_42_gated_we; + assign alert_class_shadowed_42_gated_we = alert_class_shadowed_42_we & alert_regwen_42_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_42_re), + .we (alert_class_shadowed_42_gated_we), + .wd (alert_class_shadowed_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[42].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_42_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_42_update_err), + .err_storage (alert_class_shadowed_42_storage_err) + ); + + + // Subregister 43 of Multireg alert_class_shadowed + // R[alert_class_shadowed_43]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_43_gated_we; + assign alert_class_shadowed_43_gated_we = alert_class_shadowed_43_we & alert_regwen_43_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_43_re), + .we (alert_class_shadowed_43_gated_we), + .wd (alert_class_shadowed_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[43].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_43_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_43_update_err), + .err_storage (alert_class_shadowed_43_storage_err) + ); + + + // Subregister 44 of Multireg alert_class_shadowed + // R[alert_class_shadowed_44]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_44_gated_we; + assign alert_class_shadowed_44_gated_we = alert_class_shadowed_44_we & alert_regwen_44_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_44_re), + .we (alert_class_shadowed_44_gated_we), + .wd (alert_class_shadowed_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[44].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_44_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_44_update_err), + .err_storage (alert_class_shadowed_44_storage_err) + ); + + + // Subregister 45 of Multireg alert_class_shadowed + // R[alert_class_shadowed_45]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_45_gated_we; + assign alert_class_shadowed_45_gated_we = alert_class_shadowed_45_we & alert_regwen_45_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_45_re), + .we (alert_class_shadowed_45_gated_we), + .wd (alert_class_shadowed_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[45].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_45_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_45_update_err), + .err_storage (alert_class_shadowed_45_storage_err) + ); + + + // Subregister 46 of Multireg alert_class_shadowed + // R[alert_class_shadowed_46]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_46_gated_we; + assign alert_class_shadowed_46_gated_we = alert_class_shadowed_46_we & alert_regwen_46_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_46_re), + .we (alert_class_shadowed_46_gated_we), + .wd (alert_class_shadowed_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[46].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_46_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_46_update_err), + .err_storage (alert_class_shadowed_46_storage_err) + ); + + + // Subregister 47 of Multireg alert_class_shadowed + // R[alert_class_shadowed_47]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_47_gated_we; + assign alert_class_shadowed_47_gated_we = alert_class_shadowed_47_we & alert_regwen_47_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_47_re), + .we (alert_class_shadowed_47_gated_we), + .wd (alert_class_shadowed_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[47].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_47_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_47_update_err), + .err_storage (alert_class_shadowed_47_storage_err) + ); + + + // Subregister 48 of Multireg alert_class_shadowed + // R[alert_class_shadowed_48]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_48_gated_we; + assign alert_class_shadowed_48_gated_we = alert_class_shadowed_48_we & alert_regwen_48_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_48_re), + .we (alert_class_shadowed_48_gated_we), + .wd (alert_class_shadowed_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[48].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_48_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_48_update_err), + .err_storage (alert_class_shadowed_48_storage_err) + ); + + + // Subregister 49 of Multireg alert_class_shadowed + // R[alert_class_shadowed_49]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_49_gated_we; + assign alert_class_shadowed_49_gated_we = alert_class_shadowed_49_we & alert_regwen_49_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_49_re), + .we (alert_class_shadowed_49_gated_we), + .wd (alert_class_shadowed_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[49].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_49_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_49_update_err), + .err_storage (alert_class_shadowed_49_storage_err) + ); + + + // Subregister 50 of Multireg alert_class_shadowed + // R[alert_class_shadowed_50]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_50_gated_we; + assign alert_class_shadowed_50_gated_we = alert_class_shadowed_50_we & alert_regwen_50_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_50_re), + .we (alert_class_shadowed_50_gated_we), + .wd (alert_class_shadowed_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[50].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_50_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_50_update_err), + .err_storage (alert_class_shadowed_50_storage_err) + ); + + + // Subregister 51 of Multireg alert_class_shadowed + // R[alert_class_shadowed_51]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_51_gated_we; + assign alert_class_shadowed_51_gated_we = alert_class_shadowed_51_we & alert_regwen_51_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_51_re), + .we (alert_class_shadowed_51_gated_we), + .wd (alert_class_shadowed_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[51].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_51_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_51_update_err), + .err_storage (alert_class_shadowed_51_storage_err) + ); + + + // Subregister 52 of Multireg alert_class_shadowed + // R[alert_class_shadowed_52]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_52_gated_we; + assign alert_class_shadowed_52_gated_we = alert_class_shadowed_52_we & alert_regwen_52_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_52_re), + .we (alert_class_shadowed_52_gated_we), + .wd (alert_class_shadowed_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[52].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_52_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_52_update_err), + .err_storage (alert_class_shadowed_52_storage_err) + ); + + + // Subregister 53 of Multireg alert_class_shadowed + // R[alert_class_shadowed_53]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_53_gated_we; + assign alert_class_shadowed_53_gated_we = alert_class_shadowed_53_we & alert_regwen_53_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_53_re), + .we (alert_class_shadowed_53_gated_we), + .wd (alert_class_shadowed_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[53].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_53_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_53_update_err), + .err_storage (alert_class_shadowed_53_storage_err) + ); + + + // Subregister 54 of Multireg alert_class_shadowed + // R[alert_class_shadowed_54]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_54_gated_we; + assign alert_class_shadowed_54_gated_we = alert_class_shadowed_54_we & alert_regwen_54_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_54_re), + .we (alert_class_shadowed_54_gated_we), + .wd (alert_class_shadowed_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[54].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_54_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_54_update_err), + .err_storage (alert_class_shadowed_54_storage_err) + ); + + + // Subregister 55 of Multireg alert_class_shadowed + // R[alert_class_shadowed_55]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_55_gated_we; + assign alert_class_shadowed_55_gated_we = alert_class_shadowed_55_we & alert_regwen_55_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_55_re), + .we (alert_class_shadowed_55_gated_we), + .wd (alert_class_shadowed_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[55].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_55_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_55_update_err), + .err_storage (alert_class_shadowed_55_storage_err) + ); + + + // Subregister 56 of Multireg alert_class_shadowed + // R[alert_class_shadowed_56]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_56_gated_we; + assign alert_class_shadowed_56_gated_we = alert_class_shadowed_56_we & alert_regwen_56_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_56_re), + .we (alert_class_shadowed_56_gated_we), + .wd (alert_class_shadowed_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[56].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_56_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_56_update_err), + .err_storage (alert_class_shadowed_56_storage_err) + ); + + + // Subregister 57 of Multireg alert_class_shadowed + // R[alert_class_shadowed_57]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_57_gated_we; + assign alert_class_shadowed_57_gated_we = alert_class_shadowed_57_we & alert_regwen_57_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_57_re), + .we (alert_class_shadowed_57_gated_we), + .wd (alert_class_shadowed_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[57].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_57_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_57_update_err), + .err_storage (alert_class_shadowed_57_storage_err) + ); + + + // Subregister 58 of Multireg alert_class_shadowed + // R[alert_class_shadowed_58]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_58_gated_we; + assign alert_class_shadowed_58_gated_we = alert_class_shadowed_58_we & alert_regwen_58_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_58_re), + .we (alert_class_shadowed_58_gated_we), + .wd (alert_class_shadowed_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[58].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_58_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_58_update_err), + .err_storage (alert_class_shadowed_58_storage_err) + ); + + + // Subregister 59 of Multireg alert_class_shadowed + // R[alert_class_shadowed_59]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_59_gated_we; + assign alert_class_shadowed_59_gated_we = alert_class_shadowed_59_we & alert_regwen_59_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_59_re), + .we (alert_class_shadowed_59_gated_we), + .wd (alert_class_shadowed_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[59].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_59_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_59_update_err), + .err_storage (alert_class_shadowed_59_storage_err) + ); + + + // Subregister 60 of Multireg alert_class_shadowed + // R[alert_class_shadowed_60]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_60_gated_we; + assign alert_class_shadowed_60_gated_we = alert_class_shadowed_60_we & alert_regwen_60_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_60_re), + .we (alert_class_shadowed_60_gated_we), + .wd (alert_class_shadowed_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[60].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_60_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_60_update_err), + .err_storage (alert_class_shadowed_60_storage_err) + ); + + + // Subregister 61 of Multireg alert_class_shadowed + // R[alert_class_shadowed_61]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_61_gated_we; + assign alert_class_shadowed_61_gated_we = alert_class_shadowed_61_we & alert_regwen_61_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_61_re), + .we (alert_class_shadowed_61_gated_we), + .wd (alert_class_shadowed_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[61].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_61_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_61_update_err), + .err_storage (alert_class_shadowed_61_storage_err) + ); + + + // Subregister 62 of Multireg alert_class_shadowed + // R[alert_class_shadowed_62]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_62_gated_we; + assign alert_class_shadowed_62_gated_we = alert_class_shadowed_62_we & alert_regwen_62_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_62_re), + .we (alert_class_shadowed_62_gated_we), + .wd (alert_class_shadowed_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[62].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_62_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_62_update_err), + .err_storage (alert_class_shadowed_62_storage_err) + ); + + + // Subregister 63 of Multireg alert_class_shadowed + // R[alert_class_shadowed_63]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_63_gated_we; + assign alert_class_shadowed_63_gated_we = alert_class_shadowed_63_we & alert_regwen_63_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_63_re), + .we (alert_class_shadowed_63_gated_we), + .wd (alert_class_shadowed_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[63].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_63_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_63_update_err), + .err_storage (alert_class_shadowed_63_storage_err) + ); + + + // Subregister 64 of Multireg alert_class_shadowed + // R[alert_class_shadowed_64]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_64_gated_we; + assign alert_class_shadowed_64_gated_we = alert_class_shadowed_64_we & alert_regwen_64_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_64_re), + .we (alert_class_shadowed_64_gated_we), + .wd (alert_class_shadowed_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[64].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_64_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_64_update_err), + .err_storage (alert_class_shadowed_64_storage_err) + ); + + + // Subregister 65 of Multireg alert_class_shadowed + // R[alert_class_shadowed_65]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_65_gated_we; + assign alert_class_shadowed_65_gated_we = alert_class_shadowed_65_we & alert_regwen_65_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_65_re), + .we (alert_class_shadowed_65_gated_we), + .wd (alert_class_shadowed_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[65].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_65_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_65_update_err), + .err_storage (alert_class_shadowed_65_storage_err) + ); + + + // Subregister 66 of Multireg alert_class_shadowed + // R[alert_class_shadowed_66]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_66_gated_we; + assign alert_class_shadowed_66_gated_we = alert_class_shadowed_66_we & alert_regwen_66_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_66_re), + .we (alert_class_shadowed_66_gated_we), + .wd (alert_class_shadowed_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[66].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_66_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_66_update_err), + .err_storage (alert_class_shadowed_66_storage_err) + ); + + + // Subregister 67 of Multireg alert_class_shadowed + // R[alert_class_shadowed_67]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_67_gated_we; + assign alert_class_shadowed_67_gated_we = alert_class_shadowed_67_we & alert_regwen_67_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_67_re), + .we (alert_class_shadowed_67_gated_we), + .wd (alert_class_shadowed_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[67].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_67_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_67_update_err), + .err_storage (alert_class_shadowed_67_storage_err) + ); + + + // Subregister 68 of Multireg alert_class_shadowed + // R[alert_class_shadowed_68]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_68_gated_we; + assign alert_class_shadowed_68_gated_we = alert_class_shadowed_68_we & alert_regwen_68_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_68_re), + .we (alert_class_shadowed_68_gated_we), + .wd (alert_class_shadowed_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[68].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_68_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_68_update_err), + .err_storage (alert_class_shadowed_68_storage_err) + ); + + + // Subregister 69 of Multireg alert_class_shadowed + // R[alert_class_shadowed_69]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_69_gated_we; + assign alert_class_shadowed_69_gated_we = alert_class_shadowed_69_we & alert_regwen_69_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_69_re), + .we (alert_class_shadowed_69_gated_we), + .wd (alert_class_shadowed_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[69].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_69_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_69_update_err), + .err_storage (alert_class_shadowed_69_storage_err) + ); + + + // Subregister 70 of Multireg alert_class_shadowed + // R[alert_class_shadowed_70]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_70_gated_we; + assign alert_class_shadowed_70_gated_we = alert_class_shadowed_70_we & alert_regwen_70_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_70_re), + .we (alert_class_shadowed_70_gated_we), + .wd (alert_class_shadowed_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[70].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_70_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_70_update_err), + .err_storage (alert_class_shadowed_70_storage_err) + ); + + + // Subregister 71 of Multireg alert_class_shadowed + // R[alert_class_shadowed_71]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_71_gated_we; + assign alert_class_shadowed_71_gated_we = alert_class_shadowed_71_we & alert_regwen_71_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_71_re), + .we (alert_class_shadowed_71_gated_we), + .wd (alert_class_shadowed_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[71].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_71_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_71_update_err), + .err_storage (alert_class_shadowed_71_storage_err) + ); + + + // Subregister 72 of Multireg alert_class_shadowed + // R[alert_class_shadowed_72]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_72_gated_we; + assign alert_class_shadowed_72_gated_we = alert_class_shadowed_72_we & alert_regwen_72_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_72_re), + .we (alert_class_shadowed_72_gated_we), + .wd (alert_class_shadowed_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[72].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_72_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_72_update_err), + .err_storage (alert_class_shadowed_72_storage_err) + ); + + + // Subregister 73 of Multireg alert_class_shadowed + // R[alert_class_shadowed_73]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_73_gated_we; + assign alert_class_shadowed_73_gated_we = alert_class_shadowed_73_we & alert_regwen_73_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_73_re), + .we (alert_class_shadowed_73_gated_we), + .wd (alert_class_shadowed_73_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[73].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_73_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_73_update_err), + .err_storage (alert_class_shadowed_73_storage_err) + ); + + + // Subregister 74 of Multireg alert_class_shadowed + // R[alert_class_shadowed_74]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_74_gated_we; + assign alert_class_shadowed_74_gated_we = alert_class_shadowed_74_we & alert_regwen_74_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_74_re), + .we (alert_class_shadowed_74_gated_we), + .wd (alert_class_shadowed_74_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[74].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_74_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_74_update_err), + .err_storage (alert_class_shadowed_74_storage_err) + ); + + + // Subregister 75 of Multireg alert_class_shadowed + // R[alert_class_shadowed_75]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_75_gated_we; + assign alert_class_shadowed_75_gated_we = alert_class_shadowed_75_we & alert_regwen_75_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_75_re), + .we (alert_class_shadowed_75_gated_we), + .wd (alert_class_shadowed_75_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[75].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_75_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_75_update_err), + .err_storage (alert_class_shadowed_75_storage_err) + ); + + + // Subregister 76 of Multireg alert_class_shadowed + // R[alert_class_shadowed_76]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_76_gated_we; + assign alert_class_shadowed_76_gated_we = alert_class_shadowed_76_we & alert_regwen_76_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_76_re), + .we (alert_class_shadowed_76_gated_we), + .wd (alert_class_shadowed_76_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[76].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_76_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_76_update_err), + .err_storage (alert_class_shadowed_76_storage_err) + ); + + + // Subregister 77 of Multireg alert_class_shadowed + // R[alert_class_shadowed_77]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_77_gated_we; + assign alert_class_shadowed_77_gated_we = alert_class_shadowed_77_we & alert_regwen_77_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_77_re), + .we (alert_class_shadowed_77_gated_we), + .wd (alert_class_shadowed_77_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[77].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_77_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_77_update_err), + .err_storage (alert_class_shadowed_77_storage_err) + ); + + + // Subregister 78 of Multireg alert_class_shadowed + // R[alert_class_shadowed_78]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_78_gated_we; + assign alert_class_shadowed_78_gated_we = alert_class_shadowed_78_we & alert_regwen_78_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_78_re), + .we (alert_class_shadowed_78_gated_we), + .wd (alert_class_shadowed_78_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[78].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_78_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_78_update_err), + .err_storage (alert_class_shadowed_78_storage_err) + ); + + + // Subregister 79 of Multireg alert_class_shadowed + // R[alert_class_shadowed_79]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_79_gated_we; + assign alert_class_shadowed_79_gated_we = alert_class_shadowed_79_we & alert_regwen_79_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_79_re), + .we (alert_class_shadowed_79_gated_we), + .wd (alert_class_shadowed_79_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[79].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_79_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_79_update_err), + .err_storage (alert_class_shadowed_79_storage_err) + ); + + + // Subregister 80 of Multireg alert_class_shadowed + // R[alert_class_shadowed_80]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_80_gated_we; + assign alert_class_shadowed_80_gated_we = alert_class_shadowed_80_we & alert_regwen_80_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_80_re), + .we (alert_class_shadowed_80_gated_we), + .wd (alert_class_shadowed_80_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[80].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_80_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_80_update_err), + .err_storage (alert_class_shadowed_80_storage_err) + ); + + + // Subregister 81 of Multireg alert_class_shadowed + // R[alert_class_shadowed_81]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_81_gated_we; + assign alert_class_shadowed_81_gated_we = alert_class_shadowed_81_we & alert_regwen_81_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_81_re), + .we (alert_class_shadowed_81_gated_we), + .wd (alert_class_shadowed_81_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[81].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_81_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_81_update_err), + .err_storage (alert_class_shadowed_81_storage_err) + ); + + + // Subregister 82 of Multireg alert_class_shadowed + // R[alert_class_shadowed_82]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_82_gated_we; + assign alert_class_shadowed_82_gated_we = alert_class_shadowed_82_we & alert_regwen_82_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_82_re), + .we (alert_class_shadowed_82_gated_we), + .wd (alert_class_shadowed_82_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[82].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_82_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_82_update_err), + .err_storage (alert_class_shadowed_82_storage_err) + ); + + + // Subregister 83 of Multireg alert_class_shadowed + // R[alert_class_shadowed_83]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_83_gated_we; + assign alert_class_shadowed_83_gated_we = alert_class_shadowed_83_we & alert_regwen_83_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_83_re), + .we (alert_class_shadowed_83_gated_we), + .wd (alert_class_shadowed_83_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[83].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_83_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_83_update_err), + .err_storage (alert_class_shadowed_83_storage_err) + ); + + + // Subregister 84 of Multireg alert_class_shadowed + // R[alert_class_shadowed_84]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_84_gated_we; + assign alert_class_shadowed_84_gated_we = alert_class_shadowed_84_we & alert_regwen_84_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_84_re), + .we (alert_class_shadowed_84_gated_we), + .wd (alert_class_shadowed_84_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[84].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_84_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_84_update_err), + .err_storage (alert_class_shadowed_84_storage_err) + ); + + + // Subregister 85 of Multireg alert_class_shadowed + // R[alert_class_shadowed_85]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_85_gated_we; + assign alert_class_shadowed_85_gated_we = alert_class_shadowed_85_we & alert_regwen_85_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_85_re), + .we (alert_class_shadowed_85_gated_we), + .wd (alert_class_shadowed_85_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[85].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_85_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_85_update_err), + .err_storage (alert_class_shadowed_85_storage_err) + ); + + + // Subregister 86 of Multireg alert_class_shadowed + // R[alert_class_shadowed_86]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_86_gated_we; + assign alert_class_shadowed_86_gated_we = alert_class_shadowed_86_we & alert_regwen_86_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_86_re), + .we (alert_class_shadowed_86_gated_we), + .wd (alert_class_shadowed_86_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[86].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_86_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_86_update_err), + .err_storage (alert_class_shadowed_86_storage_err) + ); + + + // Subregister 87 of Multireg alert_class_shadowed + // R[alert_class_shadowed_87]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_87_gated_we; + assign alert_class_shadowed_87_gated_we = alert_class_shadowed_87_we & alert_regwen_87_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_87_re), + .we (alert_class_shadowed_87_gated_we), + .wd (alert_class_shadowed_87_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[87].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_87_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_87_update_err), + .err_storage (alert_class_shadowed_87_storage_err) + ); + + + // Subregister 88 of Multireg alert_class_shadowed + // R[alert_class_shadowed_88]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_88_gated_we; + assign alert_class_shadowed_88_gated_we = alert_class_shadowed_88_we & alert_regwen_88_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_88_re), + .we (alert_class_shadowed_88_gated_we), + .wd (alert_class_shadowed_88_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[88].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_88_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_88_update_err), + .err_storage (alert_class_shadowed_88_storage_err) + ); + + + // Subregister 89 of Multireg alert_class_shadowed + // R[alert_class_shadowed_89]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_89_gated_we; + assign alert_class_shadowed_89_gated_we = alert_class_shadowed_89_we & alert_regwen_89_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_89_re), + .we (alert_class_shadowed_89_gated_we), + .wd (alert_class_shadowed_89_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[89].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_89_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_89_update_err), + .err_storage (alert_class_shadowed_89_storage_err) + ); + + + // Subregister 90 of Multireg alert_class_shadowed + // R[alert_class_shadowed_90]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_90_gated_we; + assign alert_class_shadowed_90_gated_we = alert_class_shadowed_90_we & alert_regwen_90_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_90_re), + .we (alert_class_shadowed_90_gated_we), + .wd (alert_class_shadowed_90_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[90].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_90_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_90_update_err), + .err_storage (alert_class_shadowed_90_storage_err) + ); + + + // Subregister 91 of Multireg alert_class_shadowed + // R[alert_class_shadowed_91]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_91_gated_we; + assign alert_class_shadowed_91_gated_we = alert_class_shadowed_91_we & alert_regwen_91_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_91_re), + .we (alert_class_shadowed_91_gated_we), + .wd (alert_class_shadowed_91_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[91].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_91_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_91_update_err), + .err_storage (alert_class_shadowed_91_storage_err) + ); + + + // Subregister 92 of Multireg alert_class_shadowed + // R[alert_class_shadowed_92]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_92_gated_we; + assign alert_class_shadowed_92_gated_we = alert_class_shadowed_92_we & alert_regwen_92_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_92_re), + .we (alert_class_shadowed_92_gated_we), + .wd (alert_class_shadowed_92_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[92].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_92_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_92_update_err), + .err_storage (alert_class_shadowed_92_storage_err) + ); + + + // Subregister 93 of Multireg alert_class_shadowed + // R[alert_class_shadowed_93]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_93_gated_we; + assign alert_class_shadowed_93_gated_we = alert_class_shadowed_93_we & alert_regwen_93_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_93_re), + .we (alert_class_shadowed_93_gated_we), + .wd (alert_class_shadowed_93_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[93].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_93_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_93_update_err), + .err_storage (alert_class_shadowed_93_storage_err) + ); + + + // Subregister 94 of Multireg alert_class_shadowed + // R[alert_class_shadowed_94]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_94_gated_we; + assign alert_class_shadowed_94_gated_we = alert_class_shadowed_94_we & alert_regwen_94_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_94_re), + .we (alert_class_shadowed_94_gated_we), + .wd (alert_class_shadowed_94_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[94].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_94_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_94_update_err), + .err_storage (alert_class_shadowed_94_storage_err) + ); + + + // Subregister 95 of Multireg alert_class_shadowed + // R[alert_class_shadowed_95]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_95_gated_we; + assign alert_class_shadowed_95_gated_we = alert_class_shadowed_95_we & alert_regwen_95_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_95_re), + .we (alert_class_shadowed_95_gated_we), + .wd (alert_class_shadowed_95_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[95].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_95_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_95_update_err), + .err_storage (alert_class_shadowed_95_storage_err) + ); + + + // Subregister 96 of Multireg alert_class_shadowed + // R[alert_class_shadowed_96]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_96_gated_we; + assign alert_class_shadowed_96_gated_we = alert_class_shadowed_96_we & alert_regwen_96_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_96_re), + .we (alert_class_shadowed_96_gated_we), + .wd (alert_class_shadowed_96_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[96].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_96_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_96_update_err), + .err_storage (alert_class_shadowed_96_storage_err) + ); + + + // Subregister 97 of Multireg alert_class_shadowed + // R[alert_class_shadowed_97]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_97_gated_we; + assign alert_class_shadowed_97_gated_we = alert_class_shadowed_97_we & alert_regwen_97_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_97_re), + .we (alert_class_shadowed_97_gated_we), + .wd (alert_class_shadowed_97_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[97].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_97_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_97_update_err), + .err_storage (alert_class_shadowed_97_storage_err) + ); + + + // Subregister 98 of Multireg alert_class_shadowed + // R[alert_class_shadowed_98]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_98_gated_we; + assign alert_class_shadowed_98_gated_we = alert_class_shadowed_98_we & alert_regwen_98_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_98_re), + .we (alert_class_shadowed_98_gated_we), + .wd (alert_class_shadowed_98_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[98].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_98_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_98_update_err), + .err_storage (alert_class_shadowed_98_storage_err) + ); + + + // Subregister 0 of Multireg alert_cause + // R[alert_cause_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_0_we), + .wd (alert_cause_0_wd), + + // from internal hardware + .de (hw2reg.alert_cause[0].de), + .d (hw2reg.alert_cause[0].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[0].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_0_qs) + ); + + + // Subregister 1 of Multireg alert_cause + // R[alert_cause_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_1_we), + .wd (alert_cause_1_wd), + + // from internal hardware + .de (hw2reg.alert_cause[1].de), + .d (hw2reg.alert_cause[1].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[1].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_1_qs) + ); + + + // Subregister 2 of Multireg alert_cause + // R[alert_cause_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_2_we), + .wd (alert_cause_2_wd), + + // from internal hardware + .de (hw2reg.alert_cause[2].de), + .d (hw2reg.alert_cause[2].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[2].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_2_qs) + ); + + + // Subregister 3 of Multireg alert_cause + // R[alert_cause_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_3_we), + .wd (alert_cause_3_wd), + + // from internal hardware + .de (hw2reg.alert_cause[3].de), + .d (hw2reg.alert_cause[3].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[3].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_3_qs) + ); + + + // Subregister 4 of Multireg alert_cause + // R[alert_cause_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_4_we), + .wd (alert_cause_4_wd), + + // from internal hardware + .de (hw2reg.alert_cause[4].de), + .d (hw2reg.alert_cause[4].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[4].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_4_qs) + ); + + + // Subregister 5 of Multireg alert_cause + // R[alert_cause_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_5_we), + .wd (alert_cause_5_wd), + + // from internal hardware + .de (hw2reg.alert_cause[5].de), + .d (hw2reg.alert_cause[5].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[5].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_5_qs) + ); + + + // Subregister 6 of Multireg alert_cause + // R[alert_cause_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_6_we), + .wd (alert_cause_6_wd), + + // from internal hardware + .de (hw2reg.alert_cause[6].de), + .d (hw2reg.alert_cause[6].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[6].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_6_qs) + ); + + + // Subregister 7 of Multireg alert_cause + // R[alert_cause_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_7_we), + .wd (alert_cause_7_wd), + + // from internal hardware + .de (hw2reg.alert_cause[7].de), + .d (hw2reg.alert_cause[7].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[7].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_7_qs) + ); + + + // Subregister 8 of Multireg alert_cause + // R[alert_cause_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_8_we), + .wd (alert_cause_8_wd), + + // from internal hardware + .de (hw2reg.alert_cause[8].de), + .d (hw2reg.alert_cause[8].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[8].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_8_qs) + ); + + + // Subregister 9 of Multireg alert_cause + // R[alert_cause_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_9_we), + .wd (alert_cause_9_wd), + + // from internal hardware + .de (hw2reg.alert_cause[9].de), + .d (hw2reg.alert_cause[9].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[9].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_9_qs) + ); + + + // Subregister 10 of Multireg alert_cause + // R[alert_cause_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_10_we), + .wd (alert_cause_10_wd), + + // from internal hardware + .de (hw2reg.alert_cause[10].de), + .d (hw2reg.alert_cause[10].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[10].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_10_qs) + ); + + + // Subregister 11 of Multireg alert_cause + // R[alert_cause_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_11_we), + .wd (alert_cause_11_wd), + + // from internal hardware + .de (hw2reg.alert_cause[11].de), + .d (hw2reg.alert_cause[11].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[11].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_11_qs) + ); + + + // Subregister 12 of Multireg alert_cause + // R[alert_cause_12]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_12_we), + .wd (alert_cause_12_wd), + + // from internal hardware + .de (hw2reg.alert_cause[12].de), + .d (hw2reg.alert_cause[12].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[12].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_12_qs) + ); + + + // Subregister 13 of Multireg alert_cause + // R[alert_cause_13]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_13_we), + .wd (alert_cause_13_wd), + + // from internal hardware + .de (hw2reg.alert_cause[13].de), + .d (hw2reg.alert_cause[13].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[13].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_13_qs) + ); + + + // Subregister 14 of Multireg alert_cause + // R[alert_cause_14]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_14_we), + .wd (alert_cause_14_wd), + + // from internal hardware + .de (hw2reg.alert_cause[14].de), + .d (hw2reg.alert_cause[14].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[14].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_14_qs) + ); + + + // Subregister 15 of Multireg alert_cause + // R[alert_cause_15]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_15_we), + .wd (alert_cause_15_wd), + + // from internal hardware + .de (hw2reg.alert_cause[15].de), + .d (hw2reg.alert_cause[15].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[15].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_15_qs) + ); + + + // Subregister 16 of Multireg alert_cause + // R[alert_cause_16]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_16_we), + .wd (alert_cause_16_wd), + + // from internal hardware + .de (hw2reg.alert_cause[16].de), + .d (hw2reg.alert_cause[16].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[16].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_16_qs) + ); + + + // Subregister 17 of Multireg alert_cause + // R[alert_cause_17]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_17_we), + .wd (alert_cause_17_wd), + + // from internal hardware + .de (hw2reg.alert_cause[17].de), + .d (hw2reg.alert_cause[17].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[17].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_17_qs) + ); + + + // Subregister 18 of Multireg alert_cause + // R[alert_cause_18]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_18_we), + .wd (alert_cause_18_wd), + + // from internal hardware + .de (hw2reg.alert_cause[18].de), + .d (hw2reg.alert_cause[18].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[18].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_18_qs) + ); + + + // Subregister 19 of Multireg alert_cause + // R[alert_cause_19]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_19_we), + .wd (alert_cause_19_wd), + + // from internal hardware + .de (hw2reg.alert_cause[19].de), + .d (hw2reg.alert_cause[19].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[19].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_19_qs) + ); + + + // Subregister 20 of Multireg alert_cause + // R[alert_cause_20]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_20_we), + .wd (alert_cause_20_wd), + + // from internal hardware + .de (hw2reg.alert_cause[20].de), + .d (hw2reg.alert_cause[20].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[20].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_20_qs) + ); + + + // Subregister 21 of Multireg alert_cause + // R[alert_cause_21]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_21_we), + .wd (alert_cause_21_wd), + + // from internal hardware + .de (hw2reg.alert_cause[21].de), + .d (hw2reg.alert_cause[21].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[21].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_21_qs) + ); + + + // Subregister 22 of Multireg alert_cause + // R[alert_cause_22]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_22_we), + .wd (alert_cause_22_wd), + + // from internal hardware + .de (hw2reg.alert_cause[22].de), + .d (hw2reg.alert_cause[22].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[22].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_22_qs) + ); + + + // Subregister 23 of Multireg alert_cause + // R[alert_cause_23]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_23_we), + .wd (alert_cause_23_wd), + + // from internal hardware + .de (hw2reg.alert_cause[23].de), + .d (hw2reg.alert_cause[23].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[23].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_23_qs) + ); + + + // Subregister 24 of Multireg alert_cause + // R[alert_cause_24]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_24_we), + .wd (alert_cause_24_wd), + + // from internal hardware + .de (hw2reg.alert_cause[24].de), + .d (hw2reg.alert_cause[24].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[24].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_24_qs) + ); + + + // Subregister 25 of Multireg alert_cause + // R[alert_cause_25]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_25_we), + .wd (alert_cause_25_wd), + + // from internal hardware + .de (hw2reg.alert_cause[25].de), + .d (hw2reg.alert_cause[25].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[25].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_25_qs) + ); + + + // Subregister 26 of Multireg alert_cause + // R[alert_cause_26]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_26_we), + .wd (alert_cause_26_wd), + + // from internal hardware + .de (hw2reg.alert_cause[26].de), + .d (hw2reg.alert_cause[26].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[26].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_26_qs) + ); + + + // Subregister 27 of Multireg alert_cause + // R[alert_cause_27]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_27_we), + .wd (alert_cause_27_wd), + + // from internal hardware + .de (hw2reg.alert_cause[27].de), + .d (hw2reg.alert_cause[27].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[27].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_27_qs) + ); + + + // Subregister 28 of Multireg alert_cause + // R[alert_cause_28]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_28_we), + .wd (alert_cause_28_wd), + + // from internal hardware + .de (hw2reg.alert_cause[28].de), + .d (hw2reg.alert_cause[28].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[28].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_28_qs) + ); + + + // Subregister 29 of Multireg alert_cause + // R[alert_cause_29]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_29_we), + .wd (alert_cause_29_wd), + + // from internal hardware + .de (hw2reg.alert_cause[29].de), + .d (hw2reg.alert_cause[29].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[29].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_29_qs) + ); + + + // Subregister 30 of Multireg alert_cause + // R[alert_cause_30]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_30_we), + .wd (alert_cause_30_wd), + + // from internal hardware + .de (hw2reg.alert_cause[30].de), + .d (hw2reg.alert_cause[30].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[30].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_30_qs) + ); + + + // Subregister 31 of Multireg alert_cause + // R[alert_cause_31]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_31_we), + .wd (alert_cause_31_wd), + + // from internal hardware + .de (hw2reg.alert_cause[31].de), + .d (hw2reg.alert_cause[31].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[31].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_31_qs) + ); + + + // Subregister 32 of Multireg alert_cause + // R[alert_cause_32]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_32_we), + .wd (alert_cause_32_wd), + + // from internal hardware + .de (hw2reg.alert_cause[32].de), + .d (hw2reg.alert_cause[32].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[32].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_32_qs) + ); + + + // Subregister 33 of Multireg alert_cause + // R[alert_cause_33]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_33_we), + .wd (alert_cause_33_wd), + + // from internal hardware + .de (hw2reg.alert_cause[33].de), + .d (hw2reg.alert_cause[33].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[33].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_33_qs) + ); + + + // Subregister 34 of Multireg alert_cause + // R[alert_cause_34]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_34_we), + .wd (alert_cause_34_wd), + + // from internal hardware + .de (hw2reg.alert_cause[34].de), + .d (hw2reg.alert_cause[34].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[34].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_34_qs) + ); + + + // Subregister 35 of Multireg alert_cause + // R[alert_cause_35]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_35_we), + .wd (alert_cause_35_wd), + + // from internal hardware + .de (hw2reg.alert_cause[35].de), + .d (hw2reg.alert_cause[35].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[35].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_35_qs) + ); + + + // Subregister 36 of Multireg alert_cause + // R[alert_cause_36]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_36_we), + .wd (alert_cause_36_wd), + + // from internal hardware + .de (hw2reg.alert_cause[36].de), + .d (hw2reg.alert_cause[36].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[36].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_36_qs) + ); + + + // Subregister 37 of Multireg alert_cause + // R[alert_cause_37]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_37_we), + .wd (alert_cause_37_wd), + + // from internal hardware + .de (hw2reg.alert_cause[37].de), + .d (hw2reg.alert_cause[37].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[37].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_37_qs) + ); + + + // Subregister 38 of Multireg alert_cause + // R[alert_cause_38]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_38_we), + .wd (alert_cause_38_wd), + + // from internal hardware + .de (hw2reg.alert_cause[38].de), + .d (hw2reg.alert_cause[38].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[38].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_38_qs) + ); + + + // Subregister 39 of Multireg alert_cause + // R[alert_cause_39]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_39_we), + .wd (alert_cause_39_wd), + + // from internal hardware + .de (hw2reg.alert_cause[39].de), + .d (hw2reg.alert_cause[39].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[39].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_39_qs) + ); + + + // Subregister 40 of Multireg alert_cause + // R[alert_cause_40]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_40_we), + .wd (alert_cause_40_wd), + + // from internal hardware + .de (hw2reg.alert_cause[40].de), + .d (hw2reg.alert_cause[40].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[40].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_40_qs) + ); + + + // Subregister 41 of Multireg alert_cause + // R[alert_cause_41]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_41_we), + .wd (alert_cause_41_wd), + + // from internal hardware + .de (hw2reg.alert_cause[41].de), + .d (hw2reg.alert_cause[41].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[41].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_41_qs) + ); + + + // Subregister 42 of Multireg alert_cause + // R[alert_cause_42]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_42_we), + .wd (alert_cause_42_wd), + + // from internal hardware + .de (hw2reg.alert_cause[42].de), + .d (hw2reg.alert_cause[42].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[42].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_42_qs) + ); + + + // Subregister 43 of Multireg alert_cause + // R[alert_cause_43]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_43_we), + .wd (alert_cause_43_wd), + + // from internal hardware + .de (hw2reg.alert_cause[43].de), + .d (hw2reg.alert_cause[43].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[43].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_43_qs) + ); + + + // Subregister 44 of Multireg alert_cause + // R[alert_cause_44]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_44_we), + .wd (alert_cause_44_wd), + + // from internal hardware + .de (hw2reg.alert_cause[44].de), + .d (hw2reg.alert_cause[44].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[44].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_44_qs) + ); + + + // Subregister 45 of Multireg alert_cause + // R[alert_cause_45]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_45_we), + .wd (alert_cause_45_wd), + + // from internal hardware + .de (hw2reg.alert_cause[45].de), + .d (hw2reg.alert_cause[45].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[45].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_45_qs) + ); + + + // Subregister 46 of Multireg alert_cause + // R[alert_cause_46]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_46_we), + .wd (alert_cause_46_wd), + + // from internal hardware + .de (hw2reg.alert_cause[46].de), + .d (hw2reg.alert_cause[46].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[46].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_46_qs) + ); + + + // Subregister 47 of Multireg alert_cause + // R[alert_cause_47]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_47_we), + .wd (alert_cause_47_wd), + + // from internal hardware + .de (hw2reg.alert_cause[47].de), + .d (hw2reg.alert_cause[47].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[47].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_47_qs) + ); + + + // Subregister 48 of Multireg alert_cause + // R[alert_cause_48]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_48_we), + .wd (alert_cause_48_wd), + + // from internal hardware + .de (hw2reg.alert_cause[48].de), + .d (hw2reg.alert_cause[48].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[48].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_48_qs) + ); + + + // Subregister 49 of Multireg alert_cause + // R[alert_cause_49]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_49_we), + .wd (alert_cause_49_wd), + + // from internal hardware + .de (hw2reg.alert_cause[49].de), + .d (hw2reg.alert_cause[49].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[49].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_49_qs) + ); + + + // Subregister 50 of Multireg alert_cause + // R[alert_cause_50]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_50_we), + .wd (alert_cause_50_wd), + + // from internal hardware + .de (hw2reg.alert_cause[50].de), + .d (hw2reg.alert_cause[50].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[50].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_50_qs) + ); + + + // Subregister 51 of Multireg alert_cause + // R[alert_cause_51]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_51_we), + .wd (alert_cause_51_wd), + + // from internal hardware + .de (hw2reg.alert_cause[51].de), + .d (hw2reg.alert_cause[51].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[51].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_51_qs) + ); + + + // Subregister 52 of Multireg alert_cause + // R[alert_cause_52]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_52_we), + .wd (alert_cause_52_wd), + + // from internal hardware + .de (hw2reg.alert_cause[52].de), + .d (hw2reg.alert_cause[52].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[52].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_52_qs) + ); + + + // Subregister 53 of Multireg alert_cause + // R[alert_cause_53]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_53_we), + .wd (alert_cause_53_wd), + + // from internal hardware + .de (hw2reg.alert_cause[53].de), + .d (hw2reg.alert_cause[53].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[53].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_53_qs) + ); + + + // Subregister 54 of Multireg alert_cause + // R[alert_cause_54]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_54_we), + .wd (alert_cause_54_wd), + + // from internal hardware + .de (hw2reg.alert_cause[54].de), + .d (hw2reg.alert_cause[54].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[54].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_54_qs) + ); + + + // Subregister 55 of Multireg alert_cause + // R[alert_cause_55]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_55_we), + .wd (alert_cause_55_wd), + + // from internal hardware + .de (hw2reg.alert_cause[55].de), + .d (hw2reg.alert_cause[55].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[55].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_55_qs) + ); + + + // Subregister 56 of Multireg alert_cause + // R[alert_cause_56]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_56_we), + .wd (alert_cause_56_wd), + + // from internal hardware + .de (hw2reg.alert_cause[56].de), + .d (hw2reg.alert_cause[56].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[56].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_56_qs) + ); + + + // Subregister 57 of Multireg alert_cause + // R[alert_cause_57]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_57_we), + .wd (alert_cause_57_wd), + + // from internal hardware + .de (hw2reg.alert_cause[57].de), + .d (hw2reg.alert_cause[57].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[57].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_57_qs) + ); + + + // Subregister 58 of Multireg alert_cause + // R[alert_cause_58]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_58_we), + .wd (alert_cause_58_wd), + + // from internal hardware + .de (hw2reg.alert_cause[58].de), + .d (hw2reg.alert_cause[58].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[58].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_58_qs) + ); + + + // Subregister 59 of Multireg alert_cause + // R[alert_cause_59]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_59_we), + .wd (alert_cause_59_wd), + + // from internal hardware + .de (hw2reg.alert_cause[59].de), + .d (hw2reg.alert_cause[59].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[59].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_59_qs) + ); + + + // Subregister 60 of Multireg alert_cause + // R[alert_cause_60]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_60_we), + .wd (alert_cause_60_wd), + + // from internal hardware + .de (hw2reg.alert_cause[60].de), + .d (hw2reg.alert_cause[60].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[60].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_60_qs) + ); + + + // Subregister 61 of Multireg alert_cause + // R[alert_cause_61]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_61_we), + .wd (alert_cause_61_wd), + + // from internal hardware + .de (hw2reg.alert_cause[61].de), + .d (hw2reg.alert_cause[61].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[61].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_61_qs) + ); + + + // Subregister 62 of Multireg alert_cause + // R[alert_cause_62]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_62_we), + .wd (alert_cause_62_wd), + + // from internal hardware + .de (hw2reg.alert_cause[62].de), + .d (hw2reg.alert_cause[62].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[62].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_62_qs) + ); + + + // Subregister 63 of Multireg alert_cause + // R[alert_cause_63]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_63_we), + .wd (alert_cause_63_wd), + + // from internal hardware + .de (hw2reg.alert_cause[63].de), + .d (hw2reg.alert_cause[63].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[63].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_63_qs) + ); + + + // Subregister 64 of Multireg alert_cause + // R[alert_cause_64]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_64_we), + .wd (alert_cause_64_wd), + + // from internal hardware + .de (hw2reg.alert_cause[64].de), + .d (hw2reg.alert_cause[64].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[64].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_64_qs) + ); + + + // Subregister 65 of Multireg alert_cause + // R[alert_cause_65]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_65_we), + .wd (alert_cause_65_wd), + + // from internal hardware + .de (hw2reg.alert_cause[65].de), + .d (hw2reg.alert_cause[65].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[65].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_65_qs) + ); + + + // Subregister 66 of Multireg alert_cause + // R[alert_cause_66]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_66_we), + .wd (alert_cause_66_wd), + + // from internal hardware + .de (hw2reg.alert_cause[66].de), + .d (hw2reg.alert_cause[66].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[66].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_66_qs) + ); + + + // Subregister 67 of Multireg alert_cause + // R[alert_cause_67]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_67_we), + .wd (alert_cause_67_wd), + + // from internal hardware + .de (hw2reg.alert_cause[67].de), + .d (hw2reg.alert_cause[67].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[67].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_67_qs) + ); + + + // Subregister 68 of Multireg alert_cause + // R[alert_cause_68]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_68_we), + .wd (alert_cause_68_wd), + + // from internal hardware + .de (hw2reg.alert_cause[68].de), + .d (hw2reg.alert_cause[68].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[68].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_68_qs) + ); + + + // Subregister 69 of Multireg alert_cause + // R[alert_cause_69]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_69_we), + .wd (alert_cause_69_wd), + + // from internal hardware + .de (hw2reg.alert_cause[69].de), + .d (hw2reg.alert_cause[69].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[69].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_69_qs) + ); + + + // Subregister 70 of Multireg alert_cause + // R[alert_cause_70]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_70_we), + .wd (alert_cause_70_wd), + + // from internal hardware + .de (hw2reg.alert_cause[70].de), + .d (hw2reg.alert_cause[70].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[70].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_70_qs) + ); + + + // Subregister 71 of Multireg alert_cause + // R[alert_cause_71]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_71_we), + .wd (alert_cause_71_wd), + + // from internal hardware + .de (hw2reg.alert_cause[71].de), + .d (hw2reg.alert_cause[71].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[71].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_71_qs) + ); + + + // Subregister 72 of Multireg alert_cause + // R[alert_cause_72]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_72_we), + .wd (alert_cause_72_wd), + + // from internal hardware + .de (hw2reg.alert_cause[72].de), + .d (hw2reg.alert_cause[72].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[72].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_72_qs) + ); + + + // Subregister 73 of Multireg alert_cause + // R[alert_cause_73]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_73_we), + .wd (alert_cause_73_wd), + + // from internal hardware + .de (hw2reg.alert_cause[73].de), + .d (hw2reg.alert_cause[73].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[73].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_73_qs) + ); + + + // Subregister 74 of Multireg alert_cause + // R[alert_cause_74]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_74_we), + .wd (alert_cause_74_wd), + + // from internal hardware + .de (hw2reg.alert_cause[74].de), + .d (hw2reg.alert_cause[74].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[74].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_74_qs) + ); + + + // Subregister 75 of Multireg alert_cause + // R[alert_cause_75]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_75_we), + .wd (alert_cause_75_wd), + + // from internal hardware + .de (hw2reg.alert_cause[75].de), + .d (hw2reg.alert_cause[75].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[75].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_75_qs) + ); + + + // Subregister 76 of Multireg alert_cause + // R[alert_cause_76]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_76_we), + .wd (alert_cause_76_wd), + + // from internal hardware + .de (hw2reg.alert_cause[76].de), + .d (hw2reg.alert_cause[76].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[76].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_76_qs) + ); + + + // Subregister 77 of Multireg alert_cause + // R[alert_cause_77]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_77_we), + .wd (alert_cause_77_wd), + + // from internal hardware + .de (hw2reg.alert_cause[77].de), + .d (hw2reg.alert_cause[77].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[77].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_77_qs) + ); + + + // Subregister 78 of Multireg alert_cause + // R[alert_cause_78]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_78_we), + .wd (alert_cause_78_wd), + + // from internal hardware + .de (hw2reg.alert_cause[78].de), + .d (hw2reg.alert_cause[78].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[78].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_78_qs) + ); + + + // Subregister 79 of Multireg alert_cause + // R[alert_cause_79]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_79_we), + .wd (alert_cause_79_wd), + + // from internal hardware + .de (hw2reg.alert_cause[79].de), + .d (hw2reg.alert_cause[79].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[79].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_79_qs) + ); + + + // Subregister 80 of Multireg alert_cause + // R[alert_cause_80]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_80_we), + .wd (alert_cause_80_wd), + + // from internal hardware + .de (hw2reg.alert_cause[80].de), + .d (hw2reg.alert_cause[80].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[80].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_80_qs) + ); + + + // Subregister 81 of Multireg alert_cause + // R[alert_cause_81]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_81_we), + .wd (alert_cause_81_wd), + + // from internal hardware + .de (hw2reg.alert_cause[81].de), + .d (hw2reg.alert_cause[81].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[81].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_81_qs) + ); + + + // Subregister 82 of Multireg alert_cause + // R[alert_cause_82]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_82_we), + .wd (alert_cause_82_wd), + + // from internal hardware + .de (hw2reg.alert_cause[82].de), + .d (hw2reg.alert_cause[82].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[82].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_82_qs) + ); + + + // Subregister 83 of Multireg alert_cause + // R[alert_cause_83]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_83_we), + .wd (alert_cause_83_wd), + + // from internal hardware + .de (hw2reg.alert_cause[83].de), + .d (hw2reg.alert_cause[83].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[83].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_83_qs) + ); + + + // Subregister 84 of Multireg alert_cause + // R[alert_cause_84]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_84_we), + .wd (alert_cause_84_wd), + + // from internal hardware + .de (hw2reg.alert_cause[84].de), + .d (hw2reg.alert_cause[84].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[84].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_84_qs) + ); + + + // Subregister 85 of Multireg alert_cause + // R[alert_cause_85]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_85_we), + .wd (alert_cause_85_wd), + + // from internal hardware + .de (hw2reg.alert_cause[85].de), + .d (hw2reg.alert_cause[85].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[85].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_85_qs) + ); + + + // Subregister 86 of Multireg alert_cause + // R[alert_cause_86]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_86_we), + .wd (alert_cause_86_wd), + + // from internal hardware + .de (hw2reg.alert_cause[86].de), + .d (hw2reg.alert_cause[86].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[86].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_86_qs) + ); + + + // Subregister 87 of Multireg alert_cause + // R[alert_cause_87]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_87_we), + .wd (alert_cause_87_wd), + + // from internal hardware + .de (hw2reg.alert_cause[87].de), + .d (hw2reg.alert_cause[87].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[87].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_87_qs) + ); + + + // Subregister 88 of Multireg alert_cause + // R[alert_cause_88]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_88_we), + .wd (alert_cause_88_wd), + + // from internal hardware + .de (hw2reg.alert_cause[88].de), + .d (hw2reg.alert_cause[88].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[88].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_88_qs) + ); + + + // Subregister 89 of Multireg alert_cause + // R[alert_cause_89]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_89_we), + .wd (alert_cause_89_wd), + + // from internal hardware + .de (hw2reg.alert_cause[89].de), + .d (hw2reg.alert_cause[89].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[89].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_89_qs) + ); + + + // Subregister 90 of Multireg alert_cause + // R[alert_cause_90]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_90_we), + .wd (alert_cause_90_wd), + + // from internal hardware + .de (hw2reg.alert_cause[90].de), + .d (hw2reg.alert_cause[90].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[90].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_90_qs) + ); + + + // Subregister 91 of Multireg alert_cause + // R[alert_cause_91]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_91_we), + .wd (alert_cause_91_wd), + + // from internal hardware + .de (hw2reg.alert_cause[91].de), + .d (hw2reg.alert_cause[91].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[91].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_91_qs) + ); + + + // Subregister 92 of Multireg alert_cause + // R[alert_cause_92]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_92_we), + .wd (alert_cause_92_wd), + + // from internal hardware + .de (hw2reg.alert_cause[92].de), + .d (hw2reg.alert_cause[92].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[92].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_92_qs) + ); + + + // Subregister 93 of Multireg alert_cause + // R[alert_cause_93]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_93_we), + .wd (alert_cause_93_wd), + + // from internal hardware + .de (hw2reg.alert_cause[93].de), + .d (hw2reg.alert_cause[93].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[93].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_93_qs) + ); + + + // Subregister 94 of Multireg alert_cause + // R[alert_cause_94]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_94_we), + .wd (alert_cause_94_wd), + + // from internal hardware + .de (hw2reg.alert_cause[94].de), + .d (hw2reg.alert_cause[94].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[94].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_94_qs) + ); + + + // Subregister 95 of Multireg alert_cause + // R[alert_cause_95]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_95_we), + .wd (alert_cause_95_wd), + + // from internal hardware + .de (hw2reg.alert_cause[95].de), + .d (hw2reg.alert_cause[95].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[95].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_95_qs) + ); + + + // Subregister 96 of Multireg alert_cause + // R[alert_cause_96]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_96_we), + .wd (alert_cause_96_wd), + + // from internal hardware + .de (hw2reg.alert_cause[96].de), + .d (hw2reg.alert_cause[96].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[96].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_96_qs) + ); + + + // Subregister 97 of Multireg alert_cause + // R[alert_cause_97]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_97_we), + .wd (alert_cause_97_wd), + + // from internal hardware + .de (hw2reg.alert_cause[97].de), + .d (hw2reg.alert_cause[97].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[97].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_97_qs) + ); + + + // Subregister 98 of Multireg alert_cause + // R[alert_cause_98]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_98_we), + .wd (alert_cause_98_wd), + + // from internal hardware + .de (hw2reg.alert_cause[98].de), + .d (hw2reg.alert_cause[98].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[98].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_98_qs) + ); + + + // Subregister 0 of Multireg loc_alert_regwen + // R[loc_alert_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_0_we), + .wd (loc_alert_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_0_qs) + ); + + + // Subregister 1 of Multireg loc_alert_regwen + // R[loc_alert_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_1_we), + .wd (loc_alert_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_1_qs) + ); + + + // Subregister 2 of Multireg loc_alert_regwen + // R[loc_alert_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_2_we), + .wd (loc_alert_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_2_qs) + ); + + + // Subregister 3 of Multireg loc_alert_regwen + // R[loc_alert_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_3_we), + .wd (loc_alert_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_3_qs) + ); + + + // Subregister 4 of Multireg loc_alert_regwen + // R[loc_alert_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_4_we), + .wd (loc_alert_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_4_qs) + ); + + + // Subregister 5 of Multireg loc_alert_regwen + // R[loc_alert_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_5_we), + .wd (loc_alert_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_5_qs) + ); + + + // Subregister 6 of Multireg loc_alert_regwen + // R[loc_alert_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_6_we), + .wd (loc_alert_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_6_qs) + ); + + + // Subregister 0 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_0]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_0_gated_we; + assign loc_alert_en_shadowed_0_gated_we = loc_alert_en_shadowed_0_we & loc_alert_regwen_0_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_0_re), + .we (loc_alert_en_shadowed_0_gated_we), + .wd (loc_alert_en_shadowed_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[0].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_0_update_err), + .err_storage (loc_alert_en_shadowed_0_storage_err) + ); + + + // Subregister 1 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_1]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_1_gated_we; + assign loc_alert_en_shadowed_1_gated_we = loc_alert_en_shadowed_1_we & loc_alert_regwen_1_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_1_re), + .we (loc_alert_en_shadowed_1_gated_we), + .wd (loc_alert_en_shadowed_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[1].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_1_update_err), + .err_storage (loc_alert_en_shadowed_1_storage_err) + ); + + + // Subregister 2 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_2]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_2_gated_we; + assign loc_alert_en_shadowed_2_gated_we = loc_alert_en_shadowed_2_we & loc_alert_regwen_2_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_2_re), + .we (loc_alert_en_shadowed_2_gated_we), + .wd (loc_alert_en_shadowed_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[2].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_2_update_err), + .err_storage (loc_alert_en_shadowed_2_storage_err) + ); + + + // Subregister 3 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_3]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_3_gated_we; + assign loc_alert_en_shadowed_3_gated_we = loc_alert_en_shadowed_3_we & loc_alert_regwen_3_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_3_re), + .we (loc_alert_en_shadowed_3_gated_we), + .wd (loc_alert_en_shadowed_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[3].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_3_update_err), + .err_storage (loc_alert_en_shadowed_3_storage_err) + ); + + + // Subregister 4 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_4]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_4_gated_we; + assign loc_alert_en_shadowed_4_gated_we = loc_alert_en_shadowed_4_we & loc_alert_regwen_4_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_4_re), + .we (loc_alert_en_shadowed_4_gated_we), + .wd (loc_alert_en_shadowed_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[4].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_4_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_4_update_err), + .err_storage (loc_alert_en_shadowed_4_storage_err) + ); + + + // Subregister 5 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_5]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_5_gated_we; + assign loc_alert_en_shadowed_5_gated_we = loc_alert_en_shadowed_5_we & loc_alert_regwen_5_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_5_re), + .we (loc_alert_en_shadowed_5_gated_we), + .wd (loc_alert_en_shadowed_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[5].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_5_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_5_update_err), + .err_storage (loc_alert_en_shadowed_5_storage_err) + ); + + + // Subregister 6 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_6]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_6_gated_we; + assign loc_alert_en_shadowed_6_gated_we = loc_alert_en_shadowed_6_we & loc_alert_regwen_6_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_6_re), + .we (loc_alert_en_shadowed_6_gated_we), + .wd (loc_alert_en_shadowed_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[6].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_6_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_6_update_err), + .err_storage (loc_alert_en_shadowed_6_storage_err) + ); + + + // Subregister 0 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_0]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_0_gated_we; + assign loc_alert_class_shadowed_0_gated_we = + loc_alert_class_shadowed_0_we & loc_alert_regwen_0_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_0_re), + .we (loc_alert_class_shadowed_0_gated_we), + .wd (loc_alert_class_shadowed_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[0].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_0_update_err), + .err_storage (loc_alert_class_shadowed_0_storage_err) + ); + + + // Subregister 1 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_1]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_1_gated_we; + assign loc_alert_class_shadowed_1_gated_we = + loc_alert_class_shadowed_1_we & loc_alert_regwen_1_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_1_re), + .we (loc_alert_class_shadowed_1_gated_we), + .wd (loc_alert_class_shadowed_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[1].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_1_update_err), + .err_storage (loc_alert_class_shadowed_1_storage_err) + ); + + + // Subregister 2 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_2]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_2_gated_we; + assign loc_alert_class_shadowed_2_gated_we = + loc_alert_class_shadowed_2_we & loc_alert_regwen_2_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_2_re), + .we (loc_alert_class_shadowed_2_gated_we), + .wd (loc_alert_class_shadowed_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[2].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_2_update_err), + .err_storage (loc_alert_class_shadowed_2_storage_err) + ); + + + // Subregister 3 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_3]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_3_gated_we; + assign loc_alert_class_shadowed_3_gated_we = + loc_alert_class_shadowed_3_we & loc_alert_regwen_3_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_3_re), + .we (loc_alert_class_shadowed_3_gated_we), + .wd (loc_alert_class_shadowed_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[3].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_3_update_err), + .err_storage (loc_alert_class_shadowed_3_storage_err) + ); + + + // Subregister 4 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_4]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_4_gated_we; + assign loc_alert_class_shadowed_4_gated_we = + loc_alert_class_shadowed_4_we & loc_alert_regwen_4_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_4_re), + .we (loc_alert_class_shadowed_4_gated_we), + .wd (loc_alert_class_shadowed_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[4].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_4_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_4_update_err), + .err_storage (loc_alert_class_shadowed_4_storage_err) + ); + + + // Subregister 5 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_5]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_5_gated_we; + assign loc_alert_class_shadowed_5_gated_we = + loc_alert_class_shadowed_5_we & loc_alert_regwen_5_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_5_re), + .we (loc_alert_class_shadowed_5_gated_we), + .wd (loc_alert_class_shadowed_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[5].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_5_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_5_update_err), + .err_storage (loc_alert_class_shadowed_5_storage_err) + ); + + + // Subregister 6 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_6]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_6_gated_we; + assign loc_alert_class_shadowed_6_gated_we = + loc_alert_class_shadowed_6_we & loc_alert_regwen_6_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_6_re), + .we (loc_alert_class_shadowed_6_gated_we), + .wd (loc_alert_class_shadowed_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[6].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_6_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_6_update_err), + .err_storage (loc_alert_class_shadowed_6_storage_err) + ); + + + // Subregister 0 of Multireg loc_alert_cause + // R[loc_alert_cause_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_0_we), + .wd (loc_alert_cause_0_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[0].de), + .d (hw2reg.loc_alert_cause[0].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[0].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_0_qs) + ); + + + // Subregister 1 of Multireg loc_alert_cause + // R[loc_alert_cause_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_1_we), + .wd (loc_alert_cause_1_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[1].de), + .d (hw2reg.loc_alert_cause[1].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[1].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_1_qs) + ); + + + // Subregister 2 of Multireg loc_alert_cause + // R[loc_alert_cause_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_2_we), + .wd (loc_alert_cause_2_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[2].de), + .d (hw2reg.loc_alert_cause[2].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[2].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_2_qs) + ); + + + // Subregister 3 of Multireg loc_alert_cause + // R[loc_alert_cause_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_3_we), + .wd (loc_alert_cause_3_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[3].de), + .d (hw2reg.loc_alert_cause[3].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[3].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_3_qs) + ); + + + // Subregister 4 of Multireg loc_alert_cause + // R[loc_alert_cause_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_4_we), + .wd (loc_alert_cause_4_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[4].de), + .d (hw2reg.loc_alert_cause[4].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[4].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_4_qs) + ); + + + // Subregister 5 of Multireg loc_alert_cause + // R[loc_alert_cause_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_5_we), + .wd (loc_alert_cause_5_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[5].de), + .d (hw2reg.loc_alert_cause[5].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[5].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_5_qs) + ); + + + // Subregister 6 of Multireg loc_alert_cause + // R[loc_alert_cause_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_6_we), + .wd (loc_alert_cause_6_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[6].de), + .d (hw2reg.loc_alert_cause[6].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[6].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_6_qs) + ); + + + // R[classa_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classa_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classa_regwen_we), + .wd (classa_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classa_regwen_qs) + ); + + + // R[classa_ctrl_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_ctrl_shadowed_gated_we; + assign classa_ctrl_shadowed_gated_we = classa_ctrl_shadowed_we & classa_regwen_qs; + // F[en]: 0:0 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.en.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_en_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_en_update_err), + .err_storage (classa_ctrl_shadowed_en_storage_err) + ); + + // F[lock]: 1:1 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.lock.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_lock_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_lock_update_err), + .err_storage (classa_ctrl_shadowed_lock_storage_err) + ); + + // F[en_e0]: 2:2 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_en_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_en_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.en_e0.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_en_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_en_e0_update_err), + .err_storage (classa_ctrl_shadowed_en_e0_storage_err) + ); + + // F[en_e1]: 3:3 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_en_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_en_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.en_e1.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_en_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_en_e1_update_err), + .err_storage (classa_ctrl_shadowed_en_e1_storage_err) + ); + + // F[en_e2]: 4:4 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_en_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_en_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.en_e2.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_en_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_en_e2_update_err), + .err_storage (classa_ctrl_shadowed_en_e2_storage_err) + ); + + // F[en_e3]: 5:5 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_en_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_en_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.en_e3.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_en_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_en_e3_update_err), + .err_storage (classa_ctrl_shadowed_en_e3_storage_err) + ); + + // F[map_e0]: 7:6 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_map_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_map_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.map_e0.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_map_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_map_e0_update_err), + .err_storage (classa_ctrl_shadowed_map_e0_storage_err) + ); + + // F[map_e1]: 9:8 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h1), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_map_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_map_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.map_e1.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_map_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_map_e1_update_err), + .err_storage (classa_ctrl_shadowed_map_e1_storage_err) + ); + + // F[map_e2]: 11:10 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_map_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_map_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.map_e2.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_map_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_map_e2_update_err), + .err_storage (classa_ctrl_shadowed_map_e2_storage_err) + ); + + // F[map_e3]: 13:12 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h3), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_map_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_map_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.map_e3.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_map_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_map_e3_update_err), + .err_storage (classa_ctrl_shadowed_map_e3_storage_err) + ); + + + // R[classa_clr_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classa_clr_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classa_clr_regwen_we), + .wd (classa_clr_regwen_wd), + + // from internal hardware + .de (hw2reg.classa_clr_regwen.de), + .d (hw2reg.classa_clr_regwen.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classa_clr_regwen_qs) + ); + + + // R[classa_clr_shadowed]: V(False) + logic classa_clr_shadowed_qe; + logic [0:0] classa_clr_shadowed_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_classa_clr_shadowed0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&classa_clr_shadowed_flds_we), + .q_o(classa_clr_shadowed_qe) + ); + // Create REGWEN-gated WE signal + logic classa_clr_shadowed_gated_we; + assign classa_clr_shadowed_gated_we = classa_clr_shadowed_we & classa_clr_regwen_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classa_clr_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_clr_shadowed_re), + .we (classa_clr_shadowed_gated_we), + .wd (classa_clr_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (classa_clr_shadowed_flds_we[0]), + .q (reg2hw.classa_clr_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_clr_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_clr_shadowed_update_err), + .err_storage (classa_clr_shadowed_storage_err) + ); + assign reg2hw.classa_clr_shadowed.qe = classa_clr_shadowed_qe; + + + // R[classa_accum_cnt]: V(True) + prim_subreg_ext #( + .DW (16) + ) u_classa_accum_cnt ( + .re (classa_accum_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classa_accum_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classa_accum_cnt_qs) + ); + + + // R[classa_accum_thresh_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_accum_thresh_shadowed_gated_we; + assign classa_accum_thresh_shadowed_gated_we = classa_accum_thresh_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_classa_accum_thresh_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_accum_thresh_shadowed_re), + .we (classa_accum_thresh_shadowed_gated_we), + .wd (classa_accum_thresh_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_accum_thresh_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_accum_thresh_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_accum_thresh_shadowed_update_err), + .err_storage (classa_accum_thresh_shadowed_storage_err) + ); + + + // R[classa_timeout_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_timeout_cyc_shadowed_gated_we; + assign classa_timeout_cyc_shadowed_gated_we = classa_timeout_cyc_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classa_timeout_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_timeout_cyc_shadowed_re), + .we (classa_timeout_cyc_shadowed_gated_we), + .wd (classa_timeout_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_timeout_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_timeout_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_timeout_cyc_shadowed_update_err), + .err_storage (classa_timeout_cyc_shadowed_storage_err) + ); + + + // R[classa_crashdump_trigger_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_crashdump_trigger_shadowed_gated_we; + assign classa_crashdump_trigger_shadowed_gated_we = + classa_crashdump_trigger_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classa_crashdump_trigger_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_crashdump_trigger_shadowed_re), + .we (classa_crashdump_trigger_shadowed_gated_we), + .wd (classa_crashdump_trigger_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_crashdump_trigger_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_crashdump_trigger_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_crashdump_trigger_shadowed_update_err), + .err_storage (classa_crashdump_trigger_shadowed_storage_err) + ); + + + // R[classa_phase0_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_phase0_cyc_shadowed_gated_we; + assign classa_phase0_cyc_shadowed_gated_we = classa_phase0_cyc_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classa_phase0_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_phase0_cyc_shadowed_re), + .we (classa_phase0_cyc_shadowed_gated_we), + .wd (classa_phase0_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_phase0_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_phase0_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_phase0_cyc_shadowed_update_err), + .err_storage (classa_phase0_cyc_shadowed_storage_err) + ); + + + // R[classa_phase1_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_phase1_cyc_shadowed_gated_we; + assign classa_phase1_cyc_shadowed_gated_we = classa_phase1_cyc_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classa_phase1_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_phase1_cyc_shadowed_re), + .we (classa_phase1_cyc_shadowed_gated_we), + .wd (classa_phase1_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_phase1_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_phase1_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_phase1_cyc_shadowed_update_err), + .err_storage (classa_phase1_cyc_shadowed_storage_err) + ); + + + // R[classa_phase2_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_phase2_cyc_shadowed_gated_we; + assign classa_phase2_cyc_shadowed_gated_we = classa_phase2_cyc_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classa_phase2_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_phase2_cyc_shadowed_re), + .we (classa_phase2_cyc_shadowed_gated_we), + .wd (classa_phase2_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_phase2_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_phase2_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_phase2_cyc_shadowed_update_err), + .err_storage (classa_phase2_cyc_shadowed_storage_err) + ); + + + // R[classa_phase3_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_phase3_cyc_shadowed_gated_we; + assign classa_phase3_cyc_shadowed_gated_we = classa_phase3_cyc_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classa_phase3_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_phase3_cyc_shadowed_re), + .we (classa_phase3_cyc_shadowed_gated_we), + .wd (classa_phase3_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_phase3_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_phase3_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_phase3_cyc_shadowed_update_err), + .err_storage (classa_phase3_cyc_shadowed_storage_err) + ); + + + // R[classa_esc_cnt]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_classa_esc_cnt ( + .re (classa_esc_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classa_esc_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classa_esc_cnt_qs) + ); + + + // R[classa_state]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_classa_state ( + .re (classa_state_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classa_state.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classa_state_qs) + ); + + + // R[classb_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classb_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classb_regwen_we), + .wd (classb_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classb_regwen_qs) + ); + + + // R[classb_ctrl_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_ctrl_shadowed_gated_we; + assign classb_ctrl_shadowed_gated_we = classb_ctrl_shadowed_we & classb_regwen_qs; + // F[en]: 0:0 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.en.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_en_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_en_update_err), + .err_storage (classb_ctrl_shadowed_en_storage_err) + ); + + // F[lock]: 1:1 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.lock.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_lock_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_lock_update_err), + .err_storage (classb_ctrl_shadowed_lock_storage_err) + ); + + // F[en_e0]: 2:2 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_en_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_en_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.en_e0.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_en_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_en_e0_update_err), + .err_storage (classb_ctrl_shadowed_en_e0_storage_err) + ); + + // F[en_e1]: 3:3 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_en_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_en_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.en_e1.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_en_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_en_e1_update_err), + .err_storage (classb_ctrl_shadowed_en_e1_storage_err) + ); + + // F[en_e2]: 4:4 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_en_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_en_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.en_e2.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_en_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_en_e2_update_err), + .err_storage (classb_ctrl_shadowed_en_e2_storage_err) + ); + + // F[en_e3]: 5:5 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_en_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_en_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.en_e3.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_en_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_en_e3_update_err), + .err_storage (classb_ctrl_shadowed_en_e3_storage_err) + ); + + // F[map_e0]: 7:6 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_map_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_map_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.map_e0.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_map_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_map_e0_update_err), + .err_storage (classb_ctrl_shadowed_map_e0_storage_err) + ); + + // F[map_e1]: 9:8 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h1), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_map_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_map_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.map_e1.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_map_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_map_e1_update_err), + .err_storage (classb_ctrl_shadowed_map_e1_storage_err) + ); + + // F[map_e2]: 11:10 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_map_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_map_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.map_e2.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_map_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_map_e2_update_err), + .err_storage (classb_ctrl_shadowed_map_e2_storage_err) + ); + + // F[map_e3]: 13:12 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h3), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_map_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_map_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.map_e3.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_map_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_map_e3_update_err), + .err_storage (classb_ctrl_shadowed_map_e3_storage_err) + ); + + + // R[classb_clr_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classb_clr_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classb_clr_regwen_we), + .wd (classb_clr_regwen_wd), + + // from internal hardware + .de (hw2reg.classb_clr_regwen.de), + .d (hw2reg.classb_clr_regwen.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classb_clr_regwen_qs) + ); + + + // R[classb_clr_shadowed]: V(False) + logic classb_clr_shadowed_qe; + logic [0:0] classb_clr_shadowed_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_classb_clr_shadowed0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&classb_clr_shadowed_flds_we), + .q_o(classb_clr_shadowed_qe) + ); + // Create REGWEN-gated WE signal + logic classb_clr_shadowed_gated_we; + assign classb_clr_shadowed_gated_we = classb_clr_shadowed_we & classb_clr_regwen_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classb_clr_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_clr_shadowed_re), + .we (classb_clr_shadowed_gated_we), + .wd (classb_clr_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (classb_clr_shadowed_flds_we[0]), + .q (reg2hw.classb_clr_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_clr_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_clr_shadowed_update_err), + .err_storage (classb_clr_shadowed_storage_err) + ); + assign reg2hw.classb_clr_shadowed.qe = classb_clr_shadowed_qe; + + + // R[classb_accum_cnt]: V(True) + prim_subreg_ext #( + .DW (16) + ) u_classb_accum_cnt ( + .re (classb_accum_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classb_accum_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classb_accum_cnt_qs) + ); + + + // R[classb_accum_thresh_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_accum_thresh_shadowed_gated_we; + assign classb_accum_thresh_shadowed_gated_we = classb_accum_thresh_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_classb_accum_thresh_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_accum_thresh_shadowed_re), + .we (classb_accum_thresh_shadowed_gated_we), + .wd (classb_accum_thresh_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_accum_thresh_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_accum_thresh_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_accum_thresh_shadowed_update_err), + .err_storage (classb_accum_thresh_shadowed_storage_err) + ); + + + // R[classb_timeout_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_timeout_cyc_shadowed_gated_we; + assign classb_timeout_cyc_shadowed_gated_we = classb_timeout_cyc_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classb_timeout_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_timeout_cyc_shadowed_re), + .we (classb_timeout_cyc_shadowed_gated_we), + .wd (classb_timeout_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_timeout_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_timeout_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_timeout_cyc_shadowed_update_err), + .err_storage (classb_timeout_cyc_shadowed_storage_err) + ); + + + // R[classb_crashdump_trigger_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_crashdump_trigger_shadowed_gated_we; + assign classb_crashdump_trigger_shadowed_gated_we = + classb_crashdump_trigger_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classb_crashdump_trigger_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_crashdump_trigger_shadowed_re), + .we (classb_crashdump_trigger_shadowed_gated_we), + .wd (classb_crashdump_trigger_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_crashdump_trigger_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_crashdump_trigger_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_crashdump_trigger_shadowed_update_err), + .err_storage (classb_crashdump_trigger_shadowed_storage_err) + ); + + + // R[classb_phase0_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_phase0_cyc_shadowed_gated_we; + assign classb_phase0_cyc_shadowed_gated_we = classb_phase0_cyc_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classb_phase0_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_phase0_cyc_shadowed_re), + .we (classb_phase0_cyc_shadowed_gated_we), + .wd (classb_phase0_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_phase0_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_phase0_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_phase0_cyc_shadowed_update_err), + .err_storage (classb_phase0_cyc_shadowed_storage_err) + ); + + + // R[classb_phase1_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_phase1_cyc_shadowed_gated_we; + assign classb_phase1_cyc_shadowed_gated_we = classb_phase1_cyc_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classb_phase1_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_phase1_cyc_shadowed_re), + .we (classb_phase1_cyc_shadowed_gated_we), + .wd (classb_phase1_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_phase1_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_phase1_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_phase1_cyc_shadowed_update_err), + .err_storage (classb_phase1_cyc_shadowed_storage_err) + ); + + + // R[classb_phase2_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_phase2_cyc_shadowed_gated_we; + assign classb_phase2_cyc_shadowed_gated_we = classb_phase2_cyc_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classb_phase2_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_phase2_cyc_shadowed_re), + .we (classb_phase2_cyc_shadowed_gated_we), + .wd (classb_phase2_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_phase2_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_phase2_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_phase2_cyc_shadowed_update_err), + .err_storage (classb_phase2_cyc_shadowed_storage_err) + ); + + + // R[classb_phase3_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_phase3_cyc_shadowed_gated_we; + assign classb_phase3_cyc_shadowed_gated_we = classb_phase3_cyc_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classb_phase3_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_phase3_cyc_shadowed_re), + .we (classb_phase3_cyc_shadowed_gated_we), + .wd (classb_phase3_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_phase3_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_phase3_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_phase3_cyc_shadowed_update_err), + .err_storage (classb_phase3_cyc_shadowed_storage_err) + ); + + + // R[classb_esc_cnt]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_classb_esc_cnt ( + .re (classb_esc_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classb_esc_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classb_esc_cnt_qs) + ); + + + // R[classb_state]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_classb_state ( + .re (classb_state_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classb_state.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classb_state_qs) + ); + + + // R[classc_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classc_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classc_regwen_we), + .wd (classc_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classc_regwen_qs) + ); + + + // R[classc_ctrl_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_ctrl_shadowed_gated_we; + assign classc_ctrl_shadowed_gated_we = classc_ctrl_shadowed_we & classc_regwen_qs; + // F[en]: 0:0 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.en.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_en_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_en_update_err), + .err_storage (classc_ctrl_shadowed_en_storage_err) + ); + + // F[lock]: 1:1 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.lock.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_lock_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_lock_update_err), + .err_storage (classc_ctrl_shadowed_lock_storage_err) + ); + + // F[en_e0]: 2:2 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_en_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_en_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.en_e0.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_en_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_en_e0_update_err), + .err_storage (classc_ctrl_shadowed_en_e0_storage_err) + ); + + // F[en_e1]: 3:3 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_en_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_en_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.en_e1.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_en_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_en_e1_update_err), + .err_storage (classc_ctrl_shadowed_en_e1_storage_err) + ); + + // F[en_e2]: 4:4 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_en_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_en_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.en_e2.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_en_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_en_e2_update_err), + .err_storage (classc_ctrl_shadowed_en_e2_storage_err) + ); + + // F[en_e3]: 5:5 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_en_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_en_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.en_e3.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_en_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_en_e3_update_err), + .err_storage (classc_ctrl_shadowed_en_e3_storage_err) + ); + + // F[map_e0]: 7:6 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_map_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_map_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.map_e0.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_map_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_map_e0_update_err), + .err_storage (classc_ctrl_shadowed_map_e0_storage_err) + ); + + // F[map_e1]: 9:8 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h1), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_map_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_map_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.map_e1.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_map_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_map_e1_update_err), + .err_storage (classc_ctrl_shadowed_map_e1_storage_err) + ); + + // F[map_e2]: 11:10 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_map_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_map_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.map_e2.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_map_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_map_e2_update_err), + .err_storage (classc_ctrl_shadowed_map_e2_storage_err) + ); + + // F[map_e3]: 13:12 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h3), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_map_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_map_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.map_e3.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_map_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_map_e3_update_err), + .err_storage (classc_ctrl_shadowed_map_e3_storage_err) + ); + + + // R[classc_clr_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classc_clr_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classc_clr_regwen_we), + .wd (classc_clr_regwen_wd), + + // from internal hardware + .de (hw2reg.classc_clr_regwen.de), + .d (hw2reg.classc_clr_regwen.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classc_clr_regwen_qs) + ); + + + // R[classc_clr_shadowed]: V(False) + logic classc_clr_shadowed_qe; + logic [0:0] classc_clr_shadowed_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_classc_clr_shadowed0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&classc_clr_shadowed_flds_we), + .q_o(classc_clr_shadowed_qe) + ); + // Create REGWEN-gated WE signal + logic classc_clr_shadowed_gated_we; + assign classc_clr_shadowed_gated_we = classc_clr_shadowed_we & classc_clr_regwen_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classc_clr_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_clr_shadowed_re), + .we (classc_clr_shadowed_gated_we), + .wd (classc_clr_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (classc_clr_shadowed_flds_we[0]), + .q (reg2hw.classc_clr_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_clr_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_clr_shadowed_update_err), + .err_storage (classc_clr_shadowed_storage_err) + ); + assign reg2hw.classc_clr_shadowed.qe = classc_clr_shadowed_qe; + + + // R[classc_accum_cnt]: V(True) + prim_subreg_ext #( + .DW (16) + ) u_classc_accum_cnt ( + .re (classc_accum_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classc_accum_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classc_accum_cnt_qs) + ); + + + // R[classc_accum_thresh_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_accum_thresh_shadowed_gated_we; + assign classc_accum_thresh_shadowed_gated_we = classc_accum_thresh_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_classc_accum_thresh_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_accum_thresh_shadowed_re), + .we (classc_accum_thresh_shadowed_gated_we), + .wd (classc_accum_thresh_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_accum_thresh_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_accum_thresh_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_accum_thresh_shadowed_update_err), + .err_storage (classc_accum_thresh_shadowed_storage_err) + ); + + + // R[classc_timeout_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_timeout_cyc_shadowed_gated_we; + assign classc_timeout_cyc_shadowed_gated_we = classc_timeout_cyc_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classc_timeout_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_timeout_cyc_shadowed_re), + .we (classc_timeout_cyc_shadowed_gated_we), + .wd (classc_timeout_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_timeout_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_timeout_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_timeout_cyc_shadowed_update_err), + .err_storage (classc_timeout_cyc_shadowed_storage_err) + ); + + + // R[classc_crashdump_trigger_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_crashdump_trigger_shadowed_gated_we; + assign classc_crashdump_trigger_shadowed_gated_we = + classc_crashdump_trigger_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classc_crashdump_trigger_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_crashdump_trigger_shadowed_re), + .we (classc_crashdump_trigger_shadowed_gated_we), + .wd (classc_crashdump_trigger_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_crashdump_trigger_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_crashdump_trigger_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_crashdump_trigger_shadowed_update_err), + .err_storage (classc_crashdump_trigger_shadowed_storage_err) + ); + + + // R[classc_phase0_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_phase0_cyc_shadowed_gated_we; + assign classc_phase0_cyc_shadowed_gated_we = classc_phase0_cyc_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classc_phase0_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_phase0_cyc_shadowed_re), + .we (classc_phase0_cyc_shadowed_gated_we), + .wd (classc_phase0_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_phase0_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_phase0_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_phase0_cyc_shadowed_update_err), + .err_storage (classc_phase0_cyc_shadowed_storage_err) + ); + + + // R[classc_phase1_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_phase1_cyc_shadowed_gated_we; + assign classc_phase1_cyc_shadowed_gated_we = classc_phase1_cyc_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classc_phase1_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_phase1_cyc_shadowed_re), + .we (classc_phase1_cyc_shadowed_gated_we), + .wd (classc_phase1_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_phase1_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_phase1_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_phase1_cyc_shadowed_update_err), + .err_storage (classc_phase1_cyc_shadowed_storage_err) + ); + + + // R[classc_phase2_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_phase2_cyc_shadowed_gated_we; + assign classc_phase2_cyc_shadowed_gated_we = classc_phase2_cyc_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classc_phase2_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_phase2_cyc_shadowed_re), + .we (classc_phase2_cyc_shadowed_gated_we), + .wd (classc_phase2_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_phase2_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_phase2_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_phase2_cyc_shadowed_update_err), + .err_storage (classc_phase2_cyc_shadowed_storage_err) + ); + + + // R[classc_phase3_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_phase3_cyc_shadowed_gated_we; + assign classc_phase3_cyc_shadowed_gated_we = classc_phase3_cyc_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classc_phase3_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_phase3_cyc_shadowed_re), + .we (classc_phase3_cyc_shadowed_gated_we), + .wd (classc_phase3_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_phase3_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_phase3_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_phase3_cyc_shadowed_update_err), + .err_storage (classc_phase3_cyc_shadowed_storage_err) + ); + + + // R[classc_esc_cnt]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_classc_esc_cnt ( + .re (classc_esc_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classc_esc_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classc_esc_cnt_qs) + ); + + + // R[classc_state]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_classc_state ( + .re (classc_state_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classc_state.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classc_state_qs) + ); + + + // R[classd_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classd_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classd_regwen_we), + .wd (classd_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classd_regwen_qs) + ); + + + // R[classd_ctrl_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_ctrl_shadowed_gated_we; + assign classd_ctrl_shadowed_gated_we = classd_ctrl_shadowed_we & classd_regwen_qs; + // F[en]: 0:0 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.en.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_en_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_en_update_err), + .err_storage (classd_ctrl_shadowed_en_storage_err) + ); + + // F[lock]: 1:1 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.lock.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_lock_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_lock_update_err), + .err_storage (classd_ctrl_shadowed_lock_storage_err) + ); + + // F[en_e0]: 2:2 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_en_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_en_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.en_e0.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_en_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_en_e0_update_err), + .err_storage (classd_ctrl_shadowed_en_e0_storage_err) + ); + + // F[en_e1]: 3:3 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_en_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_en_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.en_e1.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_en_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_en_e1_update_err), + .err_storage (classd_ctrl_shadowed_en_e1_storage_err) + ); + + // F[en_e2]: 4:4 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_en_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_en_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.en_e2.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_en_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_en_e2_update_err), + .err_storage (classd_ctrl_shadowed_en_e2_storage_err) + ); + + // F[en_e3]: 5:5 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_en_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_en_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.en_e3.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_en_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_en_e3_update_err), + .err_storage (classd_ctrl_shadowed_en_e3_storage_err) + ); + + // F[map_e0]: 7:6 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_map_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_map_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.map_e0.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_map_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_map_e0_update_err), + .err_storage (classd_ctrl_shadowed_map_e0_storage_err) + ); + + // F[map_e1]: 9:8 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h1), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_map_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_map_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.map_e1.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_map_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_map_e1_update_err), + .err_storage (classd_ctrl_shadowed_map_e1_storage_err) + ); + + // F[map_e2]: 11:10 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_map_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_map_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.map_e2.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_map_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_map_e2_update_err), + .err_storage (classd_ctrl_shadowed_map_e2_storage_err) + ); + + // F[map_e3]: 13:12 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h3), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_map_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_map_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.map_e3.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_map_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_map_e3_update_err), + .err_storage (classd_ctrl_shadowed_map_e3_storage_err) + ); + + + // R[classd_clr_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classd_clr_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classd_clr_regwen_we), + .wd (classd_clr_regwen_wd), + + // from internal hardware + .de (hw2reg.classd_clr_regwen.de), + .d (hw2reg.classd_clr_regwen.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classd_clr_regwen_qs) + ); + + + // R[classd_clr_shadowed]: V(False) + logic classd_clr_shadowed_qe; + logic [0:0] classd_clr_shadowed_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_classd_clr_shadowed0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&classd_clr_shadowed_flds_we), + .q_o(classd_clr_shadowed_qe) + ); + // Create REGWEN-gated WE signal + logic classd_clr_shadowed_gated_we; + assign classd_clr_shadowed_gated_we = classd_clr_shadowed_we & classd_clr_regwen_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classd_clr_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_clr_shadowed_re), + .we (classd_clr_shadowed_gated_we), + .wd (classd_clr_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (classd_clr_shadowed_flds_we[0]), + .q (reg2hw.classd_clr_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_clr_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_clr_shadowed_update_err), + .err_storage (classd_clr_shadowed_storage_err) + ); + assign reg2hw.classd_clr_shadowed.qe = classd_clr_shadowed_qe; + + + // R[classd_accum_cnt]: V(True) + prim_subreg_ext #( + .DW (16) + ) u_classd_accum_cnt ( + .re (classd_accum_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classd_accum_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classd_accum_cnt_qs) + ); + + + // R[classd_accum_thresh_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_accum_thresh_shadowed_gated_we; + assign classd_accum_thresh_shadowed_gated_we = classd_accum_thresh_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_classd_accum_thresh_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_accum_thresh_shadowed_re), + .we (classd_accum_thresh_shadowed_gated_we), + .wd (classd_accum_thresh_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_accum_thresh_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_accum_thresh_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_accum_thresh_shadowed_update_err), + .err_storage (classd_accum_thresh_shadowed_storage_err) + ); + + + // R[classd_timeout_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_timeout_cyc_shadowed_gated_we; + assign classd_timeout_cyc_shadowed_gated_we = classd_timeout_cyc_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classd_timeout_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_timeout_cyc_shadowed_re), + .we (classd_timeout_cyc_shadowed_gated_we), + .wd (classd_timeout_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_timeout_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_timeout_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_timeout_cyc_shadowed_update_err), + .err_storage (classd_timeout_cyc_shadowed_storage_err) + ); + + + // R[classd_crashdump_trigger_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_crashdump_trigger_shadowed_gated_we; + assign classd_crashdump_trigger_shadowed_gated_we = + classd_crashdump_trigger_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classd_crashdump_trigger_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_crashdump_trigger_shadowed_re), + .we (classd_crashdump_trigger_shadowed_gated_we), + .wd (classd_crashdump_trigger_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_crashdump_trigger_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_crashdump_trigger_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_crashdump_trigger_shadowed_update_err), + .err_storage (classd_crashdump_trigger_shadowed_storage_err) + ); + + + // R[classd_phase0_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_phase0_cyc_shadowed_gated_we; + assign classd_phase0_cyc_shadowed_gated_we = classd_phase0_cyc_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classd_phase0_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_phase0_cyc_shadowed_re), + .we (classd_phase0_cyc_shadowed_gated_we), + .wd (classd_phase0_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_phase0_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_phase0_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_phase0_cyc_shadowed_update_err), + .err_storage (classd_phase0_cyc_shadowed_storage_err) + ); + + + // R[classd_phase1_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_phase1_cyc_shadowed_gated_we; + assign classd_phase1_cyc_shadowed_gated_we = classd_phase1_cyc_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classd_phase1_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_phase1_cyc_shadowed_re), + .we (classd_phase1_cyc_shadowed_gated_we), + .wd (classd_phase1_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_phase1_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_phase1_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_phase1_cyc_shadowed_update_err), + .err_storage (classd_phase1_cyc_shadowed_storage_err) + ); + + + // R[classd_phase2_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_phase2_cyc_shadowed_gated_we; + assign classd_phase2_cyc_shadowed_gated_we = classd_phase2_cyc_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classd_phase2_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_phase2_cyc_shadowed_re), + .we (classd_phase2_cyc_shadowed_gated_we), + .wd (classd_phase2_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_phase2_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_phase2_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_phase2_cyc_shadowed_update_err), + .err_storage (classd_phase2_cyc_shadowed_storage_err) + ); + + + // R[classd_phase3_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_phase3_cyc_shadowed_gated_we; + assign classd_phase3_cyc_shadowed_gated_we = classd_phase3_cyc_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classd_phase3_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_phase3_cyc_shadowed_re), + .we (classd_phase3_cyc_shadowed_gated_we), + .wd (classd_phase3_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_phase3_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_phase3_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_phase3_cyc_shadowed_update_err), + .err_storage (classd_phase3_cyc_shadowed_storage_err) + ); + + + // R[classd_esc_cnt]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_classd_esc_cnt ( + .re (classd_esc_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classd_esc_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classd_esc_cnt_qs) + ); + + + // R[classd_state]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_classd_state ( + .re (classd_state_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classd_state.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classd_state_qs) + ); + + + + logic [485:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == ALERT_HANDLER_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == ALERT_HANDLER_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == ALERT_HANDLER_PING_TIMER_REGWEN_OFFSET); + addr_hit[ 4] = (reg_addr == ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[ 5] = (reg_addr == ALERT_HANDLER_PING_TIMER_EN_SHADOWED_OFFSET); + addr_hit[ 6] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_0_OFFSET); + addr_hit[ 7] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_1_OFFSET); + addr_hit[ 8] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_2_OFFSET); + addr_hit[ 9] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_3_OFFSET); + addr_hit[ 10] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_4_OFFSET); + addr_hit[ 11] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_5_OFFSET); + addr_hit[ 12] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_6_OFFSET); + addr_hit[ 13] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_7_OFFSET); + addr_hit[ 14] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_8_OFFSET); + addr_hit[ 15] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_9_OFFSET); + addr_hit[ 16] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_10_OFFSET); + addr_hit[ 17] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_11_OFFSET); + addr_hit[ 18] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_12_OFFSET); + addr_hit[ 19] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_13_OFFSET); + addr_hit[ 20] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_14_OFFSET); + addr_hit[ 21] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_15_OFFSET); + addr_hit[ 22] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_16_OFFSET); + addr_hit[ 23] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_17_OFFSET); + addr_hit[ 24] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_18_OFFSET); + addr_hit[ 25] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_19_OFFSET); + addr_hit[ 26] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_20_OFFSET); + addr_hit[ 27] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_21_OFFSET); + addr_hit[ 28] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_22_OFFSET); + addr_hit[ 29] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_23_OFFSET); + addr_hit[ 30] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_24_OFFSET); + addr_hit[ 31] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_25_OFFSET); + addr_hit[ 32] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_26_OFFSET); + addr_hit[ 33] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_27_OFFSET); + addr_hit[ 34] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_28_OFFSET); + addr_hit[ 35] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_29_OFFSET); + addr_hit[ 36] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_30_OFFSET); + addr_hit[ 37] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_31_OFFSET); + addr_hit[ 38] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_32_OFFSET); + addr_hit[ 39] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_33_OFFSET); + addr_hit[ 40] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_34_OFFSET); + addr_hit[ 41] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_35_OFFSET); + addr_hit[ 42] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_36_OFFSET); + addr_hit[ 43] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_37_OFFSET); + addr_hit[ 44] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_38_OFFSET); + addr_hit[ 45] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_39_OFFSET); + addr_hit[ 46] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_40_OFFSET); + addr_hit[ 47] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_41_OFFSET); + addr_hit[ 48] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_42_OFFSET); + addr_hit[ 49] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_43_OFFSET); + addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_44_OFFSET); + addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_45_OFFSET); + addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_46_OFFSET); + addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_47_OFFSET); + addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_48_OFFSET); + addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_49_OFFSET); + addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_50_OFFSET); + addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_51_OFFSET); + addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_52_OFFSET); + addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_53_OFFSET); + addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_54_OFFSET); + addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_55_OFFSET); + addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_56_OFFSET); + addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_57_OFFSET); + addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_58_OFFSET); + addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_59_OFFSET); + addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_60_OFFSET); + addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_61_OFFSET); + addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_62_OFFSET); + addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_63_OFFSET); + addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_64_OFFSET); + addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_65_OFFSET); + addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_66_OFFSET); + addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_67_OFFSET); + addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_68_OFFSET); + addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_69_OFFSET); + addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_70_OFFSET); + addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_71_OFFSET); + addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_72_OFFSET); + addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_73_OFFSET); + addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_74_OFFSET); + addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_75_OFFSET); + addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_76_OFFSET); + addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_77_OFFSET); + addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_78_OFFSET); + addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_79_OFFSET); + addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_80_OFFSET); + addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_81_OFFSET); + addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_82_OFFSET); + addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_83_OFFSET); + addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_84_OFFSET); + addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_85_OFFSET); + addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_86_OFFSET); + addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_87_OFFSET); + addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_88_OFFSET); + addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_89_OFFSET); + addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_90_OFFSET); + addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_91_OFFSET); + addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_92_OFFSET); + addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_93_OFFSET); + addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_94_OFFSET); + addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_95_OFFSET); + addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_96_OFFSET); + addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_97_OFFSET); + addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_98_OFFSET); + addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET); + addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET); + addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET); + addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET); + addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET); + addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET); + addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET); + addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET); + addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET); + addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET); + addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET); + addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET); + addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET); + addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET); + addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET); + addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET); + addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET); + addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET); + addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET); + addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET); + addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET); + addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET); + addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET); + addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET); + addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET); + addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET); + addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET); + addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET); + addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET); + addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET); + addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET); + addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET); + addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET); + addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET); + addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET); + addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET); + addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET); + addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET); + addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET); + addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET); + addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET); + addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET); + addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET); + addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET); + addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET); + addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET); + addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET); + addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET); + addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET); + addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET); + addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET); + addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET); + addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET); + addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET); + addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET); + addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET); + addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET); + addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET); + addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET); + addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET); + addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET); + addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET); + addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET); + addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET); + addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET); + addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_65_OFFSET); + addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_66_OFFSET); + addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_67_OFFSET); + addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_68_OFFSET); + addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_69_OFFSET); + addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_70_OFFSET); + addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_71_OFFSET); + addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_72_OFFSET); + addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_73_OFFSET); + addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_74_OFFSET); + addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_75_OFFSET); + addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_76_OFFSET); + addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_77_OFFSET); + addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_78_OFFSET); + addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_79_OFFSET); + addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_80_OFFSET); + addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_81_OFFSET); + addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_82_OFFSET); + addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_83_OFFSET); + addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_84_OFFSET); + addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_85_OFFSET); + addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_86_OFFSET); + addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_87_OFFSET); + addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_88_OFFSET); + addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_89_OFFSET); + addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_90_OFFSET); + addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_91_OFFSET); + addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_92_OFFSET); + addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_93_OFFSET); + addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_94_OFFSET); + addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_95_OFFSET); + addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_96_OFFSET); + addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_97_OFFSET); + addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_98_OFFSET); + addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET); + addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET); + addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET); + addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET); + addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET); + addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET); + addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET); + addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET); + addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET); + addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET); + addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET); + addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET); + addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET); + addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET); + addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET); + addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET); + addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET); + addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET); + addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET); + addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET); + addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET); + addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET); + addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET); + addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET); + addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET); + addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET); + addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET); + addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET); + addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET); + addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET); + addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET); + addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET); + addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET); + addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET); + addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET); + addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET); + addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET); + addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET); + addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET); + addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET); + addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET); + addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET); + addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET); + addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET); + addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET); + addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET); + addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET); + addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET); + addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET); + addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET); + addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET); + addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET); + addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET); + addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET); + addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET); + addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET); + addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET); + addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET); + addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET); + addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET); + addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET); + addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET); + addr_hit[266] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET); + addr_hit[267] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET); + addr_hit[268] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET); + addr_hit[269] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_OFFSET); + addr_hit[270] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_OFFSET); + addr_hit[271] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_OFFSET); + addr_hit[272] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_OFFSET); + addr_hit[273] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_OFFSET); + addr_hit[274] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_OFFSET); + addr_hit[275] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_OFFSET); + addr_hit[276] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_OFFSET); + addr_hit[277] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_OFFSET); + addr_hit[278] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_OFFSET); + addr_hit[279] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_75_OFFSET); + addr_hit[280] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_76_OFFSET); + addr_hit[281] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_77_OFFSET); + addr_hit[282] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_78_OFFSET); + addr_hit[283] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_79_OFFSET); + addr_hit[284] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_80_OFFSET); + addr_hit[285] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_81_OFFSET); + addr_hit[286] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_82_OFFSET); + addr_hit[287] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_83_OFFSET); + addr_hit[288] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_84_OFFSET); + addr_hit[289] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_85_OFFSET); + addr_hit[290] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_86_OFFSET); + addr_hit[291] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_87_OFFSET); + addr_hit[292] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_88_OFFSET); + addr_hit[293] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_89_OFFSET); + addr_hit[294] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_90_OFFSET); + addr_hit[295] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_91_OFFSET); + addr_hit[296] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_92_OFFSET); + addr_hit[297] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_93_OFFSET); + addr_hit[298] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_94_OFFSET); + addr_hit[299] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_95_OFFSET); + addr_hit[300] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_96_OFFSET); + addr_hit[301] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_97_OFFSET); + addr_hit[302] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_98_OFFSET); + addr_hit[303] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); + addr_hit[304] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); + addr_hit[305] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); + addr_hit[306] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); + addr_hit[307] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); + addr_hit[308] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); + addr_hit[309] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); + addr_hit[310] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); + addr_hit[311] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); + addr_hit[312] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); + addr_hit[313] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); + addr_hit[314] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); + addr_hit[315] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); + addr_hit[316] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); + addr_hit[317] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); + addr_hit[318] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); + addr_hit[319] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); + addr_hit[320] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); + addr_hit[321] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); + addr_hit[322] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); + addr_hit[323] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); + addr_hit[324] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); + addr_hit[325] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); + addr_hit[326] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); + addr_hit[327] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); + addr_hit[328] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); + addr_hit[329] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); + addr_hit[330] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); + addr_hit[331] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); + addr_hit[332] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); + addr_hit[333] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); + addr_hit[334] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); + addr_hit[335] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); + addr_hit[336] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); + addr_hit[337] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); + addr_hit[338] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); + addr_hit[339] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); + addr_hit[340] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); + addr_hit[341] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); + addr_hit[342] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); + addr_hit[343] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); + addr_hit[344] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); + addr_hit[345] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); + addr_hit[346] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); + addr_hit[347] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); + addr_hit[348] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); + addr_hit[349] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); + addr_hit[350] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); + addr_hit[351] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); + addr_hit[352] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); + addr_hit[353] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); + addr_hit[354] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); + addr_hit[355] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); + addr_hit[356] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); + addr_hit[357] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); + addr_hit[358] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); + addr_hit[359] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); + addr_hit[360] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); + addr_hit[361] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); + addr_hit[362] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); + addr_hit[363] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); + addr_hit[364] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); + addr_hit[365] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); + addr_hit[366] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET); + addr_hit[367] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET); + addr_hit[368] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_65_OFFSET); + addr_hit[369] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_66_OFFSET); + addr_hit[370] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_67_OFFSET); + addr_hit[371] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_68_OFFSET); + addr_hit[372] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_69_OFFSET); + addr_hit[373] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_70_OFFSET); + addr_hit[374] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_71_OFFSET); + addr_hit[375] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_72_OFFSET); + addr_hit[376] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_73_OFFSET); + addr_hit[377] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_74_OFFSET); + addr_hit[378] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_75_OFFSET); + addr_hit[379] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_76_OFFSET); + addr_hit[380] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_77_OFFSET); + addr_hit[381] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_78_OFFSET); + addr_hit[382] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_79_OFFSET); + addr_hit[383] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_80_OFFSET); + addr_hit[384] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_81_OFFSET); + addr_hit[385] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_82_OFFSET); + addr_hit[386] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_83_OFFSET); + addr_hit[387] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_84_OFFSET); + addr_hit[388] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_85_OFFSET); + addr_hit[389] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_86_OFFSET); + addr_hit[390] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_87_OFFSET); + addr_hit[391] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_88_OFFSET); + addr_hit[392] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_89_OFFSET); + addr_hit[393] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_90_OFFSET); + addr_hit[394] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_91_OFFSET); + addr_hit[395] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_92_OFFSET); + addr_hit[396] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_93_OFFSET); + addr_hit[397] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_94_OFFSET); + addr_hit[398] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_95_OFFSET); + addr_hit[399] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_96_OFFSET); + addr_hit[400] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_97_OFFSET); + addr_hit[401] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_98_OFFSET); + addr_hit[402] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); + addr_hit[403] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); + addr_hit[404] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); + addr_hit[405] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); + addr_hit[406] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); + addr_hit[407] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET); + addr_hit[408] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET); + addr_hit[409] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET); + addr_hit[410] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET); + addr_hit[411] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET); + addr_hit[412] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET); + addr_hit[413] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET); + addr_hit[414] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET); + addr_hit[415] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET); + addr_hit[416] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET); + addr_hit[417] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET); + addr_hit[418] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET); + addr_hit[419] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET); + addr_hit[420] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET); + addr_hit[421] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET); + addr_hit[422] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET); + addr_hit[423] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); + addr_hit[424] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); + addr_hit[425] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); + addr_hit[426] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); + addr_hit[427] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); + addr_hit[428] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET); + addr_hit[429] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET); + addr_hit[430] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); + addr_hit[431] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET); + addr_hit[432] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); + addr_hit[433] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET); + addr_hit[434] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); + addr_hit[435] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[436] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[437] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[438] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[439] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[440] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[441] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[442] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); + addr_hit[443] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); + addr_hit[444] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); + addr_hit[445] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET); + addr_hit[446] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); + addr_hit[447] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET); + addr_hit[448] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); + addr_hit[449] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[450] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[451] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[452] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[453] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[454] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[455] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[456] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); + addr_hit[457] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); + addr_hit[458] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); + addr_hit[459] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET); + addr_hit[460] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); + addr_hit[461] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET); + addr_hit[462] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); + addr_hit[463] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[464] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[465] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[466] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[467] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[468] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[469] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[470] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); + addr_hit[471] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); + addr_hit[472] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); + addr_hit[473] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET); + addr_hit[474] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); + addr_hit[475] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET); + addr_hit[476] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); + addr_hit[477] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[478] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[479] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[480] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[481] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[482] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[483] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[484] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); + addr_hit[485] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(ALERT_HANDLER_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(ALERT_HANDLER_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(ALERT_HANDLER_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(ALERT_HANDLER_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(ALERT_HANDLER_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(ALERT_HANDLER_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(ALERT_HANDLER_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(ALERT_HANDLER_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(ALERT_HANDLER_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(ALERT_HANDLER_PERMIT[ 9] & ~reg_be))) | + (addr_hit[ 10] & (|(ALERT_HANDLER_PERMIT[ 10] & ~reg_be))) | + (addr_hit[ 11] & (|(ALERT_HANDLER_PERMIT[ 11] & ~reg_be))) | + (addr_hit[ 12] & (|(ALERT_HANDLER_PERMIT[ 12] & ~reg_be))) | + (addr_hit[ 13] & (|(ALERT_HANDLER_PERMIT[ 13] & ~reg_be))) | + (addr_hit[ 14] & (|(ALERT_HANDLER_PERMIT[ 14] & ~reg_be))) | + (addr_hit[ 15] & (|(ALERT_HANDLER_PERMIT[ 15] & ~reg_be))) | + (addr_hit[ 16] & (|(ALERT_HANDLER_PERMIT[ 16] & ~reg_be))) | + (addr_hit[ 17] & (|(ALERT_HANDLER_PERMIT[ 17] & ~reg_be))) | + (addr_hit[ 18] & (|(ALERT_HANDLER_PERMIT[ 18] & ~reg_be))) | + (addr_hit[ 19] & (|(ALERT_HANDLER_PERMIT[ 19] & ~reg_be))) | + (addr_hit[ 20] & (|(ALERT_HANDLER_PERMIT[ 20] & ~reg_be))) | + (addr_hit[ 21] & (|(ALERT_HANDLER_PERMIT[ 21] & ~reg_be))) | + (addr_hit[ 22] & (|(ALERT_HANDLER_PERMIT[ 22] & ~reg_be))) | + (addr_hit[ 23] & (|(ALERT_HANDLER_PERMIT[ 23] & ~reg_be))) | + (addr_hit[ 24] & (|(ALERT_HANDLER_PERMIT[ 24] & ~reg_be))) | + (addr_hit[ 25] & (|(ALERT_HANDLER_PERMIT[ 25] & ~reg_be))) | + (addr_hit[ 26] & (|(ALERT_HANDLER_PERMIT[ 26] & ~reg_be))) | + (addr_hit[ 27] & (|(ALERT_HANDLER_PERMIT[ 27] & ~reg_be))) | + (addr_hit[ 28] & (|(ALERT_HANDLER_PERMIT[ 28] & ~reg_be))) | + (addr_hit[ 29] & (|(ALERT_HANDLER_PERMIT[ 29] & ~reg_be))) | + (addr_hit[ 30] & (|(ALERT_HANDLER_PERMIT[ 30] & ~reg_be))) | + (addr_hit[ 31] & (|(ALERT_HANDLER_PERMIT[ 31] & ~reg_be))) | + (addr_hit[ 32] & (|(ALERT_HANDLER_PERMIT[ 32] & ~reg_be))) | + (addr_hit[ 33] & (|(ALERT_HANDLER_PERMIT[ 33] & ~reg_be))) | + (addr_hit[ 34] & (|(ALERT_HANDLER_PERMIT[ 34] & ~reg_be))) | + (addr_hit[ 35] & (|(ALERT_HANDLER_PERMIT[ 35] & ~reg_be))) | + (addr_hit[ 36] & (|(ALERT_HANDLER_PERMIT[ 36] & ~reg_be))) | + (addr_hit[ 37] & (|(ALERT_HANDLER_PERMIT[ 37] & ~reg_be))) | + (addr_hit[ 38] & (|(ALERT_HANDLER_PERMIT[ 38] & ~reg_be))) | + (addr_hit[ 39] & (|(ALERT_HANDLER_PERMIT[ 39] & ~reg_be))) | + (addr_hit[ 40] & (|(ALERT_HANDLER_PERMIT[ 40] & ~reg_be))) | + (addr_hit[ 41] & (|(ALERT_HANDLER_PERMIT[ 41] & ~reg_be))) | + (addr_hit[ 42] & (|(ALERT_HANDLER_PERMIT[ 42] & ~reg_be))) | + (addr_hit[ 43] & (|(ALERT_HANDLER_PERMIT[ 43] & ~reg_be))) | + (addr_hit[ 44] & (|(ALERT_HANDLER_PERMIT[ 44] & ~reg_be))) | + (addr_hit[ 45] & (|(ALERT_HANDLER_PERMIT[ 45] & ~reg_be))) | + (addr_hit[ 46] & (|(ALERT_HANDLER_PERMIT[ 46] & ~reg_be))) | + (addr_hit[ 47] & (|(ALERT_HANDLER_PERMIT[ 47] & ~reg_be))) | + (addr_hit[ 48] & (|(ALERT_HANDLER_PERMIT[ 48] & ~reg_be))) | + (addr_hit[ 49] & (|(ALERT_HANDLER_PERMIT[ 49] & ~reg_be))) | + (addr_hit[ 50] & (|(ALERT_HANDLER_PERMIT[ 50] & ~reg_be))) | + (addr_hit[ 51] & (|(ALERT_HANDLER_PERMIT[ 51] & ~reg_be))) | + (addr_hit[ 52] & (|(ALERT_HANDLER_PERMIT[ 52] & ~reg_be))) | + (addr_hit[ 53] & (|(ALERT_HANDLER_PERMIT[ 53] & ~reg_be))) | + (addr_hit[ 54] & (|(ALERT_HANDLER_PERMIT[ 54] & ~reg_be))) | + (addr_hit[ 55] & (|(ALERT_HANDLER_PERMIT[ 55] & ~reg_be))) | + (addr_hit[ 56] & (|(ALERT_HANDLER_PERMIT[ 56] & ~reg_be))) | + (addr_hit[ 57] & (|(ALERT_HANDLER_PERMIT[ 57] & ~reg_be))) | + (addr_hit[ 58] & (|(ALERT_HANDLER_PERMIT[ 58] & ~reg_be))) | + (addr_hit[ 59] & (|(ALERT_HANDLER_PERMIT[ 59] & ~reg_be))) | + (addr_hit[ 60] & (|(ALERT_HANDLER_PERMIT[ 60] & ~reg_be))) | + (addr_hit[ 61] & (|(ALERT_HANDLER_PERMIT[ 61] & ~reg_be))) | + (addr_hit[ 62] & (|(ALERT_HANDLER_PERMIT[ 62] & ~reg_be))) | + (addr_hit[ 63] & (|(ALERT_HANDLER_PERMIT[ 63] & ~reg_be))) | + (addr_hit[ 64] & (|(ALERT_HANDLER_PERMIT[ 64] & ~reg_be))) | + (addr_hit[ 65] & (|(ALERT_HANDLER_PERMIT[ 65] & ~reg_be))) | + (addr_hit[ 66] & (|(ALERT_HANDLER_PERMIT[ 66] & ~reg_be))) | + (addr_hit[ 67] & (|(ALERT_HANDLER_PERMIT[ 67] & ~reg_be))) | + (addr_hit[ 68] & (|(ALERT_HANDLER_PERMIT[ 68] & ~reg_be))) | + (addr_hit[ 69] & (|(ALERT_HANDLER_PERMIT[ 69] & ~reg_be))) | + (addr_hit[ 70] & (|(ALERT_HANDLER_PERMIT[ 70] & ~reg_be))) | + (addr_hit[ 71] & (|(ALERT_HANDLER_PERMIT[ 71] & ~reg_be))) | + (addr_hit[ 72] & (|(ALERT_HANDLER_PERMIT[ 72] & ~reg_be))) | + (addr_hit[ 73] & (|(ALERT_HANDLER_PERMIT[ 73] & ~reg_be))) | + (addr_hit[ 74] & (|(ALERT_HANDLER_PERMIT[ 74] & ~reg_be))) | + (addr_hit[ 75] & (|(ALERT_HANDLER_PERMIT[ 75] & ~reg_be))) | + (addr_hit[ 76] & (|(ALERT_HANDLER_PERMIT[ 76] & ~reg_be))) | + (addr_hit[ 77] & (|(ALERT_HANDLER_PERMIT[ 77] & ~reg_be))) | + (addr_hit[ 78] & (|(ALERT_HANDLER_PERMIT[ 78] & ~reg_be))) | + (addr_hit[ 79] & (|(ALERT_HANDLER_PERMIT[ 79] & ~reg_be))) | + (addr_hit[ 80] & (|(ALERT_HANDLER_PERMIT[ 80] & ~reg_be))) | + (addr_hit[ 81] & (|(ALERT_HANDLER_PERMIT[ 81] & ~reg_be))) | + (addr_hit[ 82] & (|(ALERT_HANDLER_PERMIT[ 82] & ~reg_be))) | + (addr_hit[ 83] & (|(ALERT_HANDLER_PERMIT[ 83] & ~reg_be))) | + (addr_hit[ 84] & (|(ALERT_HANDLER_PERMIT[ 84] & ~reg_be))) | + (addr_hit[ 85] & (|(ALERT_HANDLER_PERMIT[ 85] & ~reg_be))) | + (addr_hit[ 86] & (|(ALERT_HANDLER_PERMIT[ 86] & ~reg_be))) | + (addr_hit[ 87] & (|(ALERT_HANDLER_PERMIT[ 87] & ~reg_be))) | + (addr_hit[ 88] & (|(ALERT_HANDLER_PERMIT[ 88] & ~reg_be))) | + (addr_hit[ 89] & (|(ALERT_HANDLER_PERMIT[ 89] & ~reg_be))) | + (addr_hit[ 90] & (|(ALERT_HANDLER_PERMIT[ 90] & ~reg_be))) | + (addr_hit[ 91] & (|(ALERT_HANDLER_PERMIT[ 91] & ~reg_be))) | + (addr_hit[ 92] & (|(ALERT_HANDLER_PERMIT[ 92] & ~reg_be))) | + (addr_hit[ 93] & (|(ALERT_HANDLER_PERMIT[ 93] & ~reg_be))) | + (addr_hit[ 94] & (|(ALERT_HANDLER_PERMIT[ 94] & ~reg_be))) | + (addr_hit[ 95] & (|(ALERT_HANDLER_PERMIT[ 95] & ~reg_be))) | + (addr_hit[ 96] & (|(ALERT_HANDLER_PERMIT[ 96] & ~reg_be))) | + (addr_hit[ 97] & (|(ALERT_HANDLER_PERMIT[ 97] & ~reg_be))) | + (addr_hit[ 98] & (|(ALERT_HANDLER_PERMIT[ 98] & ~reg_be))) | + (addr_hit[ 99] & (|(ALERT_HANDLER_PERMIT[ 99] & ~reg_be))) | + (addr_hit[100] & (|(ALERT_HANDLER_PERMIT[100] & ~reg_be))) | + (addr_hit[101] & (|(ALERT_HANDLER_PERMIT[101] & ~reg_be))) | + (addr_hit[102] & (|(ALERT_HANDLER_PERMIT[102] & ~reg_be))) | + (addr_hit[103] & (|(ALERT_HANDLER_PERMIT[103] & ~reg_be))) | + (addr_hit[104] & (|(ALERT_HANDLER_PERMIT[104] & ~reg_be))) | + (addr_hit[105] & (|(ALERT_HANDLER_PERMIT[105] & ~reg_be))) | + (addr_hit[106] & (|(ALERT_HANDLER_PERMIT[106] & ~reg_be))) | + (addr_hit[107] & (|(ALERT_HANDLER_PERMIT[107] & ~reg_be))) | + (addr_hit[108] & (|(ALERT_HANDLER_PERMIT[108] & ~reg_be))) | + (addr_hit[109] & (|(ALERT_HANDLER_PERMIT[109] & ~reg_be))) | + (addr_hit[110] & (|(ALERT_HANDLER_PERMIT[110] & ~reg_be))) | + (addr_hit[111] & (|(ALERT_HANDLER_PERMIT[111] & ~reg_be))) | + (addr_hit[112] & (|(ALERT_HANDLER_PERMIT[112] & ~reg_be))) | + (addr_hit[113] & (|(ALERT_HANDLER_PERMIT[113] & ~reg_be))) | + (addr_hit[114] & (|(ALERT_HANDLER_PERMIT[114] & ~reg_be))) | + (addr_hit[115] & (|(ALERT_HANDLER_PERMIT[115] & ~reg_be))) | + (addr_hit[116] & (|(ALERT_HANDLER_PERMIT[116] & ~reg_be))) | + (addr_hit[117] & (|(ALERT_HANDLER_PERMIT[117] & ~reg_be))) | + (addr_hit[118] & (|(ALERT_HANDLER_PERMIT[118] & ~reg_be))) | + (addr_hit[119] & (|(ALERT_HANDLER_PERMIT[119] & ~reg_be))) | + (addr_hit[120] & (|(ALERT_HANDLER_PERMIT[120] & ~reg_be))) | + (addr_hit[121] & (|(ALERT_HANDLER_PERMIT[121] & ~reg_be))) | + (addr_hit[122] & (|(ALERT_HANDLER_PERMIT[122] & ~reg_be))) | + (addr_hit[123] & (|(ALERT_HANDLER_PERMIT[123] & ~reg_be))) | + (addr_hit[124] & (|(ALERT_HANDLER_PERMIT[124] & ~reg_be))) | + (addr_hit[125] & (|(ALERT_HANDLER_PERMIT[125] & ~reg_be))) | + (addr_hit[126] & (|(ALERT_HANDLER_PERMIT[126] & ~reg_be))) | + (addr_hit[127] & (|(ALERT_HANDLER_PERMIT[127] & ~reg_be))) | + (addr_hit[128] & (|(ALERT_HANDLER_PERMIT[128] & ~reg_be))) | + (addr_hit[129] & (|(ALERT_HANDLER_PERMIT[129] & ~reg_be))) | + (addr_hit[130] & (|(ALERT_HANDLER_PERMIT[130] & ~reg_be))) | + (addr_hit[131] & (|(ALERT_HANDLER_PERMIT[131] & ~reg_be))) | + (addr_hit[132] & (|(ALERT_HANDLER_PERMIT[132] & ~reg_be))) | + (addr_hit[133] & (|(ALERT_HANDLER_PERMIT[133] & ~reg_be))) | + (addr_hit[134] & (|(ALERT_HANDLER_PERMIT[134] & ~reg_be))) | + (addr_hit[135] & (|(ALERT_HANDLER_PERMIT[135] & ~reg_be))) | + (addr_hit[136] & (|(ALERT_HANDLER_PERMIT[136] & ~reg_be))) | + (addr_hit[137] & (|(ALERT_HANDLER_PERMIT[137] & ~reg_be))) | + (addr_hit[138] & (|(ALERT_HANDLER_PERMIT[138] & ~reg_be))) | + (addr_hit[139] & (|(ALERT_HANDLER_PERMIT[139] & ~reg_be))) | + (addr_hit[140] & (|(ALERT_HANDLER_PERMIT[140] & ~reg_be))) | + (addr_hit[141] & (|(ALERT_HANDLER_PERMIT[141] & ~reg_be))) | + (addr_hit[142] & (|(ALERT_HANDLER_PERMIT[142] & ~reg_be))) | + (addr_hit[143] & (|(ALERT_HANDLER_PERMIT[143] & ~reg_be))) | + (addr_hit[144] & (|(ALERT_HANDLER_PERMIT[144] & ~reg_be))) | + (addr_hit[145] & (|(ALERT_HANDLER_PERMIT[145] & ~reg_be))) | + (addr_hit[146] & (|(ALERT_HANDLER_PERMIT[146] & ~reg_be))) | + (addr_hit[147] & (|(ALERT_HANDLER_PERMIT[147] & ~reg_be))) | + (addr_hit[148] & (|(ALERT_HANDLER_PERMIT[148] & ~reg_be))) | + (addr_hit[149] & (|(ALERT_HANDLER_PERMIT[149] & ~reg_be))) | + (addr_hit[150] & (|(ALERT_HANDLER_PERMIT[150] & ~reg_be))) | + (addr_hit[151] & (|(ALERT_HANDLER_PERMIT[151] & ~reg_be))) | + (addr_hit[152] & (|(ALERT_HANDLER_PERMIT[152] & ~reg_be))) | + (addr_hit[153] & (|(ALERT_HANDLER_PERMIT[153] & ~reg_be))) | + (addr_hit[154] & (|(ALERT_HANDLER_PERMIT[154] & ~reg_be))) | + (addr_hit[155] & (|(ALERT_HANDLER_PERMIT[155] & ~reg_be))) | + (addr_hit[156] & (|(ALERT_HANDLER_PERMIT[156] & ~reg_be))) | + (addr_hit[157] & (|(ALERT_HANDLER_PERMIT[157] & ~reg_be))) | + (addr_hit[158] & (|(ALERT_HANDLER_PERMIT[158] & ~reg_be))) | + (addr_hit[159] & (|(ALERT_HANDLER_PERMIT[159] & ~reg_be))) | + (addr_hit[160] & (|(ALERT_HANDLER_PERMIT[160] & ~reg_be))) | + (addr_hit[161] & (|(ALERT_HANDLER_PERMIT[161] & ~reg_be))) | + (addr_hit[162] & (|(ALERT_HANDLER_PERMIT[162] & ~reg_be))) | + (addr_hit[163] & (|(ALERT_HANDLER_PERMIT[163] & ~reg_be))) | + (addr_hit[164] & (|(ALERT_HANDLER_PERMIT[164] & ~reg_be))) | + (addr_hit[165] & (|(ALERT_HANDLER_PERMIT[165] & ~reg_be))) | + (addr_hit[166] & (|(ALERT_HANDLER_PERMIT[166] & ~reg_be))) | + (addr_hit[167] & (|(ALERT_HANDLER_PERMIT[167] & ~reg_be))) | + (addr_hit[168] & (|(ALERT_HANDLER_PERMIT[168] & ~reg_be))) | + (addr_hit[169] & (|(ALERT_HANDLER_PERMIT[169] & ~reg_be))) | + (addr_hit[170] & (|(ALERT_HANDLER_PERMIT[170] & ~reg_be))) | + (addr_hit[171] & (|(ALERT_HANDLER_PERMIT[171] & ~reg_be))) | + (addr_hit[172] & (|(ALERT_HANDLER_PERMIT[172] & ~reg_be))) | + (addr_hit[173] & (|(ALERT_HANDLER_PERMIT[173] & ~reg_be))) | + (addr_hit[174] & (|(ALERT_HANDLER_PERMIT[174] & ~reg_be))) | + (addr_hit[175] & (|(ALERT_HANDLER_PERMIT[175] & ~reg_be))) | + (addr_hit[176] & (|(ALERT_HANDLER_PERMIT[176] & ~reg_be))) | + (addr_hit[177] & (|(ALERT_HANDLER_PERMIT[177] & ~reg_be))) | + (addr_hit[178] & (|(ALERT_HANDLER_PERMIT[178] & ~reg_be))) | + (addr_hit[179] & (|(ALERT_HANDLER_PERMIT[179] & ~reg_be))) | + (addr_hit[180] & (|(ALERT_HANDLER_PERMIT[180] & ~reg_be))) | + (addr_hit[181] & (|(ALERT_HANDLER_PERMIT[181] & ~reg_be))) | + (addr_hit[182] & (|(ALERT_HANDLER_PERMIT[182] & ~reg_be))) | + (addr_hit[183] & (|(ALERT_HANDLER_PERMIT[183] & ~reg_be))) | + (addr_hit[184] & (|(ALERT_HANDLER_PERMIT[184] & ~reg_be))) | + (addr_hit[185] & (|(ALERT_HANDLER_PERMIT[185] & ~reg_be))) | + (addr_hit[186] & (|(ALERT_HANDLER_PERMIT[186] & ~reg_be))) | + (addr_hit[187] & (|(ALERT_HANDLER_PERMIT[187] & ~reg_be))) | + (addr_hit[188] & (|(ALERT_HANDLER_PERMIT[188] & ~reg_be))) | + (addr_hit[189] & (|(ALERT_HANDLER_PERMIT[189] & ~reg_be))) | + (addr_hit[190] & (|(ALERT_HANDLER_PERMIT[190] & ~reg_be))) | + (addr_hit[191] & (|(ALERT_HANDLER_PERMIT[191] & ~reg_be))) | + (addr_hit[192] & (|(ALERT_HANDLER_PERMIT[192] & ~reg_be))) | + (addr_hit[193] & (|(ALERT_HANDLER_PERMIT[193] & ~reg_be))) | + (addr_hit[194] & (|(ALERT_HANDLER_PERMIT[194] & ~reg_be))) | + (addr_hit[195] & (|(ALERT_HANDLER_PERMIT[195] & ~reg_be))) | + (addr_hit[196] & (|(ALERT_HANDLER_PERMIT[196] & ~reg_be))) | + (addr_hit[197] & (|(ALERT_HANDLER_PERMIT[197] & ~reg_be))) | + (addr_hit[198] & (|(ALERT_HANDLER_PERMIT[198] & ~reg_be))) | + (addr_hit[199] & (|(ALERT_HANDLER_PERMIT[199] & ~reg_be))) | + (addr_hit[200] & (|(ALERT_HANDLER_PERMIT[200] & ~reg_be))) | + (addr_hit[201] & (|(ALERT_HANDLER_PERMIT[201] & ~reg_be))) | + (addr_hit[202] & (|(ALERT_HANDLER_PERMIT[202] & ~reg_be))) | + (addr_hit[203] & (|(ALERT_HANDLER_PERMIT[203] & ~reg_be))) | + (addr_hit[204] & (|(ALERT_HANDLER_PERMIT[204] & ~reg_be))) | + (addr_hit[205] & (|(ALERT_HANDLER_PERMIT[205] & ~reg_be))) | + (addr_hit[206] & (|(ALERT_HANDLER_PERMIT[206] & ~reg_be))) | + (addr_hit[207] & (|(ALERT_HANDLER_PERMIT[207] & ~reg_be))) | + (addr_hit[208] & (|(ALERT_HANDLER_PERMIT[208] & ~reg_be))) | + (addr_hit[209] & (|(ALERT_HANDLER_PERMIT[209] & ~reg_be))) | + (addr_hit[210] & (|(ALERT_HANDLER_PERMIT[210] & ~reg_be))) | + (addr_hit[211] & (|(ALERT_HANDLER_PERMIT[211] & ~reg_be))) | + (addr_hit[212] & (|(ALERT_HANDLER_PERMIT[212] & ~reg_be))) | + (addr_hit[213] & (|(ALERT_HANDLER_PERMIT[213] & ~reg_be))) | + (addr_hit[214] & (|(ALERT_HANDLER_PERMIT[214] & ~reg_be))) | + (addr_hit[215] & (|(ALERT_HANDLER_PERMIT[215] & ~reg_be))) | + (addr_hit[216] & (|(ALERT_HANDLER_PERMIT[216] & ~reg_be))) | + (addr_hit[217] & (|(ALERT_HANDLER_PERMIT[217] & ~reg_be))) | + (addr_hit[218] & (|(ALERT_HANDLER_PERMIT[218] & ~reg_be))) | + (addr_hit[219] & (|(ALERT_HANDLER_PERMIT[219] & ~reg_be))) | + (addr_hit[220] & (|(ALERT_HANDLER_PERMIT[220] & ~reg_be))) | + (addr_hit[221] & (|(ALERT_HANDLER_PERMIT[221] & ~reg_be))) | + (addr_hit[222] & (|(ALERT_HANDLER_PERMIT[222] & ~reg_be))) | + (addr_hit[223] & (|(ALERT_HANDLER_PERMIT[223] & ~reg_be))) | + (addr_hit[224] & (|(ALERT_HANDLER_PERMIT[224] & ~reg_be))) | + (addr_hit[225] & (|(ALERT_HANDLER_PERMIT[225] & ~reg_be))) | + (addr_hit[226] & (|(ALERT_HANDLER_PERMIT[226] & ~reg_be))) | + (addr_hit[227] & (|(ALERT_HANDLER_PERMIT[227] & ~reg_be))) | + (addr_hit[228] & (|(ALERT_HANDLER_PERMIT[228] & ~reg_be))) | + (addr_hit[229] & (|(ALERT_HANDLER_PERMIT[229] & ~reg_be))) | + (addr_hit[230] & (|(ALERT_HANDLER_PERMIT[230] & ~reg_be))) | + (addr_hit[231] & (|(ALERT_HANDLER_PERMIT[231] & ~reg_be))) | + (addr_hit[232] & (|(ALERT_HANDLER_PERMIT[232] & ~reg_be))) | + (addr_hit[233] & (|(ALERT_HANDLER_PERMIT[233] & ~reg_be))) | + (addr_hit[234] & (|(ALERT_HANDLER_PERMIT[234] & ~reg_be))) | + (addr_hit[235] & (|(ALERT_HANDLER_PERMIT[235] & ~reg_be))) | + (addr_hit[236] & (|(ALERT_HANDLER_PERMIT[236] & ~reg_be))) | + (addr_hit[237] & (|(ALERT_HANDLER_PERMIT[237] & ~reg_be))) | + (addr_hit[238] & (|(ALERT_HANDLER_PERMIT[238] & ~reg_be))) | + (addr_hit[239] & (|(ALERT_HANDLER_PERMIT[239] & ~reg_be))) | + (addr_hit[240] & (|(ALERT_HANDLER_PERMIT[240] & ~reg_be))) | + (addr_hit[241] & (|(ALERT_HANDLER_PERMIT[241] & ~reg_be))) | + (addr_hit[242] & (|(ALERT_HANDLER_PERMIT[242] & ~reg_be))) | + (addr_hit[243] & (|(ALERT_HANDLER_PERMIT[243] & ~reg_be))) | + (addr_hit[244] & (|(ALERT_HANDLER_PERMIT[244] & ~reg_be))) | + (addr_hit[245] & (|(ALERT_HANDLER_PERMIT[245] & ~reg_be))) | + (addr_hit[246] & (|(ALERT_HANDLER_PERMIT[246] & ~reg_be))) | + (addr_hit[247] & (|(ALERT_HANDLER_PERMIT[247] & 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~reg_be))) | + (addr_hit[436] & (|(ALERT_HANDLER_PERMIT[436] & ~reg_be))) | + (addr_hit[437] & (|(ALERT_HANDLER_PERMIT[437] & ~reg_be))) | + (addr_hit[438] & (|(ALERT_HANDLER_PERMIT[438] & ~reg_be))) | + (addr_hit[439] & (|(ALERT_HANDLER_PERMIT[439] & ~reg_be))) | + (addr_hit[440] & (|(ALERT_HANDLER_PERMIT[440] & ~reg_be))) | + (addr_hit[441] & (|(ALERT_HANDLER_PERMIT[441] & ~reg_be))) | + (addr_hit[442] & (|(ALERT_HANDLER_PERMIT[442] & ~reg_be))) | + (addr_hit[443] & (|(ALERT_HANDLER_PERMIT[443] & ~reg_be))) | + (addr_hit[444] & (|(ALERT_HANDLER_PERMIT[444] & ~reg_be))) | + (addr_hit[445] & (|(ALERT_HANDLER_PERMIT[445] & ~reg_be))) | + (addr_hit[446] & (|(ALERT_HANDLER_PERMIT[446] & ~reg_be))) | + (addr_hit[447] & (|(ALERT_HANDLER_PERMIT[447] & ~reg_be))) | + (addr_hit[448] & (|(ALERT_HANDLER_PERMIT[448] & ~reg_be))) | + (addr_hit[449] & (|(ALERT_HANDLER_PERMIT[449] & ~reg_be))) | + (addr_hit[450] & (|(ALERT_HANDLER_PERMIT[450] & ~reg_be))) | + (addr_hit[451] & (|(ALERT_HANDLER_PERMIT[451] & ~reg_be))) | + (addr_hit[452] & (|(ALERT_HANDLER_PERMIT[452] & ~reg_be))) | + (addr_hit[453] & (|(ALERT_HANDLER_PERMIT[453] & ~reg_be))) | + (addr_hit[454] & (|(ALERT_HANDLER_PERMIT[454] & ~reg_be))) | + (addr_hit[455] & (|(ALERT_HANDLER_PERMIT[455] & ~reg_be))) | + (addr_hit[456] & (|(ALERT_HANDLER_PERMIT[456] & ~reg_be))) | + (addr_hit[457] & (|(ALERT_HANDLER_PERMIT[457] & ~reg_be))) | + (addr_hit[458] & (|(ALERT_HANDLER_PERMIT[458] & ~reg_be))) | + (addr_hit[459] & (|(ALERT_HANDLER_PERMIT[459] & ~reg_be))) | + (addr_hit[460] & (|(ALERT_HANDLER_PERMIT[460] & ~reg_be))) | + (addr_hit[461] & (|(ALERT_HANDLER_PERMIT[461] & ~reg_be))) | + (addr_hit[462] & (|(ALERT_HANDLER_PERMIT[462] & ~reg_be))) | + (addr_hit[463] & (|(ALERT_HANDLER_PERMIT[463] & ~reg_be))) | + (addr_hit[464] & (|(ALERT_HANDLER_PERMIT[464] & ~reg_be))) | + (addr_hit[465] & (|(ALERT_HANDLER_PERMIT[465] & ~reg_be))) | + (addr_hit[466] & (|(ALERT_HANDLER_PERMIT[466] & ~reg_be))) | + (addr_hit[467] & (|(ALERT_HANDLER_PERMIT[467] & ~reg_be))) | + (addr_hit[468] & (|(ALERT_HANDLER_PERMIT[468] & ~reg_be))) | + (addr_hit[469] & (|(ALERT_HANDLER_PERMIT[469] & ~reg_be))) | + (addr_hit[470] & (|(ALERT_HANDLER_PERMIT[470] & ~reg_be))) | + (addr_hit[471] & (|(ALERT_HANDLER_PERMIT[471] & ~reg_be))) | + (addr_hit[472] & (|(ALERT_HANDLER_PERMIT[472] & ~reg_be))) | + (addr_hit[473] & (|(ALERT_HANDLER_PERMIT[473] & ~reg_be))) | + (addr_hit[474] & (|(ALERT_HANDLER_PERMIT[474] & ~reg_be))) | + (addr_hit[475] & (|(ALERT_HANDLER_PERMIT[475] & ~reg_be))) | + (addr_hit[476] & (|(ALERT_HANDLER_PERMIT[476] & ~reg_be))) | + (addr_hit[477] & (|(ALERT_HANDLER_PERMIT[477] & ~reg_be))) | + (addr_hit[478] & (|(ALERT_HANDLER_PERMIT[478] & ~reg_be))) | + (addr_hit[479] & (|(ALERT_HANDLER_PERMIT[479] & ~reg_be))) | + (addr_hit[480] & (|(ALERT_HANDLER_PERMIT[480] & ~reg_be))) | + (addr_hit[481] & (|(ALERT_HANDLER_PERMIT[481] & ~reg_be))) | + (addr_hit[482] & (|(ALERT_HANDLER_PERMIT[482] & ~reg_be))) | + (addr_hit[483] & (|(ALERT_HANDLER_PERMIT[483] & ~reg_be))) | + (addr_hit[484] & (|(ALERT_HANDLER_PERMIT[484] & ~reg_be))) | + (addr_hit[485] & (|(ALERT_HANDLER_PERMIT[485] & ~reg_be))))); + end + + // Generate write-enables + assign intr_state_we = addr_hit[0] & reg_we & !reg_error; + + assign intr_state_classa_wd = reg_wdata[0]; + + assign intr_state_classb_wd = reg_wdata[1]; + + assign intr_state_classc_wd = reg_wdata[2]; + + assign intr_state_classd_wd = reg_wdata[3]; + assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; + + assign intr_enable_classa_wd = reg_wdata[0]; + + assign intr_enable_classb_wd = reg_wdata[1]; + + assign intr_enable_classc_wd = reg_wdata[2]; + + assign intr_enable_classd_wd = reg_wdata[3]; + assign intr_test_we = addr_hit[2] & reg_we & !reg_error; + + assign intr_test_classa_wd = reg_wdata[0]; + + assign intr_test_classb_wd = reg_wdata[1]; + + assign intr_test_classc_wd = reg_wdata[2]; + + assign intr_test_classd_wd = reg_wdata[3]; + assign ping_timer_regwen_we = addr_hit[3] & reg_we & !reg_error; + + assign ping_timer_regwen_wd = reg_wdata[0]; + assign ping_timeout_cyc_shadowed_re = addr_hit[4] & reg_re & !reg_error; + assign ping_timeout_cyc_shadowed_we = addr_hit[4] & reg_we & !reg_error; + + assign ping_timeout_cyc_shadowed_wd = reg_wdata[15:0]; + assign ping_timer_en_shadowed_re = addr_hit[5] & reg_re & !reg_error; + assign ping_timer_en_shadowed_we = addr_hit[5] & reg_we & !reg_error; + + assign ping_timer_en_shadowed_wd = reg_wdata[0]; + assign alert_regwen_0_we = addr_hit[6] & reg_we & !reg_error; + + assign alert_regwen_0_wd = reg_wdata[0]; + assign alert_regwen_1_we = addr_hit[7] & reg_we & !reg_error; + + assign alert_regwen_1_wd = reg_wdata[0]; + assign alert_regwen_2_we = addr_hit[8] & reg_we & !reg_error; + + assign alert_regwen_2_wd = reg_wdata[0]; + assign alert_regwen_3_we = addr_hit[9] & reg_we & !reg_error; + + assign alert_regwen_3_wd = reg_wdata[0]; + assign alert_regwen_4_we = addr_hit[10] & reg_we & !reg_error; + + assign alert_regwen_4_wd = reg_wdata[0]; + assign alert_regwen_5_we = addr_hit[11] & reg_we & !reg_error; + + assign alert_regwen_5_wd = reg_wdata[0]; + assign alert_regwen_6_we = addr_hit[12] & reg_we & !reg_error; + + assign alert_regwen_6_wd = reg_wdata[0]; + assign alert_regwen_7_we = addr_hit[13] & reg_we & !reg_error; + + assign alert_regwen_7_wd = reg_wdata[0]; + assign alert_regwen_8_we = addr_hit[14] & reg_we & !reg_error; + + assign alert_regwen_8_wd = reg_wdata[0]; + assign alert_regwen_9_we = addr_hit[15] & reg_we & !reg_error; + + assign alert_regwen_9_wd = reg_wdata[0]; + assign alert_regwen_10_we = addr_hit[16] & reg_we & !reg_error; + + assign alert_regwen_10_wd = reg_wdata[0]; + assign alert_regwen_11_we = addr_hit[17] & reg_we & !reg_error; + + assign alert_regwen_11_wd = reg_wdata[0]; + assign alert_regwen_12_we = addr_hit[18] & reg_we & !reg_error; + + assign alert_regwen_12_wd = reg_wdata[0]; + assign alert_regwen_13_we = addr_hit[19] & reg_we & !reg_error; + + assign alert_regwen_13_wd = reg_wdata[0]; + assign alert_regwen_14_we = addr_hit[20] & reg_we & !reg_error; + + assign alert_regwen_14_wd = reg_wdata[0]; + assign alert_regwen_15_we = addr_hit[21] & reg_we & !reg_error; + + assign alert_regwen_15_wd = reg_wdata[0]; + assign alert_regwen_16_we = addr_hit[22] & reg_we & !reg_error; + + assign alert_regwen_16_wd = reg_wdata[0]; + assign alert_regwen_17_we = addr_hit[23] & reg_we & !reg_error; + + assign alert_regwen_17_wd = reg_wdata[0]; + assign alert_regwen_18_we = addr_hit[24] & reg_we & !reg_error; + + assign alert_regwen_18_wd = reg_wdata[0]; + assign alert_regwen_19_we = addr_hit[25] & reg_we & !reg_error; + + assign alert_regwen_19_wd = reg_wdata[0]; + assign alert_regwen_20_we = addr_hit[26] & reg_we & !reg_error; + + assign alert_regwen_20_wd = reg_wdata[0]; + assign alert_regwen_21_we = addr_hit[27] & reg_we & !reg_error; + + assign alert_regwen_21_wd = reg_wdata[0]; + assign alert_regwen_22_we = addr_hit[28] & reg_we & !reg_error; + + assign alert_regwen_22_wd = reg_wdata[0]; + assign alert_regwen_23_we = addr_hit[29] & reg_we & !reg_error; + + assign alert_regwen_23_wd = reg_wdata[0]; + assign alert_regwen_24_we = addr_hit[30] & reg_we & !reg_error; + + assign alert_regwen_24_wd = reg_wdata[0]; + assign alert_regwen_25_we = addr_hit[31] & reg_we & !reg_error; + + assign alert_regwen_25_wd = reg_wdata[0]; + assign alert_regwen_26_we = addr_hit[32] & reg_we & !reg_error; + + assign alert_regwen_26_wd = reg_wdata[0]; + assign alert_regwen_27_we = addr_hit[33] & reg_we & !reg_error; + + assign alert_regwen_27_wd = reg_wdata[0]; + assign alert_regwen_28_we = addr_hit[34] & reg_we & !reg_error; + + assign alert_regwen_28_wd = reg_wdata[0]; + assign alert_regwen_29_we = addr_hit[35] & reg_we & !reg_error; + + assign alert_regwen_29_wd = reg_wdata[0]; + assign alert_regwen_30_we = addr_hit[36] & reg_we & !reg_error; + + assign alert_regwen_30_wd = reg_wdata[0]; + assign alert_regwen_31_we = addr_hit[37] & reg_we & !reg_error; + + assign alert_regwen_31_wd = reg_wdata[0]; + assign alert_regwen_32_we = addr_hit[38] & reg_we & !reg_error; + + assign alert_regwen_32_wd = reg_wdata[0]; + assign alert_regwen_33_we = addr_hit[39] & reg_we & !reg_error; + + assign alert_regwen_33_wd = reg_wdata[0]; + assign alert_regwen_34_we = addr_hit[40] & reg_we & !reg_error; + + assign alert_regwen_34_wd = reg_wdata[0]; + assign alert_regwen_35_we = addr_hit[41] & reg_we & !reg_error; + + assign alert_regwen_35_wd = reg_wdata[0]; + assign alert_regwen_36_we = addr_hit[42] & reg_we & !reg_error; + + assign alert_regwen_36_wd = reg_wdata[0]; + assign alert_regwen_37_we = addr_hit[43] & reg_we & !reg_error; + + assign alert_regwen_37_wd = reg_wdata[0]; + assign alert_regwen_38_we = addr_hit[44] & reg_we & !reg_error; + + assign alert_regwen_38_wd = reg_wdata[0]; + assign alert_regwen_39_we = addr_hit[45] & reg_we & !reg_error; + + assign alert_regwen_39_wd = reg_wdata[0]; + assign alert_regwen_40_we = addr_hit[46] & reg_we & !reg_error; + + assign alert_regwen_40_wd = reg_wdata[0]; + assign alert_regwen_41_we = addr_hit[47] & reg_we & !reg_error; + + assign alert_regwen_41_wd = reg_wdata[0]; + assign alert_regwen_42_we = addr_hit[48] & reg_we & !reg_error; + + assign alert_regwen_42_wd = reg_wdata[0]; + assign alert_regwen_43_we = addr_hit[49] & reg_we & !reg_error; + + assign alert_regwen_43_wd = reg_wdata[0]; + assign alert_regwen_44_we = addr_hit[50] & reg_we & !reg_error; + + assign alert_regwen_44_wd = reg_wdata[0]; + assign alert_regwen_45_we = addr_hit[51] & reg_we & !reg_error; + + assign alert_regwen_45_wd = reg_wdata[0]; + assign alert_regwen_46_we = addr_hit[52] & reg_we & !reg_error; + + assign alert_regwen_46_wd = reg_wdata[0]; + assign alert_regwen_47_we = addr_hit[53] & reg_we & !reg_error; + + assign alert_regwen_47_wd = reg_wdata[0]; + assign alert_regwen_48_we = addr_hit[54] & reg_we & !reg_error; + + assign alert_regwen_48_wd = reg_wdata[0]; + assign alert_regwen_49_we = addr_hit[55] & reg_we & !reg_error; + + assign alert_regwen_49_wd = reg_wdata[0]; + assign alert_regwen_50_we = addr_hit[56] & reg_we & !reg_error; + + assign alert_regwen_50_wd = reg_wdata[0]; + assign alert_regwen_51_we = addr_hit[57] & reg_we & !reg_error; + + assign alert_regwen_51_wd = reg_wdata[0]; + assign alert_regwen_52_we = addr_hit[58] & reg_we & !reg_error; + + assign alert_regwen_52_wd = reg_wdata[0]; + assign alert_regwen_53_we = addr_hit[59] & reg_we & !reg_error; + + assign alert_regwen_53_wd = reg_wdata[0]; + assign alert_regwen_54_we = addr_hit[60] & reg_we & !reg_error; + + assign alert_regwen_54_wd = reg_wdata[0]; + assign alert_regwen_55_we = addr_hit[61] & reg_we & !reg_error; + + assign alert_regwen_55_wd = reg_wdata[0]; + assign alert_regwen_56_we = addr_hit[62] & reg_we & !reg_error; + + assign alert_regwen_56_wd = reg_wdata[0]; + assign alert_regwen_57_we = addr_hit[63] & reg_we & !reg_error; + + assign alert_regwen_57_wd = reg_wdata[0]; + assign alert_regwen_58_we = addr_hit[64] & reg_we & !reg_error; + + assign alert_regwen_58_wd = reg_wdata[0]; + assign alert_regwen_59_we = addr_hit[65] & reg_we & !reg_error; + + assign alert_regwen_59_wd = reg_wdata[0]; + assign alert_regwen_60_we = addr_hit[66] & reg_we & !reg_error; + + assign alert_regwen_60_wd = reg_wdata[0]; + assign alert_regwen_61_we = addr_hit[67] & reg_we & !reg_error; + + assign alert_regwen_61_wd = reg_wdata[0]; + assign alert_regwen_62_we = addr_hit[68] & reg_we & !reg_error; + + assign alert_regwen_62_wd = reg_wdata[0]; + assign alert_regwen_63_we = addr_hit[69] & reg_we & !reg_error; + + assign alert_regwen_63_wd = reg_wdata[0]; + assign alert_regwen_64_we = addr_hit[70] & reg_we & !reg_error; + + assign alert_regwen_64_wd = reg_wdata[0]; + assign alert_regwen_65_we = addr_hit[71] & reg_we & !reg_error; + + assign alert_regwen_65_wd = reg_wdata[0]; + assign alert_regwen_66_we = addr_hit[72] & reg_we & !reg_error; + + assign alert_regwen_66_wd = reg_wdata[0]; + assign alert_regwen_67_we = addr_hit[73] & reg_we & !reg_error; + + assign alert_regwen_67_wd = reg_wdata[0]; + assign alert_regwen_68_we = addr_hit[74] & reg_we & !reg_error; + + assign alert_regwen_68_wd = reg_wdata[0]; + assign alert_regwen_69_we = addr_hit[75] & reg_we & !reg_error; + + assign alert_regwen_69_wd = reg_wdata[0]; + assign alert_regwen_70_we = addr_hit[76] & reg_we & !reg_error; + + assign alert_regwen_70_wd = reg_wdata[0]; + assign alert_regwen_71_we = addr_hit[77] & reg_we & !reg_error; + + assign alert_regwen_71_wd = reg_wdata[0]; + assign alert_regwen_72_we = addr_hit[78] & reg_we & !reg_error; + + assign alert_regwen_72_wd = reg_wdata[0]; + assign alert_regwen_73_we = addr_hit[79] & reg_we & !reg_error; + + assign alert_regwen_73_wd = reg_wdata[0]; + assign alert_regwen_74_we = addr_hit[80] & reg_we & !reg_error; + + assign alert_regwen_74_wd = reg_wdata[0]; + assign alert_regwen_75_we = addr_hit[81] & reg_we & !reg_error; + + assign alert_regwen_75_wd = reg_wdata[0]; + assign alert_regwen_76_we = addr_hit[82] & reg_we & !reg_error; + + assign alert_regwen_76_wd = reg_wdata[0]; + assign alert_regwen_77_we = addr_hit[83] & reg_we & !reg_error; + + assign alert_regwen_77_wd = reg_wdata[0]; + assign alert_regwen_78_we = addr_hit[84] & reg_we & !reg_error; + + assign alert_regwen_78_wd = reg_wdata[0]; + assign alert_regwen_79_we = addr_hit[85] & reg_we & !reg_error; + + assign alert_regwen_79_wd = reg_wdata[0]; + assign alert_regwen_80_we = addr_hit[86] & reg_we & !reg_error; + + assign alert_regwen_80_wd = reg_wdata[0]; + assign alert_regwen_81_we = addr_hit[87] & reg_we & !reg_error; + + assign alert_regwen_81_wd = reg_wdata[0]; + assign alert_regwen_82_we = addr_hit[88] & reg_we & !reg_error; + + assign alert_regwen_82_wd = reg_wdata[0]; + assign alert_regwen_83_we = addr_hit[89] & reg_we & !reg_error; + + assign alert_regwen_83_wd = reg_wdata[0]; + assign alert_regwen_84_we = addr_hit[90] & reg_we & !reg_error; + + assign alert_regwen_84_wd = reg_wdata[0]; + assign alert_regwen_85_we = addr_hit[91] & reg_we & !reg_error; + + assign alert_regwen_85_wd = reg_wdata[0]; + assign alert_regwen_86_we = addr_hit[92] & reg_we & !reg_error; + + assign alert_regwen_86_wd = reg_wdata[0]; + assign alert_regwen_87_we = addr_hit[93] & reg_we & !reg_error; + + assign alert_regwen_87_wd = reg_wdata[0]; + assign alert_regwen_88_we = addr_hit[94] & reg_we & !reg_error; + + assign alert_regwen_88_wd = reg_wdata[0]; + assign alert_regwen_89_we = addr_hit[95] & reg_we & !reg_error; + + assign alert_regwen_89_wd = reg_wdata[0]; + assign alert_regwen_90_we = addr_hit[96] & reg_we & !reg_error; + + assign alert_regwen_90_wd = reg_wdata[0]; + assign alert_regwen_91_we = addr_hit[97] & reg_we & !reg_error; + + assign alert_regwen_91_wd = reg_wdata[0]; + assign alert_regwen_92_we = addr_hit[98] & reg_we & !reg_error; + + assign alert_regwen_92_wd = reg_wdata[0]; + assign alert_regwen_93_we = addr_hit[99] & reg_we & !reg_error; + + assign alert_regwen_93_wd = reg_wdata[0]; + assign alert_regwen_94_we = addr_hit[100] & reg_we & !reg_error; + + assign alert_regwen_94_wd = reg_wdata[0]; + assign alert_regwen_95_we = addr_hit[101] & reg_we & !reg_error; + + assign alert_regwen_95_wd = reg_wdata[0]; + assign alert_regwen_96_we = addr_hit[102] & reg_we & !reg_error; + + assign alert_regwen_96_wd = reg_wdata[0]; + assign alert_regwen_97_we = addr_hit[103] & reg_we & !reg_error; + + assign alert_regwen_97_wd = reg_wdata[0]; + assign alert_regwen_98_we = addr_hit[104] & reg_we & !reg_error; + + assign alert_regwen_98_wd = reg_wdata[0]; + assign alert_en_shadowed_0_re = addr_hit[105] & reg_re & !reg_error; + assign alert_en_shadowed_0_we = addr_hit[105] & reg_we & !reg_error; + + assign alert_en_shadowed_0_wd = reg_wdata[0]; + assign alert_en_shadowed_1_re = addr_hit[106] & reg_re & !reg_error; + assign alert_en_shadowed_1_we = addr_hit[106] & reg_we & !reg_error; + + assign alert_en_shadowed_1_wd = reg_wdata[0]; + assign alert_en_shadowed_2_re = addr_hit[107] & reg_re & !reg_error; + assign alert_en_shadowed_2_we = addr_hit[107] & reg_we & !reg_error; + + assign alert_en_shadowed_2_wd = reg_wdata[0]; + assign alert_en_shadowed_3_re = addr_hit[108] & reg_re & !reg_error; + assign alert_en_shadowed_3_we = addr_hit[108] & reg_we & !reg_error; + + assign alert_en_shadowed_3_wd = reg_wdata[0]; + assign alert_en_shadowed_4_re = addr_hit[109] & reg_re & !reg_error; + assign alert_en_shadowed_4_we = addr_hit[109] & reg_we & !reg_error; + + assign alert_en_shadowed_4_wd = reg_wdata[0]; + assign alert_en_shadowed_5_re = addr_hit[110] & reg_re & !reg_error; + assign alert_en_shadowed_5_we = addr_hit[110] & reg_we & !reg_error; + + assign alert_en_shadowed_5_wd = reg_wdata[0]; + assign alert_en_shadowed_6_re = addr_hit[111] & reg_re & !reg_error; + assign alert_en_shadowed_6_we = addr_hit[111] & reg_we & !reg_error; + + assign alert_en_shadowed_6_wd = reg_wdata[0]; + assign alert_en_shadowed_7_re = addr_hit[112] & reg_re & !reg_error; + assign alert_en_shadowed_7_we = addr_hit[112] & reg_we & !reg_error; + + assign alert_en_shadowed_7_wd = reg_wdata[0]; + assign alert_en_shadowed_8_re = addr_hit[113] & reg_re & !reg_error; + assign alert_en_shadowed_8_we = addr_hit[113] & reg_we & !reg_error; + + assign alert_en_shadowed_8_wd = reg_wdata[0]; + assign alert_en_shadowed_9_re = addr_hit[114] & reg_re & !reg_error; + assign alert_en_shadowed_9_we = addr_hit[114] & reg_we & !reg_error; + + assign alert_en_shadowed_9_wd = reg_wdata[0]; + assign alert_en_shadowed_10_re = addr_hit[115] & reg_re & !reg_error; + assign alert_en_shadowed_10_we = addr_hit[115] & reg_we & !reg_error; + + assign alert_en_shadowed_10_wd = reg_wdata[0]; + assign alert_en_shadowed_11_re = addr_hit[116] & reg_re & !reg_error; + assign alert_en_shadowed_11_we = addr_hit[116] & reg_we & !reg_error; + + assign alert_en_shadowed_11_wd = reg_wdata[0]; + assign alert_en_shadowed_12_re = addr_hit[117] & reg_re & !reg_error; + assign alert_en_shadowed_12_we = addr_hit[117] & reg_we & !reg_error; + + assign alert_en_shadowed_12_wd = reg_wdata[0]; + assign alert_en_shadowed_13_re = addr_hit[118] & reg_re & !reg_error; + assign alert_en_shadowed_13_we = addr_hit[118] & reg_we & !reg_error; + + assign alert_en_shadowed_13_wd = reg_wdata[0]; + assign alert_en_shadowed_14_re = addr_hit[119] & reg_re & !reg_error; + assign alert_en_shadowed_14_we = addr_hit[119] & reg_we & !reg_error; + + assign alert_en_shadowed_14_wd = reg_wdata[0]; + assign alert_en_shadowed_15_re = addr_hit[120] & reg_re & !reg_error; + assign alert_en_shadowed_15_we = addr_hit[120] & reg_we & !reg_error; + + assign alert_en_shadowed_15_wd = reg_wdata[0]; + assign alert_en_shadowed_16_re = addr_hit[121] & reg_re & !reg_error; + assign alert_en_shadowed_16_we = addr_hit[121] & reg_we & !reg_error; + + assign alert_en_shadowed_16_wd = reg_wdata[0]; + assign alert_en_shadowed_17_re = addr_hit[122] & reg_re & !reg_error; + assign alert_en_shadowed_17_we = addr_hit[122] & reg_we & !reg_error; + + assign alert_en_shadowed_17_wd = reg_wdata[0]; + assign alert_en_shadowed_18_re = addr_hit[123] & reg_re & !reg_error; + assign alert_en_shadowed_18_we = addr_hit[123] & reg_we & !reg_error; + + assign alert_en_shadowed_18_wd = reg_wdata[0]; + assign alert_en_shadowed_19_re = addr_hit[124] & reg_re & !reg_error; + assign alert_en_shadowed_19_we = addr_hit[124] & reg_we & !reg_error; + + assign alert_en_shadowed_19_wd = reg_wdata[0]; + assign alert_en_shadowed_20_re = addr_hit[125] & reg_re & !reg_error; + assign alert_en_shadowed_20_we = addr_hit[125] & reg_we & !reg_error; + + assign alert_en_shadowed_20_wd = reg_wdata[0]; + assign alert_en_shadowed_21_re = addr_hit[126] & reg_re & !reg_error; + assign alert_en_shadowed_21_we = addr_hit[126] & reg_we & !reg_error; + + assign alert_en_shadowed_21_wd = reg_wdata[0]; + assign alert_en_shadowed_22_re = addr_hit[127] & reg_re & !reg_error; + assign alert_en_shadowed_22_we = addr_hit[127] & reg_we & !reg_error; + + assign alert_en_shadowed_22_wd = reg_wdata[0]; + assign alert_en_shadowed_23_re = addr_hit[128] & reg_re & !reg_error; + assign alert_en_shadowed_23_we = addr_hit[128] & reg_we & !reg_error; + + assign alert_en_shadowed_23_wd = reg_wdata[0]; + assign alert_en_shadowed_24_re = addr_hit[129] & reg_re & !reg_error; + assign alert_en_shadowed_24_we = addr_hit[129] & reg_we & !reg_error; + + assign alert_en_shadowed_24_wd = reg_wdata[0]; + assign alert_en_shadowed_25_re = addr_hit[130] & reg_re & !reg_error; + assign alert_en_shadowed_25_we = addr_hit[130] & reg_we & !reg_error; + + assign alert_en_shadowed_25_wd = reg_wdata[0]; + assign alert_en_shadowed_26_re = addr_hit[131] & reg_re & !reg_error; + assign alert_en_shadowed_26_we = addr_hit[131] & reg_we & !reg_error; + + assign alert_en_shadowed_26_wd = reg_wdata[0]; + assign alert_en_shadowed_27_re = addr_hit[132] & reg_re & !reg_error; + assign alert_en_shadowed_27_we = addr_hit[132] & reg_we & !reg_error; + + assign alert_en_shadowed_27_wd = reg_wdata[0]; + assign alert_en_shadowed_28_re = addr_hit[133] & reg_re & !reg_error; + assign alert_en_shadowed_28_we = addr_hit[133] & reg_we & !reg_error; + + assign alert_en_shadowed_28_wd = reg_wdata[0]; + assign alert_en_shadowed_29_re = addr_hit[134] & reg_re & !reg_error; + assign alert_en_shadowed_29_we = addr_hit[134] & reg_we & !reg_error; + + assign alert_en_shadowed_29_wd = reg_wdata[0]; + assign alert_en_shadowed_30_re = addr_hit[135] & reg_re & !reg_error; + assign alert_en_shadowed_30_we = addr_hit[135] & reg_we & !reg_error; + + assign alert_en_shadowed_30_wd = reg_wdata[0]; + assign alert_en_shadowed_31_re = addr_hit[136] & reg_re & !reg_error; + assign alert_en_shadowed_31_we = addr_hit[136] & reg_we & !reg_error; + + assign alert_en_shadowed_31_wd = reg_wdata[0]; + assign alert_en_shadowed_32_re = addr_hit[137] & reg_re & !reg_error; + assign alert_en_shadowed_32_we = addr_hit[137] & reg_we & !reg_error; + + assign alert_en_shadowed_32_wd = reg_wdata[0]; + assign alert_en_shadowed_33_re = addr_hit[138] & reg_re & !reg_error; + assign alert_en_shadowed_33_we = addr_hit[138] & reg_we & !reg_error; + + assign alert_en_shadowed_33_wd = reg_wdata[0]; + assign alert_en_shadowed_34_re = addr_hit[139] & reg_re & !reg_error; + assign alert_en_shadowed_34_we = addr_hit[139] & reg_we & !reg_error; + + assign alert_en_shadowed_34_wd = reg_wdata[0]; + assign alert_en_shadowed_35_re = addr_hit[140] & reg_re & !reg_error; + assign alert_en_shadowed_35_we = addr_hit[140] & reg_we & !reg_error; + + assign alert_en_shadowed_35_wd = reg_wdata[0]; + assign alert_en_shadowed_36_re = addr_hit[141] & reg_re & !reg_error; + assign alert_en_shadowed_36_we = addr_hit[141] & reg_we & !reg_error; + + assign alert_en_shadowed_36_wd = reg_wdata[0]; + assign alert_en_shadowed_37_re = addr_hit[142] & reg_re & !reg_error; + assign alert_en_shadowed_37_we = addr_hit[142] & reg_we & !reg_error; + + assign alert_en_shadowed_37_wd = reg_wdata[0]; + assign alert_en_shadowed_38_re = addr_hit[143] & reg_re & !reg_error; + assign alert_en_shadowed_38_we = addr_hit[143] & reg_we & !reg_error; + + assign alert_en_shadowed_38_wd = reg_wdata[0]; + assign alert_en_shadowed_39_re = addr_hit[144] & reg_re & !reg_error; + assign alert_en_shadowed_39_we = addr_hit[144] & reg_we & !reg_error; + + assign alert_en_shadowed_39_wd = reg_wdata[0]; + assign alert_en_shadowed_40_re = addr_hit[145] & reg_re & !reg_error; + assign alert_en_shadowed_40_we = addr_hit[145] & reg_we & !reg_error; + + assign alert_en_shadowed_40_wd = reg_wdata[0]; + assign alert_en_shadowed_41_re = addr_hit[146] & reg_re & !reg_error; + assign alert_en_shadowed_41_we = addr_hit[146] & reg_we & !reg_error; + + assign alert_en_shadowed_41_wd = reg_wdata[0]; + assign alert_en_shadowed_42_re = addr_hit[147] & reg_re & !reg_error; + assign alert_en_shadowed_42_we = addr_hit[147] & reg_we & !reg_error; + + assign alert_en_shadowed_42_wd = reg_wdata[0]; + assign alert_en_shadowed_43_re = addr_hit[148] & reg_re & !reg_error; + assign alert_en_shadowed_43_we = addr_hit[148] & reg_we & !reg_error; + + assign alert_en_shadowed_43_wd = reg_wdata[0]; + assign alert_en_shadowed_44_re = addr_hit[149] & reg_re & !reg_error; + assign alert_en_shadowed_44_we = addr_hit[149] & reg_we & !reg_error; + + assign alert_en_shadowed_44_wd = reg_wdata[0]; + assign alert_en_shadowed_45_re = addr_hit[150] & reg_re & !reg_error; + assign alert_en_shadowed_45_we = addr_hit[150] & reg_we & !reg_error; + + assign alert_en_shadowed_45_wd = reg_wdata[0]; + assign alert_en_shadowed_46_re = addr_hit[151] & reg_re & !reg_error; + assign alert_en_shadowed_46_we = addr_hit[151] & reg_we & !reg_error; + + assign alert_en_shadowed_46_wd = reg_wdata[0]; + assign alert_en_shadowed_47_re = addr_hit[152] & reg_re & !reg_error; + assign alert_en_shadowed_47_we = addr_hit[152] & reg_we & !reg_error; + + assign alert_en_shadowed_47_wd = reg_wdata[0]; + assign alert_en_shadowed_48_re = addr_hit[153] & reg_re & !reg_error; + assign alert_en_shadowed_48_we = addr_hit[153] & reg_we & !reg_error; + + assign alert_en_shadowed_48_wd = reg_wdata[0]; + assign alert_en_shadowed_49_re = addr_hit[154] & reg_re & !reg_error; + assign alert_en_shadowed_49_we = addr_hit[154] & reg_we & !reg_error; + + assign alert_en_shadowed_49_wd = reg_wdata[0]; + assign alert_en_shadowed_50_re = addr_hit[155] & reg_re & !reg_error; + assign alert_en_shadowed_50_we = addr_hit[155] & reg_we & !reg_error; + + assign alert_en_shadowed_50_wd = reg_wdata[0]; + assign alert_en_shadowed_51_re = addr_hit[156] & reg_re & !reg_error; + assign alert_en_shadowed_51_we = addr_hit[156] & reg_we & !reg_error; + + assign alert_en_shadowed_51_wd = reg_wdata[0]; + assign alert_en_shadowed_52_re = addr_hit[157] & reg_re & !reg_error; + assign alert_en_shadowed_52_we = addr_hit[157] & reg_we & !reg_error; + + assign alert_en_shadowed_52_wd = reg_wdata[0]; + assign alert_en_shadowed_53_re = addr_hit[158] & reg_re & !reg_error; + assign alert_en_shadowed_53_we = addr_hit[158] & reg_we & !reg_error; + + assign alert_en_shadowed_53_wd = reg_wdata[0]; + assign alert_en_shadowed_54_re = addr_hit[159] & reg_re & !reg_error; + assign alert_en_shadowed_54_we = addr_hit[159] & reg_we & !reg_error; + + assign alert_en_shadowed_54_wd = reg_wdata[0]; + assign alert_en_shadowed_55_re = addr_hit[160] & reg_re & !reg_error; + assign alert_en_shadowed_55_we = addr_hit[160] & reg_we & !reg_error; + + assign alert_en_shadowed_55_wd = reg_wdata[0]; + assign alert_en_shadowed_56_re = addr_hit[161] & reg_re & !reg_error; + assign alert_en_shadowed_56_we = addr_hit[161] & reg_we & !reg_error; + + assign alert_en_shadowed_56_wd = reg_wdata[0]; + assign alert_en_shadowed_57_re = addr_hit[162] & reg_re & !reg_error; + assign alert_en_shadowed_57_we = addr_hit[162] & reg_we & !reg_error; + + assign alert_en_shadowed_57_wd = reg_wdata[0]; + assign alert_en_shadowed_58_re = addr_hit[163] & reg_re & !reg_error; + assign alert_en_shadowed_58_we = addr_hit[163] & reg_we & !reg_error; + + assign alert_en_shadowed_58_wd = reg_wdata[0]; + assign alert_en_shadowed_59_re = addr_hit[164] & reg_re & !reg_error; + assign alert_en_shadowed_59_we = addr_hit[164] & reg_we & !reg_error; + + assign alert_en_shadowed_59_wd = reg_wdata[0]; + assign alert_en_shadowed_60_re = addr_hit[165] & reg_re & !reg_error; + assign alert_en_shadowed_60_we = addr_hit[165] & reg_we & !reg_error; + + assign alert_en_shadowed_60_wd = reg_wdata[0]; + assign alert_en_shadowed_61_re = addr_hit[166] & reg_re & !reg_error; + assign alert_en_shadowed_61_we = addr_hit[166] & reg_we & !reg_error; + + assign alert_en_shadowed_61_wd = reg_wdata[0]; + assign alert_en_shadowed_62_re = addr_hit[167] & reg_re & !reg_error; + assign alert_en_shadowed_62_we = addr_hit[167] & reg_we & !reg_error; + + assign alert_en_shadowed_62_wd = reg_wdata[0]; + assign alert_en_shadowed_63_re = addr_hit[168] & reg_re & !reg_error; + assign alert_en_shadowed_63_we = addr_hit[168] & reg_we & !reg_error; + + assign alert_en_shadowed_63_wd = reg_wdata[0]; + assign alert_en_shadowed_64_re = addr_hit[169] & reg_re & !reg_error; + assign alert_en_shadowed_64_we = addr_hit[169] & reg_we & !reg_error; + + assign alert_en_shadowed_64_wd = reg_wdata[0]; + assign alert_en_shadowed_65_re = addr_hit[170] & reg_re & !reg_error; + assign alert_en_shadowed_65_we = addr_hit[170] & reg_we & !reg_error; + + assign alert_en_shadowed_65_wd = reg_wdata[0]; + assign alert_en_shadowed_66_re = addr_hit[171] & reg_re & !reg_error; + assign alert_en_shadowed_66_we = addr_hit[171] & reg_we & !reg_error; + + assign alert_en_shadowed_66_wd = reg_wdata[0]; + assign alert_en_shadowed_67_re = addr_hit[172] & reg_re & !reg_error; + assign alert_en_shadowed_67_we = addr_hit[172] & reg_we & !reg_error; + + assign alert_en_shadowed_67_wd = reg_wdata[0]; + assign alert_en_shadowed_68_re = addr_hit[173] & reg_re & !reg_error; + assign alert_en_shadowed_68_we = addr_hit[173] & reg_we & !reg_error; + + assign alert_en_shadowed_68_wd = reg_wdata[0]; + assign alert_en_shadowed_69_re = addr_hit[174] & reg_re & !reg_error; + assign alert_en_shadowed_69_we = addr_hit[174] & reg_we & !reg_error; + + assign alert_en_shadowed_69_wd = reg_wdata[0]; + assign alert_en_shadowed_70_re = addr_hit[175] & reg_re & !reg_error; + assign alert_en_shadowed_70_we = addr_hit[175] & reg_we & !reg_error; + + assign alert_en_shadowed_70_wd = reg_wdata[0]; + assign alert_en_shadowed_71_re = addr_hit[176] & reg_re & !reg_error; + assign alert_en_shadowed_71_we = addr_hit[176] & reg_we & !reg_error; + + assign alert_en_shadowed_71_wd = reg_wdata[0]; + assign alert_en_shadowed_72_re = addr_hit[177] & reg_re & !reg_error; + assign alert_en_shadowed_72_we = addr_hit[177] & reg_we & !reg_error; + + assign alert_en_shadowed_72_wd = reg_wdata[0]; + assign alert_en_shadowed_73_re = addr_hit[178] & reg_re & !reg_error; + assign alert_en_shadowed_73_we = addr_hit[178] & reg_we & !reg_error; + + assign alert_en_shadowed_73_wd = reg_wdata[0]; + assign alert_en_shadowed_74_re = addr_hit[179] & reg_re & !reg_error; + assign alert_en_shadowed_74_we = addr_hit[179] & reg_we & !reg_error; + + assign alert_en_shadowed_74_wd = reg_wdata[0]; + assign alert_en_shadowed_75_re = addr_hit[180] & reg_re & !reg_error; + assign alert_en_shadowed_75_we = addr_hit[180] & reg_we & !reg_error; + + assign alert_en_shadowed_75_wd = reg_wdata[0]; + assign alert_en_shadowed_76_re = addr_hit[181] & reg_re & !reg_error; + assign alert_en_shadowed_76_we = addr_hit[181] & reg_we & !reg_error; + + assign alert_en_shadowed_76_wd = reg_wdata[0]; + assign alert_en_shadowed_77_re = addr_hit[182] & reg_re & !reg_error; + assign alert_en_shadowed_77_we = addr_hit[182] & reg_we & !reg_error; + + assign alert_en_shadowed_77_wd = reg_wdata[0]; + assign alert_en_shadowed_78_re = addr_hit[183] & reg_re & !reg_error; + assign alert_en_shadowed_78_we = addr_hit[183] & reg_we & !reg_error; + + assign alert_en_shadowed_78_wd = reg_wdata[0]; + assign alert_en_shadowed_79_re = addr_hit[184] & reg_re & !reg_error; + assign alert_en_shadowed_79_we = addr_hit[184] & reg_we & !reg_error; + + assign alert_en_shadowed_79_wd = reg_wdata[0]; + assign alert_en_shadowed_80_re = addr_hit[185] & reg_re & !reg_error; + assign alert_en_shadowed_80_we = addr_hit[185] & reg_we & !reg_error; + + assign alert_en_shadowed_80_wd = reg_wdata[0]; + assign alert_en_shadowed_81_re = addr_hit[186] & reg_re & !reg_error; + assign alert_en_shadowed_81_we = addr_hit[186] & reg_we & !reg_error; + + assign alert_en_shadowed_81_wd = reg_wdata[0]; + assign alert_en_shadowed_82_re = addr_hit[187] & reg_re & !reg_error; + assign alert_en_shadowed_82_we = addr_hit[187] & reg_we & !reg_error; + + assign alert_en_shadowed_82_wd = reg_wdata[0]; + assign alert_en_shadowed_83_re = addr_hit[188] & reg_re & !reg_error; + assign alert_en_shadowed_83_we = addr_hit[188] & reg_we & !reg_error; + + assign alert_en_shadowed_83_wd = reg_wdata[0]; + assign alert_en_shadowed_84_re = addr_hit[189] & reg_re & !reg_error; + assign alert_en_shadowed_84_we = addr_hit[189] & reg_we & !reg_error; + + assign alert_en_shadowed_84_wd = reg_wdata[0]; + assign alert_en_shadowed_85_re = addr_hit[190] & reg_re & !reg_error; + assign alert_en_shadowed_85_we = addr_hit[190] & reg_we & !reg_error; + + assign alert_en_shadowed_85_wd = reg_wdata[0]; + assign alert_en_shadowed_86_re = addr_hit[191] & reg_re & !reg_error; + assign alert_en_shadowed_86_we = addr_hit[191] & reg_we & !reg_error; + + assign alert_en_shadowed_86_wd = reg_wdata[0]; + assign alert_en_shadowed_87_re = addr_hit[192] & reg_re & !reg_error; + assign alert_en_shadowed_87_we = addr_hit[192] & reg_we & !reg_error; + + assign alert_en_shadowed_87_wd = reg_wdata[0]; + assign alert_en_shadowed_88_re = addr_hit[193] & reg_re & !reg_error; + assign alert_en_shadowed_88_we = addr_hit[193] & reg_we & !reg_error; + + assign alert_en_shadowed_88_wd = reg_wdata[0]; + assign alert_en_shadowed_89_re = addr_hit[194] & reg_re & !reg_error; + assign alert_en_shadowed_89_we = addr_hit[194] & reg_we & !reg_error; + + assign alert_en_shadowed_89_wd = reg_wdata[0]; + assign alert_en_shadowed_90_re = addr_hit[195] & reg_re & !reg_error; + assign alert_en_shadowed_90_we = addr_hit[195] & reg_we & !reg_error; + + assign alert_en_shadowed_90_wd = reg_wdata[0]; + assign alert_en_shadowed_91_re = addr_hit[196] & reg_re & !reg_error; + assign alert_en_shadowed_91_we = addr_hit[196] & reg_we & !reg_error; + + assign alert_en_shadowed_91_wd = reg_wdata[0]; + assign alert_en_shadowed_92_re = addr_hit[197] & reg_re & !reg_error; + assign alert_en_shadowed_92_we = addr_hit[197] & reg_we & !reg_error; + + assign alert_en_shadowed_92_wd = reg_wdata[0]; + assign alert_en_shadowed_93_re = addr_hit[198] & reg_re & !reg_error; + assign alert_en_shadowed_93_we = addr_hit[198] & reg_we & !reg_error; + + assign alert_en_shadowed_93_wd = reg_wdata[0]; + assign alert_en_shadowed_94_re = addr_hit[199] & reg_re & !reg_error; + assign alert_en_shadowed_94_we = addr_hit[199] & reg_we & !reg_error; + + assign alert_en_shadowed_94_wd = reg_wdata[0]; + assign alert_en_shadowed_95_re = addr_hit[200] & reg_re & !reg_error; + assign alert_en_shadowed_95_we = addr_hit[200] & reg_we & !reg_error; + + assign alert_en_shadowed_95_wd = reg_wdata[0]; + assign alert_en_shadowed_96_re = addr_hit[201] & reg_re & !reg_error; + assign alert_en_shadowed_96_we = addr_hit[201] & reg_we & !reg_error; + + assign alert_en_shadowed_96_wd = reg_wdata[0]; + assign alert_en_shadowed_97_re = addr_hit[202] & reg_re & !reg_error; + assign alert_en_shadowed_97_we = addr_hit[202] & reg_we & !reg_error; + + assign alert_en_shadowed_97_wd = reg_wdata[0]; + assign alert_en_shadowed_98_re = addr_hit[203] & reg_re & !reg_error; + assign alert_en_shadowed_98_we = addr_hit[203] & reg_we & !reg_error; + + assign alert_en_shadowed_98_wd = reg_wdata[0]; + assign alert_class_shadowed_0_re = addr_hit[204] & reg_re & !reg_error; + assign alert_class_shadowed_0_we = addr_hit[204] & reg_we & !reg_error; + + assign alert_class_shadowed_0_wd = reg_wdata[1:0]; + assign alert_class_shadowed_1_re = addr_hit[205] & reg_re & !reg_error; + assign alert_class_shadowed_1_we = addr_hit[205] & reg_we & !reg_error; + + assign alert_class_shadowed_1_wd = reg_wdata[1:0]; + assign alert_class_shadowed_2_re = addr_hit[206] & reg_re & !reg_error; + assign alert_class_shadowed_2_we = addr_hit[206] & reg_we & !reg_error; + + assign alert_class_shadowed_2_wd = reg_wdata[1:0]; + assign alert_class_shadowed_3_re = addr_hit[207] & reg_re & !reg_error; + assign alert_class_shadowed_3_we = addr_hit[207] & reg_we & !reg_error; + + assign alert_class_shadowed_3_wd = reg_wdata[1:0]; + assign alert_class_shadowed_4_re = addr_hit[208] & reg_re & !reg_error; + assign alert_class_shadowed_4_we = addr_hit[208] & reg_we & !reg_error; + + assign alert_class_shadowed_4_wd = reg_wdata[1:0]; + assign alert_class_shadowed_5_re = addr_hit[209] & reg_re & !reg_error; + assign alert_class_shadowed_5_we = addr_hit[209] & reg_we & !reg_error; + + assign alert_class_shadowed_5_wd = reg_wdata[1:0]; + assign alert_class_shadowed_6_re = addr_hit[210] & reg_re & !reg_error; + assign alert_class_shadowed_6_we = addr_hit[210] & reg_we & !reg_error; + + assign alert_class_shadowed_6_wd = reg_wdata[1:0]; + assign alert_class_shadowed_7_re = addr_hit[211] & reg_re & !reg_error; + assign alert_class_shadowed_7_we = addr_hit[211] & reg_we & !reg_error; + + assign alert_class_shadowed_7_wd = reg_wdata[1:0]; + assign alert_class_shadowed_8_re = addr_hit[212] & reg_re & !reg_error; + assign alert_class_shadowed_8_we = addr_hit[212] & reg_we & !reg_error; + + assign alert_class_shadowed_8_wd = reg_wdata[1:0]; + assign alert_class_shadowed_9_re = addr_hit[213] & reg_re & !reg_error; + assign alert_class_shadowed_9_we = addr_hit[213] & reg_we & !reg_error; + + assign alert_class_shadowed_9_wd = reg_wdata[1:0]; + assign alert_class_shadowed_10_re = addr_hit[214] & reg_re & !reg_error; + assign alert_class_shadowed_10_we = addr_hit[214] & reg_we & !reg_error; + + assign alert_class_shadowed_10_wd = reg_wdata[1:0]; + assign alert_class_shadowed_11_re = addr_hit[215] & reg_re & !reg_error; + assign alert_class_shadowed_11_we = addr_hit[215] & reg_we & !reg_error; + + assign alert_class_shadowed_11_wd = reg_wdata[1:0]; + assign alert_class_shadowed_12_re = addr_hit[216] & reg_re & !reg_error; + assign alert_class_shadowed_12_we = addr_hit[216] & reg_we & !reg_error; + + assign alert_class_shadowed_12_wd = reg_wdata[1:0]; + assign alert_class_shadowed_13_re = addr_hit[217] & reg_re & !reg_error; + assign alert_class_shadowed_13_we = addr_hit[217] & reg_we & !reg_error; + + assign alert_class_shadowed_13_wd = reg_wdata[1:0]; + assign alert_class_shadowed_14_re = addr_hit[218] & reg_re & !reg_error; + assign alert_class_shadowed_14_we = addr_hit[218] & reg_we & !reg_error; + + assign alert_class_shadowed_14_wd = reg_wdata[1:0]; + assign alert_class_shadowed_15_re = addr_hit[219] & reg_re & !reg_error; + assign alert_class_shadowed_15_we = addr_hit[219] & reg_we & !reg_error; + + assign alert_class_shadowed_15_wd = reg_wdata[1:0]; + assign alert_class_shadowed_16_re = addr_hit[220] & reg_re & !reg_error; + assign alert_class_shadowed_16_we = addr_hit[220] & reg_we & !reg_error; + + assign alert_class_shadowed_16_wd = reg_wdata[1:0]; + assign alert_class_shadowed_17_re = addr_hit[221] & reg_re & !reg_error; + assign alert_class_shadowed_17_we = addr_hit[221] & reg_we & !reg_error; + + assign alert_class_shadowed_17_wd = reg_wdata[1:0]; + assign alert_class_shadowed_18_re = addr_hit[222] & reg_re & !reg_error; + assign alert_class_shadowed_18_we = addr_hit[222] & reg_we & !reg_error; + + assign alert_class_shadowed_18_wd = reg_wdata[1:0]; + assign alert_class_shadowed_19_re = addr_hit[223] & reg_re & !reg_error; + assign alert_class_shadowed_19_we = addr_hit[223] & reg_we & !reg_error; + + assign alert_class_shadowed_19_wd = reg_wdata[1:0]; + assign alert_class_shadowed_20_re = addr_hit[224] & reg_re & !reg_error; + assign alert_class_shadowed_20_we = addr_hit[224] & reg_we & !reg_error; + + assign alert_class_shadowed_20_wd = reg_wdata[1:0]; + assign alert_class_shadowed_21_re = addr_hit[225] & reg_re & !reg_error; + assign alert_class_shadowed_21_we = addr_hit[225] & reg_we & !reg_error; + + assign alert_class_shadowed_21_wd = reg_wdata[1:0]; + assign alert_class_shadowed_22_re = addr_hit[226] & reg_re & !reg_error; + assign alert_class_shadowed_22_we = addr_hit[226] & reg_we & !reg_error; + + assign alert_class_shadowed_22_wd = reg_wdata[1:0]; + assign alert_class_shadowed_23_re = addr_hit[227] & reg_re & !reg_error; + assign alert_class_shadowed_23_we = addr_hit[227] & reg_we & !reg_error; + + assign alert_class_shadowed_23_wd = reg_wdata[1:0]; + assign alert_class_shadowed_24_re = addr_hit[228] & reg_re & !reg_error; + assign alert_class_shadowed_24_we = addr_hit[228] & reg_we & !reg_error; + + assign alert_class_shadowed_24_wd = reg_wdata[1:0]; + assign alert_class_shadowed_25_re = addr_hit[229] & reg_re & !reg_error; + assign alert_class_shadowed_25_we = addr_hit[229] & reg_we & !reg_error; + + assign alert_class_shadowed_25_wd = reg_wdata[1:0]; + assign alert_class_shadowed_26_re = addr_hit[230] & reg_re & !reg_error; + assign alert_class_shadowed_26_we = addr_hit[230] & reg_we & !reg_error; + + assign alert_class_shadowed_26_wd = reg_wdata[1:0]; + assign alert_class_shadowed_27_re = addr_hit[231] & reg_re & !reg_error; + assign alert_class_shadowed_27_we = addr_hit[231] & reg_we & !reg_error; + + assign alert_class_shadowed_27_wd = reg_wdata[1:0]; + assign alert_class_shadowed_28_re = addr_hit[232] & reg_re & !reg_error; + assign alert_class_shadowed_28_we = addr_hit[232] & reg_we & !reg_error; + + assign alert_class_shadowed_28_wd = reg_wdata[1:0]; + assign alert_class_shadowed_29_re = addr_hit[233] & reg_re & !reg_error; + assign alert_class_shadowed_29_we = addr_hit[233] & reg_we & !reg_error; + + assign alert_class_shadowed_29_wd = reg_wdata[1:0]; + assign alert_class_shadowed_30_re = addr_hit[234] & reg_re & !reg_error; + assign alert_class_shadowed_30_we = addr_hit[234] & reg_we & !reg_error; + + assign alert_class_shadowed_30_wd = reg_wdata[1:0]; + assign alert_class_shadowed_31_re = addr_hit[235] & reg_re & !reg_error; + assign alert_class_shadowed_31_we = addr_hit[235] & reg_we & !reg_error; + + assign alert_class_shadowed_31_wd = reg_wdata[1:0]; + assign alert_class_shadowed_32_re = addr_hit[236] & reg_re & !reg_error; + assign alert_class_shadowed_32_we = addr_hit[236] & reg_we & !reg_error; + + assign alert_class_shadowed_32_wd = reg_wdata[1:0]; + assign alert_class_shadowed_33_re = addr_hit[237] & reg_re & !reg_error; + assign alert_class_shadowed_33_we = addr_hit[237] & reg_we & !reg_error; + + assign alert_class_shadowed_33_wd = reg_wdata[1:0]; + assign alert_class_shadowed_34_re = addr_hit[238] & reg_re & !reg_error; + assign alert_class_shadowed_34_we = addr_hit[238] & reg_we & !reg_error; + + assign alert_class_shadowed_34_wd = reg_wdata[1:0]; + assign alert_class_shadowed_35_re = addr_hit[239] & reg_re & !reg_error; + assign alert_class_shadowed_35_we = addr_hit[239] & reg_we & !reg_error; + + assign alert_class_shadowed_35_wd = reg_wdata[1:0]; + assign alert_class_shadowed_36_re = addr_hit[240] & reg_re & !reg_error; + assign alert_class_shadowed_36_we = addr_hit[240] & reg_we & !reg_error; + + assign alert_class_shadowed_36_wd = reg_wdata[1:0]; + assign alert_class_shadowed_37_re = addr_hit[241] & reg_re & !reg_error; + assign alert_class_shadowed_37_we = addr_hit[241] & reg_we & !reg_error; + + assign alert_class_shadowed_37_wd = reg_wdata[1:0]; + assign alert_class_shadowed_38_re = addr_hit[242] & reg_re & !reg_error; + assign alert_class_shadowed_38_we = addr_hit[242] & reg_we & !reg_error; + + assign alert_class_shadowed_38_wd = reg_wdata[1:0]; + assign alert_class_shadowed_39_re = addr_hit[243] & reg_re & !reg_error; + assign alert_class_shadowed_39_we = addr_hit[243] & reg_we & !reg_error; + + assign alert_class_shadowed_39_wd = reg_wdata[1:0]; + assign alert_class_shadowed_40_re = addr_hit[244] & reg_re & !reg_error; + assign alert_class_shadowed_40_we = addr_hit[244] & reg_we & !reg_error; + + assign alert_class_shadowed_40_wd = reg_wdata[1:0]; + assign alert_class_shadowed_41_re = addr_hit[245] & reg_re & !reg_error; + assign alert_class_shadowed_41_we = addr_hit[245] & reg_we & !reg_error; + + assign alert_class_shadowed_41_wd = reg_wdata[1:0]; + assign alert_class_shadowed_42_re = addr_hit[246] & reg_re & !reg_error; + assign alert_class_shadowed_42_we = addr_hit[246] & reg_we & !reg_error; + + assign alert_class_shadowed_42_wd = reg_wdata[1:0]; + assign alert_class_shadowed_43_re = addr_hit[247] & reg_re & !reg_error; + assign alert_class_shadowed_43_we = addr_hit[247] & reg_we & !reg_error; + + assign alert_class_shadowed_43_wd = reg_wdata[1:0]; + assign alert_class_shadowed_44_re = addr_hit[248] & reg_re & !reg_error; + assign alert_class_shadowed_44_we = addr_hit[248] & reg_we & !reg_error; + + assign alert_class_shadowed_44_wd = reg_wdata[1:0]; + assign alert_class_shadowed_45_re = addr_hit[249] & reg_re & !reg_error; + assign alert_class_shadowed_45_we = addr_hit[249] & reg_we & !reg_error; + + assign alert_class_shadowed_45_wd = reg_wdata[1:0]; + assign alert_class_shadowed_46_re = addr_hit[250] & reg_re & !reg_error; + assign alert_class_shadowed_46_we = addr_hit[250] & reg_we & !reg_error; + + assign alert_class_shadowed_46_wd = reg_wdata[1:0]; + assign alert_class_shadowed_47_re = addr_hit[251] & reg_re & !reg_error; + assign alert_class_shadowed_47_we = addr_hit[251] & reg_we & !reg_error; + + assign alert_class_shadowed_47_wd = reg_wdata[1:0]; + assign alert_class_shadowed_48_re = addr_hit[252] & reg_re & !reg_error; + assign alert_class_shadowed_48_we = addr_hit[252] & reg_we & !reg_error; + + assign alert_class_shadowed_48_wd = reg_wdata[1:0]; + assign alert_class_shadowed_49_re = addr_hit[253] & reg_re & !reg_error; + assign alert_class_shadowed_49_we = addr_hit[253] & reg_we & !reg_error; + + assign alert_class_shadowed_49_wd = reg_wdata[1:0]; + assign alert_class_shadowed_50_re = addr_hit[254] & reg_re & !reg_error; + assign alert_class_shadowed_50_we = addr_hit[254] & reg_we & !reg_error; + + assign alert_class_shadowed_50_wd = reg_wdata[1:0]; + assign alert_class_shadowed_51_re = addr_hit[255] & reg_re & !reg_error; + assign alert_class_shadowed_51_we = addr_hit[255] & reg_we & !reg_error; + + assign alert_class_shadowed_51_wd = reg_wdata[1:0]; + assign alert_class_shadowed_52_re = addr_hit[256] & reg_re & !reg_error; + assign alert_class_shadowed_52_we = addr_hit[256] & reg_we & !reg_error; + + assign alert_class_shadowed_52_wd = reg_wdata[1:0]; + assign alert_class_shadowed_53_re = addr_hit[257] & reg_re & !reg_error; + assign alert_class_shadowed_53_we = addr_hit[257] & reg_we & !reg_error; + + assign alert_class_shadowed_53_wd = reg_wdata[1:0]; + assign alert_class_shadowed_54_re = addr_hit[258] & reg_re & !reg_error; + assign alert_class_shadowed_54_we = addr_hit[258] & reg_we & !reg_error; + + assign alert_class_shadowed_54_wd = reg_wdata[1:0]; + assign alert_class_shadowed_55_re = addr_hit[259] & reg_re & !reg_error; + assign alert_class_shadowed_55_we = addr_hit[259] & reg_we & !reg_error; + + assign alert_class_shadowed_55_wd = reg_wdata[1:0]; + assign alert_class_shadowed_56_re = addr_hit[260] & reg_re & !reg_error; + assign alert_class_shadowed_56_we = addr_hit[260] & reg_we & !reg_error; + + assign alert_class_shadowed_56_wd = reg_wdata[1:0]; + assign alert_class_shadowed_57_re = addr_hit[261] & reg_re & !reg_error; + assign alert_class_shadowed_57_we = addr_hit[261] & reg_we & !reg_error; + + assign alert_class_shadowed_57_wd = reg_wdata[1:0]; + assign alert_class_shadowed_58_re = addr_hit[262] & reg_re & !reg_error; + assign alert_class_shadowed_58_we = addr_hit[262] & reg_we & !reg_error; + + assign alert_class_shadowed_58_wd = reg_wdata[1:0]; + assign alert_class_shadowed_59_re = addr_hit[263] & reg_re & !reg_error; + assign alert_class_shadowed_59_we = addr_hit[263] & reg_we & !reg_error; + + assign alert_class_shadowed_59_wd = reg_wdata[1:0]; + assign alert_class_shadowed_60_re = addr_hit[264] & reg_re & !reg_error; + assign alert_class_shadowed_60_we = addr_hit[264] & reg_we & !reg_error; + + assign alert_class_shadowed_60_wd = reg_wdata[1:0]; + assign alert_class_shadowed_61_re = addr_hit[265] & reg_re & !reg_error; + assign alert_class_shadowed_61_we = addr_hit[265] & reg_we & !reg_error; + + assign alert_class_shadowed_61_wd = reg_wdata[1:0]; + assign alert_class_shadowed_62_re = addr_hit[266] & reg_re & !reg_error; + assign alert_class_shadowed_62_we = addr_hit[266] & reg_we & !reg_error; + + assign alert_class_shadowed_62_wd = reg_wdata[1:0]; + assign alert_class_shadowed_63_re = addr_hit[267] & reg_re & !reg_error; + assign alert_class_shadowed_63_we = addr_hit[267] & reg_we & !reg_error; + + assign alert_class_shadowed_63_wd = reg_wdata[1:0]; + assign alert_class_shadowed_64_re = addr_hit[268] & reg_re & !reg_error; + assign alert_class_shadowed_64_we = addr_hit[268] & reg_we & !reg_error; + + assign alert_class_shadowed_64_wd = reg_wdata[1:0]; + assign alert_class_shadowed_65_re = addr_hit[269] & reg_re & !reg_error; + assign alert_class_shadowed_65_we = addr_hit[269] & reg_we & !reg_error; + + assign alert_class_shadowed_65_wd = reg_wdata[1:0]; + assign alert_class_shadowed_66_re = addr_hit[270] & reg_re & !reg_error; + assign alert_class_shadowed_66_we = addr_hit[270] & reg_we & !reg_error; + + assign alert_class_shadowed_66_wd = reg_wdata[1:0]; + assign alert_class_shadowed_67_re = addr_hit[271] & reg_re & !reg_error; + assign alert_class_shadowed_67_we = addr_hit[271] & reg_we & !reg_error; + + assign alert_class_shadowed_67_wd = reg_wdata[1:0]; + assign alert_class_shadowed_68_re = addr_hit[272] & reg_re & !reg_error; + assign alert_class_shadowed_68_we = addr_hit[272] & reg_we & !reg_error; + + assign alert_class_shadowed_68_wd = reg_wdata[1:0]; + assign alert_class_shadowed_69_re = addr_hit[273] & reg_re & !reg_error; + assign alert_class_shadowed_69_we = addr_hit[273] & reg_we & !reg_error; + + assign alert_class_shadowed_69_wd = reg_wdata[1:0]; + assign alert_class_shadowed_70_re = addr_hit[274] & reg_re & !reg_error; + assign alert_class_shadowed_70_we = addr_hit[274] & reg_we & !reg_error; + + assign alert_class_shadowed_70_wd = reg_wdata[1:0]; + assign alert_class_shadowed_71_re = addr_hit[275] & reg_re & !reg_error; + assign alert_class_shadowed_71_we = addr_hit[275] & reg_we & !reg_error; + + assign alert_class_shadowed_71_wd = reg_wdata[1:0]; + assign alert_class_shadowed_72_re = addr_hit[276] & reg_re & !reg_error; + assign alert_class_shadowed_72_we = addr_hit[276] & reg_we & !reg_error; + + assign alert_class_shadowed_72_wd = reg_wdata[1:0]; + assign alert_class_shadowed_73_re = addr_hit[277] & reg_re & !reg_error; + assign alert_class_shadowed_73_we = addr_hit[277] & reg_we & !reg_error; + + assign alert_class_shadowed_73_wd = reg_wdata[1:0]; + assign alert_class_shadowed_74_re = addr_hit[278] & reg_re & !reg_error; + assign alert_class_shadowed_74_we = addr_hit[278] & reg_we & !reg_error; + + assign alert_class_shadowed_74_wd = reg_wdata[1:0]; + assign alert_class_shadowed_75_re = addr_hit[279] & reg_re & !reg_error; + assign alert_class_shadowed_75_we = addr_hit[279] & reg_we & !reg_error; + + assign alert_class_shadowed_75_wd = reg_wdata[1:0]; + assign alert_class_shadowed_76_re = addr_hit[280] & reg_re & !reg_error; + assign alert_class_shadowed_76_we = addr_hit[280] & reg_we & !reg_error; + + assign alert_class_shadowed_76_wd = reg_wdata[1:0]; + assign alert_class_shadowed_77_re = addr_hit[281] & reg_re & !reg_error; + assign alert_class_shadowed_77_we = addr_hit[281] & reg_we & !reg_error; + + assign alert_class_shadowed_77_wd = reg_wdata[1:0]; + assign alert_class_shadowed_78_re = addr_hit[282] & reg_re & !reg_error; + assign alert_class_shadowed_78_we = addr_hit[282] & reg_we & !reg_error; + + assign alert_class_shadowed_78_wd = reg_wdata[1:0]; + assign alert_class_shadowed_79_re = addr_hit[283] & reg_re & !reg_error; + assign alert_class_shadowed_79_we = addr_hit[283] & reg_we & !reg_error; + + assign alert_class_shadowed_79_wd = reg_wdata[1:0]; + assign alert_class_shadowed_80_re = addr_hit[284] & reg_re & !reg_error; + assign alert_class_shadowed_80_we = addr_hit[284] & reg_we & !reg_error; + + assign alert_class_shadowed_80_wd = reg_wdata[1:0]; + assign alert_class_shadowed_81_re = addr_hit[285] & reg_re & !reg_error; + assign alert_class_shadowed_81_we = addr_hit[285] & reg_we & !reg_error; + + assign alert_class_shadowed_81_wd = reg_wdata[1:0]; + assign alert_class_shadowed_82_re = addr_hit[286] & reg_re & !reg_error; + assign alert_class_shadowed_82_we = addr_hit[286] & reg_we & !reg_error; + + assign alert_class_shadowed_82_wd = reg_wdata[1:0]; + assign alert_class_shadowed_83_re = addr_hit[287] & reg_re & !reg_error; + assign alert_class_shadowed_83_we = addr_hit[287] & reg_we & !reg_error; + + assign alert_class_shadowed_83_wd = reg_wdata[1:0]; + assign alert_class_shadowed_84_re = addr_hit[288] & reg_re & !reg_error; + assign alert_class_shadowed_84_we = addr_hit[288] & reg_we & !reg_error; + + assign alert_class_shadowed_84_wd = reg_wdata[1:0]; + assign alert_class_shadowed_85_re = addr_hit[289] & reg_re & !reg_error; + assign alert_class_shadowed_85_we = addr_hit[289] & reg_we & !reg_error; + + assign alert_class_shadowed_85_wd = reg_wdata[1:0]; + assign alert_class_shadowed_86_re = addr_hit[290] & reg_re & !reg_error; + assign alert_class_shadowed_86_we = addr_hit[290] & reg_we & !reg_error; + + assign alert_class_shadowed_86_wd = reg_wdata[1:0]; + assign alert_class_shadowed_87_re = addr_hit[291] & reg_re & !reg_error; + assign alert_class_shadowed_87_we = addr_hit[291] & reg_we & !reg_error; + + assign alert_class_shadowed_87_wd = reg_wdata[1:0]; + assign alert_class_shadowed_88_re = addr_hit[292] & reg_re & !reg_error; + assign alert_class_shadowed_88_we = addr_hit[292] & reg_we & !reg_error; + + assign alert_class_shadowed_88_wd = reg_wdata[1:0]; + assign alert_class_shadowed_89_re = addr_hit[293] & reg_re & !reg_error; + assign alert_class_shadowed_89_we = addr_hit[293] & reg_we & !reg_error; + + assign alert_class_shadowed_89_wd = reg_wdata[1:0]; + assign alert_class_shadowed_90_re = addr_hit[294] & reg_re & !reg_error; + assign alert_class_shadowed_90_we = addr_hit[294] & reg_we & !reg_error; + + assign alert_class_shadowed_90_wd = reg_wdata[1:0]; + assign alert_class_shadowed_91_re = addr_hit[295] & reg_re & !reg_error; + assign alert_class_shadowed_91_we = addr_hit[295] & reg_we & !reg_error; + + assign alert_class_shadowed_91_wd = reg_wdata[1:0]; + assign alert_class_shadowed_92_re = addr_hit[296] & reg_re & !reg_error; + assign alert_class_shadowed_92_we = addr_hit[296] & reg_we & !reg_error; + + assign alert_class_shadowed_92_wd = reg_wdata[1:0]; + assign alert_class_shadowed_93_re = addr_hit[297] & reg_re & !reg_error; + assign alert_class_shadowed_93_we = addr_hit[297] & reg_we & !reg_error; + + assign alert_class_shadowed_93_wd = reg_wdata[1:0]; + assign alert_class_shadowed_94_re = addr_hit[298] & reg_re & !reg_error; + assign alert_class_shadowed_94_we = addr_hit[298] & reg_we & !reg_error; + + assign alert_class_shadowed_94_wd = reg_wdata[1:0]; + assign alert_class_shadowed_95_re = addr_hit[299] & reg_re & !reg_error; + assign alert_class_shadowed_95_we = addr_hit[299] & reg_we & !reg_error; + + assign alert_class_shadowed_95_wd = reg_wdata[1:0]; + assign alert_class_shadowed_96_re = addr_hit[300] & reg_re & !reg_error; + assign alert_class_shadowed_96_we = addr_hit[300] & reg_we & !reg_error; + + assign alert_class_shadowed_96_wd = reg_wdata[1:0]; + assign alert_class_shadowed_97_re = addr_hit[301] & reg_re & !reg_error; + assign alert_class_shadowed_97_we = addr_hit[301] & reg_we & !reg_error; + + assign alert_class_shadowed_97_wd = reg_wdata[1:0]; + assign alert_class_shadowed_98_re = addr_hit[302] & reg_re & !reg_error; + assign alert_class_shadowed_98_we = addr_hit[302] & reg_we & !reg_error; + + assign alert_class_shadowed_98_wd = reg_wdata[1:0]; + assign alert_cause_0_we = addr_hit[303] & reg_we & !reg_error; + + assign alert_cause_0_wd = reg_wdata[0]; + assign alert_cause_1_we = addr_hit[304] & reg_we & !reg_error; + + assign alert_cause_1_wd = reg_wdata[0]; + assign alert_cause_2_we = addr_hit[305] & reg_we & !reg_error; + + assign alert_cause_2_wd = reg_wdata[0]; + assign alert_cause_3_we = addr_hit[306] & reg_we & !reg_error; + + assign alert_cause_3_wd = reg_wdata[0]; + assign alert_cause_4_we = addr_hit[307] & reg_we & !reg_error; + + assign alert_cause_4_wd = reg_wdata[0]; + assign alert_cause_5_we = addr_hit[308] & reg_we & !reg_error; + + assign alert_cause_5_wd = reg_wdata[0]; + assign alert_cause_6_we = addr_hit[309] & reg_we & !reg_error; + + assign alert_cause_6_wd = reg_wdata[0]; + assign alert_cause_7_we = addr_hit[310] & reg_we & !reg_error; + + assign alert_cause_7_wd = reg_wdata[0]; + assign alert_cause_8_we = addr_hit[311] & reg_we & !reg_error; + + assign alert_cause_8_wd = reg_wdata[0]; + assign alert_cause_9_we = addr_hit[312] & reg_we & !reg_error; + + assign alert_cause_9_wd = reg_wdata[0]; + assign alert_cause_10_we = addr_hit[313] & reg_we & !reg_error; + + assign alert_cause_10_wd = reg_wdata[0]; + assign alert_cause_11_we = addr_hit[314] & reg_we & !reg_error; + + assign alert_cause_11_wd = reg_wdata[0]; + assign alert_cause_12_we = addr_hit[315] & reg_we & !reg_error; + + assign alert_cause_12_wd = reg_wdata[0]; + assign alert_cause_13_we = addr_hit[316] & reg_we & !reg_error; + + assign alert_cause_13_wd = reg_wdata[0]; + assign alert_cause_14_we = addr_hit[317] & reg_we & !reg_error; + + assign alert_cause_14_wd = reg_wdata[0]; + assign alert_cause_15_we = addr_hit[318] & reg_we & !reg_error; + + assign alert_cause_15_wd = reg_wdata[0]; + assign alert_cause_16_we = addr_hit[319] & reg_we & !reg_error; + + assign alert_cause_16_wd = reg_wdata[0]; + assign alert_cause_17_we = addr_hit[320] & reg_we & !reg_error; + + assign alert_cause_17_wd = reg_wdata[0]; + assign alert_cause_18_we = addr_hit[321] & reg_we & !reg_error; + + assign alert_cause_18_wd = reg_wdata[0]; + assign alert_cause_19_we = addr_hit[322] & reg_we & !reg_error; + + assign alert_cause_19_wd = reg_wdata[0]; + assign alert_cause_20_we = addr_hit[323] & reg_we & !reg_error; + + assign alert_cause_20_wd = reg_wdata[0]; + assign alert_cause_21_we = addr_hit[324] & reg_we & !reg_error; + + assign alert_cause_21_wd = reg_wdata[0]; + assign alert_cause_22_we = addr_hit[325] & reg_we & !reg_error; + + assign alert_cause_22_wd = reg_wdata[0]; + assign alert_cause_23_we = addr_hit[326] & reg_we & !reg_error; + + assign alert_cause_23_wd = reg_wdata[0]; + assign alert_cause_24_we = addr_hit[327] & reg_we & !reg_error; + + assign alert_cause_24_wd = reg_wdata[0]; + assign alert_cause_25_we = addr_hit[328] & reg_we & !reg_error; + + assign alert_cause_25_wd = reg_wdata[0]; + assign alert_cause_26_we = addr_hit[329] & reg_we & !reg_error; + + assign alert_cause_26_wd = reg_wdata[0]; + assign alert_cause_27_we = addr_hit[330] & reg_we & !reg_error; + + assign alert_cause_27_wd = reg_wdata[0]; + assign alert_cause_28_we = addr_hit[331] & reg_we & !reg_error; + + assign alert_cause_28_wd = reg_wdata[0]; + assign alert_cause_29_we = addr_hit[332] & reg_we & !reg_error; + + assign alert_cause_29_wd = reg_wdata[0]; + assign alert_cause_30_we = addr_hit[333] & reg_we & !reg_error; + + assign alert_cause_30_wd = reg_wdata[0]; + assign alert_cause_31_we = addr_hit[334] & reg_we & !reg_error; + + assign alert_cause_31_wd = reg_wdata[0]; + assign alert_cause_32_we = addr_hit[335] & reg_we & !reg_error; + + assign alert_cause_32_wd = reg_wdata[0]; + assign alert_cause_33_we = addr_hit[336] & reg_we & !reg_error; + + assign alert_cause_33_wd = reg_wdata[0]; + assign alert_cause_34_we = addr_hit[337] & reg_we & !reg_error; + + assign alert_cause_34_wd = reg_wdata[0]; + assign alert_cause_35_we = addr_hit[338] & reg_we & !reg_error; + + assign alert_cause_35_wd = reg_wdata[0]; + assign alert_cause_36_we = addr_hit[339] & reg_we & !reg_error; + + assign alert_cause_36_wd = reg_wdata[0]; + assign alert_cause_37_we = addr_hit[340] & reg_we & !reg_error; + + assign alert_cause_37_wd = reg_wdata[0]; + assign alert_cause_38_we = addr_hit[341] & reg_we & !reg_error; + + assign alert_cause_38_wd = reg_wdata[0]; + assign alert_cause_39_we = addr_hit[342] & reg_we & !reg_error; + + assign alert_cause_39_wd = reg_wdata[0]; + assign alert_cause_40_we = addr_hit[343] & reg_we & !reg_error; + + assign alert_cause_40_wd = reg_wdata[0]; + assign alert_cause_41_we = addr_hit[344] & reg_we & !reg_error; + + assign alert_cause_41_wd = reg_wdata[0]; + assign alert_cause_42_we = addr_hit[345] & reg_we & !reg_error; + + assign alert_cause_42_wd = reg_wdata[0]; + assign alert_cause_43_we = addr_hit[346] & reg_we & !reg_error; + + assign alert_cause_43_wd = reg_wdata[0]; + assign alert_cause_44_we = addr_hit[347] & reg_we & !reg_error; + + assign alert_cause_44_wd = reg_wdata[0]; + assign alert_cause_45_we = addr_hit[348] & reg_we & !reg_error; + + assign alert_cause_45_wd = reg_wdata[0]; + assign alert_cause_46_we = addr_hit[349] & reg_we & !reg_error; + + assign alert_cause_46_wd = reg_wdata[0]; + assign alert_cause_47_we = addr_hit[350] & reg_we & !reg_error; + + assign alert_cause_47_wd = reg_wdata[0]; + assign alert_cause_48_we = addr_hit[351] & reg_we & !reg_error; + + assign alert_cause_48_wd = reg_wdata[0]; + assign alert_cause_49_we = addr_hit[352] & reg_we & !reg_error; + + assign alert_cause_49_wd = reg_wdata[0]; + assign alert_cause_50_we = addr_hit[353] & reg_we & !reg_error; + + assign alert_cause_50_wd = reg_wdata[0]; + assign alert_cause_51_we = addr_hit[354] & reg_we & !reg_error; + + assign alert_cause_51_wd = reg_wdata[0]; + assign alert_cause_52_we = addr_hit[355] & reg_we & !reg_error; + + assign alert_cause_52_wd = reg_wdata[0]; + assign alert_cause_53_we = addr_hit[356] & reg_we & !reg_error; + + assign alert_cause_53_wd = reg_wdata[0]; + assign alert_cause_54_we = addr_hit[357] & reg_we & !reg_error; + + assign alert_cause_54_wd = reg_wdata[0]; + assign alert_cause_55_we = addr_hit[358] & reg_we & !reg_error; + + assign alert_cause_55_wd = reg_wdata[0]; + assign alert_cause_56_we = addr_hit[359] & reg_we & !reg_error; + + assign alert_cause_56_wd = reg_wdata[0]; + assign alert_cause_57_we = addr_hit[360] & reg_we & !reg_error; + + assign alert_cause_57_wd = reg_wdata[0]; + assign alert_cause_58_we = addr_hit[361] & reg_we & !reg_error; + + assign alert_cause_58_wd = reg_wdata[0]; + assign alert_cause_59_we = addr_hit[362] & reg_we & !reg_error; + + assign alert_cause_59_wd = reg_wdata[0]; + assign alert_cause_60_we = addr_hit[363] & reg_we & !reg_error; + + assign alert_cause_60_wd = reg_wdata[0]; + assign alert_cause_61_we = addr_hit[364] & reg_we & !reg_error; + + assign alert_cause_61_wd = reg_wdata[0]; + assign alert_cause_62_we = addr_hit[365] & reg_we & !reg_error; + + assign alert_cause_62_wd = reg_wdata[0]; + assign alert_cause_63_we = addr_hit[366] & reg_we & !reg_error; + + assign alert_cause_63_wd = reg_wdata[0]; + assign alert_cause_64_we = addr_hit[367] & reg_we & !reg_error; + + assign alert_cause_64_wd = reg_wdata[0]; + assign alert_cause_65_we = addr_hit[368] & reg_we & !reg_error; + + assign alert_cause_65_wd = reg_wdata[0]; + assign alert_cause_66_we = addr_hit[369] & reg_we & !reg_error; + + assign alert_cause_66_wd = reg_wdata[0]; + assign alert_cause_67_we = addr_hit[370] & reg_we & !reg_error; + + assign alert_cause_67_wd = reg_wdata[0]; + assign alert_cause_68_we = addr_hit[371] & reg_we & !reg_error; + + assign alert_cause_68_wd = reg_wdata[0]; + assign alert_cause_69_we = addr_hit[372] & reg_we & !reg_error; + + assign alert_cause_69_wd = reg_wdata[0]; + assign alert_cause_70_we = addr_hit[373] & reg_we & !reg_error; + + assign alert_cause_70_wd = reg_wdata[0]; + assign alert_cause_71_we = addr_hit[374] & reg_we & !reg_error; + + assign alert_cause_71_wd = reg_wdata[0]; + assign alert_cause_72_we = addr_hit[375] & reg_we & !reg_error; + + assign alert_cause_72_wd = reg_wdata[0]; + assign alert_cause_73_we = addr_hit[376] & reg_we & !reg_error; + + assign alert_cause_73_wd = reg_wdata[0]; + assign alert_cause_74_we = addr_hit[377] & reg_we & !reg_error; + + assign alert_cause_74_wd = reg_wdata[0]; + assign alert_cause_75_we = addr_hit[378] & reg_we & !reg_error; + + assign alert_cause_75_wd = reg_wdata[0]; + assign alert_cause_76_we = addr_hit[379] & reg_we & !reg_error; + + assign alert_cause_76_wd = reg_wdata[0]; + assign alert_cause_77_we = addr_hit[380] & reg_we & !reg_error; + + assign alert_cause_77_wd = reg_wdata[0]; + assign alert_cause_78_we = addr_hit[381] & reg_we & !reg_error; + + assign alert_cause_78_wd = reg_wdata[0]; + assign alert_cause_79_we = addr_hit[382] & reg_we & !reg_error; + + assign alert_cause_79_wd = reg_wdata[0]; + assign alert_cause_80_we = addr_hit[383] & reg_we & !reg_error; + + assign alert_cause_80_wd = reg_wdata[0]; + assign alert_cause_81_we = addr_hit[384] & reg_we & !reg_error; + + assign alert_cause_81_wd = reg_wdata[0]; + assign alert_cause_82_we = addr_hit[385] & reg_we & !reg_error; + + assign alert_cause_82_wd = reg_wdata[0]; + assign alert_cause_83_we = addr_hit[386] & reg_we & !reg_error; + + assign alert_cause_83_wd = reg_wdata[0]; + assign alert_cause_84_we = addr_hit[387] & reg_we & !reg_error; + + assign alert_cause_84_wd = reg_wdata[0]; + assign alert_cause_85_we = addr_hit[388] & reg_we & !reg_error; + + assign alert_cause_85_wd = reg_wdata[0]; + assign alert_cause_86_we = addr_hit[389] & reg_we & !reg_error; + + assign alert_cause_86_wd = reg_wdata[0]; + assign alert_cause_87_we = addr_hit[390] & reg_we & !reg_error; + + assign alert_cause_87_wd = reg_wdata[0]; + assign alert_cause_88_we = addr_hit[391] & reg_we & !reg_error; + + assign alert_cause_88_wd = reg_wdata[0]; + assign alert_cause_89_we = addr_hit[392] & reg_we & !reg_error; + + assign alert_cause_89_wd = reg_wdata[0]; + assign alert_cause_90_we = addr_hit[393] & reg_we & !reg_error; + + assign alert_cause_90_wd = reg_wdata[0]; + assign alert_cause_91_we = addr_hit[394] & reg_we & !reg_error; + + assign alert_cause_91_wd = reg_wdata[0]; + assign alert_cause_92_we = addr_hit[395] & reg_we & !reg_error; + + assign alert_cause_92_wd = reg_wdata[0]; + assign alert_cause_93_we = addr_hit[396] & reg_we & !reg_error; + + assign alert_cause_93_wd = reg_wdata[0]; + assign alert_cause_94_we = addr_hit[397] & reg_we & !reg_error; + + assign alert_cause_94_wd = reg_wdata[0]; + assign alert_cause_95_we = addr_hit[398] & reg_we & !reg_error; + + assign alert_cause_95_wd = reg_wdata[0]; + assign alert_cause_96_we = addr_hit[399] & reg_we & !reg_error; + + assign alert_cause_96_wd = reg_wdata[0]; + assign alert_cause_97_we = addr_hit[400] & reg_we & !reg_error; + + assign alert_cause_97_wd = reg_wdata[0]; + assign alert_cause_98_we = addr_hit[401] & reg_we & !reg_error; + + assign alert_cause_98_wd = reg_wdata[0]; + assign loc_alert_regwen_0_we = addr_hit[402] & reg_we & !reg_error; + + assign loc_alert_regwen_0_wd = reg_wdata[0]; + assign loc_alert_regwen_1_we = addr_hit[403] & reg_we & !reg_error; + + assign loc_alert_regwen_1_wd = reg_wdata[0]; + assign loc_alert_regwen_2_we = addr_hit[404] & reg_we & !reg_error; + + assign loc_alert_regwen_2_wd = reg_wdata[0]; + assign loc_alert_regwen_3_we = addr_hit[405] & reg_we & !reg_error; + + assign loc_alert_regwen_3_wd = reg_wdata[0]; + assign loc_alert_regwen_4_we = addr_hit[406] & reg_we & !reg_error; + + assign loc_alert_regwen_4_wd = reg_wdata[0]; + assign loc_alert_regwen_5_we = addr_hit[407] & reg_we & !reg_error; + + assign loc_alert_regwen_5_wd = reg_wdata[0]; + assign loc_alert_regwen_6_we = addr_hit[408] & reg_we & !reg_error; + + assign loc_alert_regwen_6_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_0_re = addr_hit[409] & reg_re & !reg_error; + assign loc_alert_en_shadowed_0_we = addr_hit[409] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_0_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_1_re = addr_hit[410] & reg_re & !reg_error; + assign loc_alert_en_shadowed_1_we = addr_hit[410] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_1_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_2_re = addr_hit[411] & reg_re & !reg_error; + assign loc_alert_en_shadowed_2_we = addr_hit[411] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_2_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_3_re = addr_hit[412] & reg_re & !reg_error; + assign loc_alert_en_shadowed_3_we = addr_hit[412] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_3_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_4_re = addr_hit[413] & reg_re & !reg_error; + assign loc_alert_en_shadowed_4_we = addr_hit[413] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_4_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_5_re = addr_hit[414] & reg_re & !reg_error; + assign loc_alert_en_shadowed_5_we = addr_hit[414] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_5_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_6_re = addr_hit[415] & reg_re & !reg_error; + assign loc_alert_en_shadowed_6_we = addr_hit[415] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_6_wd = reg_wdata[0]; + assign loc_alert_class_shadowed_0_re = addr_hit[416] & reg_re & !reg_error; + assign loc_alert_class_shadowed_0_we = addr_hit[416] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_0_wd = reg_wdata[1:0]; + assign loc_alert_class_shadowed_1_re = addr_hit[417] & reg_re & !reg_error; + assign loc_alert_class_shadowed_1_we = addr_hit[417] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_1_wd = reg_wdata[1:0]; + assign loc_alert_class_shadowed_2_re = addr_hit[418] & reg_re & !reg_error; + assign loc_alert_class_shadowed_2_we = addr_hit[418] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_2_wd = reg_wdata[1:0]; + assign loc_alert_class_shadowed_3_re = addr_hit[419] & reg_re & !reg_error; + assign loc_alert_class_shadowed_3_we = addr_hit[419] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_3_wd = reg_wdata[1:0]; + assign loc_alert_class_shadowed_4_re = addr_hit[420] & reg_re & !reg_error; + assign loc_alert_class_shadowed_4_we = addr_hit[420] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_4_wd = reg_wdata[1:0]; + assign loc_alert_class_shadowed_5_re = addr_hit[421] & reg_re & !reg_error; + assign loc_alert_class_shadowed_5_we = addr_hit[421] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_5_wd = reg_wdata[1:0]; + assign loc_alert_class_shadowed_6_re = addr_hit[422] & reg_re & !reg_error; + assign loc_alert_class_shadowed_6_we = addr_hit[422] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_6_wd = reg_wdata[1:0]; + assign loc_alert_cause_0_we = addr_hit[423] & reg_we & !reg_error; + + assign loc_alert_cause_0_wd = reg_wdata[0]; + assign loc_alert_cause_1_we = addr_hit[424] & reg_we & !reg_error; + + assign loc_alert_cause_1_wd = reg_wdata[0]; + assign loc_alert_cause_2_we = addr_hit[425] & reg_we & !reg_error; + + assign loc_alert_cause_2_wd = reg_wdata[0]; + assign loc_alert_cause_3_we = addr_hit[426] & reg_we & !reg_error; + + assign loc_alert_cause_3_wd = reg_wdata[0]; + assign loc_alert_cause_4_we = addr_hit[427] & reg_we & !reg_error; + + assign loc_alert_cause_4_wd = reg_wdata[0]; + assign loc_alert_cause_5_we = addr_hit[428] & reg_we & !reg_error; + + assign loc_alert_cause_5_wd = reg_wdata[0]; + assign loc_alert_cause_6_we = addr_hit[429] & reg_we & !reg_error; + + assign loc_alert_cause_6_wd = reg_wdata[0]; + assign classa_regwen_we = addr_hit[430] & reg_we & !reg_error; + + assign classa_regwen_wd = reg_wdata[0]; + assign classa_ctrl_shadowed_re = addr_hit[431] & reg_re & !reg_error; + assign classa_ctrl_shadowed_we = addr_hit[431] & reg_we & !reg_error; + + assign classa_ctrl_shadowed_en_wd = reg_wdata[0]; + + assign classa_ctrl_shadowed_lock_wd = reg_wdata[1]; + + assign classa_ctrl_shadowed_en_e0_wd = reg_wdata[2]; + + assign classa_ctrl_shadowed_en_e1_wd = reg_wdata[3]; + + assign classa_ctrl_shadowed_en_e2_wd = reg_wdata[4]; + + assign classa_ctrl_shadowed_en_e3_wd = reg_wdata[5]; + + assign classa_ctrl_shadowed_map_e0_wd = reg_wdata[7:6]; + + assign classa_ctrl_shadowed_map_e1_wd = reg_wdata[9:8]; + + assign classa_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; + + assign classa_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; + assign classa_clr_regwen_we = addr_hit[432] & reg_we & !reg_error; + + assign classa_clr_regwen_wd = reg_wdata[0]; + assign classa_clr_shadowed_re = addr_hit[433] & reg_re & !reg_error; + assign classa_clr_shadowed_we = addr_hit[433] & reg_we & !reg_error; + + assign classa_clr_shadowed_wd = reg_wdata[0]; + assign classa_accum_cnt_re = addr_hit[434] & reg_re & !reg_error; + assign classa_accum_thresh_shadowed_re = addr_hit[435] & reg_re & !reg_error; + assign classa_accum_thresh_shadowed_we = addr_hit[435] & reg_we & !reg_error; + + assign classa_accum_thresh_shadowed_wd = reg_wdata[15:0]; + assign classa_timeout_cyc_shadowed_re = addr_hit[436] & reg_re & !reg_error; + assign classa_timeout_cyc_shadowed_we = addr_hit[436] & reg_we & !reg_error; + + assign classa_timeout_cyc_shadowed_wd = reg_wdata[31:0]; + assign classa_crashdump_trigger_shadowed_re = addr_hit[437] & reg_re & !reg_error; + assign classa_crashdump_trigger_shadowed_we = addr_hit[437] & reg_we & !reg_error; + + assign classa_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; + assign classa_phase0_cyc_shadowed_re = addr_hit[438] & reg_re & !reg_error; + assign classa_phase0_cyc_shadowed_we = addr_hit[438] & reg_we & !reg_error; + + assign classa_phase0_cyc_shadowed_wd = reg_wdata[31:0]; + assign classa_phase1_cyc_shadowed_re = addr_hit[439] & reg_re & !reg_error; + assign classa_phase1_cyc_shadowed_we = addr_hit[439] & reg_we & !reg_error; + + assign classa_phase1_cyc_shadowed_wd = reg_wdata[31:0]; + assign classa_phase2_cyc_shadowed_re = addr_hit[440] & reg_re & !reg_error; + assign classa_phase2_cyc_shadowed_we = addr_hit[440] & reg_we & !reg_error; + + assign classa_phase2_cyc_shadowed_wd = reg_wdata[31:0]; + assign classa_phase3_cyc_shadowed_re = addr_hit[441] & reg_re & !reg_error; + assign classa_phase3_cyc_shadowed_we = addr_hit[441] & reg_we & !reg_error; + + assign classa_phase3_cyc_shadowed_wd = reg_wdata[31:0]; + assign classa_esc_cnt_re = addr_hit[442] & reg_re & !reg_error; + assign classa_state_re = addr_hit[443] & reg_re & !reg_error; + assign classb_regwen_we = addr_hit[444] & reg_we & !reg_error; + + assign classb_regwen_wd = reg_wdata[0]; + assign classb_ctrl_shadowed_re = addr_hit[445] & reg_re & !reg_error; + assign classb_ctrl_shadowed_we = addr_hit[445] & reg_we & !reg_error; + + assign classb_ctrl_shadowed_en_wd = reg_wdata[0]; + + assign classb_ctrl_shadowed_lock_wd = reg_wdata[1]; + + assign classb_ctrl_shadowed_en_e0_wd = reg_wdata[2]; + + assign classb_ctrl_shadowed_en_e1_wd = reg_wdata[3]; + + assign classb_ctrl_shadowed_en_e2_wd = reg_wdata[4]; + + assign classb_ctrl_shadowed_en_e3_wd = reg_wdata[5]; + + assign classb_ctrl_shadowed_map_e0_wd = reg_wdata[7:6]; + + assign classb_ctrl_shadowed_map_e1_wd = reg_wdata[9:8]; + + assign classb_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; + + assign classb_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; + assign classb_clr_regwen_we = addr_hit[446] & reg_we & !reg_error; + + assign classb_clr_regwen_wd = reg_wdata[0]; + assign classb_clr_shadowed_re = addr_hit[447] & reg_re & !reg_error; + assign classb_clr_shadowed_we = addr_hit[447] & reg_we & !reg_error; + + assign classb_clr_shadowed_wd = reg_wdata[0]; + assign classb_accum_cnt_re = addr_hit[448] & reg_re & !reg_error; + assign classb_accum_thresh_shadowed_re = addr_hit[449] & reg_re & !reg_error; + assign classb_accum_thresh_shadowed_we = addr_hit[449] & reg_we & !reg_error; + + assign classb_accum_thresh_shadowed_wd = reg_wdata[15:0]; + assign classb_timeout_cyc_shadowed_re = addr_hit[450] & reg_re & !reg_error; + assign classb_timeout_cyc_shadowed_we = addr_hit[450] & reg_we & !reg_error; + + assign classb_timeout_cyc_shadowed_wd = reg_wdata[31:0]; + assign classb_crashdump_trigger_shadowed_re = addr_hit[451] & reg_re & !reg_error; + assign classb_crashdump_trigger_shadowed_we = addr_hit[451] & reg_we & !reg_error; + + assign classb_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; + assign classb_phase0_cyc_shadowed_re = addr_hit[452] & reg_re & !reg_error; + assign classb_phase0_cyc_shadowed_we = addr_hit[452] & reg_we & !reg_error; + + assign classb_phase0_cyc_shadowed_wd = reg_wdata[31:0]; + assign classb_phase1_cyc_shadowed_re = addr_hit[453] & reg_re & !reg_error; + assign classb_phase1_cyc_shadowed_we = addr_hit[453] & reg_we & !reg_error; + + assign classb_phase1_cyc_shadowed_wd = reg_wdata[31:0]; + assign classb_phase2_cyc_shadowed_re = addr_hit[454] & reg_re & !reg_error; + assign classb_phase2_cyc_shadowed_we = addr_hit[454] & reg_we & !reg_error; + + assign classb_phase2_cyc_shadowed_wd = reg_wdata[31:0]; + assign classb_phase3_cyc_shadowed_re = addr_hit[455] & reg_re & !reg_error; + assign classb_phase3_cyc_shadowed_we = addr_hit[455] & reg_we & !reg_error; + + assign classb_phase3_cyc_shadowed_wd = reg_wdata[31:0]; + assign classb_esc_cnt_re = addr_hit[456] & reg_re & !reg_error; + assign classb_state_re = addr_hit[457] & reg_re & !reg_error; + assign classc_regwen_we = addr_hit[458] & reg_we & !reg_error; + + assign classc_regwen_wd = reg_wdata[0]; + assign classc_ctrl_shadowed_re = addr_hit[459] & reg_re & !reg_error; + assign classc_ctrl_shadowed_we = addr_hit[459] & reg_we & !reg_error; + + assign classc_ctrl_shadowed_en_wd = reg_wdata[0]; + + assign classc_ctrl_shadowed_lock_wd = reg_wdata[1]; + + assign classc_ctrl_shadowed_en_e0_wd = reg_wdata[2]; + + assign classc_ctrl_shadowed_en_e1_wd = reg_wdata[3]; + + assign classc_ctrl_shadowed_en_e2_wd = reg_wdata[4]; + + assign classc_ctrl_shadowed_en_e3_wd = reg_wdata[5]; + + assign classc_ctrl_shadowed_map_e0_wd = reg_wdata[7:6]; + + assign classc_ctrl_shadowed_map_e1_wd = reg_wdata[9:8]; + + assign classc_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; + + assign classc_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; + assign classc_clr_regwen_we = addr_hit[460] & reg_we & !reg_error; + + assign classc_clr_regwen_wd = reg_wdata[0]; + assign classc_clr_shadowed_re = addr_hit[461] & reg_re & !reg_error; + assign classc_clr_shadowed_we = addr_hit[461] & reg_we & !reg_error; + + assign classc_clr_shadowed_wd = reg_wdata[0]; + assign classc_accum_cnt_re = addr_hit[462] & reg_re & !reg_error; + assign classc_accum_thresh_shadowed_re = addr_hit[463] & reg_re & !reg_error; + assign classc_accum_thresh_shadowed_we = addr_hit[463] & reg_we & !reg_error; + + assign classc_accum_thresh_shadowed_wd = reg_wdata[15:0]; + assign classc_timeout_cyc_shadowed_re = addr_hit[464] & reg_re & !reg_error; + assign classc_timeout_cyc_shadowed_we = addr_hit[464] & reg_we & !reg_error; + + assign classc_timeout_cyc_shadowed_wd = reg_wdata[31:0]; + assign classc_crashdump_trigger_shadowed_re = addr_hit[465] & reg_re & !reg_error; + assign classc_crashdump_trigger_shadowed_we = addr_hit[465] & reg_we & !reg_error; + + assign classc_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; + assign classc_phase0_cyc_shadowed_re = addr_hit[466] & reg_re & !reg_error; + assign classc_phase0_cyc_shadowed_we = addr_hit[466] & reg_we & !reg_error; + + assign classc_phase0_cyc_shadowed_wd = reg_wdata[31:0]; + assign classc_phase1_cyc_shadowed_re = addr_hit[467] & reg_re & !reg_error; + assign classc_phase1_cyc_shadowed_we = addr_hit[467] & reg_we & !reg_error; + + assign classc_phase1_cyc_shadowed_wd = reg_wdata[31:0]; + assign classc_phase2_cyc_shadowed_re = addr_hit[468] & reg_re & !reg_error; + assign classc_phase2_cyc_shadowed_we = addr_hit[468] & reg_we & !reg_error; + + assign classc_phase2_cyc_shadowed_wd = reg_wdata[31:0]; + assign classc_phase3_cyc_shadowed_re = addr_hit[469] & reg_re & !reg_error; + assign classc_phase3_cyc_shadowed_we = addr_hit[469] & reg_we & !reg_error; + + assign classc_phase3_cyc_shadowed_wd = reg_wdata[31:0]; + assign classc_esc_cnt_re = addr_hit[470] & reg_re & !reg_error; + assign classc_state_re = addr_hit[471] & reg_re & !reg_error; + assign classd_regwen_we = addr_hit[472] & reg_we & !reg_error; + + assign classd_regwen_wd = reg_wdata[0]; + assign classd_ctrl_shadowed_re = addr_hit[473] & reg_re & !reg_error; + assign classd_ctrl_shadowed_we = addr_hit[473] & reg_we & !reg_error; + + assign classd_ctrl_shadowed_en_wd = reg_wdata[0]; + + assign classd_ctrl_shadowed_lock_wd = reg_wdata[1]; + + assign classd_ctrl_shadowed_en_e0_wd = reg_wdata[2]; + + assign classd_ctrl_shadowed_en_e1_wd = reg_wdata[3]; + + assign classd_ctrl_shadowed_en_e2_wd = reg_wdata[4]; + + assign classd_ctrl_shadowed_en_e3_wd = reg_wdata[5]; + + assign classd_ctrl_shadowed_map_e0_wd = reg_wdata[7:6]; + + assign classd_ctrl_shadowed_map_e1_wd = reg_wdata[9:8]; + + assign classd_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; + + assign classd_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; + assign classd_clr_regwen_we = addr_hit[474] & reg_we & !reg_error; + + assign classd_clr_regwen_wd = reg_wdata[0]; + assign classd_clr_shadowed_re = addr_hit[475] & reg_re & !reg_error; + assign classd_clr_shadowed_we = addr_hit[475] & reg_we & !reg_error; + + assign classd_clr_shadowed_wd = reg_wdata[0]; + assign classd_accum_cnt_re = addr_hit[476] & reg_re & !reg_error; + assign classd_accum_thresh_shadowed_re = addr_hit[477] & reg_re & !reg_error; + assign classd_accum_thresh_shadowed_we = addr_hit[477] & reg_we & !reg_error; + + assign classd_accum_thresh_shadowed_wd = reg_wdata[15:0]; + assign classd_timeout_cyc_shadowed_re = addr_hit[478] & reg_re & !reg_error; + assign classd_timeout_cyc_shadowed_we = addr_hit[478] & reg_we & !reg_error; + + assign classd_timeout_cyc_shadowed_wd = reg_wdata[31:0]; + assign classd_crashdump_trigger_shadowed_re = addr_hit[479] & reg_re & !reg_error; + assign classd_crashdump_trigger_shadowed_we = addr_hit[479] & reg_we & !reg_error; + + assign classd_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; + assign classd_phase0_cyc_shadowed_re = addr_hit[480] & reg_re & !reg_error; + assign classd_phase0_cyc_shadowed_we = addr_hit[480] & reg_we & !reg_error; + + assign classd_phase0_cyc_shadowed_wd = reg_wdata[31:0]; + assign classd_phase1_cyc_shadowed_re = addr_hit[481] & reg_re & !reg_error; + assign classd_phase1_cyc_shadowed_we = addr_hit[481] & reg_we & !reg_error; + + assign classd_phase1_cyc_shadowed_wd = reg_wdata[31:0]; + assign classd_phase2_cyc_shadowed_re = addr_hit[482] & reg_re & !reg_error; + assign classd_phase2_cyc_shadowed_we = addr_hit[482] & reg_we & !reg_error; + + assign classd_phase2_cyc_shadowed_wd = reg_wdata[31:0]; + assign classd_phase3_cyc_shadowed_re = addr_hit[483] & reg_re & !reg_error; + assign classd_phase3_cyc_shadowed_we = addr_hit[483] & reg_we & !reg_error; + + assign classd_phase3_cyc_shadowed_wd = reg_wdata[31:0]; + assign classd_esc_cnt_re = addr_hit[484] & reg_re & !reg_error; + assign classd_state_re = addr_hit[485] & reg_re & !reg_error; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check = '0; + reg_we_check[0] = intr_state_we; + reg_we_check[1] = intr_enable_we; + reg_we_check[2] = intr_test_we; + reg_we_check[3] = ping_timer_regwen_we; + reg_we_check[4] = ping_timeout_cyc_shadowed_gated_we; + reg_we_check[5] = ping_timer_en_shadowed_gated_we; + reg_we_check[6] = alert_regwen_0_we; + reg_we_check[7] = alert_regwen_1_we; + reg_we_check[8] = alert_regwen_2_we; + reg_we_check[9] = alert_regwen_3_we; + reg_we_check[10] = alert_regwen_4_we; + reg_we_check[11] = alert_regwen_5_we; + reg_we_check[12] = alert_regwen_6_we; + reg_we_check[13] = alert_regwen_7_we; + reg_we_check[14] = alert_regwen_8_we; + reg_we_check[15] = alert_regwen_9_we; + reg_we_check[16] = alert_regwen_10_we; + reg_we_check[17] = alert_regwen_11_we; + reg_we_check[18] = alert_regwen_12_we; + reg_we_check[19] = alert_regwen_13_we; + reg_we_check[20] = alert_regwen_14_we; + reg_we_check[21] = alert_regwen_15_we; + reg_we_check[22] = alert_regwen_16_we; + reg_we_check[23] = alert_regwen_17_we; + reg_we_check[24] = alert_regwen_18_we; + reg_we_check[25] = alert_regwen_19_we; + reg_we_check[26] = alert_regwen_20_we; + reg_we_check[27] = alert_regwen_21_we; + reg_we_check[28] = alert_regwen_22_we; + reg_we_check[29] = alert_regwen_23_we; + reg_we_check[30] = alert_regwen_24_we; + reg_we_check[31] = alert_regwen_25_we; + reg_we_check[32] = alert_regwen_26_we; + reg_we_check[33] = alert_regwen_27_we; + reg_we_check[34] = alert_regwen_28_we; + reg_we_check[35] = alert_regwen_29_we; + reg_we_check[36] = alert_regwen_30_we; + reg_we_check[37] = alert_regwen_31_we; + reg_we_check[38] = alert_regwen_32_we; + reg_we_check[39] = alert_regwen_33_we; + reg_we_check[40] = alert_regwen_34_we; + reg_we_check[41] = alert_regwen_35_we; + reg_we_check[42] = alert_regwen_36_we; + reg_we_check[43] = alert_regwen_37_we; + reg_we_check[44] = alert_regwen_38_we; + reg_we_check[45] = alert_regwen_39_we; + reg_we_check[46] = alert_regwen_40_we; + reg_we_check[47] = alert_regwen_41_we; + reg_we_check[48] = alert_regwen_42_we; + reg_we_check[49] = alert_regwen_43_we; + reg_we_check[50] = alert_regwen_44_we; + reg_we_check[51] = alert_regwen_45_we; + reg_we_check[52] = alert_regwen_46_we; + reg_we_check[53] = alert_regwen_47_we; + reg_we_check[54] = alert_regwen_48_we; + reg_we_check[55] = alert_regwen_49_we; + reg_we_check[56] = alert_regwen_50_we; + reg_we_check[57] = alert_regwen_51_we; + reg_we_check[58] = alert_regwen_52_we; + reg_we_check[59] = alert_regwen_53_we; + reg_we_check[60] = alert_regwen_54_we; + reg_we_check[61] = alert_regwen_55_we; + reg_we_check[62] = alert_regwen_56_we; + reg_we_check[63] = alert_regwen_57_we; + reg_we_check[64] = alert_regwen_58_we; + reg_we_check[65] = alert_regwen_59_we; + reg_we_check[66] = alert_regwen_60_we; + reg_we_check[67] = alert_regwen_61_we; + reg_we_check[68] = alert_regwen_62_we; + reg_we_check[69] = alert_regwen_63_we; + reg_we_check[70] = alert_regwen_64_we; + reg_we_check[71] = alert_regwen_65_we; + reg_we_check[72] = alert_regwen_66_we; + reg_we_check[73] = alert_regwen_67_we; + reg_we_check[74] = alert_regwen_68_we; + reg_we_check[75] = alert_regwen_69_we; + reg_we_check[76] = alert_regwen_70_we; + reg_we_check[77] = alert_regwen_71_we; + reg_we_check[78] = alert_regwen_72_we; + reg_we_check[79] = alert_regwen_73_we; + reg_we_check[80] = alert_regwen_74_we; + reg_we_check[81] = alert_regwen_75_we; + reg_we_check[82] = alert_regwen_76_we; + reg_we_check[83] = alert_regwen_77_we; + reg_we_check[84] = alert_regwen_78_we; + reg_we_check[85] = alert_regwen_79_we; + reg_we_check[86] = alert_regwen_80_we; + reg_we_check[87] = alert_regwen_81_we; + reg_we_check[88] = alert_regwen_82_we; + reg_we_check[89] = alert_regwen_83_we; + reg_we_check[90] = alert_regwen_84_we; + reg_we_check[91] = alert_regwen_85_we; + reg_we_check[92] = alert_regwen_86_we; + reg_we_check[93] = alert_regwen_87_we; + reg_we_check[94] = alert_regwen_88_we; + reg_we_check[95] = alert_regwen_89_we; + reg_we_check[96] = alert_regwen_90_we; + reg_we_check[97] = alert_regwen_91_we; + reg_we_check[98] = alert_regwen_92_we; + reg_we_check[99] = alert_regwen_93_we; + reg_we_check[100] = alert_regwen_94_we; + reg_we_check[101] = alert_regwen_95_we; + reg_we_check[102] = alert_regwen_96_we; + reg_we_check[103] = alert_regwen_97_we; + reg_we_check[104] = alert_regwen_98_we; + reg_we_check[105] = alert_en_shadowed_0_gated_we; + reg_we_check[106] = alert_en_shadowed_1_gated_we; + reg_we_check[107] = alert_en_shadowed_2_gated_we; + reg_we_check[108] = alert_en_shadowed_3_gated_we; + reg_we_check[109] = alert_en_shadowed_4_gated_we; + reg_we_check[110] = alert_en_shadowed_5_gated_we; + reg_we_check[111] = alert_en_shadowed_6_gated_we; + reg_we_check[112] = alert_en_shadowed_7_gated_we; + reg_we_check[113] = alert_en_shadowed_8_gated_we; + reg_we_check[114] = alert_en_shadowed_9_gated_we; + reg_we_check[115] = alert_en_shadowed_10_gated_we; + reg_we_check[116] = alert_en_shadowed_11_gated_we; + reg_we_check[117] = alert_en_shadowed_12_gated_we; + reg_we_check[118] = alert_en_shadowed_13_gated_we; + reg_we_check[119] = alert_en_shadowed_14_gated_we; + reg_we_check[120] = alert_en_shadowed_15_gated_we; + reg_we_check[121] = alert_en_shadowed_16_gated_we; + reg_we_check[122] = alert_en_shadowed_17_gated_we; + reg_we_check[123] = alert_en_shadowed_18_gated_we; + reg_we_check[124] = alert_en_shadowed_19_gated_we; + reg_we_check[125] = alert_en_shadowed_20_gated_we; + reg_we_check[126] = alert_en_shadowed_21_gated_we; + reg_we_check[127] = alert_en_shadowed_22_gated_we; + reg_we_check[128] = alert_en_shadowed_23_gated_we; + reg_we_check[129] = alert_en_shadowed_24_gated_we; + reg_we_check[130] = alert_en_shadowed_25_gated_we; + reg_we_check[131] = alert_en_shadowed_26_gated_we; + reg_we_check[132] = alert_en_shadowed_27_gated_we; + reg_we_check[133] = alert_en_shadowed_28_gated_we; + reg_we_check[134] = alert_en_shadowed_29_gated_we; + reg_we_check[135] = alert_en_shadowed_30_gated_we; + reg_we_check[136] = alert_en_shadowed_31_gated_we; + reg_we_check[137] = alert_en_shadowed_32_gated_we; + reg_we_check[138] = alert_en_shadowed_33_gated_we; + reg_we_check[139] = alert_en_shadowed_34_gated_we; + reg_we_check[140] = alert_en_shadowed_35_gated_we; + reg_we_check[141] = alert_en_shadowed_36_gated_we; + reg_we_check[142] = alert_en_shadowed_37_gated_we; + reg_we_check[143] = alert_en_shadowed_38_gated_we; + reg_we_check[144] = alert_en_shadowed_39_gated_we; + reg_we_check[145] = alert_en_shadowed_40_gated_we; + reg_we_check[146] = alert_en_shadowed_41_gated_we; + reg_we_check[147] = alert_en_shadowed_42_gated_we; + reg_we_check[148] = alert_en_shadowed_43_gated_we; + reg_we_check[149] = alert_en_shadowed_44_gated_we; + reg_we_check[150] = alert_en_shadowed_45_gated_we; + reg_we_check[151] = alert_en_shadowed_46_gated_we; + reg_we_check[152] = alert_en_shadowed_47_gated_we; + reg_we_check[153] = alert_en_shadowed_48_gated_we; + reg_we_check[154] = alert_en_shadowed_49_gated_we; + reg_we_check[155] = alert_en_shadowed_50_gated_we; + reg_we_check[156] = alert_en_shadowed_51_gated_we; + reg_we_check[157] = alert_en_shadowed_52_gated_we; + reg_we_check[158] = alert_en_shadowed_53_gated_we; + reg_we_check[159] = alert_en_shadowed_54_gated_we; + reg_we_check[160] = alert_en_shadowed_55_gated_we; + reg_we_check[161] = alert_en_shadowed_56_gated_we; + reg_we_check[162] = alert_en_shadowed_57_gated_we; + reg_we_check[163] = alert_en_shadowed_58_gated_we; + reg_we_check[164] = alert_en_shadowed_59_gated_we; + reg_we_check[165] = alert_en_shadowed_60_gated_we; + reg_we_check[166] = alert_en_shadowed_61_gated_we; + reg_we_check[167] = alert_en_shadowed_62_gated_we; + reg_we_check[168] = alert_en_shadowed_63_gated_we; + reg_we_check[169] = alert_en_shadowed_64_gated_we; + reg_we_check[170] = alert_en_shadowed_65_gated_we; + reg_we_check[171] = alert_en_shadowed_66_gated_we; + reg_we_check[172] = alert_en_shadowed_67_gated_we; + reg_we_check[173] = alert_en_shadowed_68_gated_we; + reg_we_check[174] = alert_en_shadowed_69_gated_we; + reg_we_check[175] = alert_en_shadowed_70_gated_we; + reg_we_check[176] = alert_en_shadowed_71_gated_we; + reg_we_check[177] = alert_en_shadowed_72_gated_we; + reg_we_check[178] = alert_en_shadowed_73_gated_we; + reg_we_check[179] = alert_en_shadowed_74_gated_we; + reg_we_check[180] = alert_en_shadowed_75_gated_we; + reg_we_check[181] = alert_en_shadowed_76_gated_we; + reg_we_check[182] = alert_en_shadowed_77_gated_we; + reg_we_check[183] = alert_en_shadowed_78_gated_we; + reg_we_check[184] = alert_en_shadowed_79_gated_we; + reg_we_check[185] = alert_en_shadowed_80_gated_we; + reg_we_check[186] = alert_en_shadowed_81_gated_we; + reg_we_check[187] = alert_en_shadowed_82_gated_we; + reg_we_check[188] = alert_en_shadowed_83_gated_we; + reg_we_check[189] = alert_en_shadowed_84_gated_we; + reg_we_check[190] = alert_en_shadowed_85_gated_we; + reg_we_check[191] = alert_en_shadowed_86_gated_we; + reg_we_check[192] = alert_en_shadowed_87_gated_we; + reg_we_check[193] = alert_en_shadowed_88_gated_we; + reg_we_check[194] = alert_en_shadowed_89_gated_we; + reg_we_check[195] = alert_en_shadowed_90_gated_we; + reg_we_check[196] = alert_en_shadowed_91_gated_we; + reg_we_check[197] = alert_en_shadowed_92_gated_we; + reg_we_check[198] = alert_en_shadowed_93_gated_we; + reg_we_check[199] = alert_en_shadowed_94_gated_we; + reg_we_check[200] = alert_en_shadowed_95_gated_we; + reg_we_check[201] = alert_en_shadowed_96_gated_we; + reg_we_check[202] = alert_en_shadowed_97_gated_we; + reg_we_check[203] = alert_en_shadowed_98_gated_we; + reg_we_check[204] = alert_class_shadowed_0_gated_we; + reg_we_check[205] = alert_class_shadowed_1_gated_we; + reg_we_check[206] = alert_class_shadowed_2_gated_we; + reg_we_check[207] = alert_class_shadowed_3_gated_we; + reg_we_check[208] = alert_class_shadowed_4_gated_we; + reg_we_check[209] = alert_class_shadowed_5_gated_we; + reg_we_check[210] = alert_class_shadowed_6_gated_we; + reg_we_check[211] = alert_class_shadowed_7_gated_we; + reg_we_check[212] = alert_class_shadowed_8_gated_we; + reg_we_check[213] = alert_class_shadowed_9_gated_we; + reg_we_check[214] = alert_class_shadowed_10_gated_we; + reg_we_check[215] = alert_class_shadowed_11_gated_we; + reg_we_check[216] = alert_class_shadowed_12_gated_we; + reg_we_check[217] = alert_class_shadowed_13_gated_we; + reg_we_check[218] = alert_class_shadowed_14_gated_we; + reg_we_check[219] = alert_class_shadowed_15_gated_we; + reg_we_check[220] = alert_class_shadowed_16_gated_we; + reg_we_check[221] = alert_class_shadowed_17_gated_we; + reg_we_check[222] = alert_class_shadowed_18_gated_we; + reg_we_check[223] = alert_class_shadowed_19_gated_we; + reg_we_check[224] = alert_class_shadowed_20_gated_we; + reg_we_check[225] = alert_class_shadowed_21_gated_we; + reg_we_check[226] = alert_class_shadowed_22_gated_we; + reg_we_check[227] = alert_class_shadowed_23_gated_we; + reg_we_check[228] = alert_class_shadowed_24_gated_we; + reg_we_check[229] = alert_class_shadowed_25_gated_we; + reg_we_check[230] = alert_class_shadowed_26_gated_we; + reg_we_check[231] = alert_class_shadowed_27_gated_we; + reg_we_check[232] = alert_class_shadowed_28_gated_we; + reg_we_check[233] = alert_class_shadowed_29_gated_we; + reg_we_check[234] = alert_class_shadowed_30_gated_we; + reg_we_check[235] = alert_class_shadowed_31_gated_we; + reg_we_check[236] = alert_class_shadowed_32_gated_we; + reg_we_check[237] = alert_class_shadowed_33_gated_we; + reg_we_check[238] = alert_class_shadowed_34_gated_we; + reg_we_check[239] = alert_class_shadowed_35_gated_we; + reg_we_check[240] = alert_class_shadowed_36_gated_we; + reg_we_check[241] = alert_class_shadowed_37_gated_we; + reg_we_check[242] = alert_class_shadowed_38_gated_we; + reg_we_check[243] = alert_class_shadowed_39_gated_we; + reg_we_check[244] = alert_class_shadowed_40_gated_we; + reg_we_check[245] = alert_class_shadowed_41_gated_we; + reg_we_check[246] = alert_class_shadowed_42_gated_we; + reg_we_check[247] = alert_class_shadowed_43_gated_we; + reg_we_check[248] = alert_class_shadowed_44_gated_we; + reg_we_check[249] = alert_class_shadowed_45_gated_we; + reg_we_check[250] = alert_class_shadowed_46_gated_we; + reg_we_check[251] = alert_class_shadowed_47_gated_we; + reg_we_check[252] = alert_class_shadowed_48_gated_we; + reg_we_check[253] = alert_class_shadowed_49_gated_we; + reg_we_check[254] = alert_class_shadowed_50_gated_we; + reg_we_check[255] = alert_class_shadowed_51_gated_we; + reg_we_check[256] = alert_class_shadowed_52_gated_we; + reg_we_check[257] = alert_class_shadowed_53_gated_we; + reg_we_check[258] = alert_class_shadowed_54_gated_we; + reg_we_check[259] = alert_class_shadowed_55_gated_we; + reg_we_check[260] = alert_class_shadowed_56_gated_we; + reg_we_check[261] = alert_class_shadowed_57_gated_we; + reg_we_check[262] = alert_class_shadowed_58_gated_we; + reg_we_check[263] = alert_class_shadowed_59_gated_we; + reg_we_check[264] = alert_class_shadowed_60_gated_we; + reg_we_check[265] = alert_class_shadowed_61_gated_we; + reg_we_check[266] = alert_class_shadowed_62_gated_we; + reg_we_check[267] = alert_class_shadowed_63_gated_we; + reg_we_check[268] = alert_class_shadowed_64_gated_we; + reg_we_check[269] = alert_class_shadowed_65_gated_we; + reg_we_check[270] = alert_class_shadowed_66_gated_we; + reg_we_check[271] = alert_class_shadowed_67_gated_we; + reg_we_check[272] = alert_class_shadowed_68_gated_we; + reg_we_check[273] = alert_class_shadowed_69_gated_we; + reg_we_check[274] = alert_class_shadowed_70_gated_we; + reg_we_check[275] = alert_class_shadowed_71_gated_we; + reg_we_check[276] = alert_class_shadowed_72_gated_we; + reg_we_check[277] = alert_class_shadowed_73_gated_we; + reg_we_check[278] = alert_class_shadowed_74_gated_we; + reg_we_check[279] = alert_class_shadowed_75_gated_we; + reg_we_check[280] = alert_class_shadowed_76_gated_we; + reg_we_check[281] = alert_class_shadowed_77_gated_we; + reg_we_check[282] = alert_class_shadowed_78_gated_we; + reg_we_check[283] = alert_class_shadowed_79_gated_we; + reg_we_check[284] = alert_class_shadowed_80_gated_we; + reg_we_check[285] = alert_class_shadowed_81_gated_we; + reg_we_check[286] = alert_class_shadowed_82_gated_we; + reg_we_check[287] = alert_class_shadowed_83_gated_we; + reg_we_check[288] = alert_class_shadowed_84_gated_we; + reg_we_check[289] = alert_class_shadowed_85_gated_we; + reg_we_check[290] = alert_class_shadowed_86_gated_we; + reg_we_check[291] = alert_class_shadowed_87_gated_we; + reg_we_check[292] = alert_class_shadowed_88_gated_we; + reg_we_check[293] = alert_class_shadowed_89_gated_we; + reg_we_check[294] = alert_class_shadowed_90_gated_we; + reg_we_check[295] = alert_class_shadowed_91_gated_we; + reg_we_check[296] = alert_class_shadowed_92_gated_we; + reg_we_check[297] = alert_class_shadowed_93_gated_we; + reg_we_check[298] = alert_class_shadowed_94_gated_we; + reg_we_check[299] = alert_class_shadowed_95_gated_we; + reg_we_check[300] = alert_class_shadowed_96_gated_we; + reg_we_check[301] = alert_class_shadowed_97_gated_we; + reg_we_check[302] = alert_class_shadowed_98_gated_we; + reg_we_check[303] = alert_cause_0_we; + reg_we_check[304] = alert_cause_1_we; + reg_we_check[305] = alert_cause_2_we; + reg_we_check[306] = alert_cause_3_we; + reg_we_check[307] = alert_cause_4_we; + reg_we_check[308] = alert_cause_5_we; + reg_we_check[309] = alert_cause_6_we; + reg_we_check[310] = alert_cause_7_we; + reg_we_check[311] = alert_cause_8_we; + reg_we_check[312] = alert_cause_9_we; + reg_we_check[313] = alert_cause_10_we; + reg_we_check[314] = alert_cause_11_we; + reg_we_check[315] = alert_cause_12_we; + reg_we_check[316] = alert_cause_13_we; + reg_we_check[317] = alert_cause_14_we; + reg_we_check[318] = alert_cause_15_we; + reg_we_check[319] = alert_cause_16_we; + reg_we_check[320] = alert_cause_17_we; + reg_we_check[321] = alert_cause_18_we; + reg_we_check[322] = alert_cause_19_we; + reg_we_check[323] = alert_cause_20_we; + reg_we_check[324] = alert_cause_21_we; + reg_we_check[325] = alert_cause_22_we; + reg_we_check[326] = alert_cause_23_we; + reg_we_check[327] = alert_cause_24_we; + reg_we_check[328] = alert_cause_25_we; + reg_we_check[329] = alert_cause_26_we; + reg_we_check[330] = alert_cause_27_we; + reg_we_check[331] = alert_cause_28_we; + reg_we_check[332] = alert_cause_29_we; + reg_we_check[333] = alert_cause_30_we; + reg_we_check[334] = alert_cause_31_we; + reg_we_check[335] = alert_cause_32_we; + reg_we_check[336] = alert_cause_33_we; + reg_we_check[337] = alert_cause_34_we; + reg_we_check[338] = alert_cause_35_we; + reg_we_check[339] = alert_cause_36_we; + reg_we_check[340] = alert_cause_37_we; + reg_we_check[341] = alert_cause_38_we; + reg_we_check[342] = alert_cause_39_we; + reg_we_check[343] = alert_cause_40_we; + reg_we_check[344] = alert_cause_41_we; + reg_we_check[345] = alert_cause_42_we; + reg_we_check[346] = alert_cause_43_we; + reg_we_check[347] = alert_cause_44_we; + reg_we_check[348] = alert_cause_45_we; + reg_we_check[349] = alert_cause_46_we; + reg_we_check[350] = alert_cause_47_we; + reg_we_check[351] = alert_cause_48_we; + reg_we_check[352] = alert_cause_49_we; + reg_we_check[353] = alert_cause_50_we; + reg_we_check[354] = alert_cause_51_we; + reg_we_check[355] = alert_cause_52_we; + reg_we_check[356] = alert_cause_53_we; + reg_we_check[357] = alert_cause_54_we; + reg_we_check[358] = alert_cause_55_we; + reg_we_check[359] = alert_cause_56_we; + reg_we_check[360] = alert_cause_57_we; + reg_we_check[361] = alert_cause_58_we; + reg_we_check[362] = alert_cause_59_we; + reg_we_check[363] = alert_cause_60_we; + reg_we_check[364] = alert_cause_61_we; + reg_we_check[365] = alert_cause_62_we; + reg_we_check[366] = alert_cause_63_we; + reg_we_check[367] = alert_cause_64_we; + reg_we_check[368] = alert_cause_65_we; + reg_we_check[369] = alert_cause_66_we; + reg_we_check[370] = alert_cause_67_we; + reg_we_check[371] = alert_cause_68_we; + reg_we_check[372] = alert_cause_69_we; + reg_we_check[373] = alert_cause_70_we; + reg_we_check[374] = alert_cause_71_we; + reg_we_check[375] = alert_cause_72_we; + reg_we_check[376] = alert_cause_73_we; + reg_we_check[377] = alert_cause_74_we; + reg_we_check[378] = alert_cause_75_we; + reg_we_check[379] = alert_cause_76_we; + reg_we_check[380] = alert_cause_77_we; + reg_we_check[381] = alert_cause_78_we; + reg_we_check[382] = alert_cause_79_we; + reg_we_check[383] = alert_cause_80_we; + reg_we_check[384] = alert_cause_81_we; + reg_we_check[385] = alert_cause_82_we; + reg_we_check[386] = alert_cause_83_we; + reg_we_check[387] = alert_cause_84_we; + reg_we_check[388] = alert_cause_85_we; + reg_we_check[389] = alert_cause_86_we; + reg_we_check[390] = alert_cause_87_we; + reg_we_check[391] = alert_cause_88_we; + reg_we_check[392] = alert_cause_89_we; + reg_we_check[393] = alert_cause_90_we; + reg_we_check[394] = alert_cause_91_we; + reg_we_check[395] = alert_cause_92_we; + reg_we_check[396] = alert_cause_93_we; + reg_we_check[397] = alert_cause_94_we; + reg_we_check[398] = alert_cause_95_we; + reg_we_check[399] = alert_cause_96_we; + reg_we_check[400] = alert_cause_97_we; + reg_we_check[401] = alert_cause_98_we; + reg_we_check[402] = loc_alert_regwen_0_we; + reg_we_check[403] = loc_alert_regwen_1_we; + reg_we_check[404] = loc_alert_regwen_2_we; + reg_we_check[405] = loc_alert_regwen_3_we; + reg_we_check[406] = loc_alert_regwen_4_we; + reg_we_check[407] = loc_alert_regwen_5_we; + reg_we_check[408] = loc_alert_regwen_6_we; + reg_we_check[409] = loc_alert_en_shadowed_0_gated_we; + reg_we_check[410] = loc_alert_en_shadowed_1_gated_we; + reg_we_check[411] = loc_alert_en_shadowed_2_gated_we; + reg_we_check[412] = loc_alert_en_shadowed_3_gated_we; + reg_we_check[413] = loc_alert_en_shadowed_4_gated_we; + reg_we_check[414] = loc_alert_en_shadowed_5_gated_we; + reg_we_check[415] = loc_alert_en_shadowed_6_gated_we; + reg_we_check[416] = loc_alert_class_shadowed_0_gated_we; + reg_we_check[417] = loc_alert_class_shadowed_1_gated_we; + reg_we_check[418] = loc_alert_class_shadowed_2_gated_we; + reg_we_check[419] = loc_alert_class_shadowed_3_gated_we; + reg_we_check[420] = loc_alert_class_shadowed_4_gated_we; + reg_we_check[421] = loc_alert_class_shadowed_5_gated_we; + reg_we_check[422] = loc_alert_class_shadowed_6_gated_we; + reg_we_check[423] = loc_alert_cause_0_we; + reg_we_check[424] = loc_alert_cause_1_we; + reg_we_check[425] = loc_alert_cause_2_we; + reg_we_check[426] = loc_alert_cause_3_we; + reg_we_check[427] = loc_alert_cause_4_we; + reg_we_check[428] = loc_alert_cause_5_we; + reg_we_check[429] = loc_alert_cause_6_we; + reg_we_check[430] = classa_regwen_we; + reg_we_check[431] = classa_ctrl_shadowed_gated_we; + reg_we_check[432] = classa_clr_regwen_we; + reg_we_check[433] = classa_clr_shadowed_gated_we; + reg_we_check[434] = 1'b0; + reg_we_check[435] = classa_accum_thresh_shadowed_gated_we; + reg_we_check[436] = classa_timeout_cyc_shadowed_gated_we; + reg_we_check[437] = classa_crashdump_trigger_shadowed_gated_we; + reg_we_check[438] = classa_phase0_cyc_shadowed_gated_we; + reg_we_check[439] = classa_phase1_cyc_shadowed_gated_we; + reg_we_check[440] = classa_phase2_cyc_shadowed_gated_we; + reg_we_check[441] = classa_phase3_cyc_shadowed_gated_we; + reg_we_check[442] = 1'b0; + reg_we_check[443] = 1'b0; + reg_we_check[444] = classb_regwen_we; + reg_we_check[445] = classb_ctrl_shadowed_gated_we; + reg_we_check[446] = classb_clr_regwen_we; + reg_we_check[447] = classb_clr_shadowed_gated_we; + reg_we_check[448] = 1'b0; + reg_we_check[449] = classb_accum_thresh_shadowed_gated_we; + reg_we_check[450] = classb_timeout_cyc_shadowed_gated_we; + reg_we_check[451] = classb_crashdump_trigger_shadowed_gated_we; + reg_we_check[452] = classb_phase0_cyc_shadowed_gated_we; + reg_we_check[453] = classb_phase1_cyc_shadowed_gated_we; + reg_we_check[454] = classb_phase2_cyc_shadowed_gated_we; + reg_we_check[455] = classb_phase3_cyc_shadowed_gated_we; + reg_we_check[456] = 1'b0; + reg_we_check[457] = 1'b0; + reg_we_check[458] = classc_regwen_we; + reg_we_check[459] = classc_ctrl_shadowed_gated_we; + reg_we_check[460] = classc_clr_regwen_we; + reg_we_check[461] = classc_clr_shadowed_gated_we; + reg_we_check[462] = 1'b0; + reg_we_check[463] = classc_accum_thresh_shadowed_gated_we; + reg_we_check[464] = classc_timeout_cyc_shadowed_gated_we; + reg_we_check[465] = classc_crashdump_trigger_shadowed_gated_we; + reg_we_check[466] = classc_phase0_cyc_shadowed_gated_we; + reg_we_check[467] = classc_phase1_cyc_shadowed_gated_we; + reg_we_check[468] = classc_phase2_cyc_shadowed_gated_we; + reg_we_check[469] = classc_phase3_cyc_shadowed_gated_we; + reg_we_check[470] = 1'b0; + reg_we_check[471] = 1'b0; + reg_we_check[472] = classd_regwen_we; + reg_we_check[473] = classd_ctrl_shadowed_gated_we; + reg_we_check[474] = classd_clr_regwen_we; + reg_we_check[475] = classd_clr_shadowed_gated_we; + reg_we_check[476] = 1'b0; + reg_we_check[477] = classd_accum_thresh_shadowed_gated_we; + reg_we_check[478] = classd_timeout_cyc_shadowed_gated_we; + reg_we_check[479] = classd_crashdump_trigger_shadowed_gated_we; + reg_we_check[480] = classd_phase0_cyc_shadowed_gated_we; + reg_we_check[481] = classd_phase1_cyc_shadowed_gated_we; + reg_we_check[482] = classd_phase2_cyc_shadowed_gated_we; + reg_we_check[483] = classd_phase3_cyc_shadowed_gated_we; + reg_we_check[484] = 1'b0; + reg_we_check[485] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = intr_state_classa_qs; + reg_rdata_next[1] = intr_state_classb_qs; + reg_rdata_next[2] = intr_state_classc_qs; + reg_rdata_next[3] = intr_state_classd_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = intr_enable_classa_qs; + reg_rdata_next[1] = intr_enable_classb_qs; + reg_rdata_next[2] = intr_enable_classc_qs; + reg_rdata_next[3] = intr_enable_classd_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[0] = ping_timer_regwen_qs; + end + + addr_hit[4]: begin + reg_rdata_next[15:0] = ping_timeout_cyc_shadowed_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = ping_timer_en_shadowed_qs; + end + + addr_hit[6]: begin + reg_rdata_next[0] = alert_regwen_0_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = alert_regwen_1_qs; + end + + addr_hit[8]: begin + reg_rdata_next[0] = alert_regwen_2_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = alert_regwen_3_qs; + end + + addr_hit[10]: begin + reg_rdata_next[0] = alert_regwen_4_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = alert_regwen_5_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = alert_regwen_6_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = alert_regwen_7_qs; + end + + addr_hit[14]: begin + reg_rdata_next[0] = alert_regwen_8_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = alert_regwen_9_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = alert_regwen_10_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = alert_regwen_11_qs; + end + + addr_hit[18]: begin + reg_rdata_next[0] = alert_regwen_12_qs; + end + + addr_hit[19]: begin + reg_rdata_next[0] = alert_regwen_13_qs; + end + + addr_hit[20]: begin + reg_rdata_next[0] = alert_regwen_14_qs; + end + + addr_hit[21]: begin + reg_rdata_next[0] = alert_regwen_15_qs; + end + + addr_hit[22]: begin + reg_rdata_next[0] = alert_regwen_16_qs; + end + + addr_hit[23]: begin + reg_rdata_next[0] = alert_regwen_17_qs; + end + + addr_hit[24]: begin + reg_rdata_next[0] = alert_regwen_18_qs; + end + + addr_hit[25]: begin + reg_rdata_next[0] = alert_regwen_19_qs; + end + + addr_hit[26]: begin + reg_rdata_next[0] = alert_regwen_20_qs; + end + + addr_hit[27]: begin + reg_rdata_next[0] = alert_regwen_21_qs; + end + + addr_hit[28]: begin + reg_rdata_next[0] = alert_regwen_22_qs; + end + + addr_hit[29]: begin + reg_rdata_next[0] = alert_regwen_23_qs; + end + + addr_hit[30]: begin + reg_rdata_next[0] = alert_regwen_24_qs; + end + + addr_hit[31]: begin + reg_rdata_next[0] = alert_regwen_25_qs; + end + + addr_hit[32]: begin + reg_rdata_next[0] = alert_regwen_26_qs; + end + + addr_hit[33]: begin + reg_rdata_next[0] = alert_regwen_27_qs; + end + + addr_hit[34]: begin + reg_rdata_next[0] = alert_regwen_28_qs; + end + + addr_hit[35]: begin + reg_rdata_next[0] = alert_regwen_29_qs; + end + + addr_hit[36]: begin + reg_rdata_next[0] = alert_regwen_30_qs; + end + + addr_hit[37]: begin + reg_rdata_next[0] = alert_regwen_31_qs; + end + + addr_hit[38]: begin + reg_rdata_next[0] = alert_regwen_32_qs; + end + + addr_hit[39]: begin + reg_rdata_next[0] = alert_regwen_33_qs; + end + + addr_hit[40]: begin + reg_rdata_next[0] = alert_regwen_34_qs; + end + + addr_hit[41]: begin + reg_rdata_next[0] = alert_regwen_35_qs; + end + + addr_hit[42]: begin + reg_rdata_next[0] = alert_regwen_36_qs; + end + + addr_hit[43]: begin + reg_rdata_next[0] = alert_regwen_37_qs; + end + + addr_hit[44]: begin + reg_rdata_next[0] = alert_regwen_38_qs; + end + + addr_hit[45]: begin + reg_rdata_next[0] = alert_regwen_39_qs; + end + + addr_hit[46]: begin + reg_rdata_next[0] = alert_regwen_40_qs; + end + + addr_hit[47]: begin + reg_rdata_next[0] = alert_regwen_41_qs; + end + + addr_hit[48]: begin + reg_rdata_next[0] = alert_regwen_42_qs; + end + + addr_hit[49]: begin + reg_rdata_next[0] = alert_regwen_43_qs; + end + + addr_hit[50]: begin + reg_rdata_next[0] = alert_regwen_44_qs; + end + + addr_hit[51]: begin + reg_rdata_next[0] = alert_regwen_45_qs; + end + + addr_hit[52]: begin + reg_rdata_next[0] = alert_regwen_46_qs; + end + + addr_hit[53]: begin + reg_rdata_next[0] = alert_regwen_47_qs; + end + + addr_hit[54]: begin + reg_rdata_next[0] = alert_regwen_48_qs; + end + + addr_hit[55]: begin + reg_rdata_next[0] = alert_regwen_49_qs; + end + + addr_hit[56]: begin + reg_rdata_next[0] = alert_regwen_50_qs; + end + + addr_hit[57]: begin + reg_rdata_next[0] = alert_regwen_51_qs; + end + + addr_hit[58]: begin + reg_rdata_next[0] = alert_regwen_52_qs; + end + + addr_hit[59]: begin + reg_rdata_next[0] = alert_regwen_53_qs; + end + + addr_hit[60]: begin + reg_rdata_next[0] = alert_regwen_54_qs; + end + + addr_hit[61]: begin + reg_rdata_next[0] = alert_regwen_55_qs; + end + + addr_hit[62]: begin + reg_rdata_next[0] = alert_regwen_56_qs; + end + + addr_hit[63]: begin + reg_rdata_next[0] = alert_regwen_57_qs; + end + + addr_hit[64]: begin + reg_rdata_next[0] = alert_regwen_58_qs; + end + + addr_hit[65]: begin + reg_rdata_next[0] = alert_regwen_59_qs; + end + + addr_hit[66]: begin + reg_rdata_next[0] = alert_regwen_60_qs; + end + + addr_hit[67]: begin + reg_rdata_next[0] = alert_regwen_61_qs; + end + + addr_hit[68]: begin + reg_rdata_next[0] = alert_regwen_62_qs; + end + + addr_hit[69]: begin + reg_rdata_next[0] = alert_regwen_63_qs; + end + + addr_hit[70]: begin + reg_rdata_next[0] = alert_regwen_64_qs; + end + + addr_hit[71]: begin + reg_rdata_next[0] = alert_regwen_65_qs; + end + + addr_hit[72]: begin + reg_rdata_next[0] = alert_regwen_66_qs; + end + + addr_hit[73]: begin + reg_rdata_next[0] = alert_regwen_67_qs; + end + + addr_hit[74]: begin + reg_rdata_next[0] = alert_regwen_68_qs; + end + + addr_hit[75]: begin + reg_rdata_next[0] = alert_regwen_69_qs; + end + + addr_hit[76]: begin + reg_rdata_next[0] = alert_regwen_70_qs; + end + + addr_hit[77]: begin + reg_rdata_next[0] = alert_regwen_71_qs; + end + + addr_hit[78]: begin + reg_rdata_next[0] = alert_regwen_72_qs; + end + + addr_hit[79]: begin + reg_rdata_next[0] = alert_regwen_73_qs; + end + + addr_hit[80]: begin + reg_rdata_next[0] = alert_regwen_74_qs; + end + + addr_hit[81]: begin + reg_rdata_next[0] = alert_regwen_75_qs; + end + + addr_hit[82]: begin + reg_rdata_next[0] = alert_regwen_76_qs; + end + + addr_hit[83]: begin + reg_rdata_next[0] = alert_regwen_77_qs; + end + + addr_hit[84]: begin + reg_rdata_next[0] = alert_regwen_78_qs; + end + + addr_hit[85]: begin + reg_rdata_next[0] = alert_regwen_79_qs; + end + + addr_hit[86]: begin + reg_rdata_next[0] = alert_regwen_80_qs; + end + + addr_hit[87]: begin + reg_rdata_next[0] = alert_regwen_81_qs; + end + + addr_hit[88]: begin + reg_rdata_next[0] = alert_regwen_82_qs; + end + + addr_hit[89]: begin + reg_rdata_next[0] = alert_regwen_83_qs; + end + + addr_hit[90]: begin + reg_rdata_next[0] = alert_regwen_84_qs; + end + + addr_hit[91]: begin + reg_rdata_next[0] = alert_regwen_85_qs; + end + + addr_hit[92]: begin + reg_rdata_next[0] = alert_regwen_86_qs; + end + + addr_hit[93]: begin + reg_rdata_next[0] = alert_regwen_87_qs; + end + + addr_hit[94]: begin + reg_rdata_next[0] = alert_regwen_88_qs; + end + + addr_hit[95]: begin + reg_rdata_next[0] = alert_regwen_89_qs; + end + + addr_hit[96]: begin + reg_rdata_next[0] = alert_regwen_90_qs; + end + + addr_hit[97]: begin + reg_rdata_next[0] = alert_regwen_91_qs; + end + + addr_hit[98]: begin + reg_rdata_next[0] = alert_regwen_92_qs; + end + + addr_hit[99]: begin + reg_rdata_next[0] = alert_regwen_93_qs; + end + + addr_hit[100]: begin + reg_rdata_next[0] = alert_regwen_94_qs; + end + + addr_hit[101]: begin + reg_rdata_next[0] = alert_regwen_95_qs; + end + + addr_hit[102]: begin + reg_rdata_next[0] = alert_regwen_96_qs; + end + + addr_hit[103]: begin + reg_rdata_next[0] = alert_regwen_97_qs; + end + + addr_hit[104]: begin + reg_rdata_next[0] = alert_regwen_98_qs; + end + + addr_hit[105]: begin + reg_rdata_next[0] = alert_en_shadowed_0_qs; + end + + addr_hit[106]: begin + reg_rdata_next[0] = alert_en_shadowed_1_qs; + end + + addr_hit[107]: begin + reg_rdata_next[0] = alert_en_shadowed_2_qs; + end + + addr_hit[108]: begin + reg_rdata_next[0] = alert_en_shadowed_3_qs; + end + + addr_hit[109]: begin + reg_rdata_next[0] = alert_en_shadowed_4_qs; + end + + addr_hit[110]: begin + reg_rdata_next[0] = alert_en_shadowed_5_qs; + end + + addr_hit[111]: begin + reg_rdata_next[0] = alert_en_shadowed_6_qs; + end + + addr_hit[112]: begin + reg_rdata_next[0] = alert_en_shadowed_7_qs; + end + + addr_hit[113]: begin + reg_rdata_next[0] = alert_en_shadowed_8_qs; + end + + addr_hit[114]: begin + reg_rdata_next[0] = alert_en_shadowed_9_qs; + end + + addr_hit[115]: begin + reg_rdata_next[0] = alert_en_shadowed_10_qs; + end + + addr_hit[116]: begin + reg_rdata_next[0] = alert_en_shadowed_11_qs; + end + + addr_hit[117]: begin + reg_rdata_next[0] = alert_en_shadowed_12_qs; + end + + addr_hit[118]: begin + reg_rdata_next[0] = alert_en_shadowed_13_qs; + end + + addr_hit[119]: begin + reg_rdata_next[0] = alert_en_shadowed_14_qs; + end + + addr_hit[120]: begin + reg_rdata_next[0] = alert_en_shadowed_15_qs; + end + + addr_hit[121]: begin + reg_rdata_next[0] = alert_en_shadowed_16_qs; + end + + addr_hit[122]: begin + reg_rdata_next[0] = alert_en_shadowed_17_qs; + end + + addr_hit[123]: begin + reg_rdata_next[0] = alert_en_shadowed_18_qs; + end + + addr_hit[124]: begin + reg_rdata_next[0] = alert_en_shadowed_19_qs; + end + + addr_hit[125]: begin + reg_rdata_next[0] = alert_en_shadowed_20_qs; + end + + addr_hit[126]: begin + reg_rdata_next[0] = alert_en_shadowed_21_qs; + end + + addr_hit[127]: begin + reg_rdata_next[0] = alert_en_shadowed_22_qs; + end + + addr_hit[128]: begin + reg_rdata_next[0] = alert_en_shadowed_23_qs; + end + + addr_hit[129]: begin + reg_rdata_next[0] = alert_en_shadowed_24_qs; + end + + addr_hit[130]: begin + reg_rdata_next[0] = alert_en_shadowed_25_qs; + end + + addr_hit[131]: begin + reg_rdata_next[0] = alert_en_shadowed_26_qs; + end + + addr_hit[132]: begin + reg_rdata_next[0] = alert_en_shadowed_27_qs; + end + + addr_hit[133]: begin + reg_rdata_next[0] = alert_en_shadowed_28_qs; + end + + addr_hit[134]: begin + reg_rdata_next[0] = alert_en_shadowed_29_qs; + end + + addr_hit[135]: begin + reg_rdata_next[0] = alert_en_shadowed_30_qs; + end + + addr_hit[136]: begin + reg_rdata_next[0] = alert_en_shadowed_31_qs; + end + + addr_hit[137]: begin + reg_rdata_next[0] = alert_en_shadowed_32_qs; + end + + addr_hit[138]: begin + reg_rdata_next[0] = alert_en_shadowed_33_qs; + end + + addr_hit[139]: begin + reg_rdata_next[0] = alert_en_shadowed_34_qs; + end + + addr_hit[140]: begin + reg_rdata_next[0] = alert_en_shadowed_35_qs; + end + + addr_hit[141]: begin + reg_rdata_next[0] = alert_en_shadowed_36_qs; + end + + addr_hit[142]: begin + reg_rdata_next[0] = alert_en_shadowed_37_qs; + end + + addr_hit[143]: begin + reg_rdata_next[0] = alert_en_shadowed_38_qs; + end + + addr_hit[144]: begin + reg_rdata_next[0] = alert_en_shadowed_39_qs; + end + + addr_hit[145]: begin + reg_rdata_next[0] = alert_en_shadowed_40_qs; + end + + addr_hit[146]: begin + reg_rdata_next[0] = alert_en_shadowed_41_qs; + end + + addr_hit[147]: begin + reg_rdata_next[0] = alert_en_shadowed_42_qs; + end + + addr_hit[148]: begin + reg_rdata_next[0] = alert_en_shadowed_43_qs; + end + + addr_hit[149]: begin + reg_rdata_next[0] = alert_en_shadowed_44_qs; + end + + addr_hit[150]: begin + reg_rdata_next[0] = alert_en_shadowed_45_qs; + end + + addr_hit[151]: begin + reg_rdata_next[0] = alert_en_shadowed_46_qs; + end + + addr_hit[152]: begin + reg_rdata_next[0] = alert_en_shadowed_47_qs; + end + + addr_hit[153]: begin + reg_rdata_next[0] = alert_en_shadowed_48_qs; + end + + addr_hit[154]: begin + reg_rdata_next[0] = alert_en_shadowed_49_qs; + end + + addr_hit[155]: begin + reg_rdata_next[0] = alert_en_shadowed_50_qs; + end + + addr_hit[156]: begin + reg_rdata_next[0] = alert_en_shadowed_51_qs; + end + + addr_hit[157]: begin + reg_rdata_next[0] = alert_en_shadowed_52_qs; + end + + addr_hit[158]: begin + reg_rdata_next[0] = alert_en_shadowed_53_qs; + end + + addr_hit[159]: begin + reg_rdata_next[0] = alert_en_shadowed_54_qs; + end + + addr_hit[160]: begin + reg_rdata_next[0] = alert_en_shadowed_55_qs; + end + + addr_hit[161]: begin + reg_rdata_next[0] = alert_en_shadowed_56_qs; + end + + addr_hit[162]: begin + reg_rdata_next[0] = alert_en_shadowed_57_qs; + end + + addr_hit[163]: begin + reg_rdata_next[0] = alert_en_shadowed_58_qs; + end + + addr_hit[164]: begin + reg_rdata_next[0] = alert_en_shadowed_59_qs; + end + + addr_hit[165]: begin + reg_rdata_next[0] = alert_en_shadowed_60_qs; + end + + addr_hit[166]: begin + reg_rdata_next[0] = alert_en_shadowed_61_qs; + end + + addr_hit[167]: begin + reg_rdata_next[0] = alert_en_shadowed_62_qs; + end + + addr_hit[168]: begin + reg_rdata_next[0] = alert_en_shadowed_63_qs; + end + + addr_hit[169]: begin + reg_rdata_next[0] = alert_en_shadowed_64_qs; + end + + addr_hit[170]: begin + reg_rdata_next[0] = alert_en_shadowed_65_qs; + end + + addr_hit[171]: begin + reg_rdata_next[0] = alert_en_shadowed_66_qs; + end + + addr_hit[172]: begin + reg_rdata_next[0] = alert_en_shadowed_67_qs; + end + + addr_hit[173]: begin + reg_rdata_next[0] = alert_en_shadowed_68_qs; + end + + addr_hit[174]: begin + reg_rdata_next[0] = alert_en_shadowed_69_qs; + end + + addr_hit[175]: begin + reg_rdata_next[0] = alert_en_shadowed_70_qs; + end + + addr_hit[176]: begin + reg_rdata_next[0] = alert_en_shadowed_71_qs; + end + + addr_hit[177]: begin + reg_rdata_next[0] = alert_en_shadowed_72_qs; + end + + addr_hit[178]: begin + reg_rdata_next[0] = alert_en_shadowed_73_qs; + end + + addr_hit[179]: begin + reg_rdata_next[0] = alert_en_shadowed_74_qs; + end + + addr_hit[180]: begin + reg_rdata_next[0] = alert_en_shadowed_75_qs; + end + + addr_hit[181]: begin + reg_rdata_next[0] = alert_en_shadowed_76_qs; + end + + addr_hit[182]: begin + reg_rdata_next[0] = alert_en_shadowed_77_qs; + end + + addr_hit[183]: begin + reg_rdata_next[0] = alert_en_shadowed_78_qs; + end + + addr_hit[184]: begin + reg_rdata_next[0] = alert_en_shadowed_79_qs; + end + + addr_hit[185]: begin + reg_rdata_next[0] = alert_en_shadowed_80_qs; + end + + addr_hit[186]: begin + reg_rdata_next[0] = alert_en_shadowed_81_qs; + end + + addr_hit[187]: begin + reg_rdata_next[0] = alert_en_shadowed_82_qs; + end + + addr_hit[188]: begin + reg_rdata_next[0] = alert_en_shadowed_83_qs; + end + + addr_hit[189]: begin + reg_rdata_next[0] = alert_en_shadowed_84_qs; + end + + addr_hit[190]: begin + reg_rdata_next[0] = alert_en_shadowed_85_qs; + end + + addr_hit[191]: begin + reg_rdata_next[0] = alert_en_shadowed_86_qs; + end + + addr_hit[192]: begin + reg_rdata_next[0] = alert_en_shadowed_87_qs; + end + + addr_hit[193]: begin + reg_rdata_next[0] = alert_en_shadowed_88_qs; + end + + addr_hit[194]: begin + reg_rdata_next[0] = alert_en_shadowed_89_qs; + end + + addr_hit[195]: begin + reg_rdata_next[0] = alert_en_shadowed_90_qs; + end + + addr_hit[196]: begin + reg_rdata_next[0] = alert_en_shadowed_91_qs; + end + + addr_hit[197]: begin + reg_rdata_next[0] = alert_en_shadowed_92_qs; + end + + addr_hit[198]: begin + reg_rdata_next[0] = alert_en_shadowed_93_qs; + end + + addr_hit[199]: begin + reg_rdata_next[0] = alert_en_shadowed_94_qs; + end + + addr_hit[200]: begin + reg_rdata_next[0] = alert_en_shadowed_95_qs; + end + + addr_hit[201]: begin + reg_rdata_next[0] = alert_en_shadowed_96_qs; + end + + addr_hit[202]: begin + reg_rdata_next[0] = alert_en_shadowed_97_qs; + end + + addr_hit[203]: begin + reg_rdata_next[0] = alert_en_shadowed_98_qs; + end + + addr_hit[204]: begin + reg_rdata_next[1:0] = alert_class_shadowed_0_qs; + end + + addr_hit[205]: begin + reg_rdata_next[1:0] = alert_class_shadowed_1_qs; + end + + addr_hit[206]: begin + reg_rdata_next[1:0] = alert_class_shadowed_2_qs; + end + + addr_hit[207]: begin + reg_rdata_next[1:0] = alert_class_shadowed_3_qs; + end + + addr_hit[208]: begin + reg_rdata_next[1:0] = alert_class_shadowed_4_qs; + end + + addr_hit[209]: begin + reg_rdata_next[1:0] = alert_class_shadowed_5_qs; + end + + addr_hit[210]: begin + reg_rdata_next[1:0] = alert_class_shadowed_6_qs; + end + + addr_hit[211]: begin + reg_rdata_next[1:0] = alert_class_shadowed_7_qs; + end + + addr_hit[212]: begin + reg_rdata_next[1:0] = alert_class_shadowed_8_qs; + end + + addr_hit[213]: begin + reg_rdata_next[1:0] = alert_class_shadowed_9_qs; + end + + addr_hit[214]: begin + reg_rdata_next[1:0] = alert_class_shadowed_10_qs; + end + + addr_hit[215]: begin + reg_rdata_next[1:0] = alert_class_shadowed_11_qs; + end + + addr_hit[216]: begin + reg_rdata_next[1:0] = alert_class_shadowed_12_qs; + end + + addr_hit[217]: begin + reg_rdata_next[1:0] = alert_class_shadowed_13_qs; + end + + addr_hit[218]: begin + reg_rdata_next[1:0] = alert_class_shadowed_14_qs; + end + + addr_hit[219]: begin + reg_rdata_next[1:0] = alert_class_shadowed_15_qs; + end + + addr_hit[220]: begin + reg_rdata_next[1:0] = alert_class_shadowed_16_qs; + end + + addr_hit[221]: begin + reg_rdata_next[1:0] = alert_class_shadowed_17_qs; + end + + addr_hit[222]: begin + reg_rdata_next[1:0] = alert_class_shadowed_18_qs; + end + + addr_hit[223]: begin + reg_rdata_next[1:0] = alert_class_shadowed_19_qs; + end + + addr_hit[224]: begin + reg_rdata_next[1:0] = alert_class_shadowed_20_qs; + end + + addr_hit[225]: begin + reg_rdata_next[1:0] = alert_class_shadowed_21_qs; + end + + addr_hit[226]: begin + reg_rdata_next[1:0] = alert_class_shadowed_22_qs; + end + + addr_hit[227]: begin + reg_rdata_next[1:0] = alert_class_shadowed_23_qs; + end + + addr_hit[228]: begin + reg_rdata_next[1:0] = alert_class_shadowed_24_qs; + end + + addr_hit[229]: begin + reg_rdata_next[1:0] = alert_class_shadowed_25_qs; + end + + addr_hit[230]: begin + reg_rdata_next[1:0] = alert_class_shadowed_26_qs; + end + + addr_hit[231]: begin + reg_rdata_next[1:0] = alert_class_shadowed_27_qs; + end + + addr_hit[232]: begin + reg_rdata_next[1:0] = alert_class_shadowed_28_qs; + end + + addr_hit[233]: begin + reg_rdata_next[1:0] = alert_class_shadowed_29_qs; + end + + addr_hit[234]: begin + reg_rdata_next[1:0] = alert_class_shadowed_30_qs; + end + + addr_hit[235]: begin + reg_rdata_next[1:0] = alert_class_shadowed_31_qs; + end + + addr_hit[236]: begin + reg_rdata_next[1:0] = alert_class_shadowed_32_qs; + end + + addr_hit[237]: begin + reg_rdata_next[1:0] = alert_class_shadowed_33_qs; + end + + addr_hit[238]: begin + reg_rdata_next[1:0] = alert_class_shadowed_34_qs; + end + + addr_hit[239]: begin + reg_rdata_next[1:0] = alert_class_shadowed_35_qs; + end + + addr_hit[240]: begin + reg_rdata_next[1:0] = alert_class_shadowed_36_qs; + end + + addr_hit[241]: begin + reg_rdata_next[1:0] = alert_class_shadowed_37_qs; + end + + addr_hit[242]: begin + reg_rdata_next[1:0] = alert_class_shadowed_38_qs; + end + + addr_hit[243]: begin + reg_rdata_next[1:0] = alert_class_shadowed_39_qs; + end + + addr_hit[244]: begin + reg_rdata_next[1:0] = alert_class_shadowed_40_qs; + end + + addr_hit[245]: begin + reg_rdata_next[1:0] = alert_class_shadowed_41_qs; + end + + addr_hit[246]: begin + reg_rdata_next[1:0] = alert_class_shadowed_42_qs; + end + + addr_hit[247]: begin + reg_rdata_next[1:0] = alert_class_shadowed_43_qs; + end + + addr_hit[248]: begin + reg_rdata_next[1:0] = alert_class_shadowed_44_qs; + end + + addr_hit[249]: begin + reg_rdata_next[1:0] = alert_class_shadowed_45_qs; + end + + addr_hit[250]: begin + reg_rdata_next[1:0] = alert_class_shadowed_46_qs; + end + + addr_hit[251]: begin + reg_rdata_next[1:0] = alert_class_shadowed_47_qs; + end + + addr_hit[252]: begin + reg_rdata_next[1:0] = alert_class_shadowed_48_qs; + end + + addr_hit[253]: begin + reg_rdata_next[1:0] = alert_class_shadowed_49_qs; + end + + addr_hit[254]: begin + reg_rdata_next[1:0] = alert_class_shadowed_50_qs; + end + + addr_hit[255]: begin + reg_rdata_next[1:0] = alert_class_shadowed_51_qs; + end + + addr_hit[256]: begin + reg_rdata_next[1:0] = alert_class_shadowed_52_qs; + end + + addr_hit[257]: begin + reg_rdata_next[1:0] = alert_class_shadowed_53_qs; + end + + addr_hit[258]: begin + reg_rdata_next[1:0] = alert_class_shadowed_54_qs; + end + + addr_hit[259]: begin + reg_rdata_next[1:0] = alert_class_shadowed_55_qs; + end + + addr_hit[260]: begin + reg_rdata_next[1:0] = alert_class_shadowed_56_qs; + end + + addr_hit[261]: begin + reg_rdata_next[1:0] = alert_class_shadowed_57_qs; + end + + addr_hit[262]: begin + reg_rdata_next[1:0] = alert_class_shadowed_58_qs; + end + + addr_hit[263]: begin + reg_rdata_next[1:0] = alert_class_shadowed_59_qs; + end + + addr_hit[264]: begin + reg_rdata_next[1:0] = alert_class_shadowed_60_qs; + end + + addr_hit[265]: begin + reg_rdata_next[1:0] = alert_class_shadowed_61_qs; + end + + addr_hit[266]: begin + reg_rdata_next[1:0] = alert_class_shadowed_62_qs; + end + + addr_hit[267]: begin + reg_rdata_next[1:0] = alert_class_shadowed_63_qs; + end + + addr_hit[268]: begin + reg_rdata_next[1:0] = alert_class_shadowed_64_qs; + end + + addr_hit[269]: begin + reg_rdata_next[1:0] = alert_class_shadowed_65_qs; + end + + addr_hit[270]: begin + reg_rdata_next[1:0] = alert_class_shadowed_66_qs; + end + + addr_hit[271]: begin + reg_rdata_next[1:0] = alert_class_shadowed_67_qs; + end + + addr_hit[272]: begin + reg_rdata_next[1:0] = alert_class_shadowed_68_qs; + end + + addr_hit[273]: begin + reg_rdata_next[1:0] = alert_class_shadowed_69_qs; + end + + addr_hit[274]: begin + reg_rdata_next[1:0] = alert_class_shadowed_70_qs; + end + + addr_hit[275]: begin + reg_rdata_next[1:0] = alert_class_shadowed_71_qs; + end + + addr_hit[276]: begin + reg_rdata_next[1:0] = alert_class_shadowed_72_qs; + end + + addr_hit[277]: begin + reg_rdata_next[1:0] = alert_class_shadowed_73_qs; + end + + addr_hit[278]: begin + reg_rdata_next[1:0] = alert_class_shadowed_74_qs; + end + + addr_hit[279]: begin + reg_rdata_next[1:0] = alert_class_shadowed_75_qs; + end + + addr_hit[280]: begin + reg_rdata_next[1:0] = alert_class_shadowed_76_qs; + end + + addr_hit[281]: begin + reg_rdata_next[1:0] = alert_class_shadowed_77_qs; + end + + addr_hit[282]: begin + reg_rdata_next[1:0] = alert_class_shadowed_78_qs; + end + + addr_hit[283]: begin + reg_rdata_next[1:0] = alert_class_shadowed_79_qs; + end + + addr_hit[284]: begin + reg_rdata_next[1:0] = alert_class_shadowed_80_qs; + end + + addr_hit[285]: begin + reg_rdata_next[1:0] = alert_class_shadowed_81_qs; + end + + addr_hit[286]: begin + reg_rdata_next[1:0] = alert_class_shadowed_82_qs; + end + + addr_hit[287]: begin + reg_rdata_next[1:0] = alert_class_shadowed_83_qs; + end + + addr_hit[288]: begin + reg_rdata_next[1:0] = alert_class_shadowed_84_qs; + end + + addr_hit[289]: begin + reg_rdata_next[1:0] = alert_class_shadowed_85_qs; + end + + addr_hit[290]: begin + reg_rdata_next[1:0] = alert_class_shadowed_86_qs; + end + + addr_hit[291]: begin + reg_rdata_next[1:0] = alert_class_shadowed_87_qs; + end + + addr_hit[292]: begin + reg_rdata_next[1:0] = alert_class_shadowed_88_qs; + end + + addr_hit[293]: begin + reg_rdata_next[1:0] = alert_class_shadowed_89_qs; + end + + addr_hit[294]: begin + reg_rdata_next[1:0] = alert_class_shadowed_90_qs; + end + + addr_hit[295]: begin + reg_rdata_next[1:0] = alert_class_shadowed_91_qs; + end + + addr_hit[296]: begin + reg_rdata_next[1:0] = alert_class_shadowed_92_qs; + end + + addr_hit[297]: begin + reg_rdata_next[1:0] = alert_class_shadowed_93_qs; + end + + addr_hit[298]: begin + reg_rdata_next[1:0] = alert_class_shadowed_94_qs; + end + + addr_hit[299]: begin + reg_rdata_next[1:0] = alert_class_shadowed_95_qs; + end + + addr_hit[300]: begin + reg_rdata_next[1:0] = alert_class_shadowed_96_qs; + end + + addr_hit[301]: begin + reg_rdata_next[1:0] = alert_class_shadowed_97_qs; + end + + addr_hit[302]: begin + reg_rdata_next[1:0] = alert_class_shadowed_98_qs; + end + + addr_hit[303]: begin + reg_rdata_next[0] = alert_cause_0_qs; + end + + addr_hit[304]: begin + reg_rdata_next[0] = alert_cause_1_qs; + end + + addr_hit[305]: begin + reg_rdata_next[0] = alert_cause_2_qs; + end + + addr_hit[306]: begin + reg_rdata_next[0] = alert_cause_3_qs; + end + + addr_hit[307]: begin + reg_rdata_next[0] = alert_cause_4_qs; + end + + addr_hit[308]: begin + reg_rdata_next[0] = alert_cause_5_qs; + end + + addr_hit[309]: begin + reg_rdata_next[0] = alert_cause_6_qs; + end + + addr_hit[310]: begin + reg_rdata_next[0] = alert_cause_7_qs; + end + + addr_hit[311]: begin + reg_rdata_next[0] = alert_cause_8_qs; + end + + addr_hit[312]: begin + reg_rdata_next[0] = alert_cause_9_qs; + end + + addr_hit[313]: begin + reg_rdata_next[0] = alert_cause_10_qs; + end + + addr_hit[314]: begin + reg_rdata_next[0] = alert_cause_11_qs; + end + + addr_hit[315]: begin + reg_rdata_next[0] = alert_cause_12_qs; + end + + addr_hit[316]: begin + reg_rdata_next[0] = alert_cause_13_qs; + end + + addr_hit[317]: begin + reg_rdata_next[0] = alert_cause_14_qs; + end + + addr_hit[318]: begin + reg_rdata_next[0] = alert_cause_15_qs; + end + + addr_hit[319]: begin + reg_rdata_next[0] = alert_cause_16_qs; + end + + addr_hit[320]: begin + reg_rdata_next[0] = alert_cause_17_qs; + end + + addr_hit[321]: begin + reg_rdata_next[0] = alert_cause_18_qs; + end + + addr_hit[322]: begin + reg_rdata_next[0] = alert_cause_19_qs; + end + + addr_hit[323]: begin + reg_rdata_next[0] = alert_cause_20_qs; + end + + addr_hit[324]: begin + reg_rdata_next[0] = alert_cause_21_qs; + end + + addr_hit[325]: begin + reg_rdata_next[0] = alert_cause_22_qs; + end + + addr_hit[326]: begin + reg_rdata_next[0] = alert_cause_23_qs; + end + + addr_hit[327]: begin + reg_rdata_next[0] = alert_cause_24_qs; + end + + addr_hit[328]: begin + reg_rdata_next[0] = alert_cause_25_qs; + end + + addr_hit[329]: begin + reg_rdata_next[0] = alert_cause_26_qs; + end + + addr_hit[330]: begin + reg_rdata_next[0] = alert_cause_27_qs; + end + + addr_hit[331]: begin + reg_rdata_next[0] = alert_cause_28_qs; + end + + addr_hit[332]: begin + reg_rdata_next[0] = alert_cause_29_qs; + end + + addr_hit[333]: begin + reg_rdata_next[0] = alert_cause_30_qs; + end + + addr_hit[334]: begin + reg_rdata_next[0] = alert_cause_31_qs; + end + + addr_hit[335]: begin + reg_rdata_next[0] = alert_cause_32_qs; + end + + addr_hit[336]: begin + reg_rdata_next[0] = alert_cause_33_qs; + end + + addr_hit[337]: begin + reg_rdata_next[0] = alert_cause_34_qs; + end + + addr_hit[338]: begin + reg_rdata_next[0] = alert_cause_35_qs; + end + + addr_hit[339]: begin + reg_rdata_next[0] = alert_cause_36_qs; + end + + addr_hit[340]: begin + reg_rdata_next[0] = alert_cause_37_qs; + end + + addr_hit[341]: begin + reg_rdata_next[0] = alert_cause_38_qs; + end + + addr_hit[342]: begin + reg_rdata_next[0] = alert_cause_39_qs; + end + + addr_hit[343]: begin + reg_rdata_next[0] = alert_cause_40_qs; + end + + addr_hit[344]: begin + reg_rdata_next[0] = alert_cause_41_qs; + end + + addr_hit[345]: begin + reg_rdata_next[0] = alert_cause_42_qs; + end + + addr_hit[346]: begin + reg_rdata_next[0] = alert_cause_43_qs; + end + + addr_hit[347]: begin + reg_rdata_next[0] = alert_cause_44_qs; + end + + addr_hit[348]: begin + reg_rdata_next[0] = alert_cause_45_qs; + end + + addr_hit[349]: begin + reg_rdata_next[0] = alert_cause_46_qs; + end + + addr_hit[350]: begin + reg_rdata_next[0] = alert_cause_47_qs; + end + + addr_hit[351]: begin + reg_rdata_next[0] = alert_cause_48_qs; + end + + addr_hit[352]: begin + reg_rdata_next[0] = alert_cause_49_qs; + end + + addr_hit[353]: begin + reg_rdata_next[0] = alert_cause_50_qs; + end + + addr_hit[354]: begin + reg_rdata_next[0] = alert_cause_51_qs; + end + + addr_hit[355]: begin + reg_rdata_next[0] = alert_cause_52_qs; + end + + addr_hit[356]: begin + reg_rdata_next[0] = alert_cause_53_qs; + end + + addr_hit[357]: begin + reg_rdata_next[0] = alert_cause_54_qs; + end + + addr_hit[358]: begin + reg_rdata_next[0] = alert_cause_55_qs; + end + + addr_hit[359]: begin + reg_rdata_next[0] = alert_cause_56_qs; + end + + addr_hit[360]: begin + reg_rdata_next[0] = alert_cause_57_qs; + end + + addr_hit[361]: begin + reg_rdata_next[0] = alert_cause_58_qs; + end + + addr_hit[362]: begin + reg_rdata_next[0] = alert_cause_59_qs; + end + + addr_hit[363]: begin + reg_rdata_next[0] = alert_cause_60_qs; + end + + addr_hit[364]: begin + reg_rdata_next[0] = alert_cause_61_qs; + end + + addr_hit[365]: begin + reg_rdata_next[0] = alert_cause_62_qs; + end + + addr_hit[366]: begin + reg_rdata_next[0] = alert_cause_63_qs; + end + + addr_hit[367]: begin + reg_rdata_next[0] = alert_cause_64_qs; + end + + addr_hit[368]: begin + reg_rdata_next[0] = alert_cause_65_qs; + end + + addr_hit[369]: begin + reg_rdata_next[0] = alert_cause_66_qs; + end + + addr_hit[370]: begin + reg_rdata_next[0] = alert_cause_67_qs; + end + + addr_hit[371]: begin + reg_rdata_next[0] = alert_cause_68_qs; + end + + addr_hit[372]: begin + reg_rdata_next[0] = alert_cause_69_qs; + end + + addr_hit[373]: begin + reg_rdata_next[0] = alert_cause_70_qs; + end + + addr_hit[374]: begin + reg_rdata_next[0] = alert_cause_71_qs; + end + + addr_hit[375]: begin + reg_rdata_next[0] = alert_cause_72_qs; + end + + addr_hit[376]: begin + reg_rdata_next[0] = alert_cause_73_qs; + end + + addr_hit[377]: begin + reg_rdata_next[0] = alert_cause_74_qs; + end + + addr_hit[378]: begin + reg_rdata_next[0] = alert_cause_75_qs; + end + + addr_hit[379]: begin + reg_rdata_next[0] = alert_cause_76_qs; + end + + addr_hit[380]: begin + reg_rdata_next[0] = alert_cause_77_qs; + end + + addr_hit[381]: begin + reg_rdata_next[0] = alert_cause_78_qs; + end + + addr_hit[382]: begin + reg_rdata_next[0] = alert_cause_79_qs; + end + + addr_hit[383]: begin + reg_rdata_next[0] = alert_cause_80_qs; + end + + addr_hit[384]: begin + reg_rdata_next[0] = alert_cause_81_qs; + end + + addr_hit[385]: begin + reg_rdata_next[0] = alert_cause_82_qs; + end + + addr_hit[386]: begin + reg_rdata_next[0] = alert_cause_83_qs; + end + + addr_hit[387]: begin + reg_rdata_next[0] = alert_cause_84_qs; + end + + addr_hit[388]: begin + reg_rdata_next[0] = alert_cause_85_qs; + end + + addr_hit[389]: begin + reg_rdata_next[0] = alert_cause_86_qs; + end + + addr_hit[390]: begin + reg_rdata_next[0] = alert_cause_87_qs; + end + + addr_hit[391]: begin + reg_rdata_next[0] = alert_cause_88_qs; + end + + addr_hit[392]: begin + reg_rdata_next[0] = alert_cause_89_qs; + end + + addr_hit[393]: begin + reg_rdata_next[0] = alert_cause_90_qs; + end + + addr_hit[394]: begin + reg_rdata_next[0] = alert_cause_91_qs; + end + + addr_hit[395]: begin + reg_rdata_next[0] = alert_cause_92_qs; + end + + addr_hit[396]: begin + reg_rdata_next[0] = alert_cause_93_qs; + end + + addr_hit[397]: begin + reg_rdata_next[0] = alert_cause_94_qs; + end + + addr_hit[398]: begin + reg_rdata_next[0] = alert_cause_95_qs; + end + + addr_hit[399]: begin + reg_rdata_next[0] = alert_cause_96_qs; + end + + addr_hit[400]: begin + reg_rdata_next[0] = alert_cause_97_qs; + end + + addr_hit[401]: begin + reg_rdata_next[0] = alert_cause_98_qs; + end + + addr_hit[402]: begin + reg_rdata_next[0] = loc_alert_regwen_0_qs; + end + + addr_hit[403]: begin + reg_rdata_next[0] = loc_alert_regwen_1_qs; + end + + addr_hit[404]: begin + reg_rdata_next[0] = loc_alert_regwen_2_qs; + end + + addr_hit[405]: begin + reg_rdata_next[0] = loc_alert_regwen_3_qs; + end + + addr_hit[406]: begin + reg_rdata_next[0] = loc_alert_regwen_4_qs; + end + + addr_hit[407]: begin + reg_rdata_next[0] = loc_alert_regwen_5_qs; + end + + addr_hit[408]: begin + reg_rdata_next[0] = loc_alert_regwen_6_qs; + end + + addr_hit[409]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_0_qs; + end + + addr_hit[410]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_1_qs; + end + + addr_hit[411]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_2_qs; + end + + addr_hit[412]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_3_qs; + end + + addr_hit[413]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_4_qs; + end + + addr_hit[414]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_5_qs; + end + + addr_hit[415]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_6_qs; + end + + addr_hit[416]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs; + end + + addr_hit[417]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs; + end + + addr_hit[418]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs; + end + + addr_hit[419]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs; + end + + addr_hit[420]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs; + end + + addr_hit[421]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs; + end + + addr_hit[422]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs; + end + + addr_hit[423]: begin + reg_rdata_next[0] = loc_alert_cause_0_qs; + end + + addr_hit[424]: begin + reg_rdata_next[0] = loc_alert_cause_1_qs; + end + + addr_hit[425]: begin + reg_rdata_next[0] = loc_alert_cause_2_qs; + end + + addr_hit[426]: begin + reg_rdata_next[0] = loc_alert_cause_3_qs; + end + + addr_hit[427]: begin + reg_rdata_next[0] = loc_alert_cause_4_qs; + end + + addr_hit[428]: begin + reg_rdata_next[0] = loc_alert_cause_5_qs; + end + + addr_hit[429]: begin + reg_rdata_next[0] = loc_alert_cause_6_qs; + end + + addr_hit[430]: begin + reg_rdata_next[0] = classa_regwen_qs; + end + + addr_hit[431]: begin + reg_rdata_next[0] = classa_ctrl_shadowed_en_qs; + reg_rdata_next[1] = classa_ctrl_shadowed_lock_qs; + reg_rdata_next[2] = classa_ctrl_shadowed_en_e0_qs; + reg_rdata_next[3] = classa_ctrl_shadowed_en_e1_qs; + reg_rdata_next[4] = classa_ctrl_shadowed_en_e2_qs; + reg_rdata_next[5] = classa_ctrl_shadowed_en_e3_qs; + reg_rdata_next[7:6] = classa_ctrl_shadowed_map_e0_qs; + reg_rdata_next[9:8] = classa_ctrl_shadowed_map_e1_qs; + reg_rdata_next[11:10] = classa_ctrl_shadowed_map_e2_qs; + reg_rdata_next[13:12] = classa_ctrl_shadowed_map_e3_qs; + end + + addr_hit[432]: begin + reg_rdata_next[0] = classa_clr_regwen_qs; + end + + addr_hit[433]: begin + reg_rdata_next[0] = classa_clr_shadowed_qs; + end + + addr_hit[434]: begin + reg_rdata_next[15:0] = classa_accum_cnt_qs; + end + + addr_hit[435]: begin + reg_rdata_next[15:0] = classa_accum_thresh_shadowed_qs; + end + + addr_hit[436]: begin + reg_rdata_next[31:0] = classa_timeout_cyc_shadowed_qs; + end + + addr_hit[437]: begin + reg_rdata_next[1:0] = classa_crashdump_trigger_shadowed_qs; + end + + addr_hit[438]: begin + reg_rdata_next[31:0] = classa_phase0_cyc_shadowed_qs; + end + + addr_hit[439]: begin + reg_rdata_next[31:0] = classa_phase1_cyc_shadowed_qs; + end + + addr_hit[440]: begin + reg_rdata_next[31:0] = classa_phase2_cyc_shadowed_qs; + end + + addr_hit[441]: begin + reg_rdata_next[31:0] = classa_phase3_cyc_shadowed_qs; + end + + addr_hit[442]: begin + reg_rdata_next[31:0] = classa_esc_cnt_qs; + end + + addr_hit[443]: begin + reg_rdata_next[2:0] = classa_state_qs; + end + + addr_hit[444]: begin + reg_rdata_next[0] = classb_regwen_qs; + end + + addr_hit[445]: begin + reg_rdata_next[0] = classb_ctrl_shadowed_en_qs; + reg_rdata_next[1] = classb_ctrl_shadowed_lock_qs; + reg_rdata_next[2] = classb_ctrl_shadowed_en_e0_qs; + reg_rdata_next[3] = classb_ctrl_shadowed_en_e1_qs; + reg_rdata_next[4] = classb_ctrl_shadowed_en_e2_qs; + reg_rdata_next[5] = classb_ctrl_shadowed_en_e3_qs; + reg_rdata_next[7:6] = classb_ctrl_shadowed_map_e0_qs; + reg_rdata_next[9:8] = classb_ctrl_shadowed_map_e1_qs; + reg_rdata_next[11:10] = classb_ctrl_shadowed_map_e2_qs; + reg_rdata_next[13:12] = classb_ctrl_shadowed_map_e3_qs; + end + + addr_hit[446]: begin + reg_rdata_next[0] = classb_clr_regwen_qs; + end + + addr_hit[447]: begin + reg_rdata_next[0] = classb_clr_shadowed_qs; + end + + addr_hit[448]: begin + reg_rdata_next[15:0] = classb_accum_cnt_qs; + end + + addr_hit[449]: begin + reg_rdata_next[15:0] = classb_accum_thresh_shadowed_qs; + end + + addr_hit[450]: begin + reg_rdata_next[31:0] = classb_timeout_cyc_shadowed_qs; + end + + addr_hit[451]: begin + reg_rdata_next[1:0] = classb_crashdump_trigger_shadowed_qs; + end + + addr_hit[452]: begin + reg_rdata_next[31:0] = classb_phase0_cyc_shadowed_qs; + end + + addr_hit[453]: begin + reg_rdata_next[31:0] = classb_phase1_cyc_shadowed_qs; + end + + addr_hit[454]: begin + reg_rdata_next[31:0] = classb_phase2_cyc_shadowed_qs; + end + + addr_hit[455]: begin + reg_rdata_next[31:0] = classb_phase3_cyc_shadowed_qs; + end + + addr_hit[456]: begin + reg_rdata_next[31:0] = classb_esc_cnt_qs; + end + + addr_hit[457]: begin + reg_rdata_next[2:0] = classb_state_qs; + end + + addr_hit[458]: begin + reg_rdata_next[0] = classc_regwen_qs; + end + + addr_hit[459]: begin + reg_rdata_next[0] = classc_ctrl_shadowed_en_qs; + reg_rdata_next[1] = classc_ctrl_shadowed_lock_qs; + reg_rdata_next[2] = classc_ctrl_shadowed_en_e0_qs; + reg_rdata_next[3] = classc_ctrl_shadowed_en_e1_qs; + reg_rdata_next[4] = classc_ctrl_shadowed_en_e2_qs; + reg_rdata_next[5] = classc_ctrl_shadowed_en_e3_qs; + reg_rdata_next[7:6] = classc_ctrl_shadowed_map_e0_qs; + reg_rdata_next[9:8] = classc_ctrl_shadowed_map_e1_qs; + reg_rdata_next[11:10] = classc_ctrl_shadowed_map_e2_qs; + reg_rdata_next[13:12] = classc_ctrl_shadowed_map_e3_qs; + end + + addr_hit[460]: begin + reg_rdata_next[0] = classc_clr_regwen_qs; + end + + addr_hit[461]: begin + reg_rdata_next[0] = classc_clr_shadowed_qs; + end + + addr_hit[462]: begin + reg_rdata_next[15:0] = classc_accum_cnt_qs; + end + + addr_hit[463]: begin + reg_rdata_next[15:0] = classc_accum_thresh_shadowed_qs; + end + + addr_hit[464]: begin + reg_rdata_next[31:0] = classc_timeout_cyc_shadowed_qs; + end + + addr_hit[465]: begin + reg_rdata_next[1:0] = classc_crashdump_trigger_shadowed_qs; + end + + addr_hit[466]: begin + reg_rdata_next[31:0] = classc_phase0_cyc_shadowed_qs; + end + + addr_hit[467]: begin + reg_rdata_next[31:0] = classc_phase1_cyc_shadowed_qs; + end + + addr_hit[468]: begin + reg_rdata_next[31:0] = classc_phase2_cyc_shadowed_qs; + end + + addr_hit[469]: begin + reg_rdata_next[31:0] = classc_phase3_cyc_shadowed_qs; + end + + addr_hit[470]: begin + reg_rdata_next[31:0] = classc_esc_cnt_qs; + end + + addr_hit[471]: begin + reg_rdata_next[2:0] = classc_state_qs; + end + + addr_hit[472]: begin + reg_rdata_next[0] = classd_regwen_qs; + end + + addr_hit[473]: begin + reg_rdata_next[0] = classd_ctrl_shadowed_en_qs; + reg_rdata_next[1] = classd_ctrl_shadowed_lock_qs; + reg_rdata_next[2] = classd_ctrl_shadowed_en_e0_qs; + reg_rdata_next[3] = classd_ctrl_shadowed_en_e1_qs; + reg_rdata_next[4] = classd_ctrl_shadowed_en_e2_qs; + reg_rdata_next[5] = classd_ctrl_shadowed_en_e3_qs; + reg_rdata_next[7:6] = classd_ctrl_shadowed_map_e0_qs; + reg_rdata_next[9:8] = classd_ctrl_shadowed_map_e1_qs; + reg_rdata_next[11:10] = classd_ctrl_shadowed_map_e2_qs; + reg_rdata_next[13:12] = classd_ctrl_shadowed_map_e3_qs; + end + + addr_hit[474]: begin + reg_rdata_next[0] = classd_clr_regwen_qs; + end + + addr_hit[475]: begin + reg_rdata_next[0] = classd_clr_shadowed_qs; + end + + addr_hit[476]: begin + reg_rdata_next[15:0] = classd_accum_cnt_qs; + end + + addr_hit[477]: begin + reg_rdata_next[15:0] = classd_accum_thresh_shadowed_qs; + end + + addr_hit[478]: begin + reg_rdata_next[31:0] = classd_timeout_cyc_shadowed_qs; + end + + addr_hit[479]: begin + reg_rdata_next[1:0] = classd_crashdump_trigger_shadowed_qs; + end + + addr_hit[480]: begin + reg_rdata_next[31:0] = classd_phase0_cyc_shadowed_qs; + end + + addr_hit[481]: begin + reg_rdata_next[31:0] = classd_phase1_cyc_shadowed_qs; + end + + addr_hit[482]: begin + reg_rdata_next[31:0] = classd_phase2_cyc_shadowed_qs; + end + + addr_hit[483]: begin + reg_rdata_next[31:0] = classd_phase3_cyc_shadowed_qs; + end + + addr_hit[484]: begin + reg_rdata_next[31:0] = classd_esc_cnt_qs; + end + + addr_hit[485]: begin + reg_rdata_next[2:0] = classd_state_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + logic rst_done; + logic shadow_rst_done; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rst_done <= '0; + end else begin + rst_done <= 1'b1; + end + end + + always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin + if (!rst_shadowed_ni) begin + shadow_rst_done <= '0; + end else begin + shadow_rst_done <= 1'b1; + end + end + + // both shadow and normal resets have been released + assign shadow_busy = ~(rst_done & shadow_rst_done); + + // Collect up storage and update errors + assign shadowed_storage_err_o = |{ + ping_timeout_cyc_shadowed_storage_err, + ping_timer_en_shadowed_storage_err, + alert_en_shadowed_0_storage_err, + alert_en_shadowed_1_storage_err, + alert_en_shadowed_2_storage_err, + alert_en_shadowed_3_storage_err, + alert_en_shadowed_4_storage_err, + alert_en_shadowed_5_storage_err, + alert_en_shadowed_6_storage_err, + alert_en_shadowed_7_storage_err, + alert_en_shadowed_8_storage_err, + alert_en_shadowed_9_storage_err, + alert_en_shadowed_10_storage_err, + alert_en_shadowed_11_storage_err, + alert_en_shadowed_12_storage_err, + alert_en_shadowed_13_storage_err, + alert_en_shadowed_14_storage_err, + alert_en_shadowed_15_storage_err, + alert_en_shadowed_16_storage_err, + alert_en_shadowed_17_storage_err, + alert_en_shadowed_18_storage_err, + alert_en_shadowed_19_storage_err, + alert_en_shadowed_20_storage_err, + alert_en_shadowed_21_storage_err, + alert_en_shadowed_22_storage_err, + alert_en_shadowed_23_storage_err, + alert_en_shadowed_24_storage_err, + alert_en_shadowed_25_storage_err, + alert_en_shadowed_26_storage_err, + alert_en_shadowed_27_storage_err, + alert_en_shadowed_28_storage_err, + alert_en_shadowed_29_storage_err, + alert_en_shadowed_30_storage_err, + alert_en_shadowed_31_storage_err, + alert_en_shadowed_32_storage_err, + alert_en_shadowed_33_storage_err, + alert_en_shadowed_34_storage_err, + alert_en_shadowed_35_storage_err, + alert_en_shadowed_36_storage_err, + alert_en_shadowed_37_storage_err, + alert_en_shadowed_38_storage_err, + alert_en_shadowed_39_storage_err, + alert_en_shadowed_40_storage_err, + alert_en_shadowed_41_storage_err, + alert_en_shadowed_42_storage_err, + alert_en_shadowed_43_storage_err, + alert_en_shadowed_44_storage_err, + alert_en_shadowed_45_storage_err, + alert_en_shadowed_46_storage_err, + alert_en_shadowed_47_storage_err, + alert_en_shadowed_48_storage_err, + alert_en_shadowed_49_storage_err, + alert_en_shadowed_50_storage_err, + alert_en_shadowed_51_storage_err, + alert_en_shadowed_52_storage_err, + alert_en_shadowed_53_storage_err, + alert_en_shadowed_54_storage_err, + alert_en_shadowed_55_storage_err, + alert_en_shadowed_56_storage_err, + alert_en_shadowed_57_storage_err, + alert_en_shadowed_58_storage_err, + alert_en_shadowed_59_storage_err, + alert_en_shadowed_60_storage_err, + alert_en_shadowed_61_storage_err, + alert_en_shadowed_62_storage_err, + alert_en_shadowed_63_storage_err, + alert_en_shadowed_64_storage_err, + alert_en_shadowed_65_storage_err, + alert_en_shadowed_66_storage_err, + alert_en_shadowed_67_storage_err, + alert_en_shadowed_68_storage_err, + alert_en_shadowed_69_storage_err, + alert_en_shadowed_70_storage_err, + alert_en_shadowed_71_storage_err, + alert_en_shadowed_72_storage_err, + alert_en_shadowed_73_storage_err, + alert_en_shadowed_74_storage_err, + alert_en_shadowed_75_storage_err, + alert_en_shadowed_76_storage_err, + alert_en_shadowed_77_storage_err, + alert_en_shadowed_78_storage_err, + alert_en_shadowed_79_storage_err, + alert_en_shadowed_80_storage_err, + alert_en_shadowed_81_storage_err, + alert_en_shadowed_82_storage_err, + alert_en_shadowed_83_storage_err, + alert_en_shadowed_84_storage_err, + alert_en_shadowed_85_storage_err, + alert_en_shadowed_86_storage_err, + alert_en_shadowed_87_storage_err, + alert_en_shadowed_88_storage_err, + alert_en_shadowed_89_storage_err, + alert_en_shadowed_90_storage_err, + alert_en_shadowed_91_storage_err, + alert_en_shadowed_92_storage_err, + alert_en_shadowed_93_storage_err, + alert_en_shadowed_94_storage_err, + alert_en_shadowed_95_storage_err, + alert_en_shadowed_96_storage_err, + alert_en_shadowed_97_storage_err, + alert_en_shadowed_98_storage_err, + alert_class_shadowed_0_storage_err, + alert_class_shadowed_1_storage_err, + alert_class_shadowed_2_storage_err, + alert_class_shadowed_3_storage_err, + alert_class_shadowed_4_storage_err, + alert_class_shadowed_5_storage_err, + alert_class_shadowed_6_storage_err, + alert_class_shadowed_7_storage_err, + alert_class_shadowed_8_storage_err, + alert_class_shadowed_9_storage_err, + alert_class_shadowed_10_storage_err, + alert_class_shadowed_11_storage_err, + alert_class_shadowed_12_storage_err, + alert_class_shadowed_13_storage_err, + alert_class_shadowed_14_storage_err, + alert_class_shadowed_15_storage_err, + alert_class_shadowed_16_storage_err, + alert_class_shadowed_17_storage_err, + alert_class_shadowed_18_storage_err, + alert_class_shadowed_19_storage_err, + alert_class_shadowed_20_storage_err, + alert_class_shadowed_21_storage_err, + alert_class_shadowed_22_storage_err, + alert_class_shadowed_23_storage_err, + alert_class_shadowed_24_storage_err, + alert_class_shadowed_25_storage_err, + alert_class_shadowed_26_storage_err, + alert_class_shadowed_27_storage_err, + alert_class_shadowed_28_storage_err, + alert_class_shadowed_29_storage_err, + alert_class_shadowed_30_storage_err, + alert_class_shadowed_31_storage_err, + alert_class_shadowed_32_storage_err, + alert_class_shadowed_33_storage_err, + alert_class_shadowed_34_storage_err, + alert_class_shadowed_35_storage_err, + alert_class_shadowed_36_storage_err, + alert_class_shadowed_37_storage_err, + alert_class_shadowed_38_storage_err, + alert_class_shadowed_39_storage_err, + alert_class_shadowed_40_storage_err, + alert_class_shadowed_41_storage_err, + alert_class_shadowed_42_storage_err, + alert_class_shadowed_43_storage_err, + alert_class_shadowed_44_storage_err, + alert_class_shadowed_45_storage_err, + alert_class_shadowed_46_storage_err, + alert_class_shadowed_47_storage_err, + alert_class_shadowed_48_storage_err, + alert_class_shadowed_49_storage_err, + alert_class_shadowed_50_storage_err, + alert_class_shadowed_51_storage_err, + alert_class_shadowed_52_storage_err, + alert_class_shadowed_53_storage_err, + alert_class_shadowed_54_storage_err, + alert_class_shadowed_55_storage_err, + alert_class_shadowed_56_storage_err, + alert_class_shadowed_57_storage_err, + alert_class_shadowed_58_storage_err, + alert_class_shadowed_59_storage_err, + alert_class_shadowed_60_storage_err, + alert_class_shadowed_61_storage_err, + alert_class_shadowed_62_storage_err, + alert_class_shadowed_63_storage_err, + alert_class_shadowed_64_storage_err, + alert_class_shadowed_65_storage_err, + alert_class_shadowed_66_storage_err, + alert_class_shadowed_67_storage_err, + alert_class_shadowed_68_storage_err, + alert_class_shadowed_69_storage_err, + alert_class_shadowed_70_storage_err, + alert_class_shadowed_71_storage_err, + alert_class_shadowed_72_storage_err, + alert_class_shadowed_73_storage_err, + alert_class_shadowed_74_storage_err, + alert_class_shadowed_75_storage_err, + alert_class_shadowed_76_storage_err, + alert_class_shadowed_77_storage_err, + alert_class_shadowed_78_storage_err, + alert_class_shadowed_79_storage_err, + alert_class_shadowed_80_storage_err, + alert_class_shadowed_81_storage_err, + alert_class_shadowed_82_storage_err, + alert_class_shadowed_83_storage_err, + alert_class_shadowed_84_storage_err, + alert_class_shadowed_85_storage_err, + alert_class_shadowed_86_storage_err, + alert_class_shadowed_87_storage_err, + alert_class_shadowed_88_storage_err, + alert_class_shadowed_89_storage_err, + alert_class_shadowed_90_storage_err, + alert_class_shadowed_91_storage_err, + alert_class_shadowed_92_storage_err, + alert_class_shadowed_93_storage_err, + alert_class_shadowed_94_storage_err, + alert_class_shadowed_95_storage_err, + alert_class_shadowed_96_storage_err, + alert_class_shadowed_97_storage_err, + alert_class_shadowed_98_storage_err, + loc_alert_en_shadowed_0_storage_err, + loc_alert_en_shadowed_1_storage_err, + loc_alert_en_shadowed_2_storage_err, + loc_alert_en_shadowed_3_storage_err, + loc_alert_en_shadowed_4_storage_err, + loc_alert_en_shadowed_5_storage_err, + loc_alert_en_shadowed_6_storage_err, + loc_alert_class_shadowed_0_storage_err, + loc_alert_class_shadowed_1_storage_err, + loc_alert_class_shadowed_2_storage_err, + loc_alert_class_shadowed_3_storage_err, + loc_alert_class_shadowed_4_storage_err, + loc_alert_class_shadowed_5_storage_err, + loc_alert_class_shadowed_6_storage_err, + classa_ctrl_shadowed_en_storage_err, + classa_ctrl_shadowed_lock_storage_err, + classa_ctrl_shadowed_en_e0_storage_err, + classa_ctrl_shadowed_en_e1_storage_err, + classa_ctrl_shadowed_en_e2_storage_err, + classa_ctrl_shadowed_en_e3_storage_err, + classa_ctrl_shadowed_map_e0_storage_err, + classa_ctrl_shadowed_map_e1_storage_err, + classa_ctrl_shadowed_map_e2_storage_err, + classa_ctrl_shadowed_map_e3_storage_err, + classa_clr_shadowed_storage_err, + classa_accum_thresh_shadowed_storage_err, + classa_timeout_cyc_shadowed_storage_err, + classa_crashdump_trigger_shadowed_storage_err, + classa_phase0_cyc_shadowed_storage_err, + classa_phase1_cyc_shadowed_storage_err, + classa_phase2_cyc_shadowed_storage_err, + classa_phase3_cyc_shadowed_storage_err, + classb_ctrl_shadowed_en_storage_err, + classb_ctrl_shadowed_lock_storage_err, + classb_ctrl_shadowed_en_e0_storage_err, + classb_ctrl_shadowed_en_e1_storage_err, + classb_ctrl_shadowed_en_e2_storage_err, + classb_ctrl_shadowed_en_e3_storage_err, + classb_ctrl_shadowed_map_e0_storage_err, + classb_ctrl_shadowed_map_e1_storage_err, + classb_ctrl_shadowed_map_e2_storage_err, + classb_ctrl_shadowed_map_e3_storage_err, + classb_clr_shadowed_storage_err, + classb_accum_thresh_shadowed_storage_err, + classb_timeout_cyc_shadowed_storage_err, + classb_crashdump_trigger_shadowed_storage_err, + classb_phase0_cyc_shadowed_storage_err, + classb_phase1_cyc_shadowed_storage_err, + classb_phase2_cyc_shadowed_storage_err, + classb_phase3_cyc_shadowed_storage_err, + classc_ctrl_shadowed_en_storage_err, + classc_ctrl_shadowed_lock_storage_err, + classc_ctrl_shadowed_en_e0_storage_err, + classc_ctrl_shadowed_en_e1_storage_err, + classc_ctrl_shadowed_en_e2_storage_err, + classc_ctrl_shadowed_en_e3_storage_err, + classc_ctrl_shadowed_map_e0_storage_err, + classc_ctrl_shadowed_map_e1_storage_err, + classc_ctrl_shadowed_map_e2_storage_err, + classc_ctrl_shadowed_map_e3_storage_err, + classc_clr_shadowed_storage_err, + classc_accum_thresh_shadowed_storage_err, + classc_timeout_cyc_shadowed_storage_err, + classc_crashdump_trigger_shadowed_storage_err, + classc_phase0_cyc_shadowed_storage_err, + classc_phase1_cyc_shadowed_storage_err, + classc_phase2_cyc_shadowed_storage_err, + classc_phase3_cyc_shadowed_storage_err, + classd_ctrl_shadowed_en_storage_err, + classd_ctrl_shadowed_lock_storage_err, + classd_ctrl_shadowed_en_e0_storage_err, + classd_ctrl_shadowed_en_e1_storage_err, + classd_ctrl_shadowed_en_e2_storage_err, + classd_ctrl_shadowed_en_e3_storage_err, + classd_ctrl_shadowed_map_e0_storage_err, + classd_ctrl_shadowed_map_e1_storage_err, + classd_ctrl_shadowed_map_e2_storage_err, + classd_ctrl_shadowed_map_e3_storage_err, + classd_clr_shadowed_storage_err, + classd_accum_thresh_shadowed_storage_err, + classd_timeout_cyc_shadowed_storage_err, + classd_crashdump_trigger_shadowed_storage_err, + classd_phase0_cyc_shadowed_storage_err, + classd_phase1_cyc_shadowed_storage_err, + classd_phase2_cyc_shadowed_storage_err, + classd_phase3_cyc_shadowed_storage_err + }; + assign shadowed_update_err_o = |{ + ping_timeout_cyc_shadowed_update_err, + ping_timer_en_shadowed_update_err, + alert_en_shadowed_0_update_err, + alert_en_shadowed_1_update_err, + alert_en_shadowed_2_update_err, + alert_en_shadowed_3_update_err, + alert_en_shadowed_4_update_err, + alert_en_shadowed_5_update_err, + alert_en_shadowed_6_update_err, + alert_en_shadowed_7_update_err, + alert_en_shadowed_8_update_err, + alert_en_shadowed_9_update_err, + alert_en_shadowed_10_update_err, + alert_en_shadowed_11_update_err, + alert_en_shadowed_12_update_err, + alert_en_shadowed_13_update_err, + alert_en_shadowed_14_update_err, + alert_en_shadowed_15_update_err, + alert_en_shadowed_16_update_err, + alert_en_shadowed_17_update_err, + alert_en_shadowed_18_update_err, + alert_en_shadowed_19_update_err, + alert_en_shadowed_20_update_err, + alert_en_shadowed_21_update_err, + alert_en_shadowed_22_update_err, + alert_en_shadowed_23_update_err, + alert_en_shadowed_24_update_err, + alert_en_shadowed_25_update_err, + alert_en_shadowed_26_update_err, + alert_en_shadowed_27_update_err, + alert_en_shadowed_28_update_err, + alert_en_shadowed_29_update_err, + alert_en_shadowed_30_update_err, + alert_en_shadowed_31_update_err, + alert_en_shadowed_32_update_err, + alert_en_shadowed_33_update_err, + alert_en_shadowed_34_update_err, + alert_en_shadowed_35_update_err, + alert_en_shadowed_36_update_err, + alert_en_shadowed_37_update_err, + alert_en_shadowed_38_update_err, + alert_en_shadowed_39_update_err, + alert_en_shadowed_40_update_err, + alert_en_shadowed_41_update_err, + alert_en_shadowed_42_update_err, + alert_en_shadowed_43_update_err, + alert_en_shadowed_44_update_err, + alert_en_shadowed_45_update_err, + alert_en_shadowed_46_update_err, + alert_en_shadowed_47_update_err, + alert_en_shadowed_48_update_err, + alert_en_shadowed_49_update_err, + alert_en_shadowed_50_update_err, + alert_en_shadowed_51_update_err, + alert_en_shadowed_52_update_err, + alert_en_shadowed_53_update_err, + alert_en_shadowed_54_update_err, + alert_en_shadowed_55_update_err, + alert_en_shadowed_56_update_err, + alert_en_shadowed_57_update_err, + alert_en_shadowed_58_update_err, + alert_en_shadowed_59_update_err, + alert_en_shadowed_60_update_err, + alert_en_shadowed_61_update_err, + alert_en_shadowed_62_update_err, + alert_en_shadowed_63_update_err, + alert_en_shadowed_64_update_err, + alert_en_shadowed_65_update_err, + alert_en_shadowed_66_update_err, + alert_en_shadowed_67_update_err, + alert_en_shadowed_68_update_err, + alert_en_shadowed_69_update_err, + alert_en_shadowed_70_update_err, + alert_en_shadowed_71_update_err, + alert_en_shadowed_72_update_err, + alert_en_shadowed_73_update_err, + alert_en_shadowed_74_update_err, + alert_en_shadowed_75_update_err, + alert_en_shadowed_76_update_err, + alert_en_shadowed_77_update_err, + alert_en_shadowed_78_update_err, + alert_en_shadowed_79_update_err, + alert_en_shadowed_80_update_err, + alert_en_shadowed_81_update_err, + alert_en_shadowed_82_update_err, + alert_en_shadowed_83_update_err, + alert_en_shadowed_84_update_err, + alert_en_shadowed_85_update_err, + alert_en_shadowed_86_update_err, + alert_en_shadowed_87_update_err, + alert_en_shadowed_88_update_err, + alert_en_shadowed_89_update_err, + alert_en_shadowed_90_update_err, + alert_en_shadowed_91_update_err, + alert_en_shadowed_92_update_err, + alert_en_shadowed_93_update_err, + alert_en_shadowed_94_update_err, + alert_en_shadowed_95_update_err, + alert_en_shadowed_96_update_err, + alert_en_shadowed_97_update_err, + alert_en_shadowed_98_update_err, + alert_class_shadowed_0_update_err, + alert_class_shadowed_1_update_err, + alert_class_shadowed_2_update_err, + alert_class_shadowed_3_update_err, + alert_class_shadowed_4_update_err, + alert_class_shadowed_5_update_err, + alert_class_shadowed_6_update_err, + alert_class_shadowed_7_update_err, + alert_class_shadowed_8_update_err, + alert_class_shadowed_9_update_err, + alert_class_shadowed_10_update_err, + alert_class_shadowed_11_update_err, + alert_class_shadowed_12_update_err, + alert_class_shadowed_13_update_err, + alert_class_shadowed_14_update_err, + alert_class_shadowed_15_update_err, + alert_class_shadowed_16_update_err, + alert_class_shadowed_17_update_err, + alert_class_shadowed_18_update_err, + alert_class_shadowed_19_update_err, + alert_class_shadowed_20_update_err, + alert_class_shadowed_21_update_err, + alert_class_shadowed_22_update_err, + alert_class_shadowed_23_update_err, + alert_class_shadowed_24_update_err, + alert_class_shadowed_25_update_err, + alert_class_shadowed_26_update_err, + alert_class_shadowed_27_update_err, + alert_class_shadowed_28_update_err, + alert_class_shadowed_29_update_err, + alert_class_shadowed_30_update_err, + alert_class_shadowed_31_update_err, + alert_class_shadowed_32_update_err, + alert_class_shadowed_33_update_err, + alert_class_shadowed_34_update_err, + alert_class_shadowed_35_update_err, + alert_class_shadowed_36_update_err, + alert_class_shadowed_37_update_err, + alert_class_shadowed_38_update_err, + alert_class_shadowed_39_update_err, + alert_class_shadowed_40_update_err, + alert_class_shadowed_41_update_err, + alert_class_shadowed_42_update_err, + alert_class_shadowed_43_update_err, + alert_class_shadowed_44_update_err, + alert_class_shadowed_45_update_err, + alert_class_shadowed_46_update_err, + alert_class_shadowed_47_update_err, + alert_class_shadowed_48_update_err, + alert_class_shadowed_49_update_err, + alert_class_shadowed_50_update_err, + alert_class_shadowed_51_update_err, + alert_class_shadowed_52_update_err, + alert_class_shadowed_53_update_err, + alert_class_shadowed_54_update_err, + alert_class_shadowed_55_update_err, + alert_class_shadowed_56_update_err, + alert_class_shadowed_57_update_err, + alert_class_shadowed_58_update_err, + alert_class_shadowed_59_update_err, + alert_class_shadowed_60_update_err, + alert_class_shadowed_61_update_err, + alert_class_shadowed_62_update_err, + alert_class_shadowed_63_update_err, + alert_class_shadowed_64_update_err, + alert_class_shadowed_65_update_err, + alert_class_shadowed_66_update_err, + alert_class_shadowed_67_update_err, + alert_class_shadowed_68_update_err, + alert_class_shadowed_69_update_err, + alert_class_shadowed_70_update_err, + alert_class_shadowed_71_update_err, + alert_class_shadowed_72_update_err, + alert_class_shadowed_73_update_err, + alert_class_shadowed_74_update_err, + alert_class_shadowed_75_update_err, + alert_class_shadowed_76_update_err, + alert_class_shadowed_77_update_err, + alert_class_shadowed_78_update_err, + alert_class_shadowed_79_update_err, + alert_class_shadowed_80_update_err, + alert_class_shadowed_81_update_err, + alert_class_shadowed_82_update_err, + alert_class_shadowed_83_update_err, + alert_class_shadowed_84_update_err, + alert_class_shadowed_85_update_err, + alert_class_shadowed_86_update_err, + alert_class_shadowed_87_update_err, + alert_class_shadowed_88_update_err, + alert_class_shadowed_89_update_err, + alert_class_shadowed_90_update_err, + alert_class_shadowed_91_update_err, + alert_class_shadowed_92_update_err, + alert_class_shadowed_93_update_err, + alert_class_shadowed_94_update_err, + alert_class_shadowed_95_update_err, + alert_class_shadowed_96_update_err, + alert_class_shadowed_97_update_err, + alert_class_shadowed_98_update_err, + loc_alert_en_shadowed_0_update_err, + loc_alert_en_shadowed_1_update_err, + loc_alert_en_shadowed_2_update_err, + loc_alert_en_shadowed_3_update_err, + loc_alert_en_shadowed_4_update_err, + loc_alert_en_shadowed_5_update_err, + loc_alert_en_shadowed_6_update_err, + loc_alert_class_shadowed_0_update_err, + loc_alert_class_shadowed_1_update_err, + loc_alert_class_shadowed_2_update_err, + loc_alert_class_shadowed_3_update_err, + loc_alert_class_shadowed_4_update_err, + loc_alert_class_shadowed_5_update_err, + loc_alert_class_shadowed_6_update_err, + classa_ctrl_shadowed_en_update_err, + classa_ctrl_shadowed_lock_update_err, + classa_ctrl_shadowed_en_e0_update_err, + classa_ctrl_shadowed_en_e1_update_err, + classa_ctrl_shadowed_en_e2_update_err, + classa_ctrl_shadowed_en_e3_update_err, + classa_ctrl_shadowed_map_e0_update_err, + classa_ctrl_shadowed_map_e1_update_err, + classa_ctrl_shadowed_map_e2_update_err, + classa_ctrl_shadowed_map_e3_update_err, + classa_clr_shadowed_update_err, + classa_accum_thresh_shadowed_update_err, + classa_timeout_cyc_shadowed_update_err, + classa_crashdump_trigger_shadowed_update_err, + classa_phase0_cyc_shadowed_update_err, + classa_phase1_cyc_shadowed_update_err, + classa_phase2_cyc_shadowed_update_err, + classa_phase3_cyc_shadowed_update_err, + classb_ctrl_shadowed_en_update_err, + classb_ctrl_shadowed_lock_update_err, + classb_ctrl_shadowed_en_e0_update_err, + classb_ctrl_shadowed_en_e1_update_err, + classb_ctrl_shadowed_en_e2_update_err, + classb_ctrl_shadowed_en_e3_update_err, + classb_ctrl_shadowed_map_e0_update_err, + classb_ctrl_shadowed_map_e1_update_err, + classb_ctrl_shadowed_map_e2_update_err, + classb_ctrl_shadowed_map_e3_update_err, + classb_clr_shadowed_update_err, + classb_accum_thresh_shadowed_update_err, + classb_timeout_cyc_shadowed_update_err, + classb_crashdump_trigger_shadowed_update_err, + classb_phase0_cyc_shadowed_update_err, + classb_phase1_cyc_shadowed_update_err, + classb_phase2_cyc_shadowed_update_err, + classb_phase3_cyc_shadowed_update_err, + classc_ctrl_shadowed_en_update_err, + classc_ctrl_shadowed_lock_update_err, + classc_ctrl_shadowed_en_e0_update_err, + classc_ctrl_shadowed_en_e1_update_err, + classc_ctrl_shadowed_en_e2_update_err, + classc_ctrl_shadowed_en_e3_update_err, + classc_ctrl_shadowed_map_e0_update_err, + classc_ctrl_shadowed_map_e1_update_err, + classc_ctrl_shadowed_map_e2_update_err, + classc_ctrl_shadowed_map_e3_update_err, + classc_clr_shadowed_update_err, + classc_accum_thresh_shadowed_update_err, + classc_timeout_cyc_shadowed_update_err, + classc_crashdump_trigger_shadowed_update_err, + classc_phase0_cyc_shadowed_update_err, + classc_phase1_cyc_shadowed_update_err, + classc_phase2_cyc_shadowed_update_err, + classc_phase3_cyc_shadowed_update_err, + classd_ctrl_shadowed_en_update_err, + classd_ctrl_shadowed_lock_update_err, + classd_ctrl_shadowed_en_e0_update_err, + classd_ctrl_shadowed_en_e1_update_err, + classd_ctrl_shadowed_en_e2_update_err, + classd_ctrl_shadowed_en_e3_update_err, + classd_ctrl_shadowed_map_e0_update_err, + classd_ctrl_shadowed_map_e1_update_err, + classd_ctrl_shadowed_map_e2_update_err, + classd_ctrl_shadowed_map_e3_update_err, + classd_clr_shadowed_update_err, + classd_accum_thresh_shadowed_update_err, + classd_timeout_cyc_shadowed_update_err, + classd_crashdump_trigger_shadowed_update_err, + classd_phase0_cyc_shadowed_update_err, + classd_phase1_cyc_shadowed_update_err, + classd_phase2_cyc_shadowed_update_err, + classd_phase3_cyc_shadowed_update_err + }; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_reg_wrap.sv b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_reg_wrap.sv new file mode 100644 index 0000000000000..dede5d62239f4 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_handler_reg_wrap.sv @@ -0,0 +1,360 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Breakout / remapping wrapper for register file. + +module alert_handler_reg_wrap import alert_pkg::*; ( + input clk_i, + input rst_ni, + input rst_shadowed_ni, + // Bus Interface (device) + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // interrupt + output logic [N_CLASSES-1:0] irq_o, + // State information for HW crashdump + input [N_CLASSES-1:0] latch_crashdump_i, + output alert_crashdump_t crashdump_o, + // hw2reg + input hw2reg_wrap_t hw2reg_wrap, + // reg2hw + output reg2hw_wrap_t reg2hw_wrap, + // bus integrity alert + output logic fatal_integ_alert_o +); + + + ////////////////// + // reg instance // + ////////////////// + + logic [N_CLASSES-1:0] class_autolock_en; + alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw; + alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg; + + alert_handler_reg_top u_reg ( + .clk_i, + .rst_ni, + .rst_shadowed_ni, + .tl_i, + .tl_o, + .reg2hw, + .hw2reg, + .shadowed_storage_err_o(reg2hw_wrap.shadowed_err_storage), + .shadowed_update_err_o(reg2hw_wrap.shadowed_err_update), + .intg_err_o(fatal_integ_alert_o) + ); + + //////////////// + // interrupts // + //////////////// + + prim_intr_hw #( + .Width(1) + ) u_irq_classa ( + .clk_i, + .rst_ni, + .event_intr_i ( hw2reg_wrap.class_trig[0] ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classa.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.classa.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classa.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.classa.q ), + .hw2reg_intr_state_de_o ( hw2reg.intr_state.classa.de ), + .hw2reg_intr_state_d_o ( hw2reg.intr_state.classa.d ), + .intr_o ( irq_o[0] ) + ); + + prim_intr_hw #( + .Width(1) + ) u_irq_classb ( + .clk_i, + .rst_ni, + .event_intr_i ( hw2reg_wrap.class_trig[1] ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classb.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.classb.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classb.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.classb.q ), + .hw2reg_intr_state_de_o ( hw2reg.intr_state.classb.de ), + .hw2reg_intr_state_d_o ( hw2reg.intr_state.classb.d ), + .intr_o ( irq_o[1] ) + ); + + prim_intr_hw #( + .Width(1) + ) u_irq_classc ( + .clk_i, + .rst_ni, + .event_intr_i ( hw2reg_wrap.class_trig[2] ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classc.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.classc.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classc.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.classc.q ), + .hw2reg_intr_state_de_o ( hw2reg.intr_state.classc.de ), + .hw2reg_intr_state_d_o ( hw2reg.intr_state.classc.d ), + .intr_o ( irq_o[2] ) + ); + + prim_intr_hw #( + .Width(1) + ) u_irq_classd ( + .clk_i, + .rst_ni, + .event_intr_i ( hw2reg_wrap.class_trig[3] ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classd.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.classd.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classd.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.classd.q ), + .hw2reg_intr_state_de_o ( hw2reg.intr_state.classd.de ), + .hw2reg_intr_state_d_o ( hw2reg.intr_state.classd.d ), + .intr_o ( irq_o[3] ) + ); + + ///////////////////// + // hw2reg mappings // + ///////////////////// + + // if an alert is enabled and it fires, + // we have to set the corresponding cause bit + for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_cause + assign hw2reg.alert_cause[k].d = 1'b1; + assign hw2reg.alert_cause[k].de = reg2hw.alert_cause[k].q | + hw2reg_wrap.alert_cause[k]; + end + + // if a local alert is enabled and it fires, + // we have to set the corresponding cause bit + for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_cause + assign hw2reg.loc_alert_cause[k].d = 1'b1; + assign hw2reg.loc_alert_cause[k].de = reg2hw.loc_alert_cause[k].q | + hw2reg_wrap.loc_alert_cause[k]; + end + + // ping timeout in cycles + // autolock can clear these regs automatically upon entering escalation + // note: the class must be activated for this to occur + assign { hw2reg.classd_clr_regwen.d, + hw2reg.classc_clr_regwen.d, + hw2reg.classb_clr_regwen.d, + hw2reg.classa_clr_regwen.d } = '0; + + assign { hw2reg.classd_clr_regwen.de, + hw2reg.classc_clr_regwen.de, + hw2reg.classb_clr_regwen.de, + hw2reg.classa_clr_regwen.de } = hw2reg_wrap.class_esc_trig & + class_autolock_en & + reg2hw_wrap.class_en; + + // current accumulator counts + assign { hw2reg.classd_accum_cnt.d, + hw2reg.classc_accum_cnt.d, + hw2reg.classb_accum_cnt.d, + hw2reg.classa_accum_cnt.d } = hw2reg_wrap.class_accum_cnt; + + // current accumulator counts + assign { hw2reg.classd_esc_cnt.d, + hw2reg.classc_esc_cnt.d, + hw2reg.classb_esc_cnt.d, + hw2reg.classa_esc_cnt.d } = hw2reg_wrap.class_esc_cnt; + + // current accumulator counts + assign { hw2reg.classd_state.d, + hw2reg.classc_state.d, + hw2reg.classb_state.d, + hw2reg.classa_state.d } = hw2reg_wrap.class_esc_state; + + ///////////////////// + // reg2hw mappings // + ///////////////////// + + // config register lock + assign reg2hw_wrap.ping_enable = reg2hw.ping_timer_en_shadowed.q; + + // alert enable and class assignments + for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_en_class + // we only ping enabled alerts that are locked + assign reg2hw_wrap.alert_ping_en[k] = reg2hw.alert_en_shadowed[k].q & + ~reg2hw.alert_regwen[k].q; + assign reg2hw_wrap.alert_en[k] = reg2hw.alert_en_shadowed[k].q; + assign reg2hw_wrap.alert_class[k] = reg2hw.alert_class_shadowed[k].q; + end + + // local alert enable and class assignments + for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_en_class + assign reg2hw_wrap.loc_alert_en[k] = reg2hw.loc_alert_en_shadowed[k].q; + assign reg2hw_wrap.loc_alert_class[k] = reg2hw.loc_alert_class_shadowed[k].q; + end + + assign reg2hw_wrap.ping_timeout_cyc = reg2hw.ping_timeout_cyc_shadowed.q; + + // class enable + // we require that at least one of the enable signals is + // set for a class to be enabled + assign reg2hw_wrap.class_en = { + reg2hw.classd_ctrl_shadowed.en.q & ( reg2hw.classd_ctrl_shadowed.en_e3.q | + reg2hw.classd_ctrl_shadowed.en_e2.q | + reg2hw.classd_ctrl_shadowed.en_e1.q | + reg2hw.classd_ctrl_shadowed.en_e0.q ), + // + reg2hw.classc_ctrl_shadowed.en.q & ( reg2hw.classc_ctrl_shadowed.en_e3.q | + reg2hw.classc_ctrl_shadowed.en_e2.q | + reg2hw.classc_ctrl_shadowed.en_e1.q | + reg2hw.classc_ctrl_shadowed.en_e0.q ), + // + reg2hw.classb_ctrl_shadowed.en.q & ( reg2hw.classb_ctrl_shadowed.en_e3.q | + reg2hw.classb_ctrl_shadowed.en_e2.q | + reg2hw.classb_ctrl_shadowed.en_e1.q | + reg2hw.classb_ctrl_shadowed.en_e0.q ), + // + reg2hw.classa_ctrl_shadowed.en.q & ( reg2hw.classa_ctrl_shadowed.en_e3.q | + reg2hw.classa_ctrl_shadowed.en_e2.q | + reg2hw.classa_ctrl_shadowed.en_e1.q | + reg2hw.classa_ctrl_shadowed.en_e0.q ) + }; + + + // autolock enable + assign class_autolock_en = { reg2hw.classd_ctrl_shadowed.lock.q, + reg2hw.classc_ctrl_shadowed.lock.q, + reg2hw.classb_ctrl_shadowed.lock.q, + reg2hw.classa_ctrl_shadowed.lock.q }; + + // escalation signal enable + assign reg2hw_wrap.class_esc_en = { reg2hw.classd_ctrl_shadowed.en_e3.q, + reg2hw.classd_ctrl_shadowed.en_e2.q, + reg2hw.classd_ctrl_shadowed.en_e1.q, + reg2hw.classd_ctrl_shadowed.en_e0.q, + // + reg2hw.classc_ctrl_shadowed.en_e3.q, + reg2hw.classc_ctrl_shadowed.en_e2.q, + reg2hw.classc_ctrl_shadowed.en_e1.q, + reg2hw.classc_ctrl_shadowed.en_e0.q, + // + reg2hw.classb_ctrl_shadowed.en_e3.q, + reg2hw.classb_ctrl_shadowed.en_e2.q, + reg2hw.classb_ctrl_shadowed.en_e1.q, + reg2hw.classb_ctrl_shadowed.en_e0.q, + // + reg2hw.classa_ctrl_shadowed.en_e3.q, + reg2hw.classa_ctrl_shadowed.en_e2.q, + reg2hw.classa_ctrl_shadowed.en_e1.q, + reg2hw.classa_ctrl_shadowed.en_e0.q }; + + + // escalation phase to escalation signal mapping + assign reg2hw_wrap.class_esc_map = { reg2hw.classd_ctrl_shadowed.map_e3.q, + reg2hw.classd_ctrl_shadowed.map_e2.q, + reg2hw.classd_ctrl_shadowed.map_e1.q, + reg2hw.classd_ctrl_shadowed.map_e0.q, + // + reg2hw.classc_ctrl_shadowed.map_e3.q, + reg2hw.classc_ctrl_shadowed.map_e2.q, + reg2hw.classc_ctrl_shadowed.map_e1.q, + reg2hw.classc_ctrl_shadowed.map_e0.q, + // + reg2hw.classb_ctrl_shadowed.map_e3.q, + reg2hw.classb_ctrl_shadowed.map_e2.q, + reg2hw.classb_ctrl_shadowed.map_e1.q, + reg2hw.classb_ctrl_shadowed.map_e0.q, + // + reg2hw.classa_ctrl_shadowed.map_e3.q, + reg2hw.classa_ctrl_shadowed.map_e2.q, + reg2hw.classa_ctrl_shadowed.map_e1.q, + reg2hw.classa_ctrl_shadowed.map_e0.q }; + + // Determines in which phase to latch the crashdump. + assign reg2hw_wrap.class_crashdump_phase = { reg2hw.classd_crashdump_trigger_shadowed.q, + reg2hw.classc_crashdump_trigger_shadowed.q, + reg2hw.classb_crashdump_trigger_shadowed.q, + reg2hw.classa_crashdump_trigger_shadowed.q }; + + // writing 1b1 to a class clr register clears the accumulator and + // escalation state if autolock is not asserted + assign reg2hw_wrap.class_clr = { reg2hw.classd_clr_shadowed.q & reg2hw.classd_clr_shadowed.qe, + reg2hw.classc_clr_shadowed.q & reg2hw.classc_clr_shadowed.qe, + reg2hw.classb_clr_shadowed.q & reg2hw.classb_clr_shadowed.qe, + reg2hw.classa_clr_shadowed.q & reg2hw.classa_clr_shadowed.qe }; + + + // accumulator thresholds + assign reg2hw_wrap.class_accum_thresh = { reg2hw.classd_accum_thresh_shadowed.q, + reg2hw.classc_accum_thresh_shadowed.q, + reg2hw.classb_accum_thresh_shadowed.q, + reg2hw.classa_accum_thresh_shadowed.q }; + + // interrupt timeout lengths + assign reg2hw_wrap.class_timeout_cyc = { reg2hw.classd_timeout_cyc_shadowed.q, + reg2hw.classc_timeout_cyc_shadowed.q, + reg2hw.classb_timeout_cyc_shadowed.q, + reg2hw.classa_timeout_cyc_shadowed.q }; + // escalation phase lengths + assign reg2hw_wrap.class_phase_cyc = { reg2hw.classd_phase3_cyc_shadowed.q, + reg2hw.classd_phase2_cyc_shadowed.q, + reg2hw.classd_phase1_cyc_shadowed.q, + reg2hw.classd_phase0_cyc_shadowed.q, + // + reg2hw.classc_phase3_cyc_shadowed.q, + reg2hw.classc_phase2_cyc_shadowed.q, + reg2hw.classc_phase1_cyc_shadowed.q, + reg2hw.classc_phase0_cyc_shadowed.q, + // + reg2hw.classb_phase3_cyc_shadowed.q, + reg2hw.classb_phase2_cyc_shadowed.q, + reg2hw.classb_phase1_cyc_shadowed.q, + reg2hw.classb_phase0_cyc_shadowed.q, + // + reg2hw.classa_phase3_cyc_shadowed.q, + reg2hw.classa_phase2_cyc_shadowed.q, + reg2hw.classa_phase1_cyc_shadowed.q, + reg2hw.classa_phase0_cyc_shadowed.q}; + + ////////////////////// + // crashdump output // + ////////////////////// + + logic [N_CLASSES-1:0] crashdump_latched_q; + alert_crashdump_t crashdump_d, crashdump_q; + + // alert cause output + for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_cause_dump + assign crashdump_d.alert_cause[k] = reg2hw.alert_cause[k].q; + end + + // local alert cause register output + for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_cause_dump + assign crashdump_d.loc_alert_cause[k] = reg2hw.loc_alert_cause[k].q; + end + + assign crashdump_d.class_accum_cnt = hw2reg_wrap.class_accum_cnt; + assign crashdump_d.class_esc_cnt = hw2reg_wrap.class_esc_cnt; + assign crashdump_d.class_esc_state = hw2reg_wrap.class_esc_state; + + // We latch the crashdump upon triggering any of the escalation protocols. The reason for this is + // that during escalation, certain alert senders may start to trigger due to FSMs being moved + // into escalation mode - thereby masking the actual alert reasons exposed in the cause + // registers. + always_ff @(posedge clk_i or negedge rst_ni) begin : p_crashdump + if (!rst_ni) begin + crashdump_latched_q <= '0; + crashdump_q <= '0; + end else begin + // We track which class has been escalated so that the crashdump latching mechanism cannot be + // re-armed by clearing another class that has not escalated yet. This also implies that if + // an unclearable class has escalated, the crashdump latching mechanism cannot be re-armed. + crashdump_latched_q <= (crashdump_latched_q & ~reg2hw_wrap.class_clr) | latch_crashdump_i; + + // The alert handler only captures the first escalation event that asserts a latch_crashdump_i + // signal, unless all classes are cleared, in which case the crashdump latching mechanism is + // re-armed. In other words, we latch the crashdump if any of the latch_crashdump_i bits is + // asserted, and no crashdump has been latched yet. + if (|latch_crashdump_i && !(|crashdump_latched_q)) begin + crashdump_q <= crashdump_d; + end + end + end + + // As long as the crashdump has not been latched yet, we output the current alert handler state. + // Once any of the classes has triggered the latching, we switch to the latched snapshot. + assign crashdump_o = (|crashdump_latched_q) ? crashdump_q : crashdump_d; + +endmodule : alert_handler_reg_wrap diff --git a/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_pkg.sv b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_pkg.sv new file mode 100644 index 0000000000000..85542fb7a0c1d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/alert_handler/rtl/alert_pkg.sv @@ -0,0 +1,101 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +package alert_pkg; + + // these localparams are generated based on the system top-level configuration + localparam int unsigned NAlerts = alert_handler_reg_pkg::NAlerts; // maximum 252 + localparam int unsigned EscCntDw = alert_handler_reg_pkg::EscCntDw; // maximum 32 + localparam int unsigned AccuCntDw = alert_handler_reg_pkg::AccuCntDw; // maximum 32 + localparam int unsigned NLpg = alert_handler_reg_pkg::NLpg; + localparam int unsigned NLpgWidth = alert_handler_reg_pkg::NLpgWidth; + localparam logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = alert_handler_reg_pkg::LpgMap; + // enable async transitions for specific RX/TX pairs + localparam bit [NAlerts-1:0] AsyncOn = alert_handler_reg_pkg::AsyncOn; + + // common constants, do not change + localparam int unsigned N_CLASSES = alert_handler_reg_pkg::N_CLASSES; + localparam int unsigned N_ESC_SEV = alert_handler_reg_pkg::N_ESC_SEV; + localparam int unsigned N_PHASES = alert_handler_reg_pkg::N_PHASES; + localparam int unsigned N_LOC_ALERT = alert_handler_reg_pkg::N_LOC_ALERT; + + localparam int unsigned PING_CNT_DW = alert_handler_reg_pkg::PING_CNT_DW; + localparam int unsigned PHASE_DW = alert_handler_reg_pkg::PHASE_DW; + localparam int unsigned CLASS_DW = alert_handler_reg_pkg::CLASS_DW; + + // do not change the phase encoding + typedef enum logic [2:0] {Idle = 3'b000, Timeout = 3'b001, Terminal = 3'b011, + Phase0 = 3'b100, Phase1 = 3'b101, Phase2 = 3'b110, + Phase3 = 3'b111, FsmError = 3'b010} cstate_e; + + // These LFSR parameters have been generated with + // $ util/design/gen-lfsr-seed.py --width 32 --seed 2700182644 + localparam int LfsrWidth = 32; + typedef logic [LfsrWidth-1:0] lfsr_seed_t; + typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t; + localparam lfsr_seed_t RndCnstLfsrSeedDefault = 32'he96064e5; + localparam lfsr_perm_t RndCnstLfsrPermDefault = + 160'hebd1e5d4a1cee5afdb866a9c7a0278b899020d31; + + // struct containing the current alert handler state + // can be used to gather crashdump information in HW + typedef struct packed { + // alerts + logic [NAlerts-1:0] alert_cause; // alert cause bits + logic [N_LOC_ALERT-1:0] loc_alert_cause; // local alert cause bits + // class state + logic [N_CLASSES-1:0][AccuCntDw-1:0] class_accum_cnt; // current accumulator value + logic [N_CLASSES-1:0][EscCntDw-1:0] class_esc_cnt; // current escalation counter value + cstate_e [N_CLASSES-1:0] class_esc_state; // current escalation protocol state + } alert_crashdump_t; + + // Default for dangling connection + parameter alert_crashdump_t ALERT_CRASHDUMP_DEFAULT = '{ + alert_cause: '0, + loc_alert_cause: '0, + class_accum_cnt: '0, + class_esc_cnt: '0, + class_esc_state: {N_CLASSES{Idle}} + }; + + // breakout wrapper structs + typedef struct packed { + // alerts + logic [NAlerts-1:0] alert_cause; // alert cause bits + logic [N_LOC_ALERT-1:0] loc_alert_cause; // local alert cause bits + // class state + logic [N_CLASSES-1:0] class_trig; // class trigger + logic [N_CLASSES-1:0] class_esc_trig; // escalation trigger + logic [N_CLASSES-1:0][AccuCntDw-1:0] class_accum_cnt; // current accumulator value + logic [N_CLASSES-1:0][EscCntDw-1:0] class_esc_cnt; // current escalation counter value + cstate_e [N_CLASSES-1:0] class_esc_state; // current escalation protocol state + } hw2reg_wrap_t; + + typedef struct packed { + // aggregated shadow reg errors (trigger internal alerts) + logic shadowed_err_update; + logic shadowed_err_storage; + // ping config + logic ping_enable; // ping timer enable + logic [PING_CNT_DW-1:0] ping_timeout_cyc; // ping timeout config + logic [NAlerts-1:0] alert_ping_en; // ping enable for alerts + // alert config + logic [N_LOC_ALERT-1:0] loc_alert_en; // alert enable + logic [N_LOC_ALERT-1:0][CLASS_DW-1:0] loc_alert_class; // alert class config + logic [NAlerts-1:0] alert_en; // alert enable + logic [NAlerts-1:0][CLASS_DW-1:0] alert_class; // alert class config + // class config + logic [N_CLASSES-1:0] class_en; // enables esc mechanisms + logic [N_CLASSES-1:0] class_clr; // clears esc/accu + logic [N_CLASSES-1:0][AccuCntDw-1:0] class_accum_thresh; // accum esc threshold + logic [N_CLASSES-1:0][EscCntDw-1:0] class_timeout_cyc; // interrupt timeout + logic [N_CLASSES-1:0][N_PHASES-1:0][EscCntDw-1:0] class_phase_cyc; // length of phases 0..3 + logic [N_CLASSES-1:0][N_ESC_SEV-1:0] class_esc_en; // esc signal enables + logic [N_CLASSES-1:0][N_ESC_SEV-1:0][PHASE_DW-1:0] class_esc_map; // esc signal/phase map + // determines when to latch the crashdump output. + logic [N_CLASSES-1:0][PHASE_DW-1:0] class_crashdump_phase; + } reg2hw_wrap_t; + +endpackage : alert_pkg diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/BUILD b/hw/top_darjeeling/ip_autogen/clkmgr/BUILD new file mode 100644 index 0000000000000..3bed0f321eb3d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/BUILD @@ -0,0 +1,30 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +load( + "//rules:autogen.bzl", + "autogen_hjson_c_header", + "autogen_hjson_rust_header", +) + +autogen_hjson_c_header( + name = "clkmgr_c_regs", + srcs = [ + "data/clkmgr.hjson", + ], +) + +autogen_hjson_rust_header( + name = "clkmgr_rust_regs", + srcs = [ + "data/clkmgr.hjson", + ], +) + +filegroup( + name = "all_files", + srcs = glob(["**"]), +) diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/README.md b/hw/top_darjeeling/ip_autogen/clkmgr/README.md new file mode 100644 index 0000000000000..71cb24d08ddaa --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/README.md @@ -0,0 +1,18 @@ +# Clock Manager HWIP Technical Specification + +[`clkmgr`](https://reports.opentitan.org/hw/top_darjeeling/ip_autogen/clkmgr/dv/latest/report.html): +![](https://dashboards.lowrisc.org/badges/dv/clkmgr/test.svg) +![](https://dashboards.lowrisc.org/badges/dv/clkmgr/passing.svg) +![](https://dashboards.lowrisc.org/badges/dv/clkmgr/functional.svg) +![](https://dashboards.lowrisc.org/badges/dv/clkmgr/code.svg) + +# Overview + +This document specifies the functionality of the OpenTitan clock manager. + +## Features + +- Attribute based controls of OpenTitan clocks. +- Minimal software clock controls to reduce risks in clock manipulation. +- External clock switch support +- Clock frequency /time-out measurement diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core new file mode 100644 index 0000000000000..dbca598dc0dcb --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr.core @@ -0,0 +1,73 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_clkmgr:0.1 +description: "Top specific clock manager " +virtual: + - lowrisc:ip_interfaces:clkmgr + +filesets: + files_rtl: + depend: + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg + - lowrisc:ip:tlul + - lowrisc:prim:all + - lowrisc:prim:buf + - lowrisc:prim:clock_buf + - lowrisc:prim:clock_div + - lowrisc:prim:clock_gating + - lowrisc:prim:edge_detector + - lowrisc:prim:lc_sync + - lowrisc:prim:lc_sender + - lowrisc:prim:measure + - lowrisc:opentitan:top_darjeeling_clkmgr_pkg:0.1 + - lowrisc:opentitan:top_darjeeling_clkmgr_reg:0.1 + files: + - rtl/clkmgr.sv + - rtl/clkmgr_byp.sv + - rtl/clkmgr_clk_status.sv + - rtl/clkmgr_meas_chk.sv + - rtl/clkmgr_root_ctrl.sv + - rtl/clkmgr_trans.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/clkmgr.waiver + file_type: waiver + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - files_rtl + toplevel: clkmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr_pkg.core b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr_pkg.core new file mode 100644 index 0000000000000..91fefa09e71cb --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr_pkg.core @@ -0,0 +1,23 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_clkmgr_pkg:0.1 +description: "Top specific clock manager package" +virtual: + - lowrisc:ip_interfaces:clkmgr_pkg + +filesets: + files_rtl: + depend: + - lowrisc:constants:top_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg + - lowrisc:prim:mubi + files: + - rtl/clkmgr_pkg.sv + file_type: systemVerilogSource + +targets: + default: &default_target + filesets: + - files_rtl diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr_reg.core b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr_reg.core new file mode 100644 index 0000000000000..fa2fe9daada45 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/clkmgr_reg.core @@ -0,0 +1,22 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_clkmgr_reg:0.1 +description: "Clock manager registers" +virtual: + - lowrisc:ip_interfaces:clkmgr_reg + +filesets: + files_rtl: + depend: + - lowrisc:tlul:headers + files: + - rtl/clkmgr_reg_pkg.sv + - rtl/clkmgr_reg_top.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr.hjson b/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr.hjson new file mode 100644 index 0000000000000..93002a907682b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr.hjson @@ -0,0 +1,862 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +# CLKMGR register template +# +{ + name: "clkmgr", + human_name: "Clock Manager", + one_line_desc: "Derives and monitors on-chip clock signals, handles clock gating requests from power manager and software", + one_paragraph_desc: ''' + Clock Manager derives on-chip clocks from root clock signals provided by Analog Sensor Top (AST). + Input and output clocks may be asynchronous to each other. + During clock derivation, Clock Manager can divide clocks to lower frequencies and gate clocks based on control signals from the power manager and to a limited extent from software. + For example, the idle status of relevant hardware blocks is tracked and clock gating requests from software are ignored as long as these blocks are active. + Further security features include switchable clock jitter, continuous monitoring of clock frequencies, and various countermeasures to deter fault injection (FI) attacks. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "4", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_clkmgr", + revisions: [ + { + version: "1.0.1", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + } + ] + scan: "true", + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {reset: "rst_root_ni"}, + {clock: "clk_main_i", reset: "rst_main_ni"}, + {clock: "clk_io_i", reset: "rst_io_ni"}, + {clock: "clk_usb_i", reset: "rst_usb_ni"}, + {clock: "clk_aon_i", reset: "rst_aon_ni"}, + {clock: "clk_io_div2_i", reset: "rst_io_div2_ni", internal: true}, + {clock: "clk_io_div4_i", reset: "rst_io_div4_ni", internal: true}, + {reset: "rst_root_main_ni"}, + {reset: "rst_root_io_ni"}, + {reset: "rst_root_io_div2_ni"}, + {reset: "rst_root_io_div4_ni"}, + {reset: "rst_root_usb_ni"}, + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device" } + ], + alert_list: [ + { name: "recov_fault", + desc: ''' + This recoverable alert is triggered when there are measurement errors. + ''' + } + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. + ''' + } + ], + regwidth: "32", + param_list: [ + { name: "NumGroups", + desc: "Number of clock groups", + type: "int", + default: "7", + local: "true" + }, + { name: "NumSwGateableClocks", + desc: "Number of SW gateable clocks", + type: "int", + default: "3", + local: "true" + }, + { name: "NumHintableClocks", + desc: "Number of hintable clocks", + type: "int", + default: "4", + local: "true" + }, + ], + + features: [ + { name: "CLKMGR.ENABLE.IO_DIV4", + desc: "Gating of IO_DIV4 peripheral clock." + } + { name: "CLKMGR.ENABLE.IO_DIV2", + desc: "Gating of IO_DIV2 peripheral clock." + } + { name: "CLKMGR.ENABLE.USB", + desc: "Gating of USB peripheral clock." + } + { name: "CLKMGR.HINT.AES", + desc: "Gating of AES transactional clock." + } + { name: "CLKMGR.HINT.HMAC", + desc: "Gating of HMAC transactional clock." + } + { name: "CLKMGR.HINT.KMAC", + desc: "Gating of KMAC transactional clock." + } + { name: "CLKMGR.HINT.OTBN", + desc: "Gating of OTBN transactional clock." + } + { name: "CLKMGR.MEAS_CTRL.REGWEN", + desc: '''Control modification of all clock frequency and timeout + measurements. + ''' + } + { name: "CLKMGR.MEAS_CTRL.IO_DIV4", + desc: "Frequency and timeout measurements of IO_DIV4 clock." + } + { name: "CLKMGR.MEAS_CTRL.MAIN", + desc: "Frequency and timeout measurements of MAIN clock." + } + { name: "CLKMGR.MEAS_CTRL.USB", + desc: "Frequency and timeout measurements of USB clock." + } + { name: "CLKMGR.MEAS_CTRL.RECOV_ERR", + desc: "Frequency and timeout measurements can flag recoverable errors." + } + { name: "CLKMGR.LC_EXTCLK.SPEED", + desc: "Speed of LC controlled modification of external clock." + } + { name: "CLKMGR.SW_EXTCLK.REGWEN", + desc: "Control software modification of external clock configuration." + } + { name: "CLKMGR.SW_EXTCLK.HIGH_SPEED", + desc: "Software configuration of external clock running at 96 MHz." + } + { name: "CLKMGR.SW_EXTCLK.LOW_SPEED", + desc: "Software configuration of external clock running at 48 MHz." + } + { name: "CLKMGR.JITTER.REGWEN", + desc: "Control modification of clock jitter enable." + } + { name: "CLKMGR.JITTER.ENABLE", + desc: "Enable clock jitter." + } + { name: "CLKMGR.ALERT_HANDLER.CLOCK_STATUS", + desc: "Inform alert handler about clock enable status for each clock." + } +] + + inter_signal_list: [ + { struct: "clkmgr_out", + type: "uni", + name: "clocks", + act: "req", + package: "clkmgr_pkg", + }, + + { struct: "clkmgr_cg_en", + type: "uni", + name: "cg_en", + act: "req", + package: "clkmgr_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_hw_debug_en", + act: "rcv", + package: "lc_ctrl_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "io_clk_byp_req", + act: "req", + package: "prim_mubi_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "io_clk_byp_ack", + act: "rcv", + package: "prim_mubi_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "all_clk_byp_req", + act: "req", + package: "prim_mubi_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "all_clk_byp_ack", + act: "rcv", + package: "prim_mubi_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "hi_speed_sel", + act: "req", + package: "prim_mubi_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "div_step_down_req", + act: "rcv", + package: "prim_mubi_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_clk_byp_req", + act: "rcv", + package: "lc_ctrl_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_clk_byp_ack", + act: "req", + package: "lc_ctrl_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "jitter_en", + act: "req", + package: "prim_mubi_pkg" + }, + + // Exported clocks + + { struct: "pwr_clk", + type: "req_rsp", + name: "pwr", + act: "rsp", + }, + + { struct: "mubi4", + type: "uni", + name: "idle", + act: "rcv", + package: "prim_mubi_pkg", + width: "4" + }, + + { struct: "mubi4", + desc: "Indicates clocks are calibrated and frequencies accurate", + type: "uni", + name: "calib_rdy", + act: "rcv", + package: "prim_mubi_pkg", + default: "prim_mubi_pkg::MuBi4True" + }, + ], + + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + }, + { name: "TIMEOUT.CLK.BKGN_CHK", + desc: "Background check for clock timeout." + }, + { name: "MEAS.CLK.BKGN_CHK", + desc: "Background check for clock frequency." + }, + { name: "MEAS.CONFIG.SHADOW", + desc: "Measurement configurations are shadowed." + } + { name: "IDLE.INTERSIG.MUBI", + desc: "Idle inputs are multibit encoded." + } + { name: "LC_CTRL.INTERSIG.MUBI", + desc: "The life cycle control signals are multibit encoded." + } + { name: "LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI", + desc: "The life cycle clock req/ack signals are multibit encoded." + } + { name: "CLK_HANDSHAKE.INTERSIG.MUBI", + desc: "The external clock req/ack signals are multibit encoded." + } + { name: "DIV.INTERSIG.MUBI", + desc: "Divider step down request is multibit encoded." + } + { name: "JITTER.CONFIG.MUBI", + desc: "The jitter enable configuration is multibit encoded." + } + { name: "IDLE.CTR.REDUN", + desc: "Idle counter is duplicated." + } + { name: "MEAS.CONFIG.REGWEN", + desc: "The measurement controls protected with regwen." + } + { name: "CLK_CTRL.CONFIG.REGWEN", + desc: "Software controlled clock requests are proteced with regwen." + } + + ] + + registers: [ + { name: "EXTCLK_CTRL_REGWEN", + desc: "External clock control write enable", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + name: "EN", + resval: "1" + desc: ''' + When 1, the value of !!EXTCLK_CTRL can be set. When 0, writes to !!EXTCLK_CTRL have no + effect. + ''' + }, + ] + }, + + { name: "EXTCLK_CTRL", + desc: ''' + Select external clock + ''', + regwen: "EXTCLK_CTRL_REGWEN", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "3:0", + name: "SEL", + mubi: true, + desc: ''' + When the current value is not kMultiBitBool4True, writing a value of kMultiBitBool4True + selects external clock as clock for the system. Writing any other value has + no impact. + + When the current value is kMultiBitBool4True, writing a value of kMultiBitBool4False + selects internal clock as clock for the system. Writing any other value during this stage + has no impact. + + While this register can always be programmed, it only takes effect when debug functions are enabled + in life cycle TEST, DEV or RMA states. + ''' + resval: "false" + }, + { + bits: "7:4", + name: "HI_SPEED_SEL", + mubi: true, + desc: ''' + A value of kMultiBitBool4True selects nominal speed external clock. + All other values selects low speed clocks. + + Note this field only has an effect when the !!EXTCLK_CTRL.SEL field is set to + kMultiBitBool4True. + + Nominal speed means the external clock is approximately the same frequency as + the internal oscillator source. When this option is used, all clocks operate + at roughly the nominal frequency. + + Low speed means the external clock is approximately half the frequency of the + internal oscillator source. When this option is used, the internal dividers are + stepped down. As a result, previously undivided clocks now run at half frequency, + while previously divided clocks run at roughly the nominal frequency. + + See external clock switch support in documentation for more details. + ''' + resval: false + } + ] + // avoid writing random values to this register as it could trigger transient checks + // in mubi sync + tags: ["excl:CsrAllTests:CsrExclWrite"] + }, + + { name: "EXTCLK_STATUS", + desc: ''' + Status of requested external clock switch + ''', + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { + bits: "3:0", + name: "ACK", + mubi: true, + desc: ''' + When !!EXTCLK_CTRL.SEL is set to kMultiBitBool4True, this field reflects + whether the clock has been switched the external source. + + kMultiBitBool4True indicates the switch is complete. + kMultiBitBool4False indicates the switch is either not possible or still ongoing. + ''' + resval: "false" + }, + ] + }, + + { name: "JITTER_REGWEN", + desc: "Jitter write enable", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + name: "EN", + resval: "1" + desc: ''' + When 1, the value of !!JITTER_ENABLE can be changed. When 0, writes have no + effect. + ''' + }, + ] + }, + + { name: "JITTER_ENABLE", + desc: ''' + Enable jittery clock + ''', + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + mubi: true, + bits: "3:0", + name: "VAL", + desc: ''' + Enable jittery clock. + A value of kMultiBitBool4False disables the jittery clock, + while all other values enable jittery clock. + ''', + resval: false + // avoid writing random values to this register as it could trigger transient checks + // in mubi sync + tags: ["excl:CsrAllTests:CsrExclWrite"] + } + ] + }, + + { name: "CLK_ENABLES", + desc: ''' + Clock enable for software gateable clocks. + These clocks are directly controlled by software. + ''', + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0", + name: "CLK_IO_DIV4_PERI_EN", + resval: 1, + desc: ''' + 0 CLK_IO_DIV4_PERI is disabled. + 1 CLK_IO_DIV4_PERI is enabled. + ''' + } + { + bits: "1", + name: "CLK_IO_DIV2_PERI_EN", + resval: 1, + desc: ''' + 0 CLK_IO_DIV2_PERI is disabled. + 1 CLK_IO_DIV2_PERI is enabled. + ''' + } + { + bits: "2", + name: "CLK_USB_PERI_EN", + resval: 1, + desc: ''' + 0 CLK_USB_PERI is disabled. + 1 CLK_USB_PERI is enabled. + ''' + } + ] + // the CLK_ENABLE register cannot be written. + // During top level randomized tests, it is possible to disable the clocks and then access + // a register in the disabled block. This would lead to a top level hang. + tags: ["excl:CsrAllTests:CsrExclAll"] + }, + + { name: "CLK_HINTS", + desc: ''' + Clock hint for software gateable transactional clocks during active mode. + During low power mode, all clocks are gated off regardless of the software hint. + + Transactional clocks are not fully controlled by software. Instead software provides only a disable hint. + + When software provides a disable hint, the clock manager checks to see if the associated hardware block is idle. + If the hardware block is idle, then the clock is disabled. + If the hardware block is not idle, the clock is kept on. + + For the enable case, the software hint is immediately honored and the clock turned on. Hardware does not provide any + feedback in this case. + ''', + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0", + name: "CLK_MAIN_AES_HINT", + resval: 1, + desc: ''' + 0 CLK_MAIN_AES can be disabled. + 1 CLK_MAIN_AES is enabled. + ''' + } + { + bits: "1", + name: "CLK_MAIN_HMAC_HINT", + resval: 1, + desc: ''' + 0 CLK_MAIN_HMAC can be disabled. + 1 CLK_MAIN_HMAC is enabled. + ''' + } + { + bits: "2", + name: "CLK_MAIN_KMAC_HINT", + resval: 1, + desc: ''' + 0 CLK_MAIN_KMAC can be disabled. + 1 CLK_MAIN_KMAC is enabled. + ''' + } + { + bits: "3", + name: "CLK_MAIN_OTBN_HINT", + resval: 1, + desc: ''' + 0 CLK_MAIN_OTBN can be disabled. + 1 CLK_MAIN_OTBN is enabled. + ''' + } + ] + // the CLK_HINT register cannot be written. + // During top level randomized tests, it is possible to disable the clocks to transactional blocks + // and then access a register in the disabled block. This would lead to a top level hang. + tags: ["excl:CsrAllTests:CsrExclAll"] + }, + + { name: "CLK_HINTS_STATUS", + desc: ''' + Since the final state of !!CLK_HINTS is not always determined by software, + this register provides read feedback for the current clock state. + + ''', + swaccess: "ro", + hwaccess: "hwo", + fields: [ + { + bits: "0", + name: "CLK_MAIN_AES_VAL", + resval: 1, + desc: ''' + 0 CLK_MAIN_AES is disabled. + 1 CLK_MAIN_AES is enabled. + ''' + } + { + bits: "1", + name: "CLK_MAIN_HMAC_VAL", + resval: 1, + desc: ''' + 0 CLK_MAIN_HMAC is disabled. + 1 CLK_MAIN_HMAC is enabled. + ''' + } + { + bits: "2", + name: "CLK_MAIN_KMAC_VAL", + resval: 1, + desc: ''' + 0 CLK_MAIN_KMAC is disabled. + 1 CLK_MAIN_KMAC is enabled. + ''' + } + { + bits: "3", + name: "CLK_MAIN_OTBN_VAL", + resval: 1, + desc: ''' + 0 CLK_MAIN_OTBN is disabled. + 1 CLK_MAIN_OTBN is enabled. + ''' + } + ] + // the CLK_HINT_STATUS register is read-only and cannot be checked. + // This register's value depends on the IDLE inputs, so cannot be predicted. + tags: ["excl:CsrNonInitTests:CsrExclCheck:CsrExclCheck"] + }, + + { name: "MEASURE_CTRL_REGWEN", + desc: "Measurement control write enable", + swaccess: "rw0c", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "EN", + resval: "1" + desc: ''' + When 1, the value of the measurement control can be set. When 0, writes have no + effect. + ''' + }, + ] + }, + { name: "IO_DIV4_MEAS_CTRL_EN", + desc: ''' + Enable for measurement control + ''', + regwen: "MEASURE_CTRL_REGWEN", + swaccess: "rw", + hwaccess: "hrw", + async: "clk_io_div4_i", + fields: [ + { + bits: "3:0", + name: "EN", + desc: "Enable measurement for io_div4", + mubi: true, + resval: false, + }, + ] + // Measurements can cause recoverable errors depending on the + // thresholds which randomized CSR tests will not predict correctly. + // To provide better CSR coverage we allow writing the threshold + // fields, but not enabling the counters. + tags: ["excl:CsrAllTests:CsrExclWrite"] + }, + + { name: "IO_DIV4_MEAS_CTRL_SHADOWED", + desc: ''' + Configuration controls for io_div4 measurement. + + The threshold fields are made wider than required (by 1 bit) to ensure + there is room to adjust for measurement inaccuracies. + ''', + regwen: "MEASURE_CTRL_REGWEN", + swaccess: "rw", + hwaccess: "hro", + async: "clk_io_div4_i", + shadowed: "true", + update_err_alert: "recov_fault", + storage_err_alert: "fatal_fault", + fields: [ + { + bits: "7:0", + name: "HI", + desc: "Max threshold for io_div4 measurement", + resval: "130" + }, + + { + bits: "15:8", + name: "LO", + desc: "Min threshold for io_div4 measurement", + resval: "110" + }, + ] + }, + { name: "MAIN_MEAS_CTRL_EN", + desc: ''' + Enable for measurement control + ''', + regwen: "MEASURE_CTRL_REGWEN", + swaccess: "rw", + hwaccess: "hrw", + async: "clk_main_i", + fields: [ + { + bits: "3:0", + name: "EN", + desc: "Enable measurement for main", + mubi: true, + resval: false, + }, + ] + // Measurements can cause recoverable errors depending on the + // thresholds which randomized CSR tests will not predict correctly. + // To provide better CSR coverage we allow writing the threshold + // fields, but not enabling the counters. + tags: ["excl:CsrAllTests:CsrExclWrite"] + }, + + { name: "MAIN_MEAS_CTRL_SHADOWED", + desc: ''' + Configuration controls for main measurement. + + The threshold fields are made wider than required (by 1 bit) to ensure + there is room to adjust for measurement inaccuracies. + ''', + regwen: "MEASURE_CTRL_REGWEN", + swaccess: "rw", + hwaccess: "hro", + async: "clk_main_i", + shadowed: "true", + update_err_alert: "recov_fault", + storage_err_alert: "fatal_fault", + fields: [ + { + bits: "9:0", + name: "HI", + desc: "Max threshold for main measurement", + resval: "510" + }, + + { + bits: "19:10", + name: "LO", + desc: "Min threshold for main measurement", + resval: "490" + }, + ] + }, + { name: "USB_MEAS_CTRL_EN", + desc: ''' + Enable for measurement control + ''', + regwen: "MEASURE_CTRL_REGWEN", + swaccess: "rw", + hwaccess: "hrw", + async: "clk_usb_i", + fields: [ + { + bits: "3:0", + name: "EN", + desc: "Enable measurement for usb", + mubi: true, + resval: false, + }, + ] + // Measurements can cause recoverable errors depending on the + // thresholds which randomized CSR tests will not predict correctly. + // To provide better CSR coverage we allow writing the threshold + // fields, but not enabling the counters. + tags: ["excl:CsrAllTests:CsrExclWrite"] + }, + + { name: "USB_MEAS_CTRL_SHADOWED", + desc: ''' + Configuration controls for usb measurement. + + The threshold fields are made wider than required (by 1 bit) to ensure + there is room to adjust for measurement inaccuracies. + ''', + regwen: "MEASURE_CTRL_REGWEN", + swaccess: "rw", + hwaccess: "hro", + async: "clk_usb_i", + shadowed: "true", + update_err_alert: "recov_fault", + storage_err_alert: "fatal_fault", + fields: [ + { + bits: "8:0", + name: "HI", + desc: "Max threshold for usb measurement", + resval: "250" + }, + + { + bits: "17:9", + name: "LO", + desc: "Min threshold for usb measurement", + resval: "230" + }, + ] + }, + + { name: "RECOV_ERR_CODE", + desc: "Recoverable Error code", + swaccess: "rw1c", + hwaccess: "hwo", + fields: [ + { bits: "0", + name: "SHADOW_UPDATE_ERR", + resval: 0 + desc: ''' + One of the shadow registers encountered an update error. + ''' + }, + { + bits: "1", + name: "IO_DIV4_MEASURE_ERR", + resval: 0, + desc: ''' + io_div4 has encountered a measurement error. + ''' + }, + { + bits: "2", + name: "MAIN_MEASURE_ERR", + resval: 0, + desc: ''' + main has encountered a measurement error. + ''' + }, + { + bits: "3", + name: "USB_MEASURE_ERR", + resval: 0, + desc: ''' + usb has encountered a measurement error. + ''' + }, + { + bits: "4", + name: "IO_DIV4_TIMEOUT_ERR", + resval: 0, + desc: ''' + io_div4 has timed out. + ''' + } + { + bits: "5", + name: "MAIN_TIMEOUT_ERR", + resval: 0, + desc: ''' + main has timed out. + ''' + } + { + bits: "6", + name: "USB_TIMEOUT_ERR", + resval: 0, + desc: ''' + usb has timed out. + ''' + } + ] + }, + + { name: "FATAL_ERR_CODE", + desc: "Error code", + swaccess: "ro", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "REG_INTG", + resval: 0 + desc: ''' + Register file has experienced a fatal integrity error. + ''' + }, + { bits: "1", + name: "IDLE_CNT", + resval: 0 + desc: ''' + One of the idle counts encountered a duplicate error. + ''' + }, + { bits: "2", + name: "SHADOW_STORAGE_ERR", + resval: 0 + desc: ''' + One of the shadow registers encountered a storage error. + ''' + }, + ] + }, + ] +} diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_sec_cm_testplan.hjson b/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_sec_cm_testplan.hjson new file mode 100644 index 0000000000000..f9c12d7d8f4ef --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_sec_cm_testplan.hjson @@ -0,0 +1,190 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../clkmgr/data/clkmgr.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../clkmgr/data/clkmgr_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: '''Verify the countermeasure(s) BUS.INTEGRITY. + This entry is covered by tl_access_test. + ''' + stage: V2S + tests: ["clkmgr_tl_intg_err"] + } + { + name: sec_cm_meas_clk_bkgn_chk + desc: '''Verify the countermeasure(s) MEAS.CLK.BKGN_CHK. + - Test measurement feature of clkmgr_meas_chk modules. + For all test clocks (clk_main, clk_usb, clk_io, clk_io_div2 + and clk_io_div4), do measurement with normal configuration. + Then change either min or max threshold value to see + whether the module can detect measurement error for each test + clock. + - Measurement error should trigger a recoverable alert + ''' + stage: V2S + tests: ["clkmgr_frequency"] + } + { + name: sec_cm_timeout_clk_bkgn_chk + desc: '''Verify the countermeasure(s) TIMEOUT.CLK.BKGN_CHK. + - Test timeout feature of clkmgr_meas_chk modules. + While frequency measurement, one of + clk_main, clk_usb, clk_io, clk_io_div2 and clk_io_div4 are choose + and stopped. This will leads to timeout event. + - Timeout should cause a recoverable alert + ''' + stage: V2S + tests: ["clkmgr_frequency_timeout"] + } + { + name: sec_cm_meas_config_shadow + desc: ''' + Verify the countermeasure(s) MEAS.CONFIG.SHADOW. + + This is covered by shadow_reg_errors_tests + (https://github.com/lowRISC/opentitan/blob/master/ + hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson) + ''' + stage: V2S + tests: ["clkmgr_shadow_reg_errors"] + } + { + name: sec_cm_idle_intersig_mubi + desc: '''Verify the countermeasure(s) IDLE.INTERSIG.MUBI. + It uses true_strict and false_loose. + **Stimulus**: + Use same sequence as trans_enables test. + Randomize dut.idle_i ports with illegal values. + **Check**: + - hins_status check: + When clk_hints update from '1' to '0', + clk_hints_status has to wait idle becomes 'true'. So check + clk_hints_status with random idle value, then check again + after set all idle values to 'true'. + + - clock output check: + When clk_hints_status go to '0', check clocks_o + to see if clock is really off + ''' + stage: V2S + tests: ["clkmgr_idle_intersig_mubi"] + } + { + name: sec_cm_lc_ctrl_intersig_mubi + desc: '''Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI. + It compares to lc_ctrl_pkg::On only. + Use clkmgr_extclk test as in testplan.extclk but randomize + dut.lc_hw_debug_en_i s.t. all 16 values can be generated with equal priority. + + **Checks**: + When dut sees invalid values of lc_hw_debug_en_i, + all_clk_byp_req should not be asserted. Covered by assertion checker. + ''' + stage: V2S + tests: ["clkmgr_lc_ctrl_intersig_mubi"] + } + { + name: sec_cm_lc_ctrl_clk_handshake_intersig_mubi + desc: '''Verify the countermeasure(s) LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI. + It compared to lc_ctrl_pkg::On only. + Use clkmgr_extclk test but randomize lc_clk_byp_req s.t. + all 16 values can be generated with equal priority. + lc_clk_byp_req drives dut.lc_clk_byp_req_i in the test. + **Checks**: + When dut sees invalid values of lc_clk_byp_req_i, + io_clk_byp_req_o should not be asserted. Covered by assertion checker. + ''' + stage: V2S + tests: ["clkmgr_lc_clk_byp_req_intersig_mubi"] + } + { + name: sec_cm_clk_handshake_intersig_mubi + desc: '''Verify the countermeasure(s) CLK_HANDSHAKE.INTERSIG.MUBI. + It uses true_strict. + Use clkmgr_extclk test. Upon receiving [io|all]_clk_byp_req_o from dut, + assert invalid [io|all]_clk_byp_ack values to dut. + + **Check**: + all_clk_byp_ack is copied to CLKGMR.EXTCLK_STATUS as is. So read extclk + status and compare. + io_clk_byp_ack is evaluated with step_down_acks_syn. + When both are true, lc_clk_byp_req is assigned to lc_clk_byp_ack. + Covered by assertion checker. + ''' + stage: V2S + tests: ["clkmgr_clk_handshake_intersig_mubi"] + } + { + name: sec_cm_div_intersig_mubi + desc: '''Verify the countermeasure(s) DIV.INTERSIG.MUBI. + use true_strict. + Use clkmgr_extclk test. Before, test drive dut.div_step_down_req_i + with 'true', sends invalid values. + **Check**: + dut should ignore invalid req values. Covered by assertion checker. + ''' + stage: V2S + tests: ["clkmgr_div_intersig_mubi"] + } + { + name: sec_cm_jitter_config_mubi + desc: '''Verify the countermeasure(s) JITTER.CONFIG.MUBI. + use false_strict. + This doesn't do any function in the dut but indicating + jittery clock is enabled. So it can be covered by default + csr test. + ''' + stage: V2S + tests: ["clkmgr_csr_rw"] + } + { + name: sec_cm_idle_ctr_redun + desc: '''Verify the countermeasure(s) IDLE.CTR.REDUN. + This is triggered by common cm primitives (SecCmPrimCount). + **Check**: + read check CLKMGR.FATAL_ERR_CODE.IDLE_CNT == 1 + ''' + stage: V2S + tests: ["clkmgr_sec_cm"] + } + { + name: sec_cm_meas_config_regwen + desc: '''Verify the countermeasure(s) MEAS.CONFIG.REGWEN. + + This is covered by auto csr test. + ''' + stage: V2S + tests: ["clkmgr_csr_rw"] + } + { + name: sec_cm_clk_ctrl_config_regwen + desc: '''Verify the countermeasure(s) CLK_CTRL.CONFIG.REGWEN. + + This is covered by auto csr test. + ''' + stage: V2S + tests: ["clkmgr_csr_rw"] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_testplan.hjson b/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_testplan.hjson new file mode 100644 index 0000000000000..af05156616edc --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_testplan.hjson @@ -0,0 +1,334 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "clkmgr" + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", + "hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson", + "clkmgr_sec_cm_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson"] + testpoints: [ + { + name: smoke + desc: ''' + Smoke test disabling peripheral and transactional clocks. + + - Disables all peripheral clocks from their enabled reset state. + - Transactional clocks gating depends on whether they are idle. + - Initializes all units as busy (not idle). + - Clears each unit's `clk_hints` bit, which has no effect until + the unit becomes idle. + - Sets the unit's `idle_i` bit, which should disable the clock. + - Writes both values of the `jitter_enable` CSR. + + **Stimulus**: + - CSR writes to `clk_enables` and `clk_hints`. + - Setting `idle_i` clkmgr input. + + **Checks**: + - SVA assertions for peripheral clocks enable and disable + properties. + - Transactional clocks check SVA properties as follows: + - If the hint enables it, the clock becomes active. + - If the hint disables it but the unit is busy, the clock remains + active. + - If the hint disables it and the unit is idle, the clock stops. + - For transactional units the CSR `clk_hints_status` is checked + to correspond to `clk_hints` once the units are idle. + - Check in scoreboard the `jitter_en_o` output tracks updates of the + `jitter_enable` CSR. + ''' + stage: V1 + tests: ["clkmgr_smoke"] + } + { + name: peri_enables + desc: ''' + Peripheral clocks are disabled if its `clk_enables` bit is off, + or the corresponding `pwr_i.*_ip_clk_en` is off, and `scanmode_i` + is not `lc_ctrl_pkg::On`. + + This test runs multiple rounds which do the following: + - Randomize `pwr_i.usb_ip_clk_en` and `scanmode_i`, and the initial + setting of `clk_enables`. + - Send a CSR write to `clk_enables` with its initial value. + - Send a CSR write to `clk_enables` that flips all bits. + + It makes no sense to have `pwr_i.io_ip_clk_en` set to zero since + that would prevent the CPU from running and sending CSR updates. + + **Checks**: + - SVA assertions for peripheral clocks enable and disable + properties. + ''' + stage: V2 + tests: ["clkmgr_peri"] + } + { + name: trans_enables + desc: ''' + Transactional unit clocks are disabled if they are idle and + their CSR `clk_hints` bit is off, or `pwr_i.main_ip_clk_en` is off, + and `scanmode_i` is not `lc_ctrl_pkg::On`. + This test randomizes the initial setting of `idle_i` and the + desired value of `clk_hints`. Each round performs this sequence: + - Writes the desired value to CSR `clk_hints` and checks that the + CSR `clk_hints_status` reflects CSR `clk_hints` except for the + units not-idle. + - Marks all units as idle, and checks that `csr_hints_status` + matches `clk_hints`. + - Writes `clk_hints` to all ones and checks that `csr_hints_status` + is all ones. + - Writes `clk_hints` with its reset value. + + **Checks**: + - SVA assertions for transactional unit clocks described in + clkmgr_smoke. + ''' + stage: V2 + tests: ["clkmgr_trans"] + } + { + name: extclk + desc: ''' + Tests the functionality of enabling external clocks. + + - External clock is enabled if the `lc_clk_byp_req_i` input from + `lc_ctrl` is `lc_ctrl_pkg::On`. + - External clock is also be enabled when CSR `extclk_ctrl.sel` is + set to + `lc_ctrl_pkg::On` and the `lc_dtl_en_i` input from `lc_ctrl` is + `lc_ctrl_pkg::On`. + - Notice writes to the `extclk_ctrl.sel` register are ignored unless + the CSR `extclk_ctrl_regwen` is 1. + - A successful switch to external clocks due to `lc_clk_byl_req_i` + will cause the clkmgr to undo a divide by 2 for io_div4 and + io_div2 clocks except when `(scanmode_i == prim_mubi_pkg::MuBi4True)`. + - A software triggered switch to external clock will undo divides + by 2 if `extclk_ctrl.hi_speed_sel` is set to `prim_mubi_pkg::MuBi4True`. + + **Stimulus**: + - CSR writes to `extclk_ctrl` and `extclk_ctrl_regwen`. + - Setting `lc_hw_debug_en_i`, `lc_clk_byp_req_i`, and the handshake to + ast via `ast_clk_byp_req_o` and `ast_clk_byp_ack_i`. + - Setting `scanmode_i`. + + **Checks**: + Clock divider checks are done with SVA assertions. + - When the external clock is selected (and not defeated by + `scanmode_i` for scoreboard checks): + - The `clk_io_div2_powerup` output matches the `clk_io_powerup` + output. + - The `clk_io_div4_powerup` output matches the `clk_io_powerup` + output at half its frequency. + - When the external clock is not selected or division is defeated: + - The `clk_io_div2_powerup` output matches the `clk_io_powerup` + output at half its frequency. + - The `clk_io_div4_powerup` output matches the `clk_io_powerup` + output at a quarter of its frequency. + LC / AST handshake: + - When the external clock functionality is triggered the + `ast_clk_byp_req_o` output pin is set to `lc_ctrl_pkg::On`. + - When `ast_clk_byp_ack_i` is set to `lc_ctrl_pkg::On` in response + to a corresponding request: + - The clock dividers are stepped down, unless defeated by + `scanmode_i` being `lc_ctrl_pkg::On`. + - If the initial request was due to the assertion of the + `lc_clk_byp_req_i`, the `lc_clk_byp_ack_o` output is set to + `lc_ctrl_pkg::On`. + ''' + stage: V2 + tests: ["clkmgr_extclk"] + } + { + name: clk_status + desc: ''' + This tests the three `pwr_o.*_status` output ports, for the + `io`, `main`, and `usb` clocks. + + The `pwr_o.*_status` output must track the correspponding + `pwr_i.*_ip_clk_en` input. + + **Stimulus**: + - Randomize the `pwr_i.*_ip_clk_en` setting for each clock. + + **Check**: + - The checks are done in SVA at `clkmgr_pwrmgr_sva_if.sv`. + ''' + stage: V2 + tests: ["clkmgr_clk_status"] + } + { + name: jitter + desc: ''' + This tests the jitter functionality. + + The jitter functionality is implemented by the AST block, but + controlled by the `jitter_enable` CSR in this block. This CSR + directly drives the `jitter_en_o` output pin. + + **Stimulus**: + - CSR write to `jitter_enable`. + + **Check**: + - The `jitter_en_o` output pin reflects the `jitter_enable` CSR. + Test is implemented in the scoreboard, and is always running. + ''' + stage: V2 + tests: ["clkmgr_smoke"] + } + { + name: frequency + desc: '''This tests the frequency counters measured count functionality. + + These counters compute the number of cycles of each clock relative + to the aon timer, and compares it to the corresponding + thresholds written into the `*_meas_ctrl_shadowed` CSR. Measurements + beyond these thresholds trigger a recoverable alert and set a bit + in the `recov_err_code` CSR. Also, if the counters reach their + maximum value they don't wrap around. + + If clock calibration is lost, indicated by the `calib_rdy_i` input + being `prim_mubi_pkg::MuBi4False`, the measurements stop, no + error is triggered, and `measure_ctrl_regwen` is set to 1. + + **Stimulus**: + - Randomly set slow, correct, and fast interval for each counter + and test. + - Randomly set the `calib_rdy_i` input. + - Randomly trigger a clock saturation by forcing its cycle count + to be near its maximum value while counting. + + **Check**: + - Slow and fast intervals should cause a recoverable alert. + - Coverage collected per clock. + ''' + stage: V2 + tests: ["clkmgr_frequency"] + } + { + name: frequency_timeout + desc: '''This tests the frequency counters timeout functionality. + + These counters compute the number of cycles of some clock relative + to the aon timer. It should trigger a recoverable alert when there + is no valid measurement when enabled, leading to a timeout. This is + separate from the `frequenty` testpoint to simplify the test checks. + + **Stimulus**: + - Randomly stop measured clocks to trigger a timeout. + + **Check**: + - Timeout should cause a recoverable alert. + - Coverage collected per clock. + ''' + stage: V2 + tests: ["clkmgr_frequency_timeout"] + } + { + name: frequency_overflow + desc: '''This tests the overflow feature in prim_clock_meas. + + This needs to modify the state of the counter to trigger the + feature. + + **Stimulus**: + - Program the counter. Whenever it hits the value of 1, set it to + the range - 2. + + **Check**: + - The internal cnt_ovfl flop is set. + - The fast_o output should be set. + ''' + stage: V2 + tests: ["clkmgr_frequency"] + } + { + name: regwen + desc: '''This tests the behavior of the regwen CSRs. + + When a regwen is clear, any write to CSRs it locks are ignored. + Once a regwen is cleared, it will only be set again after a full + reset. + + **Stimulus**: + - Clear each regwen. + - Write to the corresponding locked CSRs. + + **Check**: + - The locked CSR value is not updated. + ''' + stage: V3 + tests: ["clkmgr_regwen"] + } + { + name: stress_all + desc: '''This runs random sequences in succession. + + Randomly chooses from the following sequences: + - clkmgr_extclk_vseq, + - clkmgr_frequency_timeout_vseq, + - clkmgr_frequency_vseq, + - clkmgr_peri_vseq, + - clkmgr_smoke_vseq, + - clkmgr_trans_vseq + ''' + stage: V2 + tests: ["clkmgr_stress_all"] + } + ] + + covergroups: [ + { + name: peri_cg + desc: ''' + Collects coverage for each peripheral clock. + + The peripheral clocks depend on a bit in the clk_enables CSR, + the ip_clk_en input from pwrmgr, and the scanmode input. + This collects the cross of them for each peripheral. + + FIXME This is collected in an array, one instance for each clock, + but the dvsim coverage flow doesn't yet support arrays. + ''' + } + { + name: trans_cg + desc: ''' + Collects coverage for each transactional unit clock. + + The transactional unit clocks depend on a bit in the clk_hints CSR, + the ip_clk_en input from pwrmgr, the respective idle input bit from + the unit, and the scanmode input. + This collects the cross of them for each transactional unit. + + FIXME This is collected in an array, one instance for each clock, + but the dvsim coverage flow doesn't yet support arrays. + ''' + } + { + name: extclk_cg + desc: ''' + Collects coverage for the external clock selection. + + The external clock selection depends on the `extclk_ctrl` CSR + fields `sel` and `hi_speed_sel`, and the `lc_hw_debug_en_i`, + `lc_clk_byp_req_i`, and `scanmode_i` input pins. This covergroup + collects their cross. + ''' + } + { + name: freq_measure_cg + desc: ''' + Collects coverage for the frequency measurement counters. + + The relevant information is whether it got an okay, slow, or + fast measurement, or a timeout. + ''' + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson new file mode 100644 index 0000000000000..03fdcf04513b5 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson @@ -0,0 +1,253 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_clkmgr + param_values: + { + src_clks: + { + main: + { + name: main + aon: false + freq: 100000000 + ref: false + } + io: + { + name: io + aon: false + freq: 96000000 + ref: false + } + usb: + { + name: usb + aon: false + freq: 48000000 + ref: false + } + aon: + { + name: aon + aon: true + freq: 200000 + ref: true + } + } + derived_clks: + { + io_div2: + { + name: io_div2 + aon: false + freq: 48000000 + ref: false + div: 2 + src: + { + name: io + aon: no + freq: "96000000" + ref: false + } + } + io_div4: + { + name: io_div4 + aon: false + freq: 24000000 + ref: false + div: 4 + src: + { + name: io + aon: no + freq: "96000000" + ref: false + } + } + } + typed_clocks: + { + ast_clks: + { + clk_main_i: + { + src_name: main + endpoint_ip: clkmgr_aon + } + clk_io_i: + { + src_name: io + endpoint_ip: clkmgr_aon + } + clk_usb_i: + { + src_name: usb + endpoint_ip: clkmgr_aon + } + clk_aon_i: + { + src_name: aon + endpoint_ip: clkmgr_aon + } + } + ft_clks: + { + clk_io_div4_powerup: + { + src_name: io_div4 + endpoint_ip: pwrmgr_aon + } + clk_aon_powerup: + { + src_name: aon + endpoint_ip: pwrmgr_aon + } + clk_main_powerup: + { + src_name: main + endpoint_ip: rstmgr_aon + } + clk_io_powerup: + { + src_name: io + endpoint_ip: rstmgr_aon + } + clk_usb_powerup: + { + src_name: usb + endpoint_ip: rstmgr_aon + } + clk_io_div2_powerup: + { + src_name: io_div2 + endpoint_ip: rstmgr_aon + } + clk_aon_infra: + { + src_name: aon + endpoint_ip: soc_proxy + } + clk_aon_secure: + { + src_name: aon + endpoint_ip: sensor_ctrl + } + clk_aon_peri: + { + src_name: aon + endpoint_ip: ast + } + clk_aon_timers: + { + src_name: aon + endpoint_ip: aon_timer_aon + } + } + rg_clks: + { + clk_io_div4_infra: + { + src_name: io_div4 + endpoint_ip: ast + } + clk_main_infra: + { + src_name: main + endpoint_ip: soc_proxy + } + clk_usb_infra: + { + src_name: usb + endpoint_ip: main + } + clk_io_div4_secure: + { + src_name: io_div4 + endpoint_ip: otp_ctrl + } + clk_main_secure: + { + src_name: main + endpoint_ip: otp_ctrl + } + clk_io_div4_timers: + { + src_name: io_div4 + endpoint_ip: rv_timer + } + } + sw_clks: + { + clk_io_div4_peri: + { + src_name: io_div4 + endpoint_ip: uart0 + } + clk_io_div2_peri: + { + src_name: io_div2 + endpoint_ip: spi_device + } + clk_usb_peri: + { + src_name: usb + endpoint_ip: ast + } + } + hint_clks: + { + clk_main_aes: + { + src_name: main + endpoint_ip: aes + } + clk_main_hmac: + { + src_name: main + endpoint_ip: hmac + } + clk_main_kmac: + { + src_name: main + endpoint_ip: kmac + } + clk_main_otbn: + { + src_name: main + endpoint_ip: otbn + } + } + } + hint_names: + { + clk_main_aes: HintMainAes + clk_main_hmac: HintMainHmac + clk_main_kmac: HintMainKmac + clk_main_otbn: HintMainOtbn + } + parent_child_clks: + { + main: + [ + main + ] + io: + [ + io + io_div2 + io_div4 + ] + usb: + [ + usb + ] + } + exported_clks: {} + number_of_clock_groups: 7 + topname: darjeeling + } +} diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/doc/checklist.md b/hw/top_darjeeling/ip_autogen/clkmgr/doc/checklist.md new file mode 100644 index 0000000000000..28ac5395584b9 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/doc/checklist.md @@ -0,0 +1,271 @@ +# CLKMGR Checklist + + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [CLKMGR peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done | [CLKMGR Design Spec](../README.md) +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | NA | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Done | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. +Documentation | [MISSING_FUNC][] | Done | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | +RTL | [STYLE_X][] | Done | +RTL | [CDC_SYNCMACRO][] | Done | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [AREA_CHECK][] | Done | +Code Quality | [TIMING_CHECK][] | Done | +Security | [SEC_CM_DOCUMENTED][] | Done | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | N/A | +Security | [SEC_CM_NON_RESET_FLOPS][] | Done | +Security | [SEC_CM_SHADOW_REGS][] | Done | +Security | [SEC_CM_RTL_REVIEWED][] | Done | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Done | + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Done | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | With waivers approved by TC on 2024-08-08 +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_RTL][] | Done | +Review | [REVIEW_DELETED_FF][] | Done | +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | matutem@, vogelpi@, adk@ +Review | Signoff date | Done | 2024-08-08 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [CLKMGR DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Done | [CLKMGR Testplan](../dv/README.md#testplan) +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | Done | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | Done | +Tests | [SIM_SMOKE_TEST_PASSING][] | Done | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | NA | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | NA | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | xcelium +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done | +Regression | [FPV_REGRESSION_SETUP][] | NA | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | NA | +Review | [DESIGN_SPEC_REVIEWED][] | Done | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Done | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | Done | +Tests | [SIM_ALL_TESTS_PASSING][] | Done | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | NA | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | NA | +Tests | [SIM_FW_SIMULATED][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Done | +Coverage | [SIM_CODE_COVERAGE_V2][] | Done | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Done | +Coverage | [FPV_CODE_COVERAGE_V2][] | NA | +Coverage | [FPV_COI_COVERAGE_V2][] | NA | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | NA | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done | +Tests | [FPV_SEC_CM_VERIFIED][] | Done | +Tests | [SIM_SEC_CM_VERIFIED][] | Done | +Coverage | [SIM_COVERAGE_REVIEWED][] | Done | +Review | [SEC_CM_DV_REVIEWED][] | Done | + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/doc/clkmgr_block_diagram.svg b/hw/top_darjeeling/ip_autogen/clkmgr/doc/clkmgr_block_diagram.svg new file mode 100644 index 0000000000000..b3977b5124cae --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/doc/clkmgr_block_diagram.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/doc/clkmgr_rst_domain.svg b/hw/top_darjeeling/ip_autogen/clkmgr/doc/clkmgr_rst_domain.svg new file mode 100644 index 0000000000000..2e5276cc7c218 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/doc/clkmgr_rst_domain.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/doc/example_chip_partition.svg b/hw/top_darjeeling/ip_autogen/clkmgr/doc/example_chip_partition.svg new file mode 100644 index 0000000000000..2c8bc65081b17 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/doc/example_chip_partition.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/doc/interfaces.md b/hw/top_darjeeling/ip_autogen/clkmgr/doc/interfaces.md new file mode 100644 index 0000000000000..b0b189dd4a62e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/doc/interfaces.md @@ -0,0 +1,59 @@ +# Hardware Interfaces + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`clkmgr`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: **`clk_main_i`**, **`clk_io_i`**, **`clk_usb_i`**, **`clk_aon_i`**, **`clk_io_div2_i`**, **`clk_io_div4_i`** +- Bus Device Interfaces (TL-UL): **`tl`** +- Bus Host Interfaces (TL-UL): *none* +- Peripheral Pins for Chip IO: *none* +- Interrupts: *none* + +## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:------------------|:-------------------------|:--------|:------|--------:|:---------------------------------------------------------| +| clocks | clkmgr_pkg::clkmgr_out | uni | req | 1 | | +| cg_en | clkmgr_pkg::clkmgr_cg_en | uni | req | 1 | | +| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| io_clk_byp_req | prim_mubi_pkg::mubi4 | uni | req | 1 | | +| io_clk_byp_ack | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | +| all_clk_byp_req | prim_mubi_pkg::mubi4 | uni | req | 1 | | +| all_clk_byp_ack | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | +| hi_speed_sel | prim_mubi_pkg::mubi4 | uni | req | 1 | | +| div_step_down_req | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | +| lc_clk_byp_req | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_clk_byp_ack | lc_ctrl_pkg::lc_tx | uni | req | 1 | | +| jitter_en | prim_mubi_pkg::mubi4 | uni | req | 1 | | +| pwr | pwr_clk | req_rsp | rsp | 1 | | +| idle | prim_mubi_pkg::mubi4 | uni | rcv | 4 | | +| calib_rdy | prim_mubi_pkg::mubi4 | uni | rcv | 1 | Indicates clocks are calibrated and frequencies accurate | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | + +## Security Alerts + +| Alert Name | Description | +|:-------------|:----------------------------------------------------------------------------------| +| recov_fault | This recoverable alert is triggered when there are measurement errors. | +| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. | + +## Security Countermeasures + +| Countermeasure ID | Description | +|:-------------------------------------------|:-------------------------------------------------------------| +| CLKMGR.BUS.INTEGRITY | End-to-end bus integrity scheme. | +| CLKMGR.TIMEOUT.CLK.BKGN_CHK | Background check for clock timeout. | +| CLKMGR.MEAS.CLK.BKGN_CHK | Background check for clock frequency. | +| CLKMGR.MEAS.CONFIG.SHADOW | Measurement configurations are shadowed. | +| CLKMGR.IDLE.INTERSIG.MUBI | Idle inputs are multibit encoded. | +| CLKMGR.LC_CTRL.INTERSIG.MUBI | The life cycle control signals are multibit encoded. | +| CLKMGR.LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI | The life cycle clock req/ack signals are multibit encoded. | +| CLKMGR.CLK_HANDSHAKE.INTERSIG.MUBI | The external clock req/ack signals are multibit encoded. | +| CLKMGR.DIV.INTERSIG.MUBI | Divider step down request is multibit encoded. | +| CLKMGR.JITTER.CONFIG.MUBI | The jitter enable configuration is multibit encoded. | +| CLKMGR.IDLE.CTR.REDUN | Idle counter is duplicated. | +| CLKMGR.MEAS.CONFIG.REGWEN | The measurement controls protected with regwen. | +| CLKMGR.CLK_CTRL.CONFIG.REGWEN | Software controlled clock requests are proteced with regwen. | + + + diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/doc/programmers_guide.md b/hw/top_darjeeling/ip_autogen/clkmgr/doc/programmers_guide.md new file mode 100644 index 0000000000000..eea3386a2e234 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/doc/programmers_guide.md @@ -0,0 +1,17 @@ +# Programmer's Guide + +There are in general only two software controllable functions in the clock manager. + + +## Transactional Clock Hints + +To enable a transactional clock, set the corresponding hint in [`CLK_HINTS`](registers.md#clk_hints) to `1`. +To disable a transactional clock, set the corresponding hint in [`CLK_HINTS`](registers.md#clk_hints) to `0`. +Note, a `0` does not indicate clock is actually disabled, software can thus check [`CLK_HINTS_STATUS`](registers.md#clk_hints_status) for the actual state of the clock. + +## Peripheral Clock Controls +To control peripheral clocks, directly change the bits in [`CLK_ENABLES`](registers.md#clk_enables). + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_clkmgr.h) diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/doc/registers.md b/hw/top_darjeeling/ip_autogen/clkmgr/doc/registers.md new file mode 100644 index 0000000000000..9143e44022560 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/doc/registers.md @@ -0,0 +1,421 @@ +# Registers + + +## Summary + +| Name | Offset | Length | Description | +|:-------------------------------------------------------------------|:---------|---------:|:---------------------------------------------------------------------------| +| clkmgr.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | +| clkmgr.[`EXTCLK_CTRL_REGWEN`](#extclk_ctrl_regwen) | 0x4 | 4 | External clock control write enable | +| clkmgr.[`EXTCLK_CTRL`](#extclk_ctrl) | 0x8 | 4 | Select external clock | +| clkmgr.[`EXTCLK_STATUS`](#extclk_status) | 0xc | 4 | Status of requested external clock switch | +| clkmgr.[`JITTER_REGWEN`](#jitter_regwen) | 0x10 | 4 | Jitter write enable | +| clkmgr.[`JITTER_ENABLE`](#jitter_enable) | 0x14 | 4 | Enable jittery clock | +| clkmgr.[`CLK_ENABLES`](#clk_enables) | 0x18 | 4 | Clock enable for software gateable clocks. | +| clkmgr.[`CLK_HINTS`](#clk_hints) | 0x1c | 4 | Clock hint for software gateable transactional clocks during active mode. | +| clkmgr.[`CLK_HINTS_STATUS`](#clk_hints_status) | 0x20 | 4 | Since the final state of !!CLK_HINTS is not always determined by software, | +| clkmgr.[`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) | 0x24 | 4 | Measurement control write enable | +| clkmgr.[`IO_DIV4_MEAS_CTRL_EN`](#io_div4_meas_ctrl_en) | 0x28 | 4 | Enable for measurement control | +| clkmgr.[`IO_DIV4_MEAS_CTRL_SHADOWED`](#io_div4_meas_ctrl_shadowed) | 0x2c | 4 | Configuration controls for io_div4 measurement. | +| clkmgr.[`MAIN_MEAS_CTRL_EN`](#main_meas_ctrl_en) | 0x30 | 4 | Enable for measurement control | +| clkmgr.[`MAIN_MEAS_CTRL_SHADOWED`](#main_meas_ctrl_shadowed) | 0x34 | 4 | Configuration controls for main measurement. | +| clkmgr.[`USB_MEAS_CTRL_EN`](#usb_meas_ctrl_en) | 0x38 | 4 | Enable for measurement control | +| clkmgr.[`USB_MEAS_CTRL_SHADOWED`](#usb_meas_ctrl_shadowed) | 0x3c | 4 | Configuration controls for usb measurement. | +| clkmgr.[`RECOV_ERR_CODE`](#recov_err_code) | 0x40 | 4 | Recoverable Error code | +| clkmgr.[`FATAL_ERR_CODE`](#fatal_err_code) | 0x44 | 4 | Error code | + +## ALERT_TEST +Alert Test Register +- Offset: `0x0` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "recov_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:-------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | +| 0 | wo | 0x0 | recov_fault | Write 1 to trigger one alert event of this kind. | + +## EXTCLK_CTRL_REGWEN +External clock control write enable +- Offset: `0x4` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, the value of [`EXTCLK_CTRL`](#extclk_ctrl) can be set. When 0, writes to [`EXTCLK_CTRL`](#extclk_ctrl) have no effect. | + +## EXTCLK_CTRL +Select external clock +- Offset: `0x8` +- Reset default: `0x99` +- Reset mask: `0xff` +- Register enable: [`EXTCLK_CTRL_REGWEN`](#extclk_ctrl_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "SEL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HI_SPEED_SEL", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-------------------------------------------| +| 31:8 | | | Reserved | +| 7:4 | rw | 0x9 | [HI_SPEED_SEL](#extclk_ctrl--hi_speed_sel) | +| 3:0 | rw | 0x9 | [SEL](#extclk_ctrl--sel) | + +### EXTCLK_CTRL . HI_SPEED_SEL +A value of kMultiBitBool4True selects nominal speed external clock. +All other values selects low speed clocks. + +Note this field only has an effect when the [`EXTCLK_CTRL.SEL`](#extclk_ctrl) field is set to +kMultiBitBool4True. + +Nominal speed means the external clock is approximately the same frequency as +the internal oscillator source. When this option is used, all clocks operate +at roughly the nominal frequency. + +Low speed means the external clock is approximately half the frequency of the +internal oscillator source. When this option is used, the internal dividers are +stepped down. As a result, previously undivided clocks now run at half frequency, +while previously divided clocks run at roughly the nominal frequency. + +See external clock switch support in documentation for more details. + +### EXTCLK_CTRL . SEL +When the current value is not kMultiBitBool4True, writing a value of kMultiBitBool4True +selects external clock as clock for the system. Writing any other value has +no impact. + +When the current value is kMultiBitBool4True, writing a value of kMultiBitBool4False +selects internal clock as clock for the system. Writing any other value during this stage +has no impact. + +While this register can always be programmed, it only takes effect when debug functions are enabled +in life cycle TEST, DEV or RMA states. + +## EXTCLK_STATUS +Status of requested external clock switch +- Offset: `0xc` +- Reset default: `0x9` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "ACK", "bits": 4, "attr": ["ro"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:---------------------------| +| 31:4 | | | Reserved | +| 3:0 | ro | 0x9 | [ACK](#extclk_status--ack) | + +### EXTCLK_STATUS . ACK +When [`EXTCLK_CTRL.SEL`](#extclk_ctrl) is set to kMultiBitBool4True, this field reflects +whether the clock has been switched the external source. + +kMultiBitBool4True indicates the switch is complete. +kMultiBitBool4False indicates the switch is either not possible or still ongoing. + +## JITTER_REGWEN +Jitter write enable +- Offset: `0x10` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, the value of [`JITTER_ENABLE`](#jitter_enable) can be changed. When 0, writes have no effect. | + +## JITTER_ENABLE +Enable jittery clock +- Offset: `0x14` +- Reset default: `0x9` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3:0 | rw | 0x9 | VAL | Enable jittery clock. A value of kMultiBitBool4False disables the jittery clock, while all other values enable jittery clock. | + +## CLK_ENABLES +Clock enable for software gateable clocks. +These clocks are directly controlled by software. +- Offset: `0x18` +- Reset default: `0x7` +- Reset mask: `0x7` + +### Fields + +```wavejson +{"reg": [{"name": "CLK_IO_DIV4_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_IO_DIV2_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_USB_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------|:---------------------------------------------------------------| +| 31:3 | | | | Reserved | +| 2 | rw | 0x1 | CLK_USB_PERI_EN | 0 CLK_USB_PERI is disabled. 1 CLK_USB_PERI is enabled. | +| 1 | rw | 0x1 | CLK_IO_DIV2_PERI_EN | 0 CLK_IO_DIV2_PERI is disabled. 1 CLK_IO_DIV2_PERI is enabled. | +| 0 | rw | 0x1 | CLK_IO_DIV4_PERI_EN | 0 CLK_IO_DIV4_PERI is disabled. 1 CLK_IO_DIV4_PERI is enabled. | + +## CLK_HINTS +Clock hint for software gateable transactional clocks during active mode. +During low power mode, all clocks are gated off regardless of the software hint. + +Transactional clocks are not fully controlled by software. Instead software provides only a disable hint. + +When software provides a disable hint, the clock manager checks to see if the associated hardware block is idle. +If the hardware block is idle, then the clock is disabled. +If the hardware block is not idle, the clock is kept on. + +For the enable case, the software hint is immediately honored and the clock turned on. Hardware does not provide any +feedback in this case. +- Offset: `0x1c` +- Reset default: `0xf` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "CLK_MAIN_AES_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------------|:-------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3 | rw | 0x1 | CLK_MAIN_OTBN_HINT | 0 CLK_MAIN_OTBN can be disabled. 1 CLK_MAIN_OTBN is enabled. | +| 2 | rw | 0x1 | CLK_MAIN_KMAC_HINT | 0 CLK_MAIN_KMAC can be disabled. 1 CLK_MAIN_KMAC is enabled. | +| 1 | rw | 0x1 | CLK_MAIN_HMAC_HINT | 0 CLK_MAIN_HMAC can be disabled. 1 CLK_MAIN_HMAC is enabled. | +| 0 | rw | 0x1 | CLK_MAIN_AES_HINT | 0 CLK_MAIN_AES can be disabled. 1 CLK_MAIN_AES is enabled. | + +## CLK_HINTS_STATUS +Since the final state of [`CLK_HINTS`](#clk_hints) is not always determined by software, +this register provides read feedback for the current clock state. + +- Offset: `0x20` +- Reset default: `0xf` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "CLK_MAIN_AES_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------------|:---------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3 | ro | 0x1 | CLK_MAIN_OTBN_VAL | 0 CLK_MAIN_OTBN is disabled. 1 CLK_MAIN_OTBN is enabled. | +| 2 | ro | 0x1 | CLK_MAIN_KMAC_VAL | 0 CLK_MAIN_KMAC is disabled. 1 CLK_MAIN_KMAC is enabled. | +| 1 | ro | 0x1 | CLK_MAIN_HMAC_VAL | 0 CLK_MAIN_HMAC is disabled. 1 CLK_MAIN_HMAC is enabled. | +| 0 | ro | 0x1 | CLK_MAIN_AES_VAL | 0 CLK_MAIN_AES is disabled. 1 CLK_MAIN_AES is enabled. | + +## MEASURE_CTRL_REGWEN +Measurement control write enable +- Offset: `0x24` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, the value of the measurement control can be set. When 0, writes have no effect. | + +## IO_DIV4_MEAS_CTRL_EN +Enable for measurement control +- Offset: `0x28` +- Reset default: `0x9` +- Reset mask: `0xf` +- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------| +| 31:4 | | | | Reserved | +| 3:0 | rw | 0x9 | EN | Enable measurement for io_div4 | + +## IO_DIV4_MEAS_CTRL_SHADOWED +Configuration controls for io_div4 measurement. + +The threshold fields are made wider than required (by 1 bit) to ensure +there is room to adjust for measurement inaccuracies. +- Offset: `0x2c` +- Reset default: `0x6e82` +- Reset mask: `0xffff` +- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "HI", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------------------------------| +| 31:16 | | | | Reserved | +| 15:8 | rw | 0x6e | LO | Min threshold for io_div4 measurement | +| 7:0 | rw | 0x82 | HI | Max threshold for io_div4 measurement | + +## MAIN_MEAS_CTRL_EN +Enable for measurement control +- Offset: `0x30` +- Reset default: `0x9` +- Reset mask: `0xf` +- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------| +| 31:4 | | | | Reserved | +| 3:0 | rw | 0x9 | EN | Enable measurement for main | + +## MAIN_MEAS_CTRL_SHADOWED +Configuration controls for main measurement. + +The threshold fields are made wider than required (by 1 bit) to ensure +there is room to adjust for measurement inaccuracies. +- Offset: `0x34` +- Reset default: `0x7a9fe` +- Reset mask: `0xfffff` +- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "HI", "bits": 10, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------| +| 31:20 | | | | Reserved | +| 19:10 | rw | 0x1ea | LO | Min threshold for main measurement | +| 9:0 | rw | 0x1fe | HI | Max threshold for main measurement | + +## USB_MEAS_CTRL_EN +Enable for measurement control +- Offset: `0x38` +- Reset default: `0x9` +- Reset mask: `0xf` +- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------| +| 31:4 | | | | Reserved | +| 3:0 | rw | 0x9 | EN | Enable measurement for usb | + +## USB_MEAS_CTRL_SHADOWED +Configuration controls for usb measurement. + +The threshold fields are made wider than required (by 1 bit) to ensure +there is room to adjust for measurement inaccuracies. +- Offset: `0x3c` +- Reset default: `0x1ccfa` +- Reset mask: `0x3ffff` +- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "HI", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------| +| 31:18 | | | | Reserved | +| 17:9 | rw | 0xe6 | LO | Min threshold for usb measurement | +| 8:0 | rw | 0xfa | HI | Max threshold for usb measurement | + +## RECOV_ERR_CODE +Recoverable Error code +- Offset: `0x40` +- Reset default: `0x0` +- Reset mask: `0x7f` + +### Fields + +```wavejson +{"reg": [{"name": "SHADOW_UPDATE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_DIV4_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "MAIN_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "USB_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_DIV4_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "MAIN_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "USB_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------|:---------------------------------------------------------| +| 31:7 | | | | Reserved | +| 6 | rw1c | 0x0 | USB_TIMEOUT_ERR | usb has timed out. | +| 5 | rw1c | 0x0 | MAIN_TIMEOUT_ERR | main has timed out. | +| 4 | rw1c | 0x0 | IO_DIV4_TIMEOUT_ERR | io_div4 has timed out. | +| 3 | rw1c | 0x0 | USB_MEASURE_ERR | usb has encountered a measurement error. | +| 2 | rw1c | 0x0 | MAIN_MEASURE_ERR | main has encountered a measurement error. | +| 1 | rw1c | 0x0 | IO_DIV4_MEASURE_ERR | io_div4 has encountered a measurement error. | +| 0 | rw1c | 0x0 | SHADOW_UPDATE_ERR | One of the shadow registers encountered an update error. | + +## FATAL_ERR_CODE +Error code +- Offset: `0x44` +- Reset default: `0x0` +- Reset mask: `0x7` + +### Fields + +```wavejson +{"reg": [{"name": "REG_INTG", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "IDLE_CNT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHADOW_STORAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------------|:---------------------------------------------------------| +| 31:3 | | | | Reserved | +| 2 | ro | 0x0 | SHADOW_STORAGE_ERR | One of the shadow registers encountered a storage error. | +| 1 | ro | 0x0 | IDLE_CNT | One of the idle counts encountered a duplicate error. | +| 0 | ro | 0x0 | REG_INTG | Register file has experienced a fatal integrity error. | + + + diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/doc/theory_of_operation.md b/hw/top_darjeeling/ip_autogen/clkmgr/doc/theory_of_operation.md new file mode 100644 index 0000000000000..5d81a4805fda5 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/doc/theory_of_operation.md @@ -0,0 +1,298 @@ +# Theory of Operation + +Clock management in OpenTitan is divided into groups. +Each group has specific attributes and controls whether software is allowed to influence individual clocks during the active power state. +For low power states, please see [power manager](../../pwrmgr/README.md). + +The grouping is derived from the chip partition and related security properties. +For illustrative purposes, this document uses the following assumed chip partition + +![Example chip partition](example_chip_partition.svg) + +The actual partition may differ per design, however the general principles are assumed to be the same. +Each group can be made up of more than 1 source clock. +The clocks themselves may be asynchronous - the grouping is thus a logical grouping instead of a physical one. + +The grouping is summarized in the table below and described in more detail afterwards. +The table shows the group name, the modules that belong to each group, and whether SW can directly (via register control) or indirectly (via wait-for-interrupt) influence the state of the clock in the form of clock gating. + +| Group | Frequencies | Modules | Software | Wait for Interrupt | +| ------------- | ------------------------------ | -------------------------------------------------------------- | -------------- | ------------------ | +| Power-up | 100~200KHz, 24MHz | Clock Manager, Power Manager, Reset Manager, Pinmux | No | No | +| Transactional | ~100MHz | Aes, Kmac, Hmac, Key Manager, Otbn | Yes (1) | Yes (2) | +| Infrastructural | 24MHz, ~100MHz | Fabric, Fabric gaskets (iopmp), Memories | No | Yes (3) | +| Security | 24MHz, ~100MHz | Alert handler, Entropy, Life cycle, Plic, Sensors | No | No | +| Peripheral | 24MHz, 48MHz, 96MHz | I2c, Spi, Uart, Usb, others | Yes | Yes | +| Timers | 100-200KHz, 24MHz | AON timers, Timers, Watchdog | No | No | + +* 1 - Transactional clock group's software control is only a software hint. +* 2 - Transactional clock group's wait-for-interrupt control is only a hint. +* 3 - May require additional complexity to handle multi-host (non-wait-for-interrupt) scenarios + +## Power-up Clock Group + +The group refers to modules responsible for power up, such as power, reset and clock managers. +Large portions of these modules operate to release clocks and resets for the rest of the design, thus cannot operate on gated versions of the clocks themselves. +They are the only group running clocks directly from the source. +All follow groups are derived after root clock gating. +See [block diagram](#block-diagram) for more details. + +## Transactional Clock Group + +This group refers to the collection of modules that are transactional by nature (example: `Hmac` / `Aes` / `Kmac`). +This means these modules perform specific tasks (for example encrypt, decrypt or hashing). +While performing these tasks, it is unsafe to manipulate or change the clocks. +Once these tasks are complete, the clocks can be safely shut-off. + +To ensure such behavior on the clocks, The final clock enable is qualified with an `Idle` indication to signify that a transaction is ongoing and manipulation of the clock is not permitted. +The `Idle` signal must be sourced from the transactional modules and sent to the clock manager. + +For this group software can only express its intent to shut-off, and does not have full control over the final state. +This intent is indicated with a register in the clock manager register file, see [`CLK_HINTS`](registers.md#clk_hints). + +Even when the hint is set, the `Idle` does not directly manipulate the clock. +When an idle indication is received, the `clkmgr` counts for a period of 10 local clocks to ensure the idle was not a glitch. + +Wait-for-interrupt based control is already a software hint, it can thus be applied to this group with the same `Idle` requirement. + +For modules in this group, each module can be individually influenced, and thus each has its own dedicated clock gating logic. +The added benefit of allowing software control in this group is to save power, as some transactional modules can be both power and area hungry. + +## Infrastructure Clock Group + +This group refers to the collection of modules that support infrastructure functions. + +If the clocks to these modules are turned off, there may not be a way to turn them back on and could thus result in system deadlock. +This includes but is not limited to: +* Turning off fabric / gasket clocks, and thus having no way to access the fabric and resume the clock. +* Turning off memory clocks such that there is no way to execute code that would resume the clocks. + +For this group, there is no reason to allow software control over the clocks, as it could be used to create a system deadlock where after disabling infrastructure clocks there is no way to turn them back on. +Wait-for-interrupt controls however can be used, as long as there is a way to break the processor out of wait-for-interrupt and handle other bus hosts, while also separating the functional portions from bus access. +See Wait-for-interrupt clock gating for more details. + +## Security Clock Group + +The security clock group is made up of security modules that either have background functions (entropy, alert manager, sensors) or perform critical security functions where disabling clocks could have unexpected side effects (life cycle, otp, pinmux, plic). + +For this group, no software influence over the clock state is allowed during the active state. +The clocks are always running as long as the source is on. + +This group is not functionally identical to the power-up group. +The power-up group is run on clocks directly from the clock source, while the security group is derived after root clock gating. + +## Timer Clock Group + +The timer clock group is composed of modules that track time for various purposes. +As influencing time can change the perspective of software and potentially reveal security vulnerabilities, the clock state for these modules cannot be directly or indirectly influenced by software. + +Functionally, this group is identical to the security group. + +## Peripheral Clock Group + +The peripheral clock group is composed of I/O peripherals modules. +By their nature, I/O peripherals are both transactional and most of the time not security critical - so long as proper care is taken to sandbox peripherals from the system. + +These modules can be both directly and indirectly controlled by software. +The controls can also be individual to each peripheral. + +## Wait-for-Interrupt (wfi) Gating + +Wait-for-interrupt clock gating refers to the mechanism of using a processor’s sleep indication to actively gate off module clocks. +Of the groups enumerated, only transactional, infrastructural and peripheral groups can be influenced by `wfi`. + +As `wfi` is effectively a processor clock request, there are subtleties related to its use. +The interaction with each clock group is briefly described below. + +### Transactional Clock Group + +While `wfi` gating can be applied to this group, the modules in this category are already expected to be turned off and on by software depending on usage. +Specifically, these modules are already completely managed by software when not in use, thus may not see significant benefit from `wfi` gating. + +### Peripheral Clock Group + +Since peripherals, especially those in device mode, are often operated in an interrupt driven way, the peripheral's core operating clock frequently must stay alive even if the processor is asleep. +This implies that in order for peripherals to completely support `wfi` clock gating, they must be split between functional clocks and bus clocks. + +The bus clocks represent the software interface and can be turned off based on `wfi gating`, while the functional clocks should be kept running to ensure outside activity can be captured and interrupts created. +In this scenario, it is important to ensure the functional clocks are responsible for creating interrupts and not the bus clocks, as the latter may not be available during `wfi`. + +This division may only be beneficial for peripherals where register and local fabric size is large relative to the functional component. + +### Infrastructural Clock Group + +This clock group matches `wfi` functionality well. +Most infrastructural components such as fabric, gaskets and memories, have no need to be clocked when the processor is idle. +Some components such as flash controller however would also need to be split into bus and functional halves to support long, background activities while the processor is idle. + +However, there are additional complications. +In systems where the processor is not the only bus host, `wfi` can only be used as the software request and not final clock state decision. +Hardware driven requests, such as those coming from a `dma` or any peripheral driven bus host, would also need to be included as part of the equation. +Further, since it is possible hardware may issue requests at the boundary of a clock state changes, additional fabric gaskets would be required to protect hosts when destinations are temporarily clocked off. +The bus requests themselves thus become dynamic clock request signals to help enable components in its path. + +There is thus a moderate design and high verification cost to supporting `wfi` gating for the infrastructural group. + +## Block Diagram + +The following is a high level block diagram of the clock manager. + +![Clock Manager Block Diagram](clkmgr_block_diagram.svg) + +### Reset Domains + +Since the function of the clock manager is tied closely into the power-up behavior of the device, the reset domain selection must also be purposefully done. +To ensure that default clocks are available for the [power manager to release resets and initialize memories](../../pwrmgr/README.md#fast-clock-domain-fsm), the clock dividers inside the clock manager directly use `por` (power-on-reset) derived resets. +This ensures that the root clocks are freely running after power-up and its status can be communicated to the `pwrmgr` regardless of any other activity in the device. + +The other functions inside the clock manager operate on the `life cycle reset` domain. +This ensures that other clock manager functions still release early relative to most functions in the system, and that a user or escalation initiated reset still restores the clock manager to a default clean slate. + +The escalation reset restoration is especially important as the clock manager can generate fatal faults that lead to escalation. +If there were not a mechanism that allows escalation to clear the original fault, the system would simply remain in a faulted state until a user initiated a `por` event. + +For a detailed breakdown between `por` and `life cycle` resets, please see the [reset manager](../../rstmgr/README.md). + +The following diagram enhances the block diagram to illustrate the overall reset domains of the clock manager. +![Clock Manager Block Diagram](clkmgr_rst_domain.svg) + +### Clock Gated Indications for Alert Handler + +The alert handler needs to know the status of the various clock domains in the system to avoid false alert indications due to the ping mechanism. +To that end, the clock manager outputs a 4bit MuBi signal for each clock domain that indicates whether its clock is active. +For more information on this mechanism, see [alert handler documentation](../../alert_handler/doc/theory_of_operation.md#low-power-management-of-alert-channels). + +## Design Details + +### Root Clock Gating and Interface with Power Manager + +All clock groups except the power-up group run from gated source clocks. +The source clocks are gated off during low power states as controlled by the power manager. +When the power manager makes a clock enable request, the clock manager ensures all root clock gates are enabled before acknowledging. +Likewise, when the power manager makes a clock disable request, the clock manager ensures all root clock gates off disabled before acknowledging. + +Note, the power manager's request to turn off clocks supersedes all other local controls in the clock manager. +This means even if a particular clock is turned on by the clock manager (for example a transactional unit that is ongoing or a peripheral that is enabled), the power manager requests will still turn clocks on / off at the root. + +This makes it software's responsibility to ensure low power entry requests (which can only be initiated by software) do not conflict with any ongoing activities controlled by software. +For example, software should ensure that Aes / Otbn activities have completed before initializing a low power entry process. + +### Clock Division + +Not all peripherals run at the full IO clock speed, hence the IO clock is divided down by 2x and 4x in normal operation. +This division ratio can be modified to 1x and 2x when switching to an external clock, since the external clock may be slower than the internal clock source. +See also [external clock switch support](#external-clock-switch-support). + +The divided clock is not assumed to be synchronous with its source and is thus treated like another asynchronous branch. +Further, the clock dividers are hardwired and have no software control, this is to further ensure there are no simple paths for faulty or malicious software to tamper. + +Note that for debug purposes, `ast` can also request a change in the clock division ratio via a dedicated hardware interface (`div_step_down_req_i`). + +### Wait-for-Interrupt Support + +Given the marginal benefits and the increased complexity of `wfi` support, the first version of this design does not support `wfi` gating. +All `wfi CG` modules in the block diagram are thus drawn with dashed lines to indicate it can be theoretically supported but currently not implemented. + +It may be added for future more complex systems where there is a need to tightly control infrastructural power consumption as a result from clocks. + +### External Clock Switch Support + +Clock manager supports the ability to request root clocks switch to an external clock. +There are two occasions where this is required: +- Life cycle transition from `RAW` / `TEST_LOCKED*` to `TEST_UNLOCKED*` [states](../../../../ip/lc_ctrl/README.md#clk_byp_req). +- Software request for external clocks during normal functional mode. + + +#### Life Cycle Requested External Clock + +The life cycle controller only requests the io clock input to be switched. +When the life cycle controller requests external clock, a request signal `lc_clk_byp_req_i` is sent from `lc_ctrl` to `clkmgr`. +`clkmgr` then forwards the request to `ast` through `io_clk_byp_req_o`, which performs the actual clock switch and is acknowledged through `io_clk_byp_ack_i`. +When the clock switch is complete, the clock dividers are stepped down by a factor of 2 and the life cycle controller is acknowledged through `lc_clk_byp_ack_o`. + +Note that this division factor change is done since the external clock is expected to be 48MHz while the nominal frequency of the internal clock is 96MHz. +I.e. this division factor change keeps the nominal frequencies of the div_2 and div_4 clocks stable at 48Mhz and 24MHz, respectively. +See [Clock Frequency Summary](#clock-frequency-summary) for more details. + +#### Software Requested External Clocks + +Unlike the life cycle controller, a software request for external clocks switches all clock sources to an external source. +Software request for external clocks is not always valid. +Software is only able to request for external clocks when hardware debug functions are [allowed](../../../../ip/lc_ctrl/README.md#hw_debug_en). + +When software requests the external clock switch, it also provides an indication how fast the external clock is through [`EXTCLK_CTRL.HI_SPEED_SEL`](registers.md#extclk_ctrl). +There are two supported clock speeds: +* High speed - external clock is close to nominal speeds (e.g. external clock is 96MHz and nominal frequency is 96MHz-100MHz) +* Low speed - external clock is half of nominal speeds (e.g. external clock is 48MHz and nominal frequency is 96MHz-100MHz) + +When software requests external clock, the register bit [`EXTCLK_CTRL.SEL`](registers.md#extclk_ctrl) is written. +If hardware debug functions are allowed, the `clkmgr` sends a request signal `all_clk_byp_req_o` to `ast` and is acknowledged through `all_clk_byp_ack_i`. + +If software requests a low speed external clock, at the completion of the switch, internal dividers are also stepped down. +When the divider is stepped down, a divide-by-4 clock becomes divide-by-2 clock , and a divide-by-2 becomes a divide-by-1 clock. + +If software requests a high speed external clock, the dividers are kept as is. + + +Note, software external clock switch support is meant to be a debug / evaluation feature, and should not be used in conjunction with the clock frequency and timeout measurement features. +This is because if the clock frequency suddenly changes, the thresholds used for timeout / measurement checks will no longer apply. +There is currently no support in hardware to dynamically synchronize a threshold change to the expected frequency. + +#### Clock Frequency Summary + +The table below summarises the valid modes and the settings required. + +| Mode | `lc_clk_byp_req_i` | `extclk_ctrl.sel` | `extclk_ctrl.hi_speed_sel` | life cycle state | +| ------------- | --------------------- | ----------------- | ----------------------------| -------------------------------| +| Life cycle in `RAW`, `TEST*` and `RMA` states | `lc_ctrl_pkg::On` | `kMultiBit4False` | Don't care | Controlled by `lc_ctrl` | +| Internal Clocks | `lc_ctrl_pkg::Off` | `kMultiBit4False` | Don't care | All | +| Software external high speed | `lc_ctrl_pkg::Off` | `kMultiBit4True` | `kMultiBit4True` | `TEST_UNLOCKED*`, `DEV`, `RMA` | +| Software external low speed | `lc_ctrl_pkg::Off` | `kMultiBit4True` | `kMultiBit4False` | `TEST_UNLOCKED*`, `DEV`, `RMA` | + +The table below summarizes the frequencies in each mode. +This table assumes that the internal clock source is 96MHz. +This table also assumes that high speed external clock is 96MHz, while low speed external clock is 48MHz. + +| Mode | External Clock Frequency | div_1_clock | div_2_clock | div_4_clock | +| ------------- | ------------------------ | ------------- | --------------- | -------------| +| Internal Clocks | Not applicable | 96MHz | 48MHz | 24MHz | +| Life cycle transition | 48MHz | 48MHz | 48MHz | 24MHz | +| Software external high speed | 96MHz | 96MHz | 48MHz | 24MHz | +| Software external low speed | 48MHz | 48MHz | 48MHz | 24MHz | + +As can be seen from the table, the external clock switch scheme prioritizes the stability of the divided clocks, while allowing the undivided clocks to slow down. + + +### Clock Frequency / Time-out Measurements + +Clock manager can continuously measure root clock frequencies to see if any of the root clocks have deviated from the expected frequency. +This feature can be enabled through the various measurement control registers such as [`IO_MEASURE_CTRL`](registers.md#io_measure_ctrl). + +The root clocks, specifically the clocks supplied from `ast` and their divided variants, are constantly measured against the `always on clock` when this feature is enabled. +Software sets both an expected maximum and minimum for each measured clock. + +Clock manager then counts the number of relevant root clock cycles in each always-on clock period. +If the resulting count differs from the programmed thresholds, a recoverable error is registered. + +Since the counts are measured against a single cycle of always on clock, the minimal error that can be detected is dependent on the clock ratio between the measured clock and 1 cycle of the always on clock. +Assume a 24MHz clock and an always-on clock of 200KHz. +The minimal error detection is then 200KHz / 24MHz, or approximately 0.83%. + +This means if the clock's actual value is between 23.8MHz and 24.2MHz, this deviation will not be detected. +Conversely, if the clock's natural operation has an error range wider than this resolution, the min / max counts must be adjusted to account for this error. + +Additionally, clock manager uses a similar time-out mechanism to see if any of the root clocks have stopped toggling for an extended period of time. +This is done by creating an artificial handshake between the root clock domain and the always on clock domain that must complete within a certain amount of time based on known clock ratios. +Based on the nature of the handshake and the margin window, the minimal timeout detection window is approximately 2-4 always on clock cycles. +If the root clock domain stops and resumes in significantly less time than this window, the time-out may not be detected. + +There are three types of errors: +* Clock too fast error +* Clock too slow error +* Clock time-out error + +Clock too fast is registered when the clock cycle count is greater than the software programmed max threshold. +Clock too slow is registered when the clock cycle count is less than the software programmed min threshold. +Clock time-out is registered when the clock stops toggling and the timeout threshold is reached. + +As these are all software supplied values, the entire measurement control can be locked from further programming through [`MEASURE_CTRL_REGWEN`](registers.md#measure_ctrl_regwen). diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/README.md b/hw/top_darjeeling/ip_autogen/clkmgr/dv/README.md new file mode 100644 index 0000000000000..a932452c67427 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/README.md @@ -0,0 +1,187 @@ +# CLKMGR DV document + +## Goals +* **DV** + * Verify all CLKMGR IP features by running dynamic simulations with a SV/UVM based testbench. + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules. +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench. + * Verify clock gating assertions. + +## Current status +* [Design & verification stage](../../../../README.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/top_darjeeling/ip_autogen/clkmgr/dv/latest/report.html) + +## Design features +The detailed information on CLKMGR design features is at [CLKMGR HWIP technical specification](../README.md). + +## Testbench architecture +CLKMGR testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +### Block diagram +![Block diagram](./doc/tb.svg) + +### Top level testbench +Top level testbench is located at `hw/top_darjeeling/ip_autogen/clkmgr/dv/tb.sv`. +It instantiates the CLKMGR DUT module `hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr.sv`. +In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: + +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [TileLink host interface](../../../../dv/sv/tl_agent/README.md) +* CLKMGR IOs: `hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_if.sv` + +### Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: + +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +### Global types & methods +All common types and methods defined at the package level can be found in +`clkmgr_env_pkg`. Some of them in use are: + +```systemverilog + localparam int NUM_PERI = 4; + localparam int NUM_TRANS = 5; + localparam int NUM_ALERTS = 2; + + typedef logic [NUM_PERI-1:0] peri_enables_t; + typedef logic [NUM_TRANS-1:0] hintables_t; + + typedef virtual clkmgr_if clkmgr_vif; + typedef virtual clk_rst_if clk_rst_vif; + typedef enum int {PeriDiv4, PeriDiv2, PeriIo, PeriUsb} peri_e; + typedef enum int {TransAes, TransHmac, TransKmac, TransOtbnIoDiv4, TransOtbnMain} trans_e; +``` + +### TL_agent +CLKMGR testbench instantiates (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md) which provides the ability to drive and independently monitor random traffic via TL host interface into CLKMGR device. + +### UVM RAL Model +The CLKMGR RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md): + +## Stimulus strategy +This module is rather simple: the stimulus is just the external pins and the CSR updates. +There are a couple stages for synchronization of the CSR updates for clock gating controls, but scanmode is used asynchronously. +These go to the clock gating latches. +The external pins controlling the external clock selection need no synchronization. +The tests randomize the inputs and issue CSR updates affecting the specific functions being tested. + +### Test sequences +All test sequences reside in `hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib`. +The `clkmgr_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. +It provides commonly used handles, variables, functions and tasks that the test sequences can use or call. +Some of the most commonly used tasks / functions are as follows: +* `clkmgr_init`: Sets the frequencies of the various clocks. +* `control_ip_clocks`: Turns on or off the input clocks based on the various clock enable and status ports to and from the `pwrmgr` IP. + +All test sequences are extended from `clkmgr_base_vseq`, and are described below. + +#### clkmgr_peri_vseq + +The sequence `clkmgr_peri_vseq` randomizes the stimuli that drive the four peripheral clocks. +These clocks are mutually independent so they are tested in parallel. +They depend on +* The `clk_enables` CSR, which has a dedicated enable for each peripheral clock +* The pwrmgr's `_ip_clk_en` which has a dedicated bit controlling `io`, `main`, and `usb` clocks +* The `scanmode_i` input, which is used asynchronously and also controls all. + +The sequence runs a number of iterations, each randomizing the above except for `io_ip_clk_en` since that would imply the processor is disabled. + +#### clkmgr_trans_vseq + +The sequence `clkmgr_trans_vseq` randomizes the stimuli that drive the five transactional unit clocks. +These are also mutually independent so they are tested in parallel. +They depend on the `clk_hints` CSR, which has a separate bit for each, `main_ip_clk_en` and `scanmode_i`, similar to the peripheral clocks. +They also depend on the `idle_i` input, which also has a separate multi-bit value for each unit. +Units are considered busy when their corresponding `idle_i` value is not `mubi_pkg::MuBi4True`, and this prevents its clock turning off until it becomes idle. + +#### clkmgr_extclk_vseq + +The sequence `clkmgr_extclk_vseq` randomizes the stimuli that drive the external clock selection. +The selection is controlled by software if the `extclk_ctrl.sel` CSR is `prim_mubi_pkg::MuBi4True`, provided the `lc_hw_debug_en_i` input is also set to `lc_ctrl_pkg::On`. +Alternatively, the external clock is selected by the life cycle controller if the `lc_ctrl_byp_req_i` input is `lc_ctrl_pkg::On`. +When the external clock is selected and `scanmode_i` is not set to `prim_mubi_pkg::MuBi4True`, the clock dividers for the clk_io_div2 and clk_io_div4 output clocks are stepped down: +* If `lc_ctrl_byp_req_i` is on, or +* If `extclk_ctrl.hi_speed_sel` CSR is `prim_mubi_pkg::MuBi4True`, when the selection is enabled by software. + +#### clkmgr_frequency_vseq + +The sequence `clkmgr_frequency_vseq` randomly programs the frequency measurement for each clock so its measurement is either okay, slow, or fast. +It checks the recoverable alerts trigger as expected when a measurement is not okay. +It also checks the `recov_err_code` CSR sets bits for clocks whose measurement is out of bounds. +It also checks that loss of calibration stops clock measurements and doesn't trigger errors. + +#### clkmgr_frequency_timeout_vseq + +The sequence `clkmgr_frequency_timeout_vseq` programs the frequency measurement for each clock so its measurement is okay. +It randomly stops one of the clocks, and checks the corresponding bit in the `recov_err_code` show a timeout. +It also checks the recoverable alerts trigger as expected for a timeout. + +#### clkmgr_clk_status_vseq + +This checks that the `pwr_o.*_status` outputs track the `pwr_i.*_ip_clk_en` inputs. +The inputs are set at random and the outputs are checked via SVA. + +### Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The following covergroups have been developed to prove that the test intent has been adequately met: + +* Covergroups for inputs to each software gated peripheral clock. + These are wrapped in class `clkmgr_peri_cg_wrap` and instantiated in `clkmgr_env_cov`. +* Covergroups for inputs to each transactional gated unit clock. + These are wrapped in class `clkmgr_trans_cg_wrap` and instantiated in `clkmgr_env_cov`. +* Covergroups for the outcome of each clock measurement. + These are wrapped in class `freq_measure_cg_wrap` and instantiated in `clkmgr_env_cov`. +* Covergroup for the external clock selection logic: `extclk_cg` in `clkmgr_env_cov`. + +See more detailed description at `hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_testplan.hjson`. + +## Self-checking strategy + +Most of the checking is done using SVA for input to output, or CSR update to output behavior. +Some of the CLKMGR outputs are gated clocks, which are controlled by both synchronous logic and asynchronous enables. +These asynchronous enables become synchronous because of the SVA semantics. +This is fine since the assertions allow some cycles for the expected behavior to occur. + +### Scoreboard +The `clkmgr_scoreboard` combines CSR updates and signals from the clkmgr vif to instrument some checks and coverage collection. +The CSR updates are determined using the TLUL analysis port. + +The CSR controlled output clocks can be separated into two groups: peripheral ip clocks and transactional unit clocks. +Please refer to the [Test sequences section](#test-sequences) above. +The clock gating logic is pretty similar across units in each group. +For each peripheral and transactional clock the scoreboard samples their coverage based on clocking blocks instantiated in `clkmgr_if`. +Most other other functional coverage groups are also sampled in the scoreboard. + +The `jitter_en_o` output is checked to match the `jitter_enable` CSR. + +### Assertions +* Pwrmgr enable-status assertions: Interface `clkmgr_pwrmgr_sva_if` contains concurrent SVA that checks that edges of the various ip_clk_en are followed by corresponding edges of their clk_status. + The clocks checked are `main`, `io`, and `usb`. +* Gated clock assertions: Interface `clkmgr_gated_clock_sva_if` contains concurrent SVA that checks each gated clock is either running or stopped based on their control logic. + There is one assertion for each of the four peripheral clock and four hintable clocks. +* Transactional clock assertions: Interface `clkmgr_trans_sva_if` contains concurrent SVA that checks each transactional clock is either running or stopped based on their control logic. + There is one assertion for each of the four hintable clocks. +* Clock divider assertions: Interface `clkmgr_div_sva_if` contains concurrent SVA that checks the `io_div2` and `io_div4` clocks are running at nominal frequency, or are divided by two each in response to the `extclk` logic. +* External clock assertions: Interface `clkmgr_extclk_sva_if` contains concurrent SVA that checks the external control outputs respond correctly to the various CSR or inputs that control them. +* Clock gating assertions: Interface `clkmgr_cg_en_sva_if` contains concurrent assertions that check a clock's cg_en output is active when the clock is disabled, and viceversa. + As a special case, interface `clkmgr_aon_cg_en_sva_if` checks cg_en is never active for an aon clock. +* Lost calibration assertions: Interfaces `clkmgr_lost_calib_ctrl_en_sva_if` and `clkmgr_lost_calib_regwen_sva_if` check that losing calibration turns off clock measurements and re-enables measure control writes. +* TLUL assertions: `clkmgr_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. +* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. + +## Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: + +```console +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson -i clkmgr_smoke +``` + +## Testplan +[Testplan](../data/clkmgr_testplan.hjson) diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core b/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core new file mode 100644 index 0000000000000..05b79c321b7d6 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:clkmgr_sim:0.1" +description: "CLKMGR DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip_interfaces:clkmgr + + files_dv: + depend: + - lowrisc:dv:clkmgr_test + - lowrisc:dv:clkmgr_sva + files: + - tb.sv + - cov/clkmgr_cov_bind.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson b/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson new file mode 100644 index 0000000000000..aecde36b77f05 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson @@ -0,0 +1,136 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: clkmgr + + // Top level dut name (sv module). + dut: clkmgr + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:dv:clkmgr_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/clkmgr_testplan.hjson" + + // RAL spec - used to generate the RAL model. + ral_spec: "{self_dir}/../data/clkmgr.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson" + ] + + // Add additional tops for simulation. + sim_tops: ["clkmgr_bind", + "clkmgr_cov_bind", + "sec_cm_prim_count_bind", + "sec_cm_prim_onehot_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // CLKMGR exclusion files. + vcs_cov_excl_files: ["{self_dir}/cov/clkmgr_cov_manual_excl.el", + "{self_dir}/cov/clkmgr_cov_unr_excl.el"] + + // Handle generated coverage exclusion. + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {dv_root}/tools/vcs/cover.cfg+{dv_root}/tools/vcs/common_cov_excl.cfg+{self_dir}/cov/clkmgr_tgl_excl.cfg" + } + ] + // Default UVM test and seq class name. + uvm_test: clkmgr_base_test + uvm_test_seq: clkmgr_base_vseq + + // Disable clearing interrupts since clkmgr doesn't have any. + run_opts: ["+do_clear_all_interrupts=0", + // Enable cdc instrumentation. + "+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: clkmgr_smoke + uvm_test_seq: clkmgr_smoke_vseq + } + { + name: clkmgr_extclk + uvm_test_seq: clkmgr_extclk_vseq + } + { + name: clkmgr_frequency + uvm_test_seq: clkmgr_frequency_vseq + } + { + name: clkmgr_frequency_timeout + uvm_test_seq: clkmgr_frequency_timeout_vseq + } + { + name: clkmgr_peri + uvm_test_seq: clkmgr_peri_vseq + } + { + name: clkmgr_trans + uvm_test_seq: clkmgr_trans_vseq + } + { + name: clkmgr_clk_status + uvm_test_seq: clkmgr_clk_status_vseq + } + { + name: clkmgr_idle_intersig_mubi + uvm_test_seq: clkmgr_trans_vseq + run_opts: ["+clkmgr_mubi_mode=ClkmgrMubiIdle"] + } + { + name: clkmgr_lc_ctrl_intersig_mubi + uvm_test_seq: clkmgr_extclk_vseq + run_opts: ["+clkmgr_mubi_mode=ClkmgrMubiLcCtrl"] + } + { + name: clkmgr_lc_clk_byp_req_intersig_mubi + uvm_test_seq: clkmgr_extclk_vseq + run_opts: ["+clkmgr_mubi_mode=ClkmgrMubiLcHand"] + } + { + name: clkmgr_clk_handshake_intersig_mubi + uvm_test_seq: clkmgr_extclk_vseq + run_opts: ["+clkmgr_mubi_mode=ClkmgrMubiHand"] + } + { + name: clkmgr_div_intersig_mubi + uvm_test_seq: clkmgr_extclk_vseq + run_opts: ["+clkmgr_mubi_mode=ClkmgrMubiDiv"] + } + { + name: clkmgr_regwen + uvm_test_seq: clkmgr_regwen_vseq + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["clkmgr_smoke"] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_bind.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_bind.sv new file mode 100644 index 0000000000000..7e5ef8e3ec923 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_bind.sv @@ -0,0 +1,50 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: +// Clock manager coverage bindings for multi bus input +module clkmgr_cov_bind; + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_idle_0_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (idle_i[0]) + ); + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_idle_1_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (idle_i[1]) + ); + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_idle_2_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (idle_i[2]) + ); + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_idle_3_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (idle_i[3]) + ); + + bind clkmgr cip_lc_tx_cov_if u_lc_hw_debug_en_mubi_cov_if ( + .rst_ni (rst_ni), + .val (lc_hw_debug_en_i) + ); + + bind clkmgr cip_lc_tx_cov_if u_lc_clk_byp_req_mubi_cov_if ( + .rst_ni (rst_ni), + .val (lc_clk_byp_req_i) + ); + + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_io_clk_byp_ack_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (io_clk_byp_ack_i) + ); + + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_all_clk_byp_ack_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (all_clk_byp_ack_i) + ); + + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_div_step_down_req_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (div_step_down_req_i) + ); + +endmodule // clkmgr_cov_bind diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el b/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el new file mode 100644 index 0000000000000..ca5f99828dd8e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This contains some obvious exclusions the UNR tool didn't flag. + +//================================================== +// This file contains the Excluded objects +// Generated By User: maturana +// Format Version: 2 +// Date: Thu Sep 29 13:57:41 2022 +// ExclMode: default +//================================================== +CHECKSUM: "2301929872 1660332954" +INSTANCE: tb.dut.u_clk_main_aes_trans.u_idle_cnt +ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." +Toggle step_i "net step_i[3:0]" +CHECKSUM: "2301929872 1660332954" +INSTANCE: tb.dut.u_clk_main_hmac_trans.u_idle_cnt +ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." +Toggle step_i "net step_i[3:0]" +CHECKSUM: "2301929872 1660332954" +INSTANCE: tb.dut.u_clk_main_kmac_trans.u_idle_cnt +ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." +Toggle step_i "net step_i[3:0]" +CHECKSUM: "2301929872 1660332954" +INSTANCE: tb.dut.u_clk_main_otbn_trans.u_idle_cnt +ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." +Toggle step_i "net step_i[3:0]" +CHECKSUM: "953655365 3155586170" +INSTANCE: tb.dut +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.aon_powerup "logic cg_en_o.aon_powerup[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.usb_powerup "logic cg_en_o.usb_powerup[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.main_powerup "logic cg_en_o.main_powerup[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.io_powerup "logic cg_en_o.io_powerup[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.io_div2_powerup "logic cg_en_o.io_div2_powerup[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.io_div4_powerup "logic cg_en_o.io_div4_powerup[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.aon_peri "logic cg_en_o.aon_peri[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.aon_timers "logic cg_en_o.aon_timers[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.aon_secure "logic cg_en_o.aon_secure[3:0]" diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el b/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el new file mode 100644 index 0000000000000..85e292d7a9fa5 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el @@ -0,0 +1,200 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Generated UNR file from Synopsys UNR tool with security modules being +// black-boxed. + +//================================================== +// This file contains the Excluded objects +// Generated By User: maturana +// Format Version: 2 +// Date: Wed Jan 18 15:59:24 2023 +// ExclMode: default +//================================================== +CHECKSUM: "2972535896 3274445021" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") +CHECKSUM: "2972535896 3274445021" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") +CHECKSUM: "2972535896 3274445021" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") +CHECKSUM: "2972535896 3274445021" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") +CHECKSUM: "2972535896 3554514034" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (1) "wr_en 0" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (2) "(!rst_ni) 0,0" +CHECKSUM: "2972535896 3554514034" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (1) "wr_en 0" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (2) "(!rst_ni) 0,0" +CHECKSUM: "2972535896 3554514034" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (1) "wr_en 0" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (2) "(!rst_ni) 0,0" +CHECKSUM: "2972535896 3554514034" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (1) "wr_en 0" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (2) "(!rst_ni) 0,0" +CHECKSUM: "215202837 3193272610" +INSTANCE: tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk +ANNOTATION: "VC_COV_UNR" +Branch 0 "3003057152" "(!rst_ni)" (4) "(!rst_ni) 0,0,0,0" +CHECKSUM: "215202837 3193272610" +INSTANCE: tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk +ANNOTATION: "VC_COV_UNR" +Branch 0 "3003057152" "(!rst_ni)" (4) "(!rst_ni) 0,0,0,0" +CHECKSUM: "215202837 3193272610" +INSTANCE: tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk +ANNOTATION: "VC_COV_UNR" +Branch 0 "3003057152" "(!rst_ni)" (4) "(!rst_ni) 0,0,0,0" +CHECKSUM: "215202837 3193272610" +INSTANCE: tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk +ANNOTATION: "VC_COV_UNR" +Branch 0 "3003057152" "(!rst_ni)" (4) "(!rst_ni) 0,0,0,0" +CHECKSUM: "215202837 3193272610" +INSTANCE: tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk +ANNOTATION: "VC_COV_UNR" +Branch 0 "3003057152" "(!rst_ni)" (4) "(!rst_ni) 0,0,0,0" +CHECKSUM: "2970503351 1213720317" +INSTANCE: tb.dut.u_reg +ANNOTATION: "VC_COV_UNR" +Condition 53 "2949805610" "(io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 55 "3453311186" "(io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 57 "3988383834" "(io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 59 "1995093715" "(main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 61 "2462107587" "(usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen) 1 -1" (1 "01") +CHECKSUM: "74367784 3785313510" +INSTANCE: tb.dut.u_reg.u_reg_if +ANNOTATION: "VC_COV_UNR" +Condition 18 "3340270436" "(addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error) 1 -1" (5 "01000") +CHECKSUM: "2928260248 4109606122" +INSTANCE: tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb +ANNOTATION: "VC_COV_UNR" +Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01") +CHECKSUM: "2928260248 4109606122" +INSTANCE: tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb +ANNOTATION: "VC_COV_UNR" +Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01") +CHECKSUM: "2928260248 4109606122" +INSTANCE: tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb +ANNOTATION: "VC_COV_UNR" +Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01") +CHECKSUM: "2928260248 4109606122" +INSTANCE: tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb +ANNOTATION: "VC_COV_UNR" +Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01") +CHECKSUM: "2928260248 4109606122" +INSTANCE: tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb +ANNOTATION: "VC_COV_UNR" +Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_io_meas.u_err_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_io_div2_meas.u_err_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_io_div4_meas.u_err_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_main_meas.u_err_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_usb_meas.u_err_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_tgl_excl.cfg b/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_tgl_excl.cfg new file mode 100644 index 0000000000000..b2661b97ca375 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/cov/clkmgr_tgl_excl.cfg @@ -0,0 +1,18 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//====================================================================== +// This file contains outputs of clkmgr tied to constants. +//====================================================================== + +-module_node clkmgr cg_en_o.io_div4_powerup +-module_node clkmgr cg_en_o.aon_powerup +-module_node clkmgr cg_en_o.main_powerup +-module_node clkmgr cg_en_o.io_powerup +-module_node clkmgr cg_en_o.usb_powerup +-module_node clkmgr cg_en_o.io_div2_powerup +-module_node clkmgr cg_en_o.aon_infra +-module_node clkmgr cg_en_o.aon_secure +-module_node clkmgr cg_en_o.aon_peri +-module_node clkmgr cg_en_o.aon_timers diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/doc/tb.svg b/hw/top_darjeeling/ip_autogen/clkmgr/dv/doc/tb.svg new file mode 100644 index 0000000000000..3f48ecc3accf2 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/doc/tb.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_csrs_if.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_csrs_if.sv new file mode 100644 index 0000000000000..df369fdf59cfb --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_csrs_if.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This interface is used to sample some csr values directly from the rtl +// to avoid any confusion. + +interface clkmgr_csrs_if ( + input logic clk, + input logic [10:0] recov_err_csr, + input logic [2:0] fatal_err_csr, + input logic [3:0] clk_enables, + input logic [3:0] clk_hints +); + +clocking csrs_cb @(posedge clk); + input recov_err_csr; + input fatal_err_csr; + input clk_enables; + input clk_hints; +endclocking + +endinterface : clkmgr_csrs_if diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env.core b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env.core new file mode 100644 index 0000000000000..2fa8234336d2c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env.core @@ -0,0 +1,49 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:clkmgr_env:0.1" +description: "CLKMGR DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:ip_interfaces:pwrmgr_pkg + - lowrisc:ip_interfaces:clkmgr_pkg + files: + - clkmgr_csrs_if.sv + - clkmgr_env_pkg.sv + - clkmgr_env_cfg.sv: {is_include_file: true} + - clkmgr_env_cov.sv: {is_include_file: true} + - clkmgr_virtual_sequencer.sv: {is_include_file: true} + - clkmgr_scoreboard.sv: {is_include_file: true} + - clkmgr_env.sv: {is_include_file: true} + - seq_lib/clkmgr_vseq_list.sv: {is_include_file: true} + - seq_lib/clkmgr_base_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_clk_status_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_common_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_extclk_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_frequency_timeout_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_frequency_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_peri_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_regwen_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_smoke_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_stress_all_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_trans_vseq.sv: {is_include_file: true} + - clkmgr_if.sv + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: clkmgr + ip_hjson: ../../data/clkmgr.hjson + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env.sv new file mode 100644 index 0000000000000..e730a933c134c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env.sv @@ -0,0 +1,67 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class clkmgr_env extends cip_base_env #( + .CFG_T (clkmgr_env_cfg), + .COV_T (clkmgr_env_cov), + .VIRTUAL_SEQUENCER_T(clkmgr_virtual_sequencer), + .SCOREBOARD_T (clkmgr_scoreboard) +); + `uvm_component_utils(clkmgr_env) + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "main_clk_rst_vif", cfg.main_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get main_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "io_clk_rst_vif", cfg.io_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get io_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "usb_clk_rst_vif", cfg.usb_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get usb_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "aon_clk_rst_vif", cfg.aon_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get aon_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "root_io_clk_rst_vif", cfg.root_io_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get root_io_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "root_main_clk_rst_vif", cfg.root_main_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get root_main_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "root_usb_clk_rst_vif", cfg.root_usb_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get root_usb_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clkmgr_if)::get(this, "", "clkmgr_vif", cfg.clkmgr_vif)) begin + `uvm_fatal(`gfn, "failed to get clkmgr_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clkmgr_csrs_if)::get( + this, "", "clkmgr_csrs_vif", cfg.clkmgr_csrs_vif + )) begin + `uvm_fatal(`gfn, "failed to get clkmgr_csrs_vif from uvm_config_db") + end + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env_cfg.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env_cfg.sv new file mode 100644 index 0000000000000..9477e59af048a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env_cfg.sv @@ -0,0 +1,45 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class clkmgr_env_cfg extends cip_base_env_cfg #( + .RAL_T(clkmgr_reg_block) +); + + // This scoreboard handle is used to flag expected errors. + clkmgr_scoreboard scoreboard; + + // ext component cfgs + + // ext interfaces + virtual clkmgr_if clkmgr_vif; + virtual clkmgr_csrs_if clkmgr_csrs_vif; + virtual clk_rst_if main_clk_rst_vif; + virtual clk_rst_if io_clk_rst_vif; + virtual clk_rst_if usb_clk_rst_vif; + virtual clk_rst_if aon_clk_rst_vif; + + virtual clk_rst_if root_io_clk_rst_vif; + virtual clk_rst_if root_main_clk_rst_vif; + virtual clk_rst_if root_usb_clk_rst_vif; + + `uvm_object_utils_begin(clkmgr_env_cfg) + `uvm_object_utils_end + + `uvm_object_new + + virtual function void initialize(bit [31:0] csr_base_addr = '1); + list_of_alerts = clkmgr_env_pkg::LIST_OF_ALERTS; + super.initialize(csr_base_addr); + + // This is for the integrity error test. + tl_intg_alert_name = "fatal_fault"; + tl_intg_alert_fields[ral.fatal_err_code.reg_intg] = 1; + m_tl_agent_cfg.max_outstanding_req = 1; + + // shadow registers + shadow_update_err_status_fields[ral.recov_err_code.shadow_update_err] = 1; + shadow_storage_err_status_fields[ral.fatal_err_code.shadow_storage_err] = 1; + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env_cov.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env_cov.sv new file mode 100644 index 0000000000000..a28c2bdf10e02 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env_cov.sv @@ -0,0 +1,190 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Covergoups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here + * Covergroups may also be wrapped inside helper classes if needed. + */ + +// Wrapper class for peripheral clock covergroup. +class clkmgr_peri_cg_wrap; + // This covergroup collects signals affecting peripheral clock. + covergroup peri_cg(string name) with function sample (bit enable, bit ip_clk_en, bit scanmode); + option.name = name; + option.per_instance = 1; + + csr_enable_cp: coverpoint enable; + ip_clk_en_cp: coverpoint ip_clk_en; + scanmode_cp: coverpoint scanmode; + + peri_cross: cross csr_enable_cp, ip_clk_en_cp, scanmode_cp{ + // The enable CSRs cannot be manipulated in low power mode. + ignore_bins ignore_enable_off = peri_cross with (csr_enable_cp == 1 && ip_clk_en_cp == 0); + } + endgroup + + function new(string name); + peri_cg = new(name); + endfunction + + function void sample (bit enable, bit ip_clk_en, bit scanmode); + peri_cg.sample(enable, ip_clk_en, scanmode); + endfunction +endclass + +// Wrapper class for transactional unit clock covergroup. +class clkmgr_trans_cg_wrap; + // This covergroup collects signals affecting transactional clock. + covergroup trans_cg( + string name + ) with function sample ( + bit hint, bit ip_clk_en, bit scanmode, bit idle + ); + option.name = name; + option.per_instance = 1; + + csr_hint_cp: coverpoint hint; + ip_clk_en_cp: coverpoint ip_clk_en; + scanmode_cp: coverpoint scanmode; + idle_cp: coverpoint idle; + + trans_cross: cross csr_hint_cp, ip_clk_en_cp, scanmode_cp, idle_cp{ + // If the clock is disabled the unit must be idle. + ignore_bins ignore_idle_off = trans_cross with (idle_cp == 0 && ip_clk_en_cp == 0); + // The hint CSRs cannot be manipulated in low power mode. + ignore_bins ignore_enable_off = trans_cross with (csr_hint_cp == 1 && ip_clk_en_cp == 0); + } + endgroup + + function new(string name); + trans_cg = new(name); + endfunction + + function void sample (bit hint, bit ip_clk_en, bit scanmode, bit idle); + trans_cg.sample(hint, ip_clk_en, scanmode, idle); + endfunction +endclass + +// Wrapper class for frequency measurement covergroup. +class freq_measure_cg_wrap; + // This covergroup collects outcomes of clock frequency measurements. + covergroup freq_measure_cg( + string name + ) with function sample ( + bit okay, bit slow, bit fast, bit timeout + ); + option.name = name; + option.per_instance = 1; + + okay_cp: coverpoint okay; + slow_cp: coverpoint slow; + fast_cp: coverpoint fast; + timeout_cp: coverpoint timeout; + endgroup + + function new(string name); + freq_measure_cg = new(name); + endfunction + + function void sample (bit okay, bit slow, bit fast, bit timeout); + freq_measure_cg.sample(okay, slow, fast, timeout); + endfunction +endclass + +class clkmgr_env_cov extends cip_base_env_cov #( + .CFG_T(clkmgr_env_cfg) +); + `uvm_component_utils(clkmgr_env_cov) + + // the base class provides the following handles for use: + // clkmgr_env_cfg: cfg + + // These covergroups collect signals affecting peripheral clocks. + clkmgr_peri_cg_wrap peri_cg_wrap[NUM_PERI]; + + // These covergroups collect signals affecting transactional clocks. + clkmgr_trans_cg_wrap trans_cg_wrap[NUM_TRANS]; + + // These covergroups collect outcomes of clock frequency measurements. + freq_measure_cg_wrap freq_measure_cg_wrap[5]; + + // This embeded covergroup collects coverage for the external clock functionality. + covergroup extclk_cg with function sample ( + bit csr_sel, bit csr_low_speed, bit hw_debug_en, bit byp_req, bit scanmode + ); + csr_sel_cp: coverpoint csr_sel; + csr_low_speed_cp: coverpoint csr_low_speed; + hw_debug_en_cp: coverpoint hw_debug_en; + byp_req_cp: coverpoint byp_req; + scanmode_cp: coverpoint scanmode; + + extclk_cross: cross csr_sel_cp, csr_low_speed_cp, hw_debug_en_cp, byp_req_cp, scanmode_cp; + endgroup + + // This collects coverage for recoverable errors. + covergroup recov_err_cg with function sample ( + bit usb_timeout, + bit main_timeout, + bit io_div4_timeout, + bit io_div2_timeout, + bit io_timeout, + bit usb_measure, + bit main_measure, + bit io_div4_measure, + bit io_div2_measure, + bit io_measure, + bit shadow_update + ); + shadow_update_cp: coverpoint shadow_update; + io_measure_cp: coverpoint io_measure; + io_div2_measure_cp: coverpoint io_div2_measure; + io_div4_measure_cp: coverpoint io_div4_measure; + main_measure_cp: coverpoint main_measure; + usb_measure_cp: coverpoint usb_measure; + io_timeout_cp: coverpoint io_timeout; + io_div2_timeout_cp: coverpoint io_div2_timeout; + io_div4_timeout_cp: coverpoint io_div4_timeout; + main_timeout_cp: coverpoint main_timeout; + usb_timeout_cp: coverpoint usb_timeout; + endgroup + + // This collects coverage for fatal errors. + covergroup fatal_err_cg with function sample ( + bit shadow_storage, bit idle_cnt, bit reg_integ + ); + reg_integ_cp: coverpoint reg_integ; + idle_cnt_cp: coverpoint idle_cnt; + shadow_storage_cp: coverpoint shadow_storage; + endgroup + + function new(string name, uvm_component parent); + super.new(name, parent); + // The peripheral covergoups. + foreach (peri_cg_wrap[i]) begin + clkmgr_env_pkg::peri_e peri = clkmgr_env_pkg::peri_e'(i); + peri_cg_wrap[i] = new(peri.name); + end + // The transactional covergroups. + foreach (trans_cg_wrap[i]) begin + clkmgr_env_pkg::trans_e trans = clkmgr_env_pkg::trans_e'(i); + trans_cg_wrap[i] = new(trans.name); + end + foreach (ExpectedCounts[i]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(i); + freq_measure_cg_wrap[i] = new(clk_mesr.name); + end + extclk_cg = new(); + recov_err_cg = new(); + fatal_err_cg = new(); + endfunction : new + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + // [or instantiate covergroups here] + // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky + // See cip_base_env_cov for details + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv new file mode 100644 index 0000000000000..9ea95973da389 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv @@ -0,0 +1,151 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package clkmgr_env_pkg; + // dep packages + import uvm_pkg::*; + import sec_cm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import dv_lib_pkg::*; + import tl_agent_pkg::*; + import cip_base_pkg::*; + import dv_base_reg_pkg::*; + import csr_utils_pkg::*; + import clkmgr_ral_pkg::*; + import prim_mubi_pkg::mubi4_t; + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4True; + + import lc_ctrl_pkg::lc_tx_t; + import lc_ctrl_pkg::On; + import lc_ctrl_pkg::Off; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + typedef virtual clkmgr_if clkmgr_vif; + typedef virtual clk_rst_if clk_rst_vif; + + // parameters + parameter int NUM_PERI = 4; + parameter int NUM_TRANS = 4; + + typedef logic [NUM_PERI-1:0] peri_enables_t; + typedef logic [NUM_TRANS-1:0] hintables_t; + typedef mubi4_t [NUM_TRANS-1:0] mubi_hintables_t; + parameter mubi_hintables_t IdleAllBusy = {NUM_TRANS{prim_mubi_pkg::MuBi4False}}; + + parameter int MainClkHz = 100_000_000; + parameter int IoClkHz = 96_000_000; + parameter int UsbClkHz = 48_000_000; + parameter int AonClkHz = 200_000; + parameter int FakeAonClkHz = 7_000_000; + + // alerts + parameter uint NUM_ALERTS = 2; + parameter string LIST_OF_ALERTS[] = {"recov_fault", "fatal_fault"}; + + // types + + // Forward class decl to enable cfg to hold a scoreboard handle. + typedef class clkmgr_scoreboard; + + // The enum values for these match the bit order in the CSRs. + typedef enum int { + PeriDiv4, + PeriDiv2, + PeriUsb, + PeriIo + } peri_e; + typedef struct packed { + logic usb_peri_en; + logic io_peri_en; + logic io_div2_peri_en; + logic io_div4_peri_en; + } clk_enables_t; + + typedef enum int { + TransAes, + TransHmac, + TransKmac, + TransOtbn + } trans_e; + typedef struct packed { + logic otbn_main; + logic kmac; + logic hmac; + logic aes; + } clk_hints_t; + + typedef struct { + logic valid; + logic slow; + logic fast; + } freq_measurement_t; + + // These are ordered per the bits in the recov_err_code register. + typedef enum int { + ClkMesrIo, + ClkMesrIoDiv2, + ClkMesrIoDiv4, + ClkMesrMain, + ClkMesrUsb + } clk_mesr_e; + + // Mubi test mode + typedef enum int { + ClkmgrMubiNone = 0, + ClkmgrMubiIdle = 1, + ClkmgrMubiLcCtrl = 2, + ClkmgrMubiLcHand = 3, + ClkmgrMubiHand = 4, + ClkmgrMubiDiv = 5 + } clkmgr_mubi_e; + + // This is to examine separately the measurement and timeout recoverable error bits. + typedef logic [ClkMesrUsb:0] recov_bits_t; + + typedef struct packed { + recov_bits_t timeouts; + recov_bits_t measures; + logic shadow_update; + } clkmgr_recov_err_t; + + // These must be after the declaration of clk_mesr_e for sizing. + parameter int ClkInHz[ClkMesrUsb+1] = {IoClkHz, IoClkHz / 2, IoClkHz / 4, MainClkHz, UsbClkHz}; + + parameter int ExpectedCounts[ClkMesrUsb+1] = { + ClkInHz[ClkMesrIo] / AonClkHz - 1, + ClkInHz[ClkMesrIoDiv2] / AonClkHz - 1, + ClkInHz[ClkMesrIoDiv4] / AonClkHz - 1, + ClkInHz[ClkMesrMain] / AonClkHz - 1, + ClkInHz[ClkMesrUsb] / AonClkHz - 1 + }; + + // functions + function automatic void print_hintable(hintables_t tbl); + foreach (tbl[i]) begin + `uvm_info("HINTBL", $sformatf("entry%0d : %b", i, tbl[i]), UVM_LOW) + end + endfunction : print_hintable + + function automatic void print_mubi_hintable(mubi_hintables_t tbl); + string val = "INVALID"; + foreach (tbl[i]) begin + if (tbl[i].name != "") val = tbl[i].name; + `uvm_info("MUBIHINTBL", $sformatf("entry%0d : %s", i, val), UVM_LOW) + end + endfunction : print_mubi_hintable + + // package sources + `include "clkmgr_env_cfg.sv" + `include "clkmgr_env_cov.sv" + `include "clkmgr_virtual_sequencer.sv" + `include "clkmgr_scoreboard.sv" + `include "clkmgr_env.sv" + `include "clkmgr_vseq_list.sv" + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_if.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_if.sv new file mode 100644 index 0000000000000..c6d8aa8d8f5dd --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_if.sv @@ -0,0 +1,362 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// clkmgr interface. + +interface clkmgr_if ( + input logic clk, + input logic rst_n, + input logic clk_main, + input logic rst_io_n, + input logic rst_main_n, + input logic rst_usb_n +); + import uvm_pkg::*; + import clkmgr_env_pkg::*; + + // The ports to the dut side. + + localparam int LcTxTWidth = $bits(lc_ctrl_pkg::lc_tx_t); + + // Encodes the transactional units that are idle. + mubi_hintables_t idle_i; + + // pwrmgr req contains ip_clk_en, set to enable the gated clocks. + pwrmgr_pkg::pwr_clk_req_t pwr_i; + + // outputs clk_status: transitions to 1 if all clocks are enabled, and + // to 0 when all are disabled. + pwrmgr_pkg::pwr_clk_rsp_t pwr_o; + + // scanmode_i == MuBi4True defeats all clock gating. + prim_mubi_pkg::mubi4_t scanmode_i; + + // Life cycle enables clock bypass functionality. + lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i; + + // Life cycle clock bypass request and clkmgr ack. + lc_ctrl_pkg::lc_tx_t lc_clk_byp_req; + lc_ctrl_pkg::lc_tx_t lc_clk_byp_ack; + // clkmgr clock bypass request for io clocks and ast ack: triggered by lc_clk_byp_req. + prim_mubi_pkg::mubi4_t io_clk_byp_req; + prim_mubi_pkg::mubi4_t io_clk_byp_ack; + // clkmgr clock bypass request for all clocks and ast ack: triggered by software. + prim_mubi_pkg::mubi4_t all_clk_byp_req; + prim_mubi_pkg::mubi4_t all_clk_byp_ack; + + prim_mubi_pkg::mubi4_t div_step_down_req; + + prim_mubi_pkg::mubi4_t jitter_en_o; + clkmgr_pkg::clkmgr_out_t clocks_o; + + prim_mubi_pkg::mubi4_t calib_rdy; + prim_mubi_pkg::mubi4_t hi_speed_sel; + + // Internal DUT signals. + // ICEBOX(lowrisc/opentitan#18379): This is a core env component (i.e. reusable entity) that + // makes hierarchical references into the DUT. A better strategy would be to bind this interface + // to the DUT in tb.sv and use relative paths instead. +`ifndef CLKMGR_HIER + `define CLKMGR_HIER tb.dut +`endif + + // The CSR values from the testbench side. + clk_enables_t clk_enables_csr; + always_comb + clk_enables_csr = '{ + usb_peri_en: `CLKMGR_HIER.reg2hw.clk_enables.clk_usb_peri_en.q, + io_peri_en: `CLKMGR_HIER.reg2hw.clk_enables.clk_io_peri_en.q, + io_div2_peri_en: `CLKMGR_HIER.reg2hw.clk_enables.clk_io_div2_peri_en.q, + io_div4_peri_en: `CLKMGR_HIER.reg2hw.clk_enables.clk_io_div4_peri_en.q + }; + + clk_hints_t clk_hints_csr; + always_comb + clk_hints_csr = '{ + otbn_main: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_otbn_hint.q, + kmac: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_kmac_hint.q, + hmac: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_hmac_hint.q, + aes: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_aes_hint.q + }; + + clk_hints_t clk_hints_status_csr; + always_comb + clk_hints_status_csr = '{ + otbn_main: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_otbn_val_qs, + kmac: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_kmac_val_qs, + hmac: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_hmac_val_qs, + aes: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_aes_val_qs + }; + + prim_mubi_pkg::mubi4_t extclk_ctrl_csr_sel; + always_comb begin + extclk_ctrl_csr_sel = prim_mubi_pkg::mubi4_t'(`CLKMGR_HIER.reg2hw.extclk_ctrl.sel.q); + end + + prim_mubi_pkg::mubi4_t extclk_ctrl_csr_step_down; + always_comb begin + extclk_ctrl_csr_step_down = prim_mubi_pkg::mubi4_t'( + `CLKMGR_HIER.reg2hw.extclk_ctrl.hi_speed_sel.q); + end + + prim_mubi_pkg::mubi4_t jitter_enable_csr; + always_comb begin + jitter_enable_csr = prim_mubi_pkg::mubi4_t'(`CLKMGR_HIER.reg2hw.jitter_enable.q); + end + + freq_measurement_t io_freq_measurement; + logic io_timeout_err; + always @(posedge `CLKMGR_HIER.u_io_meas.u_meas.clk_i) begin + if (`CLKMGR_HIER.u_io_meas.u_meas.valid_o) begin + io_freq_measurement = '{valid: `CLKMGR_HIER.u_io_meas.u_meas.valid_o, + slow: `CLKMGR_HIER.u_io_meas.u_meas.slow_o, + fast: `CLKMGR_HIER.u_io_meas.u_meas.fast_o}; + `uvm_info("clkmgr_if", $sformatf("Sampled coverage for ClkMesrIo as %p", io_freq_measurement), + UVM_HIGH) + end + end + always_comb io_timeout_err = `CLKMGR_HIER.u_io_meas.timeout_err_o; + + freq_measurement_t io_div2_freq_measurement; + logic io_div2_timeout_err; + always @(posedge `CLKMGR_HIER.u_io_div2_meas.u_meas.clk_i) begin + if (`CLKMGR_HIER.u_io_div2_meas.u_meas.valid_o) begin + io_div2_freq_measurement = '{valid: `CLKMGR_HIER.u_io_div2_meas.u_meas.valid_o, + slow: `CLKMGR_HIER.u_io_div2_meas.u_meas.slow_o, + fast: `CLKMGR_HIER.u_io_div2_meas.u_meas.fast_o}; + `uvm_info("clkmgr_if", $sformatf( + "Sampled coverage for ClkMesrIoDiv2 as %p", io_div2_freq_measurement), UVM_HIGH) + end + end + always_comb io_div2_timeout_err = `CLKMGR_HIER.u_io_div2_meas.timeout_err_o; + + freq_measurement_t io_div4_freq_measurement; + logic io_div4_timeout_err; + always @(posedge `CLKMGR_HIER.u_io_div4_meas.u_meas.clk_i) begin + if (`CLKMGR_HIER.u_io_div4_meas.u_meas.valid_o) begin + io_div4_freq_measurement = '{valid: `CLKMGR_HIER.u_io_div4_meas.u_meas.valid_o, + slow: `CLKMGR_HIER.u_io_div4_meas.u_meas.slow_o, + fast: `CLKMGR_HIER.u_io_div4_meas.u_meas.fast_o}; + `uvm_info("clkmgr_if", $sformatf( + "Sampled coverage for ClkMesrIoDiv4 as %p", io_div4_freq_measurement), UVM_HIGH) + end + end + always_comb io_div4_timeout_err = `CLKMGR_HIER.u_io_div4_meas.timeout_err_o; + + freq_measurement_t main_freq_measurement; + logic main_timeout_err; + always @(posedge `CLKMGR_HIER.u_main_meas.u_meas.clk_i) begin + if (`CLKMGR_HIER.u_main_meas.u_meas.valid_o) begin + main_freq_measurement = '{valid: `CLKMGR_HIER.u_main_meas.u_meas.valid_o, + slow: `CLKMGR_HIER.u_main_meas.u_meas.slow_o, + fast: `CLKMGR_HIER.u_main_meas.u_meas.fast_o}; + `uvm_info("clkmgr_if", $sformatf( + "Sampled coverage for ClkMesrMain as %p", main_freq_measurement), UVM_HIGH) + end + end + always_comb main_timeout_err = `CLKMGR_HIER.u_main_meas.timeout_err_o; + + freq_measurement_t usb_freq_measurement; + logic usb_timeout_err; + always @(posedge `CLKMGR_HIER.u_usb_meas.u_meas.clk_i) begin + if (`CLKMGR_HIER.u_usb_meas.u_meas.valid_o) begin + usb_freq_measurement = '{valid: `CLKMGR_HIER.u_usb_meas.u_meas.valid_o, + slow: `CLKMGR_HIER.u_usb_meas.u_meas.slow_o, + fast: `CLKMGR_HIER.u_usb_meas.u_meas.fast_o}; + `uvm_info("clkmgr_if", $sformatf("Sampled coverage for ClkMesrUsb as %p", usb_freq_measurement + ), UVM_HIGH) + end + end + always_comb usb_timeout_err = `CLKMGR_HIER.u_usb_meas.timeout_err_o; + + function automatic void update_calib_rdy(prim_mubi_pkg::mubi4_t value); + calib_rdy = value; + endfunction + + function automatic void update_idle(mubi_hintables_t value); + idle_i = value; + endfunction + + function automatic void update_io_ip_clk_en(bit value); + pwr_i.io_ip_clk_en = value; + endfunction + + function automatic void update_main_ip_clk_en(bit value); + pwr_i.main_ip_clk_en = value; + endfunction + + function automatic void update_usb_ip_clk_en(bit value); + pwr_i.usb_ip_clk_en = value; + endfunction + + function automatic void update_scanmode(prim_mubi_pkg::mubi4_t value); + scanmode_i = value; + endfunction + + function automatic void update_lc_debug_en(lc_ctrl_pkg::lc_tx_t value); + lc_hw_debug_en_i = value; + endfunction + + function automatic void update_lc_clk_byp_req(lc_ctrl_pkg::lc_tx_t value); + lc_clk_byp_req = value; + endfunction + + function automatic void update_all_clk_byp_ack(prim_mubi_pkg::mubi4_t value); + `uvm_info("clkmgr_if", $sformatf("In clkmgr_if update_all_clk_byp_ack with %b", value), + UVM_MEDIUM) + all_clk_byp_ack = value; + endfunction + + function automatic void update_div_step_down_req(prim_mubi_pkg::mubi4_t value); + `uvm_info("clkmgr_if", $sformatf("In clkmgr_if update_div_step_down_req with %b", value), + UVM_MEDIUM) + div_step_down_req = value; + endfunction + + function automatic void update_io_clk_byp_ack(prim_mubi_pkg::mubi4_t value); + io_clk_byp_ack = value; + endfunction + + function automatic void force_high_starting_count(clk_mesr_e clk); + `uvm_info("clkmgr_if", $sformatf("Forcing count of %0s to all 1.", clk.name()), UVM_MEDIUM) + case (clk) + ClkMesrIo: `CLKMGR_HIER.u_io_meas.u_meas.cnt = '1; + ClkMesrIoDiv2: `CLKMGR_HIER.u_io_div2_meas.u_meas.cnt = '1; + ClkMesrIoDiv4: `CLKMGR_HIER.u_io_div4_meas.u_meas.cnt = '1; + ClkMesrMain: `CLKMGR_HIER.u_main_meas.u_meas.cnt = '1; + ClkMesrUsb: `CLKMGR_HIER.u_usb_meas.u_meas.cnt = '1; + default: ; + endcase + endfunction + + task automatic init(mubi_hintables_t idle, prim_mubi_pkg::mubi4_t scanmode, + lc_ctrl_pkg::lc_tx_t lc_debug_en = lc_ctrl_pkg::Off, + lc_ctrl_pkg::lc_tx_t lc_clk_byp_req = lc_ctrl_pkg::Off, + prim_mubi_pkg::mubi4_t calib_rdy = prim_mubi_pkg::MuBi4True); + `uvm_info("clkmgr_if", "In clkmgr_if init", UVM_MEDIUM) + update_calib_rdy(calib_rdy); + update_idle(idle); + update_lc_clk_byp_req(lc_clk_byp_req); + update_lc_debug_en(lc_debug_en); + update_scanmode(scanmode); + endtask + + // Pipeline signals that go through synchronizers with the target clock domain's clock. + // thus the PIPELINE_DEPTH is 2. + + // Use clocking blocks clocked by the target clock domain's clock to transfer relevant + // control signals back to the scoreboard. + localparam int PIPELINE_DEPTH = 2; + + // Pipelines and clocking blocks for peripheral clocks. + + logic [PIPELINE_DEPTH-1:0] clk_enable_div4_ffs; + logic [PIPELINE_DEPTH-1:0] ip_clk_en_div4_ffs; + always @(posedge clocks_o.clk_io_div4_powerup or negedge rst_io_n) begin + if (rst_io_n) begin + clk_enable_div4_ffs <= { + clk_enable_div4_ffs[PIPELINE_DEPTH-2:0], clk_enables_csr.io_div4_peri_en + }; + ip_clk_en_div4_ffs <= {ip_clk_en_div4_ffs[PIPELINE_DEPTH-2:0], pwr_i.io_ip_clk_en}; + end else begin + clk_enable_div4_ffs <= '0; + ip_clk_en_div4_ffs <= '0; + end + end + clocking peri_div4_cb @(posedge clocks_o.clk_io_div4_powerup or negedge rst_io_n); + input ip_clk_en = ip_clk_en_div4_ffs[PIPELINE_DEPTH-1]; + input clk_enable = clk_enable_div4_ffs[PIPELINE_DEPTH-1]; + endclocking + + logic [PIPELINE_DEPTH-1:0] clk_enable_div2_ffs; + logic [PIPELINE_DEPTH-1:0] ip_clk_en_div2_ffs; + always @(posedge clocks_o.clk_io_div2_powerup or negedge rst_io_n) begin + if (rst_io_n) begin + clk_enable_div2_ffs <= { + clk_enable_div2_ffs[PIPELINE_DEPTH-2:0], clk_enables_csr.io_div2_peri_en + }; + ip_clk_en_div2_ffs <= {ip_clk_en_div2_ffs[PIPELINE_DEPTH-2:0], pwr_i.io_ip_clk_en}; + end else begin + clk_enable_div2_ffs <= '0; + ip_clk_en_div2_ffs <= '0; + end + end + clocking peri_div2_cb @(posedge clocks_o.clk_io_div2_powerup or negedge rst_io_n); + input ip_clk_en = ip_clk_en_div2_ffs[PIPELINE_DEPTH-1]; + input clk_enable = clk_enable_div2_ffs[PIPELINE_DEPTH-1]; + endclocking + + logic [PIPELINE_DEPTH-1:0] clk_enable_io_ffs; + logic [PIPELINE_DEPTH-1:0] ip_clk_en_io_ffs; + always @(posedge clocks_o.clk_io_powerup or negedge rst_io_n) begin + if (rst_io_n) begin + clk_enable_io_ffs <= {clk_enable_io_ffs[PIPELINE_DEPTH-2:0], clk_enables_csr.io_peri_en}; + ip_clk_en_io_ffs <= {ip_clk_en_io_ffs[PIPELINE_DEPTH-2:0], pwr_i.io_ip_clk_en}; + end else begin + clk_enable_io_ffs <= '0; + ip_clk_en_io_ffs <= '0; + end + end + clocking peri_io_cb @(posedge clocks_o.clk_io_powerup or negedge rst_io_n); + input ip_clk_en = ip_clk_en_io_ffs[PIPELINE_DEPTH-1]; + input clk_enable = clk_enable_io_ffs[PIPELINE_DEPTH-1]; + endclocking + + logic [PIPELINE_DEPTH-1:0] clk_enable_usb_ffs; + logic [PIPELINE_DEPTH-1:0] ip_clk_en_usb_ffs; + always @(posedge clocks_o.clk_usb_powerup or negedge rst_usb_n) begin + if (rst_usb_n) begin + clk_enable_usb_ffs <= {clk_enable_usb_ffs[PIPELINE_DEPTH-2:0], clk_enables_csr.usb_peri_en}; + ip_clk_en_usb_ffs <= {ip_clk_en_usb_ffs[PIPELINE_DEPTH-2:0], pwr_i.usb_ip_clk_en}; + end else begin + clk_enable_usb_ffs <= '0; + ip_clk_en_usb_ffs <= '0; + end + end + clocking peri_usb_cb @(posedge clocks_o.clk_usb_powerup or negedge rst_usb_n); + input ip_clk_en = ip_clk_en_usb_ffs[PIPELINE_DEPTH-1]; + input clk_enable = clk_enable_usb_ffs[PIPELINE_DEPTH-1]; + endclocking + + // Pipelining and clocking block for transactional unit clocks. + logic [PIPELINE_DEPTH-1:0][NUM_TRANS-1:0] clk_hints_ffs; + logic [PIPELINE_DEPTH-1:0] trans_clk_en_ffs; + always @(posedge clocks_o.clk_main_powerup or negedge rst_main_n) begin + if (rst_main_n) begin + clk_hints_ffs <= {clk_hints_ffs[PIPELINE_DEPTH-2:0], clk_hints_csr}; + trans_clk_en_ffs <= {trans_clk_en_ffs[PIPELINE_DEPTH-2:0], pwr_i.main_ip_clk_en}; + end else begin + clk_hints_ffs <= '0; + trans_clk_en_ffs <= '0; + end + end + clocking trans_cb @(posedge clocks_o.clk_main_powerup or negedge rst_main_n); + input ip_clk_en = trans_clk_en_ffs[PIPELINE_DEPTH-1]; + input clk_hints = clk_hints_ffs[PIPELINE_DEPTH-1]; + input idle_i; + endclocking + + // Pipelining and clocking block for external clock bypass. The divisor control is + // triggered by an ast ack, which goes through synchronizers. + logic step_down_ff; + always @(posedge clk) begin + if (rst_n) begin + step_down_ff <= io_clk_byp_ack == prim_mubi_pkg::MuBi4True; + end else begin + step_down_ff <= 1'b0; + end + end + + clocking clk_cb @(posedge clk); + input calib_rdy; + input extclk_ctrl_csr_sel; + input extclk_ctrl_csr_step_down; + input lc_hw_debug_en_i; + input io_clk_byp_req; + input lc_clk_byp_req; + input step_down = step_down_ff; + input jitter_enable_csr; + endclocking + +endinterface diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_scoreboard.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_scoreboard.sv new file mode 100644 index 0000000000000..820925dd9af5b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_scoreboard.sv @@ -0,0 +1,398 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The scoreboard checks the jitter_an_o output, and processes CSR checks. +// It also samples most functional coverage groups. +class clkmgr_scoreboard extends cip_base_scoreboard #( + .CFG_T(clkmgr_env_cfg), + .RAL_T(clkmgr_reg_block), + .COV_T(clkmgr_env_cov) +); + `uvm_component_utils(clkmgr_scoreboard) + + // local variables + logic extclk_ctrl_regwen; + logic measure_ctrl_regwen; + + // TLM agent fifos + + // local queues to hold incoming packets pending comparison + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + cfg.scoreboard = this; + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + fork + monitor_all_clk_byp(); + monitor_io_clk_byp(); + monitor_jitter_en(); + sample_peri_covs(); + sample_trans_covs(); + sample_freq_measurement_covs(); + sample_fatal_err_cov(); + sample_recov_err_cov(); + join_none + endtask + + task monitor_all_clk_byp(); + mubi4_t prev_all_clk_byp_req = MuBi4False; + forever + @cfg.clkmgr_vif.clk_cb begin + if (cfg.clkmgr_vif.all_clk_byp_req != prev_all_clk_byp_req) begin + `uvm_info(`gfn, $sformatf( + "Got all_clk_byp_req %s", + cfg.clkmgr_vif.all_clk_byp_req == MuBi4True ? "True" : "False" + ), UVM_MEDIUM) + prev_all_clk_byp_req = cfg.clkmgr_vif.all_clk_byp_req; + end + if (cfg.clk_rst_vif.rst_n) begin + if (cfg.en_cov) begin + cov.extclk_cg.sample(cfg.clkmgr_vif.clk_cb.extclk_ctrl_csr_sel == MuBi4True, + cfg.clkmgr_vif.clk_cb.extclk_ctrl_csr_step_down == MuBi4True, + cfg.clkmgr_vif.clk_cb.lc_hw_debug_en_i == On, + cfg.clkmgr_vif.clk_cb.lc_clk_byp_req == On, + cfg.clkmgr_vif.scanmode_i == MuBi4True); + end + end + end + endtask + + task monitor_io_clk_byp(); + lc_tx_t prev_lc_clk_byp_req = Off; + forever + @cfg.clkmgr_vif.clk_cb begin + if (cfg.clkmgr_vif.lc_clk_byp_req != prev_lc_clk_byp_req) begin + `uvm_info(`gfn, $sformatf( + "Got lc_clk_byp_req %s", cfg.clkmgr_vif.lc_clk_byp_req == On ? "On" : "Off"), + UVM_MEDIUM) + prev_lc_clk_byp_req = cfg.clkmgr_vif.lc_clk_byp_req; + end + if (cfg.clk_rst_vif.rst_n) begin + if (cfg.en_cov) begin + cov.extclk_cg.sample(cfg.clkmgr_vif.clk_cb.extclk_ctrl_csr_sel == MuBi4True, + cfg.clkmgr_vif.clk_cb.extclk_ctrl_csr_step_down == MuBi4True, + cfg.clkmgr_vif.clk_cb.lc_hw_debug_en_i == On, + cfg.clkmgr_vif.clk_cb.lc_clk_byp_req == On, + cfg.clkmgr_vif.scanmode_i == MuBi4True); + end + end + end + endtask + + task monitor_jitter_en(); + fork + forever + @cfg.clkmgr_vif.clk_cb begin + if (cfg.clk_rst_vif.rst_n) begin + @cfg.clkmgr_vif.jitter_enable_csr begin + cfg.clk_rst_vif.wait_clks(2); + `DV_CHECK_EQ(cfg.clkmgr_vif.jitter_en_o, cfg.clkmgr_vif.jitter_enable_csr, + "Mismatching jitter enable output") + end + end + end + forever + @cfg.clkmgr_vif.clk_cb begin + if (cfg.clk_rst_vif.rst_n) begin + @cfg.clkmgr_vif.jitter_en_o begin + cfg.clk_rst_vif.wait_clks(2); + `DV_CHECK_EQ(cfg.clkmgr_vif.jitter_en_o, cfg.clkmgr_vif.jitter_enable_csr, + "Mismatching jitter enable output") + end + end + end + join + endtask + + task sample_peri_covs(); + fork + forever + @cfg.clkmgr_vif.peri_io_cb begin + if (cfg.io_clk_rst_vif.rst_n && cfg.en_cov) begin + cov.peri_cg_wrap[PeriIo].sample(cfg.clkmgr_vif.peri_io_cb.clk_enable, + cfg.clkmgr_vif.peri_io_cb.ip_clk_en, + cfg.clkmgr_vif.scanmode_i == MuBi4True); + end + end + forever + @cfg.clkmgr_vif.peri_div2_cb begin + if (cfg.io_clk_rst_vif.rst_n && cfg.en_cov) begin + cov.peri_cg_wrap[PeriDiv2].sample(cfg.clkmgr_vif.peri_div2_cb.clk_enable, + cfg.clkmgr_vif.peri_div2_cb.ip_clk_en, + cfg.clkmgr_vif.scanmode_i == MuBi4True); + end + end + forever + @cfg.clkmgr_vif.peri_div4_cb begin + if (cfg.io_clk_rst_vif.rst_n && cfg.en_cov) begin + cov.peri_cg_wrap[PeriDiv4].sample(cfg.clkmgr_vif.peri_div4_cb.clk_enable, + cfg.clkmgr_vif.peri_div4_cb.ip_clk_en, + cfg.clkmgr_vif.scanmode_i == MuBi4True); + end + end + forever + @cfg.clkmgr_vif.peri_usb_cb begin + if (cfg.io_clk_rst_vif.rst_n && cfg.en_cov) begin + cov.peri_cg_wrap[PeriUsb].sample(cfg.clkmgr_vif.peri_usb_cb.clk_enable, + cfg.clkmgr_vif.peri_usb_cb.ip_clk_en, + cfg.clkmgr_vif.scanmode_i == MuBi4True); + end + end + join + endtask + + task sample_trans_cov(int trans_index); + logic hint, clk_en, idle, src_rst_en; + trans_e trans = trans_e'(trans_index); + forever begin + @cfg.clkmgr_vif.trans_cb; + hint = cfg.clkmgr_vif.trans_cb.clk_hints[trans_index]; + idle = cfg.clkmgr_vif.trans_cb.idle_i[trans_index]; + clk_en = cfg.clkmgr_vif.trans_cb.ip_clk_en; + src_rst_en = cfg.main_clk_rst_vif.rst_n; + if (src_rst_en && cfg.en_cov) begin + logic scan_en = cfg.clkmgr_vif.scanmode_i == prim_mubi_pkg::MuBi4True; + cov.trans_cg_wrap[trans].sample(hint, clk_en, scan_en, idle); + end + end + endtask + + task sample_trans_covs(); + for (int i = 0; i < $bits(hintables_t); ++i) begin + fork + automatic int trans_index = i; + sample_trans_cov(trans_index); + join_none + end + endtask + + local task sample_freq_measurement_cov(clk_mesr_e clk, ref freq_measurement_t measurement, + logic timeout); + if (cfg.en_cov) begin + cov.freq_measure_cg_wrap[clk].sample(!measurement.slow && !measurement.fast, measurement.slow, + measurement.fast, timeout); + `uvm_info(`gfn, $sformatf( + "Cov for %0s: %0s", + clk.name(), + measurement.slow ? "slow" : measurement.fast ? "fast" : "okay" + ), UVM_MEDIUM) + measurement = '{default: 0}; + end + endtask + + task sample_freq_measurement_covs(); + fork + forever + @(posedge cfg.clkmgr_vif.io_freq_measurement.valid or + posedge cfg.clkmgr_vif.io_timeout_err) begin + sample_freq_measurement_cov(ClkMesrIo, cfg.clkmgr_vif.io_freq_measurement, + cfg.clkmgr_vif.io_timeout_err); + end + + forever + @(posedge cfg.clkmgr_vif.io_div2_freq_measurement.valid or + posedge cfg.clkmgr_vif.io_div2_timeout_err) begin + sample_freq_measurement_cov(ClkMesrIoDiv2, cfg.clkmgr_vif.io_div2_freq_measurement, + cfg.clkmgr_vif.io_div2_timeout_err); + + end + forever + @(posedge cfg.clkmgr_vif.io_div4_freq_measurement.valid or + posedge cfg.clkmgr_vif.io_div4_timeout_err) begin + sample_freq_measurement_cov(ClkMesrIoDiv4, cfg.clkmgr_vif.io_div4_freq_measurement, + cfg.clkmgr_vif.io_div4_timeout_err); + end + forever + @(posedge cfg.clkmgr_vif.main_freq_measurement.valid or + posedge cfg.clkmgr_vif.main_timeout_err) begin + sample_freq_measurement_cov(ClkMesrMain, cfg.clkmgr_vif.main_freq_measurement, + cfg.clkmgr_vif.main_timeout_err); + end + forever + @(posedge cfg.clkmgr_vif.usb_freq_measurement.valid or + posedge cfg.clkmgr_vif.usb_timeout_err) begin + sample_freq_measurement_cov(ClkMesrUsb, cfg.clkmgr_vif.usb_freq_measurement, + cfg.clkmgr_vif.usb_timeout_err); + end + join_none + endtask + + task sample_recov_err_cov(); + fork + forever + @cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr if (cfg.en_cov) begin + cov.recov_err_cg.sample( + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[10], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[9], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[8], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[7], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[6], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[5], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[4], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[3], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[2], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[1], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[0]); + `uvm_info(`gfn, $sformatf( + "Recoverable errors sampled: 0x%x", cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr), + UVM_MEDIUM) + end + join_none + endtask + + task sample_fatal_err_cov(); + fork + forever + @cfg.clkmgr_csrs_vif.csrs_cb.fatal_err_csr if (cfg.en_cov) begin + cov.fatal_err_cg.sample( + cfg.clkmgr_csrs_vif.csrs_cb.fatal_err_csr[2], + cfg.clkmgr_csrs_vif.csrs_cb.fatal_err_csr[1], + cfg.clkmgr_csrs_vif.csrs_cb.fatal_err_csr[0]); + `uvm_info(`gfn, $sformatf( + "Fatal errors sampled: 0x%x", cfg.clkmgr_csrs_vif.csrs_cb.fatal_err_csr), + UVM_MEDIUM) + end + join_none + endtask + + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + uvm_reg csr; + bit do_read_check = 1'b1; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = (write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = (write && channel == DataChannel); + + string access_str = write ? "write" : "read"; + string channel_str = channel == AddrChannel ? "address" : "data"; + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + // If incoming access is a write to a valid csr, update prediction right away. + if (addr_phase_write) begin + `uvm_info(`gfn, $sformatf("Writing 0x%0x to %s", item.a_data, csr.get_name()), UVM_MEDIUM) + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // Process the csr req: + // - For write, update local variable and fifo at address phase. + // - For read, update predication at address phase and compare at data phase. + case (csr.get_name()) + // add individual case item for each csr + "alert_test": begin + // FIXME + end + "extclk_ctrl_regwen": begin + if (addr_phase_write) extclk_ctrl_regwen = item.a_data; + end + "extclk_ctrl": begin + typedef logic [2*$bits(prim_mubi_pkg::mubi4_t) - 1:0] extclk_ctrl_t; + if (addr_phase_write && extclk_ctrl_regwen) begin + `DV_CHECK_EQ(extclk_ctrl_t'(item.a_data), { + cfg.clkmgr_vif.extclk_ctrl_csr_step_down, cfg.clkmgr_vif.extclk_ctrl_csr_sel + }) + end + end + "extclk_status": begin + do_read_check = 1'b0; + end + "jitter_regwen": begin + end + "jitter_enable": begin + if (addr_phase_write && `gmv(ral.jitter_regwen)) begin + `DV_CHECK_EQ(prim_mubi_pkg::mubi4_t'(item.a_data), cfg.clkmgr_vif.jitter_enable_csr) + end + end + "clk_enables": begin + if (addr_phase_write) begin + `DV_CHECK_EQ(clk_enables_t'(item.a_data), cfg.clkmgr_vif.clk_enables_csr) + end + end + "clk_hints": begin + // Clearing a hint sets an expectation for the status to transition to zero. + if (addr_phase_write) begin + `DV_CHECK_EQ(clk_hints_t'(item.a_data), cfg.clkmgr_vif.clk_hints_csr) + end + end + "clk_hints_status": begin + // The status will respond to the hint once the target unit is idle. We check it in + // the sequence. + do_read_check = 1'b0; + end + "measure_ctrl_regwen": begin + if (addr_phase_write) measure_ctrl_regwen = item.a_data; + end + "io_meas_ctrl_en": begin + end + "io_div2_meas_ctrl_en": begin + end + "io_div4_meas_ctrl_en": begin + end + "main_meas_ctrl_en": begin + end + "usb_meas_ctrl_en": begin + end + "io_meas_ctrl_shadowed": begin + end + "io_div2_meas_ctrl_shadowed": begin + end + "io_div4_meas_ctrl_shadowed": begin + end + "main_meas_ctrl_shadowed": begin + end + "usb_meas_ctrl_shadowed": begin + end + "recov_err_code": begin + do_read_check = 1'b0; + end + "fatal_err_code": begin + do_read_check = 1'b0; + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + `uvm_info(`gfn, $sformatf("Reading 0x%0x from %s", item.d_data, csr.get_name()), UVM_MEDIUM) + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, $sformatf( + "reg name: %0s", csr.get_full_name())) + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end + endtask + + virtual function void reset(string kind = "HARD"); + super.reset(kind); + // reset local fifos queues and variables + extclk_ctrl_regwen = ral.extclk_ctrl_regwen.get_reset(); + measure_ctrl_regwen = ral.measure_ctrl_regwen.get_reset(); + endfunction + + function void check_phase(uvm_phase phase); + super.check_phase(phase); + // post test checks - ensure that all local fifos and queues are empty + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_virtual_sequencer.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_virtual_sequencer.sv new file mode 100644 index 0000000000000..8239de0df3ab0 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_virtual_sequencer.sv @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class clkmgr_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(clkmgr_env_cfg), + .COV_T(clkmgr_env_cov) +); + `uvm_component_utils(clkmgr_virtual_sequencer) + + + `uvm_component_new + +endclass diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_base_vseq.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_base_vseq.sv new file mode 100644 index 0000000000000..6b87fd054022d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_base_vseq.sv @@ -0,0 +1,456 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class clkmgr_base_vseq extends cip_base_vseq #( + .RAL_T (clkmgr_reg_block), + .CFG_T (clkmgr_env_cfg), + .COV_T (clkmgr_env_cov), + .VIRTUAL_SEQUENCER_T(clkmgr_virtual_sequencer) +); + + `uvm_object_utils(clkmgr_base_vseq) + `uvm_object_new + + // The extra cycles to wait after reset before starting any test, required so some CSRs (notably + // hints_status) are properly set when inputs go through synchronizers. + localparam int POST_APPLY_RESET_CYCLES = 10; + + // This delay is needed to allow updates to the idle inputs to go through synchronizers and + // counters. + localparam int IDLE_SYNC_CYCLES = 20; + + // This is the timeout for the various clk status outputs to react to their inputs. + localparam int CLK_STATUS_TIMEOUT_NS = 100_000; + + rand bit io_ip_clk_en; + rand bit main_ip_clk_en; + rand bit usb_ip_clk_en; + + rand mubi_hintables_t idle; + + // Override this from cip_base_vseq, since clkmgr tests are relatively short. + constraint rand_reset_delay_c { + rand_reset_delay dist { + [1 : 1000] :/ 1, + [1001 : 100_000] :/ 2, + [100_001 : 1_000_000] :/ 6 + }; + } + + mubi4_t scanmode; + int scanmode_on_weight = 8; + + mubi4_t extclk_ctrl_high_speed_sel; + mubi4_t extclk_ctrl_sel; + clkmgr_mubi_e mubi_mode; + + // This holds the necessary per measure control CSR info. + typedef struct { + string name; + dv_base_reg en; + dv_base_reg_field ctrl_hi; + dv_base_reg_field ctrl_lo; + } meas_ctrl_regs_t; + meas_ctrl_regs_t meas_ctrl_regs[clk_mesr_e]; + + virtual function void set_scanmode_on_low_weight(); + scanmode_on_weight = 2; + endfunction + + function void post_randomize(); + extclk_ctrl_high_speed_sel = get_rand_mubi4_val(6, 2, 2); + extclk_ctrl_sel = get_rand_mubi4_val(4, 2, 2); + scanmode = get_rand_mubi4_val(scanmode_on_weight, 4, 4); + `uvm_info(`gfn, $sformatf( + "randomize: extclk_ctrl_sel=0x%x, extclk_ctrl_high_speed_sel=0x%x, scanmode=0x%x", + extclk_ctrl_sel, + extclk_ctrl_high_speed_sel, + scanmode + ), UVM_MEDIUM) + super.post_randomize(); + endfunction + + virtual task initialize_on_start(); + `uvm_info(`gfn, "In clkmgr_if initialize_on_start", UVM_MEDIUM) + idle = {NUM_TRANS{MuBi4True}}; + scanmode = MuBi4False; + cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode), .lc_debug_en(Off)); + io_ip_clk_en = 1'b1; + main_ip_clk_en = 1'b1; + usb_ip_clk_en = 1'b1; + start_ip_clocks(); + endtask + + // Converts to bool with strict true. + protected function hintables_t mubi_hintables_to_hintables(mubi_hintables_t mubi_hints); + hintables_t ret; + foreach (mubi_hints[i]) ret[i] = prim_mubi_pkg::mubi4_test_true_strict(mubi_hints[i]); + return ret; + endfunction + + local function void disable_unnecessary_exclusions(); + ral.get_excl_item().enable_excl("clkmgr_reg_block.clk_enables", 0); + ral.get_excl_item().enable_excl("clkmgr_reg_block.clk_hints", 0); + `uvm_info(`gfn, "Adjusted exclusions", UVM_MEDIUM) + ral.get_excl_item().print_exclusions(UVM_MEDIUM); + endfunction + + task pre_start(); + meas_ctrl_regs[ClkMesrIo] = '{"io", ral.io_meas_ctrl_en, ral.io_meas_ctrl_shadowed.hi, + ral.io_meas_ctrl_shadowed.lo}; + meas_ctrl_regs[ClkMesrIoDiv2] = '{"io div2", ral.io_div2_meas_ctrl_en, + ral.io_div2_meas_ctrl_shadowed.hi, + ral.io_div2_meas_ctrl_shadowed.lo}; + meas_ctrl_regs[ClkMesrIoDiv4] = '{"io div4", ral.io_div4_meas_ctrl_en, + ral.io_div4_meas_ctrl_shadowed.hi, + ral.io_div4_meas_ctrl_shadowed.lo}; + meas_ctrl_regs[ClkMesrMain] = '{"main", ral.main_meas_ctrl_en, ral.main_meas_ctrl_shadowed.hi, + ral.main_meas_ctrl_shadowed.lo}; + meas_ctrl_regs[ClkMesrUsb] = '{"usb", ral.usb_meas_ctrl_en, ral.usb_meas_ctrl_shadowed.hi, + ral.usb_meas_ctrl_shadowed.lo}; + + mubi_mode = ClkmgrMubiNone; + `DV_GET_ENUM_PLUSARG(clkmgr_mubi_e, mubi_mode, clkmgr_mubi_mode) + `uvm_info(`gfn, $sformatf("mubi_mode = %s", mubi_mode.name), UVM_MEDIUM) + cfg.clkmgr_vif.init(.idle({NUM_TRANS{MuBi4True}}), .scanmode(scanmode), .lc_debug_en(Off)); + cfg.clkmgr_vif.update_io_ip_clk_en(1'b1); + cfg.clkmgr_vif.update_main_ip_clk_en(1'b1); + cfg.clkmgr_vif.update_usb_ip_clk_en(1'b1); + cfg.clkmgr_vif.update_all_clk_byp_ack(MuBi4False); + cfg.clkmgr_vif.update_div_step_down_req(MuBi4False); + cfg.clkmgr_vif.update_io_clk_byp_ack(MuBi4False); + + disable_unnecessary_exclusions(); + clkmgr_init(); + super.pre_start(); + if (common_seq_type inside {"shadow_reg_errors", "shadow_reg_errors_with_csr_rw"}) begin + expect_fatal_alerts = 1; + end + endtask + + virtual task dut_init(string reset_kind = "HARD"); + super.dut_init(reset_kind); + endtask + + virtual task dut_shutdown(); + // check for pending clkmgr operations and wait for them to complete + endtask + + // This turns on the actual input clocks, as the pwrmgr would. + task start_ip_clocks(); + fork + start_io_ip_clock(); + start_main_ip_clock(); + start_usb_ip_clock(); + join + endtask + + task start_io_ip_clock(); + `uvm_info(`gfn, $sformatf( + "starting io clk_en with current status %b", cfg.clkmgr_vif.pwr_o.io_status), + UVM_MEDIUM) + cfg.io_clk_rst_vif.start_clk(); + cfg.clkmgr_vif.pwr_i.io_ip_clk_en = io_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.io_status == 1'b1);, + "timeout waiting for io_status to raise", CLK_STATUS_TIMEOUT_NS) + `uvm_info(`gfn, "starting io clock done", UVM_MEDIUM) + endtask + + task start_main_ip_clock(); + `uvm_info(`gfn, $sformatf( + "starting main clk_en with current status %b", cfg.clkmgr_vif.pwr_o.main_status), + UVM_MEDIUM) + cfg.main_clk_rst_vif.start_clk(); + cfg.clkmgr_vif.pwr_i.main_ip_clk_en = main_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.main_status == 1'b1);, + "timeout waiting for main_status to raise", CLK_STATUS_TIMEOUT_NS) + `uvm_info(`gfn, "starting main clock done", UVM_MEDIUM) + endtask + + task start_usb_ip_clock(); + `uvm_info(`gfn, $sformatf( + "starting usb clk_en with current status %b", cfg.clkmgr_vif.pwr_o.usb_status), + UVM_MEDIUM) + cfg.usb_clk_rst_vif.start_clk(); + cfg.clkmgr_vif.pwr_i.usb_ip_clk_en = usb_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.usb_status == 1'b1);, + "timeout waiting for usb_status to raise", CLK_STATUS_TIMEOUT_NS) + `uvm_info(`gfn, "starting usb clock done", UVM_MEDIUM) + endtask + + // This turns on or off the actual input clocks, as the pwrmgr would. + task control_ip_clocks(); + fork + control_io_ip_clock(); + control_main_ip_clock(); + control_usb_ip_clock(); + join + endtask + + task control_io_ip_clock(); + // Do nothing if nothing interesting changed. + if (cfg.clkmgr_vif.pwr_i.io_ip_clk_en == io_ip_clk_en) return; + `uvm_info(`gfn, $sformatf( + "controlling io clk_en from %b to %b with current status %b", + cfg.clkmgr_vif.pwr_i.io_ip_clk_en, + io_ip_clk_en, + cfg.clkmgr_vif.pwr_o.io_status + ), UVM_MEDIUM) + if (!io_ip_clk_en) begin + cfg.clkmgr_vif.pwr_i.io_ip_clk_en = io_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.io_status == 1'b0);, + "timeout waiting for io_status to fall", CLK_STATUS_TIMEOUT_NS) + cfg.io_clk_rst_vif.stop_clk(); + end else begin + cfg.io_clk_rst_vif.start_clk(); + cfg.clkmgr_vif.pwr_i.io_ip_clk_en = io_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.io_status == 1'b1);, + "timeout waiting for io_status to raise", CLK_STATUS_TIMEOUT_NS) + end + `uvm_info(`gfn, "controlling io clock done", UVM_MEDIUM) + endtask + + task control_main_ip_clock(); + // Do nothing if nothing interesting changed. + if (cfg.clkmgr_vif.pwr_i.main_ip_clk_en == main_ip_clk_en) return; + `uvm_info(`gfn, $sformatf( + "controlling main clk_en from %b to %b with current status %b", + cfg.clkmgr_vif.pwr_i.main_ip_clk_en, + main_ip_clk_en, + cfg.clkmgr_vif.pwr_o.main_status + ), UVM_MEDIUM) + if (!main_ip_clk_en) begin + cfg.clkmgr_vif.pwr_i.main_ip_clk_en = main_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.main_status == 1'b0);, + "timeout waiting for main_status to fall", CLK_STATUS_TIMEOUT_NS) + cfg.main_clk_rst_vif.stop_clk(); + end else begin + cfg.main_clk_rst_vif.start_clk(); + cfg.clkmgr_vif.pwr_i.main_ip_clk_en = main_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.main_status == 1'b1);, + "timeout waiting for main_status to raise", CLK_STATUS_TIMEOUT_NS) + end + `uvm_info(`gfn, "controlling main clock done", UVM_MEDIUM) + endtask + + task control_usb_ip_clock(); + // Do nothing if nothing interesting changed. + if (cfg.clkmgr_vif.pwr_i.usb_ip_clk_en == usb_ip_clk_en) return; + `uvm_info(`gfn, $sformatf( + "controlling usb clk_en from %b to %b with current status %b", + cfg.clkmgr_vif.pwr_i.usb_ip_clk_en, + usb_ip_clk_en, + cfg.clkmgr_vif.pwr_o.usb_status + ), UVM_MEDIUM) + if (!usb_ip_clk_en) begin + cfg.clkmgr_vif.pwr_i.usb_ip_clk_en = usb_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.usb_status == 1'b0);, + "timeout waiting for usb_status to fall", CLK_STATUS_TIMEOUT_NS) + cfg.usb_clk_rst_vif.stop_clk(); + end else begin + cfg.usb_clk_rst_vif.start_clk(); + cfg.clkmgr_vif.pwr_i.usb_ip_clk_en = usb_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.usb_status == 1'b1);, + "timeout waiting for usb_status to raise", CLK_STATUS_TIMEOUT_NS) + end + `uvm_info(`gfn, "controlling usb clock done", UVM_MEDIUM) + endtask + + task disable_frequency_measurement(clk_mesr_e which); + `uvm_info(`gfn, $sformatf("Disabling frequency measurement for %0s", which.name), UVM_MEDIUM) + csr_wr(.ptr(meas_ctrl_regs[which].en), .value(MuBi4False)); + endtask + + local function int get_meas_ctrl_value(int min_threshold, int max_threshold, uvm_reg_field lo, + uvm_reg_field hi); + int lo_mask = (1 << lo.get_n_bits()) - 1; + int hi_mask = (1 << hi.get_n_bits()) - 1; + + int value = (((min_threshold & lo_mask) << lo.get_lsb_pos()) | + ((max_threshold & hi_mask) << hi.get_lsb_pos())); + return value; + endfunction + + // Any non-false mubi value in the enable CSR turns measurements on. + task enable_frequency_measurement(clk_mesr_e which, int min_threshold, int max_threshold); + int value = get_meas_ctrl_value(min_threshold, max_threshold, meas_ctrl_regs[which].ctrl_lo, + meas_ctrl_regs[which].ctrl_hi); + mubi4_t en_value = get_rand_mubi4_val(1, 0, 3); + `uvm_info(`gfn, $sformatf( + "Enabling frequency measurement for %0s, min=0x%x, max=0x%x, expected=0x%x", + which.name, + min_threshold, + max_threshold, + ExpectedCounts[which] + ), UVM_MEDIUM) + csr_wr(.ptr(meas_ctrl_regs[which].ctrl_lo.get_dv_base_reg_parent()), .value(value)); + csr_wr(.ptr(meas_ctrl_regs[which].en), .value(en_value)); + endtask + + // This checks that when calibration is lost regwen should be re-enabled and measurements + // disabled. + task calibration_lost_checks(); + void'(ral.measure_ctrl_regwen.predict(1)); + csr_rd_check(.ptr(ral.measure_ctrl_regwen), .compare_value(1)); + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + csr_rd_check(.ptr(meas_ctrl_regs[clk_mesr].en), .compare_value(MuBi4False)); + end + endtask + + local function void control_sync_pulse_assert(clk_mesr_e clk, bit enable); + case (clk) + ClkMesrIo: begin + if (enable) $asserton(0, "tb.dut.u_io_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + else $assertoff(0, "tb.dut.u_io_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + end + ClkMesrIoDiv2: begin + if (enable) $asserton(0, "tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + else $assertoff(0, "tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + end + ClkMesrIoDiv4: begin + if (enable) $asserton(0, "tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + else $assertoff(0, "tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + end + ClkMesrMain: begin + if (enable) $asserton(0, "tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + else $assertoff(0, "tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + end + ClkMesrUsb: begin + if (enable) $asserton(0, "tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + else $assertoff(0, "tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + end + default: `uvm_error(`gfn, $sformatf("unexpected clock index '%0d'", clk)) + endcase + endfunction + + // This turns off/on some clocks being measured to trigger a measurement timeout. + // A side-effect is that some RTL assertions will fire, so they are corresponsdingly controlled. + task disturb_measured_clock(clk_mesr_e clk, bit enable); + case (clk) + ClkMesrIo, ClkMesrIoDiv2, ClkMesrIoDiv4: begin + if (enable) cfg.io_clk_rst_vif.start_clk(); + else cfg.io_clk_rst_vif.stop_clk(); + control_sync_pulse_assert(.clk(ClkMesrIo), .enable(enable)); + control_sync_pulse_assert(.clk(ClkMesrIoDiv2), .enable(enable)); + control_sync_pulse_assert(.clk(ClkMesrIoDiv4), .enable(enable)); + end + ClkMesrMain: begin + if (enable) cfg.main_clk_rst_vif.start_clk(); + else cfg.main_clk_rst_vif.stop_clk(); + control_sync_pulse_assert(.clk(clk), .enable(enable)); + end + ClkMesrUsb: begin + if (enable) cfg.usb_clk_rst_vif.start_clk(); + else cfg.usb_clk_rst_vif.stop_clk(); + control_sync_pulse_assert(.clk(clk), .enable(enable)); + end + default: `uvm_fatal(`gfn, $sformatf("Unexpected clk '%0d'", clk)) + endcase + endtask + + function void report_recov_error_mismatch(string error_type, recov_bits_t expected, + recov_bits_t actual); + recov_bits_t mismatch = actual ^ expected; + foreach (mismatch[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + if (mismatch[clk]) begin + `uvm_info(`gfn, $sformatf( + "Mismatch %0s for %0s, expected %b, actual %b", + error_type, + clk_mesr.name, + expected[clk], + actual[clk] + ), UVM_LOW) + end + end + `uvm_error(`gfn, $sformatf( + "Mismatch for %0s recoverable error, expected 0b%b, got 0b%b", + error_type, + expected, + actual + )) + endfunction + + // Returns the maximum clock period across non-aon clocks. + local function int maximum_clock_period(); + int clk_periods_q[$] = { + cfg.aon_clk_rst_vif.clk_period_ps, + cfg.io_clk_rst_vif.clk_period_ps * 4, + cfg.main_clk_rst_vif.clk_period_ps, + cfg.usb_clk_rst_vif.clk_period_ps + }; + return max(clk_periods_q); + endfunction + + // This is tricky, and we choose to handle it all here, not in "super": + // - there are no multiple clk_rst_vifs, + // - it would be too complicated to coordinate reset durations with super. + // For hard resets we also reset the cfg.root*_clk_rst_vif, and its reset is shorter than + // that of all others. + virtual task apply_resets_concurrently(int reset_duration_ps = 0); + int clk_periods_q[$] = { + reset_duration_ps, + cfg.aon_clk_rst_vif.clk_period_ps, + cfg.io_clk_rst_vif.clk_period_ps * 4, + cfg.main_clk_rst_vif.clk_period_ps, + cfg.usb_clk_rst_vif.clk_period_ps + }; + reset_duration_ps = max(clk_periods_q); + + `uvm_info(`gfn, "In apply_resets_concurrently", UVM_MEDIUM) + cfg.root_io_clk_rst_vif.drive_rst_pin(0); + cfg.root_main_clk_rst_vif.drive_rst_pin(0); + cfg.root_usb_clk_rst_vif.drive_rst_pin(0); + cfg.aon_clk_rst_vif.drive_rst_pin(0); + cfg.clk_rst_vif.drive_rst_pin(0); + cfg.io_clk_rst_vif.drive_rst_pin(0); + cfg.main_clk_rst_vif.drive_rst_pin(0); + cfg.usb_clk_rst_vif.drive_rst_pin(0); + + #(reset_duration_ps * $urandom_range(2, 10) * 1ps); + cfg.root_io_clk_rst_vif.drive_rst_pin(1); + cfg.root_main_clk_rst_vif.drive_rst_pin(1); + cfg.root_usb_clk_rst_vif.drive_rst_pin(1); + `uvm_info(`gfn, "apply_resets_concurrently releases POR", UVM_MEDIUM) + + #(reset_duration_ps * $urandom_range(2, 10) * 1ps); + cfg.aon_clk_rst_vif.drive_rst_pin(1); + cfg.clk_rst_vif.drive_rst_pin(1); + cfg.io_clk_rst_vif.drive_rst_pin(1); + cfg.main_clk_rst_vif.drive_rst_pin(1); + cfg.usb_clk_rst_vif.drive_rst_pin(1); + `uvm_info(`gfn, "apply_resets_concurrently releases other resets", UVM_MEDIUM) + endtask + + virtual task apply_reset(string kind = "HARD"); + if (kind == "HARD") apply_resets_concurrently(); + else begin + fork + cfg.clk_rst_vif.apply_reset(); + cfg.aon_clk_rst_vif.apply_reset(); + cfg.main_clk_rst_vif.apply_reset(); + cfg.io_clk_rst_vif.apply_reset(); + cfg.usb_clk_rst_vif.apply_reset(); + join + end + endtask + + task post_apply_reset(string reset_kind = "HARD"); + super.post_apply_reset(reset_kind); + initialize_on_start(); + cfg.io_clk_rst_vif.wait_clks(POST_APPLY_RESET_CYCLES); + endtask + + // setup basic clkmgr features + virtual task clkmgr_init(); + // Initialize input clock frequencies. + cfg.main_clk_rst_vif.set_freq_mhz((1.0 * MainClkHz) / 1_000_000); + cfg.io_clk_rst_vif.set_freq_mhz((1.0 * IoClkHz) / 1_000_000); + cfg.usb_clk_rst_vif.set_freq_mhz((1.0 * UsbClkHz) / 1_000_000); + // The real clock rate for aon is 200kHz, but that can slow testing down. + // Increasing its frequency improves DV efficiency without compromising quality. + cfg.aon_clk_rst_vif.set_freq_mhz((1.0 * FakeAonClkHz) / 1_000_000); + endtask +endclass : clkmgr_base_vseq diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_clk_status_vseq.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_clk_status_vseq.sv new file mode 100644 index 0000000000000..f5850366aa9ad --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_clk_status_vseq.sv @@ -0,0 +1,35 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This tests the transitions of the various clock status outputs for random settings of the +// various ip_clk_en inputs. +// +// The checks are done via SVA in clkmgr_pwrmgr_sva_if. +class clkmgr_clk_status_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_clk_status_vseq) + + `uvm_object_new + + function void post_randomize(); + super.post_randomize(); + // Disable scanmode since it is not interesting. + scanmode = prim_mubi_pkg::MuBi4False; + endfunction + + task body(); + for (int i = 0; i < num_trans; ++i) begin + cfg.clk_rst_vif.wait_clks(4); + `DV_CHECK_RANDOMIZE_FATAL(this) + cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode)); + control_ip_clocks(); + + // If some units were not idle, make them so. + idle = '1; + // Wait for idle to percolate. + cfg.clk_rst_vif.wait_clks(10); + end + // And set it back to more common values for stress tests. + initialize_on_start(); + endtask : body +endclass : clkmgr_clk_status_vseq diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_common_vseq.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_common_vseq.sv new file mode 100644 index 0000000000000..21613892f0b76 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_common_vseq.sv @@ -0,0 +1,70 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class clkmgr_common_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_common_vseq) + + constraint num_trans_c {num_trans inside {[1 : 2]};} + `uvm_object_new + + virtual task pre_start(); + csr_excl_item csr_excl = ral.get_excl_item(); + super.pre_start(); + + // Remove rw1c type from same_csr_outstanding + if (common_seq_type == "same_csr_outstanding") begin + csr_excl.add_excl("clkmgr_reg_block.recov_err_code", CsrExclWrite); + end + endtask + + virtual task body(); + run_common_vseq_wrapper(num_trans); + endtask : body + + virtual task check_sec_cm_fi_resp(sec_cm_base_if_proxy if_proxy); + super.check_sec_cm_fi_resp(if_proxy); + + case (if_proxy.sec_cm_type) + SecCmPrimCount: begin + csr_rd_check(.ptr(ral.fatal_err_code.idle_cnt), .compare_value(1)); + end + default: begin + `uvm_error(`gfn, $sformatf("Unexpected sec_cm_type %0s", if_proxy.sec_cm_type.name)) + end + endcase + endtask + + task initialize_on_start(); + super.initialize_on_start(); + // update default idle to false for + // csr test. + cfg.clkmgr_vif.idle_i = {NUM_TRANS{MuBi4False}}; + endtask : initialize_on_start + + // This task is used for non-main clock registers. + // to compensate clock difference, wait longer until + // see get_alert() + task skid_check_fatal_alert_nonblocking(string alert_name); + fork + `DV_SPINWAIT_EXIT( + forever begin + // 1 extra cycle to make sure no race condition + repeat (alert_esc_agent_pkg::ALERT_B2B_DELAY + 20) begin + cfg.clk_rst_vif.wait_n_clks(1); + if (cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1) break; + end + `DV_CHECK_EQ(cfg.m_alert_agent_cfgs[alert_name].vif.get_alert(), 1, + $sformatf("fatal error %0s does not trigger!", alert_name)) + cfg.m_alert_agent_cfgs[alert_name].vif.wait_ack_complete(); + end, + wait(cfg.under_reset);) + join_none + endtask + + // Override shadow_reg_errors task + // to cover shadow regs under clock div2, div4 + task shadow_reg_errors_check_fatal_alert_nonblocking(dv_base_reg shadowed_csr, string alert_name); + skid_check_fatal_alert_nonblocking(alert_name); + endtask +endclass diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_extclk_vseq.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_extclk_vseq.sv new file mode 100644 index 0000000000000..5a10f0e49f963 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_extclk_vseq.sv @@ -0,0 +1,241 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The extclk vseq causes the external clock selection to be triggered. More details +// in the clkmgr_testplan.hjson file. +class clkmgr_extclk_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_extclk_vseq) + + `uvm_object_new + + // When extclk_ctrl_regwen is clear it is not possible to select external clocks. + // This is tested in regular csr_rw, so here this register is simply set to 1. + + // The extclk cannot be manipulated in low power mode. + constraint io_ip_clk_en_on_c {io_ip_clk_en == 1'b1;} + constraint main_ip_clk_en_on_c {main_ip_clk_en == 1'b1;} + constraint usb_ip_clk_en_on_c {usb_ip_clk_en == 1'b1;} + + // This randomizes the time when the extclk_ctrl CSR write and the lc_clk_byp_req + // input is asserted for good measure. Of course, there is a good chance only a single + // one of these trigger a request, so they are also independently tested. + rand int cycles_before_extclk_ctrl_sel; + rand int cycles_before_lc_clk_byp_req; + rand int cycles_before_lc_clk_byp_ack; + rand int cycles_before_all_clk_byp_ack; + rand int cycles_before_div_step_down_req; + rand int cycles_before_io_clk_byp_ack; + rand int cycles_before_next_trans; + + rand int flips_before_io_clk_byp_ack; + rand int flips_before_div_step_down_req; + rand int flips_before_all_clk_byp_ack; + rand int cycles_between_flips; + + constraint cycles_to_stim_c { + cycles_before_extclk_ctrl_sel inside {[4 : 20]}; + cycles_before_lc_clk_byp_req inside {[4 : 20]}; + cycles_before_lc_clk_byp_ack inside {[16 : 30]}; + cycles_before_all_clk_byp_ack inside {[3 : 11]}; + cycles_before_div_step_down_req inside {[3 : 11]}; + cycles_before_io_clk_byp_ack inside {[3 : 11]}; + cycles_before_next_trans inside {[15 : 35]}; + flips_before_io_clk_byp_ack inside {[0 : 3]}; + flips_before_div_step_down_req inside {[0 : 3]}; + flips_before_all_clk_byp_ack inside {[0 : 3]}; + cycles_between_flips inside {[3 : 5]}; + } + + lc_tx_t lc_clk_byp_req; + lc_tx_t lc_debug_en; + mubi4_t io_clk_byp_ack_non_true; + mubi4_t all_clk_byp_ack_non_true; + mubi4_t div_step_down_req_non_true; + + mubi4_t exp_all_clk_byp_ack; + + function void post_randomize(); + if (mubi_mode == ClkmgrMubiLcHand) begin + // increase weight of illegal value only in ClkmgrMubiLcHand + lc_clk_byp_req = get_rand_lc_tx_val(.t_weight(1), .f_weight(1), .other_weight(14)); + end else begin + lc_clk_byp_req = get_rand_lc_tx_val(.t_weight(8), .f_weight(2), .other_weight(2)); + end + if (mubi_mode == ClkmgrMubiLcCtrl) begin + // increase weight of illgal value only in ClkmgrMubiLcHand + lc_debug_en = get_rand_lc_tx_val(.t_weight(1), .f_weight(1), .other_weight(14)); + end else begin + lc_debug_en = get_rand_lc_tx_val(.t_weight(8), .f_weight(2), .other_weight(2)); + end + + io_clk_byp_ack_non_true = get_rand_mubi4_val(.t_weight(0), .f_weight(2), .other_weight(8)); + all_clk_byp_ack_non_true = get_rand_mubi4_val(.t_weight(0), .f_weight(2), .other_weight(8)); + div_step_down_req_non_true = get_rand_mubi4_val(.t_weight(0), .f_weight(2), .other_weight(8)); + + `uvm_info(`gfn, $sformatf( + "randomize gives lc_clk_byp_req=0x%x, lc_debug_en=0x%x", lc_clk_byp_req, lc_debug_en), + UVM_MEDIUM) + super.post_randomize(); + + extclk_ctrl_sel = get_rand_mubi4_val(.t_weight(8), .f_weight(1), .other_weight(1)); + `uvm_info(`gfn, $sformatf("overwrite extclk_ctrl_sel=0x%x", extclk_ctrl_sel), UVM_MEDIUM) + + endfunction + + // Notice only all_clk_byp_req and io_clk_byp_req Mubi4True and Mubi4False cause transitions. + local task delayed_update_all_clk_byp_ack(mubi4_t value, int cycles); + uvm_reg_data_t rd_data; + + if (mubi_mode == ClkmgrMubiHand && value == MuBi4True) begin + repeat (flips_before_all_clk_byp_ack) begin + exp_all_clk_byp_ack = get_rand_mubi4_val(.t_weight(0), .f_weight(1), .other_weight(1)); + cfg.clk_rst_vif.wait_clks(cycles_between_flips); + cfg.clkmgr_vif.update_all_clk_byp_ack(exp_all_clk_byp_ack); + cfg.clk_rst_vif.wait_clks(4); + csr_rd(.ptr(ral.extclk_status), .value(rd_data)); + // csr_rd_check didn't work well for status register read check + `DV_CHECK_EQ(exp_all_clk_byp_ack, rd_data, "extclk_status mismatch") + end + end + cfg.clk_rst_vif.wait_clks(cycles_between_flips); + cfg.clkmgr_vif.update_all_clk_byp_ack(value); + endtask + + local task delayed_update_div_step_down_req(mubi4_t value, int cycles); + if (mubi_mode == ClkmgrMubiDiv && value == MuBi4True) begin + repeat (flips_before_div_step_down_req) begin + cfg.clk_rst_vif.wait_clks(cycles_between_flips); + cfg.clkmgr_vif.update_div_step_down_req(get_rand_mubi4_val( + .t_weight(0), .f_weight(1), .other_weight(1))); + end + end + cfg.clk_rst_vif.wait_clks(cycles_between_flips); + `uvm_info(`gfn, $sformatf("Settling div_step_down_req to 0x%x", value), UVM_MEDIUM) + cfg.clkmgr_vif.update_div_step_down_req(value); + endtask + + local task delayed_update_io_clk_byp_ack(mubi4_t value, int cycles); + if (mubi_mode == ClkmgrMubiHand && value == MuBi4True) begin + repeat (flips_before_io_clk_byp_ack) begin + cfg.clk_rst_vif.wait_clks(cycles_between_flips); + cfg.clkmgr_vif.update_io_clk_byp_ack(get_rand_mubi4_val( + .t_weight(0), .f_weight(1), .other_weight(1))); + end + end + cfg.clk_rst_vif.wait_clks(cycles_between_flips); + `uvm_info(`gfn, $sformatf("Settling io_clk_byp_ack to 0x%x", value), UVM_MEDIUM) + cfg.clkmgr_vif.update_io_clk_byp_ack(value); + endtask + + local task all_clk_byp_handshake(); + forever + @cfg.clkmgr_vif.all_clk_byp_req begin : all_clk_byp_ack + if (cfg.clkmgr_vif.all_clk_byp_req == prim_mubi_pkg::MuBi4True) begin + `uvm_info(`gfn, "Got all_clk_byp_req on", UVM_MEDIUM) + fork + delayed_update_all_clk_byp_ack(MuBi4True, cycles_before_all_clk_byp_ack); + delayed_update_div_step_down_req(MuBi4True, cycles_before_div_step_down_req); + join + end else begin + `uvm_info(`gfn, "Got all_clk_byp_req off", UVM_MEDIUM) + // Set inputs to mubi4 non-True. + fork + delayed_update_all_clk_byp_ack(all_clk_byp_ack_non_true, cycles_before_all_clk_byp_ack); + delayed_update_div_step_down_req(div_step_down_req_non_true, + cycles_before_div_step_down_req); + join + end + end + endtask + + local task io_clk_byp_handshake(); + forever + @cfg.clkmgr_vif.io_clk_byp_req begin : io_clk_byp_ack + if (cfg.clkmgr_vif.io_clk_byp_req == MuBi4True) begin + `uvm_info(`gfn, "Got io_clk_byp_req True", UVM_MEDIUM) + fork + delayed_update_io_clk_byp_ack(MuBi4True, cycles_before_io_clk_byp_ack); + delayed_update_div_step_down_req(MuBi4True, cycles_before_div_step_down_req); + join + end else begin + `uvm_info(`gfn, "Got io_clk_byp_req non True", UVM_MEDIUM) + // Set inputs to mubi4 non-True. + fork + delayed_update_io_clk_byp_ack(io_clk_byp_ack_non_true, cycles_before_io_clk_byp_ack); + delayed_update_div_step_down_req(div_step_down_req_non_true, + cycles_before_div_step_down_req); + join + end + end + endtask + + local task lc_clk_byp_handshake(); + forever + @cfg.clkmgr_vif.lc_clk_byp_ack begin : lc_clk_byp_ack + if (cfg.clkmgr_vif.lc_clk_byp_ack == lc_ctrl_pkg::On) begin + `uvm_info(`gfn, "Got lc_clk_byp_ack on", UVM_MEDIUM) + end + end + endtask + + local task run_test(); + for (int i = 0; i < num_trans; ++i) begin + `DV_CHECK_RANDOMIZE_FATAL(this) + // Init needs to be synchronous. + @cfg.clk_rst_vif.cb begin + cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode), .lc_debug_en(lc_debug_en)); + control_ip_clocks(); + end + fork + begin + cfg.clk_rst_vif.wait_clks(cycles_before_extclk_ctrl_sel); + csr_wr(.ptr(ral.extclk_ctrl), .value({extclk_ctrl_high_speed_sel, extclk_ctrl_sel})); + end + begin + cfg.clk_rst_vif.wait_clks(cycles_before_lc_clk_byp_req); + cfg.clkmgr_vif.update_lc_clk_byp_req(lc_clk_byp_req); + end + join + `uvm_info(`gfn, $sformatf( + { + "extclk_ctrl_sel=0x%0x, extclk_ctrl_high_speed_sel=0x%0x, lc_clk_byp_req=0x%0x, ", + "lc_debug_en=0x%0x, scanmode=0x%0x" + }, + extclk_ctrl_sel, + extclk_ctrl_high_speed_sel, + lc_clk_byp_req, + lc_debug_en, + scanmode + ), UVM_MEDIUM) + csr_rd_check(.ptr(ral.extclk_ctrl), + .compare_value({extclk_ctrl_high_speed_sel, extclk_ctrl_sel})); + if (lc_clk_byp_req == lc_ctrl_pkg::On) begin + wait(cfg.clkmgr_vif.lc_clk_byp_req == lc_ctrl_pkg::On); + cfg.clk_rst_vif.wait_clks(cycles_before_lc_clk_byp_ack); + cfg.clkmgr_vif.update_lc_clk_byp_req(lc_ctrl_pkg::Off); + end + // Disable extclk software control. + csr_wr(.ptr(ral.extclk_ctrl), .value({Off, Off})); + cfg.clk_rst_vif.wait_clks(cycles_before_next_trans); + end + endtask + + task body(); + set_scanmode_on_low_weight(); + csr_wr(.ptr(ral.extclk_ctrl_regwen), .value(1)); + + fork + begin : isolation_fork + fork + all_clk_byp_handshake(); + io_clk_byp_handshake(); + lc_clk_byp_handshake(); + run_test(); + join_any + disable fork; + end + join + endtask + +endclass diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_frequency_timeout_vseq.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_frequency_timeout_vseq.sv new file mode 100644 index 0000000000000..c3c6aafed2b57 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_frequency_timeout_vseq.sv @@ -0,0 +1,142 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The frequency timeout vseq exercises the frequency measurement counters. More details +// in the clkmgr_testplan.hjson file. +class clkmgr_frequency_timeout_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_frequency_timeout_vseq) + + `uvm_object_new + + // This is measured in aon clocks. We need to have a few rounds of measurement for timeouts to + // trigger, since they synchronize to the aon clock, and they wait for a few number of AON + // cycles before declaring a timeout. + localparam int CyclesToGetOneMeasurement = 12; + + // If cause_timeout is set, turn off clk_timeout so it gets a timeout. + rand bit cause_timeout; + constraint cause_timeout_c { + cause_timeout dist { + 1 := 4, + 0 := 1 + }; + } + rand int clk_timeout; + constraint clk_timeout_c {clk_timeout inside {[ClkMesrIo : ClkMesrUsb]};} + + constraint all_clk_en_c { + io_ip_clk_en == 1; + main_ip_clk_en == 1; + usb_ip_clk_en == 1; + } + + // The clock that will be disabled. + clk_mesr_e clk_mesr_timeout; + + // This waits a number of AON cycles so that the timeout can get detected. + task wait_before_read_recov_err_code(); + cfg.aon_clk_rst_vif.wait_clks(CyclesToGetOneMeasurement); + endtask + + // Get things back in normal order. + virtual task apply_resets_concurrently(int reset_duration_ps = 0); + super.apply_resets_concurrently(reset_duration_ps); + if (cause_timeout) disturb_measured_clock(.clk(clk_mesr_timeout), .enable(1'b1)); + endtask + + task body(); + logic [TL_DW-1:0] value; + int prior_alert_count; + int current_alert_count; + csr_wr(.ptr(ral.measure_ctrl_regwen), .value(1)); + + // Make sure the aon clock is running as slow as it is meant to. + cfg.aon_clk_rst_vif.set_freq_khz(AonClkHz / 1_000); + control_ip_clocks(); + // Wait so the frequency change takes effect. + cfg.aon_clk_rst_vif.wait_clks(2); + + // Disable cip scoreboard exp_alert checks since they need very fine control, making checks + // really cumbersome. Instead we rely on the alert count to detect if alert were triggered. + cfg.scoreboard.do_alert_check = 0; + + `uvm_info(`gfn, $sformatf("Will run %0d rounds", num_trans), UVM_MEDIUM) + for (int i = 0; i < num_trans; ++i) begin + clkmgr_recov_err_t actual_recov_err = '{default: '0}; + logic [ClkMesrUsb:0] expected_recov_timeout_err = '0; + bit expect_alert = 0; + `DV_CHECK_RANDOMIZE_FATAL(this) + `uvm_info(`gfn, "New round", UVM_MEDIUM) + + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + int min_threshold; + int max_threshold; + int expected = ExpectedCounts[clk]; + min_threshold = expected - 2; + max_threshold = expected + 2; + enable_frequency_measurement(clk_mesr, min_threshold, max_threshold); + end + + prior_alert_count = cfg.scoreboard.get_alert_count("recov_fault"); + // Allow some cycles for measurements to start before turning off the clocks, since the + // measurement control CSRs are controlled by the clocks we intend to stop. + cfg.aon_clk_rst_vif.wait_clks(4); + clk_mesr_timeout = clk_mesr_e'(clk_timeout); + + if (cause_timeout) begin + `uvm_info(`gfn, $sformatf("Will cause a timeout for clk %0s", clk_mesr_timeout.name()), + UVM_MEDIUM) + if (clk_mesr_timeout inside {ClkMesrIo, ClkMesrIoDiv2, ClkMesrIoDiv4}) begin + // All these clocks are derived from io so that gets disabled, and all derived + // clocks will get a timeout. + expected_recov_timeout_err[ClkMesrIo] = 1; + expected_recov_timeout_err[ClkMesrIoDiv2] = 1; + expected_recov_timeout_err[ClkMesrIoDiv4] = 1; + end else begin + expected_recov_timeout_err[clk_mesr_timeout] = 1; + end + disturb_measured_clock(.clk(clk_mesr_timeout), .enable(1'b0)); + end + wait_before_read_recov_err_code(); + if (cause_timeout) begin + disturb_measured_clock(.clk(clk_mesr_e'(clk_timeout)), .enable(1'b1)); + end + csr_rd(.ptr(ral.recov_err_code), .value(actual_recov_err)); + `uvm_info(`gfn, $sformatf("Got recov err register=0x%x", actual_recov_err), UVM_MEDIUM) + if (actual_recov_err.measures) begin + report_recov_error_mismatch("measurement", recov_bits_t'(0), actual_recov_err.measures); + end + if (!cfg.under_reset && actual_recov_err.timeouts != expected_recov_timeout_err) begin + report_recov_error_mismatch("timeout", expected_recov_timeout_err, + actual_recov_err.timeouts); + end + if (actual_recov_err.shadow_update != 0) begin + `uvm_error(`gfn, "Unexpected recoverable shadow update error") + end + // And check that the alert count increased if there was a timeout. + current_alert_count = cfg.scoreboard.get_alert_count("recov_fault"); + if (cause_timeout) begin + if (!cfg.under_reset) begin + `DV_CHECK_NE(current_alert_count, prior_alert_count, "expected some alerts to fire") + end + end else begin + `DV_CHECK_EQ(current_alert_count, prior_alert_count, "expected no alerts to fire") + end + + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + disable_frequency_measurement(clk_mesr); + end + + // Wait enough time for measurements to complete, and for alerts to get processed + // by the alert agents so expected alerts are properly wound down. + cfg.aon_clk_rst_vif.wait_clks(6); + // And clear errors. + csr_wr(.ptr(ral.recov_err_code), .value('1)); + cfg.aon_clk_rst_vif.wait_clks(2); + end + endtask : body + +endclass diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_frequency_vseq.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_frequency_vseq.sv new file mode 100644 index 0000000000000..67d93694c19c4 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_frequency_vseq.sv @@ -0,0 +1,236 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The frequency vseq exercises the frequency measurement counters. More details +// in the clkmgr_testplan.hjson file. +class clkmgr_frequency_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_frequency_vseq) + + `uvm_object_new + + // This is measured in aon clocks. This is cannot be too precise because of a synchronizer. + localparam int CyclesToGetMeasurements = 6; + + // The aon cycles between measurements, to make sure the previous measurement settles. + localparam int CyclesBetweenMeasurements = 6; + + // This is measured in clkmgr clk_i clocks. It is set to cover worst case delays. + // The clk_i frequency is randomized for IPs, but the clkmgr is hooked to io_div4, which would + // allow a tighter number of cycles. Leaving the clk_i random probably provides more cases, + // so leaving it as is. + localparam int CyclesForErrUpdate = 16; + + // The min ands max offsets from the expected counts. Notice the count occasionally matches + // expected_counts +- 2 because of CDC synchronizers, so the offsets are set carefully to + // avoid spurious results. + // + // The exp_alert cip feature requires a single alert at a time, so we set at most one of the + // clocks to fail measurement. + rand int clk_tested; + constraint clk_tested_c {clk_tested inside {[ClkMesrIo : ClkMesrUsb]};} + + // If cause_saturation is active, force the initial measurement count of clk_tested to a high + // value so the counter will saturate. + rand bit cause_saturation; + + typedef enum int { + MesrLow, + MesrRight, + MesrHigh + } mesr_e; + rand mesr_e mesr; + rand int min_offset; + rand int max_offset; + + mubi4_t calib_rdy; + + constraint thresholds_c { + solve clk_tested before mesr; + solve mesr before min_offset, max_offset; + if (mesr == MesrLow) { + min_offset inside {[-5 : -3]}; + max_offset inside {[-5 : -3]}; + min_offset <= max_offset; + } else + if (mesr == MesrRight) { + min_offset == -2; + max_offset == 2; + } else + if (mesr == MesrHigh) { + min_offset inside {[3 : 5]}; + max_offset inside {[3 : 5]}; + min_offset <= max_offset; + } + } + + constraint all_clk_en_c { + io_ip_clk_en == 1; + main_ip_clk_en == 1; + usb_ip_clk_en == 1; + } + + function void post_randomize(); + calib_rdy = get_rand_mubi4_val(6, 2, 2); + `uvm_info(`gfn, $sformatf("randomize: calib_rdy=0x%x", calib_rdy), UVM_MEDIUM) + super.post_randomize(); + endfunction + + // Keep saturating the count on aon negedges if needed. + local task maybe_saturate_count(bit saturate, clk_mesr_e clk_tested); + forever begin + @cfg.aon_clk_rst_vif.cbn; + if (saturate) cfg.clkmgr_vif.force_high_starting_count(clk_mesr_e'(clk_tested)); + end + endtask + + // This waits a number of cycles so that: + // - at least one measurement completes, and, + // - the measurement has had time to update the recov_err_code CSR. + task wait_before_read_recov_err_code(bit expect_alert); + // Wait for one measurement (takes an extra cycle to really start). + cfg.aon_clk_rst_vif.wait_clks(CyclesToGetMeasurements); + // Wait for the result to propagate to the recov_err_code CSR. + cfg.clk_rst_vif.wait_clks(CyclesForErrUpdate); + endtask + + // If clocks become uncalibrated measure_ctrl_regwen is re-enabled. + task check_measure_ctrl_regwen_for_calib_rdy(); + logic value; + csr_wr(.ptr(ral.measure_ctrl_regwen), .value(0)); + cfg.clkmgr_vif.update_calib_rdy(MuBi4False); + cfg.clk_rst_vif.wait_clks(20); + calibration_lost_checks(); + endtask + + task body(); + logic [TL_DW-1:0] value; + int prior_alert_count; + int current_alert_count; + + csr_wr(.ptr(ral.measure_ctrl_regwen), .value(1)); + + // Disable alert checks since we cannot make sure a single alert will fire: there is too + // much uncertainty on the cycles for one measurement to complete due to synchronizers. + // This test will instead check whether alerts fire using the alert count. + cfg.scoreboard.do_alert_check = 0; + + // Make sure the aon clock is running as slow as it is meant to. + cfg.aon_clk_rst_vif.set_freq_khz(AonClkHz / 1_000); + control_ip_clocks(); + // Wait so the frequency change takes effect. + cfg.aon_clk_rst_vif.wait_clks(2); + + // Set the thresholds to get no error. + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + enable_frequency_measurement(clk_mesr, ExpectedCounts[clk] - 2, ExpectedCounts[clk] + 2); + end + wait_before_read_recov_err_code('0); + csr_rd_check(.ptr(ral.recov_err_code), .compare_value('0), + .err_msg("Expected no measurement errors")); + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + disable_frequency_measurement(clk_mesr); + end + cfg.aon_clk_rst_vif.wait_clks(CyclesBetweenMeasurements); + // And clear errors. + csr_wr(.ptr(ral.recov_err_code), .value('1)); + + `uvm_info(`gfn, $sformatf("Will run %0d rounds", num_trans), UVM_MEDIUM) + for (int i = 0; i < num_trans; ++i) begin + clkmgr_recov_err_t actual_recov_err = '{default: '0}; + logic [ClkMesrUsb:0] expected_recov_meas_err = '0; + bit expect_alert = 0; + `DV_CHECK_RANDOMIZE_FATAL(this) + // Update calib_rdy input: if calibration is not ready the measurements + // don't happen, so we should not get faults. + cfg.clkmgr_vif.update_calib_rdy(calib_rdy); + `uvm_info(`gfn, $sformatf( + "Updating calib_rdy to 0x%x, predicted regwen 0x%x", + calib_rdy, + ral.measure_ctrl_regwen.get() + ), UVM_MEDIUM) + `uvm_info(`gfn, "New round", UVM_MEDIUM) + // Allow calib_rdy to generate side-effects. + cfg.clk_rst_vif.wait_clks(3); + if (calib_rdy == MuBi4False) calibration_lost_checks(); + prior_alert_count = cfg.scoreboard.get_alert_count("recov_fault"); + if (cause_saturation) `uvm_info(`gfn, "Will cause saturation", UVM_MEDIUM) + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + int min_threshold; + int max_threshold; + int expected = ExpectedCounts[clk]; + if (clk == clk_tested) begin + min_threshold = expected + min_offset; + max_threshold = expected + max_offset; + if (calib_rdy != MuBi4False && + (min_threshold > expected || max_threshold < expected - 1 || cause_saturation)) begin + `uvm_info(`gfn, $sformatf( + "Expect %0s to get a %0s error%0s", + clk_mesr.name, + (cause_saturation ? "fast" : (min_threshold > expected ? "slow" : "fast")), + (cause_saturation ? " due to saturation" : "") + ), UVM_MEDIUM) + expect_alert = 1; + expected_recov_meas_err[clk] = 1; + end + end else begin + min_threshold = expected - 2; + max_threshold = expected + 2; + end + enable_frequency_measurement(clk_mesr, min_threshold, max_threshold); + end + + fork + begin : wait_for_measurements + fork + maybe_saturate_count(cause_saturation, clk_mesr_e'(clk_tested)); + wait_before_read_recov_err_code(expect_alert); + join_any + disable fork; + end + join + + csr_rd(.ptr(ral.recov_err_code), .value(actual_recov_err)); + `uvm_info(`gfn, $sformatf("Expected recov err register=0x%x", expected_recov_meas_err), + UVM_MEDIUM) + if (!cfg.under_reset && actual_recov_err.measures != expected_recov_meas_err) begin + report_recov_error_mismatch("measurement", expected_recov_meas_err, + actual_recov_err.measures); + end + if (actual_recov_err.timeouts != '0) begin + `uvm_error(`gfn, $sformatf( + "Unexpected recoverable timeout error 0b%b", actual_recov_err.timeouts)) + end + if (actual_recov_err.shadow_update != 0) begin + `uvm_error(`gfn, "Unexpected recoverable shadow update error") + end + // Check alerts. + current_alert_count = cfg.scoreboard.get_alert_count("recov_fault"); + if (expect_alert) begin + if (!cfg.under_reset) begin + `DV_CHECK_NE(current_alert_count, prior_alert_count, "expected some alerts to fire") + end + end else begin + `DV_CHECK_EQ(current_alert_count, prior_alert_count, "expected no alerts to fire") + end + + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + disable_frequency_measurement(clk_mesr); + end + + // Wait enough time for measurements to complete, and for alerts to get processed + // by the alert agents so expected alerts are properly wound down. + cfg.aon_clk_rst_vif.wait_clks(CyclesBetweenMeasurements); + // And clear errors. + csr_wr(.ptr(ral.recov_err_code), .value('1)); + cfg.aon_clk_rst_vif.wait_clks(12); + end + // And finally, check that unsetting calib_rdy causes meaesure_ctrl_regwen to be set to 1. + check_measure_ctrl_regwen_for_calib_rdy(); + endtask + +endclass diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_peri_vseq.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_peri_vseq.sv new file mode 100644 index 0000000000000..a389f66d7b8ea --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_peri_vseq.sv @@ -0,0 +1,51 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Tests the control of the peripheral clocks using clk_enables CSR. +// +// This is more general than the corresponding smoke test since it randomizes the initial +// value of clk_enables CSR and the ip_clk_en input. +// +// The expectation is that the peripheral clocks will be sampled at their rate, so this +// sequence needs to wait for the slowest clock to tick before changing enable values. +// The dv environment sets the CSRs clock frequency randomly, so it may run too fast and +// the updates may become a glitch that ends up not sampled in the SVAs. +// To be safe this waits for two cycles of the slowest clock (io_div_4) which is eight +// io_clk cycles. + +class clkmgr_peri_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_peri_vseq) + + `uvm_object_new + + // IO clock cycles to wait before changing clk enable settings. + static int WaitIoCycles = 8; + + rand peri_enables_t initial_enables; + + // The clk_enables CSR cannot be manipulated in low power mode. + constraint io_ip_clk_en_on_c {io_ip_clk_en == 1'b1;} + constraint main_ip_clk_en_on_c {main_ip_clk_en == 1'b1;} + // ICEBOX(#17963) randomize the usb clk enable. + constraint usb_ip_clk_en_on_c {usb_ip_clk_en == 1'b1;} + + task body(); + for (int i = 0; i < num_trans; ++i) begin + peri_enables_t flipped_enables; + `DV_CHECK_RANDOMIZE_FATAL(this) + cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode)); + control_ip_clocks(); + csr_wr(.ptr(ral.clk_enables), .value(initial_enables)); + + cfg.io_clk_rst_vif.wait_clks(WaitIoCycles); + // Flip all bits of clk_enables. + flipped_enables = initial_enables ^ ((1 << ral.clk_enables.get_n_bits()) - 1); + csr_wr(.ptr(ral.clk_enables), .value(flipped_enables)); + cfg.io_clk_rst_vif.wait_clks(WaitIoCycles); + end + // And set it back to the reset value for stress tests. + cfg.clk_rst_vif.wait_clks(1); + csr_wr(.ptr(ral.clk_enables), .value(ral.clk_enables.get_reset())); + endtask : body +endclass : clkmgr_peri_vseq diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_regwen_vseq.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_regwen_vseq.sv new file mode 100644 index 0000000000000..ec5d4896a650d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_regwen_vseq.sv @@ -0,0 +1,82 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The regwen vseq attempts to write to registers whose regwen is randomly on or off to check +// the register contents is not updated when off. More details in the clkmgr_testplan.hjson file. +class clkmgr_regwen_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_regwen_vseq) + + `uvm_object_new + + task check_extclk_regwen(); + bit enable; + int prev_value; + int new_value = {extclk_ctrl_high_speed_sel, extclk_ctrl_sel}; + `DV_CHECK_STD_RANDOMIZE_FATAL(enable) + `uvm_info(`gfn, $sformatf("Check extclk_ctrl regwen set to %b begin", enable), UVM_MEDIUM) + csr_wr(.ptr(ral.extclk_ctrl_regwen), .value(enable)); + csr_rd(.ptr(ral.extclk_ctrl), .value(prev_value)); + csr_wr(.ptr(ral.extclk_ctrl), .value(new_value)); + csr_rd_check(.ptr(ral.extclk_ctrl), .compare_value(enable ? new_value : prev_value)); + `uvm_info(`gfn, "Check extclk_ctrl regwen end", UVM_MEDIUM) + endtask : check_extclk_regwen + + // This must be careful to turn measurements off right after checking the updates + // to avoid measurement errors. We could set the thresholds correctly, but we + // might as well set them randomly for good measure. Carefully masks only the + // real bits for the comparison. + task check_meas_ctrl_regwen(); + bit regwen_enable; + `DV_CHECK_STD_RANDOMIZE_FATAL(regwen_enable) + csr_wr(.ptr(ral.measure_ctrl_regwen), .value(regwen_enable)); + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + uvm_reg ctrl_shadowed = meas_ctrl_regs[clk_mesr].ctrl_lo.get_dv_base_reg_parent(); + uvm_reg_data_t prev_en; + mubi4_t new_en = get_rand_mubi4_val(1, 1, 2); + int prev_ctrl; + int new_ctrl = $urandom(); + int actual_ctrl; + int lo_mask = ((1 << meas_ctrl_regs[clk_mesr].ctrl_lo.get_n_bits()) - 1) << + meas_ctrl_regs[clk_mesr].ctrl_lo.get_lsb_pos(); + int hi_mask = ((1 << meas_ctrl_regs[clk_mesr].ctrl_hi.get_n_bits()) - 1) << + meas_ctrl_regs[clk_mesr].ctrl_hi.get_lsb_pos(); + `uvm_info(`gfn, $sformatf( + "Check %0s regwen set to %b begin", meas_ctrl_regs[clk_mesr].name, regwen_enable), + UVM_MEDIUM) + csr_rd(.ptr(meas_ctrl_regs[clk_mesr].en), .value(prev_en)); + csr_rd(.ptr(ctrl_shadowed), .value(prev_ctrl)); + csr_wr(.ptr(ctrl_shadowed), .value(new_ctrl)); + csr_wr(.ptr(meas_ctrl_regs[clk_mesr].en), .value(new_en)); + csr_rd_check(.ptr(meas_ctrl_regs[clk_mesr].en), + .compare_value(mubi4_t'(regwen_enable ? new_en : prev_en))); + csr_rd_check(.ptr(ctrl_shadowed), .compare_value(regwen_enable ? new_ctrl : prev_ctrl), + .compare_mask(lo_mask | hi_mask)); + `uvm_info(`gfn, $sformatf("Check %0s regwen end", meas_ctrl_regs[clk_mesr].name), + UVM_MEDIUM) + csr_wr(.ptr(meas_ctrl_regs[clk_mesr].en), .value(MuBi4False)); + end + endtask : check_meas_ctrl_regwen + + task body(); + // Make sure the aon clock is running as slow as it is meant to, otherwise the aon clock + // runs fast enough that we could end up triggering faults due to the random settings for + // the thresholds. + cfg.aon_clk_rst_vif.set_freq_khz(AonClkHz / 1_000); + + `uvm_info(`gfn, $sformatf("Will run %0d rounds", num_trans), UVM_MEDIUM) + for (int i = 0; i < num_trans; ++i) begin + check_extclk_regwen(); + check_meas_ctrl_regwen(); + apply_reset("HARD"); + // This is to make sure we don't start writes immediately after reset, + // otherwise the tl_agent could mistakenly consider the following read + // happens during reset. + cfg.clk_rst_vif.wait_clks(4); + csr_rd_check(.ptr(ral.extclk_ctrl_regwen), .compare_value(1)); + csr_rd_check(.ptr(ral.measure_ctrl_regwen), .compare_value(1)); + end + endtask : body + +endclass : clkmgr_regwen_vseq diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv new file mode 100644 index 0000000000000..6807809aec382 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv @@ -0,0 +1,108 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// smoke test vseq +class clkmgr_smoke_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_smoke_vseq) + + `uvm_object_new + + constraint io_ip_clk_en_on_c {io_ip_clk_en == 1'b1;} + constraint main_ip_clk_en_on_c {main_ip_clk_en == 1'b1;} + constraint usb_ip_clk_en_on_c {usb_ip_clk_en == 1'b1;} + constraint all_busy_c {idle == IdleAllBusy;} + + task body(); + cfg.clk_rst_vif.wait_clks(10); + test_jitter(); + test_peri_clocks(); + test_trans_clocks(); + endtask : body + + // Simply flip the jitter enable CSR. The side-effects are checked in the scoreboard. + // This needs to be done outside the various CSR tests, since they update the jitter_enable + // CSR, but the scoreboard is disabled for those tests. + task test_jitter(); + prim_mubi_pkg::mubi4_t jitter_value; + for (int i = 0; i < (1 << $bits(prim_mubi_pkg::mubi4_t)); ++i) begin + jitter_value = prim_mubi_pkg::mubi4_t'(i); + csr_wr(.ptr(ral.jitter_enable), .value(jitter_value)); + csr_rd_check(.ptr(ral.jitter_enable), .compare_value(jitter_value)); + // And set it back. + cfg.clk_rst_vif.wait_clks(6); + csr_wr(.ptr(ral.jitter_enable), .value('0)); + csr_rd_check(.ptr(ral.jitter_enable), .compare_value('0)); + end + endtask + + // Flips all clk_enables bits from the reset value with all enabled. All is checked + // via assertions in clkmgr_if.sv and behavioral code in the scoreboard. + task test_peri_clocks(); + // Flip all bits of clk_enables. + peri_enables_t value = ral.clk_enables.get(); + peri_enables_t flipped_value; + csr_rd(.ptr(ral.clk_enables), .value(value)); + flipped_value = value ^ ((1 << ral.clk_enables.get_n_bits()) - 1); + csr_wr(.ptr(ral.clk_enables), .value(flipped_value)); + + // And set it back to the reset value for stress tests. + cfg.clk_rst_vif.wait_clks(1); + csr_wr(.ptr(ral.clk_enables), .value(ral.clk_enables.get_reset())); + endtask : test_peri_clocks + + // Starts with all units busy, and for each one this clears the hint and reads the hint status, + // expecting it to remain at 1 since the unit is busy; then it sets the corresponding idle bit + // and reads status again, expecting it to be low. + // + // We disable the value checks when reset is active since the reads return unpredictable data. + task test_trans_clocks(); + trans_e trans; + logic bit_value; + logic [TL_DW-1:0] value; + mubi_hintables_t idle; + hintables_t bool_idle; + typedef struct { + trans_e unit; + uvm_reg_field hint_bit; + uvm_reg_field value_bit; + } trans_descriptor_t; + trans_descriptor_t trans_descriptors[NUM_TRANS] = '{ + '{TransAes, ral.clk_hints.clk_main_aes_hint, ral.clk_hints_status.clk_main_aes_val}, + '{TransHmac, ral.clk_hints.clk_main_hmac_hint, ral.clk_hints_status.clk_main_hmac_val}, + '{TransKmac, ral.clk_hints.clk_main_kmac_hint, ral.clk_hints_status.clk_main_kmac_val}, + '{TransOtbn, ral.clk_hints.clk_main_otbn_hint, ral.clk_hints_status.clk_main_otbn_val} + }; + idle = 0; + // Changes in idle take at least 10 cycles to stick. + cfg.clkmgr_vif.update_idle(idle); + cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES); + + trans = trans.first; + csr_rd(.ptr(ral.clk_hints), .value(value)); + `uvm_info(`gfn, $sformatf("Starting hints at 0x%0x, idle at 0x%x", value, idle), UVM_MEDIUM) + do begin + trans_descriptor_t descriptor = trans_descriptors[int'(trans)]; + `uvm_info(`gfn, $sformatf("Clearing %s hint bit", descriptor.unit.name), UVM_MEDIUM) + csr_wr(.ptr(descriptor.hint_bit), .value(1'b0)); + csr_rd(.ptr(descriptor.value_bit), .value(bit_value)); + if (!cfg.under_reset) begin + `DV_CHECK_EQ(bit_value, 1'b1, $sformatf( + "%s hint value cannot drop while busy", descriptor.unit.name())) + end + `uvm_info(`gfn, $sformatf("Setting %s idle bit", descriptor.unit.name), UVM_MEDIUM) + cfg.clk_rst_vif.wait_clks(1); + idle[trans] = prim_mubi_pkg::MuBi4True; + cfg.clkmgr_vif.update_idle(idle); + // Some cycles for the logic to settle. + cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES); + csr_rd(.ptr(descriptor.value_bit), .value(bit_value)); + if (!cfg.under_reset) begin + `DV_CHECK_EQ(bit_value, 1'b0, $sformatf( + "%s hint value should drop when idle", descriptor.unit.name())) + end + trans = trans.next(); + end while (trans != trans.first); + csr_wr(.ptr(ral.clk_hints), .value(ral.clk_hints.get_reset())); + endtask : test_trans_clocks +endclass : clkmgr_smoke_vseq diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_stress_all_vseq.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_stress_all_vseq.sv new file mode 100644 index 0000000000000..c8e0aa5860aa0 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_stress_all_vseq.sv @@ -0,0 +1,44 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// combine all clkmgr seqs (except below seqs) in one seq to run sequentially +// 1. csr seq, which requires scb to be disabled +class clkmgr_stress_all_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_stress_all_vseq) + + `uvm_object_new + + task body(); + string seq_names[] = { + "clkmgr_extclk_vseq", + "clkmgr_frequency_timeout_vseq", + "clkmgr_frequency_vseq", + "clkmgr_peri_vseq", + "clkmgr_smoke_vseq", + "clkmgr_trans_vseq" + }; + for (int i = 1; i <= num_trans; i++) begin + uvm_sequence seq; + clkmgr_base_vseq clkmgr_vseq; + uint seq_idx = $urandom_range(0, seq_names.size - 1); + + seq = create_seq_by_name(seq_names[seq_idx]); + `downcast(clkmgr_vseq, seq) + + // if upper seq disables do_apply_reset for this seq, then can't issue reset + // as upper seq may drive reset + if (do_apply_reset) clkmgr_vseq.do_apply_reset = $urandom_range(0, 1); + else clkmgr_vseq.do_apply_reset = 0; + clkmgr_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(clkmgr_vseq) + `uvm_info(`gfn, $sformatf("seq_idx = %0d, sequence is %0s", seq_idx, clkmgr_vseq.get_name()), + UVM_MEDIUM) + + clkmgr_vseq.start(p_sequencer); + `uvm_info(`gfn, $sformatf( + "End of sequence %0s with seq_idx = %0d", clkmgr_vseq.get_name(), seq_idx), + UVM_MEDIUM) + end + endtask : body +endclass diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_trans_vseq.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_trans_vseq.sv new file mode 100644 index 0000000000000..2474ec2ab394e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_trans_vseq.sv @@ -0,0 +1,96 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// trans test vseq +// This is a more randomized version of the corresponding test in the smoke sequence. +// Starts with random units busy, set the hints at random. The idle units whose hint bit is off +// will be disabled, but the others will remain enabled. Then all units are made idle to check +// that status matches hints. Prior to the next round this raises all hints so all unit clocks are +// running. +// +// Transitions to turn off the clock only go through if idle is asserted for at least 10 main +// cycles, and there is additional synchronizer overhead. +// +// The checks for whether each unit's clock are running are done in SVA. This sequence only +// explicitly checks hints_status. + +class clkmgr_trans_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_trans_vseq) + + `uvm_object_new + + rand hintables_t initial_hints; + + // The clk_hints CSR cannot be manipulated in low power mode. + constraint io_ip_clk_en_on_c {io_ip_clk_en == 1'b1;} + constraint main_ip_clk_en_on_c {main_ip_clk_en == 1'b1;} + constraint usb_ip_clk_en_on_c {usb_ip_clk_en == 1'b1;} + + task body(); + for (int i = 0; i < num_trans; ++i) begin + logic bit_value; + hintables_t value; + hintables_t bool_idle; + + `DV_CHECK_RANDOMIZE_FATAL(this) + + csr_rd(.ptr(ral.clk_hints_status), .value(value)); + + `uvm_info(`gfn, $sformatf("Initial clk_hints_status: %b", value), UVM_MEDIUM) + cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode)); + + // add random value if mubi idle test + if (mubi_mode == ClkmgrMubiIdle) drive_idle(idle); + print_mubi_hintable(idle); + control_ip_clocks(); + `uvm_info(`gfn, $sformatf("Idle = 0x%x", cfg.clkmgr_vif.idle_i), UVM_MEDIUM) + cfg.clk_rst_vif.wait_clks(10); + `uvm_info(`gfn, $sformatf("Updating hints to 0x%0x", initial_hints), UVM_MEDIUM) + csr_wr(.ptr(ral.clk_hints), .value(initial_hints)); + + // Extra wait because of synchronizers plus counters. + cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES); + // We expect the status to be determined by hints and idle, ignoring scanmode. + bool_idle = mubi_hintables_to_hintables(idle); + value = initial_hints | ~bool_idle; + csr_rd_check(.ptr(ral.clk_hints_status), .compare_value(value), + .err_msg($sformatf( + "Busy units have status high: hints=0x%x, idle=0x%x", + initial_hints, + bool_idle + ))); + + // Setting all idle should make hint_status match hints. + `uvm_info(`gfn, "Setting all units idle", UVM_MEDIUM) + cfg.clkmgr_vif.update_idle({NUM_TRANS{MuBi4True}}); + cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES); + + csr_rd_check(.ptr(ral.clk_hints_status), .compare_value(initial_hints), + .err_msg("All idle: expect status matches hints")); + + // Now set all hints, and the status should also be all ones. + value = '1; + csr_wr(.ptr(ral.clk_hints), .value(value)); + cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES); + // We expect all units to be on. + csr_rd_check(.ptr(ral.clk_hints_status), .compare_value(value), + .err_msg("All idle and all hints high: units status should be high")); + + // Set hints to the reset value for stress tests. + csr_wr(.ptr(ral.clk_hints), .value(ral.clk_hints.get_reset())); + end + endtask : body + + task drive_idle(ref mubi_hintables_t tbl); + int period; + mubi_hintables_t rand_idle; + foreach (rand_idle[i]) + rand_idle[i] = get_rand_mubi4_val(.t_weight(0), .f_weight(0), .other_weight(1)); + + @cfg.clkmgr_vif.trans_cb; + cfg.clkmgr_vif.idle_i = rand_idle; + + tbl = rand_idle; + endtask : drive_idle +endclass : clkmgr_trans_vseq diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_vseq_list.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_vseq_list.sv new file mode 100644 index 0000000000000..c125df499f28a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_vseq_list.sv @@ -0,0 +1,15 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "clkmgr_base_vseq.sv" +`include "clkmgr_clk_status_vseq.sv" +`include "clkmgr_common_vseq.sv" +`include "clkmgr_frequency_timeout_vseq.sv" +`include "clkmgr_frequency_vseq.sv" +`include "clkmgr_extclk_vseq.sv" +`include "clkmgr_peri_vseq.sv" +`include "clkmgr_regwen_vseq.sv" +`include "clkmgr_smoke_vseq.sv" +`include "clkmgr_stress_all_vseq.sv" +`include "clkmgr_trans_vseq.sv" diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_aon_cg_en_sva_if.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_aon_cg_en_sva_if.sv new file mode 100644 index 0000000000000..9e0bcbf7e1e84 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_aon_cg_en_sva_if.sv @@ -0,0 +1,10 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions for clock gating output to alert_handler for +// AON clocks: they are never gated off. +interface clkmgr_aon_cg_en_sva_if (input logic cg_en); + + `ASSERT_INIT_NET(CgEn_A, !cg_en) +endinterface diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv new file mode 100644 index 0000000000000..5eaff15956503 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv @@ -0,0 +1,357 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module clkmgr_bind; +`ifndef GATE_LEVEL + bind clkmgr tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); + + // In top-level testbench, do not bind the csr_assert_fpv to reduce simulation time. +`ifndef TOP_LEVEL_DV + bind clkmgr clkmgr_csr_assert_fpv clkmgr_csr_assert (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); +`endif + + bind clkmgr clkmgr_pwrmgr_sva_if #(.IS_USB(0)) clkmgr_pwrmgr_main_sva_if ( + .clk_i, + .rst_ni, + .clk_en(pwr_i.main_ip_clk_en), + .status(pwr_o.main_status) + ); + + bind clkmgr clkmgr_pwrmgr_sva_if #(.IS_USB(0)) clkmgr_pwrmgr_io_sva_if ( + .clk_i, + .rst_ni, + .clk_en(pwr_i.io_ip_clk_en), + .status(pwr_o.io_status) + ); + + bind clkmgr clkmgr_pwrmgr_sva_if #(.IS_USB(1)) clkmgr_pwrmgr_usb_sva_if ( + .clk_i, + .rst_ni, + .clk_en(pwr_i.usb_ip_clk_en), + .status(pwr_o.usb_status) + ); + + bind clkmgr clkmgr_gated_clock_sva_if clkmgr_io_div4_peri_sva_if ( + .clk(clocks_o.clk_io_div4_powerup), + .rst_n(rst_io_div4_ni), + .ip_clk_en(pwr_i.io_ip_clk_en), + .sw_clk_en(clk_io_div4_peri_sw_en), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .gated_clk(clocks_o.clk_io_div4_peri) + ); + + bind clkmgr clkmgr_gated_clock_sva_if clkmgr_io_div2_peri_sva_if ( + .clk(clocks_o.clk_io_div2_powerup), + .rst_n(rst_io_div2_ni), + .ip_clk_en(pwr_i.io_ip_clk_en), + .sw_clk_en(clk_io_div2_peri_sw_en), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .gated_clk(clocks_o.clk_io_div2_peri) + ); + + bind clkmgr clkmgr_gated_clock_sva_if clkmgr_usb_peri_sva_if ( + .clk(clocks_o.clk_usb_powerup), + .rst_n(rst_usb_ni), + .ip_clk_en(pwr_i.usb_ip_clk_en), + .sw_clk_en(clk_usb_peri_sw_en), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .gated_clk(clocks_o.clk_usb_peri) + ); + + // Assertions for transactional clocks. + bind clkmgr clkmgr_trans_sva_if clkmgr_aes_trans_sva_if ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .hint(reg2hw.clk_hints.clk_main_aes_hint.q), + .idle(idle_i[HintMainAes] == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .status(hw2reg.clk_hints_status.clk_main_aes_val.d), + .trans_clk(clocks_o.clk_main_aes) + ); + + bind clkmgr clkmgr_trans_sva_if clkmgr_hmac_trans_sva_if ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .hint(reg2hw.clk_hints.clk_main_hmac_hint.q), + .idle(idle_i[HintMainHmac] == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .status(hw2reg.clk_hints_status.clk_main_hmac_val.d), + .trans_clk(clocks_o.clk_main_hmac) + ); + + bind clkmgr clkmgr_trans_sva_if clkmgr_kmac_trans_sva_if ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .hint(reg2hw.clk_hints.clk_main_kmac_hint.q), + .idle(idle_i[HintMainKmac] == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .status(hw2reg.clk_hints_status.clk_main_kmac_val.d), + .trans_clk(clocks_o.clk_main_kmac) + ); + + bind clkmgr clkmgr_trans_sva_if clkmgr_otbn_trans_sva_if ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .hint(reg2hw.clk_hints.clk_main_otbn_hint.q), + .idle(idle_i[HintMainOtbn] == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .status(hw2reg.clk_hints_status.clk_main_otbn_val.d), + .trans_clk(clocks_o.clk_main_otbn) + ); + + bind clkmgr clkmgr_extclk_sva_if clkmgr_extclk_sva_if ( + .clk_i, + .rst_ni, + .extclk_ctrl_sel, + .extclk_ctrl_hi_speed_sel, + .lc_hw_debug_en_i, + .lc_clk_byp_req_i, + .io_clk_byp_req_o, + .all_clk_byp_req_o, + .hi_speed_sel_o + ); + + bind clkmgr clkmgr_div_sva_if #( + .DIV(2) + ) clkmgr_div2_sva_if ( + .clk(clocks_o.clk_io_powerup), + .rst_n(rst_ni), + .maybe_divided_clk(clocks_o.clk_io_div2_powerup), + .div_step_down_req_i(div_step_down_req_i == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True) + ); + + // The div2 clk also steps, so not a good reference. Instead, check it always tracks io_div2. + bind clkmgr clkmgr_div_sva_if #( + .DIV(4) + ) clkmgr_div4_sva_if ( + .clk(clocks_o.clk_io_div2_powerup), + .rst_n(rst_ni), + .maybe_divided_clk(clocks_o.clk_io_div4_powerup), + .div_step_down_req_i(div_step_down_req_i == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True) + ); + + // AON clock gating enables. + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_aon_infra ( + .cg_en(cg_en_o.aon_infra == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_aon_peri ( + .cg_en(cg_en_o.aon_peri == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_aon_powerup ( + .cg_en(cg_en_o.aon_powerup == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_aon_secure ( + .cg_en(cg_en_o.aon_secure == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_aon_timers ( + .cg_en(cg_en_o.aon_timers == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_io_div2_powerup ( + .cg_en(cg_en_o.io_div2_powerup == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_io_div4_powerup ( + .cg_en(cg_en_o.io_div4_powerup == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_io_powerup ( + .cg_en(cg_en_o.io_powerup == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_main_powerup ( + .cg_en(cg_en_o.main_powerup == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_usb_powerup ( + .cg_en(cg_en_o.usb_powerup == prim_mubi_pkg::MuBi4True) + ); + + // Non-AON clock gating enables with no software control. + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div4_infra ( + .clk(clk_io_div4), + .rst_n(rst_io_div4_ni), + .ip_clk_en(clk_io_div4_en), + .sw_clk_en(1'b1), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.io_div4_infra == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div4_secure ( + .clk(clk_io_div4), + .rst_n(rst_io_div4_ni), + .ip_clk_en(clk_io_div4_en), + .sw_clk_en(1'b1), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.io_div4_secure == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div4_timers ( + .clk(clk_io_div4), + .rst_n(rst_io_div4_ni), + .ip_clk_en(clk_io_div4_en), + .sw_clk_en(1'b1), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.io_div4_timers == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_infra ( + .clk(clk_main), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(1'b1), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_infra == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_secure ( + .clk(clk_main), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(1'b1), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_secure == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_usb_infra ( + .clk(clk_usb), + .rst_n(rst_usb_ni), + .ip_clk_en(clk_usb_en), + .sw_clk_en(1'b1), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.usb_infra == prim_mubi_pkg::MuBi4True) + ); + + // Software controlled gating enables. + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div4_peri ( + .clk(clk_io_div4), + .rst_n(rst_io_div4_ni), + .ip_clk_en(clk_io_div4_en), + .sw_clk_en(clk_io_div4_peri_sw_en), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.io_div4_peri == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div2_peri ( + .clk(clk_io_div2), + .rst_n(rst_io_div2_ni), + .ip_clk_en(clk_io_div2_en), + .sw_clk_en(clk_io_div2_peri_sw_en), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.io_div2_peri == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_usb_peri ( + .clk(clk_usb), + .rst_n(rst_usb_ni), + .ip_clk_en(clk_usb_en), + .sw_clk_en(clk_usb_peri_sw_en), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.usb_peri == prim_mubi_pkg::MuBi4True) + ); + + // Hint controlled gating enables. + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_aes ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(u_clk_main_aes_trans.sw_hint_synced || !u_clk_main_aes_trans.idle_valid), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_aes == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_hmac ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(u_clk_main_hmac_trans.sw_hint_synced || !u_clk_main_hmac_trans.idle_valid), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_hmac == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_kmac ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(u_clk_main_kmac_trans.sw_hint_synced || !u_clk_main_kmac_trans.idle_valid), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_kmac == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_otbn ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(u_clk_main_otbn_trans.sw_hint_synced || !u_clk_main_otbn_trans.idle_valid), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_otbn == prim_mubi_pkg::MuBi4True) + ); + + // Calibration assertions. + bind clkmgr clkmgr_lost_calib_regwen_sva_if clkmgr_lost_calib_regwen_sva_if ( + .clk(clk_i), + .rst_n(rst_ni), + .calib_rdy(calib_rdy_i), + .meas_ctrl_regwen(u_reg.measure_ctrl_regwen_qs) + ); + + bind clkmgr clkmgr_lost_calib_ctrl_en_sva_if clkmgr_lost_calib_io_ctrl_en_sva_if ( + .clk(clk_i), + .rst_n(rst_ni), + .calib_rdy(calib_rdy_i), + .meas_ctrl_en(u_reg.io_meas_ctrl_en_qs) + ); + + bind clkmgr clkmgr_lost_calib_ctrl_en_sva_if clkmgr_lost_calib_main_ctrl_en_sva_if ( + .clk(clk_i), + .rst_n(rst_ni), + .calib_rdy(calib_rdy_i), + .meas_ctrl_en(u_reg.main_meas_ctrl_en_qs) + ); + + bind clkmgr clkmgr_lost_calib_ctrl_en_sva_if clkmgr_lost_calib_usb_ctrl_en_sva_if ( + .clk(clk_i), + .rst_n(rst_ni), + .calib_rdy(calib_rdy_i), + .meas_ctrl_en(u_reg.usb_meas_ctrl_en_qs) + ); + + bind clkmgr clkmgr_lost_calib_ctrl_en_sva_if clkmgr_lost_calib_io_div2_ctrl_en_sva_if ( + .clk(clk_i), + .rst_n(rst_ni), + .calib_rdy(calib_rdy_i), + .meas_ctrl_en(u_reg.io_div2_meas_ctrl_en_qs) + ); + + bind clkmgr clkmgr_lost_calib_ctrl_en_sva_if clkmgr_lost_calib_io_div4_ctrl_en_sva_if ( + .clk(clk_i), + .rst_n(rst_ni), + .calib_rdy(calib_rdy_i), + .meas_ctrl_en(u_reg.io_div4_meas_ctrl_en_qs) + ); + + bind clkmgr clkmgr_sec_cm_checker_assert clkmgr_sec_cm_checker_assert ( + .clk_i, + .rst_ni, + .all_clk_byp_req_o, + .lc_hw_debug_en_i, + .lc_clk_byp_req_i, + .lc_clk_byp_ack_o, + .io_clk_byp_req_o, + // internal signal is picked due to inconsistent t->f, f->t delay + .io_clk_byp_ack(u_clkmgr_byp.io_clk_byp_ack), + // internal signal is picked due to inconsistent input to signal delay + .step_down_acks_sync(u_clkmgr_byp.step_down_acks_sync), + .extclk_ctrl_sel + ); +`endif +endmodule : clkmgr_bind diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_cg_en_sva_if.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_cg_en_sva_if.sv new file mode 100644 index 0000000000000..e995057c8e908 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_cg_en_sva_if.sv @@ -0,0 +1,30 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions for clock gating output to alert_handler. +// - cg_en corresponds to clock gating enabled, which means the clock is gated, +// thus inactive. +// - ip_clk_en and sw_clk_en have the opposite polarity: when they are active +// the clock is enabled. +interface clkmgr_cg_en_sva_if + import prim_mubi_pkg::*; +( + input logic clk, + input logic rst_n, + input logic ip_clk_en, + input logic sw_clk_en, + input prim_mubi_pkg::mubi4_t scanmode, + input logic cg_en +); + + bit disable_sva; + + logic clk_enable; + always_comb clk_enable = ip_clk_en && sw_clk_en; + + `ASSERT(CgEnOn_A, $fell(clk_enable) |=> ##[0:2] clk_enable || cg_en, clk, + !rst_n || scanmode == prim_mubi_pkg::MuBi4True || disable_sva) + `ASSERT(CgEnOff_A, $rose(clk_enable) |=> ##[0:2] !clk_enable || !cg_en, clk, + !rst_n || scanmode == prim_mubi_pkg::MuBi4True || disable_sva) +endinterface diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_div_sva_if.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_div_sva_if.sv new file mode 100644 index 0000000000000..acf0408800403 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_div_sva_if.sv @@ -0,0 +1,68 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions for clock dividers. +// - For div2 (DIV == 2) the reference clk is io clock, which is never stepped. +// So when step_down check that the divided clock tracks the reference. This +// means we check at negedge, or we would see nothing interesting. +// - For div4 (DIV == 4) the reference clk is io_div2 clock, which is also stepped. +// So check it is always twice as slow, except during transitions. +// +// All checks at negedges for simplicity. +interface clkmgr_div_sva_if #( + parameter int DIV = 2 +) ( + input logic clk, + input logic rst_n, + input logic maybe_divided_clk, + input logic div_step_down_req_i, + input logic scanmode +); + + localparam int WAIT_CYCLES = 20; + logic step_down; + always_comb step_down = div_step_down_req_i && !scanmode; + + logic step_up; + always_comb step_up = !step_down; + + sequence WholeLeadHigh_S; + step_down || maybe_divided_clk ##1 step_down || !maybe_divided_clk; + endsequence + + sequence WholeLeadLow_S; + step_down || !maybe_divided_clk ##1 step_down || maybe_divided_clk; + endsequence + + if (DIV == 2) begin : g_div2 + + sequence TracksClk_S; step_up || maybe_divided_clk ##1 step_up || maybe_divided_clk; endsequence + + // Notice this fires at negedges, since maybe_divided_clk's value will be on when + // tracking. + `ASSERT(Div2Stepped_A, $rose(step_down) ##1 step_down [* WAIT_CYCLES] |-> TracksClk_S, !clk, + !rst_n) + `ASSERT(Div2Whole_A, + $fell(step_down) ##1 !step_down [* WAIT_CYCLES] |-> WholeLeadLow_S or WholeLeadHigh_S, + !clk, !rst_n) + + end else begin : g_div4 + + sequence StepLeadHigh_S; + step_up || maybe_divided_clk ##1 step_up || !maybe_divided_clk; + endsequence + + sequence StepLeadLow_S; + step_up || !maybe_divided_clk ##1 step_up || maybe_divided_clk; + endsequence + + `ASSERT(Div4Stepped_A, + $rose(step_down) ##1 step_down [* WAIT_CYCLES] |-> StepLeadLow_S or StepLeadHigh_S, + !clk, !rst_n) + `ASSERT(Div4Whole_A, + $fell(step_down) ##1 !step_down [* WAIT_CYCLES] |-> WholeLeadLow_S or WholeLeadHigh_S, + !clk, !rst_n) + + end +endinterface diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_extclk_sva_if.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_extclk_sva_if.sv new file mode 100644 index 0000000000000..ab505f527c6a6 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_extclk_sva_if.sv @@ -0,0 +1,81 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions to check the external clock bypass control outputs. +// +// Notice when a condition fails we allow the logic to generate non strict mubi values. Ideally it +// would generate mubi False: see https://github.com/lowRISC/opentitan/issues/11400. +interface clkmgr_extclk_sva_if + import prim_mubi_pkg::*, lc_ctrl_pkg::*; +( + input logic clk_i, + input logic rst_ni, + input mubi4_t extclk_ctrl_sel, + input mubi4_t extclk_ctrl_hi_speed_sel, + input lc_tx_t lc_hw_debug_en_i, + input lc_tx_t lc_clk_byp_req_i, + input mubi4_t io_clk_byp_req_o, + input mubi4_t all_clk_byp_req_o, + input mubi4_t hi_speed_sel_o +); + + // The times are to cover the clock domain synchronizers. + localparam int FallCyclesMin = 1; + localparam int FallCyclesMax = 3; + + localparam int RiseCyclesMin = 1; + localparam int RiseCyclesMax = 3; + + bit disable_sva; + + // Check lc_clk_byp_req_i triggers io_clk_byp_req_o. + logic lc_clk_byp_req; + always_comb lc_clk_byp_req = lc_clk_byp_req_i == On; + + `ASSERT(IoClkBypReqRise_A, + $rose( + lc_clk_byp_req + ) |=> ##[RiseCyclesMin:RiseCyclesMax] !lc_clk_byp_req || (io_clk_byp_req_o == MuBi4True), + clk_i, !rst_ni || disable_sva) + `ASSERT(IoClkBypReqFall_A, + $fell( + lc_clk_byp_req + ) |=> ##[FallCyclesMin:FallCyclesMax] lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False), + clk_i, !rst_ni || disable_sva) + + // Check extclk_ctrl triggers all_clk_byp_req_o and hi_speed_sel_o. + logic extclk_sel_enabled; + always_comb extclk_sel_enabled = extclk_ctrl_sel == MuBi4True && lc_hw_debug_en_i == On; + + `ASSERT(AllClkBypReqRise_A, + $rose( + extclk_sel_enabled + ) |=> ##[RiseCyclesMin:RiseCyclesMax] + !extclk_sel_enabled || (all_clk_byp_req_o == MuBi4True), + clk_i, !rst_ni || disable_sva) + `ASSERT(AllClkBypReqFall_A, + $fell( + extclk_sel_enabled + ) |=> ##[FallCyclesMin:FallCyclesMax] + extclk_sel_enabled || (all_clk_byp_req_o != MuBi4True), + clk_i, !rst_ni || disable_sva) + + logic hi_speed_enabled; + always_comb begin + hi_speed_enabled = extclk_ctrl_sel == MuBi4True && extclk_ctrl_hi_speed_sel == MuBi4True && + lc_hw_debug_en_i == On; + end + + `ASSERT(HiSpeedSelRise_A, + $rose( + hi_speed_enabled + ) |=> ##[RiseCyclesMin:RiseCyclesMax] !hi_speed_enabled || (hi_speed_sel_o == MuBi4True), + clk_i, !rst_ni || disable_sva) + `ASSERT(HiSpeedSelFall_A, + $fell( + hi_speed_enabled + ) |=> ##[FallCyclesMin:FallCyclesMax] hi_speed_enabled || (hi_speed_sel_o != MuBi4True), + clk_i, !rst_ni || disable_sva) + +endinterface diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_gated_clock_sva_if.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_gated_clock_sva_if.sv new file mode 100644 index 0000000000000..2d532f8613088 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_gated_clock_sva_if.sv @@ -0,0 +1,26 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions for gated clocks. +interface clkmgr_gated_clock_sva_if ( + input logic clk, + input logic rst_n, + input logic ip_clk_en, + input logic sw_clk_en, + input logic scanmode, + input logic gated_clk +); + // This fires at negedges: if the gated clock is inactive its value is expected to be low, + // and viceversa. The assertions pass if clk_enabled is not stable to avoid cycle accuracy, and + // these gated clocks are expected to be changed infrequently. + logic clk_enabled; + always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode; + + `ASSERT(GateOpen_A, + $rose(clk_enabled) |=> ##[0:3] !clk_enabled || $changed(clk_enabled) || gated_clk, !clk, + !rst_n) + `ASSERT(GateClose_A, + $fell(clk_enabled) |=> ##[0:3] clk_enabled || $changed(clk_enabled) || !gated_clk, !clk, + !rst_n) +endinterface diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_lost_calib_ctrl_en_sva_if.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_lost_calib_ctrl_en_sva_if.sv new file mode 100644 index 0000000000000..4b67cd01e628a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_lost_calib_ctrl_en_sva_if.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions to check losing calibration turns off clock measurements. + +interface clkmgr_lost_calib_ctrl_en_sva_if ( + input logic clk, + input logic rst_n, + input logic [$bits(prim_mubi_pkg::mubi4_t)-1:0] calib_rdy, + input logic [$bits(prim_mubi_pkg::mubi4_t)-1:0] meas_ctrl_en +); + // There are two clocks involved, the clock measured and the clkmgr clk_i. + // The latter is io_div4 so it is pretty slow compared to all others. There + // are a number of clock domain crossings, so this needs a large number of + // wait cycles to account for the worst case. + localparam int MAX_CYCLES = 45; + `ASSERT(CtrlEnOn_A, + (calib_rdy == prim_mubi_pkg::MuBi4False && meas_ctrl_en != prim_mubi_pkg::MuBi4False) |=> + ##[0:MAX_CYCLES] (meas_ctrl_en == prim_mubi_pkg::MuBi4False), + clk, !rst_n) +endinterface diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_lost_calib_regwen_sva_if.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_lost_calib_regwen_sva_if.sv new file mode 100644 index 0000000000000..47bbf710f60f2 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_lost_calib_regwen_sva_if.sv @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions to check losing calibration enables crtl regwen. + +interface clkmgr_lost_calib_regwen_sva_if ( + input logic clk, + input logic rst_n, + input prim_mubi_pkg::mubi4_t calib_rdy, + input logic meas_ctrl_regwen +); + localparam int MAX_CYCLES = 6; + `ASSERT(RegwenOff_A, + (calib_rdy == prim_mubi_pkg::MuBi4False) |=> ##[0:MAX_CYCLES] meas_ctrl_regwen, clk, + !rst_n) +endinterface diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_pwrmgr_sva_if.core b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_pwrmgr_sva_if.core new file mode 100644 index 0000000000000..186a2f8eb68fa --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_pwrmgr_sva_if.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:clkmgr_pwrmgr_sva_if:0.1" +description: "CLKMGR to PWRMGR assertion interface." +filesets: + files_dv: + depend: + - lowrisc:prim:assert + - lowrisc:prim:mubi + files: + - clkmgr_pwrmgr_sva_if.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_pwrmgr_sva_if.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_pwrmgr_sva_if.sv new file mode 100644 index 0000000000000..272d5af2ce502 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_pwrmgr_sva_if.sv @@ -0,0 +1,40 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions to check that rising or falling edges of a clock's ip_clk_en +// is followed by corresponding edges of its clk_status. +interface clkmgr_pwrmgr_sva_if #( + parameter int IS_USB = 0 +) ( + input logic clk_i, + input logic rst_ni, + input logic clk_en, + input logic status +); + + // The max times are longer to cover the different clock domain synchronizers. + // Ideally they would use the io_div4 clock, but it gets turned off when io_ip_clk_en + // goes inactive. + localparam int FallCyclesMin = 0; + localparam int FallCyclesMax = 20; + + // Assuming io_div4 : 24MHz, AON : 200KHz + localparam int AonCycleInClki = 120; + + // Since io_div4 and Aon is not aligned, max cycle delay + // can be 2 + 1 cycles fo AON clk. + localparam int UsbRiseCyclesMax = 3 * AonCycleInClki; + + localparam int RiseCyclesMin = 0; + localparam int RiseCyclesMax = IS_USB ? UsbRiseCyclesMax : 20; + + bit disable_sva; + + `ASSERT(StatusFall_A, + $fell(clk_en) |-> ##[FallCyclesMin:FallCyclesMax] clk_en || !status, clk_i, + !rst_ni || disable_sva) + `ASSERT(StatusRise_A, + $rose(clk_en) |-> ##[RiseCyclesMin:RiseCyclesMax] !clk_en || status, clk_i, + !rst_ni || disable_sva) +endinterface diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_sec_cm_checker_assert.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_sec_cm_checker_assert.sv new file mode 100644 index 0000000000000..567e26076a850 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_sec_cm_checker_assert.sv @@ -0,0 +1,59 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Assertion checker for external clock bypass +// sec cm test +module clkmgr_sec_cm_checker_assert ( + input clk_i, + input rst_ni, + input prim_mubi_pkg::mubi4_t all_clk_byp_req_o, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + input lc_ctrl_pkg::lc_tx_t lc_clk_byp_req_i, + input lc_ctrl_pkg::lc_tx_t lc_clk_byp_ack_o, + input prim_mubi_pkg::mubi4_t io_clk_byp_req_o, + input prim_mubi_pkg::mubi4_t io_clk_byp_ack, + input logic [1:0] step_down_acks_sync, + input prim_mubi_pkg::mubi4_t extclk_ctrl_sel +); + + bit disable_sva; + bit reset_or_disable; + + always_comb reset_or_disable = !rst_ni || disable_sva; + + // sec_cm_lc_ctrl_intersig_mubi + `ASSERT(AllClkBypReqTrue_A, + lc_hw_debug_en_i == lc_ctrl_pkg::On && extclk_ctrl_sel == prim_mubi_pkg::MuBi4True |=> + all_clk_byp_req_o == prim_mubi_pkg::MuBi4True, + clk_i, reset_or_disable) + `ASSERT(AllClkBypReqFalse_A, + lc_hw_debug_en_i != lc_ctrl_pkg::On || extclk_ctrl_sel != prim_mubi_pkg::MuBi4True |=> + all_clk_byp_req_o != prim_mubi_pkg::MuBi4True, + clk_i, reset_or_disable) + + // sec_cm_lc_ctrl_clk_handshake_intersig_mubi + `ASSERT(IoClkBypReqTrue_A, + lc_clk_byp_req_i == lc_ctrl_pkg::On |=> ##[2:3] + io_clk_byp_req_o == prim_mubi_pkg::MuBi4True, clk_i, reset_or_disable) + `ASSERT(IoClkBypReqFalse_A, + lc_clk_byp_req_i != lc_ctrl_pkg::On |=> ##[2:3] + io_clk_byp_req_o == prim_mubi_pkg::MuBi4False, clk_i, reset_or_disable) + + // sec_cm_clk_handshake_intersig_mubi, sec_cm_div_intersig_mubi + `ASSERT(LcClkBypAckTrue_A, + step_down_acks_sync == 2'b11 && io_clk_byp_ack == prim_mubi_pkg::MuBi4True |=> ($past( + lc_clk_byp_req_i, 3 + ) == lc_clk_byp_ack_o) || ($past( + lc_clk_byp_req_i, 4 + ) != $past( + lc_clk_byp_req_i, 3 + )), + clk_i, reset_or_disable) + `ASSERT(LcClkBypAckFalse_A, + step_down_acks_sync != 2'b11 || + io_clk_byp_ack != prim_mubi_pkg::MuBi4True |=> + lc_clk_byp_ack_o == lc_ctrl_pkg::Off, + clk_i, reset_or_disable) + +endmodule : clkmgr_sec_cm_checker_assert diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_sva.core b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_sva.core new file mode 100644 index 0000000000000..84ff5d113761b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_sva.core @@ -0,0 +1,40 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:clkmgr_sva:0.1" +description: "CLKMGR assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + - lowrisc:dv:clkmgr_sva_ifs + files: + - clkmgr_bind.sv + - clkmgr_sec_cm_checker_assert.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:ip_interfaces:clkmgr + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/clkmgr.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: clkmgr diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_sva_ifs.core b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_sva_ifs.core new file mode 100644 index 0000000000000..c1248a4f83e9a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_sva_ifs.core @@ -0,0 +1,28 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:clkmgr_sva_ifs:0.1" +description: "CLKMGR SVA interfaces." +filesets: + files_dv: + depend: + - lowrisc:prim:assert + - lowrisc:prim:mubi + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:dv:clkmgr_pwrmgr_sva_if + files: + - clkmgr_aon_cg_en_sva_if.sv + - clkmgr_cg_en_sva_if.sv + - clkmgr_div_sva_if.sv + - clkmgr_extclk_sva_if.sv + - clkmgr_gated_clock_sva_if.sv + - clkmgr_lost_calib_ctrl_en_sva_if.sv + - clkmgr_lost_calib_regwen_sva_if.sv + - clkmgr_trans_sva_if.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_trans_sva_if.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_trans_sva_if.sv new file mode 100644 index 0000000000000..692e049aac4f6 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/sva/clkmgr_trans_sva_if.sv @@ -0,0 +1,35 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions for trans clocks. +interface clkmgr_trans_sva_if ( + input logic clk, + input logic rst_n, + input logic hint, + input logic idle, + input logic scanmode, + input logic status, + input logic trans_clk +); + // This fires at negedges: if the trans clock is inactive its value is expected to be low, and + // viceversa. The clock takes some cycles to react to idle and hint. + localparam int MIN_START_CYCLES = 0; + localparam int MAX_START_CYCLES = 3; + + localparam int MIN_STOP_CYCLES = 2; + localparam int MAX_STOP_CYCLES = 15; + + `ASSERT(TransStart_A, + $rose( + hint + ) ##1 hint [* MIN_START_CYCLES] |=> + ##[0:MAX_START_CYCLES-MIN_START_CYCLES] !hint || trans_clk, + !clk, !rst_n) + `ASSERT(TransStop_A, + $fell( + hint || !idle || scanmode + ) ##1 !hint && !scanmode [* MIN_STOP_CYCLES] |=> + ##[0:MAX_STOP_CYCLES-MIN_STOP_CYCLES] hint || scanmode || !trans_clk, + !clk, !rst_n) +endinterface diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/tb.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/tb.sv new file mode 100644 index 0000000000000..b7fbf60bf322a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/tb.sv @@ -0,0 +1,211 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import clkmgr_env_pkg::*; + import clkmgr_test_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk, rst_n, rst_shadowed_n; + wire clk_main, rst_main_n; + wire clk_io, rst_io_n; + wire clk_usb, rst_usb_n; + wire clk_aon, rst_aon_n; + + // clock interfaces + clk_rst_if clk_rst_if ( + .clk (clk), + .rst_n(rst_n) + ); + clk_rst_if main_clk_rst_if ( + .clk (clk_main), + .rst_n(rst_main_n) + ); + clk_rst_if io_clk_rst_if ( + .clk (clk_io), + .rst_n(rst_io_n) + ); + clk_rst_if usb_clk_rst_if ( + .clk (clk_usb), + .rst_n(rst_usb_n) + ); + clk_rst_if aon_clk_rst_if ( + .clk (clk_aon), + .rst_n(rst_aon_n) + ); + clk_rst_if root_io_clk_rst_if ( + .clk (), + .rst_n(rst_root_io_n) + ); + clk_rst_if root_main_clk_rst_if ( + .clk (), + .rst_n(rst_root_main_n) + ); + clk_rst_if root_usb_clk_rst_if ( + .clk (), + .rst_n(rst_root_usb_n) + ); + + tl_if tl_if ( + .clk (clk), + .rst_n(rst_n) + ); + + // The clkmgr interface. + clkmgr_if clkmgr_if ( + .clk(clk), + .rst_n(rst_n), + .clk_main(clk_main), + .rst_io_n(rst_io_n), + .rst_main_n(rst_main_n), + .rst_usb_n(rst_usb_n) + ); + + bind clkmgr clkmgr_csrs_if clkmgr_csrs_if ( + .clk(clk_i), + .recov_err_csr({ + u_reg.u_recov_err_code_usb_timeout_err.qs, + u_reg.u_recov_err_code_main_timeout_err.qs, + u_reg.u_recov_err_code_io_div4_timeout_err.qs, + u_reg.u_recov_err_code_io_div2_timeout_err.qs, + u_reg.u_recov_err_code_io_timeout_err.qs, + u_reg.u_recov_err_code_usb_measure_err.qs, + u_reg.u_recov_err_code_main_measure_err.qs, + u_reg.u_recov_err_code_io_div4_measure_err.qs, + u_reg.u_recov_err_code_io_div2_measure_err.qs, + u_reg.u_recov_err_code_io_measure_err.qs, + u_reg.u_recov_err_code_shadow_update_err.qs + }), + .fatal_err_csr({ + u_reg.u_fatal_err_code_shadow_storage_err.qs, + u_reg.u_fatal_err_code_idle_cnt.qs, + u_reg.u_fatal_err_code_reg_intg.qs + }), + .clk_enables({ + reg2hw.clk_enables.clk_usb_peri_en.q, + reg2hw.clk_enables.clk_io_peri_en.q, + reg2hw.clk_enables.clk_io_div2_peri_en.q, + reg2hw.clk_enables.clk_io_div4_peri_en.q}), + .clk_hints({ + reg2hw.clk_hints.clk_main_otbn_hint.q, + reg2hw.clk_hints.clk_main_kmac_hint.q, + reg2hw.clk_hints.clk_main_hmac_hint.q, + reg2hw.clk_hints.clk_main_aes_hint.q}) + ); + + rst_shadowed_if rst_shadowed_if ( + .rst_n(rst_n), + .rst_shadowed_n(rst_shadowed_n) + ); + + initial begin + // Clocks must be set to active at time 0. The rest of the clock configuration happens + // in clkmgr_base_vseq.sv. + clk_rst_if.set_active(); + main_clk_rst_if.set_active(); + io_clk_rst_if.set_active(); + usb_clk_rst_if.set_active(); + aon_clk_rst_if.set_active(); + + root_io_clk_rst_if.set_active(); + root_main_clk_rst_if.set_active(); + root_usb_clk_rst_if.set_active(); + end + + `DV_ALERT_IF_CONNECT() + + // dut + clkmgr dut ( + .clk_i(clk), + .rst_ni(rst_n), + .rst_shadowed_ni(rst_shadowed_n), + + .clk_main_i (clk_main), + .rst_main_ni(rst_main_n), + .clk_io_i (clk_io), + // ICEBOX(#17934): differentiate the io resets to check they generate the + // expected side-effects. Probably doable with a very simple test. + .rst_io_ni (rst_io_n), + .rst_io_div2_ni(rst_io_n), + .rst_io_div4_ni(rst_io_n), + .clk_usb_i (clk_usb), + .rst_usb_ni (rst_usb_n), + .clk_aon_i (clk_aon), + .rst_aon_ni (rst_aon_n), + + // ICEBOX(#17934): differentiate the root resets as mentioned for rst_io_ni above. + .rst_root_ni(rst_root_io_n), + .rst_root_io_ni(rst_root_io_n), + .rst_root_io_div2_ni(rst_root_io_n), + .rst_root_io_div4_ni(rst_root_io_n), + .rst_root_main_ni(rst_root_main_n), + .rst_root_usb_ni(rst_root_usb_n), + + .tl_i(tl_if.h2d), + .tl_o(tl_if.d2h), + + .alert_rx_i(alert_rx), + .alert_tx_o(alert_tx), + + .pwr_i(clkmgr_if.pwr_i), + .pwr_o(clkmgr_if.pwr_o), + + .scanmode_i(clkmgr_if.scanmode_i), + .idle_i (clkmgr_if.idle_i), + + .lc_hw_debug_en_i(clkmgr_if.lc_hw_debug_en_i), + .all_clk_byp_req_o(clkmgr_if.all_clk_byp_req), + .all_clk_byp_ack_i(clkmgr_if.all_clk_byp_ack), + .io_clk_byp_req_o(clkmgr_if.io_clk_byp_req), + .io_clk_byp_ack_i(clkmgr_if.io_clk_byp_ack), + .lc_clk_byp_req_i(clkmgr_if.lc_clk_byp_req), + .lc_clk_byp_ack_o(clkmgr_if.lc_clk_byp_ack), + .div_step_down_req_i(clkmgr_if.div_step_down_req), + + .cg_en_o(), + + .jitter_en_o(clkmgr_if.jitter_en_o), + .clocks_o (clkmgr_if.clocks_o), + + .calib_rdy_i(clkmgr_if.calib_rdy), + .hi_speed_sel_o(clkmgr_if.hi_speed_sel) + ); + + initial begin + // Register interfaces with uvm. + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "main_clk_rst_vif", main_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "io_clk_rst_vif", io_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "usb_clk_rst_vif", usb_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "aon_clk_rst_vif", aon_clk_rst_if); + + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "root_io_clk_rst_vif", + root_io_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "root_main_clk_rst_vif", + root_main_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "root_usb_clk_rst_vif", + root_usb_clk_rst_if); + + uvm_config_db#(virtual clkmgr_if)::set(null, "*.env", "clkmgr_vif", clkmgr_if); + + uvm_config_db#(virtual clkmgr_csrs_if)::set(null, "*.env", "clkmgr_csrs_vif", + dut.clkmgr_csrs_if); + + // FIXME Un-comment this once interrupts are created for this ip. + // uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); + uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", + rst_shadowed_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/tests/clkmgr_base_test.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/tests/clkmgr_base_test.sv new file mode 100644 index 0000000000000..a0ddd45839bd1 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/tests/clkmgr_base_test.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class clkmgr_base_test extends cip_base_test #( + .CFG_T(clkmgr_env_cfg), + .ENV_T(clkmgr_env) +); + + `uvm_component_utils(clkmgr_base_test) + `uvm_component_new + + // the base class dv_base_test creates the following instances: + // clkmgr_env_cfg: cfg + // clkmgr_env: env + + // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in + // the run_phase; as such, nothing more needs to be done + +endclass : clkmgr_base_test diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/tests/clkmgr_test.core b/hw/top_darjeeling/ip_autogen/clkmgr/dv/tests/clkmgr_test.core new file mode 100644 index 0000000000000..e1a34e5553226 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/tests/clkmgr_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:clkmgr_test:0.1" +description: "CLKMGR DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:dv:clkmgr_env + files: + - clkmgr_test_pkg.sv + - clkmgr_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/dv/tests/clkmgr_test_pkg.sv b/hw/top_darjeeling/ip_autogen/clkmgr/dv/tests/clkmgr_test_pkg.sv new file mode 100644 index 0000000000000..0d1e07762f22f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/dv/tests/clkmgr_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package clkmgr_test_pkg; + // dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import clkmgr_env_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // local types + + // functions + + // package sources + `include "clkmgr_base_test.sv" + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/lint/clkmgr.vlt b/hw/top_darjeeling/ip_autogen/clkmgr/lint/clkmgr.vlt new file mode 100644 index 0000000000000..f71656fb1304b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/lint/clkmgr.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for clkmgr diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/lint/clkmgr.waiver b/hw/top_darjeeling/ip_autogen/clkmgr/lint/clkmgr.waiver new file mode 100644 index 0000000000000..49663c1a7f696 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/lint/clkmgr.waiver @@ -0,0 +1,21 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for clkmgr + +# +# fake errors + +waive -rules INPUT_NOT_READ -location {prim_clock_gating.sv} -regexp {.*} \ + -comment "Generated abstraction files use .*'s which create fake errors" + +waive -rules EMPTY_PARAM_LIST -location {prim_clock_gating.sv} -regexp {.*} \ + -comment "Generated abstraction files may have empty params" + +waive -rules OUTPUT_NOT_DRIVEN -location {prim_clock_gating.sv} -regexp {.*} \ + -comment "Generated abstraction files do not detect drivers" + +# clock mux errors +waive -rules CLOCK_MUX -location {clkmgr.sv} -regexp {.*clk_io_div.* is driven by a multiplexer here} \ + -comment "All divided clocks terminate with a scan mux" diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr.sv new file mode 100644 index 0000000000000..bccaa7a34dc35 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr.sv @@ -0,0 +1,973 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// The overall clock manager + + +`include "prim_assert.sv" + + module clkmgr + import clkmgr_pkg::*; + import clkmgr_reg_pkg::*; + import lc_ctrl_pkg::lc_tx_t; + import prim_mubi_pkg::mubi4_t; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}} +) ( + // Primary module control clocks and resets + // This drives the register interface + input clk_i, + input rst_ni, + input rst_shadowed_ni, + + // System clocks and resets + // These are the source clocks for the system + input clk_main_i, + input rst_main_ni, + input clk_io_i, + input rst_io_ni, + input clk_usb_i, + input rst_usb_ni, + input clk_aon_i, + input rst_aon_ni, + + // Resets for derived clocks + // clocks are derived locally + input rst_io_div2_ni, + input rst_io_div4_ni, + + // Resets for derived clock generation, root clock gating and related status + input rst_root_ni, + input rst_root_main_ni, + input rst_root_io_ni, + input rst_root_io_div2_ni, + input rst_root_io_div4_ni, + input rst_root_usb_ni, + + // Bus Interface + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + // pwrmgr interface + input pwrmgr_pkg::pwr_clk_req_t pwr_i, + output pwrmgr_pkg::pwr_clk_rsp_t pwr_o, + + // dft interface + input prim_mubi_pkg::mubi4_t scanmode_i, + + // idle hints + // SEC_CM: IDLE.INTERSIG.MUBI + input prim_mubi_pkg::mubi4_t [3:0] idle_i, + + // life cycle state output + // SEC_CM: LC_CTRL.INTERSIG.MUBI + input lc_tx_t lc_hw_debug_en_i, + + // clock bypass control with lc_ctrl + // SEC_CM: LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI + input lc_tx_t lc_clk_byp_req_i, + output lc_tx_t lc_clk_byp_ack_o, + + // clock bypass control with ast + // SEC_CM: CLK_HANDSHAKE.INTERSIG.MUBI + output mubi4_t io_clk_byp_req_o, + input mubi4_t io_clk_byp_ack_i, + output mubi4_t all_clk_byp_req_o, + input mubi4_t all_clk_byp_ack_i, + output mubi4_t hi_speed_sel_o, + + // clock calibration has been done. + // If this is signal is 0, assume clock frequencies to be + // uncalibrated. + input prim_mubi_pkg::mubi4_t calib_rdy_i, + + // jittery enable to ast + output mubi4_t jitter_en_o, + + // external indication for whether dividers should be stepped down + // SEC_CM: DIV.INTERSIG.MUBI + input mubi4_t div_step_down_req_i, + + // clock gated indications going to alert handlers + output clkmgr_cg_en_t cg_en_o, + + // clock output interface + output clkmgr_out_t clocks_o + +); + + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4True; + import prim_mubi_pkg::mubi4_test_true_strict; + import prim_mubi_pkg::mubi4_test_true_loose; + import prim_mubi_pkg::mubi4_test_false_strict; + + // Hookup point for OCC's on root clocks. + logic clk_main; + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_clk_main_buf ( + .clk_i(clk_main_i), + .clk_o(clk_main) + ); + logic clk_io; + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_clk_io_buf ( + .clk_i(clk_io_i), + .clk_o(clk_io) + ); + logic clk_usb; + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_clk_usb_buf ( + .clk_i(clk_usb_i), + .clk_o(clk_usb) + ); + logic clk_aon; + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_clk_aon_buf ( + .clk_i(clk_aon_i), + .clk_o(clk_aon) + ); + + //////////////////////////////////////////////////// + // External step down request + //////////////////////////////////////////////////// + mubi4_t io_step_down_req; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(1), + .StabilityCheck(1), + .ResetValue(MuBi4False) + ) u_io_step_down_req_sync ( + .clk_i(clk_io), + .rst_ni(rst_io_ni), + .mubi_i(div_step_down_req_i), + .mubi_o({io_step_down_req}) + ); + + + //////////////////////////////////////////////////// + // Divided clocks + // Note divided clocks must use the por version of + // its related reset to ensure clock division + // can happen without any dependency + //////////////////////////////////////////////////// + + logic [1:0] step_down_acks; + + logic clk_io_div2; + logic clk_io_div4; + + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] io_div2_div_scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_io_div2_div_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o({io_div2_div_scanmode}) + ); + + prim_clock_div #( + .Divisor(2) + ) u_no_scan_io_div2_div ( + // We're using the pre-occ hookup (*_i) version for clock derivation. + .clk_i(clk_io_i), + .rst_ni(rst_root_io_ni), + .step_down_req_i(mubi4_test_true_strict(io_step_down_req)), + .step_down_ack_o(step_down_acks[0]), + .test_en_i(mubi4_test_true_strict(io_div2_div_scanmode[0])), + .clk_o(clk_io_div2) + ); + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] io_div4_div_scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_io_div4_div_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o({io_div4_div_scanmode}) + ); + + prim_clock_div #( + .Divisor(4) + ) u_no_scan_io_div4_div ( + // We're using the pre-occ hookup (*_i) version for clock derivation. + .clk_i(clk_io_i), + .rst_ni(rst_root_io_ni), + .step_down_req_i(mubi4_test_true_strict(io_step_down_req)), + .step_down_ack_o(step_down_acks[1]), + .test_en_i(mubi4_test_true_strict(io_div4_div_scanmode[0])), + .clk_o(clk_io_div4) + ); + + //////////////////////////////////////////////////// + // Register Interface + //////////////////////////////////////////////////// + + logic [NumAlerts-1:0] alert_test, alerts; + clkmgr_reg_pkg::clkmgr_reg2hw_t reg2hw; + clkmgr_reg_pkg::clkmgr_hw2reg_t hw2reg; + + // SEC_CM: MEAS.CONFIG.REGWEN + // SEC_CM: MEAS.CONFIG.SHADOW + // SEC_CM: CLK_CTRL.CONFIG.REGWEN + clkmgr_reg_top u_reg ( + .clk_i, + .rst_ni, + .rst_shadowed_ni, + .clk_io_div4_i(clk_io_div4), + .rst_io_div4_ni, + .clk_main_i(clk_main), + .rst_main_ni, + .clk_usb_i(clk_usb), + .rst_usb_ni, + .tl_i, + .tl_o, + .reg2hw, + .hw2reg, + .shadowed_storage_err_o(hw2reg.fatal_err_code.shadow_storage_err.de), + .shadowed_update_err_o(hw2reg.recov_err_code.shadow_update_err.de), + // SEC_CM: BUS.INTEGRITY + .intg_err_o(hw2reg.fatal_err_code.reg_intg.de) + ); + assign hw2reg.fatal_err_code.reg_intg.d = 1'b1; + assign hw2reg.recov_err_code.shadow_update_err.d = 1'b1; + assign hw2reg.fatal_err_code.shadow_storage_err.d = 1'b1; + + //////////////////////////////////////////////////// + // Alerts + //////////////////////////////////////////////////// + + assign alert_test = { + reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe, + reg2hw.alert_test.recov_fault.q & reg2hw.alert_test.recov_fault.qe + }; + + logic recov_alert; + assign recov_alert = + hw2reg.recov_err_code.io_div4_measure_err.de | + hw2reg.recov_err_code.io_div4_timeout_err.de | + hw2reg.recov_err_code.main_measure_err.de | + hw2reg.recov_err_code.main_timeout_err.de | + hw2reg.recov_err_code.usb_measure_err.de | + hw2reg.recov_err_code.usb_timeout_err.de | + hw2reg.recov_err_code.shadow_update_err.de; + + assign alerts = { + |reg2hw.fatal_err_code, + recov_alert + }; + + localparam logic [NumAlerts-1:0] AlertFatal = {1'b1, 1'b0}; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .IsFatal(AlertFatal[i]) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[i] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + //////////////////////////////////////////////////// + // Clock bypass request + //////////////////////////////////////////////////// + + mubi4_t extclk_ctrl_sel; + mubi4_t extclk_ctrl_hi_speed_sel; + + assign extclk_ctrl_sel = mubi4_t'(reg2hw.extclk_ctrl.sel.q); + assign extclk_ctrl_hi_speed_sel = mubi4_t'(reg2hw.extclk_ctrl.hi_speed_sel.q); + + clkmgr_byp #( + .NumDivClks(2) + ) u_clkmgr_byp ( + .clk_i, + .rst_ni, + .en_i(lc_hw_debug_en_i), + .lc_clk_byp_req_i, + .lc_clk_byp_ack_o, + .byp_req_i(extclk_ctrl_sel), + .byp_ack_o(hw2reg.extclk_status.d), + .hi_speed_sel_i(extclk_ctrl_hi_speed_sel), + .all_clk_byp_req_o, + .all_clk_byp_ack_i, + .io_clk_byp_req_o, + .io_clk_byp_ack_i, + .hi_speed_sel_o, + + // divider step down controls + .step_down_acks_i(step_down_acks) + ); + + //////////////////////////////////////////////////// + // Feed through clocks + // Feed through clocks do not actually need to be in clkmgr, as they are + // completely untouched. The only reason they are here is for easier + // bundling management purposes through clocks_o + //////////////////////////////////////////////////// + prim_clock_buf u_clk_io_div4_powerup_buf ( + .clk_i(clk_io_div4), + .clk_o(clocks_o.clk_io_div4_powerup) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.io_div4_powerup = MuBi4False; + prim_clock_buf u_clk_aon_powerup_buf ( + .clk_i(clk_aon), + .clk_o(clocks_o.clk_aon_powerup) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.aon_powerup = MuBi4False; + prim_clock_buf u_clk_main_powerup_buf ( + .clk_i(clk_main), + .clk_o(clocks_o.clk_main_powerup) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.main_powerup = MuBi4False; + prim_clock_buf u_clk_io_powerup_buf ( + .clk_i(clk_io), + .clk_o(clocks_o.clk_io_powerup) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.io_powerup = MuBi4False; + prim_clock_buf u_clk_usb_powerup_buf ( + .clk_i(clk_usb), + .clk_o(clocks_o.clk_usb_powerup) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.usb_powerup = MuBi4False; + prim_clock_buf u_clk_io_div2_powerup_buf ( + .clk_i(clk_io_div2), + .clk_o(clocks_o.clk_io_div2_powerup) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.io_div2_powerup = MuBi4False; + prim_clock_buf u_clk_aon_infra_buf ( + .clk_i(clk_aon), + .clk_o(clocks_o.clk_aon_infra) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.aon_infra = MuBi4False; + prim_clock_buf u_clk_aon_secure_buf ( + .clk_i(clk_aon), + .clk_o(clocks_o.clk_aon_secure) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.aon_secure = MuBi4False; + prim_clock_buf u_clk_aon_peri_buf ( + .clk_i(clk_aon), + .clk_o(clocks_o.clk_aon_peri) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.aon_peri = MuBi4False; + prim_clock_buf u_clk_aon_timers_buf ( + .clk_i(clk_aon), + .clk_o(clocks_o.clk_aon_timers) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.aon_timers = MuBi4False; + + //////////////////////////////////////////////////// + // Distribute pwrmgr ip_clk_en requests to each family + //////////////////////////////////////////////////// + // clk_main family + logic pwrmgr_main_en; + assign pwrmgr_main_en = pwr_i.main_ip_clk_en; + // clk_io family + logic pwrmgr_io_en; + logic pwrmgr_io_div2_en; + logic pwrmgr_io_div4_en; + assign pwrmgr_io_en = pwr_i.io_ip_clk_en; + assign pwrmgr_io_div2_en = pwr_i.io_ip_clk_en; + assign pwrmgr_io_div4_en = pwr_i.io_ip_clk_en; + // clk_usb family + logic pwrmgr_usb_en; + assign pwrmgr_usb_en = pwr_i.usb_ip_clk_en; + + //////////////////////////////////////////////////// + // Root gating + //////////////////////////////////////////////////// + + // clk_main family + logic [0:0] main_ens; + + logic clk_main_en; + logic clk_main_root; + clkmgr_root_ctrl u_main_root_ctrl ( + .clk_i(clk_main), + .rst_ni(rst_root_main_ni), + .scanmode_i, + .async_en_i(pwrmgr_main_en), + .en_o(clk_main_en), + .clk_o(clk_main_root) + ); + assign main_ens[0] = clk_main_en; + + // create synchronized status + clkmgr_clk_status #( + .NumClocks(1) + ) u_main_status ( + .clk_i, + .rst_ni(rst_root_ni), + .ens_i(main_ens), + .status_o(pwr_o.main_status) + ); + + // clk_io family + logic [2:0] io_ens; + + logic clk_io_en; + logic clk_io_root; + clkmgr_root_ctrl u_io_root_ctrl ( + .clk_i(clk_io), + .rst_ni(rst_root_io_ni), + .scanmode_i, + .async_en_i(pwrmgr_io_en), + .en_o(clk_io_en), + .clk_o(clk_io_root) + ); + assign io_ens[0] = clk_io_en; + + logic clk_io_div2_en; + logic clk_io_div2_root; + clkmgr_root_ctrl u_io_div2_root_ctrl ( + .clk_i(clk_io_div2), + .rst_ni(rst_root_io_div2_ni), + .scanmode_i, + .async_en_i(pwrmgr_io_div2_en), + .en_o(clk_io_div2_en), + .clk_o(clk_io_div2_root) + ); + assign io_ens[1] = clk_io_div2_en; + + logic clk_io_div4_en; + logic clk_io_div4_root; + clkmgr_root_ctrl u_io_div4_root_ctrl ( + .clk_i(clk_io_div4), + .rst_ni(rst_root_io_div4_ni), + .scanmode_i, + .async_en_i(pwrmgr_io_div4_en), + .en_o(clk_io_div4_en), + .clk_o(clk_io_div4_root) + ); + assign io_ens[2] = clk_io_div4_en; + + // create synchronized status + clkmgr_clk_status #( + .NumClocks(3) + ) u_io_status ( + .clk_i, + .rst_ni(rst_root_ni), + .ens_i(io_ens), + .status_o(pwr_o.io_status) + ); + + // clk_usb family + logic [0:0] usb_ens; + + logic clk_usb_en; + logic clk_usb_root; + clkmgr_root_ctrl u_usb_root_ctrl ( + .clk_i(clk_usb), + .rst_ni(rst_root_usb_ni), + .scanmode_i, + .async_en_i(pwrmgr_usb_en), + .en_o(clk_usb_en), + .clk_o(clk_usb_root) + ); + assign usb_ens[0] = clk_usb_en; + + // create synchronized status + clkmgr_clk_status #( + .NumClocks(1) + ) u_usb_status ( + .clk_i, + .rst_ni(rst_root_ni), + .ens_i(usb_ens), + .status_o(pwr_o.usb_status) + ); + + //////////////////////////////////////////////////// + // Clock Measurement for the roots + // SEC_CM: TIMEOUT.CLK.BKGN_CHK, MEAS.CLK.BKGN_CHK + //////////////////////////////////////////////////// + + typedef enum logic [2:0] { + BaseIdx, + ClkIoDiv4Idx, + ClkMainIdx, + ClkUsbIdx, + CalibRdyLastIdx + } clkmgr_calib_idx_e; + + // if clocks become uncalibrated, allow the measurement control configurations to change + mubi4_t [CalibRdyLastIdx-1:0] calib_rdy; + prim_mubi4_sync #( + .AsyncOn(1), + .NumCopies(int'(CalibRdyLastIdx)), + .ResetValue(MuBi4False) + ) u_calib_rdy_sync ( + .clk_i, + .rst_ni, + .mubi_i(calib_rdy_i), + .mubi_o({calib_rdy}) + ); + + always_comb begin + hw2reg.measure_ctrl_regwen.de = '0; + hw2reg.measure_ctrl_regwen.d = reg2hw.measure_ctrl_regwen; + + if (mubi4_test_false_strict(calib_rdy[BaseIdx])) begin + hw2reg.measure_ctrl_regwen.de = 1'b1; + hw2reg.measure_ctrl_regwen.d = 1'b1; + end + end + + clkmgr_meas_chk #( + .Cnt(240), + .RefCnt(1) + ) u_io_div4_meas ( + .clk_i, + .rst_ni, + .clk_src_i(clk_io_div4), + .rst_src_ni(rst_io_div4_ni), + .clk_ref_i(clk_aon), + .rst_ref_ni(rst_aon_ni), + // signals on source domain + .src_en_i(clk_io_div4_en & mubi4_test_true_loose(mubi4_t'(reg2hw.io_div4_meas_ctrl_en))), + .src_max_cnt_i(reg2hw.io_div4_meas_ctrl_shadowed.hi.q), + .src_min_cnt_i(reg2hw.io_div4_meas_ctrl_shadowed.lo.q), + .src_cfg_meas_en_i(mubi4_t'(reg2hw.io_div4_meas_ctrl_en.q)), + .src_cfg_meas_en_valid_o(hw2reg.io_div4_meas_ctrl_en.de), + .src_cfg_meas_en_o(hw2reg.io_div4_meas_ctrl_en.d), + // signals on local clock domain + .calib_rdy_i(calib_rdy[ClkIoDiv4Idx]), + .meas_err_o(hw2reg.recov_err_code.io_div4_measure_err.de), + .timeout_err_o(hw2reg.recov_err_code.io_div4_timeout_err.de) + ); + + assign hw2reg.recov_err_code.io_div4_measure_err.d = 1'b1; + assign hw2reg.recov_err_code.io_div4_timeout_err.d = 1'b1; + + + clkmgr_meas_chk #( + .Cnt(1000), + .RefCnt(1) + ) u_main_meas ( + .clk_i, + .rst_ni, + .clk_src_i(clk_main), + .rst_src_ni(rst_main_ni), + .clk_ref_i(clk_aon), + .rst_ref_ni(rst_aon_ni), + // signals on source domain + .src_en_i(clk_main_en & mubi4_test_true_loose(mubi4_t'(reg2hw.main_meas_ctrl_en))), + .src_max_cnt_i(reg2hw.main_meas_ctrl_shadowed.hi.q), + .src_min_cnt_i(reg2hw.main_meas_ctrl_shadowed.lo.q), + .src_cfg_meas_en_i(mubi4_t'(reg2hw.main_meas_ctrl_en.q)), + .src_cfg_meas_en_valid_o(hw2reg.main_meas_ctrl_en.de), + .src_cfg_meas_en_o(hw2reg.main_meas_ctrl_en.d), + // signals on local clock domain + .calib_rdy_i(calib_rdy[ClkMainIdx]), + .meas_err_o(hw2reg.recov_err_code.main_measure_err.de), + .timeout_err_o(hw2reg.recov_err_code.main_timeout_err.de) + ); + + assign hw2reg.recov_err_code.main_measure_err.d = 1'b1; + assign hw2reg.recov_err_code.main_timeout_err.d = 1'b1; + + + clkmgr_meas_chk #( + .Cnt(480), + .RefCnt(1) + ) u_usb_meas ( + .clk_i, + .rst_ni, + .clk_src_i(clk_usb), + .rst_src_ni(rst_usb_ni), + .clk_ref_i(clk_aon), + .rst_ref_ni(rst_aon_ni), + // signals on source domain + .src_en_i(clk_usb_en & mubi4_test_true_loose(mubi4_t'(reg2hw.usb_meas_ctrl_en))), + .src_max_cnt_i(reg2hw.usb_meas_ctrl_shadowed.hi.q), + .src_min_cnt_i(reg2hw.usb_meas_ctrl_shadowed.lo.q), + .src_cfg_meas_en_i(mubi4_t'(reg2hw.usb_meas_ctrl_en.q)), + .src_cfg_meas_en_valid_o(hw2reg.usb_meas_ctrl_en.de), + .src_cfg_meas_en_o(hw2reg.usb_meas_ctrl_en.d), + // signals on local clock domain + .calib_rdy_i(calib_rdy[ClkUsbIdx]), + .meas_err_o(hw2reg.recov_err_code.usb_measure_err.de), + .timeout_err_o(hw2reg.recov_err_code.usb_timeout_err.de) + ); + + assign hw2reg.recov_err_code.usb_measure_err.d = 1'b1; + assign hw2reg.recov_err_code.usb_timeout_err.d = 1'b1; + + + //////////////////////////////////////////////////// + // Clocks with only root gate + //////////////////////////////////////////////////// + assign clocks_o.clk_io_div4_infra = clk_io_div4_root; + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_io_div4_infra ( + .clk_i(clk_io_div4), + .rst_ni(rst_io_div4_ni), + .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.io_div4_infra) + ); + assign clocks_o.clk_main_infra = clk_main_root; + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_main_infra ( + .clk_i(clk_main), + .rst_ni(rst_main_ni), + .mubi_i(((clk_main_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.main_infra) + ); + assign clocks_o.clk_usb_infra = clk_usb_root; + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_usb_infra ( + .clk_i(clk_usb), + .rst_ni(rst_usb_ni), + .mubi_i(((clk_usb_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.usb_infra) + ); + assign clocks_o.clk_io_div4_secure = clk_io_div4_root; + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_io_div4_secure ( + .clk_i(clk_io_div4), + .rst_ni(rst_io_div4_ni), + .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.io_div4_secure) + ); + assign clocks_o.clk_main_secure = clk_main_root; + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_main_secure ( + .clk_i(clk_main), + .rst_ni(rst_main_ni), + .mubi_i(((clk_main_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.main_secure) + ); + assign clocks_o.clk_io_div4_timers = clk_io_div4_root; + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_io_div4_timers ( + .clk_i(clk_io_div4), + .rst_ni(rst_io_div4_ni), + .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.io_div4_timers) + ); + + //////////////////////////////////////////////////// + // Software direct control group + //////////////////////////////////////////////////// + + logic clk_io_div4_peri_sw_en; + logic clk_io_div2_peri_sw_en; + logic clk_usb_peri_sw_en; + + prim_flop_2sync #( + .Width(1) + ) u_clk_io_div4_peri_sw_en_sync ( + .clk_i(clk_io_div4), + .rst_ni(rst_io_div4_ni), + .d_i(reg2hw.clk_enables.clk_io_div4_peri_en.q), + .q_o(clk_io_div4_peri_sw_en) + ); + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] clk_io_div4_peri_scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_clk_io_div4_peri_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o(clk_io_div4_peri_scanmode) + ); + + logic clk_io_div4_peri_combined_en; + assign clk_io_div4_peri_combined_en = clk_io_div4_peri_sw_en & clk_io_div4_en; + prim_clock_gating #( + .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions. + ) u_clk_io_div4_peri_cg ( + .clk_i(clk_io_div4), + .en_i(clk_io_div4_peri_combined_en), + .test_en_i(mubi4_test_true_strict(clk_io_div4_peri_scanmode[0])), + .clk_o(clocks_o.clk_io_div4_peri) + ); + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_io_div4_peri ( + .clk_i(clk_io_div4), + .rst_ni(rst_io_div4_ni), + .mubi_i(((clk_io_div4_peri_combined_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.io_div4_peri) + ); + + prim_flop_2sync #( + .Width(1) + ) u_clk_io_div2_peri_sw_en_sync ( + .clk_i(clk_io_div2), + .rst_ni(rst_io_div2_ni), + .d_i(reg2hw.clk_enables.clk_io_div2_peri_en.q), + .q_o(clk_io_div2_peri_sw_en) + ); + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] clk_io_div2_peri_scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_clk_io_div2_peri_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o(clk_io_div2_peri_scanmode) + ); + + logic clk_io_div2_peri_combined_en; + assign clk_io_div2_peri_combined_en = clk_io_div2_peri_sw_en & clk_io_div2_en; + prim_clock_gating #( + .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions. + ) u_clk_io_div2_peri_cg ( + .clk_i(clk_io_div2), + .en_i(clk_io_div2_peri_combined_en), + .test_en_i(mubi4_test_true_strict(clk_io_div2_peri_scanmode[0])), + .clk_o(clocks_o.clk_io_div2_peri) + ); + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_io_div2_peri ( + .clk_i(clk_io_div2), + .rst_ni(rst_io_div2_ni), + .mubi_i(((clk_io_div2_peri_combined_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.io_div2_peri) + ); + + prim_flop_2sync #( + .Width(1) + ) u_clk_usb_peri_sw_en_sync ( + .clk_i(clk_usb), + .rst_ni(rst_usb_ni), + .d_i(reg2hw.clk_enables.clk_usb_peri_en.q), + .q_o(clk_usb_peri_sw_en) + ); + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] clk_usb_peri_scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_clk_usb_peri_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o(clk_usb_peri_scanmode) + ); + + logic clk_usb_peri_combined_en; + assign clk_usb_peri_combined_en = clk_usb_peri_sw_en & clk_usb_en; + prim_clock_gating #( + .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions. + ) u_clk_usb_peri_cg ( + .clk_i(clk_usb), + .en_i(clk_usb_peri_combined_en), + .test_en_i(mubi4_test_true_strict(clk_usb_peri_scanmode[0])), + .clk_o(clocks_o.clk_usb_peri) + ); + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_usb_peri ( + .clk_i(clk_usb), + .rst_ni(rst_usb_ni), + .mubi_i(((clk_usb_peri_combined_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.usb_peri) + ); + + + //////////////////////////////////////////////////// + // Software hint group + // The idle hint feedback is assumed to be synchronous to the + // clock target + //////////////////////////////////////////////////// + + logic [3:0] idle_cnt_err; + + clkmgr_trans #( + .FpgaBufGlobal(1'b0) // This clock is used primarily locally. + ) u_clk_main_aes_trans ( + .clk_i(clk_main), + .clk_gated_i(clk_main_root), + .rst_ni(rst_main_ni), + .en_i(clk_main_en), + .idle_i(idle_i[HintMainAes]), + .sw_hint_i(reg2hw.clk_hints.clk_main_aes_hint.q), + .scanmode_i, + .alert_cg_en_o(cg_en_o.main_aes), + .clk_o(clocks_o.clk_main_aes), + .clk_reg_i(clk_i), + .rst_reg_ni(rst_ni), + .reg_en_o(hw2reg.clk_hints_status.clk_main_aes_val.d), + .reg_cnt_err_o(idle_cnt_err[HintMainAes]) + ); + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( + ClkMainAesCountCheck_A, + u_clk_main_aes_trans.u_idle_cnt, + alert_tx_o[1]) + + clkmgr_trans #( + .FpgaBufGlobal(1'b0) // This clock is used primarily locally. + ) u_clk_main_hmac_trans ( + .clk_i(clk_main), + .clk_gated_i(clk_main_root), + .rst_ni(rst_main_ni), + .en_i(clk_main_en), + .idle_i(idle_i[HintMainHmac]), + .sw_hint_i(reg2hw.clk_hints.clk_main_hmac_hint.q), + .scanmode_i, + .alert_cg_en_o(cg_en_o.main_hmac), + .clk_o(clocks_o.clk_main_hmac), + .clk_reg_i(clk_i), + .rst_reg_ni(rst_ni), + .reg_en_o(hw2reg.clk_hints_status.clk_main_hmac_val.d), + .reg_cnt_err_o(idle_cnt_err[HintMainHmac]) + ); + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( + ClkMainHmacCountCheck_A, + u_clk_main_hmac_trans.u_idle_cnt, + alert_tx_o[1]) + + clkmgr_trans #( + .FpgaBufGlobal(1'b1) // KMAC is getting too big for a single clock region. + ) u_clk_main_kmac_trans ( + .clk_i(clk_main), + .clk_gated_i(clk_main_root), + .rst_ni(rst_main_ni), + .en_i(clk_main_en), + .idle_i(idle_i[HintMainKmac]), + .sw_hint_i(reg2hw.clk_hints.clk_main_kmac_hint.q), + .scanmode_i, + .alert_cg_en_o(cg_en_o.main_kmac), + .clk_o(clocks_o.clk_main_kmac), + .clk_reg_i(clk_i), + .rst_reg_ni(rst_ni), + .reg_en_o(hw2reg.clk_hints_status.clk_main_kmac_val.d), + .reg_cnt_err_o(idle_cnt_err[HintMainKmac]) + ); + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( + ClkMainKmacCountCheck_A, + u_clk_main_kmac_trans.u_idle_cnt, + alert_tx_o[1]) + + clkmgr_trans #( + .FpgaBufGlobal(1'b0) // This clock is used primarily locally. + ) u_clk_main_otbn_trans ( + .clk_i(clk_main), + .clk_gated_i(clk_main_root), + .rst_ni(rst_main_ni), + .en_i(clk_main_en), + .idle_i(idle_i[HintMainOtbn]), + .sw_hint_i(reg2hw.clk_hints.clk_main_otbn_hint.q), + .scanmode_i, + .alert_cg_en_o(cg_en_o.main_otbn), + .clk_o(clocks_o.clk_main_otbn), + .clk_reg_i(clk_i), + .rst_reg_ni(rst_ni), + .reg_en_o(hw2reg.clk_hints_status.clk_main_otbn_val.d), + .reg_cnt_err_o(idle_cnt_err[HintMainOtbn]) + ); + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( + ClkMainOtbnCountCheck_A, + u_clk_main_otbn_trans.u_idle_cnt, + alert_tx_o[1]) + assign hw2reg.fatal_err_code.idle_cnt.d = 1'b1; + assign hw2reg.fatal_err_code.idle_cnt.de = |idle_cnt_err; + + // state readback + assign hw2reg.clk_hints_status.clk_main_aes_val.de = 1'b1; + assign hw2reg.clk_hints_status.clk_main_hmac_val.de = 1'b1; + assign hw2reg.clk_hints_status.clk_main_kmac_val.de = 1'b1; + assign hw2reg.clk_hints_status.clk_main_otbn_val.de = 1'b1; + + // SEC_CM: JITTER.CONFIG.MUBI + assign jitter_en_o = mubi4_t'(reg2hw.jitter_enable.q); + + //////////////////////////////////////////////////// + // Exported clocks + //////////////////////////////////////////////////// + + + //////////////////////////////////////////////////// + // Assertions + //////////////////////////////////////////////////// + + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready) + `ASSERT_KNOWN(AlertsKnownO_A, alert_tx_o) + `ASSERT_KNOWN(PwrMgrKnownO_A, pwr_o) + `ASSERT_KNOWN(AllClkBypReqKnownO_A, all_clk_byp_req_o) + `ASSERT_KNOWN(IoClkBypReqKnownO_A, io_clk_byp_req_o) + `ASSERT_KNOWN(LcCtrlClkBypAckKnownO_A, lc_clk_byp_ack_o) + `ASSERT_KNOWN(JitterEnableKnownO_A, jitter_en_o) + `ASSERT_KNOWN(ClocksKownO_A, clocks_o) + `ASSERT_KNOWN(CgEnKnownO_A, cg_en_o) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[1]) +endmodule // clkmgr diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_byp.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_byp.sv new file mode 100644 index 0000000000000..28bb82baa6087 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_byp.sv @@ -0,0 +1,163 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Handle clock manager bypass requests + +module clkmgr_byp + import clkmgr_pkg::*; + import lc_ctrl_pkg::lc_tx_t; + import prim_mubi_pkg::mubi4_t; +# ( + parameter int NumDivClks = 1 +) ( + input clk_i, + input rst_ni, + // interaction with lc_ctrl + input lc_tx_t en_i, + input lc_tx_t lc_clk_byp_req_i, + output lc_tx_t lc_clk_byp_ack_o, + // interaction with software + input mubi4_t byp_req_i, + output mubi4_t byp_ack_o, + input mubi4_t hi_speed_sel_i, + // interaction with ast + output mubi4_t all_clk_byp_req_o, + input mubi4_t all_clk_byp_ack_i, + output mubi4_t io_clk_byp_req_o, + input mubi4_t io_clk_byp_ack_i, + output mubi4_t hi_speed_sel_o, + // interaction with dividers + input [NumDivClks-1:0] step_down_acks_i +); + + import prim_mubi_pkg::MuBi4Width; + import prim_mubi_pkg::MuBi4True; + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::mubi4_and_hi; + import prim_mubi_pkg::mubi4_test_true_strict; + + // synchornize incoming lc signals + lc_tx_t en; + prim_lc_sync #( + .NumCopies(1), + .AsyncOn(1), + .ResetValueIsOn(0) + ) u_en_sync ( + .clk_i, + .rst_ni, + .lc_en_i(en_i), + .lc_en_o({en}) + ); + + typedef enum logic [1:0] { + LcClkBypReqIoReq, + LcClkBypReqLcAck, + LcClkBypReqLast + } lc_clk_byp_req_e; + + lc_tx_t [LcClkBypReqLast-1:0] lc_clk_byp_req; + prim_lc_sync #( + .NumCopies(int'(LcClkBypReqLast)), + .AsyncOn(1), + .ResetValueIsOn(0) + ) u_lc_byp_req ( + .clk_i, + .rst_ni, + .lc_en_i(lc_clk_byp_req_i), + .lc_en_o(lc_clk_byp_req) + ); + + // synchronize step down acks + logic [NumDivClks-1:0] step_down_acks_sync; + prim_flop #( + .Width(NumDivClks), + .ResetValue(0) + ) u_step_down_acks_sync ( + .clk_i, + .rst_ni, + .d_i(step_down_acks_i), + .q_o(step_down_acks_sync) + ); + + // life cycle handling + mubi4_t io_clk_byp_req_d; + assign io_clk_byp_req_d = lc_ctrl_pkg::lc_tx_test_true_strict(lc_clk_byp_req[LcClkBypReqIoReq]) ? + MuBi4True : + MuBi4False; + + prim_mubi4_sender #( + .ResetValue(MuBi4False), + .EnSecBuf(1) + ) u_io_byp_req ( + .clk_i, + .rst_ni, + .mubi_i(io_clk_byp_req_d), + .mubi_o(io_clk_byp_req_o) + ); + + // only ack the lc_ctrl if it made a request. + mubi4_t io_clk_byp_ack; + prim_lc_sender u_send ( + .clk_i, + .rst_ni, + .lc_en_i(&step_down_acks_sync & mubi4_test_true_strict(io_clk_byp_ack) ? + lc_clk_byp_req[LcClkBypReqLcAck] : lc_ctrl_pkg::Off), + .lc_en_o(lc_clk_byp_ack_o) + ); + + // software switch request handling + mubi4_t debug_en; + assign debug_en = lc_ctrl_pkg::lc_to_mubi4(en); + + mubi4_t all_clk_byp_req_d; + assign all_clk_byp_req_d = mubi4_and_hi(byp_req_i, debug_en); + + prim_mubi4_sender #( + .AsyncOn(1), + .ResetValue(MuBi4False), + .EnSecBuf(1) + ) u_all_byp_req ( + .clk_i, + .rst_ni, + .mubi_i(all_clk_byp_req_d), + .mubi_o(all_clk_byp_req_o) + ); + + prim_mubi4_sync #( + .AsyncOn(1), + .StabilityCheck(1), + .ResetValue(MuBi4False) + ) u_io_ack_sync ( + .clk_i, + .rst_ni, + .mubi_i(io_clk_byp_ack_i), + .mubi_o({io_clk_byp_ack}) + ); + + // since div_step_down_req is now directly fed externally, there is no longer + // a use for the related 'ack' signals + prim_mubi4_sync #( + .AsyncOn(1), + .StabilityCheck(1), + .ResetValue(MuBi4False) + ) u_all_ack_sync ( + .clk_i, + .rst_ni, + .mubi_i(all_clk_byp_ack_i), + .mubi_o({byp_ack_o}) + ); + + // the software high speed select is valid only when software requests clock + // bypass + prim_mubi4_sender #( + .AsyncOn(1), + .ResetValue(MuBi4True) + ) u_hi_speed_sel ( + .clk_i, + .rst_ni, + .mubi_i(mubi4_and_hi(all_clk_byp_req_d, hi_speed_sel_i)), + .mubi_o(hi_speed_sel_o) + ); + +endmodule // clkmgr_byp diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_clk_status.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_clk_status.sv new file mode 100644 index 0000000000000..3c6b38b1025c1 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_clk_status.sv @@ -0,0 +1,58 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Wrapper module for computing enable / disable status on family of clocks + +module clkmgr_clk_status #( + parameter int NumClocks = 1, + parameter int FilterStages = 2 +) ( + input clk_i, + input rst_ni, + input [NumClocks-1:0] ens_i, + output logic status_o +); + + // The enables are coming from different clock domains, + // therefore after synchronization we must de-bounce the + // signal to ensure it is stable + logic [NumClocks-1:0] ens_sync; + prim_flop_2sync #( + .Width(NumClocks) + ) u_en_sync ( + .clk_i, + .rst_ni, + .d_i(ens_i), + .q_o(ens_sync) + ); + + logic [FilterStages-1:0] en_q, dis_q, en_d, dis_d; + + // enable is true when all inputs are 1 + assign en_d = {en_q[FilterStages-2:0], &ens_sync}; + + // disable is true all all inputs are 0 + assign dis_d = {dis_q[FilterStages-2:0], ~|ens_sync}; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + en_q <= '0; + dis_q <= '0; + end else begin + en_q <= en_d; + dis_q <= dis_d; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + status_o <= '0; + end else if (&en_q) begin + status_o <= 1'b1; + end else if (&dis_q) begin + status_o <= 1'b0; + end + end + +endmodule // clkmgr_clk_status diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv new file mode 100644 index 0000000000000..ea0bc8e92be6f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv @@ -0,0 +1,127 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Clock manager measurement and timeout checks + +module clkmgr_meas_chk + import prim_mubi_pkg::mubi4_t; +#( + // Maximum value of input clock counts over measurement period + parameter int Cnt = 16, + // Maximum value of reference clock counts over measurement period + parameter int RefCnt = 1, + localparam int CntWidth = prim_util_pkg::vbits(Cnt) +) ( + // the local operating clock + input clk_i, + input rst_ni, + // the clock we are measuring + input clk_src_i, + input rst_src_ni, + // the reference clock we are measuring against + input clk_ref_i, + input rst_ref_ni, + // controls all provided on src clock + input src_en_i, + input [CntWidth-1:0] src_max_cnt_i, + input [CntWidth-1:0] src_min_cnt_i, + input mubi4_t src_cfg_meas_en_i, + output logic src_cfg_meas_en_valid_o, + output mubi4_t src_cfg_meas_en_o, + // calibration ready input provided on local operating clock + input mubi4_t calib_rdy_i, + // error output are provided on local operating clock + output logic meas_err_o, + output logic timeout_err_o +); + + logic src_fast_err; + logic src_slow_err; + logic ref_timeout_err; + + prim_clock_meas #( + .Cnt(Cnt), + .RefCnt(RefCnt), + .ClkTimeOutChkEn(1'b1), + .RefTimeOutChkEn(1'b0) + ) u_meas ( + .clk_i(clk_src_i), + .rst_ni(rst_src_ni), + .clk_ref_i, + .rst_ref_ni, + .en_i(src_en_i), + .max_cnt(src_max_cnt_i), + .min_cnt(src_min_cnt_i), + .valid_o(), + .fast_o(src_fast_err), + .slow_o(src_slow_err), + .timeout_clk_ref_o(), + .ref_timeout_clk_o(ref_timeout_err) + ); + + mubi4_t src_calib_rdy; + prim_mubi4_sync #( + .AsyncOn(1), + .ResetValue(prim_mubi_pkg::MuBi4False) + ) u_calib_rdy_sync ( + .clk_i, + .rst_ni, + .mubi_i(calib_rdy_i), + .mubi_o({src_calib_rdy}) + ); + + // if clocks become uncalibrated, switch off measurement controls + always_comb begin + src_cfg_meas_en_valid_o = '0; + src_cfg_meas_en_o = src_cfg_meas_en_i; + + // if calibration is lost when measurement is currently enabled, + // disable measurement enable. + if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && + prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin + src_cfg_meas_en_valid_o = 1'b1; + src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False; + end + end + + // A reqack module is used here instead of a pulse_saync + // because the source pulses may toggle too fast for the + // the destination to receive. + logic src_err_req, src_err_ack; + always_ff @(posedge clk_src_i or negedge rst_src_ni) begin + if (!rst_src_ni) begin + src_err_req <= '0; + end else if (src_fast_err || src_slow_err) begin + src_err_req <= 1'b1; + end else if (src_err_req && src_err_ack) begin + src_err_req <= '0; + end + end + + prim_sync_reqack u_err_sync ( + .clk_src_i, + .rst_src_ni, + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .req_chk_i(1'b1), + .src_req_i(src_err_req), + .src_ack_o(src_err_ack), + .dst_req_o(meas_err_o), + .dst_ack_i(meas_err_o) + ); + + prim_edge_detector #( + .Width(1), + .ResetValue('0), + .EnSync(1'b1) + ) u_timeout_err_sync ( + .clk_i, + .rst_ni, + .d_i(ref_timeout_err), + .q_sync_o(), + .q_posedge_pulse_o(timeout_err_o), + .q_negedge_pulse_o() + ); + +endmodule // clkmgr_meas_chk diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv new file mode 100644 index 0000000000000..1a0b5de9ef159 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv @@ -0,0 +1,81 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + + + +package clkmgr_pkg; + + typedef enum int { + HintMainAes = 0, + HintMainHmac = 1, + HintMainKmac = 2, + HintMainOtbn = 3 + } hint_names_e; + + // clocks generated and broadcast + typedef struct packed { + logic clk_io_div4_powerup; + logic clk_aon_powerup; + logic clk_main_powerup; + logic clk_io_powerup; + logic clk_usb_powerup; + logic clk_io_div2_powerup; + logic clk_aon_infra; + logic clk_aon_secure; + logic clk_aon_peri; + logic clk_aon_timers; + logic clk_main_aes; + logic clk_main_hmac; + logic clk_main_kmac; + logic clk_main_otbn; + logic clk_io_div4_infra; + logic clk_main_infra; + logic clk_usb_infra; + logic clk_io_div4_secure; + logic clk_main_secure; + logic clk_io_div4_timers; + logic clk_io_div4_peri; + logic clk_io_div2_peri; + logic clk_usb_peri; + } clkmgr_out_t; + + // clock gating indication for alert handler + typedef struct packed { + prim_mubi_pkg::mubi4_t io_div4_powerup; + prim_mubi_pkg::mubi4_t aon_powerup; + prim_mubi_pkg::mubi4_t main_powerup; + prim_mubi_pkg::mubi4_t io_powerup; + prim_mubi_pkg::mubi4_t usb_powerup; + prim_mubi_pkg::mubi4_t io_div2_powerup; + prim_mubi_pkg::mubi4_t aon_infra; + prim_mubi_pkg::mubi4_t aon_secure; + prim_mubi_pkg::mubi4_t aon_peri; + prim_mubi_pkg::mubi4_t aon_timers; + prim_mubi_pkg::mubi4_t main_aes; + prim_mubi_pkg::mubi4_t main_hmac; + prim_mubi_pkg::mubi4_t main_kmac; + prim_mubi_pkg::mubi4_t main_otbn; + prim_mubi_pkg::mubi4_t io_div4_infra; + prim_mubi_pkg::mubi4_t main_infra; + prim_mubi_pkg::mubi4_t usb_infra; + prim_mubi_pkg::mubi4_t io_div4_secure; + prim_mubi_pkg::mubi4_t main_secure; + prim_mubi_pkg::mubi4_t io_div4_timers; + prim_mubi_pkg::mubi4_t io_div4_peri; + prim_mubi_pkg::mubi4_t io_div2_peri; + prim_mubi_pkg::mubi4_t usb_peri; + } clkmgr_cg_en_t; + + parameter int NumOutputClk = 23; + + + typedef struct packed { + logic [4-1:0] idle; + } clk_hint_status_t; + + parameter clk_hint_status_t CLK_HINT_STATUS_DEFAULT = '{ + idle: {4{1'b1}} + }; + +endpackage // clkmgr_pkg diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv new file mode 100644 index 0000000000000..a366a4e0b5f7a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv @@ -0,0 +1,317 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package clkmgr_reg_pkg; + + // Param list + parameter int NumGroups = 7; + parameter int NumSwGateableClocks = 3; + parameter int NumHintableClocks = 4; + parameter int NumAlerts = 2; + + // Address widths within the block + parameter int BlockAw = 7; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic q; + logic qe; + } fatal_fault; + struct packed { + logic q; + logic qe; + } recov_fault; + } clkmgr_reg2hw_alert_test_reg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + } hi_speed_sel; + struct packed { + logic [3:0] q; + } sel; + } clkmgr_reg2hw_extclk_ctrl_reg_t; + + typedef struct packed { + logic [3:0] q; + } clkmgr_reg2hw_jitter_enable_reg_t; + + typedef struct packed { + struct packed { + logic q; + } clk_usb_peri_en; + struct packed { + logic q; + } clk_io_div2_peri_en; + struct packed { + logic q; + } clk_io_div4_peri_en; + } clkmgr_reg2hw_clk_enables_reg_t; + + typedef struct packed { + struct packed { + logic q; + } clk_main_otbn_hint; + struct packed { + logic q; + } clk_main_kmac_hint; + struct packed { + logic q; + } clk_main_hmac_hint; + struct packed { + logic q; + } clk_main_aes_hint; + } clkmgr_reg2hw_clk_hints_reg_t; + + typedef struct packed { + logic q; + } clkmgr_reg2hw_measure_ctrl_regwen_reg_t; + + typedef struct packed { + logic [3:0] q; + } clkmgr_reg2hw_io_div4_meas_ctrl_en_reg_t; + + typedef struct packed { + struct packed { + logic [7:0] q; + } lo; + struct packed { + logic [7:0] q; + } hi; + } clkmgr_reg2hw_io_div4_meas_ctrl_shadowed_reg_t; + + typedef struct packed { + logic [3:0] q; + } clkmgr_reg2hw_main_meas_ctrl_en_reg_t; + + typedef struct packed { + struct packed { + logic [9:0] q; + } lo; + struct packed { + logic [9:0] q; + } hi; + } clkmgr_reg2hw_main_meas_ctrl_shadowed_reg_t; + + typedef struct packed { + logic [3:0] q; + } clkmgr_reg2hw_usb_meas_ctrl_en_reg_t; + + typedef struct packed { + struct packed { + logic [8:0] q; + } lo; + struct packed { + logic [8:0] q; + } hi; + } clkmgr_reg2hw_usb_meas_ctrl_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic q; + } shadow_storage_err; + struct packed { + logic q; + } idle_cnt; + struct packed { + logic q; + } reg_intg; + } clkmgr_reg2hw_fatal_err_code_reg_t; + + typedef struct packed { + logic [3:0] d; + } clkmgr_hw2reg_extclk_status_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } clk_main_aes_val; + struct packed { + logic d; + logic de; + } clk_main_hmac_val; + struct packed { + logic d; + logic de; + } clk_main_kmac_val; + struct packed { + logic d; + logic de; + } clk_main_otbn_val; + } clkmgr_hw2reg_clk_hints_status_reg_t; + + typedef struct packed { + logic d; + logic de; + } clkmgr_hw2reg_measure_ctrl_regwen_reg_t; + + typedef struct packed { + logic [3:0] d; + logic de; + } clkmgr_hw2reg_io_div4_meas_ctrl_en_reg_t; + + typedef struct packed { + logic [3:0] d; + logic de; + } clkmgr_hw2reg_main_meas_ctrl_en_reg_t; + + typedef struct packed { + logic [3:0] d; + logic de; + } clkmgr_hw2reg_usb_meas_ctrl_en_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } shadow_update_err; + struct packed { + logic d; + logic de; + } io_div4_measure_err; + struct packed { + logic d; + logic de; + } main_measure_err; + struct packed { + logic d; + logic de; + } usb_measure_err; + struct packed { + logic d; + logic de; + } io_div4_timeout_err; + struct packed { + logic d; + logic de; + } main_timeout_err; + struct packed { + logic d; + logic de; + } usb_timeout_err; + } clkmgr_hw2reg_recov_err_code_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } reg_intg; + struct packed { + logic d; + logic de; + } idle_cnt; + struct packed { + logic d; + logic de; + } shadow_storage_err; + } clkmgr_hw2reg_fatal_err_code_reg_t; + + // Register -> HW type + typedef struct packed { + clkmgr_reg2hw_alert_test_reg_t alert_test; // [92:89] + clkmgr_reg2hw_extclk_ctrl_reg_t extclk_ctrl; // [88:81] + clkmgr_reg2hw_jitter_enable_reg_t jitter_enable; // [80:77] + clkmgr_reg2hw_clk_enables_reg_t clk_enables; // [76:74] + clkmgr_reg2hw_clk_hints_reg_t clk_hints; // [73:70] + clkmgr_reg2hw_measure_ctrl_regwen_reg_t measure_ctrl_regwen; // [69:69] + clkmgr_reg2hw_io_div4_meas_ctrl_en_reg_t io_div4_meas_ctrl_en; // [68:65] + clkmgr_reg2hw_io_div4_meas_ctrl_shadowed_reg_t io_div4_meas_ctrl_shadowed; // [64:49] + clkmgr_reg2hw_main_meas_ctrl_en_reg_t main_meas_ctrl_en; // [48:45] + clkmgr_reg2hw_main_meas_ctrl_shadowed_reg_t main_meas_ctrl_shadowed; // [44:25] + clkmgr_reg2hw_usb_meas_ctrl_en_reg_t usb_meas_ctrl_en; // [24:21] + clkmgr_reg2hw_usb_meas_ctrl_shadowed_reg_t usb_meas_ctrl_shadowed; // [20:3] + clkmgr_reg2hw_fatal_err_code_reg_t fatal_err_code; // [2:0] + } clkmgr_reg2hw_t; + + // HW -> register type + typedef struct packed { + clkmgr_hw2reg_extclk_status_reg_t extclk_status; // [48:45] + clkmgr_hw2reg_clk_hints_status_reg_t clk_hints_status; // [44:37] + clkmgr_hw2reg_measure_ctrl_regwen_reg_t measure_ctrl_regwen; // [36:35] + clkmgr_hw2reg_io_div4_meas_ctrl_en_reg_t io_div4_meas_ctrl_en; // [34:30] + clkmgr_hw2reg_main_meas_ctrl_en_reg_t main_meas_ctrl_en; // [29:25] + clkmgr_hw2reg_usb_meas_ctrl_en_reg_t usb_meas_ctrl_en; // [24:20] + clkmgr_hw2reg_recov_err_code_reg_t recov_err_code; // [19:6] + clkmgr_hw2reg_fatal_err_code_reg_t fatal_err_code; // [5:0] + } clkmgr_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] CLKMGR_ALERT_TEST_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_CTRL_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_STATUS_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] CLKMGR_JITTER_REGWEN_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] CLKMGR_JITTER_ENABLE_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] CLKMGR_CLK_ENABLES_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_STATUS_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] CLKMGR_MEASURE_CTRL_REGWEN_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] CLKMGR_USB_MEAS_CTRL_EN_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] CLKMGR_RECOV_ERR_CODE_OFFSET = 7'h 40; + parameter logic [BlockAw-1:0] CLKMGR_FATAL_ERR_CODE_OFFSET = 7'h 44; + + // Reset values for hwext registers and their fields + parameter logic [1:0] CLKMGR_ALERT_TEST_RESVAL = 2'h 0; + parameter logic [0:0] CLKMGR_ALERT_TEST_RECOV_FAULT_RESVAL = 1'h 0; + parameter logic [0:0] CLKMGR_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [3:0] CLKMGR_EXTCLK_STATUS_RESVAL = 4'h 9; + parameter logic [3:0] CLKMGR_EXTCLK_STATUS_ACK_RESVAL = 4'h 9; + + // Register index + typedef enum int { + CLKMGR_ALERT_TEST, + CLKMGR_EXTCLK_CTRL_REGWEN, + CLKMGR_EXTCLK_CTRL, + CLKMGR_EXTCLK_STATUS, + CLKMGR_JITTER_REGWEN, + CLKMGR_JITTER_ENABLE, + CLKMGR_CLK_ENABLES, + CLKMGR_CLK_HINTS, + CLKMGR_CLK_HINTS_STATUS, + CLKMGR_MEASURE_CTRL_REGWEN, + CLKMGR_IO_DIV4_MEAS_CTRL_EN, + CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED, + CLKMGR_MAIN_MEAS_CTRL_EN, + CLKMGR_MAIN_MEAS_CTRL_SHADOWED, + CLKMGR_USB_MEAS_CTRL_EN, + CLKMGR_USB_MEAS_CTRL_SHADOWED, + CLKMGR_RECOV_ERR_CODE, + CLKMGR_FATAL_ERR_CODE + } clkmgr_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] CLKMGR_PERMIT [18] = '{ + 4'b 0001, // index[ 0] CLKMGR_ALERT_TEST + 4'b 0001, // index[ 1] CLKMGR_EXTCLK_CTRL_REGWEN + 4'b 0001, // index[ 2] CLKMGR_EXTCLK_CTRL + 4'b 0001, // index[ 3] CLKMGR_EXTCLK_STATUS + 4'b 0001, // index[ 4] CLKMGR_JITTER_REGWEN + 4'b 0001, // index[ 5] CLKMGR_JITTER_ENABLE + 4'b 0001, // index[ 6] CLKMGR_CLK_ENABLES + 4'b 0001, // index[ 7] CLKMGR_CLK_HINTS + 4'b 0001, // index[ 8] CLKMGR_CLK_HINTS_STATUS + 4'b 0001, // index[ 9] CLKMGR_MEASURE_CTRL_REGWEN + 4'b 0001, // index[10] CLKMGR_IO_DIV4_MEAS_CTRL_EN + 4'b 0011, // index[11] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED + 4'b 0001, // index[12] CLKMGR_MAIN_MEAS_CTRL_EN + 4'b 0111, // index[13] CLKMGR_MAIN_MEAS_CTRL_SHADOWED + 4'b 0001, // index[14] CLKMGR_USB_MEAS_CTRL_EN + 4'b 0111, // index[15] CLKMGR_USB_MEAS_CTRL_SHADOWED + 4'b 0001, // index[16] CLKMGR_RECOV_ERR_CODE + 4'b 0001 // index[17] CLKMGR_FATAL_ERR_CODE + }; + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv new file mode 100644 index 0000000000000..8c43d14339582 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv @@ -0,0 +1,2096 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module clkmgr_reg_top ( + input clk_i, + input rst_ni, + input rst_shadowed_ni, + input clk_io_div4_i, + input rst_io_div4_ni, + input clk_main_i, + input rst_main_ni, + input clk_usb_i, + input rst_usb_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output clkmgr_reg_pkg::clkmgr_reg2hw_t reg2hw, // Write + input clkmgr_reg_pkg::clkmgr_hw2reg_t hw2reg, // Read + + output logic shadowed_storage_err_o, + output logic shadowed_update_err_o, + + // Integrity check errors + output logic intg_err_o +); + + import clkmgr_reg_pkg::* ; + + localparam int AW = 7; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [17:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(18) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic alert_test_we; + logic alert_test_recov_fault_wd; + logic alert_test_fatal_fault_wd; + logic extclk_ctrl_regwen_we; + logic extclk_ctrl_regwen_qs; + logic extclk_ctrl_regwen_wd; + logic extclk_ctrl_we; + logic [3:0] extclk_ctrl_sel_qs; + logic [3:0] extclk_ctrl_sel_wd; + logic [3:0] extclk_ctrl_hi_speed_sel_qs; + logic [3:0] extclk_ctrl_hi_speed_sel_wd; + logic extclk_status_re; + logic [3:0] extclk_status_qs; + logic jitter_regwen_we; + logic jitter_regwen_qs; + logic jitter_regwen_wd; + logic jitter_enable_we; + logic [3:0] jitter_enable_qs; + logic [3:0] jitter_enable_wd; + logic clk_enables_we; + logic clk_enables_clk_io_div4_peri_en_qs; + logic clk_enables_clk_io_div4_peri_en_wd; + logic clk_enables_clk_io_div2_peri_en_qs; + logic clk_enables_clk_io_div2_peri_en_wd; + logic clk_enables_clk_usb_peri_en_qs; + logic clk_enables_clk_usb_peri_en_wd; + logic clk_hints_we; + logic clk_hints_clk_main_aes_hint_qs; + logic clk_hints_clk_main_aes_hint_wd; + logic clk_hints_clk_main_hmac_hint_qs; + logic clk_hints_clk_main_hmac_hint_wd; + logic clk_hints_clk_main_kmac_hint_qs; + logic clk_hints_clk_main_kmac_hint_wd; + logic clk_hints_clk_main_otbn_hint_qs; + logic clk_hints_clk_main_otbn_hint_wd; + logic clk_hints_status_clk_main_aes_val_qs; + logic clk_hints_status_clk_main_hmac_val_qs; + logic clk_hints_status_clk_main_kmac_val_qs; + logic clk_hints_status_clk_main_otbn_val_qs; + logic measure_ctrl_regwen_we; + logic measure_ctrl_regwen_qs; + logic measure_ctrl_regwen_wd; + logic io_div4_meas_ctrl_en_we; + logic [3:0] io_div4_meas_ctrl_en_qs; + logic io_div4_meas_ctrl_en_busy; + logic io_div4_meas_ctrl_shadowed_re; + logic io_div4_meas_ctrl_shadowed_we; + logic [15:0] io_div4_meas_ctrl_shadowed_qs; + logic io_div4_meas_ctrl_shadowed_busy; + logic io_div4_meas_ctrl_shadowed_hi_storage_err; + logic io_div4_meas_ctrl_shadowed_hi_update_err; + logic io_div4_meas_ctrl_shadowed_lo_storage_err; + logic io_div4_meas_ctrl_shadowed_lo_update_err; + logic main_meas_ctrl_en_we; + logic [3:0] main_meas_ctrl_en_qs; + logic main_meas_ctrl_en_busy; + logic main_meas_ctrl_shadowed_re; + logic main_meas_ctrl_shadowed_we; + logic [19:0] main_meas_ctrl_shadowed_qs; + logic main_meas_ctrl_shadowed_busy; + logic main_meas_ctrl_shadowed_hi_storage_err; + logic main_meas_ctrl_shadowed_hi_update_err; + logic main_meas_ctrl_shadowed_lo_storage_err; + logic main_meas_ctrl_shadowed_lo_update_err; + logic usb_meas_ctrl_en_we; + logic [3:0] usb_meas_ctrl_en_qs; + logic usb_meas_ctrl_en_busy; + logic usb_meas_ctrl_shadowed_re; + logic usb_meas_ctrl_shadowed_we; + logic [17:0] usb_meas_ctrl_shadowed_qs; + logic usb_meas_ctrl_shadowed_busy; + logic usb_meas_ctrl_shadowed_hi_storage_err; + logic usb_meas_ctrl_shadowed_hi_update_err; + logic usb_meas_ctrl_shadowed_lo_storage_err; + logic usb_meas_ctrl_shadowed_lo_update_err; + logic recov_err_code_we; + logic recov_err_code_shadow_update_err_qs; + logic recov_err_code_shadow_update_err_wd; + logic recov_err_code_io_div4_measure_err_qs; + logic recov_err_code_io_div4_measure_err_wd; + logic recov_err_code_main_measure_err_qs; + logic recov_err_code_main_measure_err_wd; + logic recov_err_code_usb_measure_err_qs; + logic recov_err_code_usb_measure_err_wd; + logic recov_err_code_io_div4_timeout_err_qs; + logic recov_err_code_io_div4_timeout_err_wd; + logic recov_err_code_main_timeout_err_qs; + logic recov_err_code_main_timeout_err_wd; + logic recov_err_code_usb_timeout_err_qs; + logic recov_err_code_usb_timeout_err_wd; + logic fatal_err_code_reg_intg_qs; + logic fatal_err_code_idle_cnt_qs; + logic fatal_err_code_shadow_storage_err_qs; + // Define register CDC handling. + // CDC handling is done on a per-reg instead of per-field boundary. + + logic [3:0] io_div4_io_div4_meas_ctrl_en_ds_int; + logic [3:0] io_div4_io_div4_meas_ctrl_en_qs_int; + logic [3:0] io_div4_io_div4_meas_ctrl_en_ds; + logic io_div4_io_div4_meas_ctrl_en_qe; + logic [3:0] io_div4_io_div4_meas_ctrl_en_qs; + logic [3:0] io_div4_io_div4_meas_ctrl_en_wdata; + logic io_div4_io_div4_meas_ctrl_en_we; + logic unused_io_div4_io_div4_meas_ctrl_en_wdata; + logic io_div4_io_div4_meas_ctrl_en_regwen; + + always_comb begin + io_div4_io_div4_meas_ctrl_en_qs = 4'h9; + io_div4_io_div4_meas_ctrl_en_ds = 4'h9; + io_div4_io_div4_meas_ctrl_en_ds = io_div4_io_div4_meas_ctrl_en_ds_int; + io_div4_io_div4_meas_ctrl_en_qs = io_div4_io_div4_meas_ctrl_en_qs_int; + end + + prim_reg_cdc #( + .DataWidth(4), + .ResetVal(4'h9), + .BitMask(4'hf), + .DstWrReq(1) + ) u_io_div4_meas_ctrl_en_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_io_div4_i), + .rst_dst_ni (rst_io_div4_ni), + .src_regwen_i (measure_ctrl_regwen_qs), + .src_we_i (io_div4_meas_ctrl_en_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[3:0]), + .src_busy_o (io_div4_meas_ctrl_en_busy), + .src_qs_o (io_div4_meas_ctrl_en_qs), // for software read back + .dst_update_i (io_div4_io_div4_meas_ctrl_en_qe), + .dst_ds_i (io_div4_io_div4_meas_ctrl_en_ds), + .dst_qs_i (io_div4_io_div4_meas_ctrl_en_qs), + .dst_we_o (io_div4_io_div4_meas_ctrl_en_we), + .dst_re_o (), + .dst_regwen_o (io_div4_io_div4_meas_ctrl_en_regwen), + .dst_wd_o (io_div4_io_div4_meas_ctrl_en_wdata) + ); + assign unused_io_div4_io_div4_meas_ctrl_en_wdata = + ^io_div4_io_div4_meas_ctrl_en_wdata; + + logic [7:0] io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int; + logic [7:0] io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int; + logic [15:0] io_div4_io_div4_meas_ctrl_shadowed_qs; + logic [15:0] io_div4_io_div4_meas_ctrl_shadowed_wdata; + logic io_div4_io_div4_meas_ctrl_shadowed_we; + logic unused_io_div4_io_div4_meas_ctrl_shadowed_wdata; + logic io_div4_io_div4_meas_ctrl_shadowed_re; + logic io_div4_io_div4_meas_ctrl_shadowed_regwen; + + always_comb begin + io_div4_io_div4_meas_ctrl_shadowed_qs = 16'h6e82; + io_div4_io_div4_meas_ctrl_shadowed_qs[7:0] = io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int; + io_div4_io_div4_meas_ctrl_shadowed_qs[15:8] = io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int; + end + + prim_reg_cdc #( + .DataWidth(16), + .ResetVal(16'h6e82), + .BitMask(16'hffff), + .DstWrReq(0) + ) u_io_div4_meas_ctrl_shadowed_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_io_div4_i), + .rst_dst_ni (rst_io_div4_ni), + .src_regwen_i (measure_ctrl_regwen_qs), + .src_we_i (io_div4_meas_ctrl_shadowed_we), + .src_re_i (io_div4_meas_ctrl_shadowed_re), + .src_wd_i (reg_wdata[15:0]), + .src_busy_o (io_div4_meas_ctrl_shadowed_busy), + .src_qs_o (io_div4_meas_ctrl_shadowed_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (io_div4_io_div4_meas_ctrl_shadowed_qs), + .dst_we_o (io_div4_io_div4_meas_ctrl_shadowed_we), + .dst_re_o (io_div4_io_div4_meas_ctrl_shadowed_re), + .dst_regwen_o (io_div4_io_div4_meas_ctrl_shadowed_regwen), + .dst_wd_o (io_div4_io_div4_meas_ctrl_shadowed_wdata) + ); + assign unused_io_div4_io_div4_meas_ctrl_shadowed_wdata = + ^io_div4_io_div4_meas_ctrl_shadowed_wdata; + + logic [3:0] main_main_meas_ctrl_en_ds_int; + logic [3:0] main_main_meas_ctrl_en_qs_int; + logic [3:0] main_main_meas_ctrl_en_ds; + logic main_main_meas_ctrl_en_qe; + logic [3:0] main_main_meas_ctrl_en_qs; + logic [3:0] main_main_meas_ctrl_en_wdata; + logic main_main_meas_ctrl_en_we; + logic unused_main_main_meas_ctrl_en_wdata; + logic main_main_meas_ctrl_en_regwen; + + always_comb begin + main_main_meas_ctrl_en_qs = 4'h9; + main_main_meas_ctrl_en_ds = 4'h9; + main_main_meas_ctrl_en_ds = main_main_meas_ctrl_en_ds_int; + main_main_meas_ctrl_en_qs = main_main_meas_ctrl_en_qs_int; + end + + prim_reg_cdc #( + .DataWidth(4), + .ResetVal(4'h9), + .BitMask(4'hf), + .DstWrReq(1) + ) u_main_meas_ctrl_en_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_main_i), + .rst_dst_ni (rst_main_ni), + .src_regwen_i (measure_ctrl_regwen_qs), + .src_we_i (main_meas_ctrl_en_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[3:0]), + .src_busy_o (main_meas_ctrl_en_busy), + .src_qs_o (main_meas_ctrl_en_qs), // for software read back + .dst_update_i (main_main_meas_ctrl_en_qe), + .dst_ds_i (main_main_meas_ctrl_en_ds), + .dst_qs_i (main_main_meas_ctrl_en_qs), + .dst_we_o (main_main_meas_ctrl_en_we), + .dst_re_o (), + .dst_regwen_o (main_main_meas_ctrl_en_regwen), + .dst_wd_o (main_main_meas_ctrl_en_wdata) + ); + assign unused_main_main_meas_ctrl_en_wdata = + ^main_main_meas_ctrl_en_wdata; + + logic [9:0] main_main_meas_ctrl_shadowed_hi_qs_int; + logic [9:0] main_main_meas_ctrl_shadowed_lo_qs_int; + logic [19:0] main_main_meas_ctrl_shadowed_qs; + logic [19:0] main_main_meas_ctrl_shadowed_wdata; + logic main_main_meas_ctrl_shadowed_we; + logic unused_main_main_meas_ctrl_shadowed_wdata; + logic main_main_meas_ctrl_shadowed_re; + logic main_main_meas_ctrl_shadowed_regwen; + + always_comb begin + main_main_meas_ctrl_shadowed_qs = 20'h7a9fe; + main_main_meas_ctrl_shadowed_qs[9:0] = main_main_meas_ctrl_shadowed_hi_qs_int; + main_main_meas_ctrl_shadowed_qs[19:10] = main_main_meas_ctrl_shadowed_lo_qs_int; + end + + prim_reg_cdc #( + .DataWidth(20), + .ResetVal(20'h7a9fe), + .BitMask(20'hfffff), + .DstWrReq(0) + ) u_main_meas_ctrl_shadowed_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_main_i), + .rst_dst_ni (rst_main_ni), + .src_regwen_i (measure_ctrl_regwen_qs), + .src_we_i (main_meas_ctrl_shadowed_we), + .src_re_i (main_meas_ctrl_shadowed_re), + .src_wd_i (reg_wdata[19:0]), + .src_busy_o (main_meas_ctrl_shadowed_busy), + .src_qs_o (main_meas_ctrl_shadowed_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (main_main_meas_ctrl_shadowed_qs), + .dst_we_o (main_main_meas_ctrl_shadowed_we), + .dst_re_o (main_main_meas_ctrl_shadowed_re), + .dst_regwen_o (main_main_meas_ctrl_shadowed_regwen), + .dst_wd_o (main_main_meas_ctrl_shadowed_wdata) + ); + assign unused_main_main_meas_ctrl_shadowed_wdata = + ^main_main_meas_ctrl_shadowed_wdata; + + logic [3:0] usb_usb_meas_ctrl_en_ds_int; + logic [3:0] usb_usb_meas_ctrl_en_qs_int; + logic [3:0] usb_usb_meas_ctrl_en_ds; + logic usb_usb_meas_ctrl_en_qe; + logic [3:0] usb_usb_meas_ctrl_en_qs; + logic [3:0] usb_usb_meas_ctrl_en_wdata; + logic usb_usb_meas_ctrl_en_we; + logic unused_usb_usb_meas_ctrl_en_wdata; + logic usb_usb_meas_ctrl_en_regwen; + + always_comb begin + usb_usb_meas_ctrl_en_qs = 4'h9; + usb_usb_meas_ctrl_en_ds = 4'h9; + usb_usb_meas_ctrl_en_ds = usb_usb_meas_ctrl_en_ds_int; + usb_usb_meas_ctrl_en_qs = usb_usb_meas_ctrl_en_qs_int; + end + + prim_reg_cdc #( + .DataWidth(4), + .ResetVal(4'h9), + .BitMask(4'hf), + .DstWrReq(1) + ) u_usb_meas_ctrl_en_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_usb_i), + .rst_dst_ni (rst_usb_ni), + .src_regwen_i (measure_ctrl_regwen_qs), + .src_we_i (usb_meas_ctrl_en_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[3:0]), + .src_busy_o (usb_meas_ctrl_en_busy), + .src_qs_o (usb_meas_ctrl_en_qs), // for software read back + .dst_update_i (usb_usb_meas_ctrl_en_qe), + .dst_ds_i (usb_usb_meas_ctrl_en_ds), + .dst_qs_i (usb_usb_meas_ctrl_en_qs), + .dst_we_o (usb_usb_meas_ctrl_en_we), + .dst_re_o (), + .dst_regwen_o (usb_usb_meas_ctrl_en_regwen), + .dst_wd_o (usb_usb_meas_ctrl_en_wdata) + ); + assign unused_usb_usb_meas_ctrl_en_wdata = + ^usb_usb_meas_ctrl_en_wdata; + + logic [8:0] usb_usb_meas_ctrl_shadowed_hi_qs_int; + logic [8:0] usb_usb_meas_ctrl_shadowed_lo_qs_int; + logic [17:0] usb_usb_meas_ctrl_shadowed_qs; + logic [17:0] usb_usb_meas_ctrl_shadowed_wdata; + logic usb_usb_meas_ctrl_shadowed_we; + logic unused_usb_usb_meas_ctrl_shadowed_wdata; + logic usb_usb_meas_ctrl_shadowed_re; + logic usb_usb_meas_ctrl_shadowed_regwen; + + always_comb begin + usb_usb_meas_ctrl_shadowed_qs = 18'h1ccfa; + usb_usb_meas_ctrl_shadowed_qs[8:0] = usb_usb_meas_ctrl_shadowed_hi_qs_int; + usb_usb_meas_ctrl_shadowed_qs[17:9] = usb_usb_meas_ctrl_shadowed_lo_qs_int; + end + + prim_reg_cdc #( + .DataWidth(18), + .ResetVal(18'h1ccfa), + .BitMask(18'h3ffff), + .DstWrReq(0) + ) u_usb_meas_ctrl_shadowed_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_usb_i), + .rst_dst_ni (rst_usb_ni), + .src_regwen_i (measure_ctrl_regwen_qs), + .src_we_i (usb_meas_ctrl_shadowed_we), + .src_re_i (usb_meas_ctrl_shadowed_re), + .src_wd_i (reg_wdata[17:0]), + .src_busy_o (usb_meas_ctrl_shadowed_busy), + .src_qs_o (usb_meas_ctrl_shadowed_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (usb_usb_meas_ctrl_shadowed_qs), + .dst_we_o (usb_usb_meas_ctrl_shadowed_we), + .dst_re_o (usb_usb_meas_ctrl_shadowed_re), + .dst_regwen_o (usb_usb_meas_ctrl_shadowed_regwen), + .dst_wd_o (usb_usb_meas_ctrl_shadowed_wdata) + ); + assign unused_usb_usb_meas_ctrl_shadowed_wdata = + ^usb_usb_meas_ctrl_shadowed_wdata; + + // Register instances + // R[alert_test]: V(True) + logic alert_test_qe; + logic [1:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + // F[recov_fault]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_fault ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_recov_fault_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.recov_fault.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.recov_fault.qe = alert_test_qe; + + // F[fatal_fault]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_fault ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_fault_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[1]), + .q (reg2hw.alert_test.fatal_fault.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe; + + + // R[extclk_ctrl_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_extclk_ctrl_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (extclk_ctrl_regwen_we), + .wd (extclk_ctrl_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (extclk_ctrl_regwen_qs) + ); + + + // R[extclk_ctrl]: V(False) + // Create REGWEN-gated WE signal + logic extclk_ctrl_gated_we; + assign extclk_ctrl_gated_we = extclk_ctrl_we & extclk_ctrl_regwen_qs; + // F[sel]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_extclk_ctrl_sel ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (extclk_ctrl_gated_we), + .wd (extclk_ctrl_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.extclk_ctrl.sel.q), + .ds (), + + // to register interface (read) + .qs (extclk_ctrl_sel_qs) + ); + + // F[hi_speed_sel]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_extclk_ctrl_hi_speed_sel ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (extclk_ctrl_gated_we), + .wd (extclk_ctrl_hi_speed_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.extclk_ctrl.hi_speed_sel.q), + .ds (), + + // to register interface (read) + .qs (extclk_ctrl_hi_speed_sel_qs) + ); + + + // R[extclk_status]: V(True) + prim_subreg_ext #( + .DW (4) + ) u_extclk_status ( + .re (extclk_status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.extclk_status.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (extclk_status_qs) + ); + + + // R[jitter_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_jitter_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (jitter_regwen_we), + .wd (jitter_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (jitter_regwen_qs) + ); + + + // R[jitter_enable]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_jitter_enable ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (jitter_enable_we), + .wd (jitter_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.jitter_enable.q), + .ds (), + + // to register interface (read) + .qs (jitter_enable_qs) + ); + + + // R[clk_enables]: V(False) + // F[clk_io_div4_peri_en]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_enables_clk_io_div4_peri_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (clk_enables_we), + .wd (clk_enables_clk_io_div4_peri_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.clk_enables.clk_io_div4_peri_en.q), + .ds (), + + // to register interface (read) + .qs (clk_enables_clk_io_div4_peri_en_qs) + ); + + // F[clk_io_div2_peri_en]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_enables_clk_io_div2_peri_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (clk_enables_we), + .wd (clk_enables_clk_io_div2_peri_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.clk_enables.clk_io_div2_peri_en.q), + .ds (), + + // to register interface (read) + .qs (clk_enables_clk_io_div2_peri_en_qs) + ); + + // F[clk_usb_peri_en]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_enables_clk_usb_peri_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (clk_enables_we), + .wd (clk_enables_clk_usb_peri_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.clk_enables.clk_usb_peri_en.q), + .ds (), + + // to register interface (read) + .qs (clk_enables_clk_usb_peri_en_qs) + ); + + + // R[clk_hints]: V(False) + // F[clk_main_aes_hint]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_clk_main_aes_hint ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (clk_hints_we), + .wd (clk_hints_clk_main_aes_hint_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.clk_hints.clk_main_aes_hint.q), + .ds (), + + // to register interface (read) + .qs (clk_hints_clk_main_aes_hint_qs) + ); + + // F[clk_main_hmac_hint]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_clk_main_hmac_hint ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (clk_hints_we), + .wd (clk_hints_clk_main_hmac_hint_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.clk_hints.clk_main_hmac_hint.q), + .ds (), + + // to register interface (read) + .qs (clk_hints_clk_main_hmac_hint_qs) + ); + + // F[clk_main_kmac_hint]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_clk_main_kmac_hint ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (clk_hints_we), + .wd (clk_hints_clk_main_kmac_hint_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.clk_hints.clk_main_kmac_hint.q), + .ds (), + + // to register interface (read) + .qs (clk_hints_clk_main_kmac_hint_qs) + ); + + // F[clk_main_otbn_hint]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_clk_main_otbn_hint ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (clk_hints_we), + .wd (clk_hints_clk_main_otbn_hint_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.clk_hints.clk_main_otbn_hint.q), + .ds (), + + // to register interface (read) + .qs (clk_hints_clk_main_otbn_hint_qs) + ); + + + // R[clk_hints_status]: V(False) + // F[clk_main_aes_val]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_status_clk_main_aes_val ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.clk_hints_status.clk_main_aes_val.de), + .d (hw2reg.clk_hints_status.clk_main_aes_val.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (clk_hints_status_clk_main_aes_val_qs) + ); + + // F[clk_main_hmac_val]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_status_clk_main_hmac_val ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.clk_hints_status.clk_main_hmac_val.de), + .d (hw2reg.clk_hints_status.clk_main_hmac_val.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (clk_hints_status_clk_main_hmac_val_qs) + ); + + // F[clk_main_kmac_val]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_status_clk_main_kmac_val ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.clk_hints_status.clk_main_kmac_val.de), + .d (hw2reg.clk_hints_status.clk_main_kmac_val.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (clk_hints_status_clk_main_kmac_val_qs) + ); + + // F[clk_main_otbn_val]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_status_clk_main_otbn_val ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.clk_hints_status.clk_main_otbn_val.de), + .d (hw2reg.clk_hints_status.clk_main_otbn_val.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (clk_hints_status_clk_main_otbn_val_qs) + ); + + + // R[measure_ctrl_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_measure_ctrl_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (measure_ctrl_regwen_we), + .wd (measure_ctrl_regwen_wd), + + // from internal hardware + .de (hw2reg.measure_ctrl_regwen.de), + .d (hw2reg.measure_ctrl_regwen.d), + + // to internal hardware + .qe (), + .q (reg2hw.measure_ctrl_regwen.q), + .ds (), + + // to register interface (read) + .qs (measure_ctrl_regwen_qs) + ); + + + // R[io_div4_meas_ctrl_en]: V(False) + logic [0:0] io_div4_meas_ctrl_en_flds_we; + assign io_div4_io_div4_meas_ctrl_en_qe = |io_div4_meas_ctrl_en_flds_we; + // Create REGWEN-gated WE signal + logic io_div4_io_div4_meas_ctrl_en_gated_we; + assign io_div4_io_div4_meas_ctrl_en_gated_we = + io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_io_div4_meas_ctrl_en ( + .clk_i (clk_io_div4_i), + .rst_ni (rst_io_div4_ni), + + // from register interface + .we (io_div4_io_div4_meas_ctrl_en_gated_we), + .wd (io_div4_io_div4_meas_ctrl_en_wdata[3:0]), + + // from internal hardware + .de (hw2reg.io_div4_meas_ctrl_en.de), + .d (hw2reg.io_div4_meas_ctrl_en.d), + + // to internal hardware + .qe (io_div4_meas_ctrl_en_flds_we[0]), + .q (reg2hw.io_div4_meas_ctrl_en.q), + .ds (io_div4_io_div4_meas_ctrl_en_ds_int), + + // to register interface (read) + .qs (io_div4_io_div4_meas_ctrl_en_qs_int) + ); + + + // R[io_div4_meas_ctrl_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic io_div4_io_div4_meas_ctrl_shadowed_gated_we; + assign io_div4_io_div4_meas_ctrl_shadowed_gated_we = + io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen; + // F[hi]: 7:0 + logic async_io_div4_meas_ctrl_shadowed_hi_err_update; + logic async_io_div4_meas_ctrl_shadowed_hi_err_storage; + + // storage error is persistent and can be sampled at any time + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync ( + .clk_i, + .rst_ni, + .d_i(async_io_div4_meas_ctrl_shadowed_hi_err_storage), + .q_o(io_div4_meas_ctrl_shadowed_hi_storage_err) + ); + + // update error is transient and must be immediately captured + prim_pulse_sync u_io_div4_meas_ctrl_shadowed_hi_err_update_sync ( + .clk_src_i(clk_io_div4_i), + .rst_src_ni(rst_io_div4_ni), + .src_pulse_i(async_io_div4_meas_ctrl_shadowed_hi_err_update), + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .dst_pulse_o(io_div4_meas_ctrl_shadowed_hi_update_err) + ); + prim_subreg_shadow #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h82), + .Mubi (1'b0) + ) u_io_div4_meas_ctrl_shadowed_hi ( + .clk_i (clk_io_div4_i), + .rst_ni (rst_io_div4_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (io_div4_io_div4_meas_ctrl_shadowed_re), + .we (io_div4_io_div4_meas_ctrl_shadowed_gated_we), + .wd (io_div4_io_div4_meas_ctrl_shadowed_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.io_div4_meas_ctrl_shadowed.hi.q), + .ds (), + + // to register interface (read) + .qs (io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (async_io_div4_meas_ctrl_shadowed_hi_err_update), + .err_storage (async_io_div4_meas_ctrl_shadowed_hi_err_storage) + ); + + // F[lo]: 15:8 + logic async_io_div4_meas_ctrl_shadowed_lo_err_update; + logic async_io_div4_meas_ctrl_shadowed_lo_err_storage; + + // storage error is persistent and can be sampled at any time + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync ( + .clk_i, + .rst_ni, + .d_i(async_io_div4_meas_ctrl_shadowed_lo_err_storage), + .q_o(io_div4_meas_ctrl_shadowed_lo_storage_err) + ); + + // update error is transient and must be immediately captured + prim_pulse_sync u_io_div4_meas_ctrl_shadowed_lo_err_update_sync ( + .clk_src_i(clk_io_div4_i), + .rst_src_ni(rst_io_div4_ni), + .src_pulse_i(async_io_div4_meas_ctrl_shadowed_lo_err_update), + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .dst_pulse_o(io_div4_meas_ctrl_shadowed_lo_update_err) + ); + prim_subreg_shadow #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h6e), + .Mubi (1'b0) + ) u_io_div4_meas_ctrl_shadowed_lo ( + .clk_i (clk_io_div4_i), + .rst_ni (rst_io_div4_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (io_div4_io_div4_meas_ctrl_shadowed_re), + .we (io_div4_io_div4_meas_ctrl_shadowed_gated_we), + .wd (io_div4_io_div4_meas_ctrl_shadowed_wdata[15:8]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.io_div4_meas_ctrl_shadowed.lo.q), + .ds (), + + // to register interface (read) + .qs (io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (async_io_div4_meas_ctrl_shadowed_lo_err_update), + .err_storage (async_io_div4_meas_ctrl_shadowed_lo_err_storage) + ); + + + // R[main_meas_ctrl_en]: V(False) + logic [0:0] main_meas_ctrl_en_flds_we; + assign main_main_meas_ctrl_en_qe = |main_meas_ctrl_en_flds_we; + // Create REGWEN-gated WE signal + logic main_main_meas_ctrl_en_gated_we; + assign main_main_meas_ctrl_en_gated_we = + main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_main_meas_ctrl_en ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + + // from register interface + .we (main_main_meas_ctrl_en_gated_we), + .wd (main_main_meas_ctrl_en_wdata[3:0]), + + // from internal hardware + .de (hw2reg.main_meas_ctrl_en.de), + .d (hw2reg.main_meas_ctrl_en.d), + + // to internal hardware + .qe (main_meas_ctrl_en_flds_we[0]), + .q (reg2hw.main_meas_ctrl_en.q), + .ds (main_main_meas_ctrl_en_ds_int), + + // to register interface (read) + .qs (main_main_meas_ctrl_en_qs_int) + ); + + + // R[main_meas_ctrl_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic main_main_meas_ctrl_shadowed_gated_we; + assign main_main_meas_ctrl_shadowed_gated_we = + main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen; + // F[hi]: 9:0 + logic async_main_meas_ctrl_shadowed_hi_err_update; + logic async_main_meas_ctrl_shadowed_hi_err_storage; + + // storage error is persistent and can be sampled at any time + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_main_meas_ctrl_shadowed_hi_err_storage_sync ( + .clk_i, + .rst_ni, + .d_i(async_main_meas_ctrl_shadowed_hi_err_storage), + .q_o(main_meas_ctrl_shadowed_hi_storage_err) + ); + + // update error is transient and must be immediately captured + prim_pulse_sync u_main_meas_ctrl_shadowed_hi_err_update_sync ( + .clk_src_i(clk_main_i), + .rst_src_ni(rst_main_ni), + .src_pulse_i(async_main_meas_ctrl_shadowed_hi_err_update), + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .dst_pulse_o(main_meas_ctrl_shadowed_hi_update_err) + ); + prim_subreg_shadow #( + .DW (10), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (10'h1fe), + .Mubi (1'b0) + ) u_main_meas_ctrl_shadowed_hi ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (main_main_meas_ctrl_shadowed_re), + .we (main_main_meas_ctrl_shadowed_gated_we), + .wd (main_main_meas_ctrl_shadowed_wdata[9:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.main_meas_ctrl_shadowed.hi.q), + .ds (), + + // to register interface (read) + .qs (main_main_meas_ctrl_shadowed_hi_qs_int), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (async_main_meas_ctrl_shadowed_hi_err_update), + .err_storage (async_main_meas_ctrl_shadowed_hi_err_storage) + ); + + // F[lo]: 19:10 + logic async_main_meas_ctrl_shadowed_lo_err_update; + logic async_main_meas_ctrl_shadowed_lo_err_storage; + + // storage error is persistent and can be sampled at any time + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_main_meas_ctrl_shadowed_lo_err_storage_sync ( + .clk_i, + .rst_ni, + .d_i(async_main_meas_ctrl_shadowed_lo_err_storage), + .q_o(main_meas_ctrl_shadowed_lo_storage_err) + ); + + // update error is transient and must be immediately captured + prim_pulse_sync u_main_meas_ctrl_shadowed_lo_err_update_sync ( + .clk_src_i(clk_main_i), + .rst_src_ni(rst_main_ni), + .src_pulse_i(async_main_meas_ctrl_shadowed_lo_err_update), + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .dst_pulse_o(main_meas_ctrl_shadowed_lo_update_err) + ); + prim_subreg_shadow #( + .DW (10), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (10'h1ea), + .Mubi (1'b0) + ) u_main_meas_ctrl_shadowed_lo ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (main_main_meas_ctrl_shadowed_re), + .we (main_main_meas_ctrl_shadowed_gated_we), + .wd (main_main_meas_ctrl_shadowed_wdata[19:10]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.main_meas_ctrl_shadowed.lo.q), + .ds (), + + // to register interface (read) + .qs (main_main_meas_ctrl_shadowed_lo_qs_int), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (async_main_meas_ctrl_shadowed_lo_err_update), + .err_storage (async_main_meas_ctrl_shadowed_lo_err_storage) + ); + + + // R[usb_meas_ctrl_en]: V(False) + logic [0:0] usb_meas_ctrl_en_flds_we; + assign usb_usb_meas_ctrl_en_qe = |usb_meas_ctrl_en_flds_we; + // Create REGWEN-gated WE signal + logic usb_usb_meas_ctrl_en_gated_we; + assign usb_usb_meas_ctrl_en_gated_we = usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_usb_meas_ctrl_en ( + .clk_i (clk_usb_i), + .rst_ni (rst_usb_ni), + + // from register interface + .we (usb_usb_meas_ctrl_en_gated_we), + .wd (usb_usb_meas_ctrl_en_wdata[3:0]), + + // from internal hardware + .de (hw2reg.usb_meas_ctrl_en.de), + .d (hw2reg.usb_meas_ctrl_en.d), + + // to internal hardware + .qe (usb_meas_ctrl_en_flds_we[0]), + .q (reg2hw.usb_meas_ctrl_en.q), + .ds (usb_usb_meas_ctrl_en_ds_int), + + // to register interface (read) + .qs (usb_usb_meas_ctrl_en_qs_int) + ); + + + // R[usb_meas_ctrl_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic usb_usb_meas_ctrl_shadowed_gated_we; + assign usb_usb_meas_ctrl_shadowed_gated_we = + usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen; + // F[hi]: 8:0 + logic async_usb_meas_ctrl_shadowed_hi_err_update; + logic async_usb_meas_ctrl_shadowed_hi_err_storage; + + // storage error is persistent and can be sampled at any time + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_usb_meas_ctrl_shadowed_hi_err_storage_sync ( + .clk_i, + .rst_ni, + .d_i(async_usb_meas_ctrl_shadowed_hi_err_storage), + .q_o(usb_meas_ctrl_shadowed_hi_storage_err) + ); + + // update error is transient and must be immediately captured + prim_pulse_sync u_usb_meas_ctrl_shadowed_hi_err_update_sync ( + .clk_src_i(clk_usb_i), + .rst_src_ni(rst_usb_ni), + .src_pulse_i(async_usb_meas_ctrl_shadowed_hi_err_update), + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .dst_pulse_o(usb_meas_ctrl_shadowed_hi_update_err) + ); + prim_subreg_shadow #( + .DW (9), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (9'hfa), + .Mubi (1'b0) + ) u_usb_meas_ctrl_shadowed_hi ( + .clk_i (clk_usb_i), + .rst_ni (rst_usb_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (usb_usb_meas_ctrl_shadowed_re), + .we (usb_usb_meas_ctrl_shadowed_gated_we), + .wd (usb_usb_meas_ctrl_shadowed_wdata[8:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.usb_meas_ctrl_shadowed.hi.q), + .ds (), + + // to register interface (read) + .qs (usb_usb_meas_ctrl_shadowed_hi_qs_int), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (async_usb_meas_ctrl_shadowed_hi_err_update), + .err_storage (async_usb_meas_ctrl_shadowed_hi_err_storage) + ); + + // F[lo]: 17:9 + logic async_usb_meas_ctrl_shadowed_lo_err_update; + logic async_usb_meas_ctrl_shadowed_lo_err_storage; + + // storage error is persistent and can be sampled at any time + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_usb_meas_ctrl_shadowed_lo_err_storage_sync ( + .clk_i, + .rst_ni, + .d_i(async_usb_meas_ctrl_shadowed_lo_err_storage), + .q_o(usb_meas_ctrl_shadowed_lo_storage_err) + ); + + // update error is transient and must be immediately captured + prim_pulse_sync u_usb_meas_ctrl_shadowed_lo_err_update_sync ( + .clk_src_i(clk_usb_i), + .rst_src_ni(rst_usb_ni), + .src_pulse_i(async_usb_meas_ctrl_shadowed_lo_err_update), + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .dst_pulse_o(usb_meas_ctrl_shadowed_lo_update_err) + ); + prim_subreg_shadow #( + .DW (9), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (9'he6), + .Mubi (1'b0) + ) u_usb_meas_ctrl_shadowed_lo ( + .clk_i (clk_usb_i), + .rst_ni (rst_usb_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (usb_usb_meas_ctrl_shadowed_re), + .we (usb_usb_meas_ctrl_shadowed_gated_we), + .wd (usb_usb_meas_ctrl_shadowed_wdata[17:9]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.usb_meas_ctrl_shadowed.lo.q), + .ds (), + + // to register interface (read) + .qs (usb_usb_meas_ctrl_shadowed_lo_qs_int), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (async_usb_meas_ctrl_shadowed_lo_err_update), + .err_storage (async_usb_meas_ctrl_shadowed_lo_err_storage) + ); + + + // R[recov_err_code]: V(False) + // F[shadow_update_err]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_recov_err_code_shadow_update_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (recov_err_code_we), + .wd (recov_err_code_shadow_update_err_wd), + + // from internal hardware + .de (hw2reg.recov_err_code.shadow_update_err.de), + .d (hw2reg.recov_err_code.shadow_update_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (recov_err_code_shadow_update_err_qs) + ); + + // F[io_div4_measure_err]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_recov_err_code_io_div4_measure_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (recov_err_code_we), + .wd (recov_err_code_io_div4_measure_err_wd), + + // from internal hardware + .de (hw2reg.recov_err_code.io_div4_measure_err.de), + .d (hw2reg.recov_err_code.io_div4_measure_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (recov_err_code_io_div4_measure_err_qs) + ); + + // F[main_measure_err]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_recov_err_code_main_measure_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (recov_err_code_we), + .wd (recov_err_code_main_measure_err_wd), + + // from internal hardware + .de (hw2reg.recov_err_code.main_measure_err.de), + .d (hw2reg.recov_err_code.main_measure_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (recov_err_code_main_measure_err_qs) + ); + + // F[usb_measure_err]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_recov_err_code_usb_measure_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (recov_err_code_we), + .wd (recov_err_code_usb_measure_err_wd), + + // from internal hardware + .de (hw2reg.recov_err_code.usb_measure_err.de), + .d (hw2reg.recov_err_code.usb_measure_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (recov_err_code_usb_measure_err_qs) + ); + + // F[io_div4_timeout_err]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_recov_err_code_io_div4_timeout_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (recov_err_code_we), + .wd (recov_err_code_io_div4_timeout_err_wd), + + // from internal hardware + .de (hw2reg.recov_err_code.io_div4_timeout_err.de), + .d (hw2reg.recov_err_code.io_div4_timeout_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (recov_err_code_io_div4_timeout_err_qs) + ); + + // F[main_timeout_err]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_recov_err_code_main_timeout_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (recov_err_code_we), + .wd (recov_err_code_main_timeout_err_wd), + + // from internal hardware + .de (hw2reg.recov_err_code.main_timeout_err.de), + .d (hw2reg.recov_err_code.main_timeout_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (recov_err_code_main_timeout_err_qs) + ); + + // F[usb_timeout_err]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_recov_err_code_usb_timeout_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (recov_err_code_we), + .wd (recov_err_code_usb_timeout_err_wd), + + // from internal hardware + .de (hw2reg.recov_err_code.usb_timeout_err.de), + .d (hw2reg.recov_err_code.usb_timeout_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (recov_err_code_usb_timeout_err_qs) + ); + + + // R[fatal_err_code]: V(False) + // F[reg_intg]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_fatal_err_code_reg_intg ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.fatal_err_code.reg_intg.de), + .d (hw2reg.fatal_err_code.reg_intg.d), + + // to internal hardware + .qe (), + .q (reg2hw.fatal_err_code.reg_intg.q), + .ds (), + + // to register interface (read) + .qs (fatal_err_code_reg_intg_qs) + ); + + // F[idle_cnt]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_fatal_err_code_idle_cnt ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.fatal_err_code.idle_cnt.de), + .d (hw2reg.fatal_err_code.idle_cnt.d), + + // to internal hardware + .qe (), + .q (reg2hw.fatal_err_code.idle_cnt.q), + .ds (), + + // to register interface (read) + .qs (fatal_err_code_idle_cnt_qs) + ); + + // F[shadow_storage_err]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_fatal_err_code_shadow_storage_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.fatal_err_code.shadow_storage_err.de), + .d (hw2reg.fatal_err_code.shadow_storage_err.d), + + // to internal hardware + .qe (), + .q (reg2hw.fatal_err_code.shadow_storage_err.q), + .ds (), + + // to register interface (read) + .qs (fatal_err_code_shadow_storage_err_qs) + ); + + + + logic [17:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == CLKMGR_ALERT_TEST_OFFSET); + addr_hit[ 1] = (reg_addr == CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET); + addr_hit[ 2] = (reg_addr == CLKMGR_EXTCLK_CTRL_OFFSET); + addr_hit[ 3] = (reg_addr == CLKMGR_EXTCLK_STATUS_OFFSET); + addr_hit[ 4] = (reg_addr == CLKMGR_JITTER_REGWEN_OFFSET); + addr_hit[ 5] = (reg_addr == CLKMGR_JITTER_ENABLE_OFFSET); + addr_hit[ 6] = (reg_addr == CLKMGR_CLK_ENABLES_OFFSET); + addr_hit[ 7] = (reg_addr == CLKMGR_CLK_HINTS_OFFSET); + addr_hit[ 8] = (reg_addr == CLKMGR_CLK_HINTS_STATUS_OFFSET); + addr_hit[ 9] = (reg_addr == CLKMGR_MEASURE_CTRL_REGWEN_OFFSET); + addr_hit[10] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET); + addr_hit[11] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[12] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET); + addr_hit[13] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[14] = (reg_addr == CLKMGR_USB_MEAS_CTRL_EN_OFFSET); + addr_hit[15] = (reg_addr == CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[16] = (reg_addr == CLKMGR_RECOV_ERR_CODE_OFFSET); + addr_hit[17] = (reg_addr == CLKMGR_FATAL_ERR_CODE_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(CLKMGR_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(CLKMGR_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(CLKMGR_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(CLKMGR_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(CLKMGR_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(CLKMGR_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(CLKMGR_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(CLKMGR_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(CLKMGR_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(CLKMGR_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(CLKMGR_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(CLKMGR_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(CLKMGR_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(CLKMGR_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(CLKMGR_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(CLKMGR_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(CLKMGR_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(CLKMGR_PERMIT[17] & ~reg_be))))); + end + + // Generate write-enables + assign alert_test_we = addr_hit[0] & reg_we & !reg_error; + + assign alert_test_recov_fault_wd = reg_wdata[0]; + + assign alert_test_fatal_fault_wd = reg_wdata[1]; + assign extclk_ctrl_regwen_we = addr_hit[1] & reg_we & !reg_error; + + assign extclk_ctrl_regwen_wd = reg_wdata[0]; + assign extclk_ctrl_we = addr_hit[2] & reg_we & !reg_error; + + assign extclk_ctrl_sel_wd = reg_wdata[3:0]; + + assign extclk_ctrl_hi_speed_sel_wd = reg_wdata[7:4]; + assign extclk_status_re = addr_hit[3] & reg_re & !reg_error; + assign jitter_regwen_we = addr_hit[4] & reg_we & !reg_error; + + assign jitter_regwen_wd = reg_wdata[0]; + assign jitter_enable_we = addr_hit[5] & reg_we & !reg_error; + + assign jitter_enable_wd = reg_wdata[3:0]; + assign clk_enables_we = addr_hit[6] & reg_we & !reg_error; + + assign clk_enables_clk_io_div4_peri_en_wd = reg_wdata[0]; + + assign clk_enables_clk_io_div2_peri_en_wd = reg_wdata[1]; + + assign clk_enables_clk_usb_peri_en_wd = reg_wdata[2]; + assign clk_hints_we = addr_hit[7] & reg_we & !reg_error; + + assign clk_hints_clk_main_aes_hint_wd = reg_wdata[0]; + + assign clk_hints_clk_main_hmac_hint_wd = reg_wdata[1]; + + assign clk_hints_clk_main_kmac_hint_wd = reg_wdata[2]; + + assign clk_hints_clk_main_otbn_hint_wd = reg_wdata[3]; + assign measure_ctrl_regwen_we = addr_hit[9] & reg_we & !reg_error; + + assign measure_ctrl_regwen_wd = reg_wdata[0]; + assign io_div4_meas_ctrl_en_we = addr_hit[10] & reg_we & !reg_error; + + assign io_div4_meas_ctrl_shadowed_re = addr_hit[11] & reg_re & !reg_error; + assign io_div4_meas_ctrl_shadowed_we = addr_hit[11] & reg_we & !reg_error; + + + assign main_meas_ctrl_en_we = addr_hit[12] & reg_we & !reg_error; + + assign main_meas_ctrl_shadowed_re = addr_hit[13] & reg_re & !reg_error; + assign main_meas_ctrl_shadowed_we = addr_hit[13] & reg_we & !reg_error; + + + assign usb_meas_ctrl_en_we = addr_hit[14] & reg_we & !reg_error; + + assign usb_meas_ctrl_shadowed_re = addr_hit[15] & reg_re & !reg_error; + assign usb_meas_ctrl_shadowed_we = addr_hit[15] & reg_we & !reg_error; + + + assign recov_err_code_we = addr_hit[16] & reg_we & !reg_error; + + assign recov_err_code_shadow_update_err_wd = reg_wdata[0]; + + assign recov_err_code_io_div4_measure_err_wd = reg_wdata[1]; + + assign recov_err_code_main_measure_err_wd = reg_wdata[2]; + + assign recov_err_code_usb_measure_err_wd = reg_wdata[3]; + + assign recov_err_code_io_div4_timeout_err_wd = reg_wdata[4]; + + assign recov_err_code_main_timeout_err_wd = reg_wdata[5]; + + assign recov_err_code_usb_timeout_err_wd = reg_wdata[6]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check = '0; + reg_we_check[0] = alert_test_we; + reg_we_check[1] = extclk_ctrl_regwen_we; + reg_we_check[2] = extclk_ctrl_gated_we; + reg_we_check[3] = 1'b0; + reg_we_check[4] = jitter_regwen_we; + reg_we_check[5] = jitter_enable_we; + reg_we_check[6] = clk_enables_we; + reg_we_check[7] = clk_hints_we; + reg_we_check[8] = 1'b0; + reg_we_check[9] = measure_ctrl_regwen_we; + reg_we_check[10] = io_div4_meas_ctrl_en_we; + reg_we_check[11] = io_div4_meas_ctrl_shadowed_we; + reg_we_check[12] = main_meas_ctrl_en_we; + reg_we_check[13] = main_meas_ctrl_shadowed_we; + reg_we_check[14] = usb_meas_ctrl_en_we; + reg_we_check[15] = usb_meas_ctrl_shadowed_we; + reg_we_check[16] = recov_err_code_we; + reg_we_check[17] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + addr_hit[1]: begin + reg_rdata_next[0] = extclk_ctrl_regwen_qs; + end + + addr_hit[2]: begin + reg_rdata_next[3:0] = extclk_ctrl_sel_qs; + reg_rdata_next[7:4] = extclk_ctrl_hi_speed_sel_qs; + end + + addr_hit[3]: begin + reg_rdata_next[3:0] = extclk_status_qs; + end + + addr_hit[4]: begin + reg_rdata_next[0] = jitter_regwen_qs; + end + + addr_hit[5]: begin + reg_rdata_next[3:0] = jitter_enable_qs; + end + + addr_hit[6]: begin + reg_rdata_next[0] = clk_enables_clk_io_div4_peri_en_qs; + reg_rdata_next[1] = clk_enables_clk_io_div2_peri_en_qs; + reg_rdata_next[2] = clk_enables_clk_usb_peri_en_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs; + reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs; + reg_rdata_next[2] = clk_hints_clk_main_kmac_hint_qs; + reg_rdata_next[3] = clk_hints_clk_main_otbn_hint_qs; + end + + addr_hit[8]: begin + reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs; + reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs; + reg_rdata_next[2] = clk_hints_status_clk_main_kmac_val_qs; + reg_rdata_next[3] = clk_hints_status_clk_main_otbn_val_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = measure_ctrl_regwen_qs; + end + + addr_hit[10]: begin + reg_rdata_next = DW'(io_div4_meas_ctrl_en_qs); + end + addr_hit[11]: begin + reg_rdata_next = DW'(io_div4_meas_ctrl_shadowed_qs); + end + addr_hit[12]: begin + reg_rdata_next = DW'(main_meas_ctrl_en_qs); + end + addr_hit[13]: begin + reg_rdata_next = DW'(main_meas_ctrl_shadowed_qs); + end + addr_hit[14]: begin + reg_rdata_next = DW'(usb_meas_ctrl_en_qs); + end + addr_hit[15]: begin + reg_rdata_next = DW'(usb_meas_ctrl_shadowed_qs); + end + addr_hit[16]: begin + reg_rdata_next[0] = recov_err_code_shadow_update_err_qs; + reg_rdata_next[1] = recov_err_code_io_div4_measure_err_qs; + reg_rdata_next[2] = recov_err_code_main_measure_err_qs; + reg_rdata_next[3] = recov_err_code_usb_measure_err_qs; + reg_rdata_next[4] = recov_err_code_io_div4_timeout_err_qs; + reg_rdata_next[5] = recov_err_code_main_timeout_err_qs; + reg_rdata_next[6] = recov_err_code_usb_timeout_err_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = fatal_err_code_reg_intg_qs; + reg_rdata_next[1] = fatal_err_code_idle_cnt_qs; + reg_rdata_next[2] = fatal_err_code_shadow_storage_err_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + logic rst_done; + logic shadow_rst_done; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rst_done <= '0; + end else begin + rst_done <= 1'b1; + end + end + + always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin + if (!rst_shadowed_ni) begin + shadow_rst_done <= '0; + end else begin + shadow_rst_done <= 1'b1; + end + end + + // both shadow and normal resets have been released + assign shadow_busy = ~(rst_done & shadow_rst_done); + + // Collect up storage and update errors + assign shadowed_storage_err_o = |{ + io_div4_meas_ctrl_shadowed_hi_storage_err, + io_div4_meas_ctrl_shadowed_lo_storage_err, + main_meas_ctrl_shadowed_hi_storage_err, + main_meas_ctrl_shadowed_lo_storage_err, + usb_meas_ctrl_shadowed_hi_storage_err, + usb_meas_ctrl_shadowed_lo_storage_err + }; + assign shadowed_update_err_o = |{ + io_div4_meas_ctrl_shadowed_hi_update_err, + io_div4_meas_ctrl_shadowed_lo_update_err, + main_meas_ctrl_shadowed_hi_update_err, + main_meas_ctrl_shadowed_lo_update_err, + usb_meas_ctrl_shadowed_hi_update_err, + usb_meas_ctrl_shadowed_lo_update_err + }; + + // register busy + logic reg_busy_sel; + assign reg_busy = reg_busy_sel | shadow_busy; + always_comb begin + reg_busy_sel = '0; + unique case (1'b1) + addr_hit[10]: begin + reg_busy_sel = io_div4_meas_ctrl_en_busy; + end + addr_hit[11]: begin + reg_busy_sel = io_div4_meas_ctrl_shadowed_busy; + end + addr_hit[12]: begin + reg_busy_sel = main_meas_ctrl_en_busy; + end + addr_hit[13]: begin + reg_busy_sel = main_meas_ctrl_shadowed_busy; + end + addr_hit[14]: begin + reg_busy_sel = usb_meas_ctrl_en_busy; + end + addr_hit[15]: begin + reg_busy_sel = usb_meas_ctrl_shadowed_busy; + end + default: begin + reg_busy_sel = '0; + end + endcase + end + + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_root_ctrl.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_root_ctrl.sv new file mode 100644 index 0000000000000..3008d2b24aa9e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_root_ctrl.sv @@ -0,0 +1,41 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Wrapper for scan sync and clock gating cell + +module clkmgr_root_ctrl + import clkmgr_pkg::*; + import prim_mubi_pkg::mubi4_t; +( + input clk_i, + input rst_ni, + + input mubi4_t scanmode_i, + input async_en_i, + + output logic en_o, + output logic clk_o +); + + mubi4_t scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) // clock/reset below is only used for SVAs. + ) u_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o({scanmode}) + ); + + prim_clock_gating_sync u_cg ( + .clk_i, + .rst_ni, + .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(scanmode)), + .async_en_i, + .en_o, + .clk_o + ); + +endmodule // clkmgr_root_ctrl diff --git a/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_trans.sv b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_trans.sv new file mode 100644 index 0000000000000..80c6aa2164256 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/clkmgr/rtl/clkmgr_trans.sv @@ -0,0 +1,175 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Handle clock manager transactional clocks + +module clkmgr_trans + import clkmgr_pkg::*; + import prim_mubi_pkg::mubi4_t; +# ( + parameter bit FpgaBufGlobal = 1 +) ( + input clk_i, + input clk_gated_i, + input rst_ni, + input en_i, + input mubi4_t idle_i, + input sw_hint_i, + input mubi4_t scanmode_i, + output mubi4_t alert_cg_en_o, + output logic clk_o, + + // interface to regfile + input clk_reg_i, + input rst_reg_ni, + output logic reg_en_o, + output logic reg_cnt_err_o +); + + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4True; + import prim_mubi_pkg::mubi4_test_true_strict; + import prim_mubi_pkg::mubi4_test_false_loose; + + // Note this value is specifically chosen. + // The binary value is 1010, which is a balanced 4-bit value + // that should in theory be resistant to all 0 or all 1 attacks. + localparam int unsigned TransIdleCnt = 10; + localparam int IdleCntWidth = $clog2(TransIdleCnt + 1); + + logic [IdleCntWidth-1:0] idle_cnt; + logic idle_valid; + logic sw_hint_synced; + logic local_en; + assign idle_valid = (idle_cnt == IdleCntWidth'(TransIdleCnt)); + assign local_en = sw_hint_synced | ~idle_valid; + + prim_flop_2sync #( + .Width(1) + ) u_hint_sync ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(sw_hint_i), + .q_o(sw_hint_synced) + ); + + // Idle sync: Idle signal comes from IP module. The reset of the Idle signal + // may differ from the reset here. Adding mubi sync to synchronize. + prim_mubi_pkg::mubi4_t [0:0] idle; + prim_mubi4_sync #( + .NumCopies ( 1 ), + .AsyncOn ( 1'b 1 ), + .StabilityCheck ( 1'b 1 ) + ) u_idle_sync ( + .clk_i, + .rst_ni, + .mubi_i (idle_i), + .mubi_o (idle) + ); + + // SEC_CM: IDLE.CTR.REDUN + logic cnt_err; + prim_count #( + .Width(IdleCntWidth) + ) u_idle_cnt ( + .clk_i(clk_i), + .rst_ni(rst_ni), + // the default condition is to keep the clock enabled + .clr_i(mubi4_test_false_loose(idle[0])), + .set_i('0), + .set_cnt_i('0), + .incr_en_i(mubi4_test_true_strict(idle[0]) & ~idle_valid), + .decr_en_i(1'b0), + .step_i(IdleCntWidth'(1'b1)), + .commit_i(1'b1), + .cnt_o(idle_cnt), + .cnt_after_commit_o(), + .err_o(cnt_err) + ); + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o(scanmode) + ); + + // Add a prim buf here to make sure the CG and the lc sender inputs + // are derived from the same physical signal. + logic combined_en_d, combined_en_q; + prim_buf u_prim_buf_en ( + .in_i(local_en & en_i), + .out_o(combined_en_d) + ); + + // clk_gated_i is already controlled by en_i, so there is no need + // to use it in the below gating function + prim_clock_gating #( + .FpgaBufGlobal(FpgaBufGlobal) + ) u_cg ( + .clk_i(clk_gated_i), + .en_i(local_en), + .test_en_i(mubi4_test_true_strict(scanmode[0])), + .clk_o(clk_o) + ); + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .mubi_i(combined_en_d ? MuBi4False : MuBi4True), + .mubi_o(alert_cg_en_o) + ); + + // we hold the error because there is no guarantee on + // what the timing of cnt_err looks like, it may be a + // pulse or it may be level. If it's for former, + // prim_sync_reqack may miss it, if it's the latter, + // prim_pulse_sync may miss it. As a result, just + // latch forever and sync it over. + logic hold_err; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + hold_err <= '0; + end else if (cnt_err) begin + hold_err <= 1'b1; + end + end + + // register facing domain + prim_flop_2sync #( + .Width(1) + ) u_err_sync ( + .clk_i(clk_reg_i), + .rst_ni(rst_reg_ni), + .d_i(hold_err), + .q_o(reg_cnt_err_o) + ); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + combined_en_q <= '0; + end else begin + combined_en_q <= combined_en_d; + end + end + + prim_flop_2sync #( + .Width(1) + ) u_en_sync ( + .clk_i(clk_reg_i), + .rst_ni(rst_reg_ni), + .d_i(combined_en_q), + .q_o(reg_en_o) + ); + + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/pinmux/BUILD b/hw/top_darjeeling/ip_autogen/pinmux/BUILD new file mode 100644 index 0000000000000..5a99add16588c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/BUILD @@ -0,0 +1,30 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +load( + "//rules:autogen.bzl", + "autogen_hjson_c_header", + "autogen_hjson_rust_header", +) + +autogen_hjson_c_header( + name = "pinmux_c_regs", + srcs = [ + "data/pinmux.hjson", + ], +) + +autogen_hjson_rust_header( + name = "pinmux_rust_regs", + srcs = [ + "data/pinmux.hjson", + ], +) + +filegroup( + name = "all_files", + srcs = glob(["**"]), +) diff --git a/hw/top_darjeeling/ip_autogen/pinmux/README.md b/hw/top_darjeeling/ip_autogen/pinmux/README.md new file mode 100644 index 0000000000000..d247e97a2c295 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/README.md @@ -0,0 +1,29 @@ +# Pinmux Technical Specification + + +# Overview + +This document specifies the functionality of the pin multiplexer (`pinmux`) peripheral. +This module conforms to the [OpenTitan guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability). +See that document for integration overview within the broader OpenTitan top level system. +The module provides a mechanism to reconfigure the peripheral-to-pin mapping at runtime, which greatly enhances the system flexibility. +In addition to that, the `pinmux` also allows the user to control pad attributes (such as pull-up, pull-down, open-drain, drive-strength, keeper and inversion), and it contains features that facilitate low-power modes of the system. +For example, the sleep behavior of each pad can be programmed individually, and the module contains additional pattern detectors that can listen on any IO and wake up the system if a specific pattern has been detected. + +## Features + +- Configurable number of chip bidirectional IOs + +- Configurable number of peripheral inputs and outputs + +- Programmable mapping from peripheral outputs (and output enables) to top-level outputs (and output enables) + +- Programmable mapping from top-level inputs to peripheral inputs + +- Programmable control of chip pad attributes like output drive-strength, pull-up, pull-down and virtual open-drain + +- Programmable pattern detectors to detect wakeup conditions during sleep mode + +- Programmable sleep mode behavior + +- Support for life-cycle-based JTAG (TAP) isolation and muxing diff --git a/hw/top_darjeeling/ip_autogen/pinmux/data/pinmux.hjson b/hw/top_darjeeling/ip_autogen/pinmux/data/pinmux.hjson new file mode 100644 index 0000000000000..0ea4635b13953 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/data/pinmux.hjson @@ -0,0 +1,1127 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +{ + name: "pinmux", + human_name: "Pin Multiplexer", + one_line_desc: "Multiplexes between on-chip hardware blocks and pins, and can be configured at runtime", + one_paragraph_desc: ''' + Pin Multiplexer connects on-chip hardware blocks to IC pins and controls the attributes of the pin drivers (such as pull-up/down, open-drain, and drive strength). + Large parts of its functionality can be controlled by software through registers. + Further features include per-pin programmable sleep behavior and wakeup pattern detectors as well as support for life-cycle-based JTAG (TAP) isolation and muxing. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "18", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_pinmux", + version: "1.1.0", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + notes: "Use FPV to perform block level verification.", + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {clock: "clk_aon_i", reset: "rst_aon_ni"}, + {reset: "rst_sys_ni"} + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device" } + ], + regwidth: "32", + scan: "true", + + alert_list: [ + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. + ''' + } + ], + + wakeup_list: [ + { name: "pin_wkup_req", + desc: "pin wake request" + }, + { name: "usb_wkup_req", + desc: "usb wake request" + }, + ], + + inter_signal_list: [ + // Life cycle inputs + { struct: "lc_tx" + type: "uni" + name: "lc_hw_debug_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg", + desc: ''' + Debug enable qualifier coming from life cycle controller, used for HW strap qualification. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_dft_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg", + desc: ''' + Test enable qualifier coming from life cycle controller, used for HW strap qualification. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_escalate_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg", + desc: ''' + Escalation enable signal coming from life cycle controller, used for invalidating + the latched lc_hw_debug_en state inside the strap sampling logic. + ''',} + + { struct: "lc_tx" + type: "uni" + name: "lc_check_byp_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg", + desc: ''' + Check bypass enable signal coming from life cycle controller, used for invalidating + the latched lc_hw_debug_en state inside the strap sampling logic. This signal is asserted + whenever the life cycle controller performs a life cycle transition. Its main use is + to skip any background checks inside the life cycle partition of the OTP controller while + a life cycle transition is in progress. + ''',} + + { struct: "lc_tx" + type: "uni" + name: "pinmux_hw_debug_en" + act: "req" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg", + desc: ''' + This is the latched version of lc_hw_debug_en_i. We use it exclusively to gate the JTAG + signals and TAP side of the RV_DM so that RV_DM can remain live during an NDM reset cycle. + ''',} + + // JTAG TAPs + { struct: "jtag" + type: "req_rsp" + name: "lc_jtag" + act: "req" + package: "jtag_pkg" + desc: ''' + Qualified JTAG signals for life cycle controller TAP. + ''',} + + { struct: "jtag" + type: "req_rsp" + name: "rv_jtag" + act: "req" + package: "jtag_pkg" + desc: ''' + Qualified JTAG signals for RISC-V processor TAP. + ''',} + + { struct: "jtag" + type: "req_rsp" + name: "dft_jtag" + act: "req" + package: "jtag_pkg" + desc: ''' + Qualified JTAG signals for DFT TAP. + ''',} + + // Testmode signals to AST + { struct: "dft_strap_test_req", + type: "uni", + name: "dft_strap_test", + act: "req", + package: "pinmux_pkg", + desc: ''' + Sampled DFT strap values, going to the DFT TAP. + ''', + default: "'0" + } + // DFT indication to stop tap strap sampling + { struct: "logic", + type: "uni", + name: "dft_hold_tap_sel", + act: "rcv", + package: "", + desc: ''' + TAP selection hold indication, asserted by the DFT TAP during boundary scan. + ''', + default: "'0" + } + // Define pwr mgr <-> pinmux signals + { struct: "logic", + type: "uni", + name: "sleep_en", + act: "rcv", + package: "", + desc: ''' + Level signal that is asserted when the power manager enters sleep. + ''', + default: "1'b0" + }, + { struct: "logic", + type: "uni", + name: "strap_en", + act: "rcv", + package: "", + desc: ''' + This signal is pulsed high by the power manager after reset in order to sample the HW straps. + ''', + default: "1'b0" + }, + { struct: "logic", + type: "uni", + name: "strap_en_override", + act: "rcv", + desc: ''' + This signal transitions from 0 -> 1 by the lc_ctrl manager after volatile RAW_UNLOCK in order to re-sample the HW straps. + The signal must stay at 1 until reset. + Note that this is only used in test chips when SecVolatileRawUnlockEn = 1. + Otherwise this signal is unused. + ''', + default: "1'b0" + }, + { struct: "logic", + type: "uni", + name: "pin_wkup_req", + act: "req", + package: "", + desc: ''' + Wakeup request from wakeup detectors, to the power manager, running on the AON clock. + ''', + default: "1'b0" + }, + { name: "usbdev_dppullup_en", + type: "uni", + act: "rcv", + package: "", + desc: ''' + Pullup enable signal coming from the USB IP. + ''', + struct: "logic", + width: "1" + }, + { name: "usbdev_dnpullup_en", + type: "uni", + act: "rcv", + package: "", + desc: ''' + Pullup enable signal coming from the USB IP. + ''', + struct: "logic", + width: "1" + }, + { name: "usb_dppullup_en", + type: "uni", + act: "req", + package: "", + desc: ''' + Pullup enable signal going to USB PHY, needs to be maintained in low-power mode. + ''', + struct: "logic", + width: "1" + default: "1'b0" + }, + { name: "usb_dnpullup_en", + type: "uni", + act: "req", + package: "", + desc: ''' + Pullup enable signal going to USB PHY, needs to be maintained in low-power mode. + ''', + struct: "logic", + width: "1" + default: "1'b0" + }, + { struct: "logic", + type: "uni", + name: "usb_wkup_req", + act: "req", + package: "", + desc: ''' + Wakeup request from USB wakeup detector, going to the power manager, running on the AON clock. + ''', + default: "1'b0" + }, + { name: "usbdev_suspend_req", + type: "uni", + act: "rcv", + package: "", + desc: ''' + Indicates whether USB is in suspended state, coming from the USB device. + ''', + struct: "logic", + width: "1" + }, + { name: "usbdev_wake_ack", + type: "uni", + act: "rcv", + package: "", + desc: ''' + Acknowledges the USB wakeup request, coming from the USB device. + ''', + struct: "logic", + width: "1" + }, + { name: "usbdev_bus_not_idle", + type: "uni", + act: "req", + package: "", + desc: ''' + Event signal that indicates that the USB was not idle while monitoring. + ''', + struct: "logic", + width: "1", + default: "1'b0" + }, + { name: "usbdev_bus_reset", + type: "uni", + act: "req", + package: "", + desc: ''' + Event signal that indicates that the USB issued a Bus Reset while monitoring. + ''', + struct: "logic", + width: "1", + default: "1'b0" + }, + { name: "usbdev_sense_lost", + type: "uni", + act: "req", + package: "", + desc: ''' + Event signal that indicates that USB SENSE signal was lost while monitoring. + ''', + struct: "logic", + width: "1", + default: "1'b0" + }, + { name: "usbdev_wake_detect_active", + type: "uni", + act: "req", + package: "", + desc: ''' + State debug information. + ''', + struct: "logic", + width: 1, + default: "1'b0" + }, + ] + + param_list: [ + // Secure parameters + { name: "SecVolatileRawUnlockEn", + type: "bit", + default: "1'b0", + desc: ''' + Disable (0) or enable (1) volatile RAW UNLOCK capability. + If enabled, the strap_en_override_i input can be used to re-sample the straps at runtime. + + IMPORTANT NOTE: This should only be used in test chips. The parameter must be set + to 0 in production tapeouts since this weakens the security posture of the RAW + UNLOCK mechanism. + ''' + local: "false", + expose: "true" + }, + { name: "NMioPeriphIn", + desc: "Number of muxed peripheral inputs", + type: "int", + default: "4", + local: "true" + }, + { name: "NMioPeriphOut", + desc: "Number of muxed peripheral outputs", + type: "int", + default: "5", + local: "true" + }, + { name: "NMioPads", + desc: "Number of muxed IO pads", + type: "int", + default: "12", + local: "true" + }, + { name: "NDioPads", + desc: "Number of dedicated IO pads", + type: "int", + default: "73", + local: "true" + }, + { name: "NWkupDetect", + desc: "Number of wakeup detectors", + type: "int", + default: "8", + local: "true" + }, + { name: "WkupCntWidth", + desc: "Number of wakeup counter bits", + type: "int", + default: "8", + local: "true" + }, + // Since the target-specific top-levels often have slightly + // different debug signal positions, we need a way to pass + // this info from the target specific top-level into the pinmux + // logic. The parameter struct below serves this purpose. + { name: "TargetCfg", + desc: "Target specific pinmux configuration.", + type: "pinmux_pkg::target_cfg_t", + default: "pinmux_pkg::DefaultTargetCfg", + local: "false", + expose: "true" + }, + ], + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + ] + + registers: [ +////////////////////////// +// MIO Inputs // +////////////////////////// + { multireg: { name: "MIO_PERIPH_INSEL_REGWEN", + desc: "Register write enable for MIO peripheral input selects.", + count: "NMioPeriphIn", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "MIO_PERIPH_INSEL", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding MIO_PERIPH_INSEL + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "MIO_PERIPH_INSEL", + desc: "For each peripheral input, this selects the muxable pad input.", + count: "NMioPeriphIn", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "MIO_PERIPH_INSEL_REGWEN", + regwen_multi: "true", + cname: "IN", + fields: [ + { bits: "3:0", + name: "IN", + desc: ''' + 0: tie constantly to zero, 1: tie constantly to 1, + >=2: MIO pads (i.e., add 2 to the native MIO pad index). + ''' + resval: 0, + } + ] + } + }, + +////////////////////////// +// MIO Outputs // +////////////////////////// + { multireg: { name: "MIO_OUTSEL_REGWEN", + desc: "Register write enable for MIO output selects.", + count: "NMioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "MIO_OUTSEL", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding MIO_OUTSEL + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "MIO_OUTSEL", + desc: "For each muxable pad, this selects the peripheral output.", + count: "NMioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "MIO_OUTSEL_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "2:0", + name: "OUT", + desc: ''' + 0: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, + >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index). + ''' + resval: 2, + } + ] + // Random writes to this field may result in pad drive conflicts, + // which in turn leads to propagating Xes and assertion failures. + tags: ["excl:CsrAllTests:CsrExclWrite"] + } + }, + +////////////////////////// +// MIO PAD attributes // +////////////////////////// + { multireg: { name: "MIO_PAD_ATTR_REGWEN", + desc: "Register write enable for MIO PAD attributes.", + count: "NMioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "MIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!MIO_PAD_ATTR + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "MIO_PAD_ATTR", + desc: ''' + Muxed pad attributes. + This register has WARL behavior since not each pad type may support + all attributes. + The muxed pad that is used for TAP strap 0 has a different reset value, with `pull_en` set to 1. + ''', + count: "NMioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + regwen: "MIO_PAD_ATTR_REGWEN", + regwen_multi: "true", + cname: "MIO_PAD", + resval: 0 + fields: [ + { bits: "0", + name: "invert", + desc: "Invert input and output levels." + }, + { bits: "1", + name: "virtual_od_en", + desc: "Enable virtual open drain." + }, + { bits: "2", + name: "pull_en", + desc: "Enable pull-up or pull-down resistor." + }, + { bits: "3", + name: "pull_select", + desc: "Pull select (0: pull-down, 1: pull-up)." + enum: [ + { value: "0", + name: "pull_down", + desc: "Select the pull-down resistor." + }, + { value: "1", + name: "pull_up", + desc: "Select the pull-up resistor." + } + ] + }, + { bits: "4", + name: "keeper_en", + desc: "Enable keeper termination. This weakly drives the previous pad output value when output is disabled, similar to a verilog `trireg`." + }, + { bits: "5", + name: "schmitt_en", + desc: "Enable the schmitt trigger." + }, + { bits: "6", + name: "od_en", + desc: "Enable open drain." + }, + { bits: "7", + name: "input_disable", + desc: ''' + Disable input drivers. + Setting this to 1 for pads that are not used as input can reduce their leakage current. + ''' + }, + { bits: "17:16", + name: "slew_rate", + desc: "Slew rate (0x0: slowest, 0x3: fastest)." + }, + { bits: "23:20", + name: "drive_strength", + desc: "Drive strength (0x0: weakest, 0xf: strongest)" + } + ], + // these CSRs have WARL behavior and may not + // read back the same value that was written to them. + // further, they have hardware side effects since they drive the + // pad attributes, and hence no random data should be written to them. + // Additionally, their reset value is defined by the RTL implementation and may not equal `resval` for all instances (#24621). + tags: ["excl:CsrAllTests:CsrExclAll"] + } + }, + +////////////////////////// +// DIO PAD attributes // +////////////////////////// + { multireg: { name: "DIO_PAD_ATTR_REGWEN", + desc: "Register write enable for DIO PAD attributes.", + count: "NDioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "DIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!DIO_PAD_ATTR + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "DIO_PAD_ATTR", + desc: ''' + Dedicated pad attributes. + This register has WARL behavior since not each pad type may support + all attributes. + ''', + count: "NDioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + regwen: "DIO_PAD_ATTR_REGWEN", + regwen_multi: "true", + cname: "DIO_PAD", + resval: 0, + fields: [ + { bits: "0", + name: "invert", + desc: "Invert input and output levels." + }, + { bits: "1", + name: "virtual_od_en", + desc: "Enable virtual open drain." + }, + { bits: "2", + name: "pull_en", + desc: "Enable pull-up or pull-down resistor." + }, + { bits: "3", + name: "pull_select", + desc: "Pull select (0: pull-down, 1: pull-up)." + enum: [ + { value: "0", + name: "pull_down", + desc: "Select the pull-down resistor." + }, + { value: "1", + name: "pull_up", + desc: "Select the pull-up resistor." + } + ] + }, + { bits: "4", + name: "keeper_en", + desc: "Enable keeper termination. This weakly drives the previous pad output value when output is disabled, similar to a verilog `trireg`." + }, + { bits: "5", + name: "schmitt_en", + desc: "Enable the schmitt trigger." + }, + { bits: "6", + name: "od_en", + desc: "Enable open drain." + }, + { bits: "7", + name: "input_disable", + desc: ''' + Disable input drivers. + Setting this to 1 for pads that are not used as input can reduce their leakage current. + ''' + }, + { bits: "17:16", + name: "slew_rate", + desc: "Slew rate (0x0: slowest, 0x3: fastest)." + }, + { bits: "23:20", + name: "drive_strength", + desc: "Drive strength (0x0: weakest, 0xf: strongest)" + } + ], + // these CSRs have WARL behavior and may not + // read back the same value that was written to them. + // further, they have hardware side effects since they drive the + // pad attributes, and hence no random data should be written to them. + tags: ["excl:CsrAllTests:CsrExclWrite"] + } + }, + +////////////////////////// +// MIO PAD sleep mode // +////////////////////////// + { multireg: { name: "MIO_PAD_SLEEP_STATUS", + desc: "Register indicating whether the corresponding pad is in sleep mode.", + count: "NMioPads", + swaccess: "rw0c", + hwaccess: "hrw", + cname: "MIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + This register is set to 1 if the deep sleep mode of the corresponding + pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. + The sleep mode of the corresponding pad will remain active until SW + clears this bit. + ''', + resval: "0", + } + ] + } + }, + { multireg: { name: "MIO_PAD_SLEEP_REGWEN", + desc: "Register write enable for MIO sleep value configuration.", + count: "NMioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "MIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!MIO_PAD_SLEEP_MODE + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "MIO_PAD_SLEEP_EN", + desc: '''Enables the sleep mode of the corresponding muxed pad. + ''' + count: "NMioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "MIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "0", + name: "EN", + resval: 0, + desc: ''' + Deep sleep mode enable. + If this bit is set to 1 the corresponding pad will enable the sleep behavior + specified in !!MIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit + in !!MIO_PAD_SLEEP_STATUS will be set to 1. + The pad remains in deep sleep mode until the corresponding bit in + !!MIO_PAD_SLEEP_STATUS is cleared by SW. + Note that if an always on peripheral is connected to a specific MIO pad, + the corresponding !!MIO_PAD_SLEEP_EN bit should be set to 0. + ''' + } + ] + } + }, + { multireg: { name: "MIO_PAD_SLEEP_MODE", + desc: '''Defines sleep behavior of the corresponding muxed pad. + ''' + count: "NMioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "MIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "1:0", + name: "OUT", + resval: 2, + desc: "Value to drive in deep sleep." + enum: [ + { value: "0", + name: "Tie-Low", + desc: "The pad is driven actively to zero in deep sleep mode." + }, + { value: "1", + name: "Tie-High", + desc: "The pad is driven actively to one in deep sleep mode." + }, + { value: "2", + name: "High-Z", + desc: ''' + The pad is left undriven in deep sleep mode. Note that the actual + driving behavior during deep sleep will then depend on the pull-up/-down + configuration of in !!MIO_PAD_ATTR. + ''' + }, + { value: "3", + name: "Keep", + desc: "Keep last driven value (including high-Z)." + }, + ] + } + ] + } + }, +////////////////////////// +// DIO PAD sleep mode // +////////////////////////// + { multireg: { name: "DIO_PAD_SLEEP_STATUS", + desc: "Register indicating whether the corresponding pad is in sleep mode.", + count: "NDioPads", + swaccess: "rw0c", + hwaccess: "hrw", + cname: "DIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + This register is set to 1 if the deep sleep mode of the corresponding + pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. + The sleep mode of the corresponding pad will remain active until SW + clears this bit. + ''', + resval: "0", + } + ] + } + }, + { multireg: { name: "DIO_PAD_SLEEP_REGWEN", + desc: "Register write enable for DIO sleep value configuration.", + count: "NDioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "DIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!DIO_PAD_SLEEP_MODE + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "DIO_PAD_SLEEP_EN", + desc: '''Enables the sleep mode of the corresponding dedicated pad. + ''' + count: "NDioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "DIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "0", + name: "EN", + resval: 0, + desc: ''' + Deep sleep mode enable. + If this bit is set to 1 the corresponding pad will enable the sleep behavior + specified in !!DIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit + in !!DIO_PAD_SLEEP_STATUS will be set to 1. + The pad remains in deep sleep mode until the corresponding bit in + !!DIO_PAD_SLEEP_STATUS is cleared by SW. + Note that if an always on peripheral is connected to a specific DIO pad, + the corresponding !!DIO_PAD_SLEEP_EN bit should be set to 0. + ''' + } + ] + } + }, + { multireg: { name: "DIO_PAD_SLEEP_MODE", + desc: '''Defines sleep behavior of the corresponding dedicated pad. + ''' + count: "NDioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "DIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "1:0", + name: "OUT", + resval: 2, + desc: "Value to drive in deep sleep." + enum: [ + { value: "0", + name: "Tie-Low", + desc: "The pad is driven actively to zero in deep sleep mode." + }, + { value: "1", + name: "Tie-High", + desc: "The pad is driven actively to one in deep sleep mode." + }, + { value: "2", + name: "High-Z", + desc: ''' + The pad is left undriven in deep sleep mode. Note that the actual + driving behavior during deep sleep will then depend on the pull-up/-down + configuration of in !!DIO_PAD_ATTR. + ''' + }, + { value: "3", + name: "Keep", + desc: "Keep last driven value (including high-Z)." + }, + ] + } + ] + } + }, +//////////////////////// +// Wakeup detectors // +//////////////////////// + { multireg: { name: "WKUP_DETECTOR_REGWEN", + desc: "Register write enable for wakeup detectors.", + count: "NWkupDetect", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "WKUP_DETECTOR", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding WKUP_DETECTOR + configuration is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "WKUP_DETECTOR_EN", + desc: ''' + Enables for the wakeup detectors. + Note that these registers are synced to the always-on clock. + The first write access always completes immediately. + However, read/write accesses following a write will block until that write has completed. + ''' + count: "NWkupDetect", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "WKUP_DETECTOR_REGWEN", + regwen_multi: "true", + cname: "DETECTOR", + async: "clk_aon_i", + fields: [ + { bits: "0:0", + name: "EN", + resval: 0, + desc: ''' + Setting this bit activates the corresponding wakeup detector. + The behavior is as specified in !!WKUP_DETECTOR, + !!WKUP_DETECTOR_CNT_TH and !!WKUP_DETECTOR_PADSEL. + ''' + // In CSR tests, we do not touch the chip IOs. Thet are either pulled low or + // or undriven. + // + // Random writes to the wkup detect CSRs may result in the case where the + // wakeup gets enabled and signaled due to a pin being low for a programmed + // time, which results in wkup_cause register to mismatch, OR, result in + // assertion error due to a pin programmed for wakeup detection is undriven + // Also exclude write for csr_hw_reset, otherwise, X may be detected and propagating. + tags: ["excl:CsrAllTests:CsrExclWrite"] + } + ] + } + + }, + { multireg: { name: "WKUP_DETECTOR", + desc: ''' + Configuration of wakeup condition detectors. + Note that these registers are synced to the always-on clock. + The first write access always completes immediately. + However, read/write accesses following a write will block until that write has completed. + + Note that the wkup detector should be disabled by setting !!WKUP_DETECTOR_EN_0 before changing the detection mode. + The reason for that is that the pulse width counter is NOT cleared upon a mode change while the detector is enabled. + ''' + count: "NWkupDetect", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "WKUP_DETECTOR_REGWEN", + regwen_multi: "true", + cname: "DETECTOR", + async: "clk_aon_i", + fields: [ + { bits: "2:0", + name: "MODE", + resval: 0, + desc: "Wakeup detection mode. Out of range values default to Posedge." + enum: [ + { value: "0", + name: "Posedge", + desc: "Trigger a wakeup request when observing a positive edge." + }, + { value: "1", + name: "Negedge", + desc: "Trigger a wakeup request when observing a negative edge." + }, + { value: "2", + name: "Edge", + desc: "Trigger a wakeup request when observing an edge in any direction." + }, + { value: "3", + name: "TimedHigh", + desc: ''' + Trigger a wakeup request when pin is driven HIGH for a certain amount + of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH. + ''' + }, + { value: "4", + name: "TimedLow", + desc: ''' + Trigger a wakeup request when pin is driven LOW for a certain amount + of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH. + ''' + }, + + ] + } + { bits: "3", + name: "FILTER", + resval: 0, + desc: '''0: signal filter disabled, 1: signal filter enabled. the signal must + be stable for 4 always-on clock cycles before the value is being forwarded. + can be used for debouncing. + ''' + } + { bits: "4", + name: "MIODIO", + resval: 0, + desc: '''0: select index !!WKUP_DETECTOR_PADSEL from MIO pads, + 1: select index !!WKUP_DETECTOR_PADSEL from DIO pads. + ''' + } + ] + } + + }, + { multireg: { name: "WKUP_DETECTOR_CNT_TH", + desc: ''' + Counter thresholds for wakeup condition detectors. + Note that these registers are synced to the always-on clock. + The first write access always completes immediately. + However, read/write accesses following a write will block until that write has completed. + ''' + count: "NWkupDetect", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "WKUP_DETECTOR_REGWEN", + regwen_multi: "true", + cname: "DETECTOR", + async: "clk_aon_i", + fields: [ + { bits: "WkupCntWidth-1:0", + name: "TH", + resval: 0, + desc: '''Counter threshold for TimedLow and TimedHigh wakeup detector modes (see !!WKUP_DETECTOR). + The threshold is in terms of always-on clock cycles. + ''' + } + ] + } + + }, + { multireg: { name: "WKUP_DETECTOR_PADSEL", + desc: ''' + Pad selects for pad wakeup condition detectors. + This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix. + ''' + count: "NWkupDetect", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "WKUP_DETECTOR_REGWEN", + regwen_multi: "true", + cname: "DETECTOR", + fields: [ + { bits: "5:0", + name: "SEL", + resval: 0, + desc: '''Selects a specific MIO or DIO pad (depending on !!WKUP_DETECTOR configuration). + In case of MIO, the pad select index is the same as used for !!MIO_PERIPH_INSEL, meaning that index + 0 and 1 just select constants 0 and 1, and the MIO pads live at indices >= 2. In case of DIO pads, + the pad select index corresponds 1:1 to the DIO pad to be selected. + ''' + } + ] + } + + }, + { multireg: { name: "WKUP_CAUSE", + desc: ''' + Cause registers for wakeup detectors. + Note that these registers are synced to the always-on clock. + The first write access always completes immediately. + However, read/write accesses following a write will block until that write has completed. + ''' + count: "NWkupDetect", + swaccess: "rw0c", + hwaccess: "hrw", + cname: "DETECTOR", + async: "clk_aon_i", + fields: [ + { bits: "0", + name: "CAUSE", + resval: 0, + desc: '''Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. + ''' + } + ] + } + + }, + ], +} diff --git a/hw/top_darjeeling/ip_autogen/pinmux/data/pinmux_fpv_testplan.hjson b/hw/top_darjeeling/ip_autogen/pinmux/data/pinmux_fpv_testplan.hjson new file mode 100644 index 0000000000000..c7b93e78e2883 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/data/pinmux_fpv_testplan.hjson @@ -0,0 +1,883 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "pinmux" + import_testplans: ["hw/dv/tools/dvsim/testplans/fpv_csr_testplan.hjson"] + testpoints: [ + // `mio_to_periph_o` tests. + // Symbolic variable `periph_sel_i` is used to select a specific `mio_to_periph_o` pin. + { + name: InSel0_A + desc: '''When register `periph_insel` is set to 0, which means the selected input is constant + zero, the corresponding `mio_to_periph_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: InSel1_A + desc: '''When register `periph_insel` is set to 1, which means the selected input is constant + one, the corresponding `mio_to_periph_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: InSelN_A + desc: '''When register `periph_insel` is set to any value between 2 and + (2 + number of MioPads) and the select index is not jtag, the corresponding + `mio_to_periph_o` must be equal to the related `mio_in_i` value.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: InSelOOB_A + desc: '''When register `periph_insel` is set to any value larger than + (2 + number of MioPads), the corresponding `mio_to_periph_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `mio_to_periph_o` backward tests + // Symbolic variable `periph_sel_i` is used to select a specific `mio_to_periph_o` pin. + { + name: MioToPeriph0Backward_A + desc: '''`mio_to_periph_o` should output 0 only if one of the following conditions meets: + - Register `periph_insel` is set to 0. + - The corresponding `mio_in_i` is 0. + - Jtag is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: MioToPeriph1Backward_A + desc: '''`mio_to_periph_o` should output 1 only if one of the following conditions meets: + - Register `periph_insel` is set to 1. + - The corresponding `mio_in_i` is 1. + - Jtag is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `dio_to_periph_o` tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_to_periph_o` pin. + { + name: DioInSelN_A + desc: "This assertion checks that `dio_to_periph_o` is directly connected to `dio_in_i`." + stage: V1 + tests: ["pinmux_assert"] + } + + // `mio_out_o` not in sleep_mode tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_out_o` pin. + { + name: OutSel0_A + desc: '''When register `mio_outsel` is set to 0 and is not in sleep mode or jtag, which means + the selected output is constant zero, the corresponding `mio_out_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSel1_A + desc: '''When register `mio_outsel` is set to 1 and is not in sleep mode or jtag, which means + the selected output is constant one, the corresponding `mio_out_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSel2_A + desc: '''When register `mio_outsel` is set to 2 and is not in sleep mode or jtag, which means + the selected output is driving high-Z, the corresponding `mio_out_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSelN_A + desc: '''When register `mio_outsel` is set to any value between 3 and + (3 + Number of periph out) and is not in sleep mode or jtag, the corresponding + `mio_out_o` must be equal to the related `periph_to_mio_i` value.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSelOOB_A + desc: '''When register `mio_outsel` is set to any value larger than + (3 + Number of periph out) and is not in sleep mode, the corresponding `mio_out_o` must + be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `mio_out_o` backward tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_out_o` pin. + { + name: MioOut0Backward_A + desc: '''`mio_out_o` should output 0 only if one of the following conditions meets: + - Register `mio_insel` is set to 0 or 2. + - The corresponding `periph_to_mio_i` is 0. + - Sleep mode is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: MioOut1Backward_A + desc: '''`mio_out_o` should output 1 only if one of the following conditions meets: + - Register `mio_insel` is set to 1. + - The corresponding `periph_to_mio_i` is 1. + - Sleep mode is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `mio_oe_o` not in sleep_mode tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_out_o` pin. + { + name: OutSelOe0_A + desc: '''When register `mio_outsel` is set to 0 and is not in sleep mode or jtag, the + corresponding `mio_oe_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSelOe1_A + desc: '''When register `mio_outsel` is set to 1 and is not in sleep mode or jtag, the + corresponding `mio_oe_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSelOe2_A + desc: '''When register `mio_outsel` is set to 2 and is not in sleep mode or jtag, which + indicates driving high-Z to the selected output, the corresponding `mio_oe_o` must + be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSelOeN_A + desc: '''When register `mio_outsel` is set to any value between 3 and + (3 + Number of periph out) and is not in sleep mode or jtag, the corresponding + `mio_oe_o` must be equal to the related `periph_to_mio_oe_i` value.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSelOeOOB_A + desc: '''When register `mio_outsel` is set to any value larger than + (3 + Number of periph out) and is not in sleep mode, the corresponding `mio_oe_o` must + be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `mio_oe_o` backward tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_oe_o` pin. + { + name: MioOe0Backward_A + desc: '''`mio_oe_o` should output 0 only if one of the following conditions meets: + - Register `mio_insel` is set to 2. + - The corresponding `periph_to_mio_oe_i` is 0. + - Sleep mode is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: MioOe1Backward_A + desc: '''`mio_oe_o` should output 1 only if one of the following conditions meets: + - Register `mio_insel` is set to 0 or 1. + - The corresponding `periph_to_mio_oe_i` is 1. + - Sleep mode is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `mio_out_o` in sleep mode tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_out_o` pin. + { + name: MioSleepMode0_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 0, which means the pad is driven zero in deep sleep mode. + If, in the meantime, register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_out_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioSleepMode1_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 1, which means the pad is driven one in deep sleep mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_out_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioSleepMode2_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 2, which means the pad is driven high-Z in deep sleep mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_out_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioSleepMode3_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 3, which means the pad keeps last driven value in deep sleep + mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_out_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioSleepStable_A + desc: '''If not at posedge of `sleep_en_i`, and in the meantime register + `mio_pad_sleep_status` is not written via TLUL interface to clear the sleep status, the + corresponding `mio_out_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `mio_oe_o` in sleep mode tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_oe_o` pin. + { + name: MioOeSleepMode0_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 0, which means the pad is driven zero in deep sleep mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_oe_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioOeSleepMode1_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 1, which means the pad is driven one in deep sleep mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_oe_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioOeSleepMode2_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 2, which means the pad is driven high-Z in deep sleep mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_oe_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioOeSleepMode3_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 3, which means the pad keeps last driven value in deep sleep + mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_oe_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioOeSleepStable_A + desc: '''If not at posedge of `sleep_en_i`, and in the meantime, if register + `mio_pad_sleep_status` is not written via TLUL interface to clear the sleep status, the + corresponding `mio_oe_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `mio_out_o` sleep mode related backward tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_out_o` pin. + { + name: MioSleep0Backward_A + desc: '''`mio_out_o` should output 0 only if one of the following conditions meets: + - In sleep mode, register `mio_pad_sleep_mode` is set to 0 or 2. + - In sleep mode, previous `mio_out_o` is 0 and `mio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `mio_out_o` is 0 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: MioSleep1Backward_A + desc: '''`mio_out_o` should output 1 only if one of the following conditions meets: + - In sleep mode, register `mio_pad_sleep_mode` is set to 1. + - In sleep mode, previous `mio_out_o` is 1 and `mio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `mio_out_o` is 1 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `mio_oe_o` sleep mode related backward tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_oe_o` pin. + { + name: MioOeSleep0Backward_A + desc: '''`mio_oe_o` should output 0 only if one of the following conditions meets: + - In sleep mode, register `mio_pad_sleep_mode` is set to 2. + - In sleep mode, previous `mio_oe_o` is 0 and `mio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `mio_oe_o` is 0 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: MioOeSleep1Backward_A + desc: '''`mio_oe_o` should output 1 only if one of the following conditions meets: + - In sleep mode, register `mio_pad_sleep_mode` is set to 0 or 1. + - In sleep mode, previous `mio_oe_o` is 1 and `mio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `mio_oe_o` is 1 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `dio_out_o` not in sleep mode tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_out_o` pin. + { + name: DOutSelN_A + desc: "`dio_out_o` is connected to `periph_to_dio_i` if not in sleep mode." + stage: V1 + tests: ["pinmux_assert"] + } + + // `dio_oe_o` not in sleep mode tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_oe_o` pin. + { + name: DOutSelOeN_A + desc: "`dio_oe_o` is connected to `periph_to_dio_oe_i` if not in sleep mode." + stage: V1 + tests: ["pinmux_assert"] + } + + // `dio_out_o` in sleep mode tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_out_o` pin. + { + name: DioSleepMode0_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 0, which means the pad is driven zero in deep sleep mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_out_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioSleepMode1_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 1, which means the pad is driven one in deep sleep mode. + In the meantime, if register `dmio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_out_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioSleepMode2_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 2, which means the pad is driven high-Z in deep sleep mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_out_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioSleepMode3_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 3, which means the pad keeps last driven value in deep sleep + mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_out_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioSleepStable_A + desc: '''If not at posedge of `sleep_en_i`, and in the meantime, if register + `dio_pad_sleep_status` is not written via TLUL interface to clear the sleep status, the + corresponding `dio_out_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `dio_oe_o` in sleep mode tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_oe_o` pin. + { + name: DioOeSleepMode0_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 0, which means the pad is driven zero in deep sleep mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_oe_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioOeSleepMode1_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 1, which means the pad is driven one in deep sleep mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_oe_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioOeSleepMode2_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 2, which means the pad is driven high-Z in deep sleep mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_oe_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioOeSleepMode3_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 3, which means the pad keeps last driven value in deep sleep + mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_oe_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioOeSleepStable_A + desc: '''If not at posedge of `sleep_en_i`, and in the meantime, if register + `dio_pad_sleep_status` is not written via TLUL interface to clear the sleep status, the + corresponding `dio_oe_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `dio_out_o` backward tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_out_o` pin. + { + name: Dio0Backward_A + desc: '''`dio_out_o` should output 0 only if one of the following conditions meets: + - The corresponding `periph_to_dio_i` is 0. + - In sleep mode, register `dio_pad_sleep_mode` is set to 0 or 2. + - In sleep mode, previous `dio_out_o` is 0 and `dio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `dio_out_o` is 0 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: Dio1Backward_A + desc: '''`dio_out_o` should output 1 only if one of the following conditions meets: + - The corresponding `periph_to_dio_i` is 1. + - In sleep mode, register `dio_pad_sleep_mode` is set to 1. + - In sleep mode, previous `dio_out_o` is 1 and `dio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `dio_out_o` is 1 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `dio_oe_o` backward tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_oe_o` pin. + { + name: DioOe0Backward_A + desc: '''`dio_oe_o` should output 0 only if one of the following conditions meets: + - The corresponding `periph_to_dio_i` is 0. + - In sleep mode, register `dio_pad_sleep_mode` is set to 2. + - In sleep mode, previous `dio_oe_o` is 0 and `dio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `dio_oe_o` is 0 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: DioOe1Backward_A + desc: '''`dio_oe_o` should output 1 only if one of the following conditions meets: + - The corresponding `periph_to_dio_i` is 1. + - In sleep mode, register `dio_pad_sleep_mode` is set to 0 or 1. + - In sleep mode, previous `dio_oe_o` is 1 and `dio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `dio_oe_o` is 1 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `mio_pad_attr_o` tests + { + name: MioAttrO_A + desc: '''`mio_attr_o` should be equal to corresponding `mio_pad_attr` register value and + TargetCfg's mio_pad_type configuration.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioJtagAttrO_A + desc: "If jtag is enabled, the jtag `mio_attr_o` index should be equal to 0." + stage: V1 + tests: ["pinmux_assert"] + } + + // `dio_pad_attr_o` tests + { + name: DioAttrO_A + desc: '''`dio_attr_o` should be equal to corresponding `dio_pad_attr` register value and + TargetCfg's dio_pad_type configuration.''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `pin_wkup_req_o` tests + // Symbolic variable `wkup_sel_i` is used to select a specific wkup_cause. + // Variable `final_pin_val` is created to capture selected wakeup pins based on register + // `wkup_detector_padsel` and `wkup_detector.filter`. + { + name: WkupPosedge_A + desc: '''When register `wkup_detector_en` is set to 1 and `wkup_detector.mode` is set to 0, + which means rising edge is used to detect wakeup. If variable `final_pin_val` is at + posedge then `wkup_cause` register's `de` attribute should be set to 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: WkupNegedge_A + desc: '''When register `wkup_detector_en` is set to 1 and `wkup_detector.mode` is set to 1, + which means falling edge is used to detect wakeup. If variable `final_pin_val` is at + negedge, then `wkup_cause` register's `de` attribute should be set to 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: WkupEdge_A + desc: '''When register `wkup_detector_en` is set to 1 and `wkup_detector.mode` is set to 2, + which means either rising or falling edge is used to detect wakeup. If variable + `final_pin_val` is at posedge or negedge, then `wkup_cause` register's `de` attribute + should be set to 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: WkupTimedHigh_A + desc: '''When register `wkup_detector_en` is set to 1 and `wkup_detector.mode` is set to 3, + which means postive pulse cycles are used to detect wakeup. If variable `final_pin_val` + stays high longer than the threshold, then `wkup_cause` register's `de` attribute + should be set to 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: WkupTimedLow_A + desc: '''When register `wkup_detector_en` is set to 1 and `wkup_detector.mode` is set to 4, + which means negative pulse cycles are used to detect wakeup. If variable `final_pin_val` + stays low longer than the threshold, then `wkup_cause` register's `de` attribute should + be set to 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: WkupCauseQ_A + desc: '''When `wkup_cause` register's `de` attribute is set to 1 and user is not writing to + `wkup_cause` at the same cycle, then `wkup_cause.q` should be set to 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: AonWkupO_A + desc: '''When register `wkup_cause` is 1, `pin_wkup_req_o` should also be 1. + `pin_wkup_req_o` is 0 only when all `wkup_cause` registers are 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `pin_wkup_req_o` backward tests + { + name: WkupCause0_A + desc: "Register `wkup_cause` is 0 only when none of the above wakeup conditions is met." + stage: V2 + tests: ["pinmux_assert"] + } + { + name: WkupCause1_A + desc: "Register `wkup_cause` is 1 when at least one of the above wakeup conditions is met." + stage: V2 + tests: ["pinmux_assert"] + } + + // `lc_jtag_o` tests + { + name: LcJtagWoScanmode_A + desc: '''Not in scanmode, when tap_strap select LC_tap, `lc_jtag_o` must be equal to the + corresponding `mio_in_i` pins based on the `TargetCfg` configuration.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: LcJtagWScanmode_A + desc: '''In scanmode, when tap_strap select LC_tap, `lc_jtag_o` must be equal to the + corresponding `mio_in_i` pins based on the `TargetCfg` configuration except the + `jtag_trst` pin, which must be equal to `rst_ni`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: LcJtagODefault_A + desc: "`lc_jtag_o` should stay 0 if tap_strap did not select LC_tap." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: LcJtagOBackward_A + desc: '''`lc_jtag_o` pins are equal to the corresponding `mio_in_i` inputs if one of the + following conditions are met: + - Lc Jtag is disabled and the corresponding pins are 0. + - Lc Jtag is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `rv_jtag_o` tests + { + name: RvJtagWoScanmode_A + desc: '''Not in scanmode, when tap_strap select RV_tap and `lc_hw_debug_en_i` input is On for + the past two clock cycles due to the synchronizer, then `rv_jtag_o` must be equal to + the corresponding `mio_in_i` pins based on the `TargetCfg` configuration.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: RvJtagWScanmode_A + desc: '''In scanmode, When tap_strap select RV_tap and `lc_hw_debug_en_i` is On for the past + two clock cycles due to the synchronizer, then `rv_jtag_o` must be equal to the + corresponding `mio_in_i` pins based on the `TargetCfg` configuration except the + `jtag_trst` pin, which must be equal to `rst_ni`. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: RvJtagODefault_A + desc: '''`rv_jtag_o` should stay 0 if tap_strap did not select RV_tap or `lc_hw_debug_en_i` + input is Off for the past two clock cycles due to the synchronizer.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: RvJtagOBackward_A + desc: '''`rv_jtag_o` pins are equal to the corresponding `mio_in_i` inputs if one of the + following conditions are met: + - Rv Jtag is disabled and the corresponding pins are 0. + - Rv Jtag is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `dft_jtag_o` tests + { + name: DftJtagWoScanmode_A + desc: '''Not in scanmode, when tap_strap select DFT_tap and `lc_dft_en_i` is On for the past + two clock cycles due to the synchronizer, `lc_jtag_o` must be equal to the + corresponding `mio_in_i` pins based on the `TargetCfg` configuration.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DftJtagWScanmode_A + desc: '''In scanmode, when tap_strap select DFT_tap and `lc_dft_en_i` is On for the past + two clock cycles due to the synchronizer, `lc_jtag_o` must be equal to the + corresponding `mio_in_i` pins based on the `TargetCfg` configuration except the + `jtag_trst` pin, which must be equal to `rst_ni`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DftJtagODefault_A + desc: '''`dft_jtag_o` should stay 0 if tap_strap did not select DFT_tap or the `lc_dft_en_i` + input is Off for the past two clock cycles due to the synchronizer.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DftJtagOBackward_A + desc: '''`dft_jtag_o` pins are equal to the corresponding `mio_in_i` inputs if one of the + following conditions are met: + - Dft Jtag is disabled and the corresponding pins are 0. + - Dft Jtag is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: DftJtagO1Backward_A + desc: '''`dft_jtag_o` pins are ones if one of the following conditions are met: + - Dft Jtag is enabled and the corresponding pins are 1. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + { + name: TapStrap_A + desc: '''If `dft_hold_tap_sel_i` is 0 and `lc_dft_en_i` is On for the past two clock cycles + due to the synchronizer, or `strap_en_i` is 1. + And in the meantime, if `lc_hw_debug_en_i` is On for the past two clock cycles due to + the synchronizer, then tap_strap must be equal to the past value of corresponding + `mio_in_i`. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: TapStrap0_A + desc: '''If `dft_hold_tap_sel_i` is 0 and `lc_dft_en_i` is On for the past two clock cycles + due to the synchronizer, or `strap_en_i` is 1. + Then tap_strap[0] must be equal to the past value of corresponding `mio_in_i`. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + + // Jtag pinmux output tests + { + name: LcJtagI_A + desc: '''When Lc tap is selected, the corresponding `mio_out_o` and `mio_out_oe` should be + equal to `lc_jtag_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: RvJtagI_A + desc: '''When Rv tap is selected and `lc_hw_debug_en_i` is On for the past two clock cycles + due to the synchronizer, the corresponding `mio_out_o` and `mio_out_oe` should be equal + to `rv_jtag_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DftJtagI_A + desc: '''When Dft tap is selected and `lc_dft_en_i` is On for the past two clock cycles + due to the synchronizer, the corresponding `mio_out_o` and `mio_out_oe` should be equal + to `dft_jtag_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + + // Dft `strap_test_o` tests + { + name: DftStrapTestO_A + desc: '''When `lc_dft_en_i` is On for the past two clock cycles due to the synchronizer, + `dft_strap_test_o.valid` must be 1, and `dft_strap_test_o.straps` should be equal to + the corresponding `mio_in_i` index.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DftStrapTestOValidStable_A + desc: "`dft_strap_test_o.valid` once set to 1 will stay high until reset." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DftStrapTestOStrapStable_A + desc: "`dft_strap_test_o.valid` once set, `dft_strap_test_o.straps` should stay stable." + stage: V1 + tests: ["pinmux_assert"] + } + + // USB related IOs. + // Current plan is to only check connectivity via assertions because usbdev design is fully + // verified separately in a DV testbench. + { + name: UsbSleepEnI_A + desc: "`sleep_en_i` should be connected directly to usbdev's `low_power_alw_i`." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbDppullupEnUpwrI_A + desc: '''`usb_dppullup_en_upwr_i` should be connected directly to usbdev's + `usb_dppullup_en_upwr_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbDnpullupEnUpwrI_A + desc: '''`usb_dnpullup_en_upwr_i` should be connected directly to usbdev's + `usb_dnpullup_en_upwr_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbDppullupEnO_A + desc: '''`usb_dppullup_en_o` should be connected directly to usbdev's + `usb_dppullup_en_o`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbDnpullupEnO_A + desc: '''`usb_dnpullup_en_o` should be connected directly to usbdev's + `usb_dnpullup_en_o`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbOutOfRstI_A + desc: "`usb_out_of_rst_i` should be connected directly to usbdev's `usb_out_of_rst_upwr_i`." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbAonWakeEnUpwrI_A + desc: '''`usb_aon_wake_en_i` should be connected directly to usbdev's + `usb_aon_wake_en_upwr_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbAonWakeAckUpwrI_A + desc: '''`usb_aon_wake_ack_i` should be connected directly to usbdev's + `usb_aon_woken_upwr_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbSuspendI_A + desc: "`usb_suspend_i` should be connected directly to usbdev's `usb_suspended_upwr_i`." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbWkupReqO_A + desc: "`usb_wkup_req_o` should be connected directly to usbdev's `wake_rep_alw_o`." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbBusResetO_A + desc: "`usb_bus_reset_o` should be connected directly to usbdev's `bus_reset_alw_o`." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbSenseLostO_A + desc: "`usb_sense_lost_o` should be connected directly to usbdev's `bus_lost_alw_o`." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbStateDebugO_A + desc: "`usb_state_debug_o` should be connected directly to usbdev's `bus_debug_o`." + stage: V1 + tests: ["pinmux_assert"] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/pinmux/data/pinmux_sec_cm_testplan.hjson b/hw/top_darjeeling/ip_autogen/pinmux/data/pinmux_sec_cm_testplan.hjson new file mode 100644 index 0000000000000..9111fdccf4956 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/data/pinmux_sec_cm_testplan.hjson @@ -0,0 +1,33 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../pinmux/data/pinmux.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../pinmux/data/pinmux_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: "Verify the countermeasure(s) BUS.INTEGRITY." + stage: V2S + tests: [] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/pinmux/data/top_darjeeling_pinmux.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/pinmux/data/top_darjeeling_pinmux.ipconfig.hjson new file mode 100644 index 0000000000000..45b4885cd88ba --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/data/top_darjeeling_pinmux.ipconfig.hjson @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_pinmux + param_values: + { + n_wkup_detect: 8 + wkup_cnt_width: 8 + n_mio_pads: 12 + n_mio_periph_in: 4 + n_mio_periph_out: 5 + n_dio_pads: 73 + n_dio_periph_in: 58 + n_dio_periph_out: 57 + enable_usb_wakeup: false + enable_strap_sampling: false + topname: darjeeling + } +} diff --git a/hw/top_darjeeling/ip_autogen/pinmux/doc/checklist.md b/hw/top_darjeeling/ip_autogen/pinmux/doc/checklist.md new file mode 100644 index 0000000000000..37f48b1992dea --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/doc/checklist.md @@ -0,0 +1,267 @@ +# Pinmux Checklist + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [Pinmux peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done | [Pinmux spec](../README.md) +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | Done | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | Primary I/Os are exempted from KNOWN assertions since the chip-level testbench may drive X'es onto some of these signals. +Code Quality | [LINT_SETUP][] | Done | + + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Done | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. +Documentation | [MISSING_FUNC][] | Done | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | +RTL | [STYLE_X][] | Done | +RTL | [CDC_SYNCMACRO][] | Done | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [AREA_CHECK][] | Done | +Code Quality | [TIMING_CHECK][] | Done | +Security | [SEC_CM_DOCUMENTED][] | N/A | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | N/A | +Security | [SEC_CM_NON_RESET_FLOPS][] | N/A | +Security | [SEC_CM_SHADOW_REGS][] | N/A | +Security | [SEC_CM_RTL_REVIEWED][] | N/A | +Security | [SEC_CM_COUNCIL_REVIEWED][] | N/A | This block only contains the bus-integrity CM. + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Done | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_RTL][] | Done | Note that the USB wakeup detector submodule `u_usbdev_aon_wake` is excluded in this review as it will be reviewed as part of the USB sign-off process. +Review | [REVIEW_DELETED_FF][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | msf@ tjaychen@ chencindy@ awill@ +Review | Signoff date | Done | 2022-08-17 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | +Documentation | [TESTPLAN_COMPLETED][] | Done | +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | N/A | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | N/A | This block uses FPV +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | Done | +Tests | [SIM_SMOKE_TEST_PASSING][] | N/A | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | N/A | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Done | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | N/A | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | N/A | +Regression | [FPV_REGRESSION_SETUP][] | Done | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | N/A | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Waived | usbdev will be verified by a separate DV testbench. +Review | [DESIGN_SPEC_REVIEWED][] | Not Started | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | N/A | +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Done | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | N/A | +Tests | [SIM_ALL_TESTS_PASSING][] | N/A | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Done | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Done | +Tests | [SIM_FW_SIMULATED][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | N/A | +Coverage | [SIM_CODE_COVERAGE_V2][] | N/A | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | N/A | +Coverage | [FPV_CODE_COVERAGE_V2][] | Done | +Coverage | [FPV_COI_COVERAGE_V2][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Waived | usbdev will be verified by a separate DV testbench. +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done | The testplan has been generated, but there is no DV environment to test these CMs. The CMs (bus integrity and LC gated TAP muxing/demuxing) are tested with the FPV testbench instead. +Tests | [FPV_SEC_CM_PROVEN][] | Done | The SEC_CM behavior has been proven with formal. +Tests | [SIM_SEC_CM_VERIFIED][] | N/A | This module only has an FPV testbench. +Coverage | [SIM_COVERAGE_REVIEWED][] | N/A | This module only has an FPV testbench. +Review | [SEC_CM_DV_REVIEWED][] | Done | + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pendingg diff --git a/hw/top_darjeeling/ip_autogen/pinmux/doc/dv/README.md b/hw/top_darjeeling/ip_autogen/pinmux/doc/dv/README.md new file mode 100644 index 0000000000000..e9fb9da7872ab --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/doc/dv/README.md @@ -0,0 +1,35 @@ +# PINMUX DV document + +* **DV**: + * TODO: Add a UVM testbench to reuse auto-generated common tests for TLUL and alerts. + +* **FPV**: + * Verify all the PINMUX outputs by writing assumptions and assertions with a FPV based testbench + * Verify TileLink device protocol compliance with a FPV based testbench + +* [Design & verification stage](../../../../../README.md) + * [HW development stages](../../../../../../doc/project_governance/development_stages.md) +* [FPV dashboard](https://reports.opentitan.org/hw/top_darjeeling/formal/summary.html) + +For detailed information on PINMUX design features, please see the +[PINMUX design specification](../../README.md). + +PINMUX FPV testbench has been constructed based on the [formal architecture](../../../../../formal/README.md). + +![Block diagram](fpv.svg) + +* The `../fpv/tb/pinmux_bind.sv` binds the `tlul_assert` [assertions](../../../../../ip/tlul/doc/TlulProtocolChecker.md) with pinmux to ensure TileLink interface protocol compliance. +* The `../fpv/tb/pinmux_bind.sv` also binds the `pinmux_csr_assert_fpv` to assert the TileLink writes and reads correctly. + +* The `../fpv/tb/pinmux_bind_fpv.sv` binds module `pinmux_assert_fpv` with the pinmux RTL. +The assertion file ensures all pinmux's outputs are verified based on the [testplan](#testplan). + +In the pinmux design, it includes usbdev logic because it operates on an always-on domain. +Pinmux FPV assertions will only cover the connectivities between usbdev IOs and pinmux IOs. +All functional checks will be implemented in the usbdev testbench. + +Due to the large number of peripheral, muxed, dedicated IOs, and wakeup causes, symbolic variables are used to reduce the number of repeated assertions code. +In the pinmux_assert_fpv module, we declared four symbolic variables (`mio_sel_i`, `periph_sel_i`, `dio_sel_i`, `wkup_sel_i`) to represent the index for muxed IOs, peripheral IOs, dedicated IOs, and wakeup causes. +Detailed explanation is listed in the [Symbolic Variables](../../../../../formal/README.md#symbolic-variables) section. + +[Testplan](../../data/pinmux_fpv_testplan.hjson) diff --git a/hw/top_darjeeling/ip_autogen/pinmux/doc/dv/fpv.svg b/hw/top_darjeeling/ip_autogen/pinmux/doc/dv/fpv.svg new file mode 100644 index 0000000000000..0061e7fd012f5 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/doc/dv/fpv.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/pinmux/doc/generic_pad_wrapper.svg b/hw/top_darjeeling/ip_autogen/pinmux/doc/generic_pad_wrapper.svg new file mode 100644 index 0000000000000..bd95569d8ea00 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/doc/generic_pad_wrapper.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/pinmux/doc/interfaces.md b/hw/top_darjeeling/ip_autogen/pinmux/doc/interfaces.md new file mode 100644 index 0000000000000..b3931f980ddb2 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/doc/interfaces.md @@ -0,0 +1,91 @@ +# Hardware Interfaces + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`pinmux`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: **`clk_aon_i`** +- Bus Device Interfaces (TL-UL): **`tl`** +- Bus Host Interfaces (TL-UL): *none* +- Peripheral Pins for Chip IO: *none* +- Interrupts: *none* + +## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:--------------------------|:-------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Debug enable qualifier coming from life cycle controller, used for HW strap qualification. | +| lc_dft_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Test enable qualifier coming from life cycle controller, used for HW strap qualification. | +| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Escalation enable signal coming from life cycle controller, used for invalidating the latched lc_hw_debug_en state inside the strap sampling logic. | +| lc_check_byp_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Check bypass enable signal coming from life cycle controller, used for invalidating the latched lc_hw_debug_en state inside the strap sampling logic. This signal is asserted whenever the life cycle controller performs a life cycle transition. Its main use is to skip any background checks inside the life cycle partition of the OTP controller while a life cycle transition is in progress. | +| pinmux_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | This is the latched version of lc_hw_debug_en_i. We use it exclusively to gate the JTAG signals and TAP side of the RV_DM so that RV_DM can remain live during an NDM reset cycle. | +| lc_jtag | jtag_pkg::jtag | req_rsp | req | 1 | Qualified JTAG signals for life cycle controller TAP. | +| rv_jtag | jtag_pkg::jtag | req_rsp | req | 1 | Qualified JTAG signals for RISC-V processor TAP. | +| dft_jtag | jtag_pkg::jtag | req_rsp | req | 1 | Qualified JTAG signals for DFT TAP. | +| dft_strap_test | pinmux_pkg::dft_strap_test_req | uni | req | 1 | Sampled DFT strap values, going to the DFT TAP. | +| dft_hold_tap_sel | logic | uni | rcv | 1 | TAP selection hold indication, asserted by the DFT TAP during boundary scan. | +| sleep_en | logic | uni | rcv | 1 | Level signal that is asserted when the power manager enters sleep. | +| strap_en | logic | uni | rcv | 1 | This signal is pulsed high by the power manager after reset in order to sample the HW straps. | +| strap_en_override | logic | uni | rcv | 1 | This signal transitions from 0 -> 1 by the lc_ctrl manager after volatile RAW_UNLOCK in order to re-sample the HW straps. The signal must stay at 1 until reset. Note that this is only used in test chips when SecVolatileRawUnlockEn = 1. Otherwise this signal is unused. | +| pin_wkup_req | logic | uni | req | 1 | Wakeup request from wakeup detectors, to the power manager, running on the AON clock. | +| usbdev_dppullup_en | logic | uni | rcv | 1 | Pullup enable signal coming from the USB IP. | +| usbdev_dnpullup_en | logic | uni | rcv | 1 | Pullup enable signal coming from the USB IP. | +| usb_dppullup_en | logic | uni | req | 1 | Pullup enable signal going to USB PHY, needs to be maintained in low-power mode. | +| usb_dnpullup_en | logic | uni | req | 1 | Pullup enable signal going to USB PHY, needs to be maintained in low-power mode. | +| usb_wkup_req | logic | uni | req | 1 | Wakeup request from USB wakeup detector, going to the power manager, running on the AON clock. | +| usbdev_suspend_req | logic | uni | rcv | 1 | Indicates whether USB is in suspended state, coming from the USB device. | +| usbdev_wake_ack | logic | uni | rcv | 1 | Acknowledges the USB wakeup request, coming from the USB device. | +| usbdev_bus_not_idle | logic | uni | req | 1 | Event signal that indicates that the USB was not idle while monitoring. | +| usbdev_bus_reset | logic | uni | req | 1 | Event signal that indicates that the USB issued a Bus Reset while monitoring. | +| usbdev_sense_lost | logic | uni | req | 1 | Event signal that indicates that USB SENSE signal was lost while monitoring. | +| usbdev_wake_detect_active | logic | uni | req | 1 | State debug information. | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | + +## Security Alerts + +| Alert Name | Description | +|:-------------|:----------------------------------------------------------------------------------| +| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. | + +## Security Countermeasures + +| Countermeasure ID | Description | +|:---------------------|:---------------------------------| +| PINMUX.BUS.INTEGRITY | End-to-end bus integrity scheme. | + + + + +## Parameters + +The following table lists the main parameters used throughout the `pinmux` design. +Note that the `pinmux` is generated based on the system configuration, and hence these parameters are placed into a package. +The pinout and `pinmux` mappings are listed under [Pinout and Pinmux Mapping](#pinout-and-pinmux-mapping) for specific top-level configurations. + +Parameter | Description +---------------|--------------- +`NPeriphOut` | Number of peripheral outputs. +`NPeriphIn` | Number of peripheral input. +`NMioPads` | Number of muxed bidirectional pads. +`NDioPads` | Number of dedicated pads. + +## Primary IO Signals + +The table below lists the primary `pinmux` IO signals to/from the pad ring. +The number of dedicated and muxed IOs is parametric, and hence the signals are stacked in packed arrays. + +Signal | Direction | Type | Description +---------------------------------------|-----------|------------------------------------|--------------- +`periph_to_mio_i[NPeriphOut-1:0]` | `input` | packed `logic` | Signals from `NPeriphOut` muxed peripheral outputs coming into the `pinmux`. +`periph_to_mio_oe_i[NPeriphOut-1:0]` | `input` | packed `logic` | Signals from `NPeriphOut` muxed peripheral output enables coming into the `pinmux`. +`mio_to_periph_o[NPeriphIn-1:0]` | `output` | packed `logic` | Signals to `NPeriphIn` muxed peripherals coming from the `pinmux`. +`periph_to_dio_i[NDioPads-1:0]` | `input` | packed `logic` | Signals from `NDioPads` dedicated peripheral outputs coming into the `pinmux`. +`periph_to_dio_oe_i[NDioPads-1:0]` | `input` | packed `logic` | Signals from `NDioPads` dedicated peripheral output enables coming into the `pinmux`. +`dio_to_periph_o[NDioPads-1:0]` | `output` | packed `logic` | Signals to `NDioPads` dedicated peripherals coming from the `pinmux`. +`mio_attr_o[NMioPads-1:0]` | `output` | prim_pad_wrapper_pkg::pad_attr_t | Packed array containing the pad attributes of all muxed IOs. +`mio_out_o[NMioPads-1:0]` | `output` | packed `logic` | Signals to `NMioPads` bidirectional muxed pads as output data. +`mio_oe_o[NMioPads-1:0]` | `output` | packed `logic` | Signals to `NMioPads` bidirectional muxed pads as output enables. +`mio_in_i[NMioPads-1:0]` | `input` | packed `logic` | Signals from `NMioPads` bidirectional muxed pads as input data. +`dio_attr_o[NDioPads-1:0]` | `output` | prim_pad_wrapper_pkg::pad_attr_t | Packed array containing the pad attributes of all dedicated IOs. +`dio_out_o[NDioPads-1:0]` | `output` | packed `logic` | Signals to `NDioPads` bidirectional dedicated pads as output data. +`dio_oe_o[NDioPads-1:0]` | `output` | packed `logic` | Signals to `NDioPads` bidirectional dedicated pads as output enables. +`dio_in_i[NDioPads-1:0]` | `input` | packed `logic` | Signals from `NDioPads` bidirectional dedicated pads as input data. diff --git a/hw/top_darjeeling/ip_autogen/pinmux/doc/pinmux_muxing_matrix.svg b/hw/top_darjeeling/ip_autogen/pinmux/doc/pinmux_muxing_matrix.svg new file mode 100644 index 0000000000000..0cd96b99002d7 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/doc/pinmux_muxing_matrix.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/pinmux/doc/pinmux_overview_block_diagram.svg b/hw/top_darjeeling/ip_autogen/pinmux/doc/pinmux_overview_block_diagram.svg new file mode 100644 index 0000000000000..895eec6e6da41 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/doc/pinmux_overview_block_diagram.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/pinmux/doc/pinout_asic.md b/hw/top_darjeeling/ip_autogen/pinmux/doc/pinout_asic.md new file mode 100644 index 0000000000000..b44cf3e93310e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/doc/pinout_asic.md @@ -0,0 +1,188 @@ +# "ASIC" Target : Pinout and Pinmux Connectivity + +## Pinout Table + +|

Pad Name

|

Type

|

Bank

|

Connection

|

Special Function

|

Pinmux Insel Constant / Muxed Output Index

|

Description

| +|:-------------------------------------------------:|:------------------------------------------:|:---------------------------------------:|:---------------------------------------------:|:---------------------------------------------------:|:-------------------------------------------------------------------------------------------------:|:-------------------------------------------------------------------:| +|

POR_N

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

System reset

| +|

JTAG_TCK

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TCK signal

| +|

JTAG_TMS

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TMS signal

| +|

JTAG_TDI

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TDI signal

| +|

JTAG_TDO

|

BidirStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TDO signal

| +|

JTAG_TRST_N

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TRST_N signal

| +|

OTP_EXT_VOLT

|

AnalogIn1

|

VIO

|

manual

|

-

|

- / -

|

OTP external voltage input

| +|

SPI_HOST_D0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_CLK

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host clock

| +|

SPI_HOST_CS_L

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host chip select

| +|

SPI_DEV_D0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_CLK

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device clock

| +|

SPI_DEV_CS_L

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device chip select

| +|

SPI_DEV_TPM_CS_L

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device TPM chip select

| +|

UART_RX

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

UART receive

| +|

UART_TX

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

UART transmit

| +|

I2C_SCL

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

I2C clock

| +|

I2C_SDA

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

I2C data

| +|

GPIO0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO4

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO5

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO6

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO7

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO8

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO9

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO10

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO11

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO12

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO13

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO14

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO15

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO16

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO17

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO18

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO19

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO20

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO21

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO22

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO23

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO24

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO25

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO26

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO27

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO28

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO29

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO30

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO31

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

SOC_GPI0

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI1

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI2

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI3

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI4

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI5

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI6

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI7

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI8

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI9

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI10

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI11

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPO0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO4

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO5

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO6

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO7

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO8

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO9

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO10

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO11

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

MIO0

|

BidirStd

|

VIO

|

muxed

|

tap0

|

kTopDarjeelingPinmuxInselMio0 / kTopDarjeelingPinmuxMioOutMio0

|

Muxed IO pad / TAP strap signal.

| +|

MIO1

|

BidirStd

|

VIO

|

muxed

|

tap1

|

kTopDarjeelingPinmuxInselMio1 / kTopDarjeelingPinmuxMioOutMio1

|

Muxed IO pad / TAP strap signal.

| +|

MIO2

|

BidirStd

|

VIO

|

muxed

|

dft0

|

kTopDarjeelingPinmuxInselMio2 / kTopDarjeelingPinmuxMioOutMio2

|

Muxed IO pad / DFT strap signal.

| +|

MIO3

|

BidirStd

|

VIO

|

muxed

|

dft1

|

kTopDarjeelingPinmuxInselMio3 / kTopDarjeelingPinmuxMioOutMio3

|

Muxed IO pad / DFT strap signal.

| +|

MIO4

|

BidirStd

|

VIO

|

muxed

|

tck

|

kTopDarjeelingPinmuxInselMio4 / kTopDarjeelingPinmuxMioOutMio4

|

Muxed IO pad / JTAG tck signal.

| +|

MIO5

|

BidirStd

|

VIO

|

muxed

|

tms

|

kTopDarjeelingPinmuxInselMio5 / kTopDarjeelingPinmuxMioOutMio5

|

Muxed IO pad / JTAG tms signal.

| +|

MIO6

|

BidirStd

|

VIO

|

muxed

|

trst_n

|

kTopDarjeelingPinmuxInselMio6 / kTopDarjeelingPinmuxMioOutMio6

|

Muxed IO pad / JTAG trst_n signal.

| +|

MIO7

|

BidirStd

|

VIO

|

muxed

|

tdi

|

kTopDarjeelingPinmuxInselMio7 / kTopDarjeelingPinmuxMioOutMio7

|

Muxed IO pad / JTAG tdi signal.

| +|

MIO8

|

BidirStd

|

VIO

|

muxed

|

tdo

|

kTopDarjeelingPinmuxInselMio8 / kTopDarjeelingPinmuxMioOutMio8

|

Muxed IO pad / JTAG tdo signal.

| +|

MIO9

|

BidirStd

|

VIO

|

muxed

|

-

|

kTopDarjeelingPinmuxInselMio9 / kTopDarjeelingPinmuxMioOutMio9

|

Muxed IO pad

| +|

MIO10

|

BidirStd

|

VIO

|

muxed

|

-

|

kTopDarjeelingPinmuxInselMio10 / kTopDarjeelingPinmuxMioOutMio10

|

Muxed IO pad

| +|

MIO11

|

BidirStd

|

VIO

|

muxed

|

-

|

kTopDarjeelingPinmuxInselMio11 / kTopDarjeelingPinmuxMioOutMio11

|

Muxed IO pad

| +## Pinmux Connectivity + +|

Module / Signal

|

Connection

|

Pad

|

Pinmux Outsel Constant / Peripheral Input Index

|

Description

| +|:------------------------------------------------------:|:---------------------------------------------:|:-------------------------------------------------:|:-------------------------------------------------------------------------------------:|:----------------------------------------------:| +|

spi_host0_sd[0]

|

direct

|

SPI_HOST_D0

|

- / -

|

| +|

spi_host0_sd[1]

|

direct

|

SPI_HOST_D1

|

- / -

|

| +|

spi_host0_sd[2]

|

direct

|

SPI_HOST_D2

|

- / -

|

| +|

spi_host0_sd[3]

|

direct

|

SPI_HOST_D3

|

- / -

|

| +|

spi_device_sd[0]

|

direct

|

SPI_DEV_D0

|

- / -

|

| +|

spi_device_sd[1]

|

direct

|

SPI_DEV_D1

|

- / -

|

| +|

spi_device_sd[2]

|

direct

|

SPI_DEV_D2

|

- / -

|

| +|

spi_device_sd[3]

|

direct

|

SPI_DEV_D3

|

- / -

|

| +|

i2c0_scl

|

direct

|

I2C_SCL

|

- / -

|

| +|

i2c0_sda

|

direct

|

I2C_SDA

|

- / -

|

| +|

gpio_gpio[0]

|

direct

|

GPIO0

|

- / -

|

| +|

gpio_gpio[1]

|

direct

|

GPIO1

|

- / -

|

| +|

gpio_gpio[2]

|

direct

|

GPIO2

|

- / -

|

| +|

gpio_gpio[3]

|

direct

|

GPIO3

|

- / -

|

| +|

gpio_gpio[4]

|

direct

|

GPIO4

|

- / -

|

| +|

gpio_gpio[5]

|

direct

|

GPIO5

|

- / -

|

| +|

gpio_gpio[6]

|

direct

|

GPIO6

|

- / -

|

| +|

gpio_gpio[7]

|

direct

|

GPIO7

|

- / -

|

| +|

gpio_gpio[8]

|

direct

|

GPIO8

|

- / -

|

| +|

gpio_gpio[9]

|

direct

|

GPIO9

|

- / -

|

| +|

gpio_gpio[10]

|

direct

|

GPIO10

|

- / -

|

| +|

gpio_gpio[11]

|

direct

|

GPIO11

|

- / -

|

| +|

gpio_gpio[12]

|

direct

|

GPIO12

|

- / -

|

| +|

gpio_gpio[13]

|

direct

|

GPIO13

|

- / -

|

| +|

gpio_gpio[14]

|

direct

|

GPIO14

|

- / -

|

| +|

gpio_gpio[15]

|

direct

|

GPIO15

|

- / -

|

| +|

gpio_gpio[16]

|

direct

|

GPIO16

|

- / -

|

| +|

gpio_gpio[17]

|

direct

|

GPIO17

|

- / -

|

| +|

gpio_gpio[18]

|

direct

|

GPIO18

|

- / -

|

| +|

gpio_gpio[19]

|

direct

|

GPIO19

|

- / -

|

| +|

gpio_gpio[20]

|

direct

|

GPIO20

|

- / -

|

| +|

gpio_gpio[21]

|

direct

|

GPIO21

|

- / -

|

| +|

gpio_gpio[22]

|

direct

|

GPIO22

|

- / -

|

| +|

gpio_gpio[23]

|

direct

|

GPIO23

|

- / -

|

| +|

gpio_gpio[24]

|

direct

|

GPIO24

|

- / -

|

| +|

gpio_gpio[25]

|

direct

|

GPIO25

|

- / -

|

| +|

gpio_gpio[26]

|

direct

|

GPIO26

|

- / -

|

| +|

gpio_gpio[27]

|

direct

|

GPIO27

|

- / -

|

| +|

gpio_gpio[28]

|

direct

|

GPIO28

|

- / -

|

| +|

gpio_gpio[29]

|

direct

|

GPIO29

|

- / -

|

| +|

gpio_gpio[30]

|

direct

|

GPIO30

|

- / -

|

| +|

gpio_gpio[31]

|

direct

|

GPIO31

|

- / -

|

| +|

spi_device_sck

|

direct

|

SPI_DEV_CLK

|

- / -

|

| +|

spi_device_csb

|

direct

|

SPI_DEV_CS_L

|

- / -

|

| +|

spi_device_tpm_csb

|

direct

|

SPI_DEV_TPM_CS_L

|

- / -

|

| +|

uart0_rx

|

direct

|

UART_RX

|

- / -

|

| +|

soc_proxy_soc_gpi[0]

|

direct

|

SOC_GPI0

|

- / -

|

| +|

soc_proxy_soc_gpi[1]

|

direct

|

SOC_GPI1

|

- / -

|

| +|

soc_proxy_soc_gpi[2]

|

direct

|

SOC_GPI2

|

- / -

|

| +|

soc_proxy_soc_gpi[3]

|

direct

|

SOC_GPI3

|

- / -

|

| +|

soc_proxy_soc_gpi[4]

|

direct

|

SOC_GPI4

|

- / -

|

| +|

soc_proxy_soc_gpi[5]

|

direct

|

SOC_GPI5

|

- / -

|

| +|

soc_proxy_soc_gpi[6]

|

direct

|

SOC_GPI6

|

- / -

|

| +|

soc_proxy_soc_gpi[7]

|

direct

|

SOC_GPI7

|

- / -

|

| +|

soc_proxy_soc_gpi[8]

|

direct

|

SOC_GPI8

|

- / -

|

| +|

soc_proxy_soc_gpi[9]

|

direct

|

SOC_GPI9

|

- / -

|

| +|

soc_proxy_soc_gpi[10]

|

direct

|

SOC_GPI10

|

- / -

|

| +|

soc_proxy_soc_gpi[11]

|

direct

|

SOC_GPI11

|

- / -

|

| +|

soc_proxy_soc_gpi[12]

|

muxed

|

-

|

- / kTopDarjeelingPinmuxPeripheralInSocProxySocGpi12

|

| +|

soc_proxy_soc_gpi[13]

|

muxed

|

-

|

- / kTopDarjeelingPinmuxPeripheralInSocProxySocGpi13

|

| +|

soc_proxy_soc_gpi[14]

|

muxed

|

-

|

- / kTopDarjeelingPinmuxPeripheralInSocProxySocGpi14

|

| +|

soc_proxy_soc_gpi[15]

|

muxed

|

-

|

- / kTopDarjeelingPinmuxPeripheralInSocProxySocGpi15

|

| +|

spi_host0_sck

|

direct

|

SPI_HOST_CLK

|

- / -

|

| +|

spi_host0_csb

|

direct

|

SPI_HOST_CS_L

|

- / -

|

| +|

uart0_tx

|

direct

|

UART_TX

|

- / -

|

| +|

soc_proxy_soc_gpo[0]

|

direct

|

SOC_GPO0

|

- / -

|

| +|

soc_proxy_soc_gpo[1]

|

direct

|

SOC_GPO1

|

- / -

|

| +|

soc_proxy_soc_gpo[2]

|

direct

|

SOC_GPO2

|

- / -

|

| +|

soc_proxy_soc_gpo[3]

|

direct

|

SOC_GPO3

|

- / -

|

| +|

soc_proxy_soc_gpo[4]

|

direct

|

SOC_GPO4

|

- / -

|

| +|

soc_proxy_soc_gpo[5]

|

direct

|

SOC_GPO5

|

- / -

|

| +|

soc_proxy_soc_gpo[6]

|

direct

|

SOC_GPO6

|

- / -

|

| +|

soc_proxy_soc_gpo[7]

|

direct

|

SOC_GPO7

|

- / -

|

| +|

soc_proxy_soc_gpo[8]

|

direct

|

SOC_GPO8

|

- / -

|

| +|

soc_proxy_soc_gpo[9]

|

direct

|

SOC_GPO9

|

- / -

|

| +|

soc_proxy_soc_gpo[10]

|

direct

|

SOC_GPO10

|

- / -

|

| +|

soc_proxy_soc_gpo[11]

|

direct

|

SOC_GPO11

|

- / -

|

| +|

soc_proxy_soc_gpo[12]

|

muxed

|

-

|

kTopDarjeelingPinmuxOutselSocProxySocGpo12 / -

|

| +|

soc_proxy_soc_gpo[13]

|

muxed

|

-

|

kTopDarjeelingPinmuxOutselSocProxySocGpo13 / -

|

| +|

soc_proxy_soc_gpo[14]

|

muxed

|

-

|

kTopDarjeelingPinmuxOutselSocProxySocGpo14 / -

|

| +|

soc_proxy_soc_gpo[15]

|

muxed

|

-

|

kTopDarjeelingPinmuxOutselSocProxySocGpo15 / -

|

| +|

otp_ctrl_test[0]

|

muxed

|

-

|

kTopDarjeelingPinmuxOutselOtpCtrlTest0 / -

|

| diff --git a/hw/top_darjeeling/ip_autogen/pinmux/doc/pinout_cw310.md b/hw/top_darjeeling/ip_autogen/pinmux/doc/pinout_cw310.md new file mode 100644 index 0000000000000..c650c25a924e9 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/doc/pinout_cw310.md @@ -0,0 +1,191 @@ +# "CW310" Target : Pinout and Pinmux Connectivity + +## Pinout Table + +|

Pad Name

|

Type

|

Bank

|

Connection

|

Special Function

|

Pinmux Insel Constant / Muxed Output Index

|

Description

| +|:-------------------------------------------------:|:-----------------------------------------:|:---------------------------------------:|:---------------------------------------------:|:---------------------------------------------------:|:-------------------------------------------------------------------------------------------------:|:--------------------------------------------------------------------:| +|

POR_N

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

System reset

| +|

JTAG_TCK

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TCK signal

| +|

JTAG_TMS

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TMS signal

| +|

JTAG_TDI

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TDI signal

| +|

JTAG_TDO

|

BidirStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TDO signal

| +|

JTAG_TRST_N

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TRST_N signal

| +|

SPI_HOST_D0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_CLK

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host clock

| +|

SPI_HOST_CS_L

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host chip select

| +|

SPI_DEV_D0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_CLK

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device clock

| +|

SPI_DEV_CS_L

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device chip select

| +|

SPI_DEV_TPM_CS_L

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device TPM chip select

| +|

UART_RX

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

UART receive

| +|

UART_TX

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

UART transmit

| +|

I2C_SCL

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

I2C clock

| +|

I2C_SDA

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

I2C data

| +|

GPIO0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO4

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO5

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO6

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO7

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO8

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO9

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO10

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO11

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO12

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO13

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO14

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO15

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO16

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO17

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO18

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO19

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO20

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO21

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO22

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO23

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO24

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO25

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO26

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO27

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO28

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO29

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO30

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO31

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

SOC_GPI0

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI1

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI2

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI3

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI4

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI5

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI6

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI7

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI8

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI9

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI10

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI11

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPO0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO4

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO5

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO6

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO7

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO8

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO9

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO10

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO11

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

MIO0

|

BidirStd

|

VIO

|

muxed

|

tap0

|

kTopDarjeelingPinmuxInselMio0 / kTopDarjeelingPinmuxMioOutMio0

|

Muxed IO pad / TAP strap signal.

| +|

MIO1

|

BidirStd

|

VIO

|

muxed

|

tap1

|

kTopDarjeelingPinmuxInselMio1 / kTopDarjeelingPinmuxMioOutMio1

|

Muxed IO pad / TAP strap signal.

| +|

MIO2

|

BidirStd

|

VIO

|

muxed

|

dft0

|

kTopDarjeelingPinmuxInselMio2 / kTopDarjeelingPinmuxMioOutMio2

|

Muxed IO pad / DFT strap signal.

| +|

MIO3

|

BidirStd

|

VIO

|

muxed

|

dft1

|

kTopDarjeelingPinmuxInselMio3 / kTopDarjeelingPinmuxMioOutMio3

|

Muxed IO pad / DFT strap signal.

| +|

MIO4

|

BidirStd

|

VIO

|

muxed

|

tck

|

kTopDarjeelingPinmuxInselMio4 / kTopDarjeelingPinmuxMioOutMio4

|

Muxed IO pad / JTAG tck signal.

| +|

MIO5

|

BidirStd

|

VIO

|

muxed

|

tms

|

kTopDarjeelingPinmuxInselMio5 / kTopDarjeelingPinmuxMioOutMio5

|

Muxed IO pad / JTAG tms signal.

| +|

MIO6

|

BidirStd

|

VIO

|

muxed

|

trst_n

|

kTopDarjeelingPinmuxInselMio6 / kTopDarjeelingPinmuxMioOutMio6

|

Muxed IO pad / JTAG trst_n signal.

| +|

MIO7

|

BidirStd

|

VIO

|

muxed

|

tdi

|

kTopDarjeelingPinmuxInselMio7 / kTopDarjeelingPinmuxMioOutMio7

|

Muxed IO pad / JTAG tdi signal.

| +|

MIO8

|

BidirStd

|

VIO

|

muxed

|

tdo

|

kTopDarjeelingPinmuxInselMio8 / kTopDarjeelingPinmuxMioOutMio8

|

Muxed IO pad / JTAG tdo signal.

| +|

MIO9

|

BidirStd

|

VIO

|

muxed

|

-

|

kTopDarjeelingPinmuxInselMio9 / kTopDarjeelingPinmuxMioOutMio9

|

Muxed IO pad

| +|

MIO10

|

BidirStd

|

VIO

|

muxed

|

-

|

kTopDarjeelingPinmuxInselMio10 / kTopDarjeelingPinmuxMioOutMio10

|

Muxed IO pad

| +|

MIO11

|

BidirStd

|

VIO

|

muxed

|

-

|

kTopDarjeelingPinmuxInselMio11 / kTopDarjeelingPinmuxMioOutMio11

|

Muxed IO pad

| +|

IO_CLK

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

Extra clock input for FPGA target

| +|

POR_BUTTON_N

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

Power-on reset button input

| +|

IO_CLKOUT

|

BidirStd

|

VIO

|

manual

|

-

|

- / -

|

Manual clock output for SCA setup

| +|

IO_TRIGGER

|

BidirStd

|

VIO

|

manual

|

-

|

- / -

|

Manual trigger output for SCA setup

| +## Pinmux Connectivity + +|

Module / Signal

|

Connection

|

Pad

|

Pinmux Outsel Constant / Peripheral Input Index

|

Description

| +|:------------------------------------------------------:|:---------------------------------------------:|:-------------------------------------------------:|:-------------------------------------------------------------------------------------:|:----------------------------------------------:| +|

spi_host0_sd[0]

|

direct

|

SPI_HOST_D0

|

- / -

|

| +|

spi_host0_sd[1]

|

direct

|

SPI_HOST_D1

|

- / -

|

| +|

spi_host0_sd[2]

|

direct

|

SPI_HOST_D2

|

- / -

|

| +|

spi_host0_sd[3]

|

direct

|

SPI_HOST_D3

|

- / -

|

| +|

spi_device_sd[0]

|

direct

|

SPI_DEV_D0

|

- / -

|

| +|

spi_device_sd[1]

|

direct

|

SPI_DEV_D1

|

- / -

|

| +|

spi_device_sd[2]

|

direct

|

SPI_DEV_D2

|

- / -

|

| +|

spi_device_sd[3]

|

direct

|

SPI_DEV_D3

|

- / -

|

| +|

i2c0_scl

|

direct

|

I2C_SCL

|

- / -

|

| +|

i2c0_sda

|

direct

|

I2C_SDA

|

- / -

|

| +|

gpio_gpio[0]

|

direct

|

GPIO0

|

- / -

|

| +|

gpio_gpio[1]

|

direct

|

GPIO1

|

- / -

|

| +|

gpio_gpio[2]

|

direct

|

GPIO2

|

- / -

|

| +|

gpio_gpio[3]

|

direct

|

GPIO3

|

- / -

|

| +|

gpio_gpio[4]

|

direct

|

GPIO4

|

- / -

|

| +|

gpio_gpio[5]

|

direct

|

GPIO5

|

- / -

|

| +|

gpio_gpio[6]

|

direct

|

GPIO6

|

- / -

|

| +|

gpio_gpio[7]

|

direct

|

GPIO7

|

- / -

|

| +|

gpio_gpio[8]

|

direct

|

GPIO8

|

- / -

|

| +|

gpio_gpio[9]

|

direct

|

GPIO9

|

- / -

|

| +|

gpio_gpio[10]

|

direct

|

GPIO10

|

- / -

|

| +|

gpio_gpio[11]

|

direct

|

GPIO11

|

- / -

|

| +|

gpio_gpio[12]

|

direct

|

GPIO12

|

- / -

|

| +|

gpio_gpio[13]

|

direct

|

GPIO13

|

- / -

|

| +|

gpio_gpio[14]

|

direct

|

GPIO14

|

- / -

|

| +|

gpio_gpio[15]

|

direct

|

GPIO15

|

- / -

|

| +|

gpio_gpio[16]

|

direct

|

GPIO16

|

- / -

|

| +|

gpio_gpio[17]

|

direct

|

GPIO17

|

- / -

|

| +|

gpio_gpio[18]

|

direct

|

GPIO18

|

- / -

|

| +|

gpio_gpio[19]

|

direct

|

GPIO19

|

- / -

|

| +|

gpio_gpio[20]

|

direct

|

GPIO20

|

- / -

|

| +|

gpio_gpio[21]

|

direct

|

GPIO21

|

- / -

|

| +|

gpio_gpio[22]

|

direct

|

GPIO22

|

- / -

|

| +|

gpio_gpio[23]

|

direct

|

GPIO23

|

- / -

|

| +|

gpio_gpio[24]

|

direct

|

GPIO24

|

- / -

|

| +|

gpio_gpio[25]

|

direct

|

GPIO25

|

- / -

|

| +|

gpio_gpio[26]

|

direct

|

GPIO26

|

- / -

|

| +|

gpio_gpio[27]

|

direct

|

GPIO27

|

- / -

|

| +|

gpio_gpio[28]

|

direct

|

GPIO28

|

- / -

|

| +|

gpio_gpio[29]

|

direct

|

GPIO29

|

- / -

|

| +|

gpio_gpio[30]

|

direct

|

GPIO30

|

- / -

|

| +|

gpio_gpio[31]

|

direct

|

GPIO31

|

- / -

|

| +|

spi_device_sck

|

direct

|

SPI_DEV_CLK

|

- / -

|

| +|

spi_device_csb

|

direct

|

SPI_DEV_CS_L

|

- / -

|

| +|

spi_device_tpm_csb

|

direct

|

SPI_DEV_TPM_CS_L

|

- / -

|

| +|

uart0_rx

|

direct

|

UART_RX

|

- / -

|

| +|

soc_proxy_soc_gpi[0]

|

direct

|

SOC_GPI0

|

- / -

|

| +|

soc_proxy_soc_gpi[1]

|

direct

|

SOC_GPI1

|

- / -

|

| +|

soc_proxy_soc_gpi[2]

|

direct

|

SOC_GPI2

|

- / -

|

| +|

soc_proxy_soc_gpi[3]

|

direct

|

SOC_GPI3

|

- / -

|

| +|

soc_proxy_soc_gpi[4]

|

direct

|

SOC_GPI4

|

- / -

|

| +|

soc_proxy_soc_gpi[5]

|

direct

|

SOC_GPI5

|

- / -

|

| +|

soc_proxy_soc_gpi[6]

|

direct

|

SOC_GPI6

|

- / -

|

| +|

soc_proxy_soc_gpi[7]

|

direct

|

SOC_GPI7

|

- / -

|

| +|

soc_proxy_soc_gpi[8]

|

direct

|

SOC_GPI8

|

- / -

|

| +|

soc_proxy_soc_gpi[9]

|

direct

|

SOC_GPI9

|

- / -

|

| +|

soc_proxy_soc_gpi[10]

|

direct

|

SOC_GPI10

|

- / -

|

| +|

soc_proxy_soc_gpi[11]

|

direct

|

SOC_GPI11

|

- / -

|

| +|

soc_proxy_soc_gpi[12]

|

muxed

|

-

|

- / kTopDarjeelingPinmuxPeripheralInSocProxySocGpi12

|

| +|

soc_proxy_soc_gpi[13]

|

muxed

|

-

|

- / kTopDarjeelingPinmuxPeripheralInSocProxySocGpi13

|

| +|

soc_proxy_soc_gpi[14]

|

muxed

|

-

|

- / kTopDarjeelingPinmuxPeripheralInSocProxySocGpi14

|

| +|

soc_proxy_soc_gpi[15]

|

muxed

|

-

|

- / kTopDarjeelingPinmuxPeripheralInSocProxySocGpi15

|

| +|

spi_host0_sck

|

direct

|

SPI_HOST_CLK

|

- / -

|

| +|

spi_host0_csb

|

direct

|

SPI_HOST_CS_L

|

- / -

|

| +|

uart0_tx

|

direct

|

UART_TX

|

- / -

|

| +|

soc_proxy_soc_gpo[0]

|

direct

|

SOC_GPO0

|

- / -

|

| +|

soc_proxy_soc_gpo[1]

|

direct

|

SOC_GPO1

|

- / -

|

| +|

soc_proxy_soc_gpo[2]

|

direct

|

SOC_GPO2

|

- / -

|

| +|

soc_proxy_soc_gpo[3]

|

direct

|

SOC_GPO3

|

- / -

|

| +|

soc_proxy_soc_gpo[4]

|

direct

|

SOC_GPO4

|

- / -

|

| +|

soc_proxy_soc_gpo[5]

|

direct

|

SOC_GPO5

|

- / -

|

| +|

soc_proxy_soc_gpo[6]

|

direct

|

SOC_GPO6

|

- / -

|

| +|

soc_proxy_soc_gpo[7]

|

direct

|

SOC_GPO7

|

- / -

|

| +|

soc_proxy_soc_gpo[8]

|

direct

|

SOC_GPO8

|

- / -

|

| +|

soc_proxy_soc_gpo[9]

|

direct

|

SOC_GPO9

|

- / -

|

| +|

soc_proxy_soc_gpo[10]

|

direct

|

SOC_GPO10

|

- / -

|

| +|

soc_proxy_soc_gpo[11]

|

direct

|

SOC_GPO11

|

- / -

|

| +|

soc_proxy_soc_gpo[12]

|

muxed

|

-

|

kTopDarjeelingPinmuxOutselSocProxySocGpo12 / -

|

| +|

soc_proxy_soc_gpo[13]

|

muxed

|

-

|

kTopDarjeelingPinmuxOutselSocProxySocGpo13 / -

|

| +|

soc_proxy_soc_gpo[14]

|

muxed

|

-

|

kTopDarjeelingPinmuxOutselSocProxySocGpo14 / -

|

| +|

soc_proxy_soc_gpo[15]

|

muxed

|

-

|

kTopDarjeelingPinmuxOutselSocProxySocGpo15 / -

|

| +|

otp_ctrl_test[0]

|

muxed

|

-

|

kTopDarjeelingPinmuxOutselOtpCtrlTest0 / -

|

| diff --git a/hw/top_darjeeling/ip_autogen/pinmux/doc/programmers_guide.md b/hw/top_darjeeling/ip_autogen/pinmux/doc/programmers_guide.md new file mode 100644 index 0000000000000..6bff0cd858749 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/doc/programmers_guide.md @@ -0,0 +1,115 @@ +# Programmer's Guide + +## Pad Attributes + +Software should determine and program the pad attributes at startup, or reprogram the attributes when the functionality requirements change at runtime. + +This can be achieved by writing to the [`MIO_PAD_ATTR_0`](registers.md#mio_pad_attr) and [`DIO_PAD_ATTR_0`](registers.md#dio_pad_attr) registers. +Note that the IO attributes should be configured before enabling muxed IOs going through the `pinmux` matrix in order to avoid undesired electrical behavior and/or contention at the pads. + +The pad attributes configuration can be locked down individually for each pad via the [`MIO_PAD_ATTR_REGWEN_0`](registers.md#mio_pad_attr_regwen) and [`DIO_PAD_ATTR_REGWEN_0`](registers.md#dio_pad_attr_regwen) registers. +The configuration can then not be altered anymore until the next system reset. + +The following pad attributes are supported by this register layout by default: + +ATTR Bits | Description | Access +----------|-----------------------------------------------|--------- +0 | Input/output inversion | WARL +1 | Virtual open drain enable | WARL +2 | Pull enable | WARL +3 | Pull select (0: down, 1: up) | WARL +4 | Keeper enable | WARL +5 | Schmitt trigger enable | WARL +6 | Open drain enable | WARL +8:7 | Slew rate (0x0: slowest, 0x3: fastest) | WARL +12:9 | Drive strength (0x0: weakest, 0xf: strongest) | WARL + +Since some of the pad attributes may not be implemented, SW can probe this capability by writing the CSRs and read them back to determine whether the value was legal. +This behavior is also referred to as "writes-any-reads-legal" or "WARL" in the RISC-V world. +For example, certain pads may only support two drive-strength bits, instead of four. +The unsupported drive-strength bits in the corresponding CSRs would then always read as zero, even if SW attempts to set them to 1. + +## Pinmux Configuration + +Upon POR, the `pinmux` state is such that all MIO outputs are high-Z, and all MIO peripheral inputs are tied off to 0. +Software should determine and program the `pinmux` mapping at startup, or reprogram it when the functionality requirements change at runtime. +This can be achieved by writing the following values to the [`PERIPH_INSEL_0`](registers.md#periph_insel_0) and [`MIO_OUTSEL_0`](registers.md#mio_outsel) registers. + +`periph_insel` Value | Selected Input Signal +----------------------|----------------------- +0 | Constant zero (default) +1 | Constant one +2 + k | Corresponding MIO input signal at index k + +The global default at reset is `0`, but the default of individual signals can be overridden at design time, if needed. + +`mio_outsel` Value | Selected Output signal +----------------------|----------------------- +0 | Constant zero (default) +1 | Constant one +2 | High-Z +3 + k | Corresponding peripheral output signal at index k + +The global default at reset is `2`, but the default of individual signals can be overridden at design time, if needed. + +Note that the `pinmux` configuration should be sequenced after any IO attribute-specific configuration in the [`MIO_PAD_ATTR_0`](registers.md#mio_pad_attr) and [`DIO_PAD_ATTR_0`](registers.md#dio_pad_attr) registers to avoid any unwanted electric behavior and/or contention. +If needed, each select signal can be individually locked down via [`MIO_PERIPH_INSEL_REGWEN_0`](registers.md#mio_periph_insel_regwen) or [`MIO_OUTSEL_REGWEN_0`](registers.md#mio_outsel_regwen). +The configuration can then not be altered anymore until the next system reset. + +## Sleep Features + +The sleep behavior of each individual MIO or DIO can be defined via the (registers.md#mio_pad_sleep_en), [`DIO_PAD_SLEEP_EN_0`](registers.md#dio_pad_sleep_en), [`MIO_PAD_SLEEP_MODE_0`](registers.md#mio_pad_sleep_mode) and [`DIO_PAD_SLEEP_MODE_0`](registers.md#dio_pad_sleep_mode)) registers. +Available sleep behaviors are: + +`dio/mio_pad_sleep_en` Value | `dio/mio_pad_sleep_mode` Value | Sleep Behavior +------------------------------|--------------------------------|----------------------- +0 | - | Drive (default) +1 | 0 | Tie-low +1 | 1 | Tie-high +1 | 2 | High-Z +1 | 3 | Keep last value + +Note that if the behavior is set to "Drive", the sleep mode will not be activated upon sleep entry. +Rather, the retention logic continues to drive the value coming from the peripheral side. +Also note that the sleep logic is located after the `pinmux` matrix, hence the sleep configuration is per MIO pad and not per MIO peripheral. + +Before sleep entry, SW should configure the appropriate sleep behavior of all MIOs/DIOs via [`MIO_PAD_SLEEP_MODE_0`](registers.md#mio_pad_sleep_mode), [`DIO_PAD_SLEEP_MODE_0`](registers.md#dio_pad_sleep_mode). +This configuration can be optionally locked down, in which case it cannot be modified again until POR. +The configured behavior is then activated for all pads that have sleep mode set to enabled (registers.md#mio_pad_sleep_en) and [`DIO_PAD_SLEEP_EN_0`](registers.md#dio_pad_sleep_en)) at once by the power manager during the sleep entry sequence. + +When exiting sleep, the task of disabling the sleep behavior is however up to SW. +I.e., it must clear the per-pad sleep status bits in registers [`MIO_PAD_SLEEP_STATUS_0`](registers.md#mio_pad_sleep_status) and [`DIO_PAD_SLEEP_STATUS_0`](registers.md#dio_pad_sleep_status) that have been set upon sleep entry. +The rationale for this is that it may not be desirable to disable sleep behavior on all pads at once due to some additional book keeping / re-initialization that needs to be performed while exiting sleep. + +## Wakeup Features + +The `pinmux` contains eight wakeup detectors. +These detectors can be individually enabled and disabled regardless of the sleep state. +This ensures that SW can set them up before and disable them after sleep in order to ensure that no events are missed during sleep entry and exit. + +For more information on the patterns supported by the wakeup detectors, see [wakeup detectors](theory_of_operation.md#wakeup-detectors). + +A typical programming sequence for the wakeup detectors looks as follows: + +1. Before initiating any sleep mode, SW should configure the wakeup detectors appropriately and enable them via the [`WKUP_DETECTOR_0`](registers.md#wkup_detector), [`WKUP_DETECTOR_CNT_TH_0`](registers.md#wkup_detector_cnt_th) and [`WKUP_DETECTOR_PADSEL_0`](registers.md#wkup_detector_padsel) registers. + +2. Optionally, lock the wakeup detector configuration via the [`WKUP_DETECTOR_REGWEN_0`](registers.md#wkup_detector_regwen) registers. + +3. During sleep, the wakeup detectors will trigger a wakeup request if a matching pattern has been observed. + A bit corresponding to the wakeup detector that has observed the pattern will be set in the [`WKUP_CAUSE`](registers.md#wkup_cause) register. + +4. When exiting sleep, SW should read the wake info register in the [power manager](../../pwrmgr/README.md) to determine the reason(s) for the wakeup request. + +5. If the wakeup request was due to a pin wakeup pattern detector, SW should inspect the [`WKUP_CAUSE`](registers.md#wkup_cause) registers in order to determine the exact cause. + +6. SW should in any case disable the wakeup detectors and clear the [`WKUP_CAUSE`](registers.md#wkup_cause) registers once it is safe to do so (in order to not miss any events). + Note that the [`WKUP_CAUSE`](registers.md#wkup_cause) registers reside in the slow AON clock domain, and hence clearing them takes a few uS to take effect. + If needed, a SW readback can be performed to ensure that the clear operation has completed successfully. + +## Pinout and Pinmux Mapping + +Please see the specific documentation for detailed pinout and pinmux mapping tables for [this top](../doc/targets.md). + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_pinmux.h) diff --git a/hw/top_darjeeling/ip_autogen/pinmux/doc/registers.md b/hw/top_darjeeling/ip_autogen/pinmux/doc/registers.md new file mode 100644 index 0000000000000..f605ef842d8ea --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/doc/registers.md @@ -0,0 +1,1805 @@ +# Registers + + +## Summary + +| Name | Offset | Length | Description | +|:---------------------------------------------------------------|:---------|---------:|:--------------------------------------------------------------------| +| pinmux.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | +| pinmux.[`MIO_PERIPH_INSEL_REGWEN_0`](#mio_periph_insel_regwen) | 0x4 | 4 | Register write enable for MIO peripheral input selects. | +| pinmux.[`MIO_PERIPH_INSEL_REGWEN_1`](#mio_periph_insel_regwen) | 0x8 | 4 | Register write enable for MIO peripheral input selects. | +| pinmux.[`MIO_PERIPH_INSEL_REGWEN_2`](#mio_periph_insel_regwen) | 0xc | 4 | Register write enable for MIO peripheral input selects. | +| pinmux.[`MIO_PERIPH_INSEL_REGWEN_3`](#mio_periph_insel_regwen) | 0x10 | 4 | Register write enable for MIO peripheral input selects. | +| pinmux.[`MIO_PERIPH_INSEL_0`](#mio_periph_insel) | 0x14 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_1`](#mio_periph_insel) | 0x18 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_2`](#mio_periph_insel) | 0x1c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_3`](#mio_periph_insel) | 0x20 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_OUTSEL_REGWEN_0`](#mio_outsel_regwen) | 0x24 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_1`](#mio_outsel_regwen) | 0x28 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_2`](#mio_outsel_regwen) | 0x2c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_3`](#mio_outsel_regwen) | 0x30 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_4`](#mio_outsel_regwen) | 0x34 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_5`](#mio_outsel_regwen) | 0x38 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_6`](#mio_outsel_regwen) | 0x3c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_7`](#mio_outsel_regwen) | 0x40 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_8`](#mio_outsel_regwen) | 0x44 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_9`](#mio_outsel_regwen) | 0x48 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_10`](#mio_outsel_regwen) | 0x4c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_11`](#mio_outsel_regwen) | 0x50 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_0`](#mio_outsel) | 0x54 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_1`](#mio_outsel) | 0x58 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_2`](#mio_outsel) | 0x5c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_3`](#mio_outsel) | 0x60 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_4`](#mio_outsel) | 0x64 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_5`](#mio_outsel) | 0x68 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_6`](#mio_outsel) | 0x6c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_7`](#mio_outsel) | 0x70 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_8`](#mio_outsel) | 0x74 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_9`](#mio_outsel) | 0x78 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_10`](#mio_outsel) | 0x7c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_11`](#mio_outsel) | 0x80 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_0`](#mio_pad_attr_regwen) | 0x84 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_1`](#mio_pad_attr_regwen) | 0x88 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_2`](#mio_pad_attr_regwen) | 0x8c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_3`](#mio_pad_attr_regwen) | 0x90 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_4`](#mio_pad_attr_regwen) | 0x94 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_5`](#mio_pad_attr_regwen) | 0x98 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_6`](#mio_pad_attr_regwen) | 0x9c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_7`](#mio_pad_attr_regwen) | 0xa0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_8`](#mio_pad_attr_regwen) | 0xa4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_9`](#mio_pad_attr_regwen) | 0xa8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_10`](#mio_pad_attr_regwen) | 0xac | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_11`](#mio_pad_attr_regwen) | 0xb0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_0`](#mio_pad_attr) | 0xb4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_1`](#mio_pad_attr) | 0xb8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_2`](#mio_pad_attr) | 0xbc | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_3`](#mio_pad_attr) | 0xc0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_4`](#mio_pad_attr) | 0xc4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_5`](#mio_pad_attr) | 0xc8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_6`](#mio_pad_attr) | 0xcc | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_7`](#mio_pad_attr) | 0xd0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_8`](#mio_pad_attr) | 0xd4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_9`](#mio_pad_attr) | 0xd8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_10`](#mio_pad_attr) | 0xdc | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_11`](#mio_pad_attr) | 0xe0 | 4 | Muxed pad attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_0`](#dio_pad_attr_regwen) | 0xe4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_1`](#dio_pad_attr_regwen) | 0xe8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_2`](#dio_pad_attr_regwen) | 0xec | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_3`](#dio_pad_attr_regwen) | 0xf0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_4`](#dio_pad_attr_regwen) | 0xf4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_5`](#dio_pad_attr_regwen) | 0xf8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_6`](#dio_pad_attr_regwen) | 0xfc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_7`](#dio_pad_attr_regwen) | 0x100 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_8`](#dio_pad_attr_regwen) | 0x104 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_9`](#dio_pad_attr_regwen) | 0x108 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_10`](#dio_pad_attr_regwen) | 0x10c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_11`](#dio_pad_attr_regwen) | 0x110 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_12`](#dio_pad_attr_regwen) | 0x114 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_13`](#dio_pad_attr_regwen) | 0x118 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_14`](#dio_pad_attr_regwen) | 0x11c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_15`](#dio_pad_attr_regwen) | 0x120 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_16`](#dio_pad_attr_regwen) | 0x124 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_17`](#dio_pad_attr_regwen) | 0x128 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_18`](#dio_pad_attr_regwen) | 0x12c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_19`](#dio_pad_attr_regwen) | 0x130 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_20`](#dio_pad_attr_regwen) | 0x134 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_21`](#dio_pad_attr_regwen) | 0x138 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_22`](#dio_pad_attr_regwen) | 0x13c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_23`](#dio_pad_attr_regwen) | 0x140 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_24`](#dio_pad_attr_regwen) | 0x144 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_25`](#dio_pad_attr_regwen) | 0x148 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_26`](#dio_pad_attr_regwen) | 0x14c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_27`](#dio_pad_attr_regwen) | 0x150 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_28`](#dio_pad_attr_regwen) | 0x154 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_29`](#dio_pad_attr_regwen) | 0x158 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_30`](#dio_pad_attr_regwen) | 0x15c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_31`](#dio_pad_attr_regwen) | 0x160 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_32`](#dio_pad_attr_regwen) | 0x164 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_33`](#dio_pad_attr_regwen) | 0x168 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_34`](#dio_pad_attr_regwen) | 0x16c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_35`](#dio_pad_attr_regwen) | 0x170 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_36`](#dio_pad_attr_regwen) | 0x174 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_37`](#dio_pad_attr_regwen) | 0x178 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_38`](#dio_pad_attr_regwen) | 0x17c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_39`](#dio_pad_attr_regwen) | 0x180 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_40`](#dio_pad_attr_regwen) | 0x184 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_41`](#dio_pad_attr_regwen) | 0x188 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_42`](#dio_pad_attr_regwen) | 0x18c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_43`](#dio_pad_attr_regwen) | 0x190 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_44`](#dio_pad_attr_regwen) | 0x194 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_45`](#dio_pad_attr_regwen) | 0x198 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_46`](#dio_pad_attr_regwen) | 0x19c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_47`](#dio_pad_attr_regwen) | 0x1a0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_48`](#dio_pad_attr_regwen) | 0x1a4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_49`](#dio_pad_attr_regwen) | 0x1a8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_50`](#dio_pad_attr_regwen) | 0x1ac | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_51`](#dio_pad_attr_regwen) | 0x1b0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_52`](#dio_pad_attr_regwen) | 0x1b4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_53`](#dio_pad_attr_regwen) | 0x1b8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_54`](#dio_pad_attr_regwen) | 0x1bc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_55`](#dio_pad_attr_regwen) | 0x1c0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_56`](#dio_pad_attr_regwen) | 0x1c4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_57`](#dio_pad_attr_regwen) | 0x1c8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_58`](#dio_pad_attr_regwen) | 0x1cc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_59`](#dio_pad_attr_regwen) | 0x1d0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_60`](#dio_pad_attr_regwen) | 0x1d4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_61`](#dio_pad_attr_regwen) | 0x1d8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_62`](#dio_pad_attr_regwen) | 0x1dc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_63`](#dio_pad_attr_regwen) | 0x1e0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_64`](#dio_pad_attr_regwen) | 0x1e4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_65`](#dio_pad_attr_regwen) | 0x1e8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_66`](#dio_pad_attr_regwen) | 0x1ec | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_67`](#dio_pad_attr_regwen) | 0x1f0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_68`](#dio_pad_attr_regwen) | 0x1f4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_69`](#dio_pad_attr_regwen) | 0x1f8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_70`](#dio_pad_attr_regwen) | 0x1fc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_71`](#dio_pad_attr_regwen) | 0x200 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_72`](#dio_pad_attr_regwen) | 0x204 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_0`](#dio_pad_attr) | 0x208 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_1`](#dio_pad_attr) | 0x20c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_2`](#dio_pad_attr) | 0x210 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_3`](#dio_pad_attr) | 0x214 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_4`](#dio_pad_attr) | 0x218 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_5`](#dio_pad_attr) | 0x21c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_6`](#dio_pad_attr) | 0x220 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_7`](#dio_pad_attr) | 0x224 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_8`](#dio_pad_attr) | 0x228 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_9`](#dio_pad_attr) | 0x22c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_10`](#dio_pad_attr) | 0x230 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_11`](#dio_pad_attr) | 0x234 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_12`](#dio_pad_attr) | 0x238 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_13`](#dio_pad_attr) | 0x23c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_14`](#dio_pad_attr) | 0x240 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_15`](#dio_pad_attr) | 0x244 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_16`](#dio_pad_attr) | 0x248 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_17`](#dio_pad_attr) | 0x24c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_18`](#dio_pad_attr) | 0x250 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_19`](#dio_pad_attr) | 0x254 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_20`](#dio_pad_attr) | 0x258 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_21`](#dio_pad_attr) | 0x25c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_22`](#dio_pad_attr) | 0x260 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_23`](#dio_pad_attr) | 0x264 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_24`](#dio_pad_attr) | 0x268 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_25`](#dio_pad_attr) | 0x26c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_26`](#dio_pad_attr) | 0x270 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_27`](#dio_pad_attr) | 0x274 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_28`](#dio_pad_attr) | 0x278 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_29`](#dio_pad_attr) | 0x27c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_30`](#dio_pad_attr) | 0x280 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_31`](#dio_pad_attr) | 0x284 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_32`](#dio_pad_attr) | 0x288 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_33`](#dio_pad_attr) | 0x28c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_34`](#dio_pad_attr) | 0x290 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_35`](#dio_pad_attr) | 0x294 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_36`](#dio_pad_attr) | 0x298 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_37`](#dio_pad_attr) | 0x29c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_38`](#dio_pad_attr) | 0x2a0 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_39`](#dio_pad_attr) | 0x2a4 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_40`](#dio_pad_attr) | 0x2a8 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_41`](#dio_pad_attr) | 0x2ac | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_42`](#dio_pad_attr) | 0x2b0 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_43`](#dio_pad_attr) | 0x2b4 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_44`](#dio_pad_attr) | 0x2b8 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_45`](#dio_pad_attr) | 0x2bc | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_46`](#dio_pad_attr) | 0x2c0 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_47`](#dio_pad_attr) | 0x2c4 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_48`](#dio_pad_attr) | 0x2c8 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_49`](#dio_pad_attr) | 0x2cc | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_50`](#dio_pad_attr) | 0x2d0 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_51`](#dio_pad_attr) | 0x2d4 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_52`](#dio_pad_attr) | 0x2d8 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_53`](#dio_pad_attr) | 0x2dc | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_54`](#dio_pad_attr) | 0x2e0 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_55`](#dio_pad_attr) | 0x2e4 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_56`](#dio_pad_attr) | 0x2e8 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_57`](#dio_pad_attr) | 0x2ec | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_58`](#dio_pad_attr) | 0x2f0 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_59`](#dio_pad_attr) | 0x2f4 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_60`](#dio_pad_attr) | 0x2f8 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_61`](#dio_pad_attr) | 0x2fc | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_62`](#dio_pad_attr) | 0x300 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_63`](#dio_pad_attr) | 0x304 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_64`](#dio_pad_attr) | 0x308 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_65`](#dio_pad_attr) | 0x30c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_66`](#dio_pad_attr) | 0x310 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_67`](#dio_pad_attr) | 0x314 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_68`](#dio_pad_attr) | 0x318 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_69`](#dio_pad_attr) | 0x31c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_70`](#dio_pad_attr) | 0x320 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_71`](#dio_pad_attr) | 0x324 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_72`](#dio_pad_attr) | 0x328 | 4 | Dedicated pad attributes. | +| pinmux.[`MIO_PAD_SLEEP_STATUS`](#MIO_PAD_SLEEP_STATUS) | 0x32c | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_0`](#mio_pad_sleep_regwen) | 0x330 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_1`](#mio_pad_sleep_regwen) | 0x334 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_2`](#mio_pad_sleep_regwen) | 0x338 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_3`](#mio_pad_sleep_regwen) | 0x33c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_4`](#mio_pad_sleep_regwen) | 0x340 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_5`](#mio_pad_sleep_regwen) | 0x344 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_6`](#mio_pad_sleep_regwen) | 0x348 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_7`](#mio_pad_sleep_regwen) | 0x34c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_8`](#mio_pad_sleep_regwen) | 0x350 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_9`](#mio_pad_sleep_regwen) | 0x354 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_10`](#mio_pad_sleep_regwen) | 0x358 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_11`](#mio_pad_sleep_regwen) | 0x35c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_EN_0`](#mio_pad_sleep_en) | 0x360 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_1`](#mio_pad_sleep_en) | 0x364 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_2`](#mio_pad_sleep_en) | 0x368 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_3`](#mio_pad_sleep_en) | 0x36c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_4`](#mio_pad_sleep_en) | 0x370 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_5`](#mio_pad_sleep_en) | 0x374 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_6`](#mio_pad_sleep_en) | 0x378 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_7`](#mio_pad_sleep_en) | 0x37c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_8`](#mio_pad_sleep_en) | 0x380 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_9`](#mio_pad_sleep_en) | 0x384 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_10`](#mio_pad_sleep_en) | 0x388 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_11`](#mio_pad_sleep_en) | 0x38c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_0`](#mio_pad_sleep_mode) | 0x390 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_1`](#mio_pad_sleep_mode) | 0x394 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_2`](#mio_pad_sleep_mode) | 0x398 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_3`](#mio_pad_sleep_mode) | 0x39c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_4`](#mio_pad_sleep_mode) | 0x3a0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_5`](#mio_pad_sleep_mode) | 0x3a4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_6`](#mio_pad_sleep_mode) | 0x3a8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_7`](#mio_pad_sleep_mode) | 0x3ac | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_8`](#mio_pad_sleep_mode) | 0x3b0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_9`](#mio_pad_sleep_mode) | 0x3b4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_10`](#mio_pad_sleep_mode) | 0x3b8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_11`](#mio_pad_sleep_mode) | 0x3bc | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`DIO_PAD_SLEEP_STATUS_0`](#DIO_PAD_SLEEP_STATUS_0) | 0x3c0 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`DIO_PAD_SLEEP_STATUS_1`](#DIO_PAD_SLEEP_STATUS_1) | 0x3c4 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`DIO_PAD_SLEEP_STATUS_2`](#DIO_PAD_SLEEP_STATUS_2) | 0x3c8 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_0`](#dio_pad_sleep_regwen) | 0x3cc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_1`](#dio_pad_sleep_regwen) | 0x3d0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_2`](#dio_pad_sleep_regwen) | 0x3d4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_3`](#dio_pad_sleep_regwen) | 0x3d8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_4`](#dio_pad_sleep_regwen) | 0x3dc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_5`](#dio_pad_sleep_regwen) | 0x3e0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_6`](#dio_pad_sleep_regwen) | 0x3e4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_7`](#dio_pad_sleep_regwen) | 0x3e8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_8`](#dio_pad_sleep_regwen) | 0x3ec | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_9`](#dio_pad_sleep_regwen) | 0x3f0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_10`](#dio_pad_sleep_regwen) | 0x3f4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_11`](#dio_pad_sleep_regwen) | 0x3f8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_12`](#dio_pad_sleep_regwen) | 0x3fc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_13`](#dio_pad_sleep_regwen) | 0x400 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_14`](#dio_pad_sleep_regwen) | 0x404 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_15`](#dio_pad_sleep_regwen) | 0x408 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_16`](#dio_pad_sleep_regwen) | 0x40c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_17`](#dio_pad_sleep_regwen) | 0x410 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_18`](#dio_pad_sleep_regwen) | 0x414 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_19`](#dio_pad_sleep_regwen) | 0x418 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_20`](#dio_pad_sleep_regwen) | 0x41c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_21`](#dio_pad_sleep_regwen) | 0x420 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_22`](#dio_pad_sleep_regwen) | 0x424 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_23`](#dio_pad_sleep_regwen) | 0x428 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_24`](#dio_pad_sleep_regwen) | 0x42c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_25`](#dio_pad_sleep_regwen) | 0x430 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_26`](#dio_pad_sleep_regwen) | 0x434 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_27`](#dio_pad_sleep_regwen) | 0x438 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_28`](#dio_pad_sleep_regwen) | 0x43c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_29`](#dio_pad_sleep_regwen) | 0x440 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_30`](#dio_pad_sleep_regwen) | 0x444 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_31`](#dio_pad_sleep_regwen) | 0x448 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_32`](#dio_pad_sleep_regwen) | 0x44c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_33`](#dio_pad_sleep_regwen) | 0x450 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_34`](#dio_pad_sleep_regwen) | 0x454 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_35`](#dio_pad_sleep_regwen) | 0x458 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_36`](#dio_pad_sleep_regwen) | 0x45c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_37`](#dio_pad_sleep_regwen) | 0x460 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_38`](#dio_pad_sleep_regwen) | 0x464 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_39`](#dio_pad_sleep_regwen) | 0x468 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_40`](#dio_pad_sleep_regwen) | 0x46c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_41`](#dio_pad_sleep_regwen) | 0x470 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_42`](#dio_pad_sleep_regwen) | 0x474 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_43`](#dio_pad_sleep_regwen) | 0x478 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_44`](#dio_pad_sleep_regwen) | 0x47c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_45`](#dio_pad_sleep_regwen) | 0x480 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_46`](#dio_pad_sleep_regwen) | 0x484 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_47`](#dio_pad_sleep_regwen) | 0x488 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_48`](#dio_pad_sleep_regwen) | 0x48c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_49`](#dio_pad_sleep_regwen) | 0x490 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_50`](#dio_pad_sleep_regwen) | 0x494 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_51`](#dio_pad_sleep_regwen) | 0x498 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_52`](#dio_pad_sleep_regwen) | 0x49c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_53`](#dio_pad_sleep_regwen) | 0x4a0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_54`](#dio_pad_sleep_regwen) | 0x4a4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_55`](#dio_pad_sleep_regwen) | 0x4a8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_56`](#dio_pad_sleep_regwen) | 0x4ac | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_57`](#dio_pad_sleep_regwen) | 0x4b0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_58`](#dio_pad_sleep_regwen) | 0x4b4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_59`](#dio_pad_sleep_regwen) | 0x4b8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_60`](#dio_pad_sleep_regwen) | 0x4bc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_61`](#dio_pad_sleep_regwen) | 0x4c0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_62`](#dio_pad_sleep_regwen) | 0x4c4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_63`](#dio_pad_sleep_regwen) | 0x4c8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_64`](#dio_pad_sleep_regwen) | 0x4cc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_65`](#dio_pad_sleep_regwen) | 0x4d0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_66`](#dio_pad_sleep_regwen) | 0x4d4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_67`](#dio_pad_sleep_regwen) | 0x4d8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_68`](#dio_pad_sleep_regwen) | 0x4dc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_69`](#dio_pad_sleep_regwen) | 0x4e0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_70`](#dio_pad_sleep_regwen) | 0x4e4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_71`](#dio_pad_sleep_regwen) | 0x4e8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_72`](#dio_pad_sleep_regwen) | 0x4ec | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_EN_0`](#dio_pad_sleep_en) | 0x4f0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_1`](#dio_pad_sleep_en) | 0x4f4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_2`](#dio_pad_sleep_en) | 0x4f8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_3`](#dio_pad_sleep_en) | 0x4fc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_4`](#dio_pad_sleep_en) | 0x500 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_5`](#dio_pad_sleep_en) | 0x504 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_6`](#dio_pad_sleep_en) | 0x508 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_7`](#dio_pad_sleep_en) | 0x50c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_8`](#dio_pad_sleep_en) | 0x510 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_9`](#dio_pad_sleep_en) | 0x514 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_10`](#dio_pad_sleep_en) | 0x518 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_11`](#dio_pad_sleep_en) | 0x51c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_12`](#dio_pad_sleep_en) | 0x520 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_13`](#dio_pad_sleep_en) | 0x524 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_14`](#dio_pad_sleep_en) | 0x528 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_15`](#dio_pad_sleep_en) | 0x52c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_16`](#dio_pad_sleep_en) | 0x530 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_17`](#dio_pad_sleep_en) | 0x534 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_18`](#dio_pad_sleep_en) | 0x538 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_19`](#dio_pad_sleep_en) | 0x53c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_20`](#dio_pad_sleep_en) | 0x540 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_21`](#dio_pad_sleep_en) | 0x544 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_22`](#dio_pad_sleep_en) | 0x548 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_23`](#dio_pad_sleep_en) | 0x54c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_24`](#dio_pad_sleep_en) | 0x550 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_25`](#dio_pad_sleep_en) | 0x554 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_26`](#dio_pad_sleep_en) | 0x558 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_27`](#dio_pad_sleep_en) | 0x55c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_28`](#dio_pad_sleep_en) | 0x560 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_29`](#dio_pad_sleep_en) | 0x564 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_30`](#dio_pad_sleep_en) | 0x568 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_31`](#dio_pad_sleep_en) | 0x56c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_32`](#dio_pad_sleep_en) | 0x570 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_33`](#dio_pad_sleep_en) | 0x574 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_34`](#dio_pad_sleep_en) | 0x578 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_35`](#dio_pad_sleep_en) | 0x57c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_36`](#dio_pad_sleep_en) | 0x580 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_37`](#dio_pad_sleep_en) | 0x584 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_38`](#dio_pad_sleep_en) | 0x588 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_39`](#dio_pad_sleep_en) | 0x58c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_40`](#dio_pad_sleep_en) | 0x590 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_41`](#dio_pad_sleep_en) | 0x594 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_42`](#dio_pad_sleep_en) | 0x598 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_43`](#dio_pad_sleep_en) | 0x59c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_44`](#dio_pad_sleep_en) | 0x5a0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_45`](#dio_pad_sleep_en) | 0x5a4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_46`](#dio_pad_sleep_en) | 0x5a8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_47`](#dio_pad_sleep_en) | 0x5ac | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_48`](#dio_pad_sleep_en) | 0x5b0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_49`](#dio_pad_sleep_en) | 0x5b4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_50`](#dio_pad_sleep_en) | 0x5b8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_51`](#dio_pad_sleep_en) | 0x5bc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_52`](#dio_pad_sleep_en) | 0x5c0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_53`](#dio_pad_sleep_en) | 0x5c4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_54`](#dio_pad_sleep_en) | 0x5c8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_55`](#dio_pad_sleep_en) | 0x5cc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_56`](#dio_pad_sleep_en) | 0x5d0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_57`](#dio_pad_sleep_en) | 0x5d4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_58`](#dio_pad_sleep_en) | 0x5d8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_59`](#dio_pad_sleep_en) | 0x5dc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_60`](#dio_pad_sleep_en) | 0x5e0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_61`](#dio_pad_sleep_en) | 0x5e4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_62`](#dio_pad_sleep_en) | 0x5e8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_63`](#dio_pad_sleep_en) | 0x5ec | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_64`](#dio_pad_sleep_en) | 0x5f0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_65`](#dio_pad_sleep_en) | 0x5f4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_66`](#dio_pad_sleep_en) | 0x5f8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_67`](#dio_pad_sleep_en) | 0x5fc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_68`](#dio_pad_sleep_en) | 0x600 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_69`](#dio_pad_sleep_en) | 0x604 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_70`](#dio_pad_sleep_en) | 0x608 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_71`](#dio_pad_sleep_en) | 0x60c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_72`](#dio_pad_sleep_en) | 0x610 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_0`](#dio_pad_sleep_mode) | 0x614 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_1`](#dio_pad_sleep_mode) | 0x618 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_2`](#dio_pad_sleep_mode) | 0x61c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_3`](#dio_pad_sleep_mode) | 0x620 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_4`](#dio_pad_sleep_mode) | 0x624 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_5`](#dio_pad_sleep_mode) | 0x628 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_6`](#dio_pad_sleep_mode) | 0x62c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_7`](#dio_pad_sleep_mode) | 0x630 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_8`](#dio_pad_sleep_mode) | 0x634 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_9`](#dio_pad_sleep_mode) | 0x638 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_10`](#dio_pad_sleep_mode) | 0x63c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_11`](#dio_pad_sleep_mode) | 0x640 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_12`](#dio_pad_sleep_mode) | 0x644 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_13`](#dio_pad_sleep_mode) | 0x648 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_14`](#dio_pad_sleep_mode) | 0x64c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_15`](#dio_pad_sleep_mode) | 0x650 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_16`](#dio_pad_sleep_mode) | 0x654 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_17`](#dio_pad_sleep_mode) | 0x658 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_18`](#dio_pad_sleep_mode) | 0x65c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_19`](#dio_pad_sleep_mode) | 0x660 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_20`](#dio_pad_sleep_mode) | 0x664 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_21`](#dio_pad_sleep_mode) | 0x668 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_22`](#dio_pad_sleep_mode) | 0x66c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_23`](#dio_pad_sleep_mode) | 0x670 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_24`](#dio_pad_sleep_mode) | 0x674 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_25`](#dio_pad_sleep_mode) | 0x678 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_26`](#dio_pad_sleep_mode) | 0x67c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_27`](#dio_pad_sleep_mode) | 0x680 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_28`](#dio_pad_sleep_mode) | 0x684 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_29`](#dio_pad_sleep_mode) | 0x688 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_30`](#dio_pad_sleep_mode) | 0x68c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_31`](#dio_pad_sleep_mode) | 0x690 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_32`](#dio_pad_sleep_mode) | 0x694 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_33`](#dio_pad_sleep_mode) | 0x698 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_34`](#dio_pad_sleep_mode) | 0x69c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_35`](#dio_pad_sleep_mode) | 0x6a0 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_36`](#dio_pad_sleep_mode) | 0x6a4 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_37`](#dio_pad_sleep_mode) | 0x6a8 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_38`](#dio_pad_sleep_mode) | 0x6ac | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_39`](#dio_pad_sleep_mode) | 0x6b0 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_40`](#dio_pad_sleep_mode) | 0x6b4 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_41`](#dio_pad_sleep_mode) | 0x6b8 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_42`](#dio_pad_sleep_mode) | 0x6bc | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_43`](#dio_pad_sleep_mode) | 0x6c0 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_44`](#dio_pad_sleep_mode) | 0x6c4 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_45`](#dio_pad_sleep_mode) | 0x6c8 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_46`](#dio_pad_sleep_mode) | 0x6cc | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_47`](#dio_pad_sleep_mode) | 0x6d0 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_48`](#dio_pad_sleep_mode) | 0x6d4 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_49`](#dio_pad_sleep_mode) | 0x6d8 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_50`](#dio_pad_sleep_mode) | 0x6dc | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_51`](#dio_pad_sleep_mode) | 0x6e0 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_52`](#dio_pad_sleep_mode) | 0x6e4 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_53`](#dio_pad_sleep_mode) | 0x6e8 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_54`](#dio_pad_sleep_mode) | 0x6ec | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_55`](#dio_pad_sleep_mode) | 0x6f0 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_56`](#dio_pad_sleep_mode) | 0x6f4 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_57`](#dio_pad_sleep_mode) | 0x6f8 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_58`](#dio_pad_sleep_mode) | 0x6fc | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_59`](#dio_pad_sleep_mode) | 0x700 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_60`](#dio_pad_sleep_mode) | 0x704 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_61`](#dio_pad_sleep_mode) | 0x708 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_62`](#dio_pad_sleep_mode) | 0x70c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_63`](#dio_pad_sleep_mode) | 0x710 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_64`](#dio_pad_sleep_mode) | 0x714 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_65`](#dio_pad_sleep_mode) | 0x718 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_66`](#dio_pad_sleep_mode) | 0x71c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_67`](#dio_pad_sleep_mode) | 0x720 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_68`](#dio_pad_sleep_mode) | 0x724 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_69`](#dio_pad_sleep_mode) | 0x728 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_70`](#dio_pad_sleep_mode) | 0x72c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_71`](#dio_pad_sleep_mode) | 0x730 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_72`](#dio_pad_sleep_mode) | 0x734 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`WKUP_DETECTOR_REGWEN_0`](#wkup_detector_regwen) | 0x738 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_1`](#wkup_detector_regwen) | 0x73c | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_2`](#wkup_detector_regwen) | 0x740 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_3`](#wkup_detector_regwen) | 0x744 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_4`](#wkup_detector_regwen) | 0x748 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_5`](#wkup_detector_regwen) | 0x74c | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_6`](#wkup_detector_regwen) | 0x750 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_7`](#wkup_detector_regwen) | 0x754 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_0`](#wkup_detector_en) | 0x758 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_1`](#wkup_detector_en) | 0x75c | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_2`](#wkup_detector_en) | 0x760 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_3`](#wkup_detector_en) | 0x764 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_4`](#wkup_detector_en) | 0x768 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_5`](#wkup_detector_en) | 0x76c | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_6`](#wkup_detector_en) | 0x770 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_7`](#wkup_detector_en) | 0x774 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_0`](#wkup_detector) | 0x778 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_1`](#wkup_detector) | 0x77c | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_2`](#wkup_detector) | 0x780 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_3`](#wkup_detector) | 0x784 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_4`](#wkup_detector) | 0x788 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_5`](#wkup_detector) | 0x78c | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_6`](#wkup_detector) | 0x790 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_7`](#wkup_detector) | 0x794 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_0`](#wkup_detector_cnt_th) | 0x798 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_1`](#wkup_detector_cnt_th) | 0x79c | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_2`](#wkup_detector_cnt_th) | 0x7a0 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_3`](#wkup_detector_cnt_th) | 0x7a4 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_4`](#wkup_detector_cnt_th) | 0x7a8 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_5`](#wkup_detector_cnt_th) | 0x7ac | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_6`](#wkup_detector_cnt_th) | 0x7b0 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_7`](#wkup_detector_cnt_th) | 0x7b4 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_0`](#wkup_detector_padsel) | 0x7b8 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_1`](#wkup_detector_padsel) | 0x7bc | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_2`](#wkup_detector_padsel) | 0x7c0 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_3`](#wkup_detector_padsel) | 0x7c4 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_4`](#wkup_detector_padsel) | 0x7c8 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_5`](#wkup_detector_padsel) | 0x7cc | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_6`](#wkup_detector_padsel) | 0x7d0 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_7`](#wkup_detector_padsel) | 0x7d4 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_CAUSE`](#WKUP_CAUSE) | 0x7d8 | 4 | Cause registers for wakeup detectors. | + +## ALERT_TEST +Alert Test Register +- Offset: `0x0` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:-------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | + +## MIO_PERIPH_INSEL_REGWEN +Register write enable for MIO peripheral input selects. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:--------------------------|:---------| +| MIO_PERIPH_INSEL_REGWEN_0 | 0x4 | +| MIO_PERIPH_INSEL_REGWEN_1 | 0x8 | +| MIO_PERIPH_INSEL_REGWEN_2 | 0xc | +| MIO_PERIPH_INSEL_REGWEN_3 | 0x10 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding MIO_PERIPH_INSEL is not writable anymore. | + +## MIO_PERIPH_INSEL +For each peripheral input, this selects the muxable pad input. +- Reset default: `0x0` +- Reset mask: `0xf` + +### Instances + +| Name | Offset | +|:-------------------|:---------| +| MIO_PERIPH_INSEL_0 | 0x14 | +| MIO_PERIPH_INSEL_1 | 0x18 | +| MIO_PERIPH_INSEL_2 | 0x1c | +| MIO_PERIPH_INSEL_3 | 0x20 | + + +### Fields + +```wavejson +{"reg": [{"name": "IN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3:0 | rw | 0x0 | IN | 0: tie constantly to zero, 1: tie constantly to 1, >=2: MIO pads (i.e., add 2 to the native MIO pad index). | + +## MIO_OUTSEL_REGWEN +Register write enable for MIO output selects. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:---------------------|:---------| +| MIO_OUTSEL_REGWEN_0 | 0x24 | +| MIO_OUTSEL_REGWEN_1 | 0x28 | +| MIO_OUTSEL_REGWEN_2 | 0x2c | +| MIO_OUTSEL_REGWEN_3 | 0x30 | +| MIO_OUTSEL_REGWEN_4 | 0x34 | +| MIO_OUTSEL_REGWEN_5 | 0x38 | +| MIO_OUTSEL_REGWEN_6 | 0x3c | +| MIO_OUTSEL_REGWEN_7 | 0x40 | +| MIO_OUTSEL_REGWEN_8 | 0x44 | +| MIO_OUTSEL_REGWEN_9 | 0x48 | +| MIO_OUTSEL_REGWEN_10 | 0x4c | +| MIO_OUTSEL_REGWEN_11 | 0x50 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding MIO_OUTSEL is not writable anymore. | + +## MIO_OUTSEL +For each muxable pad, this selects the peripheral output. +- Reset default: `0x2` +- Reset mask: `0x7` + +### Instances + +| Name | Offset | +|:--------------|:---------| +| MIO_OUTSEL_0 | 0x54 | +| MIO_OUTSEL_1 | 0x58 | +| MIO_OUTSEL_2 | 0x5c | +| MIO_OUTSEL_3 | 0x60 | +| MIO_OUTSEL_4 | 0x64 | +| MIO_OUTSEL_5 | 0x68 | +| MIO_OUTSEL_6 | 0x6c | +| MIO_OUTSEL_7 | 0x70 | +| MIO_OUTSEL_8 | 0x74 | +| MIO_OUTSEL_9 | 0x78 | +| MIO_OUTSEL_10 | 0x7c | +| MIO_OUTSEL_11 | 0x80 | + + +### Fields + +```wavejson +{"reg": [{"name": "OUT", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------| +| 31:3 | | | | Reserved | +| 2:0 | rw | 0x2 | OUT | 0: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index). | + +## MIO_PAD_ATTR_REGWEN +Register write enable for MIO PAD attributes. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:-----------------------|:---------| +| MIO_PAD_ATTR_REGWEN_0 | 0x84 | +| MIO_PAD_ATTR_REGWEN_1 | 0x88 | +| MIO_PAD_ATTR_REGWEN_2 | 0x8c | +| MIO_PAD_ATTR_REGWEN_3 | 0x90 | +| MIO_PAD_ATTR_REGWEN_4 | 0x94 | +| MIO_PAD_ATTR_REGWEN_5 | 0x98 | +| MIO_PAD_ATTR_REGWEN_6 | 0x9c | +| MIO_PAD_ATTR_REGWEN_7 | 0xa0 | +| MIO_PAD_ATTR_REGWEN_8 | 0xa4 | +| MIO_PAD_ATTR_REGWEN_9 | 0xa8 | +| MIO_PAD_ATTR_REGWEN_10 | 0xac | +| MIO_PAD_ATTR_REGWEN_11 | 0xb0 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding [`MIO_PAD_ATTR`](#mio_pad_attr) is not writable anymore. | + +## MIO_PAD_ATTR +Muxed pad attributes. +This register has WARL behavior since not each pad type may support +all attributes. +The muxed pad that is used for TAP strap 0 has a different reset value, with `pull_en` set to 1. +- Reset default: `0x0` +- Reset mask: `0xf300ff` + +### Instances + +| Name | Offset | +|:----------------|:---------| +| MIO_PAD_ATTR_0 | 0xb4 | +| MIO_PAD_ATTR_1 | 0xb8 | +| MIO_PAD_ATTR_2 | 0xbc | +| MIO_PAD_ATTR_3 | 0xc0 | +| MIO_PAD_ATTR_4 | 0xc4 | +| MIO_PAD_ATTR_5 | 0xc8 | +| MIO_PAD_ATTR_6 | 0xcc | +| MIO_PAD_ATTR_7 | 0xd0 | +| MIO_PAD_ATTR_8 | 0xd4 | +| MIO_PAD_ATTR_9 | 0xd8 | +| MIO_PAD_ATTR_10 | 0xdc | +| MIO_PAD_ATTR_11 | 0xe0 | + + +### Fields + +```wavejson +{"reg": [{"name": "invert", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "virtual_od_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pull_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pull_select", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "keeper_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "schmitt_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "od_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "input_disable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 8}, {"name": "slew_rate", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 2}, {"name": "drive_strength", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:------------------------------------------------| +| 31:24 | | | Reserved | +| 23:20 | rw | 0x0 | [drive_strength](#mio_pad_attr--drive_strength) | +| 19:18 | | | Reserved | +| 17:16 | rw | 0x0 | [slew_rate](#mio_pad_attr--slew_rate) | +| 15:8 | | | Reserved | +| 7 | rw | 0x0 | [input_disable](#mio_pad_attr--input_disable) | +| 6 | rw | 0x0 | [od_en](#mio_pad_attr--od_en) | +| 5 | rw | 0x0 | [schmitt_en](#mio_pad_attr--schmitt_en) | +| 4 | rw | 0x0 | [keeper_en](#mio_pad_attr--keeper_en) | +| 3 | rw | 0x0 | [pull_select](#mio_pad_attr--pull_select) | +| 2 | rw | 0x0 | [pull_en](#mio_pad_attr--pull_en) | +| 1 | rw | 0x0 | [virtual_od_en](#mio_pad_attr--virtual_od_en) | +| 0 | rw | 0x0 | [invert](#mio_pad_attr--invert) | + +### MIO_PAD_ATTR . drive_strength +Drive strength (0x0: weakest, 0xf: strongest) + +### MIO_PAD_ATTR . slew_rate +Slew rate (0x0: slowest, 0x3: fastest). + +### MIO_PAD_ATTR . input_disable +Disable input drivers. +Setting this to 1 for pads that are not used as input can reduce their leakage current. + +### MIO_PAD_ATTR . od_en +Enable open drain. + +### MIO_PAD_ATTR . schmitt_en +Enable the schmitt trigger. + +### MIO_PAD_ATTR . keeper_en +Enable keeper termination. This weakly drives the previous pad output value when output is disabled, similar to a verilog `trireg`. + +### MIO_PAD_ATTR . pull_select +Pull select (0: pull-down, 1: pull-up). + +| Value | Name | Description | +|:--------|:----------|:-------------------------------| +| 0x0 | pull_down | Select the pull-down resistor. | +| 0x1 | pull_up | Select the pull-up resistor. | + + +### MIO_PAD_ATTR . pull_en +Enable pull-up or pull-down resistor. + +### MIO_PAD_ATTR . virtual_od_en +Enable virtual open drain. + +### MIO_PAD_ATTR . invert +Invert input and output levels. + +## DIO_PAD_ATTR_REGWEN +Register write enable for DIO PAD attributes. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:-----------------------|:---------| +| DIO_PAD_ATTR_REGWEN_0 | 0xe4 | +| DIO_PAD_ATTR_REGWEN_1 | 0xe8 | +| DIO_PAD_ATTR_REGWEN_2 | 0xec | +| DIO_PAD_ATTR_REGWEN_3 | 0xf0 | +| DIO_PAD_ATTR_REGWEN_4 | 0xf4 | +| DIO_PAD_ATTR_REGWEN_5 | 0xf8 | +| DIO_PAD_ATTR_REGWEN_6 | 0xfc | +| DIO_PAD_ATTR_REGWEN_7 | 0x100 | +| DIO_PAD_ATTR_REGWEN_8 | 0x104 | +| DIO_PAD_ATTR_REGWEN_9 | 0x108 | +| DIO_PAD_ATTR_REGWEN_10 | 0x10c | +| DIO_PAD_ATTR_REGWEN_11 | 0x110 | +| DIO_PAD_ATTR_REGWEN_12 | 0x114 | +| DIO_PAD_ATTR_REGWEN_13 | 0x118 | +| DIO_PAD_ATTR_REGWEN_14 | 0x11c | +| DIO_PAD_ATTR_REGWEN_15 | 0x120 | +| DIO_PAD_ATTR_REGWEN_16 | 0x124 | +| DIO_PAD_ATTR_REGWEN_17 | 0x128 | +| DIO_PAD_ATTR_REGWEN_18 | 0x12c | +| DIO_PAD_ATTR_REGWEN_19 | 0x130 | +| DIO_PAD_ATTR_REGWEN_20 | 0x134 | +| DIO_PAD_ATTR_REGWEN_21 | 0x138 | +| DIO_PAD_ATTR_REGWEN_22 | 0x13c | +| DIO_PAD_ATTR_REGWEN_23 | 0x140 | +| DIO_PAD_ATTR_REGWEN_24 | 0x144 | +| DIO_PAD_ATTR_REGWEN_25 | 0x148 | +| DIO_PAD_ATTR_REGWEN_26 | 0x14c | +| DIO_PAD_ATTR_REGWEN_27 | 0x150 | +| DIO_PAD_ATTR_REGWEN_28 | 0x154 | +| DIO_PAD_ATTR_REGWEN_29 | 0x158 | +| DIO_PAD_ATTR_REGWEN_30 | 0x15c | +| DIO_PAD_ATTR_REGWEN_31 | 0x160 | +| DIO_PAD_ATTR_REGWEN_32 | 0x164 | +| DIO_PAD_ATTR_REGWEN_33 | 0x168 | +| DIO_PAD_ATTR_REGWEN_34 | 0x16c | +| DIO_PAD_ATTR_REGWEN_35 | 0x170 | +| DIO_PAD_ATTR_REGWEN_36 | 0x174 | +| DIO_PAD_ATTR_REGWEN_37 | 0x178 | +| DIO_PAD_ATTR_REGWEN_38 | 0x17c | +| DIO_PAD_ATTR_REGWEN_39 | 0x180 | +| DIO_PAD_ATTR_REGWEN_40 | 0x184 | +| DIO_PAD_ATTR_REGWEN_41 | 0x188 | +| DIO_PAD_ATTR_REGWEN_42 | 0x18c | +| DIO_PAD_ATTR_REGWEN_43 | 0x190 | +| DIO_PAD_ATTR_REGWEN_44 | 0x194 | +| DIO_PAD_ATTR_REGWEN_45 | 0x198 | +| DIO_PAD_ATTR_REGWEN_46 | 0x19c | +| DIO_PAD_ATTR_REGWEN_47 | 0x1a0 | +| DIO_PAD_ATTR_REGWEN_48 | 0x1a4 | +| DIO_PAD_ATTR_REGWEN_49 | 0x1a8 | +| DIO_PAD_ATTR_REGWEN_50 | 0x1ac | +| DIO_PAD_ATTR_REGWEN_51 | 0x1b0 | +| DIO_PAD_ATTR_REGWEN_52 | 0x1b4 | +| DIO_PAD_ATTR_REGWEN_53 | 0x1b8 | +| DIO_PAD_ATTR_REGWEN_54 | 0x1bc | +| DIO_PAD_ATTR_REGWEN_55 | 0x1c0 | +| DIO_PAD_ATTR_REGWEN_56 | 0x1c4 | +| DIO_PAD_ATTR_REGWEN_57 | 0x1c8 | +| DIO_PAD_ATTR_REGWEN_58 | 0x1cc | +| DIO_PAD_ATTR_REGWEN_59 | 0x1d0 | +| DIO_PAD_ATTR_REGWEN_60 | 0x1d4 | +| DIO_PAD_ATTR_REGWEN_61 | 0x1d8 | +| DIO_PAD_ATTR_REGWEN_62 | 0x1dc | +| DIO_PAD_ATTR_REGWEN_63 | 0x1e0 | +| DIO_PAD_ATTR_REGWEN_64 | 0x1e4 | +| DIO_PAD_ATTR_REGWEN_65 | 0x1e8 | +| DIO_PAD_ATTR_REGWEN_66 | 0x1ec | +| DIO_PAD_ATTR_REGWEN_67 | 0x1f0 | +| DIO_PAD_ATTR_REGWEN_68 | 0x1f4 | +| DIO_PAD_ATTR_REGWEN_69 | 0x1f8 | +| DIO_PAD_ATTR_REGWEN_70 | 0x1fc | +| DIO_PAD_ATTR_REGWEN_71 | 0x200 | +| DIO_PAD_ATTR_REGWEN_72 | 0x204 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding [`DIO_PAD_ATTR`](#dio_pad_attr) is not writable anymore. | + +## DIO_PAD_ATTR +Dedicated pad attributes. +This register has WARL behavior since not each pad type may support +all attributes. +- Reset default: `0x0` +- Reset mask: `0xf300ff` + +### Instances + +| Name | Offset | +|:----------------|:---------| +| DIO_PAD_ATTR_0 | 0x208 | +| DIO_PAD_ATTR_1 | 0x20c | +| DIO_PAD_ATTR_2 | 0x210 | +| DIO_PAD_ATTR_3 | 0x214 | +| DIO_PAD_ATTR_4 | 0x218 | +| DIO_PAD_ATTR_5 | 0x21c | +| DIO_PAD_ATTR_6 | 0x220 | +| DIO_PAD_ATTR_7 | 0x224 | +| DIO_PAD_ATTR_8 | 0x228 | +| DIO_PAD_ATTR_9 | 0x22c | +| DIO_PAD_ATTR_10 | 0x230 | +| DIO_PAD_ATTR_11 | 0x234 | +| DIO_PAD_ATTR_12 | 0x238 | +| DIO_PAD_ATTR_13 | 0x23c | +| DIO_PAD_ATTR_14 | 0x240 | +| DIO_PAD_ATTR_15 | 0x244 | +| DIO_PAD_ATTR_16 | 0x248 | +| DIO_PAD_ATTR_17 | 0x24c | +| DIO_PAD_ATTR_18 | 0x250 | +| DIO_PAD_ATTR_19 | 0x254 | +| DIO_PAD_ATTR_20 | 0x258 | +| DIO_PAD_ATTR_21 | 0x25c | +| DIO_PAD_ATTR_22 | 0x260 | +| DIO_PAD_ATTR_23 | 0x264 | +| DIO_PAD_ATTR_24 | 0x268 | +| DIO_PAD_ATTR_25 | 0x26c | +| DIO_PAD_ATTR_26 | 0x270 | +| DIO_PAD_ATTR_27 | 0x274 | +| DIO_PAD_ATTR_28 | 0x278 | +| DIO_PAD_ATTR_29 | 0x27c | +| DIO_PAD_ATTR_30 | 0x280 | +| DIO_PAD_ATTR_31 | 0x284 | +| DIO_PAD_ATTR_32 | 0x288 | +| DIO_PAD_ATTR_33 | 0x28c | +| DIO_PAD_ATTR_34 | 0x290 | +| DIO_PAD_ATTR_35 | 0x294 | +| DIO_PAD_ATTR_36 | 0x298 | +| DIO_PAD_ATTR_37 | 0x29c | +| DIO_PAD_ATTR_38 | 0x2a0 | +| DIO_PAD_ATTR_39 | 0x2a4 | +| DIO_PAD_ATTR_40 | 0x2a8 | +| DIO_PAD_ATTR_41 | 0x2ac | +| DIO_PAD_ATTR_42 | 0x2b0 | +| DIO_PAD_ATTR_43 | 0x2b4 | +| DIO_PAD_ATTR_44 | 0x2b8 | +| DIO_PAD_ATTR_45 | 0x2bc | +| DIO_PAD_ATTR_46 | 0x2c0 | +| DIO_PAD_ATTR_47 | 0x2c4 | +| DIO_PAD_ATTR_48 | 0x2c8 | +| DIO_PAD_ATTR_49 | 0x2cc | +| DIO_PAD_ATTR_50 | 0x2d0 | +| DIO_PAD_ATTR_51 | 0x2d4 | +| DIO_PAD_ATTR_52 | 0x2d8 | +| DIO_PAD_ATTR_53 | 0x2dc | +| DIO_PAD_ATTR_54 | 0x2e0 | +| DIO_PAD_ATTR_55 | 0x2e4 | +| DIO_PAD_ATTR_56 | 0x2e8 | +| DIO_PAD_ATTR_57 | 0x2ec | +| DIO_PAD_ATTR_58 | 0x2f0 | +| DIO_PAD_ATTR_59 | 0x2f4 | +| DIO_PAD_ATTR_60 | 0x2f8 | +| DIO_PAD_ATTR_61 | 0x2fc | +| DIO_PAD_ATTR_62 | 0x300 | +| DIO_PAD_ATTR_63 | 0x304 | +| DIO_PAD_ATTR_64 | 0x308 | +| DIO_PAD_ATTR_65 | 0x30c | +| DIO_PAD_ATTR_66 | 0x310 | +| DIO_PAD_ATTR_67 | 0x314 | +| DIO_PAD_ATTR_68 | 0x318 | +| DIO_PAD_ATTR_69 | 0x31c | +| DIO_PAD_ATTR_70 | 0x320 | +| DIO_PAD_ATTR_71 | 0x324 | +| DIO_PAD_ATTR_72 | 0x328 | + + +### Fields + +```wavejson +{"reg": [{"name": "invert", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "virtual_od_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pull_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pull_select", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "keeper_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "schmitt_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "od_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "input_disable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 8}, {"name": "slew_rate", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 2}, {"name": "drive_strength", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:------------------------------------------------| +| 31:24 | | | Reserved | +| 23:20 | rw | 0x0 | [drive_strength](#dio_pad_attr--drive_strength) | +| 19:18 | | | Reserved | +| 17:16 | rw | 0x0 | [slew_rate](#dio_pad_attr--slew_rate) | +| 15:8 | | | Reserved | +| 7 | rw | 0x0 | [input_disable](#dio_pad_attr--input_disable) | +| 6 | rw | 0x0 | [od_en](#dio_pad_attr--od_en) | +| 5 | rw | 0x0 | [schmitt_en](#dio_pad_attr--schmitt_en) | +| 4 | rw | 0x0 | [keeper_en](#dio_pad_attr--keeper_en) | +| 3 | rw | 0x0 | [pull_select](#dio_pad_attr--pull_select) | +| 2 | rw | 0x0 | [pull_en](#dio_pad_attr--pull_en) | +| 1 | rw | 0x0 | [virtual_od_en](#dio_pad_attr--virtual_od_en) | +| 0 | rw | 0x0 | [invert](#dio_pad_attr--invert) | + +### DIO_PAD_ATTR . drive_strength +Drive strength (0x0: weakest, 0xf: strongest) + +### DIO_PAD_ATTR . slew_rate +Slew rate (0x0: slowest, 0x3: fastest). + +### DIO_PAD_ATTR . input_disable +Disable input drivers. +Setting this to 1 for pads that are not used as input can reduce their leakage current. + +### DIO_PAD_ATTR . od_en +Enable open drain. + +### DIO_PAD_ATTR . schmitt_en +Enable the schmitt trigger. + +### DIO_PAD_ATTR . keeper_en +Enable keeper termination. This weakly drives the previous pad output value when output is disabled, similar to a verilog `trireg`. + +### DIO_PAD_ATTR . pull_select +Pull select (0: pull-down, 1: pull-up). + +| Value | Name | Description | +|:--------|:----------|:-------------------------------| +| 0x0 | pull_down | Select the pull-down resistor. | +| 0x1 | pull_up | Select the pull-up resistor. | + + +### DIO_PAD_ATTR . pull_en +Enable pull-up or pull-down resistor. + +### DIO_PAD_ATTR . virtual_od_en +Enable virtual open drain. + +### DIO_PAD_ATTR . invert +Invert input and output levels. + +## MIO_PAD_SLEEP_STATUS +Register indicating whether the corresponding pad is in sleep mode. +- Offset: `0x32c` +- Reset default: `0x0` +- Reset mask: `0xfff` + +### Fields + +```wavejson +{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_2", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_3", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_4", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_5", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_6", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_7", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_8", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_9", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_10", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_11", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:12 | | | | Reserved | +| 11 | rw0c | 0x0 | EN_11 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 10 | rw0c | 0x0 | EN_10 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 9 | rw0c | 0x0 | EN_9 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 8 | rw0c | 0x0 | EN_8 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 7 | rw0c | 0x0 | EN_7 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 6 | rw0c | 0x0 | EN_6 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 5 | rw0c | 0x0 | EN_5 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 4 | rw0c | 0x0 | EN_4 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 3 | rw0c | 0x0 | EN_3 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 2 | rw0c | 0x0 | EN_2 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 1 | rw0c | 0x0 | EN_1 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 0 | rw0c | 0x0 | EN_0 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | + +## MIO_PAD_SLEEP_REGWEN +Register write enable for MIO sleep value configuration. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:------------------------|:---------| +| MIO_PAD_SLEEP_REGWEN_0 | 0x330 | +| MIO_PAD_SLEEP_REGWEN_1 | 0x334 | +| MIO_PAD_SLEEP_REGWEN_2 | 0x338 | +| MIO_PAD_SLEEP_REGWEN_3 | 0x33c | +| MIO_PAD_SLEEP_REGWEN_4 | 0x340 | +| MIO_PAD_SLEEP_REGWEN_5 | 0x344 | +| MIO_PAD_SLEEP_REGWEN_6 | 0x348 | +| MIO_PAD_SLEEP_REGWEN_7 | 0x34c | +| MIO_PAD_SLEEP_REGWEN_8 | 0x350 | +| MIO_PAD_SLEEP_REGWEN_9 | 0x354 | +| MIO_PAD_SLEEP_REGWEN_10 | 0x358 | +| MIO_PAD_SLEEP_REGWEN_11 | 0x35c | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding [`MIO_PAD_SLEEP_MODE`](#mio_pad_sleep_mode) is not writable anymore. | + +## MIO_PAD_SLEEP_EN +Enables the sleep mode of the corresponding muxed pad. +- Reset default: `0x0` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:--------------------|:---------| +| MIO_PAD_SLEEP_EN_0 | 0x360 | +| MIO_PAD_SLEEP_EN_1 | 0x364 | +| MIO_PAD_SLEEP_EN_2 | 0x368 | +| MIO_PAD_SLEEP_EN_3 | 0x36c | +| MIO_PAD_SLEEP_EN_4 | 0x370 | +| MIO_PAD_SLEEP_EN_5 | 0x374 | +| MIO_PAD_SLEEP_EN_6 | 0x378 | +| MIO_PAD_SLEEP_EN_7 | 0x37c | +| MIO_PAD_SLEEP_EN_8 | 0x380 | +| MIO_PAD_SLEEP_EN_9 | 0x384 | +| MIO_PAD_SLEEP_EN_10 | 0x388 | +| MIO_PAD_SLEEP_EN_11 | 0x38c | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:----------------------------| +| 31:1 | | | Reserved | +| 0 | rw | 0x0 | [EN](#mio_pad_sleep_en--en) | + +### MIO_PAD_SLEEP_EN . EN +Deep sleep mode enable. +If this bit is set to 1 the corresponding pad will enable the sleep behavior +specified in [`MIO_PAD_SLEEP_MODE`](#mio_pad_sleep_mode) upon deep sleep entry, and the corresponding bit +in [`MIO_PAD_SLEEP_STATUS`](#mio_pad_sleep_status) will be set to 1. +The pad remains in deep sleep mode until the corresponding bit in +[`MIO_PAD_SLEEP_STATUS`](#mio_pad_sleep_status) is cleared by SW. +Note that if an always on peripheral is connected to a specific MIO pad, +the corresponding [`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en) bit should be set to 0. + +## MIO_PAD_SLEEP_MODE +Defines sleep behavior of the corresponding muxed pad. +- Reset default: `0x2` +- Reset mask: `0x3` + +### Instances + +| Name | Offset | +|:----------------------|:---------| +| MIO_PAD_SLEEP_MODE_0 | 0x390 | +| MIO_PAD_SLEEP_MODE_1 | 0x394 | +| MIO_PAD_SLEEP_MODE_2 | 0x398 | +| MIO_PAD_SLEEP_MODE_3 | 0x39c | +| MIO_PAD_SLEEP_MODE_4 | 0x3a0 | +| MIO_PAD_SLEEP_MODE_5 | 0x3a4 | +| MIO_PAD_SLEEP_MODE_6 | 0x3a8 | +| MIO_PAD_SLEEP_MODE_7 | 0x3ac | +| MIO_PAD_SLEEP_MODE_8 | 0x3b0 | +| MIO_PAD_SLEEP_MODE_9 | 0x3b4 | +| MIO_PAD_SLEEP_MODE_10 | 0x3b8 | +| MIO_PAD_SLEEP_MODE_11 | 0x3bc | + + +### Fields + +```wavejson +{"reg": [{"name": "OUT", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:--------------------------------| +| 31:2 | | | Reserved | +| 1:0 | rw | 0x2 | [OUT](#mio_pad_sleep_mode--out) | + +### MIO_PAD_SLEEP_MODE . OUT +Value to drive in deep sleep. + +| Value | Name | Description | +|:--------|:---------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 0x0 | Tie-Low | The pad is driven actively to zero in deep sleep mode. | +| 0x1 | Tie-High | The pad is driven actively to one in deep sleep mode. | +| 0x2 | High-Z | The pad is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of in !!MIO_PAD_ATTR. | +| 0x3 | Keep | Keep last driven value (including high-Z). | + + +## DIO_PAD_SLEEP_STATUS_0 +Register indicating whether the corresponding pad is in sleep mode. +- Offset: `0x3c0` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_2", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_3", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_4", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_5", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_6", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_7", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_8", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_9", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_10", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_11", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_12", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_13", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_14", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_15", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_16", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_17", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_18", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_19", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_20", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_21", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_22", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_23", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_24", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_25", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_26", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_27", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_28", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_29", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_30", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_31", "bits": 1, "attr": ["rw0c"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31 | rw0c | 0x0 | EN_31 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 30 | rw0c | 0x0 | EN_30 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 29 | rw0c | 0x0 | EN_29 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 28 | rw0c | 0x0 | EN_28 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 27 | rw0c | 0x0 | EN_27 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 26 | rw0c | 0x0 | EN_26 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 25 | rw0c | 0x0 | EN_25 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 24 | rw0c | 0x0 | EN_24 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 23 | rw0c | 0x0 | EN_23 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 22 | rw0c | 0x0 | EN_22 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 21 | rw0c | 0x0 | EN_21 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 20 | rw0c | 0x0 | EN_20 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 19 | rw0c | 0x0 | EN_19 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 18 | rw0c | 0x0 | EN_18 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 17 | rw0c | 0x0 | EN_17 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 16 | rw0c | 0x0 | EN_16 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 15 | rw0c | 0x0 | EN_15 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 14 | rw0c | 0x0 | EN_14 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 13 | rw0c | 0x0 | EN_13 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 12 | rw0c | 0x0 | EN_12 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 11 | rw0c | 0x0 | EN_11 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 10 | rw0c | 0x0 | EN_10 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 9 | rw0c | 0x0 | EN_9 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 8 | rw0c | 0x0 | EN_8 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 7 | rw0c | 0x0 | EN_7 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 6 | rw0c | 0x0 | EN_6 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 5 | rw0c | 0x0 | EN_5 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 4 | rw0c | 0x0 | EN_4 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 3 | rw0c | 0x0 | EN_3 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 2 | rw0c | 0x0 | EN_2 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 1 | rw0c | 0x0 | EN_1 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 0 | rw0c | 0x0 | EN_0 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | + +## DIO_PAD_SLEEP_STATUS_1 +Register indicating whether the corresponding pad is in sleep mode. +- Offset: `0x3c4` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "EN_32", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_33", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_34", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_35", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_36", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_37", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_38", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_39", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_40", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_41", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_42", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_43", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_44", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_45", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_46", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_47", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_48", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_49", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_50", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_51", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_52", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_53", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_54", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_55", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_56", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_57", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_58", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_59", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_60", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_61", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_62", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_63", "bits": 1, "attr": ["rw0c"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31 | rw0c | 0x0 | EN_63 | For DIO_PAD1 | +| 30 | rw0c | 0x0 | EN_62 | For DIO_PAD1 | +| 29 | rw0c | 0x0 | EN_61 | For DIO_PAD1 | +| 28 | rw0c | 0x0 | EN_60 | For DIO_PAD1 | +| 27 | rw0c | 0x0 | EN_59 | For DIO_PAD1 | +| 26 | rw0c | 0x0 | EN_58 | For DIO_PAD1 | +| 25 | rw0c | 0x0 | EN_57 | For DIO_PAD1 | +| 24 | rw0c | 0x0 | EN_56 | For DIO_PAD1 | +| 23 | rw0c | 0x0 | EN_55 | For DIO_PAD1 | +| 22 | rw0c | 0x0 | EN_54 | For DIO_PAD1 | +| 21 | rw0c | 0x0 | EN_53 | For DIO_PAD1 | +| 20 | rw0c | 0x0 | EN_52 | For DIO_PAD1 | +| 19 | rw0c | 0x0 | EN_51 | For DIO_PAD1 | +| 18 | rw0c | 0x0 | EN_50 | For DIO_PAD1 | +| 17 | rw0c | 0x0 | EN_49 | For DIO_PAD1 | +| 16 | rw0c | 0x0 | EN_48 | For DIO_PAD1 | +| 15 | rw0c | 0x0 | EN_47 | For DIO_PAD1 | +| 14 | rw0c | 0x0 | EN_46 | For DIO_PAD1 | +| 13 | rw0c | 0x0 | EN_45 | For DIO_PAD1 | +| 12 | rw0c | 0x0 | EN_44 | For DIO_PAD1 | +| 11 | rw0c | 0x0 | EN_43 | For DIO_PAD1 | +| 10 | rw0c | 0x0 | EN_42 | For DIO_PAD1 | +| 9 | rw0c | 0x0 | EN_41 | For DIO_PAD1 | +| 8 | rw0c | 0x0 | EN_40 | For DIO_PAD1 | +| 7 | rw0c | 0x0 | EN_39 | For DIO_PAD1 | +| 6 | rw0c | 0x0 | EN_38 | For DIO_PAD1 | +| 5 | rw0c | 0x0 | EN_37 | For DIO_PAD1 | +| 4 | rw0c | 0x0 | EN_36 | For DIO_PAD1 | +| 3 | rw0c | 0x0 | EN_35 | For DIO_PAD1 | +| 2 | rw0c | 0x0 | EN_34 | For DIO_PAD1 | +| 1 | rw0c | 0x0 | EN_33 | For DIO_PAD1 | +| 0 | rw0c | 0x0 | EN_32 | For DIO_PAD1 | + +## DIO_PAD_SLEEP_STATUS_2 +Register indicating whether the corresponding pad is in sleep mode. +- Offset: `0x3c8` +- Reset default: `0x0` +- Reset mask: `0x1ff` + +### Fields + +```wavejson +{"reg": [{"name": "EN_64", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_65", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_66", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_67", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_68", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_69", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_70", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_71", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_72", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31:9 | | | | Reserved | +| 8 | rw0c | 0x0 | EN_72 | For DIO_PAD2 | +| 7 | rw0c | 0x0 | EN_71 | For DIO_PAD2 | +| 6 | rw0c | 0x0 | EN_70 | For DIO_PAD2 | +| 5 | rw0c | 0x0 | EN_69 | For DIO_PAD2 | +| 4 | rw0c | 0x0 | EN_68 | For DIO_PAD2 | +| 3 | rw0c | 0x0 | EN_67 | For DIO_PAD2 | +| 2 | rw0c | 0x0 | EN_66 | For DIO_PAD2 | +| 1 | rw0c | 0x0 | EN_65 | For DIO_PAD2 | +| 0 | rw0c | 0x0 | EN_64 | For DIO_PAD2 | + +## DIO_PAD_SLEEP_REGWEN +Register write enable for DIO sleep value configuration. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:------------------------|:---------| +| DIO_PAD_SLEEP_REGWEN_0 | 0x3cc | +| DIO_PAD_SLEEP_REGWEN_1 | 0x3d0 | +| DIO_PAD_SLEEP_REGWEN_2 | 0x3d4 | +| DIO_PAD_SLEEP_REGWEN_3 | 0x3d8 | +| DIO_PAD_SLEEP_REGWEN_4 | 0x3dc | +| DIO_PAD_SLEEP_REGWEN_5 | 0x3e0 | +| DIO_PAD_SLEEP_REGWEN_6 | 0x3e4 | +| DIO_PAD_SLEEP_REGWEN_7 | 0x3e8 | +| DIO_PAD_SLEEP_REGWEN_8 | 0x3ec | +| DIO_PAD_SLEEP_REGWEN_9 | 0x3f0 | +| DIO_PAD_SLEEP_REGWEN_10 | 0x3f4 | +| DIO_PAD_SLEEP_REGWEN_11 | 0x3f8 | +| DIO_PAD_SLEEP_REGWEN_12 | 0x3fc | +| DIO_PAD_SLEEP_REGWEN_13 | 0x400 | +| DIO_PAD_SLEEP_REGWEN_14 | 0x404 | +| DIO_PAD_SLEEP_REGWEN_15 | 0x408 | +| DIO_PAD_SLEEP_REGWEN_16 | 0x40c | +| DIO_PAD_SLEEP_REGWEN_17 | 0x410 | +| DIO_PAD_SLEEP_REGWEN_18 | 0x414 | +| DIO_PAD_SLEEP_REGWEN_19 | 0x418 | +| DIO_PAD_SLEEP_REGWEN_20 | 0x41c | +| DIO_PAD_SLEEP_REGWEN_21 | 0x420 | +| DIO_PAD_SLEEP_REGWEN_22 | 0x424 | +| DIO_PAD_SLEEP_REGWEN_23 | 0x428 | +| DIO_PAD_SLEEP_REGWEN_24 | 0x42c | +| DIO_PAD_SLEEP_REGWEN_25 | 0x430 | +| DIO_PAD_SLEEP_REGWEN_26 | 0x434 | +| DIO_PAD_SLEEP_REGWEN_27 | 0x438 | +| DIO_PAD_SLEEP_REGWEN_28 | 0x43c | +| DIO_PAD_SLEEP_REGWEN_29 | 0x440 | +| DIO_PAD_SLEEP_REGWEN_30 | 0x444 | +| DIO_PAD_SLEEP_REGWEN_31 | 0x448 | +| DIO_PAD_SLEEP_REGWEN_32 | 0x44c | +| DIO_PAD_SLEEP_REGWEN_33 | 0x450 | +| DIO_PAD_SLEEP_REGWEN_34 | 0x454 | +| DIO_PAD_SLEEP_REGWEN_35 | 0x458 | +| DIO_PAD_SLEEP_REGWEN_36 | 0x45c | +| DIO_PAD_SLEEP_REGWEN_37 | 0x460 | +| DIO_PAD_SLEEP_REGWEN_38 | 0x464 | +| DIO_PAD_SLEEP_REGWEN_39 | 0x468 | +| DIO_PAD_SLEEP_REGWEN_40 | 0x46c | +| DIO_PAD_SLEEP_REGWEN_41 | 0x470 | +| DIO_PAD_SLEEP_REGWEN_42 | 0x474 | +| DIO_PAD_SLEEP_REGWEN_43 | 0x478 | +| DIO_PAD_SLEEP_REGWEN_44 | 0x47c | +| DIO_PAD_SLEEP_REGWEN_45 | 0x480 | +| DIO_PAD_SLEEP_REGWEN_46 | 0x484 | +| DIO_PAD_SLEEP_REGWEN_47 | 0x488 | +| DIO_PAD_SLEEP_REGWEN_48 | 0x48c | +| DIO_PAD_SLEEP_REGWEN_49 | 0x490 | +| DIO_PAD_SLEEP_REGWEN_50 | 0x494 | +| DIO_PAD_SLEEP_REGWEN_51 | 0x498 | +| DIO_PAD_SLEEP_REGWEN_52 | 0x49c | +| DIO_PAD_SLEEP_REGWEN_53 | 0x4a0 | +| DIO_PAD_SLEEP_REGWEN_54 | 0x4a4 | +| DIO_PAD_SLEEP_REGWEN_55 | 0x4a8 | +| DIO_PAD_SLEEP_REGWEN_56 | 0x4ac | +| DIO_PAD_SLEEP_REGWEN_57 | 0x4b0 | +| DIO_PAD_SLEEP_REGWEN_58 | 0x4b4 | +| DIO_PAD_SLEEP_REGWEN_59 | 0x4b8 | +| DIO_PAD_SLEEP_REGWEN_60 | 0x4bc | +| DIO_PAD_SLEEP_REGWEN_61 | 0x4c0 | +| DIO_PAD_SLEEP_REGWEN_62 | 0x4c4 | +| DIO_PAD_SLEEP_REGWEN_63 | 0x4c8 | +| DIO_PAD_SLEEP_REGWEN_64 | 0x4cc | +| DIO_PAD_SLEEP_REGWEN_65 | 0x4d0 | +| DIO_PAD_SLEEP_REGWEN_66 | 0x4d4 | +| DIO_PAD_SLEEP_REGWEN_67 | 0x4d8 | +| DIO_PAD_SLEEP_REGWEN_68 | 0x4dc | +| DIO_PAD_SLEEP_REGWEN_69 | 0x4e0 | +| DIO_PAD_SLEEP_REGWEN_70 | 0x4e4 | +| DIO_PAD_SLEEP_REGWEN_71 | 0x4e8 | +| DIO_PAD_SLEEP_REGWEN_72 | 0x4ec | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding [`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode) is not writable anymore. | + +## DIO_PAD_SLEEP_EN +Enables the sleep mode of the corresponding dedicated pad. +- Reset default: `0x0` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:--------------------|:---------| +| DIO_PAD_SLEEP_EN_0 | 0x4f0 | +| DIO_PAD_SLEEP_EN_1 | 0x4f4 | +| DIO_PAD_SLEEP_EN_2 | 0x4f8 | +| DIO_PAD_SLEEP_EN_3 | 0x4fc | +| DIO_PAD_SLEEP_EN_4 | 0x500 | +| DIO_PAD_SLEEP_EN_5 | 0x504 | +| DIO_PAD_SLEEP_EN_6 | 0x508 | +| DIO_PAD_SLEEP_EN_7 | 0x50c | +| DIO_PAD_SLEEP_EN_8 | 0x510 | +| DIO_PAD_SLEEP_EN_9 | 0x514 | +| DIO_PAD_SLEEP_EN_10 | 0x518 | +| DIO_PAD_SLEEP_EN_11 | 0x51c | +| DIO_PAD_SLEEP_EN_12 | 0x520 | +| DIO_PAD_SLEEP_EN_13 | 0x524 | +| DIO_PAD_SLEEP_EN_14 | 0x528 | +| DIO_PAD_SLEEP_EN_15 | 0x52c | +| DIO_PAD_SLEEP_EN_16 | 0x530 | +| DIO_PAD_SLEEP_EN_17 | 0x534 | +| DIO_PAD_SLEEP_EN_18 | 0x538 | +| DIO_PAD_SLEEP_EN_19 | 0x53c | +| DIO_PAD_SLEEP_EN_20 | 0x540 | +| DIO_PAD_SLEEP_EN_21 | 0x544 | +| DIO_PAD_SLEEP_EN_22 | 0x548 | +| DIO_PAD_SLEEP_EN_23 | 0x54c | +| DIO_PAD_SLEEP_EN_24 | 0x550 | +| DIO_PAD_SLEEP_EN_25 | 0x554 | +| DIO_PAD_SLEEP_EN_26 | 0x558 | +| DIO_PAD_SLEEP_EN_27 | 0x55c | +| DIO_PAD_SLEEP_EN_28 | 0x560 | +| DIO_PAD_SLEEP_EN_29 | 0x564 | +| DIO_PAD_SLEEP_EN_30 | 0x568 | +| DIO_PAD_SLEEP_EN_31 | 0x56c | +| DIO_PAD_SLEEP_EN_32 | 0x570 | +| DIO_PAD_SLEEP_EN_33 | 0x574 | +| DIO_PAD_SLEEP_EN_34 | 0x578 | +| DIO_PAD_SLEEP_EN_35 | 0x57c | +| DIO_PAD_SLEEP_EN_36 | 0x580 | +| DIO_PAD_SLEEP_EN_37 | 0x584 | +| DIO_PAD_SLEEP_EN_38 | 0x588 | +| DIO_PAD_SLEEP_EN_39 | 0x58c | +| DIO_PAD_SLEEP_EN_40 | 0x590 | +| DIO_PAD_SLEEP_EN_41 | 0x594 | +| DIO_PAD_SLEEP_EN_42 | 0x598 | +| DIO_PAD_SLEEP_EN_43 | 0x59c | +| DIO_PAD_SLEEP_EN_44 | 0x5a0 | +| DIO_PAD_SLEEP_EN_45 | 0x5a4 | +| DIO_PAD_SLEEP_EN_46 | 0x5a8 | +| DIO_PAD_SLEEP_EN_47 | 0x5ac | +| DIO_PAD_SLEEP_EN_48 | 0x5b0 | +| DIO_PAD_SLEEP_EN_49 | 0x5b4 | +| DIO_PAD_SLEEP_EN_50 | 0x5b8 | +| DIO_PAD_SLEEP_EN_51 | 0x5bc | +| DIO_PAD_SLEEP_EN_52 | 0x5c0 | +| DIO_PAD_SLEEP_EN_53 | 0x5c4 | +| DIO_PAD_SLEEP_EN_54 | 0x5c8 | +| DIO_PAD_SLEEP_EN_55 | 0x5cc | +| DIO_PAD_SLEEP_EN_56 | 0x5d0 | +| DIO_PAD_SLEEP_EN_57 | 0x5d4 | +| DIO_PAD_SLEEP_EN_58 | 0x5d8 | +| DIO_PAD_SLEEP_EN_59 | 0x5dc | +| DIO_PAD_SLEEP_EN_60 | 0x5e0 | +| DIO_PAD_SLEEP_EN_61 | 0x5e4 | +| DIO_PAD_SLEEP_EN_62 | 0x5e8 | +| DIO_PAD_SLEEP_EN_63 | 0x5ec | +| DIO_PAD_SLEEP_EN_64 | 0x5f0 | +| DIO_PAD_SLEEP_EN_65 | 0x5f4 | +| DIO_PAD_SLEEP_EN_66 | 0x5f8 | +| DIO_PAD_SLEEP_EN_67 | 0x5fc | +| DIO_PAD_SLEEP_EN_68 | 0x600 | +| DIO_PAD_SLEEP_EN_69 | 0x604 | +| DIO_PAD_SLEEP_EN_70 | 0x608 | +| DIO_PAD_SLEEP_EN_71 | 0x60c | +| DIO_PAD_SLEEP_EN_72 | 0x610 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:----------------------------| +| 31:1 | | | Reserved | +| 0 | rw | 0x0 | [EN](#dio_pad_sleep_en--en) | + +### DIO_PAD_SLEEP_EN . EN +Deep sleep mode enable. +If this bit is set to 1 the corresponding pad will enable the sleep behavior +specified in [`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode) upon deep sleep entry, and the corresponding bit +in [`DIO_PAD_SLEEP_STATUS`](#dio_pad_sleep_status) will be set to 1. +The pad remains in deep sleep mode until the corresponding bit in +[`DIO_PAD_SLEEP_STATUS`](#dio_pad_sleep_status) is cleared by SW. +Note that if an always on peripheral is connected to a specific DIO pad, +the corresponding [`DIO_PAD_SLEEP_EN`](#dio_pad_sleep_en) bit should be set to 0. + +## DIO_PAD_SLEEP_MODE +Defines sleep behavior of the corresponding dedicated pad. +- Reset default: `0x2` +- Reset mask: `0x3` + +### Instances + +| Name | Offset | +|:----------------------|:---------| +| DIO_PAD_SLEEP_MODE_0 | 0x614 | +| DIO_PAD_SLEEP_MODE_1 | 0x618 | +| DIO_PAD_SLEEP_MODE_2 | 0x61c | +| DIO_PAD_SLEEP_MODE_3 | 0x620 | +| DIO_PAD_SLEEP_MODE_4 | 0x624 | +| DIO_PAD_SLEEP_MODE_5 | 0x628 | +| DIO_PAD_SLEEP_MODE_6 | 0x62c | +| DIO_PAD_SLEEP_MODE_7 | 0x630 | +| DIO_PAD_SLEEP_MODE_8 | 0x634 | +| DIO_PAD_SLEEP_MODE_9 | 0x638 | +| DIO_PAD_SLEEP_MODE_10 | 0x63c | +| DIO_PAD_SLEEP_MODE_11 | 0x640 | +| DIO_PAD_SLEEP_MODE_12 | 0x644 | +| DIO_PAD_SLEEP_MODE_13 | 0x648 | +| DIO_PAD_SLEEP_MODE_14 | 0x64c | +| DIO_PAD_SLEEP_MODE_15 | 0x650 | +| DIO_PAD_SLEEP_MODE_16 | 0x654 | +| DIO_PAD_SLEEP_MODE_17 | 0x658 | +| DIO_PAD_SLEEP_MODE_18 | 0x65c | +| DIO_PAD_SLEEP_MODE_19 | 0x660 | +| DIO_PAD_SLEEP_MODE_20 | 0x664 | +| DIO_PAD_SLEEP_MODE_21 | 0x668 | +| DIO_PAD_SLEEP_MODE_22 | 0x66c | +| DIO_PAD_SLEEP_MODE_23 | 0x670 | +| DIO_PAD_SLEEP_MODE_24 | 0x674 | +| DIO_PAD_SLEEP_MODE_25 | 0x678 | +| DIO_PAD_SLEEP_MODE_26 | 0x67c | +| DIO_PAD_SLEEP_MODE_27 | 0x680 | +| DIO_PAD_SLEEP_MODE_28 | 0x684 | +| DIO_PAD_SLEEP_MODE_29 | 0x688 | +| DIO_PAD_SLEEP_MODE_30 | 0x68c | +| DIO_PAD_SLEEP_MODE_31 | 0x690 | +| DIO_PAD_SLEEP_MODE_32 | 0x694 | +| DIO_PAD_SLEEP_MODE_33 | 0x698 | +| DIO_PAD_SLEEP_MODE_34 | 0x69c | +| DIO_PAD_SLEEP_MODE_35 | 0x6a0 | +| DIO_PAD_SLEEP_MODE_36 | 0x6a4 | +| DIO_PAD_SLEEP_MODE_37 | 0x6a8 | +| DIO_PAD_SLEEP_MODE_38 | 0x6ac | +| DIO_PAD_SLEEP_MODE_39 | 0x6b0 | +| DIO_PAD_SLEEP_MODE_40 | 0x6b4 | +| DIO_PAD_SLEEP_MODE_41 | 0x6b8 | +| DIO_PAD_SLEEP_MODE_42 | 0x6bc | +| DIO_PAD_SLEEP_MODE_43 | 0x6c0 | +| DIO_PAD_SLEEP_MODE_44 | 0x6c4 | +| DIO_PAD_SLEEP_MODE_45 | 0x6c8 | +| DIO_PAD_SLEEP_MODE_46 | 0x6cc | +| DIO_PAD_SLEEP_MODE_47 | 0x6d0 | +| DIO_PAD_SLEEP_MODE_48 | 0x6d4 | +| DIO_PAD_SLEEP_MODE_49 | 0x6d8 | +| DIO_PAD_SLEEP_MODE_50 | 0x6dc | +| DIO_PAD_SLEEP_MODE_51 | 0x6e0 | +| DIO_PAD_SLEEP_MODE_52 | 0x6e4 | +| DIO_PAD_SLEEP_MODE_53 | 0x6e8 | +| DIO_PAD_SLEEP_MODE_54 | 0x6ec | +| DIO_PAD_SLEEP_MODE_55 | 0x6f0 | +| DIO_PAD_SLEEP_MODE_56 | 0x6f4 | +| DIO_PAD_SLEEP_MODE_57 | 0x6f8 | +| DIO_PAD_SLEEP_MODE_58 | 0x6fc | +| DIO_PAD_SLEEP_MODE_59 | 0x700 | +| DIO_PAD_SLEEP_MODE_60 | 0x704 | +| DIO_PAD_SLEEP_MODE_61 | 0x708 | +| DIO_PAD_SLEEP_MODE_62 | 0x70c | +| DIO_PAD_SLEEP_MODE_63 | 0x710 | +| DIO_PAD_SLEEP_MODE_64 | 0x714 | +| DIO_PAD_SLEEP_MODE_65 | 0x718 | +| DIO_PAD_SLEEP_MODE_66 | 0x71c | +| DIO_PAD_SLEEP_MODE_67 | 0x720 | +| DIO_PAD_SLEEP_MODE_68 | 0x724 | +| DIO_PAD_SLEEP_MODE_69 | 0x728 | +| DIO_PAD_SLEEP_MODE_70 | 0x72c | +| DIO_PAD_SLEEP_MODE_71 | 0x730 | +| DIO_PAD_SLEEP_MODE_72 | 0x734 | + + +### Fields + +```wavejson +{"reg": [{"name": "OUT", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:--------------------------------| +| 31:2 | | | Reserved | +| 1:0 | rw | 0x2 | [OUT](#dio_pad_sleep_mode--out) | + +### DIO_PAD_SLEEP_MODE . OUT +Value to drive in deep sleep. + +| Value | Name | Description | +|:--------|:---------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 0x0 | Tie-Low | The pad is driven actively to zero in deep sleep mode. | +| 0x1 | Tie-High | The pad is driven actively to one in deep sleep mode. | +| 0x2 | High-Z | The pad is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of in !!DIO_PAD_ATTR. | +| 0x3 | Keep | Keep last driven value (including high-Z). | + + +## WKUP_DETECTOR_REGWEN +Register write enable for wakeup detectors. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:-----------------------|:---------| +| WKUP_DETECTOR_REGWEN_0 | 0x738 | +| WKUP_DETECTOR_REGWEN_1 | 0x73c | +| WKUP_DETECTOR_REGWEN_2 | 0x740 | +| WKUP_DETECTOR_REGWEN_3 | 0x744 | +| WKUP_DETECTOR_REGWEN_4 | 0x748 | +| WKUP_DETECTOR_REGWEN_5 | 0x74c | +| WKUP_DETECTOR_REGWEN_6 | 0x750 | +| WKUP_DETECTOR_REGWEN_7 | 0x754 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding WKUP_DETECTOR configuration is not writable anymore. | + +## WKUP_DETECTOR_EN +Enables for the wakeup detectors. +Note that these registers are synced to the always-on clock. +The first write access always completes immediately. +However, read/write accesses following a write will block until that write has completed. +- Reset default: `0x0` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:-------------------|:---------| +| WKUP_DETECTOR_EN_0 | 0x758 | +| WKUP_DETECTOR_EN_1 | 0x75c | +| WKUP_DETECTOR_EN_2 | 0x760 | +| WKUP_DETECTOR_EN_3 | 0x764 | +| WKUP_DETECTOR_EN_4 | 0x768 | +| WKUP_DETECTOR_EN_5 | 0x76c | +| WKUP_DETECTOR_EN_6 | 0x770 | +| WKUP_DETECTOR_EN_7 | 0x774 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | EN | Setting this bit activates the corresponding wakeup detector. The behavior is as specified in [`WKUP_DETECTOR`](#wkup_detector), [`WKUP_DETECTOR_CNT_TH`](#wkup_detector_cnt_th) and [`WKUP_DETECTOR_PADSEL.`](#wkup_detector_padsel) | + +## WKUP_DETECTOR +Configuration of wakeup condition detectors. +Note that these registers are synced to the always-on clock. +The first write access always completes immediately. +However, read/write accesses following a write will block until that write has completed. + +Note that the wkup detector should be disabled by setting [`WKUP_DETECTOR_EN_0`](#wkup_detector_en_0) before changing the detection mode. +The reason for that is that the pulse width counter is NOT cleared upon a mode change while the detector is enabled. +- Reset default: `0x0` +- Reset mask: `0x1f` + +### Instances + +| Name | Offset | +|:----------------|:---------| +| WKUP_DETECTOR_0 | 0x778 | +| WKUP_DETECTOR_1 | 0x77c | +| WKUP_DETECTOR_2 | 0x780 | +| WKUP_DETECTOR_3 | 0x784 | +| WKUP_DETECTOR_4 | 0x788 | +| WKUP_DETECTOR_5 | 0x78c | +| WKUP_DETECTOR_6 | 0x790 | +| WKUP_DETECTOR_7 | 0x794 | + + +### Fields + +```wavejson +{"reg": [{"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "FILTER", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MIODIO", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:---------------------------------| +| 31:5 | | | Reserved | +| 4 | rw | 0x0 | [MIODIO](#wkup_detector--miodio) | +| 3 | rw | 0x0 | [FILTER](#wkup_detector--filter) | +| 2:0 | rw | 0x0 | [MODE](#wkup_detector--mode) | + +### WKUP_DETECTOR . MIODIO +0: select index [`WKUP_DETECTOR_PADSEL`](#wkup_detector_padsel) from MIO pads, +1: select index [`WKUP_DETECTOR_PADSEL`](#wkup_detector_padsel) from DIO pads. + +### WKUP_DETECTOR . FILTER +0: signal filter disabled, 1: signal filter enabled. the signal must +be stable for 4 always-on clock cycles before the value is being forwarded. +can be used for debouncing. + +### WKUP_DETECTOR . MODE +Wakeup detection mode. Out of range values default to Posedge. + +| Value | Name | Description | +|:--------|:----------|:-----------------------------------------------------------------------------------------------------------------------------------------| +| 0x0 | Posedge | Trigger a wakeup request when observing a positive edge. | +| 0x1 | Negedge | Trigger a wakeup request when observing a negative edge. | +| 0x2 | Edge | Trigger a wakeup request when observing an edge in any direction. | +| 0x3 | TimedHigh | Trigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH. | +| 0x4 | TimedLow | Trigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH. | + +Other values are reserved. + +## WKUP_DETECTOR_CNT_TH +Counter thresholds for wakeup condition detectors. +Note that these registers are synced to the always-on clock. +The first write access always completes immediately. +However, read/write accesses following a write will block until that write has completed. +- Reset default: `0x0` +- Reset mask: `0xff` + +### Instances + +| Name | Offset | +|:-----------------------|:---------| +| WKUP_DETECTOR_CNT_TH_0 | 0x798 | +| WKUP_DETECTOR_CNT_TH_1 | 0x79c | +| WKUP_DETECTOR_CNT_TH_2 | 0x7a0 | +| WKUP_DETECTOR_CNT_TH_3 | 0x7a4 | +| WKUP_DETECTOR_CNT_TH_4 | 0x7a8 | +| WKUP_DETECTOR_CNT_TH_5 | 0x7ac | +| WKUP_DETECTOR_CNT_TH_6 | 0x7b0 | +| WKUP_DETECTOR_CNT_TH_7 | 0x7b4 | + + +### Fields + +```wavejson +{"reg": [{"name": "TH", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:8 | | | | Reserved | +| 7:0 | rw | 0x0 | TH | Counter threshold for TimedLow and TimedHigh wakeup detector modes (see [`WKUP_DETECTOR`](#wkup_detector)). The threshold is in terms of always-on clock cycles. | + +## WKUP_DETECTOR_PADSEL +Pad selects for pad wakeup condition detectors. +This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix. +- Reset default: `0x0` +- Reset mask: `0x3f` + +### Instances + +| Name | Offset | +|:-----------------------|:---------| +| WKUP_DETECTOR_PADSEL_0 | 0x7b8 | +| WKUP_DETECTOR_PADSEL_1 | 0x7bc | +| WKUP_DETECTOR_PADSEL_2 | 0x7c0 | +| WKUP_DETECTOR_PADSEL_3 | 0x7c4 | +| WKUP_DETECTOR_PADSEL_4 | 0x7c8 | +| WKUP_DETECTOR_PADSEL_5 | 0x7cc | +| WKUP_DETECTOR_PADSEL_6 | 0x7d0 | +| WKUP_DETECTOR_PADSEL_7 | 0x7d4 | + + +### Fields + +```wavejson +{"reg": [{"name": "SEL", "bits": 6, "attr": ["rw"], "rotate": 0}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:----------------------------------| +| 31:6 | | | Reserved | +| 5:0 | rw | 0x0 | [SEL](#wkup_detector_padsel--sel) | + +### WKUP_DETECTOR_PADSEL . SEL +Selects a specific MIO or DIO pad (depending on [`WKUP_DETECTOR`](#wkup_detector) configuration). +In case of MIO, the pad select index is the same as used for [`MIO_PERIPH_INSEL`](#mio_periph_insel), meaning that index +0 and 1 just select constants 0 and 1, and the MIO pads live at indices >= 2. In case of DIO pads, +the pad select index corresponds 1:1 to the DIO pad to be selected. + +## WKUP_CAUSE +Cause registers for wakeup detectors. +Note that these registers are synced to the always-on clock. +The first write access always completes immediately. +However, read/write accesses following a write will block until that write has completed. +- Offset: `0x7d8` +- Reset default: `0x0` +- Reset mask: `0xff` + +### Fields + +```wavejson +{"reg": [{"name": "CAUSE_0", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_1", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_2", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_3", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_4", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_5", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_6", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_7", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:----------------------------------------------------------------------------------------| +| 31:8 | | | | Reserved | +| 7 | rw0c | 0x0 | CAUSE_7 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 6 | rw0c | 0x0 | CAUSE_6 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 5 | rw0c | 0x0 | CAUSE_5 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 4 | rw0c | 0x0 | CAUSE_4 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 3 | rw0c | 0x0 | CAUSE_3 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 2 | rw0c | 0x0 | CAUSE_2 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 1 | rw0c | 0x0 | CAUSE_1 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 0 | rw0c | 0x0 | CAUSE_0 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | + + + diff --git a/hw/top_darjeeling/ip_autogen/pinmux/doc/targets.md b/hw/top_darjeeling/ip_autogen/pinmux/doc/targets.md new file mode 100644 index 0000000000000..1acf888a9966d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/doc/targets.md @@ -0,0 +1,10 @@ +# "top_darjeeling" Pinmux Targets + +| Target Name | #IO Banks | #Muxed Pads | #Direct Pads | #Manual Pads | #Total Pads | Pinout / Pinmux Tables | +|:-------------:|:-----------:|:-------------:|:--------------:|:--------------:|:-------------:|:---------------------------------:| +| ASIC | 1 | 12 | 73 | 7 | 92 | [Pinout Table](./pinout_asic.md) | +| CW310 | 1 | 12 | 73 | 10 | 95 | [Pinout Table](./pinout_cw310.md) | diff --git a/hw/top_darjeeling/ip_autogen/pinmux/doc/theory_of_operation.md b/hw/top_darjeeling/ip_autogen/pinmux/doc/theory_of_operation.md new file mode 100644 index 0000000000000..fa1200779d0f3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/doc/theory_of_operation.md @@ -0,0 +1,215 @@ +# Theory of Operation + +## Block Diagram and Overview + +The `pinmux` peripheral is a programmable module designed to wire arbitrary peripheral inputs and outputs to arbitrary multiplexable chip bidirectional pins. +It gives much flexibility at the top level of the device, allowing most data pins to be flexibly wired and controlled by many peripherals. +Even though the `pinmux` is referred to as one IP, it is logically split into two modules that are instantiated on the top-level and the chip-level, respectively, as can be seen in the block diagram below. +The top-level module `pinmux` contains the CSRs accessible via the TL-UL interface, the main muxing matrix, retention registers, a set of programmable wakeup detectors, and the HW strap sampling and TAP / JTAG muxing logic. +The chip-level module `padring` instantiates the bidirectional pads and connects the physical pad attributes. + +![Pinmux Block Diagram](../doc/pinmux_overview_block_diagram.svg) + +### MIO and DIO Signal Categories + +The `pinmux` supports two different IO signal categories: +Muxed IO (MIO) signals that are routed through the `pinmux` matrix, and dedicated IO (DIO) signals that bypass the `pinmux` matrix. +This distinction is useful for accommodating IO signals that are timing critical or that must have a fixed IO mapping for another reason. +Note that although DIO signals are not routed through the `pinmux` matrix, they are still connected to the retention logic and the wakeup detectors (see next section below). + +The number of available peripheral IOs, pads, and their assignment to the MIO / DIO categories is done at design time as part of the top-level configuration. +This configurability is achieved by representing inputs / outputs as packed arrays, in combination with the SystemVerilog parameters `NPeriphIn`, `NPeriphOut`, `NMioPads` and `NDioPads`. +Note however that the register file is also affected by this configuration and needs to be regenerated for each design instance. + +It is assumed that all available pins that the `pinmux` connects to are bidirectional, controlled by logic within this module. +By default, all muxed peripheral inputs are tied to zero. +Further, all output enables are set to zero, which essentially causes all pads to be in high-Z state after reset. +In addition to wiring programmability, each muxed peripheral input can be set constantly to 0 or 1, and each muxed chip output can be set constantly to 0, 1 or high-Z. + +See the [muxing matrix](#muxing-matrix) section for more details about the mux implementation. + +### Retention and Wakeup Features + +The retention logic allows SW to specify a certain behavior during sleep for each muxed and dedicated output. +Legal behaviors are tie low, tie high, high-Z, keeping the previous state, or driving the current value (useful for peripherals that are always on). + +The wakeup detectors can detect patterns such as rising / falling edges and pulses of a certain width up to 255 AON clock cycles. +Each wakeup detector can listen on any one of the MIO / DIO signals that are routed through the `pinmux`, and if a pattern is detected, the power manager is informed of that event via a wakeup request. + +The `pinmux` module itself is in the always-on (AON) power domain, and as such does not loose configuration state when a sleep power cycle is performed. +However, only the wakeup detector logic will be actively clocked during sleep in order to save power. + +See the [retention logic](#retention-logic) and [wakeup detectors](#wakeup-detectors) sections for more details about the mux implementation. + +### USB Wakeup Detection Module + +The USB device in the Earlgrey top-level is not in the AON power domain and hence the associated wakeup detection module is placed inside the pinmux IP in that top-level. +The USB wakeup module is not connected to any pinmux infrastructure or CSRs except for the `usb_wkup_req` signal going to the power manager. +See [USB device documentation](../../../../ip/usbdev/README.md) for more information on the USB wakeup mechanism. + +### Test and Debug Access + +The hardware strap sampling and TAP isolation logic provides test and debug access to the chip during specific life cycle states. +This mechanism is explained in more detail in the [strap sampling and TAP isolation](#strap-sampling-and-tap-isolation) section. + +### Pad Attributes + +Additional pad-specific features such as inversion, pull-up, pull-down, virtual open-drain, drive-strength and input/output inversion etc. can be exercise via the pad attribute CSRs. +The `pinmux` module supports a comprehensive set of such pad attributes, but it is permissible that some of them may not be supported by the underlying pad implementation. +For example, certain ASIC libraries may not provide open-drain outputs, and FPGAs typically do not allow all of these attributes to be programmed dynamically at runtime. +See the [generic pad wrapper](#generic-pad-wrapper) section below for more details. +Note that static pad attributes for FPGAs are currently not covered in this specification. + +## Muxing Matrix + +The diagram below shows connectivity between four arbitrary chip pins, named `MIO0` .. `MIO3`, and several muxed peripheral inputs and outputs. +This shows the connectivity available in all directions, as well as the control registers described later in this document. +Two example peripherals (`uart` and `spidev`) are attached to the `pinmux` in this example, one with one input and one output, the other with three inputs and one output. +The diagram also shows the `padring` module which instantiates the bidirectional chip pads with output enable control. + +![Pinmux Block Diagram](../doc/pinmux_muxing_matrix.svg) + +Note that apart from selecting a specific input pad, the `periph_insel[*]` signals can also be used to tie the peripheral input to 0 or 1. +Likewise, the output select signals `mio_outsel[*]` can also be used to constantly drive an output pin to 0/1 or to put it into high-Z state (default). +The output enable and the associated data signal (i.e. `periph_to_mio` and `periph_to_mio_oe`) are indexed with the same select signal to allow the peripheral hardware to determine the pad direction instead of demoting that control to SW. + +## Retention Logic + +As illustrated in the picture above, all muxing matrix and DIO outputs are routed through the retention logic, which essentially consists of a set of multiplexors and two retention registers per output (one register is for the output data and one for the output enable). +This multiplexor can be configured to be automatically activated upon sleep entry in order to either drive the output low, high, high-Z or to the last seen value (keep). +If no sleep behavior is specified, the retention logic will continue to drive out the value coming from the peripheral side, which can be useful for peripherals that reside in the AON domain. + +The sleep behavior of all outputs is activated in parallel via a trigger signal asserted by the power manager. +Once activated, it is the task of SW to disable the sleep behavior for each individual pin when waking up from sleep. +This ensures that the output values remain stable until the system and its peripherals have been re-initialized. + +## Wakeup Detectors + +The `pinmux` contains eight programmable wakeup detector modules that can listen on any of the MIO or DIO pins. +Each detector contains a debounce filter and an 8bit counter running on the AON clock domain. +The detectors can be programmed via the [`WKUP_DETECTOR_0`](registers.md#wkup_detector) and [`WKUP_DETECTOR_CNT_TH_0`](registers.md#wkup_detector_cnt_th) registers to detect the following patterns: + +- rising edge +- falling edge +- rising or falling edge +- positive pulse up to 255 AON clock cycles in length +- negative pulse up to 255 AON clock cycles in length + +Note that for all patterns listed above, the input signal is sampled with the AON clock. +This means that the input signal needs to remain stable for at least one AON clock cycle after a level change for the detector to recognize the event (depending on the debounce filter configuration, the signal needs to remain stable for multiple clock cycles). + +If a pattern is detected, the wakeup detector will send a wakeup request to the power manager, and the cause bit corresponding to that detector will be set in the [`WKUP_CAUSE`](registers.md#wkup_cause) register. + +Note that the wkup detector should be disabled by setting [`WKUP_DETECTOR_EN_0`](registers.md#wkup_detector_en) before changing the detection mode. +The reason for that is that the pulse width counter is NOT cleared upon a mode change while the detector is enabled. + +## Strap Sampling and TAP Isolation + +The `pinmux` contains a set of dedicated HW "straps", which are essentially signals that are multiplexed onto fixed MIO pad locations. +Depending on the life cycle state, these straps are either continuously sampled, or latched right after POR. + +There are two groups of HW straps: +1. Three DFT straps that determine the DFT mode. + These bits are output via the `dft_strap_test_o` signal such that they can be routed to the tool-inserted DFT controller. +2. Two TAP selection straps for determining which TAP should be multiplexed onto the JTAG IOs. + +The conditions under which these two strap groups are sampled are listed in the tables below. +Note that the HW straps can be used just like regular GPIOs once they have been sampled. + +Strap Group \ Life Cycle State | TEST_UNLOCKED* | RMA | DEV | All Other States +--------------------------------|----------------|--------------|--------------|------------------ +DFT straps | Once at boot | Once at boot | - | - +TAP strap 0 | Continuously | Continuously | Once at boot | Once at boot +TAP strap 1 | Continuously | Continuously | Once at boot | - + +*Once at boot:* Sampled once after life cycle initialization (sampling event is initiated by pwrmgr). + +*Continuously:* Sampled continuously after life cycle initialization. + +The TAP muxing logic is further qualified by the life cycle state in order to isolate the TAPs in certain life cycle states. +The following table lists the TAP strap encoding and the life cycle states in which the associated TAPs can be selected and accessed. + +TAP strap 1 | TAP strap 0 | Life Cycle State | Selected TAP +------------|--------------|--------------------------|--------------- +0 | 0 | All states | - +0 | 1 | All states | Life Cycle +1 | 0 | TEST_UNLOCKED*, RMA, DEV | RISC-V +1 | 1 | TEST_UNLOCKED*, RMA | DFT + +Note that the tool-inserted DFT controller may assert the `dft_hold_tap_sel_i` during a test (e.g. boundary scan) in which case the `pinmux` will temporarily pause sampling of the TAP selection straps. + +It should be noted that the TAP straps are muxed with MIOs and that the pad attributes will take effect even in life cycles states that +continuously sample the straps. As a result, pad attributes can interfere or even disable tap selection entirely in those life cycle states. + +Also, it should be noted that the pad attributes of all JTAG IOs will be gated to all-zero temporarily, while the JTAG is enabled (this does not affect the values in the CSRs). +This is to ensure that any functional attributes like inversion or pull-ups / pull-downs do not interfere with the JTAG while it is in use. + +For more information about the life cycle states, see [Life Cycle Controller Specification](../../../../ip/lc_ctrl/README.md) and the [Life Cycle Definition Table](../../../../../doc/security/specs/device_life_cycle/README.md#manufacturing-states). + +### Non-debug Module Reset + +The only parts of the system that are not reset as part of a non-debug module (NDM) reset are in this strap sampling and TAP selection module, and in the `rv_dm`, power, reset and clock managers. +Hence, in order to keep a `rv_dm` JTAG debug session alive during an NDM reset, the `lc_hw_debug_en` state needs to be memorized. + +To that end, the TAP isolation logic in the pinmux samples the `lc_hw_debug_en` state when the strap sampling pulse is asserted by the power manager. +This pulse is asserted once during boot (and not after an NDM reset). + +Note that DFT TAP selection is not affected by this since the TAP selection logic always consumes the live value for `lc_dft_en`. +The TAP selection logic also invalidates the sampled `lc_hw_debug_en` whenever a life cycle transition is initiated or an escalation is triggered via `lc_escalate_en`. +This ensures that the sampled `lc_hw_debug_en` value does not survive a life cycle transition. + +Finally, note that there is secondary gating on the `rv_dm` and DFT TAPs that is always consuming live `lc_hw_debug_en` and `lc_dft_en` signals for added protection. + +See also [rv_dm documentation](../../../../ip/rv_dm/doc/theory_of_operation.md#non-debug-module-reset-support). + +## Generic Pad Wrapper + +
+ +
+ +The generic pad wrapper is intended to abstract away implementation differences between the target technologies by providing a generic interface that is compatible with the `padring` module. +It is the task of the RTL build flow to select the appropriate pad wrapper implementation. + +A specific implementation of a pad wrapper may choose to instantiate a technology primitive (as it is common in ASIC flows), or it may choose to model the functionality behaviorally such that it can be inferred by the technology mapping tool (e.g., in the case of an FPGA target). +It is permissible to omit the implementation of all IO attributes except input/output inversion. + +The generic pad wrapper must expose the following IOs and parameters, even if they are not connected internally. +In particular, the pad attribute struct `attr_i` must contain all fields listed below, even if not all attributes are supported (it is permissible to just leave them unconnected in the pad wrapper implementation). + +Parameter | Default | Description +---------------|------------|----------------------------------------------------- +`PadType` | `BidirStd` | Pad variant to be instantiated (technology-specific) +`ScanRole` | `NoScan` | Scan role, can be `NoScan`, `ScanIn` or `ScanOut` + +Note that `PadType` is a technology-specific parameter. +The generic pad wrapper only implements variant `BidirStd`, but for other target technologies, this parameter can be used to select among a variety of different pad flavors. + +The `ScanRole` parameter determines the behavior when scanmode is enabled. +Depending on whether a given pad acts as a scan input or output, certain pad attributes and functionalities need to be bypassed. +This parameter is typically only relevant for ASIC targets and therefore not modeled in the generic pad model. + +Also note that the pad wrapper may implement a "virtual" open-drain termination, where standard bidirectional pads are employed, but instead of driving the output high for a logic 1 the pad is put into tristate mode. + +Signal | Direction | Type | Description +---------------------|------------|-------------|----------------------------------------------- +`clk_scan_i` | `input` | `logic` | Scan clock of the pad +`scanmode_i` | `input` | `logic` | Scan mode enable of the pad +`pok_i` | `input` | `pad_pok_t` | Technology-specific power sequencing signals +`inout_io` | `inout` | `wire` | Bidirectional inout of the pad +`in_o` | `output` | `logic` | Input data signal +`in_raw_o` | `output` | `logic` | Un-inverted input data signal +`out_i` | `input` | `logic` | Output data signal +`oe_i` | `input` | `logic` | Output data enable +`attr_i[0]` | `input` | `logic` | Input/output inversion +`attr_i[1]` | `input` | `logic` | Virtual open-drain enable +`attr_i[2]` | `input` | `logic` | Pull enable +`attr_i[3]` | `input` | `logic` | Pull select (0: pull-down, 1: pull-up) +`attr_i[4]` | `input` | `logic` | Keeper enable +`attr_i[5]` | `input` | `logic` | Schmitt trigger enable +`attr_i[6]` | `input` | `logic` | Open drain enable +`attr_i[7]` | `input` | `logic` | Input disable (0: input enabled, 1: input disabled) +`attr_i[9:8]` | `input` | `logic` | Slew rate (0x0: slowest, 0x3: fastest) +`attr_i[13:10]` | `input` | `logic` | Drive strength (0x0: weakest, 0xf: strongest) + +Note that the corresponding pad attribute registers [`MIO_PAD_ATTR_0`](registers.md#mio_pad_attr) and [`DIO_PAD_ATTR_0`](registers.md#dio_pad_attr) have "writes-any-reads-legal" (WARL) behavior (see also [pad attributes](#pad-attributes)). diff --git a/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_chip_expected_failure.hjson b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_chip_expected_failure.hjson new file mode 100644 index 0000000000000..c6d4640f00fae --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_chip_expected_failure.hjson @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +{ + unreachable: + [ + pinmux_chip_tb.dut_asic.FpvSecCmRegWeOnehotCheck_A:precondition1 + pinmux_chip_tb.dut_asic.u_reg.u_prim_reg_we_check.u_prim_onehot_check.Onehot0Check_A:precondition1 + pinmux_chip_tb.dut_asic.u_reg.u_prim_reg_we_check.u_prim_onehot_check.gen_enable_check.gen_not_strict.EnableCheck_A:precondition1 + ] +} diff --git a/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core new file mode 100644 index 0000000000000..df24ef19d3e6a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core @@ -0,0 +1,43 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_pinmux_chip_fpv:0.1 +description: "pinmux FPV target with chip_earlgrey parameters" +virtual: + - lowrisc:ip_interfaces:pinmux_chip_fpv + +filesets: + files_formal: + depend: + - lowrisc:prim:all + - lowrisc:ip:tlul + - lowrisc:ip_interfaces:pinmux + - lowrisc:fpv:csr_assert_gen + - lowrisc:fpv:pinmux_common_fpv + - lowrisc:systems:top_darjeeling_pkg + - lowrisc:systems:scan_role_pkg + files: + - tb/pinmux_chip_tb.sv + file_type: systemVerilogSource + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../data/pinmux.hjson + +targets: + default: &default_target + default_tool: icarus + filesets: + - files_formal + generate: + - csr_assert_gen + toplevel: pinmux_chip_tb + + formal: + <<: *default_target + + lint: + <<: *default_target diff --git a/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_common_fpv.core b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_common_fpv.core new file mode 100644 index 0000000000000..6d99ff4929ac9 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_common_fpv.core @@ -0,0 +1,28 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:fpv:pinmux_common_fpv:0.1" +description: "pinmux common FPV target" +filesets: + files_formal: + depend: + - lowrisc:prim:all + - lowrisc:ip:tlul + - lowrisc:ip_interfaces:pinmux + files: + - vip/pinmux_assert_fpv.sv + - tb/pinmux_bind_fpv.sv + file_type: systemVerilogSource + +targets: + default: &default_target + default_tool: icarus + filesets: + - files_formal + + formal: + <<: *default_target + + lint: + <<: *default_target diff --git a/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_expected_failure.hjson b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_expected_failure.hjson new file mode 100644 index 0000000000000..ccbda769bebb3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_expected_failure.hjson @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +{ + unreachable: + [ + pinmux_tb.dut.FpvSecCmRegWeOnehotCheck_A:precondition1 + pinmux_tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.Onehot0Check_A:precondition1 + pinmux_tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.gen_enable_check.gen_not_strict.EnableCheck_A:precondition1 + ] +} diff --git a/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_fpv.core b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_fpv.core new file mode 100644 index 0000000000000..f51b37ee6feb3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/fpv/pinmux_fpv.core @@ -0,0 +1,39 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:fpv:pinmux_fpv:0.1" +description: "pinmux FPV target" +filesets: + files_formal: + depend: + - lowrisc:prim:all + - lowrisc:ip:tlul + - lowrisc:ip_interfaces:pinmux + - lowrisc:fpv:csr_assert_gen + - lowrisc:fpv:pinmux_common_fpv + - lowrisc:systems:scan_role_pkg + files: + - tb/pinmux_tb.sv + file_type: systemVerilogSource + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../data/pinmux.hjson + +targets: + default: &default_target + default_tool: icarus + filesets: + - files_formal + generate: + - csr_assert_gen + toplevel: pinmux_tb + + formal: + <<: *default_target + + lint: + <<: *default_target diff --git a/hw/top_darjeeling/ip_autogen/pinmux/fpv/tb/pinmux_bind_fpv.sv b/hw/top_darjeeling/ip_autogen/pinmux/fpv/tb/pinmux_bind_fpv.sv new file mode 100644 index 0000000000000..6667a58b32026 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/fpv/tb/pinmux_bind_fpv.sv @@ -0,0 +1,60 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +module pinmux_bind_fpv; + + + bind pinmux pinmux_assert_fpv #( + .TargetCfg(TargetCfg), + .AlertAsyncOn(AlertAsyncOn), + .SecVolatileRawUnlockEn(SecVolatileRawUnlockEn) + ) i_pinmux_assert_fpv ( + .clk_i, + .rst_ni, + .rst_sys_ni, + .scanmode_i, + .clk_aon_i, + .rst_aon_ni, + .pin_wkup_req_o, + .sleep_en_i, + .tl_i, + .tl_o, + .alert_rx_i, + .alert_tx_o, + .periph_to_mio_i, + .periph_to_mio_oe_i, + .mio_to_periph_o, + .periph_to_dio_i, + .periph_to_dio_oe_i, + .dio_to_periph_o, + .mio_attr_o, + .mio_out_o, + .mio_oe_o, + .mio_in_i, + .dio_attr_o, + .dio_out_o, + .dio_oe_o, + .dio_in_i + ); + + + bind pinmux tlul_assert #( + .EndpointType("Device") + ) i_tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o), + .* + ); + + bind pinmux pinmux_csr_assert_fpv i_pinmux_csr_assert_fpv ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + +endmodule : pinmux_bind_fpv diff --git a/hw/top_darjeeling/ip_autogen/pinmux/fpv/tb/pinmux_chip_tb.sv b/hw/top_darjeeling/ip_autogen/pinmux/fpv/tb/pinmux_chip_tb.sv new file mode 100644 index 0000000000000..f76f2378f5e3b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/fpv/tb/pinmux_chip_tb.sv @@ -0,0 +1,216 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Testbench module for pinmux. +// Intended to be used with a formal tool. + +module pinmux_chip_tb + import pinmux_pkg::*; + import pinmux_reg_pkg::*; + import prim_pad_wrapper_pkg::*; + import top_darjeeling_pkg::*; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter bit SecVolatileRawUnlockEn = 1 +) ( + input clk_i, + input rst_ni, + input rst_sys_ni, + input prim_mubi_pkg::mubi4_t scanmode_i, + input clk_aon_i, + input rst_aon_ni, + output logic pin_wkup_req_o, + input sleep_en_i, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + input prim_alert_pkg::alert_rx_t[NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t[NumAlerts-1:0] alert_tx_o, + input [NMioPeriphOut-1:0] periph_to_mio_i, + input [NMioPeriphOut-1:0] periph_to_mio_oe_i, + output logic[NMioPeriphIn-1:0] mio_to_periph_o, + input [NDioPads-1:0] periph_to_dio_i, + input [NDioPads-1:0] periph_to_dio_oe_i, + output logic[NDioPads-1:0] dio_to_periph_o, + output prim_pad_wrapper_pkg::pad_attr_t[NMioPads-1:0] mio_attr_o, + output logic[NMioPads-1:0] mio_out_o, + output logic[NMioPads-1:0] mio_oe_o, + input [NMioPads-1:0] mio_in_i, + output prim_pad_wrapper_pkg::pad_attr_t[NDioPads-1:0] dio_attr_o, + output logic[NDioPads-1:0] dio_out_o, + output logic[NDioPads-1:0] dio_oe_o, + input [NDioPads-1:0] dio_in_i +); + + import top_darjeeling_pkg::*; + + // Copied from chip_darjeeling_asic.sv + // TODO: find a better way to automatically generate this FPV testbench via topgen/ipgen. + localparam int Tap0PadIdx = 30; + localparam int Tap1PadIdx = 27; + localparam int Dft0PadIdx = 25; + localparam int Dft1PadIdx = 26; + localparam int TckPadIdx = 38; + localparam int TmsPadIdx = 35; + localparam int TrstNPadIdx = 39; + localparam int TdiPadIdx = 37; + localparam int TdoPadIdx = 36; + // DFT and Debug signal positions in the pinout. + localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ + tck_idx: TckPadIdx, + tms_idx: TmsPadIdx, + trst_idx: TrstNPadIdx, + tdi_idx: TdiPadIdx, + tdo_idx: TdoPadIdx, + tap_strap0_idx: Tap0PadIdx, + tap_strap1_idx: Tap1PadIdx, + dft_strap0_idx: Dft0PadIdx, + dft_strap1_idx: Dft1PadIdx, + // TODO: check whether there is a better way to pass these USB-specific params + usb_dp_idx: DioUsbdevUsbDp, + usb_dn_idx: DioUsbdevUsbDn, + usb_sense_idx: MioInUsbdevSense, + // Pad types for attribute WARL behavior + dio_pad_type: { + BidirStd, // DIO spi_host0_csb + BidirStd, // DIO spi_host0_sck + InputStd, // DIO spi_device_csb + InputStd, // DIO spi_device_sck + BidirOd, // DIO sysrst_ctrl_aon_flash_wp_l + BidirOd, // DIO sysrst_ctrl_aon_ec_rst_l + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO usbdev_usb_dn + BidirStd // DIO usbdev_usb_dp + }, + mio_pad_type: { + BidirOd, // MIO Pad 46 + BidirOd, // MIO Pad 45 + BidirOd, // MIO Pad 44 + BidirOd, // MIO Pad 43 + BidirStd, // MIO Pad 42 + BidirStd, // MIO Pad 41 + BidirStd, // MIO Pad 40 + BidirStd, // MIO Pad 39 + BidirStd, // MIO Pad 38 + BidirStd, // MIO Pad 37 + BidirStd, // MIO Pad 36 + BidirStd, // MIO Pad 35 + BidirOd, // MIO Pad 34 + BidirOd, // MIO Pad 33 + BidirOd, // MIO Pad 32 + BidirStd, // MIO Pad 31 + BidirStd, // MIO Pad 30 + BidirStd, // MIO Pad 29 + BidirStd, // MIO Pad 28 + BidirStd, // MIO Pad 27 + BidirStd, // MIO Pad 26 + BidirStd, // MIO Pad 25 + BidirStd, // MIO Pad 24 + BidirStd, // MIO Pad 23 + BidirStd, // MIO Pad 22 + BidirOd, // MIO Pad 21 + BidirOd, // MIO Pad 20 + BidirOd, // MIO Pad 19 + BidirOd, // MIO Pad 18 + BidirStd, // MIO Pad 17 + BidirStd, // MIO Pad 16 + BidirStd, // MIO Pad 15 + BidirStd, // MIO Pad 14 + BidirStd, // MIO Pad 13 + BidirStd, // MIO Pad 12 + BidirStd, // MIO Pad 11 + BidirStd, // MIO Pad 10 + BidirStd, // MIO Pad 9 + BidirOd, // MIO Pad 8 + BidirOd, // MIO Pad 7 + BidirOd, // MIO Pad 6 + BidirStd, // MIO Pad 5 + BidirStd, // MIO Pad 4 + BidirStd, // MIO Pad 3 + BidirStd, // MIO Pad 2 + BidirStd, // MIO Pad 1 + BidirStd // MIO Pad 0 + }, + dio_scan_role: { + scan_role_pkg::DioPadSpiHostCsLScanRole, // DIO spi_host0_csb + scan_role_pkg::DioPadSpiHostClkScanRole, // DIO spi_host0_sck + scan_role_pkg::DioPadSpiDevCsLScanRole, // DIO spi_device_csb + scan_role_pkg::DioPadSpiDevClkScanRole, // DIO spi_device_sck + scan_role_pkg::DioPadIor9ScanRole, // DIO sysrst_ctrl_aon_flash_wp_l + scan_role_pkg::DioPadIor8ScanRole, // DIO sysrst_ctrl_aon_ec_rst_l + scan_role_pkg::DioPadSpiDevD3ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiDevD2ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiDevD1ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiDevD0ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiHostD3ScanRole, // DIO spi_host0_sd + scan_role_pkg::DioPadSpiHostD2ScanRole, // DIO spi_host0_sd + scan_role_pkg::DioPadSpiHostD1ScanRole, // DIO spi_host0_sd + scan_role_pkg::DioPadSpiHostD0ScanRole, // DIO spi_host0_sd + NoScan, // DIO usbdev_usb_dn + NoScan // DIO usbdev_usb_dp + }, + mio_scan_role: { + scan_role_pkg::MioPadIor13ScanRole, + scan_role_pkg::MioPadIor12ScanRole, + scan_role_pkg::MioPadIor11ScanRole, + scan_role_pkg::MioPadIor10ScanRole, + scan_role_pkg::MioPadIor7ScanRole, + scan_role_pkg::MioPadIor6ScanRole, + scan_role_pkg::MioPadIor5ScanRole, + scan_role_pkg::MioPadIor4ScanRole, + scan_role_pkg::MioPadIor3ScanRole, + scan_role_pkg::MioPadIor2ScanRole, + scan_role_pkg::MioPadIor1ScanRole, + scan_role_pkg::MioPadIor0ScanRole, + scan_role_pkg::MioPadIoc12ScanRole, + scan_role_pkg::MioPadIoc11ScanRole, + scan_role_pkg::MioPadIoc10ScanRole, + scan_role_pkg::MioPadIoc9ScanRole, + scan_role_pkg::MioPadIoc8ScanRole, + scan_role_pkg::MioPadIoc7ScanRole, + scan_role_pkg::MioPadIoc6ScanRole, + scan_role_pkg::MioPadIoc5ScanRole, + scan_role_pkg::MioPadIoc4ScanRole, + scan_role_pkg::MioPadIoc3ScanRole, + scan_role_pkg::MioPadIoc2ScanRole, + scan_role_pkg::MioPadIoc1ScanRole, + scan_role_pkg::MioPadIoc0ScanRole, + scan_role_pkg::MioPadIob12ScanRole, + scan_role_pkg::MioPadIob11ScanRole, + scan_role_pkg::MioPadIob10ScanRole, + scan_role_pkg::MioPadIob9ScanRole, + scan_role_pkg::MioPadIob8ScanRole, + scan_role_pkg::MioPadIob7ScanRole, + scan_role_pkg::MioPadIob6ScanRole, + scan_role_pkg::MioPadIob5ScanRole, + scan_role_pkg::MioPadIob4ScanRole, + scan_role_pkg::MioPadIob3ScanRole, + scan_role_pkg::MioPadIob2ScanRole, + scan_role_pkg::MioPadIob1ScanRole, + scan_role_pkg::MioPadIob0ScanRole, + scan_role_pkg::MioPadIoa8ScanRole, + scan_role_pkg::MioPadIoa7ScanRole, + scan_role_pkg::MioPadIoa6ScanRole, + scan_role_pkg::MioPadIoa5ScanRole, + scan_role_pkg::MioPadIoa4ScanRole, + scan_role_pkg::MioPadIoa3ScanRole, + scan_role_pkg::MioPadIoa2ScanRole, + scan_role_pkg::MioPadIoa1ScanRole, + scan_role_pkg::MioPadIoa0ScanRole + } + }; + + pinmux #( + .TargetCfg(PinmuxTargetCfg), + .AlertAsyncOn(AlertAsyncOn), + .SecVolatileRawUnlockEn(SecVolatileRawUnlockEn) + ) dut_asic (.*); + +endmodule : pinmux_chip_tb diff --git a/hw/top_darjeeling/ip_autogen/pinmux/fpv/tb/pinmux_tb.sv b/hw/top_darjeeling/ip_autogen/pinmux/fpv/tb/pinmux_tb.sv new file mode 100644 index 0000000000000..9e4ce306f1425 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/fpv/tb/pinmux_tb.sv @@ -0,0 +1,82 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Testbench module for pinmux. +// Intended to be used with a formal tool. + +module pinmux_tb + import pinmux_pkg::*; + import pinmux_reg_pkg::*; + import prim_pad_wrapper_pkg::*; +#( + parameter int Tap0PadIdx = 0, + parameter int Tap1PadIdx = 1, + parameter int Dft0PadIdx = 2, + parameter int Dft1PadIdx = 3, + parameter int TckPadIdx = 4, + parameter int TmsPadIdx = 5, + parameter int TrstNPadIdx = 6, + parameter int TdiPadIdx = 7, + parameter int TdoPadIdx = 8, + parameter int DioUsbdevDp = 9, + parameter int DioUsbdevDn = 10, + parameter int MioInUsbdevSense = 11, + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter bit SecVolatileRawUnlockEn = 1 +) ( + input clk_i, + input rst_ni, + input rst_sys_ni, + input prim_mubi_pkg::mubi4_t scanmode_i, + input clk_aon_i, + input rst_aon_ni, + output logic pin_wkup_req_o, + input sleep_en_i, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + input prim_alert_pkg::alert_rx_t[NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t[NumAlerts-1:0] alert_tx_o, + input [NMioPeriphOut-1:0] periph_to_mio_i, + input [NMioPeriphOut-1:0] periph_to_mio_oe_i, + output logic[NMioPeriphIn-1:0] mio_to_periph_o, + input [NDioPads-1:0] periph_to_dio_i, + input [NDioPads-1:0] periph_to_dio_oe_i, + output logic[NDioPads-1:0] dio_to_periph_o, + output prim_pad_wrapper_pkg::pad_attr_t[NMioPads-1:0] mio_attr_o, + output logic[NMioPads-1:0] mio_out_o, + output logic[NMioPads-1:0] mio_oe_o, + input [NMioPads-1:0] mio_in_i, + output prim_pad_wrapper_pkg::pad_attr_t[NDioPads-1:0] dio_attr_o, + output logic[NDioPads-1:0] dio_out_o, + output logic[NDioPads-1:0] dio_oe_o, + input [NDioPads-1:0] dio_in_i +); + + localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ + tck_idx: TckPadIdx, + tms_idx: TmsPadIdx, + trst_idx: TrstNPadIdx, + tdi_idx: TdiPadIdx, + tdo_idx: TdoPadIdx, + tap_strap0_idx: Tap0PadIdx, + tap_strap1_idx: Tap1PadIdx, + dft_strap0_idx: Dft0PadIdx, + dft_strap1_idx: Dft1PadIdx, + usb_dp_idx: DioUsbdevDp, + usb_dn_idx: DioUsbdevDn, + usb_sense_idx: MioInUsbdevSense, + // Pad types for attribute WARL behavior + dio_pad_type: {NDioPads{BidirStd}}, + mio_pad_type: {NMioPads{BidirStd}}, + dio_scan_role: {NDioPads{NoScan}}, + mio_scan_role: {NMioPads{NoScan}} + }; + + pinmux #( + .TargetCfg(PinmuxTargetCfg), + .AlertAsyncOn(AlertAsyncOn), + .SecVolatileRawUnlockEn(SecVolatileRawUnlockEn) + ) dut (.*); + +endmodule : pinmux_tb diff --git a/hw/top_darjeeling/ip_autogen/pinmux/fpv/vip/pinmux_assert_fpv.sv b/hw/top_darjeeling/ip_autogen/pinmux/fpv/vip/pinmux_assert_fpv.sv new file mode 100644 index 0000000000000..b8c72dd8d68ff --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/fpv/vip/pinmux_assert_fpv.sv @@ -0,0 +1,556 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Assertions for pinmux. +// Intended to be used with a formal tool. + +`include "prim_assert.sv" + +module pinmux_assert_fpv + import pinmux_pkg::*; + import pinmux_reg_pkg::*; + import prim_pad_wrapper_pkg::*; +#( + parameter target_cfg_t TargetCfg = DefaultTargetCfg, + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter bit SecVolatileRawUnlockEn = 0 +) ( + input clk_i, + input rst_ni, + input rst_sys_ni, + input prim_mubi_pkg::mubi4_t scanmode_i, + input clk_aon_i, + input rst_aon_ni, + input logic pin_wkup_req_o, + input sleep_en_i, + input tlul_pkg::tl_h2d_t tl_i, + input tlul_pkg::tl_d2h_t tl_o, + input prim_alert_pkg::alert_rx_t[NumAlerts-1:0] alert_rx_i, + input prim_alert_pkg::alert_tx_t[NumAlerts-1:0] alert_tx_o, + input [NMioPeriphOut-1:0] periph_to_mio_i, + input [NMioPeriphOut-1:0] periph_to_mio_oe_i, + input logic[NMioPeriphIn-1:0] mio_to_periph_o, + input [NDioPads-1:0] periph_to_dio_i, + input [NDioPads-1:0] periph_to_dio_oe_i, + input logic[NDioPads-1:0] dio_to_periph_o, + input prim_pad_wrapper_pkg::pad_attr_t[NMioPads-1:0] mio_attr_o, + input logic[NMioPads-1:0] mio_out_o, + input logic[NMioPads-1:0] mio_oe_o, + input [NMioPads-1:0] mio_in_i, + input prim_pad_wrapper_pkg::pad_attr_t[NDioPads-1:0] dio_attr_o, + input logic[NDioPads-1:0] dio_out_o, + input logic[NDioPads-1:0] dio_oe_o, + input [NDioPads-1:0] dio_in_i +); + + /////////////////////////////// + // Declarations & Parameters // + /////////////////////////////// + + ///////////////// + // Assumptions // + ///////////////// + + // Symbolic inputs for FPV + logic [$clog2(pinmux_reg_pkg::NMioPeriphIn)-1:0] periph_sel_i; + logic [$clog2(pinmux_reg_pkg::NMioPads)-1:0] mio_sel_i; + logic [$clog2(pinmux_reg_pkg::NDioPads)-1:0] dio_sel_i; + logic [$clog2(pinmux_reg_pkg::NWkupDetect)-1:0] wkup_sel_i; + + `ASSUME(PeriphSelRange_M, periph_sel_i < pinmux_reg_pkg::NMioPeriphIn) + `ASSUME(PeriphSelStable_M, ##1 $stable(periph_sel_i)) + + `ASSUME(MioSelRange_M, mio_sel_i < pinmux_reg_pkg::NMioPads && !(mio_sel_i inside + {TargetCfg.tck_idx, TargetCfg.tms_idx, TargetCfg.trst_idx, TargetCfg.tdi_idx, + TargetCfg.tdo_idx})) + `ASSUME(MioSelStable_M, ##1 $stable(mio_sel_i)) + + `ASSUME(DioSelRange_M, dio_sel_i < pinmux_reg_pkg::NDioPads) + `ASSUME(DioSelStable_M, ##1 $stable(dio_sel_i)) + + `ASSUME(WkupSelRange_M, wkup_sel_i < pinmux_reg_pkg::NWkupDetect) + `ASSUME(WkupSelStable_M, ##1 $stable(wkup_sel_i)) + + // ------ Input mux assertions ------ + pinmux_reg_pkg::pinmux_reg2hw_mio_periph_insel_mreg_t periph_insel; + assign periph_insel = pinmux.reg2hw.mio_periph_insel[periph_sel_i]; + + `ASSERT(InSel0_A, periph_insel.q == 0 |-> mio_to_periph_o[periph_sel_i] == 1'b0) + `ASSERT(InSel1_A, periph_insel.q == 1 |-> mio_to_periph_o[periph_sel_i] == 1'b1) + `ASSERT(InSelN_A, periph_insel.q > 1 && periph_insel.q < (pinmux_reg_pkg::NMioPads + 2) && + !((periph_insel.q - 2) inside {TargetCfg.tck_idx, TargetCfg.tms_idx, TargetCfg.trst_idx, + TargetCfg.tdi_idx, TargetCfg.tdo_idx}) |-> + mio_to_periph_o[periph_sel_i] == mio_in_i[periph_insel.q - 2]) + `ASSERT(InSelOOB_A, periph_insel.q >= (pinmux_reg_pkg::NMioPads + 2) |-> + mio_to_periph_o[periph_sel_i] == 0) + + `ASSERT(MioToPeriph0Backward_A, mio_to_periph_o[periph_sel_i] == 0 |-> + (periph_insel.q == 0) || + ((periph_insel.q > 1 && periph_insel.q < (pinmux_reg_pkg::NMioPads + 2) && + (pinmux.u_pinmux_strap_sampling.jtag_en || mio_in_i[periph_insel.q - 2] == 0)) || + periph_insel.q >= (pinmux_reg_pkg::NMioPads + 2))) + + `ASSERT(MioToPeriph1Backward_A, mio_to_periph_o[periph_sel_i] == 1 |-> + (periph_insel.q == 1) || + (periph_insel.q > 1 && periph_insel.q < (pinmux_reg_pkg::NMioPads + 2) && + (mio_in_i[periph_insel.q - 2] == 1 || pinmux.u_pinmux_strap_sampling.jtag_en))) + + `ASSERT(DioInSelN_A, dio_to_periph_o == dio_in_i) + + // ------ Output mux assertions ------ + pinmux_reg_pkg::pinmux_reg2hw_mio_outsel_mreg_t mio_outsel; + assign mio_outsel = pinmux.reg2hw.mio_outsel[mio_sel_i]; + + pinmux_reg_pkg::pinmux_reg2hw_mio_pad_sleep_status_mreg_t mio_pad_sleep_status; + assign mio_pad_sleep_status = pinmux.reg2hw.mio_pad_sleep_status[mio_sel_i]; + + + `ASSERT(OutSel0_A, mio_outsel.q == 0 && !mio_pad_sleep_status.q |-> mio_out_o[mio_sel_i] == 1'b0) + `ASSERT(OutSel1_A, mio_outsel.q == 1 && !mio_pad_sleep_status.q |-> mio_out_o[mio_sel_i] == 1'b1) + `ASSERT(OutSel2_A, mio_outsel.q == 2 && !mio_pad_sleep_status.q |-> mio_out_o[mio_sel_i] == 1'b0) + `ASSERT(OutSelN_A, mio_outsel.q > 2 && mio_outsel.q < (pinmux_reg_pkg::NMioPeriphOut + 3) && + !mio_pad_sleep_status.q |-> mio_out_o[mio_sel_i] == periph_to_mio_i[mio_outsel.q - 3]) + `ASSERT(OutSelOOB_A, mio_outsel.q >= (pinmux_reg_pkg::NMioPeriphOut + 3) && + !mio_pad_sleep_status.q |-> mio_out_o[mio_sel_i] == 0) + + `ASSERT(MioOut0Backward_A, mio_out_o[mio_sel_i] == 0 |-> + mio_pad_sleep_status.q || + mio_outsel.q inside {0, 2} || + mio_outsel.q >= (pinmux_reg_pkg::NMioPeriphOut + 3) || + (mio_outsel.q > 2 && mio_outsel.q < (pinmux_reg_pkg::NMioPeriphOut + 3) && + periph_to_mio_i[mio_outsel.q - 3] == 0)) + + `ASSERT(MioOut1Backward_A, mio_out_o[mio_sel_i] == 1 |-> + mio_pad_sleep_status.q || + mio_outsel.q == 1 || + mio_outsel.q > (pinmux_reg_pkg::NMioPeriphOut + 3) || + (mio_outsel.q > 2 && mio_outsel.q < (pinmux_reg_pkg::NMioPeriphOut + 3) && + periph_to_mio_i[mio_outsel.q - 3] == 1)) + + `ASSERT(OutSelOe0_A, mio_outsel.q == 0 && !mio_pad_sleep_status.q |-> + mio_oe_o[mio_sel_i] == 1'b1) + `ASSERT(OutSelOe1_A, mio_outsel.q == 1 && !mio_pad_sleep_status.q |-> + mio_oe_o[mio_sel_i] == 1'b1) + `ASSERT(OutSelOe2_A, mio_outsel.q == 2 && !mio_pad_sleep_status.q |-> + mio_oe_o[mio_sel_i] == 1'b0) + `ASSERT(OutSelOeN_A, mio_outsel.q > 2 && mio_outsel.q < (pinmux_reg_pkg::NMioPeriphOut + 3) && + !mio_pad_sleep_status.q |-> mio_oe_o[mio_sel_i] == periph_to_mio_oe_i[mio_outsel.q - 3]) + `ASSERT(OutSelOeOOB_A, mio_outsel.q >= (pinmux_reg_pkg::NMioPeriphOut + 3) && + !mio_pad_sleep_status.q |-> mio_oe_o[mio_sel_i] == 0) + + `ASSERT(MioOe0Backward_A, mio_oe_o[mio_sel_i] == 0 |-> + mio_pad_sleep_status.q || + mio_outsel.q == 2 || + mio_outsel.q >= (pinmux_reg_pkg::NMioPeriphOut + 3) || + (mio_outsel.q > 2 && mio_outsel.q < (pinmux_reg_pkg::NMioPeriphOut + 3) && + periph_to_mio_oe_i[mio_outsel.q - 3] == 0)) + + `ASSERT(MioOe1Backward_A, mio_oe_o[mio_sel_i] == 1 |-> + mio_pad_sleep_status.q || + mio_outsel.q inside {0, 1} || + mio_outsel.q > (pinmux_reg_pkg::NMioPeriphOut + 3) || + (mio_outsel.q > 2 && mio_outsel.q < (pinmux_reg_pkg::NMioPeriphOut + 3) && + periph_to_mio_oe_i[mio_outsel.q - 3] == 1)) + + // ------ Mio sleep behavior assertions ------ + pinmux_reg_pkg::pinmux_reg2hw_mio_pad_sleep_en_mreg_t mio_pad_sleep_en; + assign mio_pad_sleep_en = pinmux.reg2hw.mio_pad_sleep_en[mio_sel_i]; + pinmux_reg_pkg::pinmux_reg2hw_mio_pad_sleep_mode_mreg_t mio_pad_sleep_mode; + assign mio_pad_sleep_mode = pinmux.reg2hw.mio_pad_sleep_mode[mio_sel_i]; + + `ASSERT(MioSleepMode0_A, ##1 mio_pad_sleep_mode.q == 0 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + mio_out_o[mio_sel_i] == 1'b0) + `ASSERT(MioSleepMode1_A, ##1 mio_pad_sleep_mode.q == 1 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + mio_out_o[mio_sel_i] == 1'b1) + `ASSERT(MioSleepMode2_A, ##1 mio_pad_sleep_mode.q == 2 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + mio_out_o[mio_sel_i] == 1'b0) + `ASSERT(MioSleepMode3_A, ##1 mio_pad_sleep_mode.q == 3 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + $stable(mio_out_o[mio_sel_i])) + `ASSERT(MioSleepStable_A, ##1 !$rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + $stable(mio_out_o[mio_sel_i])) + + `ASSERT(MioOeSleepMode0_A, ##1 mio_pad_sleep_mode.q == 0 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q && sleep_en_i|-> + mio_oe_o[mio_sel_i] == 1'b1) + `ASSERT(MioOeSleepMode1_A, ##1 mio_pad_sleep_mode.q == 1 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + mio_oe_o[mio_sel_i] == 1'b1) + `ASSERT(MioOeSleepMode2_A, ##1 mio_pad_sleep_mode.q == 2 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + mio_oe_o[mio_sel_i] == 1'b0) + `ASSERT(MioOeSleepMode3_A, ##1 mio_pad_sleep_mode.q == 3 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + $stable(mio_oe_o[mio_sel_i])) + `ASSERT(MioOeSleepStable_A, ##1 !$rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + $stable(mio_oe_o[mio_sel_i])) + + // ------Mio sleep enabled backward assertions ------ + `ASSERT(MioSleep0Backward_A, mio_out_o[mio_sel_i] == 0 |-> + mio_pad_sleep_status.q == 0 || + // Sleep mode set to 0 and 2. + $past(mio_pad_sleep_mode.q) inside {0, 2} || + // Previous value is 0 and sleep mode is set to 3. + ($past(mio_out_o[mio_sel_i]) == 0) && + ($past(mio_pad_sleep_mode.q) == 3 || + // Previous value is 0 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !mio_pad_sleep_en.q) && mio_pad_sleep_status.q))) + + `ASSERT(MioSleep1Backward_A, mio_out_o[mio_sel_i] == 1 |-> + mio_pad_sleep_status.q == 0 || + // Sleep mode set to 1. + $past(mio_pad_sleep_mode.q) == 1 || + // Previous value is 1 and sleep mode is set to 3. + ($past(mio_out_o[mio_sel_i]) == 1) && + ($past(mio_pad_sleep_mode.q) == 3 || + // Previous value is 1 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !mio_pad_sleep_en.q) && mio_pad_sleep_status.q))) + + `ASSERT(MioOeSleep0Backward_A, mio_oe_o[mio_sel_i] == 0 |-> + mio_pad_sleep_status.q == 0 || + // Sleep mode set to 2. + $past(mio_pad_sleep_mode.q) == 2 || + // Previous value is 0 and sleep mode is set to 3. + ($past(mio_oe_o[mio_sel_i]) == 0) && + ($past(mio_pad_sleep_mode.q) == 3 || + // Previous value is 0 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !mio_pad_sleep_en.q) && mio_pad_sleep_status.q))) + + `ASSERT(MioOeSleep1Backward_A, mio_oe_o[mio_sel_i] == 1 |-> + mio_pad_sleep_status.q == 0 || + // Sleep mode set to 0 or 1. + $past(mio_pad_sleep_mode.q) inside {0, 1} || + // Previous value is 1 and sleep mode is set to 3. + ($past(mio_oe_o[mio_sel_i]) == 1) && + ($past(mio_pad_sleep_mode.q) == 3 || + // Previous value is 1 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !mio_pad_sleep_en.q) && mio_pad_sleep_status.q))) + + // ------ Mio_attr_o ------ + pad_attr_t mio_pad_attr; + assign mio_pad_attr = pinmux.mio_pad_attr_q[mio_sel_i]; + + pad_attr_t mio_pad_attr_mask; + pad_type_e bid_pad_types[4]; + assign bid_pad_types = {BidirStd, BidirTol, DualBidirTol, BidirOd}; + assign mio_pad_attr_mask.invert = TargetCfg.mio_pad_type[mio_sel_i] != AnalogIn0; + assign mio_pad_attr_mask.virt_od_en = TargetCfg.mio_pad_type[mio_sel_i] inside {bid_pad_types}; + assign mio_pad_attr_mask.pull_en = TargetCfg.mio_pad_type[mio_sel_i] != AnalogIn0; + assign mio_pad_attr_mask.pull_select = TargetCfg.mio_pad_type[mio_sel_i] != AnalogIn0; + assign mio_pad_attr_mask.drive_strength[0] = + TargetCfg.mio_pad_type[mio_sel_i] inside {bid_pad_types}; + assign mio_pad_attr_mask.keep_en = 0; + assign mio_pad_attr_mask.schmitt_en = 0; + assign mio_pad_attr_mask.od_en = 0; + assign mio_pad_attr_mask.input_disable = 1'b1; + assign mio_pad_attr_mask.slew_rate = '0; + assign mio_pad_attr_mask.drive_strength[3:1] = '0; + + `ASSERT(MioAttrO_A, mio_attr_o[mio_sel_i] == (mio_pad_attr & mio_pad_attr_mask)) + + `ASSERT(MioJtagAttrO_A, pinmux.u_pinmux_strap_sampling.jtag_en |-> + mio_attr_o[TargetCfg.tck_idx] == 0 && + mio_attr_o[TargetCfg.tms_idx] == 0 && + mio_attr_o[TargetCfg.trst_idx] == 0 && + mio_attr_o[TargetCfg.tdi_idx] == 0 && + mio_attr_o[TargetCfg.tdo_idx] == 0) + + // ------ Dio_attr_o ------ + pinmux_reg_pkg::pinmux_reg2hw_dio_pad_attr_mreg_t dio_pad_attr; + assign dio_pad_attr = pinmux.dio_pad_attr_q[dio_sel_i]; + + pad_attr_t dio_pad_attr_mask; + assign dio_pad_attr_mask.invert = TargetCfg.dio_pad_type[dio_sel_i] != AnalogIn0; + assign dio_pad_attr_mask.virt_od_en = TargetCfg.dio_pad_type[dio_sel_i] inside {bid_pad_types}; + assign dio_pad_attr_mask.pull_en = TargetCfg.dio_pad_type[dio_sel_i] != AnalogIn0; + assign dio_pad_attr_mask.pull_select = TargetCfg.dio_pad_type[dio_sel_i] != AnalogIn0; + assign dio_pad_attr_mask.drive_strength[0] = + TargetCfg.dio_pad_type[dio_sel_i] inside {bid_pad_types}; + assign dio_pad_attr_mask.keep_en = 0; + assign dio_pad_attr_mask.schmitt_en = 0; + assign dio_pad_attr_mask.od_en = 0; + assign dio_pad_attr_mask.input_disable = 1; + assign dio_pad_attr_mask.slew_rate = '0; + assign dio_pad_attr_mask.drive_strength[3:1] = '0; + + `ASSERT(DioAttrO_A, dio_attr_o[dio_sel_i] == (dio_pad_attr & dio_pad_attr_mask)) + + // ------ Output dedicated output assertions ------ + pinmux_reg_pkg::pinmux_reg2hw_dio_pad_sleep_status_mreg_t dio_pad_sleep_status; + assign dio_pad_sleep_status = pinmux.reg2hw.dio_pad_sleep_status[dio_sel_i]; + + `ASSERT(DOutSelN_A, !dio_pad_sleep_status.q |-> + dio_out_o[dio_sel_i] == periph_to_dio_i[dio_sel_i]) + + `ASSERT(DOutSelOeN_A, !dio_pad_sleep_status.q |-> + dio_oe_o[dio_sel_i] == periph_to_dio_oe_i[dio_sel_i]) + + // ------ Dio sleep behavior assertions ------ + pinmux_reg_pkg::pinmux_reg2hw_dio_pad_sleep_en_mreg_t dio_pad_sleep_en; + assign dio_pad_sleep_en = pinmux.reg2hw.dio_pad_sleep_en[dio_sel_i]; + pinmux_reg_pkg::pinmux_reg2hw_dio_pad_sleep_mode_mreg_t dio_pad_sleep_mode; + assign dio_pad_sleep_mode = pinmux.reg2hw.dio_pad_sleep_mode[dio_sel_i]; + + `ASSERT(DioSleepMode0_A, ##1 dio_pad_sleep_mode.q == 0 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + dio_out_o[dio_sel_i] == 1'b0) + `ASSERT(DioSleepMode1_A, ##1 dio_pad_sleep_mode.q == 1 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + dio_out_o[dio_sel_i] == 1'b1) + `ASSERT(DioSleepMode2_A, ##1 dio_pad_sleep_mode.q == 2 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + dio_out_o[dio_sel_i] == 1'b0) + `ASSERT(DioSleepMode3_A, ##1 dio_pad_sleep_mode.q == 3 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + $stable(dio_out_o[dio_sel_i])) + `ASSERT(DioSleepStable_A, ##1 !$rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + $stable(dio_out_o[dio_sel_i])) + + `ASSERT(DioOeSleepMode0_A, ##1 dio_pad_sleep_mode.q == 0 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + dio_oe_o[dio_sel_i] == 1'b1) + `ASSERT(DioOeSleepMode1_A, ##1 dio_pad_sleep_mode.q == 1 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + dio_oe_o[dio_sel_i] == 1'b1) + `ASSERT(DioOeSleepMode2_A, ##1 dio_pad_sleep_mode.q == 2 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + dio_oe_o[dio_sel_i] == 1'b0) + `ASSERT(DioOeSleepMode3_A, ##1 dio_pad_sleep_mode.q == 3 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + $stable(dio_oe_o[dio_sel_i])) + `ASSERT(DioOeSleepStable_A, ##1 !$rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + $stable(dio_oe_o[dio_sel_i])) + + // ------Dio backward assertions ------ + `ASSERT(Dio0Backward_A, dio_out_o[dio_sel_i] == 0 |-> + // Input is 0. + periph_to_dio_i[dio_sel_i] == 0 || + // Sleep mode set to 0 and 2. + $past(dio_pad_sleep_mode.q) inside {0, 2} || + // Previous value is 0 and sleep mode is set to 3. + ($past(dio_out_o[dio_sel_i]) == 0) && + ($past(dio_pad_sleep_mode.q) == 3 || + // Previous value is 0 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !dio_pad_sleep_en.q) && dio_pad_sleep_status.q))) + + `ASSERT(Dio1Backward_A, dio_out_o[dio_sel_i] == 1 |-> + // input is 1. + periph_to_dio_i[dio_sel_i] == 1 || + // Sleep mode set to 1. + $past(dio_pad_sleep_mode.q) == 1 || + // Previous value is 1 and sleep mode is set to 3. + ($past(dio_out_o[dio_sel_i]) == 1) && + ($past(dio_pad_sleep_mode.q) == 3 || + // Previous value is 1 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !dio_pad_sleep_en.q) && dio_pad_sleep_status.q))) + + `ASSERT(DioOe0Backward_A, dio_oe_o[dio_sel_i] == 0 |-> + // Input is 0. + periph_to_dio_oe_i[dio_sel_i] == 0 || + // Sleep mode set to 2. + $past(dio_pad_sleep_mode.q) == 2 || + // Previous value is 0 and sleep mode is set to 3. + ($past(dio_oe_o[dio_sel_i]) == 0) && + ($past(dio_pad_sleep_mode.q) == 3 || + // Previous value is 0 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !dio_pad_sleep_en.q) && dio_pad_sleep_status.q))) + + `ASSERT(DioOe1Backward_A, dio_oe_o[dio_sel_i] == 1 |-> + // input is 1. + periph_to_dio_oe_i[dio_sel_i] == 1 || + // Sleep mode set to 0 or 1. + $past(dio_pad_sleep_mode.q) inside {0, 1} || + // Previous value is 1 and sleep mode is set to 3. + ($past(dio_oe_o[dio_sel_i]) == 1) && + ($past(dio_pad_sleep_mode.q) == 3 || + // Previous value is 1 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !dio_pad_sleep_en.q) && dio_pad_sleep_status.q))) + + // ------ Wakeup assertions ------ + pinmux_reg2hw_wkup_detector_en_mreg_t wkup_detector_en; + assign wkup_detector_en = pinmux.reg2hw.wkup_detector_en[wkup_sel_i]; + pinmux_reg2hw_wkup_detector_mreg_t wkup_detector; + assign wkup_detector = pinmux.reg2hw.wkup_detector[wkup_sel_i]; + pinmux_reg2hw_wkup_detector_cnt_th_mreg_t wkup_detector_cnt_th; + assign wkup_detector_cnt_th = pinmux.reg2hw.wkup_detector_cnt_th[wkup_sel_i]; + pinmux_reg2hw_wkup_detector_padsel_mreg_t wkup_detector_padsel; + assign wkup_detector_padsel = pinmux.reg2hw.wkup_detector_padsel[wkup_sel_i]; + pinmux_hw2reg_wkup_cause_mreg_t wkup_cause; + assign wkup_cause = pinmux.hw2reg.wkup_cause[wkup_sel_i]; + pinmux_reg2hw_wkup_cause_mreg_t wkup_cause_reg2hw; + + // Variable to gether all wkup causes. + assign wkup_cause_reg2hw = pinmux.reg2hw.wkup_cause[wkup_sel_i]; + logic[pinmux_reg_pkg::NWkupDetect-1:0] wkup_cause_q; + for (genvar i = 0; i < pinmux_reg_pkg::NWkupDetect; i++) begin : gen_wkup_cause_q + assign wkup_cause_q[i] = pinmux.reg2hw.wkup_cause[i].q; + end + + // Retrieve pin value based on Mio and Dio selection. + logic pin_val; + assign pin_val = wkup_detector.miodio.q ? + (wkup_detector_padsel.q >= pinmux_reg_pkg::NDioPads ? 0 : + dio_in_i[wkup_detector_padsel.q]) : + (wkup_detector_padsel.q >= (pinmux_reg_pkg::NMioPads + 2) ? 0 : + wkup_detector_padsel == 0 ? 0 : + wkup_detector_padsel == 1 ? 1 : + mio_in_i[wkup_detector_padsel.q - 2]); + + // Retrieve filterd pin value with a 2 aon_clock synchronizer. + logic [3:0] filter_vals; + logic pin_val_sync_1, pin_val_sync_2; + + always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin + if (!rst_aon_ni) begin + pin_val_sync_1 <= 1'b0; + pin_val_sync_2 <= 1'b0; + end else begin + pin_val_sync_1 <= pin_val; + pin_val_sync_2 <= pin_val_sync_1; + end + end + + always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin + if (!rst_aon_ni) begin + filter_vals <= 4'b0; + end else if (pin_val_sync_2 == filter_vals[0]) begin + filter_vals <= (filter_vals << 1) | pin_val_sync_2; + end else begin + filter_vals <= {filter_vals[3], filter_vals[3], filter_vals[3], pin_val_sync_2}; + end + end + + logic final_pin_val; + assign final_pin_val = wkup_detector.filter.q ? filter_vals[3] : pin_val_sync_2; + + // Threshold counters. + // Adding one more bit for the counters to check overflow case. + // Issue #11194 documented design will use one counter to count for both low and high threshold. + bit [WkupCntWidth:0] cnter; + always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin + if (!rst_aon_ni || !wkup_detector_en.q) begin + cnter <= 0; + end else if (wkup_detector.mode.q == 3) begin + if (final_pin_val && (cnter < wkup_detector_cnt_th.q)) begin + cnter <= cnter + 1; + end else begin + cnter <= 0; + end + end else if (wkup_detector.mode.q == 4) begin + if (!final_pin_val && (cnter < wkup_detector_cnt_th.q)) begin + cnter <= cnter + 1; + end else begin + cnter <= 0; + end + end else begin + cnter <= 0; + end + end + + `ASSERT(WkupPosedge_A, wkup_detector_en.q && wkup_detector.mode.q == 0 && + $rose(final_pin_val) |-> wkup_cause.de, + clk_aon_i, !rst_aon_ni) + `ASSERT(WkupNegedge_A, wkup_detector_en.q && wkup_detector.mode.q == 1 && + $fell(final_pin_val) |-> wkup_cause.de, + clk_aon_i, !rst_aon_ni) + `ASSERT(WkupEdge_A, wkup_detector_en.q && wkup_detector.mode.q == 2 && + ($fell(final_pin_val) || $rose(final_pin_val)) |-> wkup_cause.de, + clk_aon_i, !rst_aon_ni) + `ASSERT(WkupTimedHigh_A, (cnter >= wkup_detector_cnt_th.q) && wkup_detector_en.q && + wkup_detector.mode.q == 3 |-> wkup_cause.de, + clk_aon_i, !rst_aon_ni) + `ASSERT(WkupTimedLow_A, (cnter >= wkup_detector_cnt_th.q) && wkup_detector_en.q && + wkup_detector.mode.q == 4 |-> wkup_cause.de, + clk_aon_i, !rst_aon_ni) + + `ASSERT(WkupCauseQ_A, wkup_cause.de && !u_reg.aon_wkup_cause_we |=> + wkup_cause_reg2hw.q, clk_aon_i, !rst_aon_ni) + + `ASSERT(AonWkupO_A, |wkup_cause_q <-> pin_wkup_req_o, clk_aon_i, !rst_aon_ni) + + `ASSERT(WkupCause0_A, wkup_cause.de == 0 |-> + (wkup_detector_en.q == 0) || + (wkup_detector_en.q == 1 && + ((wkup_detector.mode.q == 0 && !$rose(final_pin_val)) || + (wkup_detector.mode.q > 4 && !$rose(final_pin_val)) || + (wkup_detector.mode.q == 1 && !$fell(final_pin_val)) || + (wkup_detector.mode.q == 2 && !$changed(final_pin_val)) || + (wkup_detector.mode.q == 3 && (cnter < wkup_detector_cnt_th.q)) || + (wkup_detector.mode.q == 4 && (cnter < wkup_detector_cnt_th.q)))), + clk_aon_i, !rst_aon_ni) + + `ASSERT(WkupCause1_A, wkup_cause.de == 1 |-> + wkup_detector_en.q == 1 && + ((wkup_detector.mode.q == 0 && $rose(final_pin_val)) || + (wkup_detector.mode.q > 4 && $rose(final_pin_val)) || + (wkup_detector.mode.q == 1 && $fell(final_pin_val)) || + (wkup_detector.mode.q == 2 && $changed(final_pin_val)) || + (wkup_detector.mode.q == 3 && (cnter >= wkup_detector_cnt_th.q)) || + (wkup_detector.mode.q == 4 && (cnter >= wkup_detector_cnt_th.q))), + clk_aon_i, !rst_aon_ni) + + // Fatal alert related assertions + `ASSUME(TriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> + pinmux.u_reg.intg_err_o == 0 [*10]) + `ASSERT(TlIntgFatalAlert_A, pinmux.u_reg.intg_err_o |-> (##[0:7] (alert_tx_o[0].alert_p)) [*2]) + + // Since the USB wake module is blackboxed, we have to add an assumption here since the + // ASSERT_KNOWN assertions embedded in pinmux.sv would fail otherwise. + `ASSUME_FPV(UsbWkupReqKnownO_M, + !$isunknown(u_usbdev_aon_wake.wake_req_aon_o), clk_aon_i, !rst_aon_ni) + `ASSUME_FPV(UsbWakeDetectActiveKnownO_M, + !$isunknown(u_usbdev_aon_wake.wake_detect_active_aon_o), clk_aon_i, !rst_aon_ni) + +endmodule : pinmux_assert_fpv diff --git a/hw/top_darjeeling/ip_autogen/pinmux/lint/pinmux.vlt b/hw/top_darjeeling/ip_autogen/pinmux/lint/pinmux.vlt new file mode 100644 index 0000000000000..26ea262b5bc4a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/lint/pinmux.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for pinmux diff --git a/hw/top_darjeeling/ip_autogen/pinmux/lint/pinmux.waiver b/hw/top_darjeeling/ip_autogen/pinmux/lint/pinmux.waiver new file mode 100644 index 0000000000000..f62b61eeefc6f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/lint/pinmux.waiver @@ -0,0 +1,42 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for pinmux + +waive -rules NOT_READ -location {pinmux_reg_top.sv} -regexp {.*reg_wdata.*} \ + -comment "Upper bits of reg_wdata are not read" + +waive -rules HIER_NET_NOT_READ -location {pinmux_reg_top.sv} -regexp {.*reg_wdata.*} \ + -comment "Upper bits of reg_wdata are not read" + +waive -rules VAR_INDEX_RANGE -location {pinmux.sv} -regexp {.*maximum value.*} \ + -comment "Indexed arrays may not be fully populated." + +waive -rules RESET_USE -location {pinmux_strap_sampling.sv} -regexp {'rst_ni' is connected to 'prim_clock_mux2' port 'clk1_i +', and used as an asynchronous reset or set at pinmux_strap_sampling} \ + -comment "This is a clock mux for DFT." + +waive -rules RESET_MUX -location {pinmux_strap_sampling.sv} -regexp {Asynchronous reset 'rst_ni' reaches a multiplexer here, used as a reset at pinmux_strap_sampling} \ + -comment "This is a clock mux for DFT." + +waive -rules {CLOCK_DRIVER CLOCK_MUX} -location {pinmux_strap_sampling.sv} -regexp {'(lc|rv)_jtag_req.tck' is driven( by a multiplexer)? here,( and)? used as a clock 'tck_i' at dmi_jtag_tap.sv} \ + -comment "These signals are muxed using the JTAG Selection Mux." + +waive -rules CLOCK_MUX -location {pinmux_strap_sampling.sv pinmux.sv} -regexp {Clock '(in_padring_i\[38\]|mio_in_i\[38\]|jtag_req.tck)' reaches a multiplexer here, used as a clock 'tck_i' at dmi_jtag_tap.sv} \ + -comment "The 'mio_in_i[TckPadIdx]' input signal is connected to 'jtag_req.tck' which eventually feeds into the JTAG Selection Mux." + +waive -rules CLOCK_DRIVER -location {pinmux.sv} -regexp {'mio_attr\[28\].pull_select' is driven here, and used as a clock} \ + -comment "'MioPadIoc6' at index 28 may also serve as an external clock input. The 'pull_select' signal impacts the actual value obtained from the pad simulation model." + +waive -rules CLOCK_USE -location {pinmux.sv} -regexp {'hw2reg.mio_pad_attr\[28\].pull_select.d' is connected to 'pinmux_reg_top' port 'hw2reg.mio_pad_attr\[28\].pull_select.d', and used as a clock} \ + -comment "'MioPadIoc6' at index 28 may also serve as an external clock input. The 'pull_select' signal impacts the actual value obtained from the pad simulation model." + +waive -rules CLOCK_USE -location {pinmux.sv} -regexp {'(dio_wkup_mux\[12\]|dio_wkup_mux\[13\]|mio_wkup_mux\[40\])' is used for some other purpose, and as clock} \ + -comment "The wakeup detectors can be configured to observe any MIO / DIO pins. 'DioSpiDeviceSck' (index 12) is the spi_device clock, 'DioSpiDeviceCsb' (index 13) is the spi_device chip select (used as a clock for detecting toggles inside spi_device), and 'Dft0PadIdx' (index 40) controls the first TAP strap and thus the TAP selection mux driving the JTAG clocks." + +waive -rules CLOCK_MUX -location {pinmux.sv} -regexp {Clock 'dio_in_i\[12\]' reaches a multiplexer here, used as a clock 'clk_i'} \ + -comment "This mux is required to filter designated scan clock inputs (e.g. 'DioSpiDeviceSck' at index 12) from wakeup detector inputs" + +waive -rules RESET_ONLY -location {pinmux.sv} -regexp {'mio_pad_attr_q\[0\]' is asynchronously reset but has no other assignments in this block} \ + -comment "This error can safely be ignored: The signal is obviously driven further down in the very same block, changing the TargetCfg.tap_strap0_idx value to a non-zero value (which it actually is in the Earlgrey top level) makes the error go away." diff --git a/hw/top_darjeeling/ip_autogen/pinmux/pinmux.core b/hw/top_darjeeling/ip_autogen/pinmux/pinmux.core new file mode 100644 index 0000000000000..6080281ea350e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/pinmux.core @@ -0,0 +1,95 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_pinmux:0.1 +description: "Pin Multiplexer" +virtual: + - lowrisc:ip_interfaces:pinmux + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:all + - lowrisc:prim:clock_buf + - lowrisc:prim:buf + - lowrisc:prim:lc_dec + - lowrisc:prim:lc_sync + - lowrisc:prim:lc_sender + - lowrisc:prim:lc_or_hardened + - lowrisc:prim:pad_wrapper_pkg + - lowrisc:prim:pad_attr + - lowrisc:ip:jtag_pkg + - lowrisc:ip:usbdev + - lowrisc:opentitan:top_darjeeling_pinmux_reg:0.1 + - lowrisc:ip_interfaces:pinmux_pkg + files: + - rtl/pinmux_wkup.sv + - rtl/pinmux_jtag_buf.sv + - rtl/pinmux_jtag_breakout.sv + - rtl/pinmux.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pinmux.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pinmux.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: pinmux + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" + + syn: + <<: *default_target + # TODO: set default to DC once + # this option is available + # olofk/edalize#89 + default_tool: icarus + parameters: + - SYNTHESIS=true + + formal: + filesets: + - files_rtl + toplevel: pinmux_tb diff --git a/hw/top_darjeeling/ip_autogen/pinmux/pinmux_pkg.core b/hw/top_darjeeling/ip_autogen/pinmux/pinmux_pkg.core new file mode 100644 index 0000000000000..f721db0098611 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/pinmux_pkg.core @@ -0,0 +1,22 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:ip:pinmux_pkg:0.1" +description: "Pinmux package" +virtual: + - lowrisc:ip_interfaces:pinmux_pkg + +filesets: + files_rtl: + depend: + - lowrisc:prim:pad_wrapper_pkg + - lowrisc:ip_interfaces:pinmux_reg + files: + - rtl/pinmux_pkg.sv + file_type: systemVerilogSource + +targets: + default: &default_target + filesets: + - files_rtl diff --git a/hw/top_darjeeling/ip_autogen/pinmux/pinmux_reg.core b/hw/top_darjeeling/ip_autogen/pinmux/pinmux_reg.core new file mode 100644 index 0000000000000..9882819e798fb --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/pinmux_reg.core @@ -0,0 +1,22 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_pinmux_reg:0.1 +description: "Auto-generated pinmux register sources" +virtual: + - lowrisc:ip_interfaces:pinmux_reg + +filesets: + files_rtl: + depend: + - lowrisc:tlul:headers + files: + - rtl/pinmux_reg_pkg.sv + - rtl/pinmux_reg_top.sv + file_type: systemVerilogSource + +targets: + default: &default_target + filesets: + - files_rtl diff --git a/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux.sv b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux.sv new file mode 100644 index 0000000000000..6826bc46ab1f5 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux.sv @@ -0,0 +1,525 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Pinmux toplevel. +// + +`include "prim_assert.sv" + +module pinmux + import pinmux_pkg::*; + import pinmux_reg_pkg::*; + import prim_pad_wrapper_pkg::*; +#( + // Taget-specific pinmux configuration passed down from the + // target-specific top-level. + parameter target_cfg_t TargetCfg = DefaultTargetCfg, + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter bit SecVolatileRawUnlockEn = 0 +) ( + input clk_i, + input rst_ni, + input rst_sys_ni, + // Scan enable + input prim_mubi_pkg::mubi4_t scanmode_i, + // Slow always-on clock + input clk_aon_i, + input rst_aon_ni, + // Wakeup request, running on clk_aon_i + output logic pin_wkup_req_o, + // Sleep enable and strap sample enable + // from pwrmgr, running on clk_i + input sleep_en_i, + // Bus Interface (device) + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + // Muxed Peripheral side + input [NMioPeriphOut-1:0] periph_to_mio_i, + input [NMioPeriphOut-1:0] periph_to_mio_oe_i, + output logic [NMioPeriphIn-1:0] mio_to_periph_o, + // Dedicated Peripheral side + input [NDioPads-1:0] periph_to_dio_i, + input [NDioPads-1:0] periph_to_dio_oe_i, + output logic [NDioPads-1:0] dio_to_periph_o, + // Pad side + // MIOs + output prim_pad_wrapper_pkg::pad_attr_t [NMioPads-1:0] mio_attr_o, + output logic [NMioPads-1:0] mio_out_o, + output logic [NMioPads-1:0] mio_oe_o, + input [NMioPads-1:0] mio_in_i, + // DIOs + output prim_pad_wrapper_pkg::pad_attr_t [NDioPads-1:0] dio_attr_o, + output logic [NDioPads-1:0] dio_out_o, + output logic [NDioPads-1:0] dio_oe_o, + input [NDioPads-1:0] dio_in_i +); + + ////////////////////////////////// + // Regfile Breakout and Mapping // + ////////////////////////////////// + + logic [NumAlerts-1:0] alert_test, alerts; + pinmux_reg2hw_t reg2hw; + pinmux_hw2reg_t hw2reg; + + pinmux_reg_top u_reg ( + .clk_i, + .rst_ni, + .clk_aon_i, + .rst_aon_ni, + .tl_i, + .tl_o, + .reg2hw, + .hw2reg, + // SEC_CM: BUS.INTEGRITY + .intg_err_o(alerts[0]) + ); + + //////////// + // Alerts // + //////////// + + assign alert_test = { + reg2hw.alert_test.q & + reg2hw.alert_test.qe + }; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .IsFatal(1'b1) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[0] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + ///////////////////////////// + // Pad attribute registers // + ///////////////////////////// + + prim_pad_wrapper_pkg::pad_attr_t [NDioPads-1:0] dio_pad_attr_q; + prim_pad_wrapper_pkg::pad_attr_t [NMioPads-1:0] mio_pad_attr_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + dio_pad_attr_q <= '0; + for (int kk = 0; kk < NMioPads; kk++) begin + if (kk == TargetCfg.tap_strap0_idx) begin + // TAP strap 0 is sampled after reset (and only once for life cycle states that are not + // TEST_UNLOCKED* or RMA). To ensure it gets sampled as 0 unless driven to 1 from an + // external source (and specifically that it gets sampled as 0 when left floating / not + // connected), this enables the pull-down of the pad at reset. + mio_pad_attr_q[kk] <= '{pull_en: 1'b1, default: '0}; + end else begin + mio_pad_attr_q[kk] <= '0; + end + end + end else begin + // dedicated pads + for (int kk = 0; kk < NDioPads; kk++) begin + if (reg2hw.dio_pad_attr[kk].drive_strength.qe) begin + dio_pad_attr_q[kk].drive_strength <= reg2hw.dio_pad_attr[kk].drive_strength.q; + end + if (reg2hw.dio_pad_attr[kk].slew_rate.qe) begin + dio_pad_attr_q[kk].slew_rate <= reg2hw.dio_pad_attr[kk].slew_rate.q; + end + if (reg2hw.dio_pad_attr[kk].input_disable.qe) begin + dio_pad_attr_q[kk].input_disable <= reg2hw.dio_pad_attr[kk].input_disable.q; + end + if (reg2hw.dio_pad_attr[kk].od_en.qe) begin + dio_pad_attr_q[kk].od_en <= reg2hw.dio_pad_attr[kk].od_en.q; + end + if (reg2hw.dio_pad_attr[kk].schmitt_en.qe) begin + dio_pad_attr_q[kk].schmitt_en <= reg2hw.dio_pad_attr[kk].schmitt_en.q; + end + if (reg2hw.dio_pad_attr[kk].keeper_en.qe) begin + dio_pad_attr_q[kk].keep_en <= reg2hw.dio_pad_attr[kk].keeper_en.q; + end + if (reg2hw.dio_pad_attr[kk].pull_select.qe) begin + dio_pad_attr_q[kk].pull_select <= reg2hw.dio_pad_attr[kk].pull_select.q; + end + if (reg2hw.dio_pad_attr[kk].pull_en.qe) begin + dio_pad_attr_q[kk].pull_en <= reg2hw.dio_pad_attr[kk].pull_en.q; + end + if (reg2hw.dio_pad_attr[kk].virtual_od_en.qe) begin + dio_pad_attr_q[kk].virt_od_en <= reg2hw.dio_pad_attr[kk].virtual_od_en.q; + end + if (reg2hw.dio_pad_attr[kk].invert.qe) begin + dio_pad_attr_q[kk].invert <= reg2hw.dio_pad_attr[kk].invert.q; + end + end + // muxed pads + for (int kk = 0; kk < NMioPads; kk++) begin + if (reg2hw.mio_pad_attr[kk].drive_strength.qe) begin + mio_pad_attr_q[kk].drive_strength <= reg2hw.mio_pad_attr[kk].drive_strength.q; + end + if (reg2hw.mio_pad_attr[kk].slew_rate.qe) begin + mio_pad_attr_q[kk].slew_rate <= reg2hw.mio_pad_attr[kk].slew_rate.q; + end + if (reg2hw.mio_pad_attr[kk].input_disable.qe) begin + mio_pad_attr_q[kk].input_disable <= reg2hw.mio_pad_attr[kk].input_disable.q; + end + if (reg2hw.mio_pad_attr[kk].od_en.qe) begin + mio_pad_attr_q[kk].od_en <= reg2hw.mio_pad_attr[kk].od_en.q; + end + if (reg2hw.mio_pad_attr[kk].schmitt_en.qe) begin + mio_pad_attr_q[kk].schmitt_en <= reg2hw.mio_pad_attr[kk].schmitt_en.q; + end + if (reg2hw.mio_pad_attr[kk].keeper_en.qe) begin + mio_pad_attr_q[kk].keep_en <= reg2hw.mio_pad_attr[kk].keeper_en.q; + end + if (reg2hw.mio_pad_attr[kk].pull_select.qe) begin + mio_pad_attr_q[kk].pull_select <= reg2hw.mio_pad_attr[kk].pull_select.q; + end + if (reg2hw.mio_pad_attr[kk].pull_en.qe) begin + mio_pad_attr_q[kk].pull_en <= reg2hw.mio_pad_attr[kk].pull_en.q; + end + if (reg2hw.mio_pad_attr[kk].virtual_od_en.qe) begin + mio_pad_attr_q[kk].virt_od_en <= reg2hw.mio_pad_attr[kk].virtual_od_en.q; + end + if (reg2hw.mio_pad_attr[kk].invert.qe) begin + mio_pad_attr_q[kk].invert <= reg2hw.mio_pad_attr[kk].invert.q; + end + end + end + end + + //////////////////////// + // Connect attributes // + //////////////////////// + + pad_attr_t [NDioPads-1:0] dio_attr; + for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_attr + pad_attr_t warl_mask; + + prim_pad_attr #( + .PadType(TargetCfg.dio_pad_type[k]) + ) u_prim_pad_attr ( + .attr_warl_o(warl_mask) + ); + + assign dio_attr[k] = dio_pad_attr_q[k] & warl_mask; + assign hw2reg.dio_pad_attr[k].drive_strength.d = dio_attr[k].drive_strength; + assign hw2reg.dio_pad_attr[k].slew_rate.d = dio_attr[k].slew_rate; + assign hw2reg.dio_pad_attr[k].input_disable.d = dio_attr[k].input_disable; + assign hw2reg.dio_pad_attr[k].od_en.d = dio_attr[k].od_en; + assign hw2reg.dio_pad_attr[k].schmitt_en.d = dio_attr[k].schmitt_en; + assign hw2reg.dio_pad_attr[k].keeper_en.d = dio_attr[k].keep_en; + assign hw2reg.dio_pad_attr[k].pull_select.d = dio_attr[k].pull_select; + assign hw2reg.dio_pad_attr[k].pull_en.d = dio_attr[k].pull_en; + assign hw2reg.dio_pad_attr[k].virtual_od_en.d = dio_attr[k].virt_od_en; + assign hw2reg.dio_pad_attr[k].invert.d = dio_attr[k].invert; + end + + pad_attr_t [NMioPads-1:0] mio_attr; + for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_attr + pad_attr_t warl_mask; + + prim_pad_attr #( + .PadType(TargetCfg.mio_pad_type[k]) + ) u_prim_pad_attr ( + .attr_warl_o(warl_mask) + ); + + assign mio_attr[k] = mio_pad_attr_q[k] & warl_mask; + assign hw2reg.mio_pad_attr[k].drive_strength.d = mio_attr[k].drive_strength; + assign hw2reg.mio_pad_attr[k].slew_rate.d = mio_attr[k].slew_rate; + assign hw2reg.mio_pad_attr[k].input_disable.d = mio_attr[k].input_disable; + assign hw2reg.mio_pad_attr[k].od_en.d = mio_attr[k].od_en; + assign hw2reg.mio_pad_attr[k].schmitt_en.d = mio_attr[k].schmitt_en; + assign hw2reg.mio_pad_attr[k].keeper_en.d = mio_attr[k].keep_en; + assign hw2reg.mio_pad_attr[k].pull_select.d = mio_attr[k].pull_select; + assign hw2reg.mio_pad_attr[k].pull_en.d = mio_attr[k].pull_en; + assign hw2reg.mio_pad_attr[k].virtual_od_en.d = mio_attr[k].virt_od_en; + assign hw2reg.mio_pad_attr[k].invert.d = mio_attr[k].invert; + end + + // Just pass through these signals. + assign { dio_out_o, mio_out_o } = { dio_out, mio_out }; + assign { dio_oe_o , mio_oe_o } = { dio_oe, mio_oe }; + assign { dio_in, mio_i } = { dio_in_i, mio_in_i }; + assign { dio_attr_o, mio_attr_o } = { dio_attr, mio_attr }; + + ///////////////////////// + // Retention Registers // + ///////////////////////// + + logic sleep_en_q, sleep_trig; + + logic [NMioPads-1:0] mio_sleep_trig; + logic [NMioPads-1:0] mio_out_retreg_d, mio_oe_retreg_d; + logic [NMioPads-1:0] mio_out_retreg_q, mio_oe_retreg_q; + + logic [NDioPads-1:0] dio_sleep_trig; + logic [NDioPads-1:0] dio_out_retreg_d, dio_oe_retreg_d; + logic [NDioPads-1:0] dio_out_retreg_q, dio_oe_retreg_q; + + // Sleep entry trigger + assign sleep_trig = sleep_en_i & ~sleep_en_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_sleep + if (!rst_ni) begin + sleep_en_q <= 1'b0; + mio_out_retreg_q <= '0; + mio_oe_retreg_q <= '0; + dio_out_retreg_q <= '0; + dio_oe_retreg_q <= '0; + end else begin + sleep_en_q <= sleep_en_i; + + // MIOs + for (int k = 0; k < NMioPads; k++) begin + if (mio_sleep_trig[k]) begin + mio_out_retreg_q[k] <= mio_out_retreg_d[k]; + mio_oe_retreg_q[k] <= mio_oe_retreg_d[k]; + end + end + + // DIOs + for (int k = 0; k < NDioPads; k++) begin + if (dio_sleep_trig[k]) begin + dio_out_retreg_q[k] <= dio_out_retreg_d[k]; + dio_oe_retreg_q[k] <= dio_oe_retreg_d[k]; + end + end + end + end + + ///////////////////// + // MIO Input Muxes // + ///////////////////// + + localparam int AlignedMuxSize = (NMioPads + 2 > NDioPads) ? 2**$clog2(NMioPads + 2) : + 2**$clog2(NDioPads); + + // stack input and default signals for convenient indexing below possible defaults: + // constant 0 or 1. make sure mux is aligned to a power of 2 to avoid Xes. + logic [AlignedMuxSize-1:0] mio_mux; + assign mio_mux = AlignedMuxSize'({mio_in, 1'b1, 1'b0}); + + for (genvar k = 0; k < NMioPeriphIn; k++) begin : gen_mio_periph_in + // index using configured insel + assign mio_to_periph_o[k] = mio_mux[reg2hw.mio_periph_insel[k].q]; + end + + ////////////////////// + // MIO Output Muxes // + ////////////////////// + + // stack output data/enable and default signals for convenient indexing below + // possible defaults: 0, 1 or 2 (high-Z). make sure mux is aligned to a power of 2 to avoid Xes. + logic [2**$clog2(NMioPeriphOut+3)-1:0] periph_data_mux, periph_oe_mux; + assign periph_data_mux = $bits(periph_data_mux)'({periph_to_mio_i, 1'b0, 1'b1, 1'b0}); + assign periph_oe_mux = $bits(periph_oe_mux)'({periph_to_mio_oe_i, 1'b0, 1'b1, 1'b1}); + + for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_out + // Check individual sleep enable status bits + assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? + mio_out_retreg_q[k] : + periph_data_mux[reg2hw.mio_outsel[k].q]; + + assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? + mio_oe_retreg_q[k] : + periph_oe_mux[reg2hw.mio_outsel[k].q]; + + // latch state when going to sleep + // 0: drive low + // 1: drive high + // 2: high-z + // 3: previous value + assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : + (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : + (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; + + assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : + (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : + (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; + + // Activate sleep behavior only if it has been enabled + assign mio_sleep_trig[k] = reg2hw.mio_pad_sleep_en[k].q & sleep_trig; + assign hw2reg.mio_pad_sleep_status[k].d = 1'b1; + assign hw2reg.mio_pad_sleep_status[k].de = mio_sleep_trig[k]; + end + + ///////////////////// + // DIO connections // + ///////////////////// + + // Inputs are just fed through + assign dio_to_periph_o = dio_in; + + for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_out + // Check individual sleep enable status bits + assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? + dio_out_retreg_q[k] : + periph_to_dio_i[k]; + + assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? + dio_oe_retreg_q[k] : + periph_to_dio_oe_i[k]; + + // latch state when going to sleep + // 0: drive low + // 1: drive high + // 2: high-z + // 3: previous value + assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : + (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : + (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; + + assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : + (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : + (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; + + // Activate sleep behavior only if it has been enabled + assign dio_sleep_trig[k] = reg2hw.dio_pad_sleep_en[k].q & sleep_trig; + assign hw2reg.dio_pad_sleep_status[k].d = 1'b1; + assign hw2reg.dio_pad_sleep_status[k].de = dio_sleep_trig[k]; + end + + ////////////////////// + // Wakeup detectors // + ////////////////////// + + // Wakeup detectors should not be connected to the scan clock, so filter + // those inputs. + logic [NDioPads-1:0] dio_wkup_no_scan; + for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_wkup_filter + if (TargetCfg.dio_scan_role[k] == ScanClock) begin : gen_dio_scan + always_comb begin + dio_wkup_no_scan[k] = dio_in_i[k]; + if (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)) begin + dio_wkup_no_scan[k] = 1'b0; + end + end + end else begin : gen_no_dio_scan + assign dio_wkup_no_scan[k] = dio_in_i[k]; + end + end + + logic [NMioPads-1:0] mio_wkup_no_scan; + for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_wkup_filter + if (TargetCfg.mio_scan_role[k] == ScanClock) begin : gen_mio_scan + always_comb begin + mio_wkup_no_scan[k] = mio_in_i[k]; + if (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)) begin + mio_wkup_no_scan[k] = 1'b0; + end + end + end else begin : gen_no_mio_scan + assign mio_wkup_no_scan[k] = mio_in_i[k]; + end + end + + // Wakeup detector taps are not affected by JTAG/strap + // selection mux. I.e., we always sample the unmuxed inputs + // that come directly from the pads. + logic [AlignedMuxSize-1:0] dio_wkup_mux; + logic [AlignedMuxSize-1:0] mio_wkup_mux; + assign dio_wkup_mux = AlignedMuxSize'(dio_wkup_no_scan); + // The two constants that are concatenated here make sure tha the selection + // indices used to index this array are the same as the ones used to index + // the mio_mux array above, where positions 0 and 1 select constant 0 and + // 1, respectively. + assign mio_wkup_mux = AlignedMuxSize'({mio_wkup_no_scan, 1'b1, 1'b0}); + + logic [NWkupDetect-1:0] aon_wkup_req; + for (genvar k = 0; k < NWkupDetect; k++) begin : gen_wkup_detect + logic pin_value; + assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? + dio_wkup_mux[reg2hw.wkup_detector_padsel[k]] : + mio_wkup_mux[reg2hw.wkup_detector_padsel[k]]; + + // This module runs on the AON clock entirely + pinmux_wkup u_pinmux_wkup ( + .clk_i (clk_aon_i ), + .rst_ni (rst_aon_ni ), + // config signals have already been synced to the AON domain inside the CSR node. + .wkup_en_i ( reg2hw.wkup_detector_en[k].q ), + .filter_en_i ( reg2hw.wkup_detector[k].filter.q ), + .wkup_mode_i ( wkup_mode_e'(reg2hw.wkup_detector[k].mode.q) ), + .wkup_cnt_th_i ( reg2hw.wkup_detector_cnt_th[k].q ), + .pin_value_i ( pin_value ), + // wakeup request pulse on clk_aon, will be synced back to the bus domain insie the CSR node. + .aon_wkup_pulse_o ( hw2reg.wkup_cause[k].de ) + ); + + assign hw2reg.wkup_cause[k].d = 1'b1; + + // This is the latched wakeup request, hence this request signal is level encoded. + assign aon_wkup_req[k] = reg2hw.wkup_cause[k].q; + end + + // OR' together all wakeup requests + assign pin_wkup_req_o = |aon_wkup_req; + + //////////////// + // Assertions // + //////////////// + + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready) + `ASSERT_KNOWN(AlertsKnown_A, alert_tx_o) + `ASSERT_KNOWN(MioOeKnownO_A, mio_oe_o) + `ASSERT_KNOWN(DioOeKnownO_A, dio_oe_o) + + `ASSERT_KNOWN(MioKnownO_A, mio_attr_o) + `ASSERT_KNOWN(DioKnownO_A, dio_attr_o) + + `ASSERT_KNOWN(LcJtagTckKnown_A, lc_jtag_o.tck) + `ASSERT_KNOWN(LcJtagTrstKnown_A, lc_jtag_o.trst_n) + `ASSERT_KNOWN(LcJtagTmsKnown_A, lc_jtag_o.tms) + + `ASSERT_KNOWN(RvJtagTckKnown_A, rv_jtag_o.tck) + `ASSERT_KNOWN(RvJtagTrstKnown_A, rv_jtag_o.trst_n) + `ASSERT_KNOWN(RvJtagTmsKnown_A, rv_jtag_o.tms) + + `ASSERT_KNOWN(DftJtagTckKnown_A, dft_jtag_o.tck) + `ASSERT_KNOWN(DftJtagTrstKnown_A, dft_jtag_o.trst_n) + `ASSERT_KNOWN(DftJtagTmsKnown_A, dft_jtag_o.tms) + + `ASSERT_KNOWN(DftStrapsKnown_A, dft_strap_test_o) + + // running on slow AON clock + `ASSERT_KNOWN(AonWkupReqKnownO_A, pin_wkup_req_o, clk_aon_i, !rst_aon_ni) + + // The wakeup signal is not latched in the pwrmgr so must be held until acked by software + `ASSUME(PinmuxWkupStable_A, pin_wkup_req_o |=> pin_wkup_req_o || + $fell(|reg2hw.wkup_cause) && !sleep_en_i, clk_aon_i, !rst_aon_ni) + + // Some inputs at the chip-level may be forced to X in chip-level simulations. + // Therefore, we do not instantiate these assertions. + // `ASSERT_KNOWN(MioToPeriphKnownO_A, mio_to_periph_o) + // `ASSERT_KNOWN(DioToPeriphKnownO_A, dio_to_periph_o) + + // The assertions below are not instantiated for a similar reason as the assertions above. + // I.e., some IPs have pass-through paths, which may lead to X'es propagating + // from input to output. + // for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_known_if + // `ASSERT_KNOWN_IF(MioOutKnownO_A, mio_out_o[k], mio_oe_o[k]) + // end + // for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_known_if + // `ASSERT_KNOWN_IF(DioOutKnownO_A, dio_out_o[k], dio_oe_o[k]) + // end + + // Pinmux does not have a block-level DV environment, hence we add an FPV assertion to test this. + `ASSERT(FpvSecCmBusIntegrity_A, + $rose(u_reg.intg_err) + |-> + ##[0:`_SEC_CM_ALERT_MAX_CYC] (alert_tx_o[0].alert_p)) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0]) + +endmodule : pinmux diff --git a/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_jtag_breakout.sv b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_jtag_breakout.sv new file mode 100644 index 0000000000000..2acba6ff7406b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_jtag_breakout.sv @@ -0,0 +1,24 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module pinmux_jtag_breakout ( + input jtag_pkg::jtag_req_t req_i, + output jtag_pkg::jtag_rsp_t rsp_o, + + output logic tck_o, + output logic trst_no, + output logic tms_o, + output logic tdi_o, + input tdo_i, + input tdo_oe_i +); + + assign tck_o = req_i.tck; + assign trst_no = req_i.trst_n; + assign tms_o = req_i.tms; + assign tdi_o = req_i.tdi; + assign rsp_o.tdo = tdo_i; + assign rsp_o.tdo_oe = tdo_oe_i; + +endmodule : pinmux_jtag_breakout diff --git a/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_jtag_buf.sv b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_jtag_buf.sv new file mode 100644 index 0000000000000..161a0cb4cbe29 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_jtag_buf.sv @@ -0,0 +1,37 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module pinmux_jtag_buf ( + input jtag_pkg::jtag_req_t req_i, + output jtag_pkg::jtag_req_t req_o, + input jtag_pkg::jtag_rsp_t rsp_i, + output jtag_pkg::jtag_rsp_t rsp_o +); + + prim_clock_buf prim_clock_buf_tck ( + .clk_i(req_i.tck), + .clk_o(req_o.tck) + ); + prim_buf prim_buf_trst_n ( + .in_i (req_i.trst_n), + .out_o(req_o.trst_n) + ); + prim_buf prim_buf_tms ( + .in_i (req_i.tms), + .out_o(req_o.tms) + ); + prim_buf prim_buf_tdi ( + .in_i (req_i.tdi), + .out_o(req_o.tdi) + ); + prim_buf prim_buf_tdo ( + .in_i (rsp_i.tdo), + .out_o(rsp_o.tdo) + ); + prim_buf prim_buf_tdo_oe ( + .in_i (rsp_i.tdo_oe), + .out_o(rsp_o.tdo_oe) + ); + +endmodule : pinmux_jtag_buf diff --git a/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_pkg.sv b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_pkg.sv new file mode 100644 index 0000000000000..d2df26f6c0c8a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_pkg.sv @@ -0,0 +1,78 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package pinmux_pkg; + + import pinmux_reg_pkg::*; + import prim_pad_wrapper_pkg::*; + + parameter int NumIOs = NMioPads + NDioPads; + parameter int NDFTStraps = 2; + parameter int NTapStraps = 2; + + // Since the target-specific top-levels often have slightly different debug signal positions, we + // need a way to pass this info from the target specific top-level into the pinmux logic. The + // datastructure below serves this purpose. Note that all the indices below are with respect to + // the concatenated {DIO, MIO} packed array. + typedef struct packed { + integer tck_idx; + integer tms_idx; + integer trst_idx; + integer tdi_idx; + integer tdo_idx; + integer tap_strap0_idx; + integer tap_strap1_idx; + integer dft_strap0_idx; + integer dft_strap1_idx; + integer usb_dp_idx; + integer usb_dn_idx; + integer usb_sense_idx; + pad_type_e [NDioPads-1:0] dio_pad_type; + pad_type_e [NMioPads-1:0] mio_pad_type; + scan_role_e [NDioPads-1:0] dio_scan_role; + scan_role_e [NMioPads-1:0] mio_scan_role; + } target_cfg_t; + + parameter target_cfg_t DefaultTargetCfg = '{ + tck_idx: 0, + tms_idx: 0, + trst_idx: 0, + tdi_idx: 0, + tdo_idx: 0, + tap_strap0_idx: 0, + tap_strap1_idx: 0, + dft_strap0_idx: 0, + dft_strap1_idx: 0, + usb_dp_idx: 0, + usb_dn_idx: 0, + usb_sense_idx: 0, + dio_pad_type: {NDioPads{BidirStd}}, + mio_pad_type: {NMioPads{BidirStd}}, + dio_scan_role: {NDioPads{NoScan}}, + mio_scan_role: {NMioPads{NoScan}} + }; + + // Wakeup Detector Modes + typedef enum logic [2:0] { + Posedge = 3'b000, + Negedge = 3'b001, + Edge = 3'b010, + HighTimed = 3'b011, + LowTimed = 3'b100 + } wkup_mode_e; + + // Interface with LC controller + typedef struct packed { + logic valid; + logic [NDFTStraps-1:0] straps; + } dft_strap_test_req_t; + + typedef enum logic [NTapStraps-1:0] { + FuncSel = 2'b00, + LcTapSel = 2'b01, + RvTapSel = 2'b10, + DftTapSel = 2'b11 + } tap_strap_t; + +endpackage : pinmux_pkg diff --git a/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv new file mode 100644 index 0000000000000..32e4a8269cd84 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv @@ -0,0 +1,2744 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package pinmux_reg_pkg; + + // Param list + parameter int NMioPeriphIn = 4; + parameter int NMioPeriphOut = 5; + parameter int NMioPads = 12; + parameter int NDioPads = 73; + parameter int NWkupDetect = 8; + parameter int WkupCntWidth = 8; + parameter int NumAlerts = 1; + + // Address widths within the block + parameter int BlockAw = 11; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic q; + logic qe; + } pinmux_reg2hw_alert_test_reg_t; + + typedef struct packed { + logic [3:0] q; + } pinmux_reg2hw_mio_periph_insel_mreg_t; + + typedef struct packed { + logic [2:0] q; + } pinmux_reg2hw_mio_outsel_mreg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + logic qe; + } drive_strength; + struct packed { + logic [1:0] q; + logic qe; + } slew_rate; + struct packed { + logic q; + logic qe; + } input_disable; + struct packed { + logic q; + logic qe; + } od_en; + struct packed { + logic q; + logic qe; + } schmitt_en; + struct packed { + logic q; + logic qe; + } keeper_en; + struct packed { + logic q; + logic qe; + } pull_select; + struct packed { + logic q; + logic qe; + } pull_en; + struct packed { + logic q; + logic qe; + } virtual_od_en; + struct packed { + logic q; + logic qe; + } invert; + } pinmux_reg2hw_mio_pad_attr_mreg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + logic qe; + } drive_strength; + struct packed { + logic [1:0] q; + logic qe; + } slew_rate; + struct packed { + logic q; + logic qe; + } input_disable; + struct packed { + logic q; + logic qe; + } od_en; + struct packed { + logic q; + logic qe; + } schmitt_en; + struct packed { + logic q; + logic qe; + } keeper_en; + struct packed { + logic q; + logic qe; + } pull_select; + struct packed { + logic q; + logic qe; + } pull_en; + struct packed { + logic q; + logic qe; + } virtual_od_en; + struct packed { + logic q; + logic qe; + } invert; + } pinmux_reg2hw_dio_pad_attr_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_mio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_mio_pad_sleep_en_mreg_t; + + typedef struct packed { + logic [1:0] q; + } pinmux_reg2hw_mio_pad_sleep_mode_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_dio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_dio_pad_sleep_en_mreg_t; + + typedef struct packed { + logic [1:0] q; + } pinmux_reg2hw_dio_pad_sleep_mode_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_wkup_detector_en_mreg_t; + + typedef struct packed { + struct packed { + logic q; + } miodio; + struct packed { + logic q; + } filter; + struct packed { + logic [2:0] q; + } mode; + } pinmux_reg2hw_wkup_detector_mreg_t; + + typedef struct packed { + logic [7:0] q; + } pinmux_reg2hw_wkup_detector_cnt_th_mreg_t; + + typedef struct packed { + logic [5:0] q; + } pinmux_reg2hw_wkup_detector_padsel_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_wkup_cause_mreg_t; + + typedef struct packed { + struct packed { + logic d; + } invert; + struct packed { + logic d; + } virtual_od_en; + struct packed { + logic d; + } pull_en; + struct packed { + logic d; + } pull_select; + struct packed { + logic d; + } keeper_en; + struct packed { + logic d; + } schmitt_en; + struct packed { + logic d; + } od_en; + struct packed { + logic d; + } input_disable; + struct packed { + logic [1:0] d; + } slew_rate; + struct packed { + logic [3:0] d; + } drive_strength; + } pinmux_hw2reg_mio_pad_attr_mreg_t; + + typedef struct packed { + struct packed { + logic d; + } invert; + struct packed { + logic d; + } virtual_od_en; + struct packed { + logic d; + } pull_en; + struct packed { + logic d; + } pull_select; + struct packed { + logic d; + } keeper_en; + struct packed { + logic d; + } schmitt_en; + struct packed { + logic d; + } od_en; + struct packed { + logic d; + } input_disable; + struct packed { + logic [1:0] d; + } slew_rate; + struct packed { + logic [3:0] d; + } drive_strength; + } pinmux_hw2reg_dio_pad_attr_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pinmux_hw2reg_mio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pinmux_hw2reg_dio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pinmux_hw2reg_wkup_cause_mreg_t; + + // Register -> HW type + typedef struct packed { + pinmux_reg2hw_alert_test_reg_t alert_test; // [2601:2600] + pinmux_reg2hw_mio_periph_insel_mreg_t [3:0] mio_periph_insel; // [2599:2584] + pinmux_reg2hw_mio_outsel_mreg_t [11:0] mio_outsel; // [2583:2548] + pinmux_reg2hw_mio_pad_attr_mreg_t [11:0] mio_pad_attr; // [2547:2260] + pinmux_reg2hw_dio_pad_attr_mreg_t [72:0] dio_pad_attr; // [2259:508] + pinmux_reg2hw_mio_pad_sleep_status_mreg_t [11:0] mio_pad_sleep_status; // [507:496] + pinmux_reg2hw_mio_pad_sleep_en_mreg_t [11:0] mio_pad_sleep_en; // [495:484] + pinmux_reg2hw_mio_pad_sleep_mode_mreg_t [11:0] mio_pad_sleep_mode; // [483:460] + pinmux_reg2hw_dio_pad_sleep_status_mreg_t [72:0] dio_pad_sleep_status; // [459:387] + pinmux_reg2hw_dio_pad_sleep_en_mreg_t [72:0] dio_pad_sleep_en; // [386:314] + pinmux_reg2hw_dio_pad_sleep_mode_mreg_t [72:0] dio_pad_sleep_mode; // [313:168] + pinmux_reg2hw_wkup_detector_en_mreg_t [7:0] wkup_detector_en; // [167:160] + pinmux_reg2hw_wkup_detector_mreg_t [7:0] wkup_detector; // [159:120] + pinmux_reg2hw_wkup_detector_cnt_th_mreg_t [7:0] wkup_detector_cnt_th; // [119:56] + pinmux_reg2hw_wkup_detector_padsel_mreg_t [7:0] wkup_detector_padsel; // [55:8] + pinmux_reg2hw_wkup_cause_mreg_t [7:0] wkup_cause; // [7:0] + } pinmux_reg2hw_t; + + // HW -> register type + typedef struct packed { + pinmux_hw2reg_mio_pad_attr_mreg_t [11:0] mio_pad_attr; // [1375:1208] + pinmux_hw2reg_dio_pad_attr_mreg_t [72:0] dio_pad_attr; // [1207:186] + pinmux_hw2reg_mio_pad_sleep_status_mreg_t [11:0] mio_pad_sleep_status; // [185:162] + pinmux_hw2reg_dio_pad_sleep_status_mreg_t [72:0] dio_pad_sleep_status; // [161:16] + pinmux_hw2reg_wkup_cause_mreg_t [7:0] wkup_cause; // [15:0] + } pinmux_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] PINMUX_ALERT_TEST_OFFSET = 11'h 0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET = 11'h 4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET = 11'h 8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET = 11'h c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET = 11'h 10; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 11'h 14; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 11'h 18; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 11'h 1c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 11'h 20; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 11'h 24; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 11'h 28; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 11'h 2c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 11'h 30; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 11'h 34; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 11'h 38; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 11'h 3c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 11'h 40; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 11'h 44; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 11'h 48; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 11'h 4c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 11'h 50; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 11'h 54; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 11'h 58; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 11'h 5c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 11'h 60; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 11'h 64; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 11'h 68; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 11'h 6c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 11'h 70; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 11'h 74; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 11'h 78; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 11'h 7c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 11'h 80; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 84; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 88; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 8c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 90; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 94; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 98; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 9c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 11'h b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 11'h b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 11'h bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 11'h c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 11'h c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 11'h c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 11'h cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 11'h d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 11'h d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 11'h d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 11'h dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 11'h e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 100; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 104; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 108; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 10c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 110; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 114; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 118; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 11c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 11'h 120; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET = 11'h 124; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET = 11'h 128; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET = 11'h 12c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET = 11'h 130; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET = 11'h 134; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET = 11'h 138; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET = 11'h 13c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_23_OFFSET = 11'h 140; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_24_OFFSET = 11'h 144; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_25_OFFSET = 11'h 148; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_26_OFFSET = 11'h 14c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_27_OFFSET = 11'h 150; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_28_OFFSET = 11'h 154; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_29_OFFSET = 11'h 158; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_30_OFFSET = 11'h 15c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_31_OFFSET = 11'h 160; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_32_OFFSET = 11'h 164; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_33_OFFSET = 11'h 168; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_34_OFFSET = 11'h 16c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_35_OFFSET = 11'h 170; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_36_OFFSET = 11'h 174; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_37_OFFSET = 11'h 178; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_38_OFFSET = 11'h 17c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_39_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_40_OFFSET = 11'h 184; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_41_OFFSET = 11'h 188; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_42_OFFSET = 11'h 18c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_43_OFFSET = 11'h 190; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_44_OFFSET = 11'h 194; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_45_OFFSET = 11'h 198; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_46_OFFSET = 11'h 19c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_47_OFFSET = 11'h 1a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_48_OFFSET = 11'h 1a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_49_OFFSET = 11'h 1a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_50_OFFSET = 11'h 1ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_51_OFFSET = 11'h 1b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_52_OFFSET = 11'h 1b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_53_OFFSET = 11'h 1b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_54_OFFSET = 11'h 1bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_55_OFFSET = 11'h 1c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_56_OFFSET = 11'h 1c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_57_OFFSET = 11'h 1c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_58_OFFSET = 11'h 1cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_59_OFFSET = 11'h 1d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_60_OFFSET = 11'h 1d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_61_OFFSET = 11'h 1d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_62_OFFSET = 11'h 1dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_63_OFFSET = 11'h 1e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_64_OFFSET = 11'h 1e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_65_OFFSET = 11'h 1e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_66_OFFSET = 11'h 1ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_67_OFFSET = 11'h 1f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_68_OFFSET = 11'h 1f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_69_OFFSET = 11'h 1f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_70_OFFSET = 11'h 1fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_71_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_72_OFFSET = 11'h 204; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 11'h 208; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 11'h 20c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 11'h 210; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 11'h 214; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 11'h 218; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 11'h 21c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 11'h 220; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 11'h 224; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 11'h 228; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 11'h 22c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 11'h 230; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 11'h 234; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 11'h 238; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 11'h 23c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 11'h 240; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 11'h 244; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_16_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_17_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_18_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_19_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_20_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_21_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_22_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_23_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_24_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_25_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_26_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_27_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_28_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_29_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_30_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_31_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_32_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_33_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_34_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_35_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_36_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_37_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_38_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_39_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_40_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_41_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_42_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_43_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_44_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_45_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_46_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_47_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_48_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_49_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_50_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_51_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_52_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_53_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_54_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_55_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_56_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_57_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_58_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_59_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_60_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_61_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_62_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_63_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_64_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_65_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_66_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_67_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_68_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_69_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_70_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_71_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_72_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_0_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_1_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_2_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_23_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_24_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_25_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_26_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_27_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_28_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_29_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_30_OFFSET = 11'h 444; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_31_OFFSET = 11'h 448; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_32_OFFSET = 11'h 44c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_33_OFFSET = 11'h 450; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_34_OFFSET = 11'h 454; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_35_OFFSET = 11'h 458; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_36_OFFSET = 11'h 45c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_37_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_38_OFFSET = 11'h 464; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_39_OFFSET = 11'h 468; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_40_OFFSET = 11'h 46c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_41_OFFSET = 11'h 470; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_42_OFFSET = 11'h 474; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_43_OFFSET = 11'h 478; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_44_OFFSET = 11'h 47c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_45_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_46_OFFSET = 11'h 484; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_47_OFFSET = 11'h 488; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_48_OFFSET = 11'h 48c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_49_OFFSET = 11'h 490; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_50_OFFSET = 11'h 494; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_51_OFFSET = 11'h 498; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_52_OFFSET = 11'h 49c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_53_OFFSET = 11'h 4a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_54_OFFSET = 11'h 4a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_55_OFFSET = 11'h 4a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_56_OFFSET = 11'h 4ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_57_OFFSET = 11'h 4b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_58_OFFSET = 11'h 4b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_59_OFFSET = 11'h 4b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_60_OFFSET = 11'h 4bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_61_OFFSET = 11'h 4c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_62_OFFSET = 11'h 4c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_63_OFFSET = 11'h 4c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_64_OFFSET = 11'h 4cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_65_OFFSET = 11'h 4d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_66_OFFSET = 11'h 4d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_67_OFFSET = 11'h 4d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_68_OFFSET = 11'h 4dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_69_OFFSET = 11'h 4e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_70_OFFSET = 11'h 4e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_71_OFFSET = 11'h 4e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_72_OFFSET = 11'h 4ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 11'h 4f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 11'h 4f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 11'h 4f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 11'h 4fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 11'h 504; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 11'h 508; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 11'h 50c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 11'h 510; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 11'h 514; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 11'h 518; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 11'h 51c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 11'h 520; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 11'h 524; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 11'h 528; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 11'h 52c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET = 11'h 530; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET = 11'h 534; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET = 11'h 538; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET = 11'h 53c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET = 11'h 540; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET = 11'h 544; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET = 11'h 548; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_23_OFFSET = 11'h 54c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_24_OFFSET = 11'h 550; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_25_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_26_OFFSET = 11'h 558; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_27_OFFSET = 11'h 55c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_28_OFFSET = 11'h 560; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_29_OFFSET = 11'h 564; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_30_OFFSET = 11'h 568; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_31_OFFSET = 11'h 56c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_32_OFFSET = 11'h 570; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_33_OFFSET = 11'h 574; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_34_OFFSET = 11'h 578; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_35_OFFSET = 11'h 57c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_36_OFFSET = 11'h 580; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_37_OFFSET = 11'h 584; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_38_OFFSET = 11'h 588; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_39_OFFSET = 11'h 58c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_40_OFFSET = 11'h 590; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_41_OFFSET = 11'h 594; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_42_OFFSET = 11'h 598; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_43_OFFSET = 11'h 59c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_44_OFFSET = 11'h 5a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_45_OFFSET = 11'h 5a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_46_OFFSET = 11'h 5a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_47_OFFSET = 11'h 5ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_48_OFFSET = 11'h 5b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_49_OFFSET = 11'h 5b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_50_OFFSET = 11'h 5b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_51_OFFSET = 11'h 5bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_52_OFFSET = 11'h 5c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_53_OFFSET = 11'h 5c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_54_OFFSET = 11'h 5c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_55_OFFSET = 11'h 5cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_56_OFFSET = 11'h 5d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_57_OFFSET = 11'h 5d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_58_OFFSET = 11'h 5d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_59_OFFSET = 11'h 5dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_60_OFFSET = 11'h 5e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_61_OFFSET = 11'h 5e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_62_OFFSET = 11'h 5e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_63_OFFSET = 11'h 5ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_64_OFFSET = 11'h 5f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_65_OFFSET = 11'h 5f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_66_OFFSET = 11'h 5f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_67_OFFSET = 11'h 5fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_68_OFFSET = 11'h 600; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_69_OFFSET = 11'h 604; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_70_OFFSET = 11'h 608; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_71_OFFSET = 11'h 60c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_72_OFFSET = 11'h 610; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 614; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 618; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 61c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 620; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 624; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 628; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 62c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 630; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 634; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 638; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 63c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 640; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 644; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 648; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 64c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 11'h 650; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET = 11'h 654; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET = 11'h 658; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET = 11'h 65c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET = 11'h 660; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET = 11'h 664; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET = 11'h 668; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET = 11'h 66c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_23_OFFSET = 11'h 670; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_24_OFFSET = 11'h 674; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_25_OFFSET = 11'h 678; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_26_OFFSET = 11'h 67c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_27_OFFSET = 11'h 680; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_28_OFFSET = 11'h 684; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_29_OFFSET = 11'h 688; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_30_OFFSET = 11'h 68c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_31_OFFSET = 11'h 690; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_32_OFFSET = 11'h 694; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_33_OFFSET = 11'h 698; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_34_OFFSET = 11'h 69c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_35_OFFSET = 11'h 6a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_36_OFFSET = 11'h 6a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_37_OFFSET = 11'h 6a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_38_OFFSET = 11'h 6ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_39_OFFSET = 11'h 6b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_40_OFFSET = 11'h 6b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_41_OFFSET = 11'h 6b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_42_OFFSET = 11'h 6bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_43_OFFSET = 11'h 6c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_44_OFFSET = 11'h 6c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_45_OFFSET = 11'h 6c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_46_OFFSET = 11'h 6cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_47_OFFSET = 11'h 6d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_48_OFFSET = 11'h 6d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_49_OFFSET = 11'h 6d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_50_OFFSET = 11'h 6dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_51_OFFSET = 11'h 6e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_52_OFFSET = 11'h 6e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_53_OFFSET = 11'h 6e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_54_OFFSET = 11'h 6ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_55_OFFSET = 11'h 6f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_56_OFFSET = 11'h 6f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_57_OFFSET = 11'h 6f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_58_OFFSET = 11'h 6fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_59_OFFSET = 11'h 700; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_60_OFFSET = 11'h 704; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_61_OFFSET = 11'h 708; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_62_OFFSET = 11'h 70c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_63_OFFSET = 11'h 710; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_64_OFFSET = 11'h 714; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_65_OFFSET = 11'h 718; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_66_OFFSET = 11'h 71c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_67_OFFSET = 11'h 720; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_68_OFFSET = 11'h 724; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_69_OFFSET = 11'h 728; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_70_OFFSET = 11'h 72c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_71_OFFSET = 11'h 730; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_72_OFFSET = 11'h 734; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 11'h 738; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 11'h 73c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 11'h 740; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 11'h 744; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 11'h 748; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 11'h 74c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 11'h 750; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 11'h 754; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 11'h 758; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 11'h 75c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 11'h 760; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 11'h 764; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 11'h 768; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 11'h 76c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 11'h 770; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 11'h 774; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 11'h 778; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 11'h 77c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 11'h 780; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 11'h 784; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 11'h 788; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 11'h 78c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 11'h 790; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 11'h 794; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 11'h 798; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 11'h 79c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 11'h 7a0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 11'h 7a4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 11'h 7a8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 11'h 7ac; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 11'h 7b0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 11'h 7b4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 11'h 7b8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 11'h 7bc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 11'h 7c0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 11'h 7c4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 11'h 7c8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 11'h 7cc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 11'h 7d0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 11'h 7d4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 11'h 7d8; + + // Reset values for hwext registers and their fields + parameter logic [0:0] PINMUX_ALERT_TEST_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_0_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_INVERT_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_PULL_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_KEEPER_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_SCHMITT_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_OD_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_INPUT_DISABLE_0_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_1_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_INVERT_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_PULL_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_PULL_SELECT_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_KEEPER_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_SCHMITT_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_OD_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_INPUT_DISABLE_1_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_2_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_INVERT_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_PULL_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_PULL_SELECT_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_KEEPER_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_SCHMITT_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_OD_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_INPUT_DISABLE_2_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_3_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_INVERT_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_PULL_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_PULL_SELECT_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_KEEPER_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_SCHMITT_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_OD_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_INPUT_DISABLE_3_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_4_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_INVERT_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_PULL_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_PULL_SELECT_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_KEEPER_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_SCHMITT_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_OD_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_INPUT_DISABLE_4_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_5_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_INVERT_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_PULL_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_PULL_SELECT_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_KEEPER_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_SCHMITT_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_OD_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_INPUT_DISABLE_5_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_6_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_INVERT_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_PULL_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_PULL_SELECT_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_KEEPER_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_SCHMITT_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_OD_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_INPUT_DISABLE_6_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_7_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_INVERT_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_PULL_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_PULL_SELECT_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_KEEPER_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_SCHMITT_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_OD_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_INPUT_DISABLE_7_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_8_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_INVERT_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_PULL_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_PULL_SELECT_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_KEEPER_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_SCHMITT_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_OD_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_INPUT_DISABLE_8_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_9_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_INVERT_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_PULL_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_PULL_SELECT_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_KEEPER_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_SCHMITT_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_OD_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_INPUT_DISABLE_9_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_10_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_INVERT_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_PULL_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_PULL_SELECT_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_KEEPER_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_SCHMITT_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_OD_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_INPUT_DISABLE_10_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_11_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_INVERT_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_PULL_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_PULL_SELECT_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_KEEPER_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_SCHMITT_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_OD_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_INPUT_DISABLE_11_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_0_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_INVERT_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_PULL_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_KEEPER_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_SCHMITT_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_OD_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_INPUT_DISABLE_0_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_1_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_INVERT_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_PULL_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_PULL_SELECT_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_KEEPER_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_SCHMITT_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_OD_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_INPUT_DISABLE_1_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_2_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_INVERT_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_PULL_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_PULL_SELECT_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_KEEPER_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_SCHMITT_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_OD_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_INPUT_DISABLE_2_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_3_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_INVERT_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_PULL_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_PULL_SELECT_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_KEEPER_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_SCHMITT_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_OD_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_INPUT_DISABLE_3_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_4_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_INVERT_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_PULL_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_PULL_SELECT_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_KEEPER_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_SCHMITT_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_OD_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_INPUT_DISABLE_4_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_5_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_INVERT_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_PULL_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_PULL_SELECT_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_KEEPER_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_SCHMITT_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_OD_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_INPUT_DISABLE_5_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_6_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_INVERT_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_PULL_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_PULL_SELECT_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_KEEPER_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_SCHMITT_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_OD_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_INPUT_DISABLE_6_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_7_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_INVERT_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_PULL_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_PULL_SELECT_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_KEEPER_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_SCHMITT_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_OD_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_INPUT_DISABLE_7_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_8_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_INVERT_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_PULL_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_PULL_SELECT_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_KEEPER_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_SCHMITT_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_OD_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_INPUT_DISABLE_8_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_9_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_INVERT_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_PULL_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_PULL_SELECT_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_KEEPER_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_SCHMITT_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_OD_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_INPUT_DISABLE_9_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_10_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_INVERT_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_PULL_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_PULL_SELECT_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_KEEPER_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_SCHMITT_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_OD_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_INPUT_DISABLE_10_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_11_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_INVERT_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_PULL_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_PULL_SELECT_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_KEEPER_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_SCHMITT_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_OD_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_INPUT_DISABLE_11_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_12_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_INVERT_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_VIRTUAL_OD_EN_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_PULL_EN_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_PULL_SELECT_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_KEEPER_EN_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_SCHMITT_EN_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_OD_EN_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_INPUT_DISABLE_12_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_13_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_INVERT_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_VIRTUAL_OD_EN_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_PULL_EN_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_PULL_SELECT_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_KEEPER_EN_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_SCHMITT_EN_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_OD_EN_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_INPUT_DISABLE_13_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_14_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_INVERT_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_VIRTUAL_OD_EN_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_PULL_EN_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_PULL_SELECT_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_KEEPER_EN_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_SCHMITT_EN_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_OD_EN_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_INPUT_DISABLE_14_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_15_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_INVERT_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_VIRTUAL_OD_EN_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_PULL_EN_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_PULL_SELECT_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_KEEPER_EN_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_SCHMITT_EN_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_OD_EN_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_INPUT_DISABLE_15_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_16_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_INVERT_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_VIRTUAL_OD_EN_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_PULL_EN_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_PULL_SELECT_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_KEEPER_EN_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_SCHMITT_EN_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_OD_EN_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_INPUT_DISABLE_16_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_17_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_INVERT_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_VIRTUAL_OD_EN_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_PULL_EN_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_PULL_SELECT_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_KEEPER_EN_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_SCHMITT_EN_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_OD_EN_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_INPUT_DISABLE_17_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_18_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_INVERT_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_VIRTUAL_OD_EN_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_PULL_EN_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_PULL_SELECT_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_KEEPER_EN_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_SCHMITT_EN_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_OD_EN_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_INPUT_DISABLE_18_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_19_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_INVERT_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_VIRTUAL_OD_EN_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_PULL_EN_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_PULL_SELECT_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_KEEPER_EN_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_SCHMITT_EN_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_OD_EN_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_INPUT_DISABLE_19_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_20_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_INVERT_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_VIRTUAL_OD_EN_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_PULL_EN_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_PULL_SELECT_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_KEEPER_EN_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_SCHMITT_EN_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_OD_EN_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_INPUT_DISABLE_20_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_21_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_INVERT_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_VIRTUAL_OD_EN_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_PULL_EN_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_PULL_SELECT_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_KEEPER_EN_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_SCHMITT_EN_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_OD_EN_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_INPUT_DISABLE_21_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_22_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_INVERT_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_VIRTUAL_OD_EN_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_PULL_EN_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_PULL_SELECT_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_KEEPER_EN_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_SCHMITT_EN_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_OD_EN_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_INPUT_DISABLE_22_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_23_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_INVERT_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_VIRTUAL_OD_EN_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_PULL_EN_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_PULL_SELECT_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_KEEPER_EN_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_SCHMITT_EN_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_OD_EN_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_INPUT_DISABLE_23_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_24_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_INVERT_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_VIRTUAL_OD_EN_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_PULL_EN_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_PULL_SELECT_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_KEEPER_EN_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_SCHMITT_EN_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_OD_EN_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_INPUT_DISABLE_24_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_25_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_INVERT_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_VIRTUAL_OD_EN_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_PULL_EN_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_PULL_SELECT_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_KEEPER_EN_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_SCHMITT_EN_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_OD_EN_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_INPUT_DISABLE_25_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_26_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_INVERT_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_VIRTUAL_OD_EN_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_PULL_EN_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_PULL_SELECT_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_KEEPER_EN_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_SCHMITT_EN_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_OD_EN_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_INPUT_DISABLE_26_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_27_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_INVERT_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_VIRTUAL_OD_EN_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_PULL_EN_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_PULL_SELECT_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_KEEPER_EN_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_SCHMITT_EN_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_OD_EN_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_INPUT_DISABLE_27_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_28_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_INVERT_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_VIRTUAL_OD_EN_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_PULL_EN_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_PULL_SELECT_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_KEEPER_EN_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_SCHMITT_EN_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_OD_EN_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_INPUT_DISABLE_28_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_29_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_INVERT_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_VIRTUAL_OD_EN_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_PULL_EN_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_PULL_SELECT_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_KEEPER_EN_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_SCHMITT_EN_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_OD_EN_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_INPUT_DISABLE_29_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_30_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_INVERT_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_VIRTUAL_OD_EN_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_PULL_EN_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_PULL_SELECT_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_KEEPER_EN_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_SCHMITT_EN_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_OD_EN_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_INPUT_DISABLE_30_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_31_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_INVERT_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_VIRTUAL_OD_EN_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_PULL_EN_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_PULL_SELECT_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_KEEPER_EN_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_SCHMITT_EN_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_OD_EN_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_INPUT_DISABLE_31_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_32_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_INVERT_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_VIRTUAL_OD_EN_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_PULL_EN_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_PULL_SELECT_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_KEEPER_EN_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_SCHMITT_EN_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_OD_EN_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_INPUT_DISABLE_32_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_33_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_INVERT_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_VIRTUAL_OD_EN_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_PULL_EN_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_PULL_SELECT_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_KEEPER_EN_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_SCHMITT_EN_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_OD_EN_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_INPUT_DISABLE_33_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_34_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_INVERT_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_VIRTUAL_OD_EN_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_PULL_EN_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_PULL_SELECT_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_KEEPER_EN_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_SCHMITT_EN_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_OD_EN_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_INPUT_DISABLE_34_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_35_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_INVERT_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_VIRTUAL_OD_EN_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_PULL_EN_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_PULL_SELECT_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_KEEPER_EN_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_SCHMITT_EN_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_OD_EN_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_INPUT_DISABLE_35_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_36_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_INVERT_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_VIRTUAL_OD_EN_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_PULL_EN_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_PULL_SELECT_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_KEEPER_EN_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_SCHMITT_EN_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_OD_EN_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_INPUT_DISABLE_36_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_37_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_INVERT_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_VIRTUAL_OD_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_PULL_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_PULL_SELECT_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_KEEPER_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_SCHMITT_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_OD_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_INPUT_DISABLE_37_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_38_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_INVERT_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_VIRTUAL_OD_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_PULL_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_PULL_SELECT_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_KEEPER_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_SCHMITT_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_OD_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_INPUT_DISABLE_38_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_39_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_INVERT_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_VIRTUAL_OD_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_PULL_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_PULL_SELECT_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_KEEPER_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_SCHMITT_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_OD_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_INPUT_DISABLE_39_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_40_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_INVERT_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_VIRTUAL_OD_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_PULL_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_PULL_SELECT_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_KEEPER_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_SCHMITT_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_OD_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_INPUT_DISABLE_40_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_41_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_INVERT_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_VIRTUAL_OD_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_PULL_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_PULL_SELECT_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_KEEPER_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_SCHMITT_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_OD_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_INPUT_DISABLE_41_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_42_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_INVERT_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_VIRTUAL_OD_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_PULL_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_PULL_SELECT_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_KEEPER_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_SCHMITT_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_OD_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_INPUT_DISABLE_42_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_43_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_INVERT_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_VIRTUAL_OD_EN_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_PULL_EN_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_PULL_SELECT_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_KEEPER_EN_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_SCHMITT_EN_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_OD_EN_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_INPUT_DISABLE_43_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_44_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_INVERT_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_VIRTUAL_OD_EN_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_PULL_EN_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_PULL_SELECT_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_KEEPER_EN_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_SCHMITT_EN_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_OD_EN_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_INPUT_DISABLE_44_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_45_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_INVERT_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_VIRTUAL_OD_EN_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_PULL_EN_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_PULL_SELECT_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_KEEPER_EN_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_SCHMITT_EN_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_OD_EN_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_INPUT_DISABLE_45_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_46_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_INVERT_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_VIRTUAL_OD_EN_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_PULL_EN_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_PULL_SELECT_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_KEEPER_EN_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_SCHMITT_EN_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_OD_EN_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_INPUT_DISABLE_46_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_47_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_INVERT_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_VIRTUAL_OD_EN_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_PULL_EN_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_PULL_SELECT_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_KEEPER_EN_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_SCHMITT_EN_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_OD_EN_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_INPUT_DISABLE_47_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_48_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_INVERT_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_VIRTUAL_OD_EN_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_PULL_EN_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_PULL_SELECT_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_KEEPER_EN_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_SCHMITT_EN_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_OD_EN_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_INPUT_DISABLE_48_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_49_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_INVERT_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_VIRTUAL_OD_EN_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_PULL_EN_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_PULL_SELECT_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_KEEPER_EN_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_SCHMITT_EN_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_OD_EN_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_INPUT_DISABLE_49_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_50_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_INVERT_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_VIRTUAL_OD_EN_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_PULL_EN_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_PULL_SELECT_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_KEEPER_EN_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_SCHMITT_EN_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_OD_EN_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_INPUT_DISABLE_50_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_51_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_INVERT_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_VIRTUAL_OD_EN_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_PULL_EN_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_PULL_SELECT_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_KEEPER_EN_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_SCHMITT_EN_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_OD_EN_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_INPUT_DISABLE_51_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_52_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_INVERT_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_VIRTUAL_OD_EN_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_PULL_EN_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_PULL_SELECT_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_KEEPER_EN_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_SCHMITT_EN_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_OD_EN_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_INPUT_DISABLE_52_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_53_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_INVERT_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_VIRTUAL_OD_EN_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_PULL_EN_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_PULL_SELECT_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_KEEPER_EN_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_SCHMITT_EN_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_OD_EN_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_INPUT_DISABLE_53_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_54_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_INVERT_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_VIRTUAL_OD_EN_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_PULL_EN_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_PULL_SELECT_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_KEEPER_EN_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_SCHMITT_EN_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_OD_EN_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_INPUT_DISABLE_54_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_55_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_INVERT_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_VIRTUAL_OD_EN_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_PULL_EN_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_PULL_SELECT_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_KEEPER_EN_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_SCHMITT_EN_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_OD_EN_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_INPUT_DISABLE_55_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_56_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_INVERT_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_VIRTUAL_OD_EN_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_PULL_EN_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_PULL_SELECT_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_KEEPER_EN_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_SCHMITT_EN_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_OD_EN_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_INPUT_DISABLE_56_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_57_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_INVERT_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_VIRTUAL_OD_EN_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_PULL_EN_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_PULL_SELECT_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_KEEPER_EN_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_SCHMITT_EN_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_OD_EN_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_INPUT_DISABLE_57_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_58_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_INVERT_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_VIRTUAL_OD_EN_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_PULL_EN_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_PULL_SELECT_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_KEEPER_EN_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_SCHMITT_EN_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_OD_EN_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_INPUT_DISABLE_58_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_59_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_INVERT_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_VIRTUAL_OD_EN_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_PULL_EN_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_PULL_SELECT_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_KEEPER_EN_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_SCHMITT_EN_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_OD_EN_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_INPUT_DISABLE_59_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_60_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_INVERT_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_VIRTUAL_OD_EN_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_PULL_EN_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_PULL_SELECT_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_KEEPER_EN_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_SCHMITT_EN_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_OD_EN_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_INPUT_DISABLE_60_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_61_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_INVERT_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_VIRTUAL_OD_EN_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_PULL_EN_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_PULL_SELECT_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_KEEPER_EN_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_SCHMITT_EN_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_OD_EN_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_INPUT_DISABLE_61_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_62_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_INVERT_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_VIRTUAL_OD_EN_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_PULL_EN_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_PULL_SELECT_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_KEEPER_EN_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_SCHMITT_EN_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_OD_EN_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_INPUT_DISABLE_62_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_63_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_INVERT_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_VIRTUAL_OD_EN_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_PULL_EN_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_PULL_SELECT_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_KEEPER_EN_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_SCHMITT_EN_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_OD_EN_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_INPUT_DISABLE_63_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_64_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_INVERT_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_VIRTUAL_OD_EN_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_PULL_EN_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_PULL_SELECT_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_KEEPER_EN_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_SCHMITT_EN_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_OD_EN_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_INPUT_DISABLE_64_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_65_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_INVERT_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_VIRTUAL_OD_EN_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_PULL_EN_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_PULL_SELECT_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_KEEPER_EN_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_SCHMITT_EN_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_OD_EN_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_INPUT_DISABLE_65_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_66_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_INVERT_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_VIRTUAL_OD_EN_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_PULL_EN_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_PULL_SELECT_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_KEEPER_EN_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_SCHMITT_EN_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_OD_EN_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_INPUT_DISABLE_66_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_67_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_INVERT_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_VIRTUAL_OD_EN_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_PULL_EN_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_PULL_SELECT_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_KEEPER_EN_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_SCHMITT_EN_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_OD_EN_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_INPUT_DISABLE_67_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_68_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_INVERT_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_VIRTUAL_OD_EN_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_PULL_EN_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_PULL_SELECT_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_KEEPER_EN_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_SCHMITT_EN_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_OD_EN_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_INPUT_DISABLE_68_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_69_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_INVERT_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_VIRTUAL_OD_EN_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_PULL_EN_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_PULL_SELECT_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_KEEPER_EN_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_SCHMITT_EN_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_OD_EN_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_INPUT_DISABLE_69_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_70_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_INVERT_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_VIRTUAL_OD_EN_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_PULL_EN_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_PULL_SELECT_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_KEEPER_EN_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_SCHMITT_EN_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_OD_EN_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_INPUT_DISABLE_70_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_71_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_INVERT_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_VIRTUAL_OD_EN_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_PULL_EN_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_PULL_SELECT_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_KEEPER_EN_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_SCHMITT_EN_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_OD_EN_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_INPUT_DISABLE_71_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_72_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_INVERT_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_VIRTUAL_OD_EN_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_PULL_EN_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_PULL_SELECT_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_KEEPER_EN_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_SCHMITT_EN_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_OD_EN_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_INPUT_DISABLE_72_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_RESVAL = 4'h 0; + + // Register index + typedef enum int { + PINMUX_ALERT_TEST, + PINMUX_MIO_PERIPH_INSEL_REGWEN_0, + PINMUX_MIO_PERIPH_INSEL_REGWEN_1, + PINMUX_MIO_PERIPH_INSEL_REGWEN_2, + PINMUX_MIO_PERIPH_INSEL_REGWEN_3, + PINMUX_MIO_PERIPH_INSEL_0, + PINMUX_MIO_PERIPH_INSEL_1, + PINMUX_MIO_PERIPH_INSEL_2, + PINMUX_MIO_PERIPH_INSEL_3, + PINMUX_MIO_OUTSEL_REGWEN_0, + PINMUX_MIO_OUTSEL_REGWEN_1, + PINMUX_MIO_OUTSEL_REGWEN_2, + PINMUX_MIO_OUTSEL_REGWEN_3, + PINMUX_MIO_OUTSEL_REGWEN_4, + PINMUX_MIO_OUTSEL_REGWEN_5, + PINMUX_MIO_OUTSEL_REGWEN_6, + PINMUX_MIO_OUTSEL_REGWEN_7, + PINMUX_MIO_OUTSEL_REGWEN_8, + PINMUX_MIO_OUTSEL_REGWEN_9, + PINMUX_MIO_OUTSEL_REGWEN_10, + PINMUX_MIO_OUTSEL_REGWEN_11, + PINMUX_MIO_OUTSEL_0, + PINMUX_MIO_OUTSEL_1, + PINMUX_MIO_OUTSEL_2, + PINMUX_MIO_OUTSEL_3, + PINMUX_MIO_OUTSEL_4, + PINMUX_MIO_OUTSEL_5, + PINMUX_MIO_OUTSEL_6, + PINMUX_MIO_OUTSEL_7, + PINMUX_MIO_OUTSEL_8, + PINMUX_MIO_OUTSEL_9, + PINMUX_MIO_OUTSEL_10, + PINMUX_MIO_OUTSEL_11, + PINMUX_MIO_PAD_ATTR_REGWEN_0, + PINMUX_MIO_PAD_ATTR_REGWEN_1, + PINMUX_MIO_PAD_ATTR_REGWEN_2, + PINMUX_MIO_PAD_ATTR_REGWEN_3, + PINMUX_MIO_PAD_ATTR_REGWEN_4, + PINMUX_MIO_PAD_ATTR_REGWEN_5, + PINMUX_MIO_PAD_ATTR_REGWEN_6, + PINMUX_MIO_PAD_ATTR_REGWEN_7, + PINMUX_MIO_PAD_ATTR_REGWEN_8, + PINMUX_MIO_PAD_ATTR_REGWEN_9, + PINMUX_MIO_PAD_ATTR_REGWEN_10, + PINMUX_MIO_PAD_ATTR_REGWEN_11, + PINMUX_MIO_PAD_ATTR_0, + PINMUX_MIO_PAD_ATTR_1, + PINMUX_MIO_PAD_ATTR_2, + PINMUX_MIO_PAD_ATTR_3, + PINMUX_MIO_PAD_ATTR_4, + PINMUX_MIO_PAD_ATTR_5, + PINMUX_MIO_PAD_ATTR_6, + PINMUX_MIO_PAD_ATTR_7, + PINMUX_MIO_PAD_ATTR_8, + PINMUX_MIO_PAD_ATTR_9, + PINMUX_MIO_PAD_ATTR_10, + PINMUX_MIO_PAD_ATTR_11, + PINMUX_DIO_PAD_ATTR_REGWEN_0, + PINMUX_DIO_PAD_ATTR_REGWEN_1, + PINMUX_DIO_PAD_ATTR_REGWEN_2, + PINMUX_DIO_PAD_ATTR_REGWEN_3, + PINMUX_DIO_PAD_ATTR_REGWEN_4, + PINMUX_DIO_PAD_ATTR_REGWEN_5, + PINMUX_DIO_PAD_ATTR_REGWEN_6, + PINMUX_DIO_PAD_ATTR_REGWEN_7, + PINMUX_DIO_PAD_ATTR_REGWEN_8, + PINMUX_DIO_PAD_ATTR_REGWEN_9, + PINMUX_DIO_PAD_ATTR_REGWEN_10, + PINMUX_DIO_PAD_ATTR_REGWEN_11, + PINMUX_DIO_PAD_ATTR_REGWEN_12, + PINMUX_DIO_PAD_ATTR_REGWEN_13, + PINMUX_DIO_PAD_ATTR_REGWEN_14, + PINMUX_DIO_PAD_ATTR_REGWEN_15, + PINMUX_DIO_PAD_ATTR_REGWEN_16, + PINMUX_DIO_PAD_ATTR_REGWEN_17, + PINMUX_DIO_PAD_ATTR_REGWEN_18, + PINMUX_DIO_PAD_ATTR_REGWEN_19, + PINMUX_DIO_PAD_ATTR_REGWEN_20, + PINMUX_DIO_PAD_ATTR_REGWEN_21, + PINMUX_DIO_PAD_ATTR_REGWEN_22, + PINMUX_DIO_PAD_ATTR_REGWEN_23, + PINMUX_DIO_PAD_ATTR_REGWEN_24, + PINMUX_DIO_PAD_ATTR_REGWEN_25, + PINMUX_DIO_PAD_ATTR_REGWEN_26, + PINMUX_DIO_PAD_ATTR_REGWEN_27, + PINMUX_DIO_PAD_ATTR_REGWEN_28, + PINMUX_DIO_PAD_ATTR_REGWEN_29, + PINMUX_DIO_PAD_ATTR_REGWEN_30, + PINMUX_DIO_PAD_ATTR_REGWEN_31, + PINMUX_DIO_PAD_ATTR_REGWEN_32, + PINMUX_DIO_PAD_ATTR_REGWEN_33, + PINMUX_DIO_PAD_ATTR_REGWEN_34, + PINMUX_DIO_PAD_ATTR_REGWEN_35, + PINMUX_DIO_PAD_ATTR_REGWEN_36, + PINMUX_DIO_PAD_ATTR_REGWEN_37, + PINMUX_DIO_PAD_ATTR_REGWEN_38, + PINMUX_DIO_PAD_ATTR_REGWEN_39, + PINMUX_DIO_PAD_ATTR_REGWEN_40, + PINMUX_DIO_PAD_ATTR_REGWEN_41, + PINMUX_DIO_PAD_ATTR_REGWEN_42, + PINMUX_DIO_PAD_ATTR_REGWEN_43, + PINMUX_DIO_PAD_ATTR_REGWEN_44, + PINMUX_DIO_PAD_ATTR_REGWEN_45, + PINMUX_DIO_PAD_ATTR_REGWEN_46, + PINMUX_DIO_PAD_ATTR_REGWEN_47, + PINMUX_DIO_PAD_ATTR_REGWEN_48, + PINMUX_DIO_PAD_ATTR_REGWEN_49, + PINMUX_DIO_PAD_ATTR_REGWEN_50, + PINMUX_DIO_PAD_ATTR_REGWEN_51, + PINMUX_DIO_PAD_ATTR_REGWEN_52, + PINMUX_DIO_PAD_ATTR_REGWEN_53, + PINMUX_DIO_PAD_ATTR_REGWEN_54, + PINMUX_DIO_PAD_ATTR_REGWEN_55, + PINMUX_DIO_PAD_ATTR_REGWEN_56, + PINMUX_DIO_PAD_ATTR_REGWEN_57, + PINMUX_DIO_PAD_ATTR_REGWEN_58, + PINMUX_DIO_PAD_ATTR_REGWEN_59, + PINMUX_DIO_PAD_ATTR_REGWEN_60, + PINMUX_DIO_PAD_ATTR_REGWEN_61, + PINMUX_DIO_PAD_ATTR_REGWEN_62, + PINMUX_DIO_PAD_ATTR_REGWEN_63, + PINMUX_DIO_PAD_ATTR_REGWEN_64, + PINMUX_DIO_PAD_ATTR_REGWEN_65, + PINMUX_DIO_PAD_ATTR_REGWEN_66, + PINMUX_DIO_PAD_ATTR_REGWEN_67, + PINMUX_DIO_PAD_ATTR_REGWEN_68, + PINMUX_DIO_PAD_ATTR_REGWEN_69, + PINMUX_DIO_PAD_ATTR_REGWEN_70, + PINMUX_DIO_PAD_ATTR_REGWEN_71, + PINMUX_DIO_PAD_ATTR_REGWEN_72, + PINMUX_DIO_PAD_ATTR_0, + PINMUX_DIO_PAD_ATTR_1, + PINMUX_DIO_PAD_ATTR_2, + PINMUX_DIO_PAD_ATTR_3, + PINMUX_DIO_PAD_ATTR_4, + PINMUX_DIO_PAD_ATTR_5, + PINMUX_DIO_PAD_ATTR_6, + PINMUX_DIO_PAD_ATTR_7, + PINMUX_DIO_PAD_ATTR_8, + PINMUX_DIO_PAD_ATTR_9, + PINMUX_DIO_PAD_ATTR_10, + PINMUX_DIO_PAD_ATTR_11, + PINMUX_DIO_PAD_ATTR_12, + PINMUX_DIO_PAD_ATTR_13, + PINMUX_DIO_PAD_ATTR_14, + PINMUX_DIO_PAD_ATTR_15, + PINMUX_DIO_PAD_ATTR_16, + PINMUX_DIO_PAD_ATTR_17, + PINMUX_DIO_PAD_ATTR_18, + PINMUX_DIO_PAD_ATTR_19, + PINMUX_DIO_PAD_ATTR_20, + PINMUX_DIO_PAD_ATTR_21, + PINMUX_DIO_PAD_ATTR_22, + PINMUX_DIO_PAD_ATTR_23, + PINMUX_DIO_PAD_ATTR_24, + PINMUX_DIO_PAD_ATTR_25, + PINMUX_DIO_PAD_ATTR_26, + PINMUX_DIO_PAD_ATTR_27, + PINMUX_DIO_PAD_ATTR_28, + PINMUX_DIO_PAD_ATTR_29, + PINMUX_DIO_PAD_ATTR_30, + PINMUX_DIO_PAD_ATTR_31, + PINMUX_DIO_PAD_ATTR_32, + PINMUX_DIO_PAD_ATTR_33, + PINMUX_DIO_PAD_ATTR_34, + PINMUX_DIO_PAD_ATTR_35, + PINMUX_DIO_PAD_ATTR_36, + PINMUX_DIO_PAD_ATTR_37, + PINMUX_DIO_PAD_ATTR_38, + PINMUX_DIO_PAD_ATTR_39, + PINMUX_DIO_PAD_ATTR_40, + PINMUX_DIO_PAD_ATTR_41, + PINMUX_DIO_PAD_ATTR_42, + PINMUX_DIO_PAD_ATTR_43, + PINMUX_DIO_PAD_ATTR_44, + PINMUX_DIO_PAD_ATTR_45, + PINMUX_DIO_PAD_ATTR_46, + PINMUX_DIO_PAD_ATTR_47, + PINMUX_DIO_PAD_ATTR_48, + PINMUX_DIO_PAD_ATTR_49, + PINMUX_DIO_PAD_ATTR_50, + PINMUX_DIO_PAD_ATTR_51, + PINMUX_DIO_PAD_ATTR_52, + PINMUX_DIO_PAD_ATTR_53, + PINMUX_DIO_PAD_ATTR_54, + PINMUX_DIO_PAD_ATTR_55, + PINMUX_DIO_PAD_ATTR_56, + PINMUX_DIO_PAD_ATTR_57, + PINMUX_DIO_PAD_ATTR_58, + PINMUX_DIO_PAD_ATTR_59, + PINMUX_DIO_PAD_ATTR_60, + PINMUX_DIO_PAD_ATTR_61, + PINMUX_DIO_PAD_ATTR_62, + PINMUX_DIO_PAD_ATTR_63, + PINMUX_DIO_PAD_ATTR_64, + PINMUX_DIO_PAD_ATTR_65, + PINMUX_DIO_PAD_ATTR_66, + PINMUX_DIO_PAD_ATTR_67, + PINMUX_DIO_PAD_ATTR_68, + PINMUX_DIO_PAD_ATTR_69, + PINMUX_DIO_PAD_ATTR_70, + PINMUX_DIO_PAD_ATTR_71, + PINMUX_DIO_PAD_ATTR_72, + PINMUX_MIO_PAD_SLEEP_STATUS, + PINMUX_MIO_PAD_SLEEP_REGWEN_0, + PINMUX_MIO_PAD_SLEEP_REGWEN_1, + PINMUX_MIO_PAD_SLEEP_REGWEN_2, + PINMUX_MIO_PAD_SLEEP_REGWEN_3, + PINMUX_MIO_PAD_SLEEP_REGWEN_4, + PINMUX_MIO_PAD_SLEEP_REGWEN_5, + PINMUX_MIO_PAD_SLEEP_REGWEN_6, + PINMUX_MIO_PAD_SLEEP_REGWEN_7, + PINMUX_MIO_PAD_SLEEP_REGWEN_8, + PINMUX_MIO_PAD_SLEEP_REGWEN_9, + PINMUX_MIO_PAD_SLEEP_REGWEN_10, + PINMUX_MIO_PAD_SLEEP_REGWEN_11, + PINMUX_MIO_PAD_SLEEP_EN_0, + PINMUX_MIO_PAD_SLEEP_EN_1, + PINMUX_MIO_PAD_SLEEP_EN_2, + PINMUX_MIO_PAD_SLEEP_EN_3, + PINMUX_MIO_PAD_SLEEP_EN_4, + PINMUX_MIO_PAD_SLEEP_EN_5, + PINMUX_MIO_PAD_SLEEP_EN_6, + PINMUX_MIO_PAD_SLEEP_EN_7, + PINMUX_MIO_PAD_SLEEP_EN_8, + PINMUX_MIO_PAD_SLEEP_EN_9, + PINMUX_MIO_PAD_SLEEP_EN_10, + PINMUX_MIO_PAD_SLEEP_EN_11, + PINMUX_MIO_PAD_SLEEP_MODE_0, + PINMUX_MIO_PAD_SLEEP_MODE_1, + PINMUX_MIO_PAD_SLEEP_MODE_2, + PINMUX_MIO_PAD_SLEEP_MODE_3, + PINMUX_MIO_PAD_SLEEP_MODE_4, + PINMUX_MIO_PAD_SLEEP_MODE_5, + PINMUX_MIO_PAD_SLEEP_MODE_6, + PINMUX_MIO_PAD_SLEEP_MODE_7, + PINMUX_MIO_PAD_SLEEP_MODE_8, + PINMUX_MIO_PAD_SLEEP_MODE_9, + PINMUX_MIO_PAD_SLEEP_MODE_10, + PINMUX_MIO_PAD_SLEEP_MODE_11, + PINMUX_DIO_PAD_SLEEP_STATUS_0, + PINMUX_DIO_PAD_SLEEP_STATUS_1, + PINMUX_DIO_PAD_SLEEP_STATUS_2, + PINMUX_DIO_PAD_SLEEP_REGWEN_0, + PINMUX_DIO_PAD_SLEEP_REGWEN_1, + PINMUX_DIO_PAD_SLEEP_REGWEN_2, + PINMUX_DIO_PAD_SLEEP_REGWEN_3, + PINMUX_DIO_PAD_SLEEP_REGWEN_4, + PINMUX_DIO_PAD_SLEEP_REGWEN_5, + PINMUX_DIO_PAD_SLEEP_REGWEN_6, + PINMUX_DIO_PAD_SLEEP_REGWEN_7, + PINMUX_DIO_PAD_SLEEP_REGWEN_8, + PINMUX_DIO_PAD_SLEEP_REGWEN_9, + PINMUX_DIO_PAD_SLEEP_REGWEN_10, + PINMUX_DIO_PAD_SLEEP_REGWEN_11, + PINMUX_DIO_PAD_SLEEP_REGWEN_12, + PINMUX_DIO_PAD_SLEEP_REGWEN_13, + PINMUX_DIO_PAD_SLEEP_REGWEN_14, + PINMUX_DIO_PAD_SLEEP_REGWEN_15, + PINMUX_DIO_PAD_SLEEP_REGWEN_16, + PINMUX_DIO_PAD_SLEEP_REGWEN_17, + PINMUX_DIO_PAD_SLEEP_REGWEN_18, + PINMUX_DIO_PAD_SLEEP_REGWEN_19, + PINMUX_DIO_PAD_SLEEP_REGWEN_20, + PINMUX_DIO_PAD_SLEEP_REGWEN_21, + PINMUX_DIO_PAD_SLEEP_REGWEN_22, + PINMUX_DIO_PAD_SLEEP_REGWEN_23, + PINMUX_DIO_PAD_SLEEP_REGWEN_24, + PINMUX_DIO_PAD_SLEEP_REGWEN_25, + PINMUX_DIO_PAD_SLEEP_REGWEN_26, + PINMUX_DIO_PAD_SLEEP_REGWEN_27, + PINMUX_DIO_PAD_SLEEP_REGWEN_28, + PINMUX_DIO_PAD_SLEEP_REGWEN_29, + PINMUX_DIO_PAD_SLEEP_REGWEN_30, + PINMUX_DIO_PAD_SLEEP_REGWEN_31, + PINMUX_DIO_PAD_SLEEP_REGWEN_32, + PINMUX_DIO_PAD_SLEEP_REGWEN_33, + PINMUX_DIO_PAD_SLEEP_REGWEN_34, + PINMUX_DIO_PAD_SLEEP_REGWEN_35, + PINMUX_DIO_PAD_SLEEP_REGWEN_36, + PINMUX_DIO_PAD_SLEEP_REGWEN_37, + PINMUX_DIO_PAD_SLEEP_REGWEN_38, + PINMUX_DIO_PAD_SLEEP_REGWEN_39, + PINMUX_DIO_PAD_SLEEP_REGWEN_40, + PINMUX_DIO_PAD_SLEEP_REGWEN_41, + PINMUX_DIO_PAD_SLEEP_REGWEN_42, + PINMUX_DIO_PAD_SLEEP_REGWEN_43, + PINMUX_DIO_PAD_SLEEP_REGWEN_44, + PINMUX_DIO_PAD_SLEEP_REGWEN_45, + PINMUX_DIO_PAD_SLEEP_REGWEN_46, + PINMUX_DIO_PAD_SLEEP_REGWEN_47, + PINMUX_DIO_PAD_SLEEP_REGWEN_48, + PINMUX_DIO_PAD_SLEEP_REGWEN_49, + PINMUX_DIO_PAD_SLEEP_REGWEN_50, + PINMUX_DIO_PAD_SLEEP_REGWEN_51, + PINMUX_DIO_PAD_SLEEP_REGWEN_52, + PINMUX_DIO_PAD_SLEEP_REGWEN_53, + PINMUX_DIO_PAD_SLEEP_REGWEN_54, + PINMUX_DIO_PAD_SLEEP_REGWEN_55, + PINMUX_DIO_PAD_SLEEP_REGWEN_56, + PINMUX_DIO_PAD_SLEEP_REGWEN_57, + PINMUX_DIO_PAD_SLEEP_REGWEN_58, + PINMUX_DIO_PAD_SLEEP_REGWEN_59, + PINMUX_DIO_PAD_SLEEP_REGWEN_60, + PINMUX_DIO_PAD_SLEEP_REGWEN_61, + PINMUX_DIO_PAD_SLEEP_REGWEN_62, + PINMUX_DIO_PAD_SLEEP_REGWEN_63, + PINMUX_DIO_PAD_SLEEP_REGWEN_64, + PINMUX_DIO_PAD_SLEEP_REGWEN_65, + PINMUX_DIO_PAD_SLEEP_REGWEN_66, + PINMUX_DIO_PAD_SLEEP_REGWEN_67, + PINMUX_DIO_PAD_SLEEP_REGWEN_68, + PINMUX_DIO_PAD_SLEEP_REGWEN_69, + PINMUX_DIO_PAD_SLEEP_REGWEN_70, + PINMUX_DIO_PAD_SLEEP_REGWEN_71, + PINMUX_DIO_PAD_SLEEP_REGWEN_72, + PINMUX_DIO_PAD_SLEEP_EN_0, + PINMUX_DIO_PAD_SLEEP_EN_1, + PINMUX_DIO_PAD_SLEEP_EN_2, + PINMUX_DIO_PAD_SLEEP_EN_3, + PINMUX_DIO_PAD_SLEEP_EN_4, + PINMUX_DIO_PAD_SLEEP_EN_5, + PINMUX_DIO_PAD_SLEEP_EN_6, + PINMUX_DIO_PAD_SLEEP_EN_7, + PINMUX_DIO_PAD_SLEEP_EN_8, + PINMUX_DIO_PAD_SLEEP_EN_9, + PINMUX_DIO_PAD_SLEEP_EN_10, + PINMUX_DIO_PAD_SLEEP_EN_11, + PINMUX_DIO_PAD_SLEEP_EN_12, + PINMUX_DIO_PAD_SLEEP_EN_13, + PINMUX_DIO_PAD_SLEEP_EN_14, + PINMUX_DIO_PAD_SLEEP_EN_15, + PINMUX_DIO_PAD_SLEEP_EN_16, + PINMUX_DIO_PAD_SLEEP_EN_17, + PINMUX_DIO_PAD_SLEEP_EN_18, + PINMUX_DIO_PAD_SLEEP_EN_19, + PINMUX_DIO_PAD_SLEEP_EN_20, + PINMUX_DIO_PAD_SLEEP_EN_21, + PINMUX_DIO_PAD_SLEEP_EN_22, + PINMUX_DIO_PAD_SLEEP_EN_23, + PINMUX_DIO_PAD_SLEEP_EN_24, + PINMUX_DIO_PAD_SLEEP_EN_25, + PINMUX_DIO_PAD_SLEEP_EN_26, + PINMUX_DIO_PAD_SLEEP_EN_27, + PINMUX_DIO_PAD_SLEEP_EN_28, + PINMUX_DIO_PAD_SLEEP_EN_29, + PINMUX_DIO_PAD_SLEEP_EN_30, + PINMUX_DIO_PAD_SLEEP_EN_31, + PINMUX_DIO_PAD_SLEEP_EN_32, + PINMUX_DIO_PAD_SLEEP_EN_33, + PINMUX_DIO_PAD_SLEEP_EN_34, + PINMUX_DIO_PAD_SLEEP_EN_35, + PINMUX_DIO_PAD_SLEEP_EN_36, + PINMUX_DIO_PAD_SLEEP_EN_37, + PINMUX_DIO_PAD_SLEEP_EN_38, + PINMUX_DIO_PAD_SLEEP_EN_39, + PINMUX_DIO_PAD_SLEEP_EN_40, + PINMUX_DIO_PAD_SLEEP_EN_41, + PINMUX_DIO_PAD_SLEEP_EN_42, + PINMUX_DIO_PAD_SLEEP_EN_43, + PINMUX_DIO_PAD_SLEEP_EN_44, + PINMUX_DIO_PAD_SLEEP_EN_45, + PINMUX_DIO_PAD_SLEEP_EN_46, + PINMUX_DIO_PAD_SLEEP_EN_47, + PINMUX_DIO_PAD_SLEEP_EN_48, + PINMUX_DIO_PAD_SLEEP_EN_49, + PINMUX_DIO_PAD_SLEEP_EN_50, + PINMUX_DIO_PAD_SLEEP_EN_51, + PINMUX_DIO_PAD_SLEEP_EN_52, + PINMUX_DIO_PAD_SLEEP_EN_53, + PINMUX_DIO_PAD_SLEEP_EN_54, + PINMUX_DIO_PAD_SLEEP_EN_55, + PINMUX_DIO_PAD_SLEEP_EN_56, + PINMUX_DIO_PAD_SLEEP_EN_57, + PINMUX_DIO_PAD_SLEEP_EN_58, + PINMUX_DIO_PAD_SLEEP_EN_59, + PINMUX_DIO_PAD_SLEEP_EN_60, + PINMUX_DIO_PAD_SLEEP_EN_61, + PINMUX_DIO_PAD_SLEEP_EN_62, + PINMUX_DIO_PAD_SLEEP_EN_63, + PINMUX_DIO_PAD_SLEEP_EN_64, + PINMUX_DIO_PAD_SLEEP_EN_65, + PINMUX_DIO_PAD_SLEEP_EN_66, + PINMUX_DIO_PAD_SLEEP_EN_67, + PINMUX_DIO_PAD_SLEEP_EN_68, + PINMUX_DIO_PAD_SLEEP_EN_69, + PINMUX_DIO_PAD_SLEEP_EN_70, + PINMUX_DIO_PAD_SLEEP_EN_71, + PINMUX_DIO_PAD_SLEEP_EN_72, + PINMUX_DIO_PAD_SLEEP_MODE_0, + PINMUX_DIO_PAD_SLEEP_MODE_1, + PINMUX_DIO_PAD_SLEEP_MODE_2, + PINMUX_DIO_PAD_SLEEP_MODE_3, + PINMUX_DIO_PAD_SLEEP_MODE_4, + PINMUX_DIO_PAD_SLEEP_MODE_5, + PINMUX_DIO_PAD_SLEEP_MODE_6, + PINMUX_DIO_PAD_SLEEP_MODE_7, + PINMUX_DIO_PAD_SLEEP_MODE_8, + PINMUX_DIO_PAD_SLEEP_MODE_9, + PINMUX_DIO_PAD_SLEEP_MODE_10, + PINMUX_DIO_PAD_SLEEP_MODE_11, + PINMUX_DIO_PAD_SLEEP_MODE_12, + PINMUX_DIO_PAD_SLEEP_MODE_13, + PINMUX_DIO_PAD_SLEEP_MODE_14, + PINMUX_DIO_PAD_SLEEP_MODE_15, + PINMUX_DIO_PAD_SLEEP_MODE_16, + PINMUX_DIO_PAD_SLEEP_MODE_17, + PINMUX_DIO_PAD_SLEEP_MODE_18, + PINMUX_DIO_PAD_SLEEP_MODE_19, + PINMUX_DIO_PAD_SLEEP_MODE_20, + PINMUX_DIO_PAD_SLEEP_MODE_21, + PINMUX_DIO_PAD_SLEEP_MODE_22, + PINMUX_DIO_PAD_SLEEP_MODE_23, + PINMUX_DIO_PAD_SLEEP_MODE_24, + PINMUX_DIO_PAD_SLEEP_MODE_25, + PINMUX_DIO_PAD_SLEEP_MODE_26, + PINMUX_DIO_PAD_SLEEP_MODE_27, + PINMUX_DIO_PAD_SLEEP_MODE_28, + PINMUX_DIO_PAD_SLEEP_MODE_29, + PINMUX_DIO_PAD_SLEEP_MODE_30, + PINMUX_DIO_PAD_SLEEP_MODE_31, + PINMUX_DIO_PAD_SLEEP_MODE_32, + PINMUX_DIO_PAD_SLEEP_MODE_33, + PINMUX_DIO_PAD_SLEEP_MODE_34, + PINMUX_DIO_PAD_SLEEP_MODE_35, + PINMUX_DIO_PAD_SLEEP_MODE_36, + PINMUX_DIO_PAD_SLEEP_MODE_37, + PINMUX_DIO_PAD_SLEEP_MODE_38, + PINMUX_DIO_PAD_SLEEP_MODE_39, + PINMUX_DIO_PAD_SLEEP_MODE_40, + PINMUX_DIO_PAD_SLEEP_MODE_41, + PINMUX_DIO_PAD_SLEEP_MODE_42, + PINMUX_DIO_PAD_SLEEP_MODE_43, + PINMUX_DIO_PAD_SLEEP_MODE_44, + PINMUX_DIO_PAD_SLEEP_MODE_45, + PINMUX_DIO_PAD_SLEEP_MODE_46, + PINMUX_DIO_PAD_SLEEP_MODE_47, + PINMUX_DIO_PAD_SLEEP_MODE_48, + PINMUX_DIO_PAD_SLEEP_MODE_49, + PINMUX_DIO_PAD_SLEEP_MODE_50, + PINMUX_DIO_PAD_SLEEP_MODE_51, + PINMUX_DIO_PAD_SLEEP_MODE_52, + PINMUX_DIO_PAD_SLEEP_MODE_53, + PINMUX_DIO_PAD_SLEEP_MODE_54, + PINMUX_DIO_PAD_SLEEP_MODE_55, + PINMUX_DIO_PAD_SLEEP_MODE_56, + PINMUX_DIO_PAD_SLEEP_MODE_57, + PINMUX_DIO_PAD_SLEEP_MODE_58, + PINMUX_DIO_PAD_SLEEP_MODE_59, + PINMUX_DIO_PAD_SLEEP_MODE_60, + PINMUX_DIO_PAD_SLEEP_MODE_61, + PINMUX_DIO_PAD_SLEEP_MODE_62, + PINMUX_DIO_PAD_SLEEP_MODE_63, + PINMUX_DIO_PAD_SLEEP_MODE_64, + PINMUX_DIO_PAD_SLEEP_MODE_65, + PINMUX_DIO_PAD_SLEEP_MODE_66, + PINMUX_DIO_PAD_SLEEP_MODE_67, + PINMUX_DIO_PAD_SLEEP_MODE_68, + PINMUX_DIO_PAD_SLEEP_MODE_69, + PINMUX_DIO_PAD_SLEEP_MODE_70, + PINMUX_DIO_PAD_SLEEP_MODE_71, + PINMUX_DIO_PAD_SLEEP_MODE_72, + PINMUX_WKUP_DETECTOR_REGWEN_0, + PINMUX_WKUP_DETECTOR_REGWEN_1, + PINMUX_WKUP_DETECTOR_REGWEN_2, + PINMUX_WKUP_DETECTOR_REGWEN_3, + PINMUX_WKUP_DETECTOR_REGWEN_4, + PINMUX_WKUP_DETECTOR_REGWEN_5, + PINMUX_WKUP_DETECTOR_REGWEN_6, + PINMUX_WKUP_DETECTOR_REGWEN_7, + PINMUX_WKUP_DETECTOR_EN_0, + PINMUX_WKUP_DETECTOR_EN_1, + PINMUX_WKUP_DETECTOR_EN_2, + PINMUX_WKUP_DETECTOR_EN_3, + PINMUX_WKUP_DETECTOR_EN_4, + PINMUX_WKUP_DETECTOR_EN_5, + PINMUX_WKUP_DETECTOR_EN_6, + PINMUX_WKUP_DETECTOR_EN_7, + PINMUX_WKUP_DETECTOR_0, + PINMUX_WKUP_DETECTOR_1, + PINMUX_WKUP_DETECTOR_2, + PINMUX_WKUP_DETECTOR_3, + PINMUX_WKUP_DETECTOR_4, + PINMUX_WKUP_DETECTOR_5, + PINMUX_WKUP_DETECTOR_6, + PINMUX_WKUP_DETECTOR_7, + PINMUX_WKUP_DETECTOR_CNT_TH_0, + PINMUX_WKUP_DETECTOR_CNT_TH_1, + PINMUX_WKUP_DETECTOR_CNT_TH_2, + PINMUX_WKUP_DETECTOR_CNT_TH_3, + PINMUX_WKUP_DETECTOR_CNT_TH_4, + PINMUX_WKUP_DETECTOR_CNT_TH_5, + PINMUX_WKUP_DETECTOR_CNT_TH_6, + PINMUX_WKUP_DETECTOR_CNT_TH_7, + PINMUX_WKUP_DETECTOR_PADSEL_0, + PINMUX_WKUP_DETECTOR_PADSEL_1, + PINMUX_WKUP_DETECTOR_PADSEL_2, + PINMUX_WKUP_DETECTOR_PADSEL_3, + PINMUX_WKUP_DETECTOR_PADSEL_4, + PINMUX_WKUP_DETECTOR_PADSEL_5, + PINMUX_WKUP_DETECTOR_PADSEL_6, + PINMUX_WKUP_DETECTOR_PADSEL_7, + PINMUX_WKUP_CAUSE + } pinmux_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] PINMUX_PERMIT [503] = '{ + 4'b 0001, // index[ 0] PINMUX_ALERT_TEST + 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_0 + 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_1 + 4'b 0001, // index[ 3] PINMUX_MIO_PERIPH_INSEL_REGWEN_2 + 4'b 0001, // index[ 4] PINMUX_MIO_PERIPH_INSEL_REGWEN_3 + 4'b 0001, // index[ 5] PINMUX_MIO_PERIPH_INSEL_0 + 4'b 0001, // index[ 6] PINMUX_MIO_PERIPH_INSEL_1 + 4'b 0001, // index[ 7] PINMUX_MIO_PERIPH_INSEL_2 + 4'b 0001, // index[ 8] PINMUX_MIO_PERIPH_INSEL_3 + 4'b 0001, // index[ 9] PINMUX_MIO_OUTSEL_REGWEN_0 + 4'b 0001, // index[ 10] PINMUX_MIO_OUTSEL_REGWEN_1 + 4'b 0001, // index[ 11] PINMUX_MIO_OUTSEL_REGWEN_2 + 4'b 0001, // index[ 12] PINMUX_MIO_OUTSEL_REGWEN_3 + 4'b 0001, // index[ 13] PINMUX_MIO_OUTSEL_REGWEN_4 + 4'b 0001, // index[ 14] PINMUX_MIO_OUTSEL_REGWEN_5 + 4'b 0001, // index[ 15] PINMUX_MIO_OUTSEL_REGWEN_6 + 4'b 0001, // index[ 16] PINMUX_MIO_OUTSEL_REGWEN_7 + 4'b 0001, // index[ 17] PINMUX_MIO_OUTSEL_REGWEN_8 + 4'b 0001, // index[ 18] PINMUX_MIO_OUTSEL_REGWEN_9 + 4'b 0001, // index[ 19] PINMUX_MIO_OUTSEL_REGWEN_10 + 4'b 0001, // index[ 20] PINMUX_MIO_OUTSEL_REGWEN_11 + 4'b 0001, // index[ 21] PINMUX_MIO_OUTSEL_0 + 4'b 0001, // index[ 22] PINMUX_MIO_OUTSEL_1 + 4'b 0001, // index[ 23] PINMUX_MIO_OUTSEL_2 + 4'b 0001, // index[ 24] PINMUX_MIO_OUTSEL_3 + 4'b 0001, // index[ 25] PINMUX_MIO_OUTSEL_4 + 4'b 0001, // index[ 26] PINMUX_MIO_OUTSEL_5 + 4'b 0001, // index[ 27] PINMUX_MIO_OUTSEL_6 + 4'b 0001, // index[ 28] PINMUX_MIO_OUTSEL_7 + 4'b 0001, // index[ 29] PINMUX_MIO_OUTSEL_8 + 4'b 0001, // index[ 30] PINMUX_MIO_OUTSEL_9 + 4'b 0001, // index[ 31] PINMUX_MIO_OUTSEL_10 + 4'b 0001, // index[ 32] PINMUX_MIO_OUTSEL_11 + 4'b 0001, // index[ 33] PINMUX_MIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[ 34] PINMUX_MIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[ 35] PINMUX_MIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[ 36] PINMUX_MIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[ 37] PINMUX_MIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[ 38] PINMUX_MIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[ 39] PINMUX_MIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[ 40] PINMUX_MIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[ 41] PINMUX_MIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[ 42] PINMUX_MIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[ 43] PINMUX_MIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[ 44] PINMUX_MIO_PAD_ATTR_REGWEN_11 + 4'b 0111, // index[ 45] PINMUX_MIO_PAD_ATTR_0 + 4'b 0111, // index[ 46] PINMUX_MIO_PAD_ATTR_1 + 4'b 0111, // index[ 47] PINMUX_MIO_PAD_ATTR_2 + 4'b 0111, // index[ 48] PINMUX_MIO_PAD_ATTR_3 + 4'b 0111, // index[ 49] PINMUX_MIO_PAD_ATTR_4 + 4'b 0111, // index[ 50] PINMUX_MIO_PAD_ATTR_5 + 4'b 0111, // index[ 51] PINMUX_MIO_PAD_ATTR_6 + 4'b 0111, // index[ 52] PINMUX_MIO_PAD_ATTR_7 + 4'b 0111, // index[ 53] PINMUX_MIO_PAD_ATTR_8 + 4'b 0111, // index[ 54] PINMUX_MIO_PAD_ATTR_9 + 4'b 0111, // index[ 55] PINMUX_MIO_PAD_ATTR_10 + 4'b 0111, // index[ 56] PINMUX_MIO_PAD_ATTR_11 + 4'b 0001, // index[ 57] PINMUX_DIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[ 58] PINMUX_DIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[ 59] PINMUX_DIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[ 60] PINMUX_DIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[ 61] PINMUX_DIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[ 62] PINMUX_DIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[ 63] PINMUX_DIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[ 64] PINMUX_DIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[ 65] PINMUX_DIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[ 66] PINMUX_DIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[ 67] PINMUX_DIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[ 68] PINMUX_DIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[ 69] PINMUX_DIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[ 70] PINMUX_DIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[ 71] PINMUX_DIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[ 72] PINMUX_DIO_PAD_ATTR_REGWEN_15 + 4'b 0001, // index[ 73] PINMUX_DIO_PAD_ATTR_REGWEN_16 + 4'b 0001, // index[ 74] PINMUX_DIO_PAD_ATTR_REGWEN_17 + 4'b 0001, // index[ 75] PINMUX_DIO_PAD_ATTR_REGWEN_18 + 4'b 0001, // index[ 76] PINMUX_DIO_PAD_ATTR_REGWEN_19 + 4'b 0001, // index[ 77] PINMUX_DIO_PAD_ATTR_REGWEN_20 + 4'b 0001, // index[ 78] PINMUX_DIO_PAD_ATTR_REGWEN_21 + 4'b 0001, // index[ 79] PINMUX_DIO_PAD_ATTR_REGWEN_22 + 4'b 0001, // index[ 80] PINMUX_DIO_PAD_ATTR_REGWEN_23 + 4'b 0001, // index[ 81] PINMUX_DIO_PAD_ATTR_REGWEN_24 + 4'b 0001, // index[ 82] PINMUX_DIO_PAD_ATTR_REGWEN_25 + 4'b 0001, // index[ 83] PINMUX_DIO_PAD_ATTR_REGWEN_26 + 4'b 0001, // index[ 84] PINMUX_DIO_PAD_ATTR_REGWEN_27 + 4'b 0001, // index[ 85] PINMUX_DIO_PAD_ATTR_REGWEN_28 + 4'b 0001, // index[ 86] PINMUX_DIO_PAD_ATTR_REGWEN_29 + 4'b 0001, // index[ 87] PINMUX_DIO_PAD_ATTR_REGWEN_30 + 4'b 0001, // index[ 88] PINMUX_DIO_PAD_ATTR_REGWEN_31 + 4'b 0001, // index[ 89] PINMUX_DIO_PAD_ATTR_REGWEN_32 + 4'b 0001, // index[ 90] PINMUX_DIO_PAD_ATTR_REGWEN_33 + 4'b 0001, // index[ 91] PINMUX_DIO_PAD_ATTR_REGWEN_34 + 4'b 0001, // index[ 92] PINMUX_DIO_PAD_ATTR_REGWEN_35 + 4'b 0001, // index[ 93] PINMUX_DIO_PAD_ATTR_REGWEN_36 + 4'b 0001, // index[ 94] PINMUX_DIO_PAD_ATTR_REGWEN_37 + 4'b 0001, // index[ 95] PINMUX_DIO_PAD_ATTR_REGWEN_38 + 4'b 0001, // index[ 96] PINMUX_DIO_PAD_ATTR_REGWEN_39 + 4'b 0001, // index[ 97] PINMUX_DIO_PAD_ATTR_REGWEN_40 + 4'b 0001, // index[ 98] PINMUX_DIO_PAD_ATTR_REGWEN_41 + 4'b 0001, // index[ 99] PINMUX_DIO_PAD_ATTR_REGWEN_42 + 4'b 0001, // index[100] PINMUX_DIO_PAD_ATTR_REGWEN_43 + 4'b 0001, // index[101] PINMUX_DIO_PAD_ATTR_REGWEN_44 + 4'b 0001, // index[102] PINMUX_DIO_PAD_ATTR_REGWEN_45 + 4'b 0001, // index[103] PINMUX_DIO_PAD_ATTR_REGWEN_46 + 4'b 0001, // index[104] PINMUX_DIO_PAD_ATTR_REGWEN_47 + 4'b 0001, // index[105] PINMUX_DIO_PAD_ATTR_REGWEN_48 + 4'b 0001, // index[106] PINMUX_DIO_PAD_ATTR_REGWEN_49 + 4'b 0001, // index[107] PINMUX_DIO_PAD_ATTR_REGWEN_50 + 4'b 0001, // index[108] PINMUX_DIO_PAD_ATTR_REGWEN_51 + 4'b 0001, // index[109] PINMUX_DIO_PAD_ATTR_REGWEN_52 + 4'b 0001, // index[110] PINMUX_DIO_PAD_ATTR_REGWEN_53 + 4'b 0001, // index[111] PINMUX_DIO_PAD_ATTR_REGWEN_54 + 4'b 0001, // index[112] PINMUX_DIO_PAD_ATTR_REGWEN_55 + 4'b 0001, // index[113] PINMUX_DIO_PAD_ATTR_REGWEN_56 + 4'b 0001, // index[114] PINMUX_DIO_PAD_ATTR_REGWEN_57 + 4'b 0001, // index[115] PINMUX_DIO_PAD_ATTR_REGWEN_58 + 4'b 0001, // index[116] PINMUX_DIO_PAD_ATTR_REGWEN_59 + 4'b 0001, // index[117] PINMUX_DIO_PAD_ATTR_REGWEN_60 + 4'b 0001, // index[118] PINMUX_DIO_PAD_ATTR_REGWEN_61 + 4'b 0001, // index[119] PINMUX_DIO_PAD_ATTR_REGWEN_62 + 4'b 0001, // index[120] PINMUX_DIO_PAD_ATTR_REGWEN_63 + 4'b 0001, // index[121] PINMUX_DIO_PAD_ATTR_REGWEN_64 + 4'b 0001, // index[122] PINMUX_DIO_PAD_ATTR_REGWEN_65 + 4'b 0001, // index[123] PINMUX_DIO_PAD_ATTR_REGWEN_66 + 4'b 0001, // index[124] PINMUX_DIO_PAD_ATTR_REGWEN_67 + 4'b 0001, // index[125] PINMUX_DIO_PAD_ATTR_REGWEN_68 + 4'b 0001, // index[126] PINMUX_DIO_PAD_ATTR_REGWEN_69 + 4'b 0001, // index[127] PINMUX_DIO_PAD_ATTR_REGWEN_70 + 4'b 0001, // index[128] PINMUX_DIO_PAD_ATTR_REGWEN_71 + 4'b 0001, // index[129] PINMUX_DIO_PAD_ATTR_REGWEN_72 + 4'b 0111, // index[130] PINMUX_DIO_PAD_ATTR_0 + 4'b 0111, // index[131] PINMUX_DIO_PAD_ATTR_1 + 4'b 0111, // index[132] PINMUX_DIO_PAD_ATTR_2 + 4'b 0111, // index[133] PINMUX_DIO_PAD_ATTR_3 + 4'b 0111, // index[134] PINMUX_DIO_PAD_ATTR_4 + 4'b 0111, // index[135] PINMUX_DIO_PAD_ATTR_5 + 4'b 0111, // index[136] PINMUX_DIO_PAD_ATTR_6 + 4'b 0111, // index[137] PINMUX_DIO_PAD_ATTR_7 + 4'b 0111, // index[138] PINMUX_DIO_PAD_ATTR_8 + 4'b 0111, // index[139] PINMUX_DIO_PAD_ATTR_9 + 4'b 0111, // index[140] PINMUX_DIO_PAD_ATTR_10 + 4'b 0111, // index[141] PINMUX_DIO_PAD_ATTR_11 + 4'b 0111, // index[142] PINMUX_DIO_PAD_ATTR_12 + 4'b 0111, // index[143] PINMUX_DIO_PAD_ATTR_13 + 4'b 0111, // index[144] PINMUX_DIO_PAD_ATTR_14 + 4'b 0111, // index[145] PINMUX_DIO_PAD_ATTR_15 + 4'b 0111, // index[146] PINMUX_DIO_PAD_ATTR_16 + 4'b 0111, // index[147] PINMUX_DIO_PAD_ATTR_17 + 4'b 0111, // index[148] PINMUX_DIO_PAD_ATTR_18 + 4'b 0111, // index[149] PINMUX_DIO_PAD_ATTR_19 + 4'b 0111, // index[150] PINMUX_DIO_PAD_ATTR_20 + 4'b 0111, // index[151] PINMUX_DIO_PAD_ATTR_21 + 4'b 0111, // index[152] PINMUX_DIO_PAD_ATTR_22 + 4'b 0111, // index[153] PINMUX_DIO_PAD_ATTR_23 + 4'b 0111, // index[154] PINMUX_DIO_PAD_ATTR_24 + 4'b 0111, // index[155] PINMUX_DIO_PAD_ATTR_25 + 4'b 0111, // index[156] PINMUX_DIO_PAD_ATTR_26 + 4'b 0111, // index[157] PINMUX_DIO_PAD_ATTR_27 + 4'b 0111, // index[158] PINMUX_DIO_PAD_ATTR_28 + 4'b 0111, // index[159] PINMUX_DIO_PAD_ATTR_29 + 4'b 0111, // index[160] PINMUX_DIO_PAD_ATTR_30 + 4'b 0111, // index[161] PINMUX_DIO_PAD_ATTR_31 + 4'b 0111, // index[162] PINMUX_DIO_PAD_ATTR_32 + 4'b 0111, // index[163] PINMUX_DIO_PAD_ATTR_33 + 4'b 0111, // index[164] PINMUX_DIO_PAD_ATTR_34 + 4'b 0111, // index[165] PINMUX_DIO_PAD_ATTR_35 + 4'b 0111, // index[166] PINMUX_DIO_PAD_ATTR_36 + 4'b 0111, // index[167] PINMUX_DIO_PAD_ATTR_37 + 4'b 0111, // index[168] PINMUX_DIO_PAD_ATTR_38 + 4'b 0111, // index[169] PINMUX_DIO_PAD_ATTR_39 + 4'b 0111, // index[170] PINMUX_DIO_PAD_ATTR_40 + 4'b 0111, // index[171] PINMUX_DIO_PAD_ATTR_41 + 4'b 0111, // index[172] PINMUX_DIO_PAD_ATTR_42 + 4'b 0111, // index[173] PINMUX_DIO_PAD_ATTR_43 + 4'b 0111, // index[174] PINMUX_DIO_PAD_ATTR_44 + 4'b 0111, // index[175] PINMUX_DIO_PAD_ATTR_45 + 4'b 0111, // index[176] PINMUX_DIO_PAD_ATTR_46 + 4'b 0111, // index[177] PINMUX_DIO_PAD_ATTR_47 + 4'b 0111, // index[178] PINMUX_DIO_PAD_ATTR_48 + 4'b 0111, // index[179] PINMUX_DIO_PAD_ATTR_49 + 4'b 0111, // index[180] PINMUX_DIO_PAD_ATTR_50 + 4'b 0111, // index[181] PINMUX_DIO_PAD_ATTR_51 + 4'b 0111, // index[182] PINMUX_DIO_PAD_ATTR_52 + 4'b 0111, // index[183] PINMUX_DIO_PAD_ATTR_53 + 4'b 0111, // index[184] PINMUX_DIO_PAD_ATTR_54 + 4'b 0111, // index[185] PINMUX_DIO_PAD_ATTR_55 + 4'b 0111, // index[186] PINMUX_DIO_PAD_ATTR_56 + 4'b 0111, // index[187] PINMUX_DIO_PAD_ATTR_57 + 4'b 0111, // index[188] PINMUX_DIO_PAD_ATTR_58 + 4'b 0111, // index[189] PINMUX_DIO_PAD_ATTR_59 + 4'b 0111, // index[190] PINMUX_DIO_PAD_ATTR_60 + 4'b 0111, // index[191] PINMUX_DIO_PAD_ATTR_61 + 4'b 0111, // index[192] PINMUX_DIO_PAD_ATTR_62 + 4'b 0111, // index[193] PINMUX_DIO_PAD_ATTR_63 + 4'b 0111, // index[194] PINMUX_DIO_PAD_ATTR_64 + 4'b 0111, // index[195] PINMUX_DIO_PAD_ATTR_65 + 4'b 0111, // index[196] PINMUX_DIO_PAD_ATTR_66 + 4'b 0111, // index[197] PINMUX_DIO_PAD_ATTR_67 + 4'b 0111, // index[198] PINMUX_DIO_PAD_ATTR_68 + 4'b 0111, // index[199] PINMUX_DIO_PAD_ATTR_69 + 4'b 0111, // index[200] PINMUX_DIO_PAD_ATTR_70 + 4'b 0111, // index[201] PINMUX_DIO_PAD_ATTR_71 + 4'b 0111, // index[202] PINMUX_DIO_PAD_ATTR_72 + 4'b 0011, // index[203] PINMUX_MIO_PAD_SLEEP_STATUS + 4'b 0001, // index[204] PINMUX_MIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[205] PINMUX_MIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[206] PINMUX_MIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[207] PINMUX_MIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[208] PINMUX_MIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[209] PINMUX_MIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[210] PINMUX_MIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[211] PINMUX_MIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[212] PINMUX_MIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[213] PINMUX_MIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[214] PINMUX_MIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[215] PINMUX_MIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[216] PINMUX_MIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[217] PINMUX_MIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[218] PINMUX_MIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[219] PINMUX_MIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[220] PINMUX_MIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[221] PINMUX_MIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[222] PINMUX_MIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[223] PINMUX_MIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[224] PINMUX_MIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[225] PINMUX_MIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[226] PINMUX_MIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[227] PINMUX_MIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[228] PINMUX_MIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[229] PINMUX_MIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[230] PINMUX_MIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[231] PINMUX_MIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[232] PINMUX_MIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[233] PINMUX_MIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[234] PINMUX_MIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[235] PINMUX_MIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[236] PINMUX_MIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[237] PINMUX_MIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[238] PINMUX_MIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[239] PINMUX_MIO_PAD_SLEEP_MODE_11 + 4'b 1111, // index[240] PINMUX_DIO_PAD_SLEEP_STATUS_0 + 4'b 1111, // index[241] PINMUX_DIO_PAD_SLEEP_STATUS_1 + 4'b 0011, // index[242] PINMUX_DIO_PAD_SLEEP_STATUS_2 + 4'b 0001, // index[243] PINMUX_DIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[244] PINMUX_DIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[245] PINMUX_DIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[246] PINMUX_DIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[247] PINMUX_DIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[248] PINMUX_DIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[249] PINMUX_DIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[250] PINMUX_DIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[251] PINMUX_DIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[252] PINMUX_DIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[253] PINMUX_DIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[254] PINMUX_DIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[255] PINMUX_DIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[256] PINMUX_DIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[257] PINMUX_DIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[258] PINMUX_DIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[259] PINMUX_DIO_PAD_SLEEP_REGWEN_16 + 4'b 0001, // index[260] PINMUX_DIO_PAD_SLEEP_REGWEN_17 + 4'b 0001, // index[261] PINMUX_DIO_PAD_SLEEP_REGWEN_18 + 4'b 0001, // index[262] PINMUX_DIO_PAD_SLEEP_REGWEN_19 + 4'b 0001, // index[263] PINMUX_DIO_PAD_SLEEP_REGWEN_20 + 4'b 0001, // index[264] PINMUX_DIO_PAD_SLEEP_REGWEN_21 + 4'b 0001, // index[265] PINMUX_DIO_PAD_SLEEP_REGWEN_22 + 4'b 0001, // index[266] PINMUX_DIO_PAD_SLEEP_REGWEN_23 + 4'b 0001, // index[267] PINMUX_DIO_PAD_SLEEP_REGWEN_24 + 4'b 0001, // index[268] PINMUX_DIO_PAD_SLEEP_REGWEN_25 + 4'b 0001, // index[269] PINMUX_DIO_PAD_SLEEP_REGWEN_26 + 4'b 0001, // index[270] PINMUX_DIO_PAD_SLEEP_REGWEN_27 + 4'b 0001, // index[271] PINMUX_DIO_PAD_SLEEP_REGWEN_28 + 4'b 0001, // index[272] PINMUX_DIO_PAD_SLEEP_REGWEN_29 + 4'b 0001, // index[273] PINMUX_DIO_PAD_SLEEP_REGWEN_30 + 4'b 0001, // index[274] PINMUX_DIO_PAD_SLEEP_REGWEN_31 + 4'b 0001, // index[275] PINMUX_DIO_PAD_SLEEP_REGWEN_32 + 4'b 0001, // index[276] PINMUX_DIO_PAD_SLEEP_REGWEN_33 + 4'b 0001, // index[277] PINMUX_DIO_PAD_SLEEP_REGWEN_34 + 4'b 0001, // index[278] PINMUX_DIO_PAD_SLEEP_REGWEN_35 + 4'b 0001, // index[279] PINMUX_DIO_PAD_SLEEP_REGWEN_36 + 4'b 0001, // index[280] PINMUX_DIO_PAD_SLEEP_REGWEN_37 + 4'b 0001, // index[281] PINMUX_DIO_PAD_SLEEP_REGWEN_38 + 4'b 0001, // index[282] PINMUX_DIO_PAD_SLEEP_REGWEN_39 + 4'b 0001, // index[283] PINMUX_DIO_PAD_SLEEP_REGWEN_40 + 4'b 0001, // index[284] PINMUX_DIO_PAD_SLEEP_REGWEN_41 + 4'b 0001, // index[285] PINMUX_DIO_PAD_SLEEP_REGWEN_42 + 4'b 0001, // index[286] PINMUX_DIO_PAD_SLEEP_REGWEN_43 + 4'b 0001, // index[287] PINMUX_DIO_PAD_SLEEP_REGWEN_44 + 4'b 0001, // index[288] PINMUX_DIO_PAD_SLEEP_REGWEN_45 + 4'b 0001, // index[289] PINMUX_DIO_PAD_SLEEP_REGWEN_46 + 4'b 0001, // index[290] PINMUX_DIO_PAD_SLEEP_REGWEN_47 + 4'b 0001, // index[291] PINMUX_DIO_PAD_SLEEP_REGWEN_48 + 4'b 0001, // index[292] PINMUX_DIO_PAD_SLEEP_REGWEN_49 + 4'b 0001, // index[293] PINMUX_DIO_PAD_SLEEP_REGWEN_50 + 4'b 0001, // index[294] PINMUX_DIO_PAD_SLEEP_REGWEN_51 + 4'b 0001, // index[295] PINMUX_DIO_PAD_SLEEP_REGWEN_52 + 4'b 0001, // index[296] PINMUX_DIO_PAD_SLEEP_REGWEN_53 + 4'b 0001, // index[297] PINMUX_DIO_PAD_SLEEP_REGWEN_54 + 4'b 0001, // index[298] PINMUX_DIO_PAD_SLEEP_REGWEN_55 + 4'b 0001, // index[299] PINMUX_DIO_PAD_SLEEP_REGWEN_56 + 4'b 0001, // index[300] PINMUX_DIO_PAD_SLEEP_REGWEN_57 + 4'b 0001, // index[301] PINMUX_DIO_PAD_SLEEP_REGWEN_58 + 4'b 0001, // index[302] PINMUX_DIO_PAD_SLEEP_REGWEN_59 + 4'b 0001, // index[303] PINMUX_DIO_PAD_SLEEP_REGWEN_60 + 4'b 0001, // index[304] PINMUX_DIO_PAD_SLEEP_REGWEN_61 + 4'b 0001, // index[305] PINMUX_DIO_PAD_SLEEP_REGWEN_62 + 4'b 0001, // index[306] PINMUX_DIO_PAD_SLEEP_REGWEN_63 + 4'b 0001, // index[307] PINMUX_DIO_PAD_SLEEP_REGWEN_64 + 4'b 0001, // index[308] PINMUX_DIO_PAD_SLEEP_REGWEN_65 + 4'b 0001, // index[309] PINMUX_DIO_PAD_SLEEP_REGWEN_66 + 4'b 0001, // index[310] PINMUX_DIO_PAD_SLEEP_REGWEN_67 + 4'b 0001, // index[311] PINMUX_DIO_PAD_SLEEP_REGWEN_68 + 4'b 0001, // index[312] PINMUX_DIO_PAD_SLEEP_REGWEN_69 + 4'b 0001, // index[313] PINMUX_DIO_PAD_SLEEP_REGWEN_70 + 4'b 0001, // index[314] PINMUX_DIO_PAD_SLEEP_REGWEN_71 + 4'b 0001, // index[315] PINMUX_DIO_PAD_SLEEP_REGWEN_72 + 4'b 0001, // index[316] PINMUX_DIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[317] PINMUX_DIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[318] PINMUX_DIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[319] PINMUX_DIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[320] PINMUX_DIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[321] PINMUX_DIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[322] PINMUX_DIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[323] PINMUX_DIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[324] PINMUX_DIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[325] PINMUX_DIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[326] PINMUX_DIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[327] PINMUX_DIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[328] PINMUX_DIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[329] PINMUX_DIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[330] PINMUX_DIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[331] PINMUX_DIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[332] PINMUX_DIO_PAD_SLEEP_EN_16 + 4'b 0001, // index[333] PINMUX_DIO_PAD_SLEEP_EN_17 + 4'b 0001, // index[334] PINMUX_DIO_PAD_SLEEP_EN_18 + 4'b 0001, // index[335] PINMUX_DIO_PAD_SLEEP_EN_19 + 4'b 0001, // index[336] PINMUX_DIO_PAD_SLEEP_EN_20 + 4'b 0001, // index[337] PINMUX_DIO_PAD_SLEEP_EN_21 + 4'b 0001, // index[338] PINMUX_DIO_PAD_SLEEP_EN_22 + 4'b 0001, // index[339] PINMUX_DIO_PAD_SLEEP_EN_23 + 4'b 0001, // index[340] PINMUX_DIO_PAD_SLEEP_EN_24 + 4'b 0001, // index[341] PINMUX_DIO_PAD_SLEEP_EN_25 + 4'b 0001, // index[342] PINMUX_DIO_PAD_SLEEP_EN_26 + 4'b 0001, // index[343] PINMUX_DIO_PAD_SLEEP_EN_27 + 4'b 0001, // index[344] PINMUX_DIO_PAD_SLEEP_EN_28 + 4'b 0001, // index[345] PINMUX_DIO_PAD_SLEEP_EN_29 + 4'b 0001, // index[346] PINMUX_DIO_PAD_SLEEP_EN_30 + 4'b 0001, // index[347] PINMUX_DIO_PAD_SLEEP_EN_31 + 4'b 0001, // index[348] PINMUX_DIO_PAD_SLEEP_EN_32 + 4'b 0001, // index[349] PINMUX_DIO_PAD_SLEEP_EN_33 + 4'b 0001, // index[350] PINMUX_DIO_PAD_SLEEP_EN_34 + 4'b 0001, // index[351] PINMUX_DIO_PAD_SLEEP_EN_35 + 4'b 0001, // index[352] PINMUX_DIO_PAD_SLEEP_EN_36 + 4'b 0001, // index[353] PINMUX_DIO_PAD_SLEEP_EN_37 + 4'b 0001, // index[354] PINMUX_DIO_PAD_SLEEP_EN_38 + 4'b 0001, // index[355] PINMUX_DIO_PAD_SLEEP_EN_39 + 4'b 0001, // index[356] PINMUX_DIO_PAD_SLEEP_EN_40 + 4'b 0001, // index[357] PINMUX_DIO_PAD_SLEEP_EN_41 + 4'b 0001, // index[358] PINMUX_DIO_PAD_SLEEP_EN_42 + 4'b 0001, // index[359] PINMUX_DIO_PAD_SLEEP_EN_43 + 4'b 0001, // index[360] PINMUX_DIO_PAD_SLEEP_EN_44 + 4'b 0001, // index[361] PINMUX_DIO_PAD_SLEEP_EN_45 + 4'b 0001, // index[362] PINMUX_DIO_PAD_SLEEP_EN_46 + 4'b 0001, // index[363] PINMUX_DIO_PAD_SLEEP_EN_47 + 4'b 0001, // index[364] PINMUX_DIO_PAD_SLEEP_EN_48 + 4'b 0001, // index[365] PINMUX_DIO_PAD_SLEEP_EN_49 + 4'b 0001, // index[366] PINMUX_DIO_PAD_SLEEP_EN_50 + 4'b 0001, // index[367] PINMUX_DIO_PAD_SLEEP_EN_51 + 4'b 0001, // index[368] PINMUX_DIO_PAD_SLEEP_EN_52 + 4'b 0001, // index[369] PINMUX_DIO_PAD_SLEEP_EN_53 + 4'b 0001, // index[370] PINMUX_DIO_PAD_SLEEP_EN_54 + 4'b 0001, // index[371] PINMUX_DIO_PAD_SLEEP_EN_55 + 4'b 0001, // index[372] PINMUX_DIO_PAD_SLEEP_EN_56 + 4'b 0001, // index[373] PINMUX_DIO_PAD_SLEEP_EN_57 + 4'b 0001, // index[374] PINMUX_DIO_PAD_SLEEP_EN_58 + 4'b 0001, // index[375] PINMUX_DIO_PAD_SLEEP_EN_59 + 4'b 0001, // index[376] PINMUX_DIO_PAD_SLEEP_EN_60 + 4'b 0001, // index[377] PINMUX_DIO_PAD_SLEEP_EN_61 + 4'b 0001, // index[378] PINMUX_DIO_PAD_SLEEP_EN_62 + 4'b 0001, // index[379] PINMUX_DIO_PAD_SLEEP_EN_63 + 4'b 0001, // index[380] PINMUX_DIO_PAD_SLEEP_EN_64 + 4'b 0001, // index[381] PINMUX_DIO_PAD_SLEEP_EN_65 + 4'b 0001, // index[382] PINMUX_DIO_PAD_SLEEP_EN_66 + 4'b 0001, // index[383] PINMUX_DIO_PAD_SLEEP_EN_67 + 4'b 0001, // index[384] PINMUX_DIO_PAD_SLEEP_EN_68 + 4'b 0001, // index[385] PINMUX_DIO_PAD_SLEEP_EN_69 + 4'b 0001, // index[386] PINMUX_DIO_PAD_SLEEP_EN_70 + 4'b 0001, // index[387] PINMUX_DIO_PAD_SLEEP_EN_71 + 4'b 0001, // index[388] PINMUX_DIO_PAD_SLEEP_EN_72 + 4'b 0001, // index[389] PINMUX_DIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[390] PINMUX_DIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[391] PINMUX_DIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[392] PINMUX_DIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[393] PINMUX_DIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[394] PINMUX_DIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[395] PINMUX_DIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[396] PINMUX_DIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[397] PINMUX_DIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[398] PINMUX_DIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[399] PINMUX_DIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[400] PINMUX_DIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[401] PINMUX_DIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[402] PINMUX_DIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[403] PINMUX_DIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[404] PINMUX_DIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[405] PINMUX_DIO_PAD_SLEEP_MODE_16 + 4'b 0001, // index[406] PINMUX_DIO_PAD_SLEEP_MODE_17 + 4'b 0001, // index[407] PINMUX_DIO_PAD_SLEEP_MODE_18 + 4'b 0001, // index[408] PINMUX_DIO_PAD_SLEEP_MODE_19 + 4'b 0001, // index[409] PINMUX_DIO_PAD_SLEEP_MODE_20 + 4'b 0001, // index[410] PINMUX_DIO_PAD_SLEEP_MODE_21 + 4'b 0001, // index[411] PINMUX_DIO_PAD_SLEEP_MODE_22 + 4'b 0001, // index[412] PINMUX_DIO_PAD_SLEEP_MODE_23 + 4'b 0001, // index[413] PINMUX_DIO_PAD_SLEEP_MODE_24 + 4'b 0001, // index[414] PINMUX_DIO_PAD_SLEEP_MODE_25 + 4'b 0001, // index[415] PINMUX_DIO_PAD_SLEEP_MODE_26 + 4'b 0001, // index[416] PINMUX_DIO_PAD_SLEEP_MODE_27 + 4'b 0001, // index[417] PINMUX_DIO_PAD_SLEEP_MODE_28 + 4'b 0001, // index[418] PINMUX_DIO_PAD_SLEEP_MODE_29 + 4'b 0001, // index[419] PINMUX_DIO_PAD_SLEEP_MODE_30 + 4'b 0001, // index[420] PINMUX_DIO_PAD_SLEEP_MODE_31 + 4'b 0001, // index[421] PINMUX_DIO_PAD_SLEEP_MODE_32 + 4'b 0001, // index[422] PINMUX_DIO_PAD_SLEEP_MODE_33 + 4'b 0001, // index[423] PINMUX_DIO_PAD_SLEEP_MODE_34 + 4'b 0001, // index[424] PINMUX_DIO_PAD_SLEEP_MODE_35 + 4'b 0001, // index[425] PINMUX_DIO_PAD_SLEEP_MODE_36 + 4'b 0001, // index[426] PINMUX_DIO_PAD_SLEEP_MODE_37 + 4'b 0001, // index[427] PINMUX_DIO_PAD_SLEEP_MODE_38 + 4'b 0001, // index[428] PINMUX_DIO_PAD_SLEEP_MODE_39 + 4'b 0001, // index[429] PINMUX_DIO_PAD_SLEEP_MODE_40 + 4'b 0001, // index[430] PINMUX_DIO_PAD_SLEEP_MODE_41 + 4'b 0001, // index[431] PINMUX_DIO_PAD_SLEEP_MODE_42 + 4'b 0001, // index[432] PINMUX_DIO_PAD_SLEEP_MODE_43 + 4'b 0001, // index[433] PINMUX_DIO_PAD_SLEEP_MODE_44 + 4'b 0001, // index[434] PINMUX_DIO_PAD_SLEEP_MODE_45 + 4'b 0001, // index[435] PINMUX_DIO_PAD_SLEEP_MODE_46 + 4'b 0001, // index[436] PINMUX_DIO_PAD_SLEEP_MODE_47 + 4'b 0001, // index[437] PINMUX_DIO_PAD_SLEEP_MODE_48 + 4'b 0001, // index[438] PINMUX_DIO_PAD_SLEEP_MODE_49 + 4'b 0001, // index[439] PINMUX_DIO_PAD_SLEEP_MODE_50 + 4'b 0001, // index[440] PINMUX_DIO_PAD_SLEEP_MODE_51 + 4'b 0001, // index[441] PINMUX_DIO_PAD_SLEEP_MODE_52 + 4'b 0001, // index[442] PINMUX_DIO_PAD_SLEEP_MODE_53 + 4'b 0001, // index[443] PINMUX_DIO_PAD_SLEEP_MODE_54 + 4'b 0001, // index[444] PINMUX_DIO_PAD_SLEEP_MODE_55 + 4'b 0001, // index[445] PINMUX_DIO_PAD_SLEEP_MODE_56 + 4'b 0001, // index[446] PINMUX_DIO_PAD_SLEEP_MODE_57 + 4'b 0001, // index[447] PINMUX_DIO_PAD_SLEEP_MODE_58 + 4'b 0001, // index[448] PINMUX_DIO_PAD_SLEEP_MODE_59 + 4'b 0001, // index[449] PINMUX_DIO_PAD_SLEEP_MODE_60 + 4'b 0001, // index[450] PINMUX_DIO_PAD_SLEEP_MODE_61 + 4'b 0001, // index[451] PINMUX_DIO_PAD_SLEEP_MODE_62 + 4'b 0001, // index[452] PINMUX_DIO_PAD_SLEEP_MODE_63 + 4'b 0001, // index[453] PINMUX_DIO_PAD_SLEEP_MODE_64 + 4'b 0001, // index[454] PINMUX_DIO_PAD_SLEEP_MODE_65 + 4'b 0001, // index[455] PINMUX_DIO_PAD_SLEEP_MODE_66 + 4'b 0001, // index[456] PINMUX_DIO_PAD_SLEEP_MODE_67 + 4'b 0001, // index[457] PINMUX_DIO_PAD_SLEEP_MODE_68 + 4'b 0001, // index[458] PINMUX_DIO_PAD_SLEEP_MODE_69 + 4'b 0001, // index[459] PINMUX_DIO_PAD_SLEEP_MODE_70 + 4'b 0001, // index[460] PINMUX_DIO_PAD_SLEEP_MODE_71 + 4'b 0001, // index[461] PINMUX_DIO_PAD_SLEEP_MODE_72 + 4'b 0001, // index[462] PINMUX_WKUP_DETECTOR_REGWEN_0 + 4'b 0001, // index[463] PINMUX_WKUP_DETECTOR_REGWEN_1 + 4'b 0001, // index[464] PINMUX_WKUP_DETECTOR_REGWEN_2 + 4'b 0001, // index[465] PINMUX_WKUP_DETECTOR_REGWEN_3 + 4'b 0001, // index[466] PINMUX_WKUP_DETECTOR_REGWEN_4 + 4'b 0001, // index[467] PINMUX_WKUP_DETECTOR_REGWEN_5 + 4'b 0001, // index[468] PINMUX_WKUP_DETECTOR_REGWEN_6 + 4'b 0001, // index[469] PINMUX_WKUP_DETECTOR_REGWEN_7 + 4'b 0001, // index[470] PINMUX_WKUP_DETECTOR_EN_0 + 4'b 0001, // index[471] PINMUX_WKUP_DETECTOR_EN_1 + 4'b 0001, // index[472] PINMUX_WKUP_DETECTOR_EN_2 + 4'b 0001, // index[473] PINMUX_WKUP_DETECTOR_EN_3 + 4'b 0001, // index[474] PINMUX_WKUP_DETECTOR_EN_4 + 4'b 0001, // index[475] PINMUX_WKUP_DETECTOR_EN_5 + 4'b 0001, // index[476] PINMUX_WKUP_DETECTOR_EN_6 + 4'b 0001, // index[477] PINMUX_WKUP_DETECTOR_EN_7 + 4'b 0001, // index[478] PINMUX_WKUP_DETECTOR_0 + 4'b 0001, // index[479] PINMUX_WKUP_DETECTOR_1 + 4'b 0001, // index[480] PINMUX_WKUP_DETECTOR_2 + 4'b 0001, // index[481] PINMUX_WKUP_DETECTOR_3 + 4'b 0001, // index[482] PINMUX_WKUP_DETECTOR_4 + 4'b 0001, // index[483] PINMUX_WKUP_DETECTOR_5 + 4'b 0001, // index[484] PINMUX_WKUP_DETECTOR_6 + 4'b 0001, // index[485] PINMUX_WKUP_DETECTOR_7 + 4'b 0001, // index[486] PINMUX_WKUP_DETECTOR_CNT_TH_0 + 4'b 0001, // index[487] PINMUX_WKUP_DETECTOR_CNT_TH_1 + 4'b 0001, // index[488] PINMUX_WKUP_DETECTOR_CNT_TH_2 + 4'b 0001, // index[489] PINMUX_WKUP_DETECTOR_CNT_TH_3 + 4'b 0001, // index[490] PINMUX_WKUP_DETECTOR_CNT_TH_4 + 4'b 0001, // index[491] PINMUX_WKUP_DETECTOR_CNT_TH_5 + 4'b 0001, // index[492] PINMUX_WKUP_DETECTOR_CNT_TH_6 + 4'b 0001, // index[493] PINMUX_WKUP_DETECTOR_CNT_TH_7 + 4'b 0001, // index[494] PINMUX_WKUP_DETECTOR_PADSEL_0 + 4'b 0001, // index[495] PINMUX_WKUP_DETECTOR_PADSEL_1 + 4'b 0001, // index[496] PINMUX_WKUP_DETECTOR_PADSEL_2 + 4'b 0001, // index[497] PINMUX_WKUP_DETECTOR_PADSEL_3 + 4'b 0001, // index[498] PINMUX_WKUP_DETECTOR_PADSEL_4 + 4'b 0001, // index[499] PINMUX_WKUP_DETECTOR_PADSEL_5 + 4'b 0001, // index[500] PINMUX_WKUP_DETECTOR_PADSEL_6 + 4'b 0001, // index[501] PINMUX_WKUP_DETECTOR_PADSEL_7 + 4'b 0001 // index[502] PINMUX_WKUP_CAUSE + }; + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_reg_top.sv b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_reg_top.sv new file mode 100644 index 0000000000000..a27a124fa0651 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_reg_top.sv @@ -0,0 +1,42194 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module pinmux_reg_top ( + input clk_i, + input rst_ni, + input clk_aon_i, + input rst_aon_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output pinmux_reg_pkg::pinmux_reg2hw_t reg2hw, // Write + input pinmux_reg_pkg::pinmux_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import pinmux_reg_pkg::* ; + + localparam int AW = 11; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [502:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(503) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic alert_test_we; + logic alert_test_wd; + logic mio_periph_insel_regwen_0_we; + logic mio_periph_insel_regwen_0_qs; + logic mio_periph_insel_regwen_0_wd; + logic mio_periph_insel_regwen_1_we; + logic mio_periph_insel_regwen_1_qs; + logic mio_periph_insel_regwen_1_wd; + logic mio_periph_insel_regwen_2_we; + logic mio_periph_insel_regwen_2_qs; + logic mio_periph_insel_regwen_2_wd; + logic mio_periph_insel_regwen_3_we; + logic mio_periph_insel_regwen_3_qs; + logic mio_periph_insel_regwen_3_wd; + logic mio_periph_insel_0_we; + logic [3:0] mio_periph_insel_0_qs; + logic [3:0] mio_periph_insel_0_wd; + logic mio_periph_insel_1_we; + logic [3:0] mio_periph_insel_1_qs; + logic [3:0] mio_periph_insel_1_wd; + logic mio_periph_insel_2_we; + logic [3:0] mio_periph_insel_2_qs; + logic [3:0] mio_periph_insel_2_wd; + logic mio_periph_insel_3_we; + logic [3:0] mio_periph_insel_3_qs; + logic [3:0] mio_periph_insel_3_wd; + logic mio_outsel_regwen_0_we; + logic mio_outsel_regwen_0_qs; + logic mio_outsel_regwen_0_wd; + logic mio_outsel_regwen_1_we; + logic mio_outsel_regwen_1_qs; + logic mio_outsel_regwen_1_wd; + logic mio_outsel_regwen_2_we; + logic mio_outsel_regwen_2_qs; + logic mio_outsel_regwen_2_wd; + logic mio_outsel_regwen_3_we; + logic mio_outsel_regwen_3_qs; + logic mio_outsel_regwen_3_wd; + logic mio_outsel_regwen_4_we; + logic mio_outsel_regwen_4_qs; + logic mio_outsel_regwen_4_wd; + logic mio_outsel_regwen_5_we; + logic mio_outsel_regwen_5_qs; + logic mio_outsel_regwen_5_wd; + logic mio_outsel_regwen_6_we; + logic mio_outsel_regwen_6_qs; + logic mio_outsel_regwen_6_wd; + logic mio_outsel_regwen_7_we; + logic mio_outsel_regwen_7_qs; + logic mio_outsel_regwen_7_wd; + logic mio_outsel_regwen_8_we; + logic mio_outsel_regwen_8_qs; + logic mio_outsel_regwen_8_wd; + logic mio_outsel_regwen_9_we; + logic mio_outsel_regwen_9_qs; + logic mio_outsel_regwen_9_wd; + logic mio_outsel_regwen_10_we; + logic mio_outsel_regwen_10_qs; + logic mio_outsel_regwen_10_wd; + logic mio_outsel_regwen_11_we; + logic mio_outsel_regwen_11_qs; + logic mio_outsel_regwen_11_wd; + logic mio_outsel_0_we; + logic [2:0] mio_outsel_0_qs; + logic [2:0] mio_outsel_0_wd; + logic mio_outsel_1_we; + logic [2:0] mio_outsel_1_qs; + logic [2:0] mio_outsel_1_wd; + logic mio_outsel_2_we; + logic [2:0] mio_outsel_2_qs; + logic [2:0] mio_outsel_2_wd; + logic mio_outsel_3_we; + logic [2:0] mio_outsel_3_qs; + logic [2:0] mio_outsel_3_wd; + logic mio_outsel_4_we; + logic [2:0] mio_outsel_4_qs; + logic [2:0] mio_outsel_4_wd; + logic mio_outsel_5_we; + logic [2:0] mio_outsel_5_qs; + logic [2:0] mio_outsel_5_wd; + logic mio_outsel_6_we; + logic [2:0] mio_outsel_6_qs; + logic [2:0] mio_outsel_6_wd; + logic mio_outsel_7_we; + logic [2:0] mio_outsel_7_qs; + logic [2:0] mio_outsel_7_wd; + logic mio_outsel_8_we; + logic [2:0] mio_outsel_8_qs; + logic [2:0] mio_outsel_8_wd; + logic mio_outsel_9_we; + logic [2:0] mio_outsel_9_qs; + logic [2:0] mio_outsel_9_wd; + logic mio_outsel_10_we; + logic [2:0] mio_outsel_10_qs; + logic [2:0] mio_outsel_10_wd; + logic mio_outsel_11_we; + logic [2:0] mio_outsel_11_qs; + logic [2:0] mio_outsel_11_wd; + logic mio_pad_attr_regwen_0_we; + logic mio_pad_attr_regwen_0_qs; + logic mio_pad_attr_regwen_0_wd; + logic mio_pad_attr_regwen_1_we; + logic mio_pad_attr_regwen_1_qs; + logic mio_pad_attr_regwen_1_wd; + logic mio_pad_attr_regwen_2_we; + logic mio_pad_attr_regwen_2_qs; + logic mio_pad_attr_regwen_2_wd; + logic mio_pad_attr_regwen_3_we; + logic mio_pad_attr_regwen_3_qs; + logic mio_pad_attr_regwen_3_wd; + logic mio_pad_attr_regwen_4_we; + logic mio_pad_attr_regwen_4_qs; + logic mio_pad_attr_regwen_4_wd; + logic mio_pad_attr_regwen_5_we; + logic mio_pad_attr_regwen_5_qs; + logic mio_pad_attr_regwen_5_wd; + logic mio_pad_attr_regwen_6_we; + logic mio_pad_attr_regwen_6_qs; + logic mio_pad_attr_regwen_6_wd; + logic mio_pad_attr_regwen_7_we; + logic mio_pad_attr_regwen_7_qs; + logic mio_pad_attr_regwen_7_wd; + logic mio_pad_attr_regwen_8_we; + logic mio_pad_attr_regwen_8_qs; + logic mio_pad_attr_regwen_8_wd; + logic mio_pad_attr_regwen_9_we; + logic mio_pad_attr_regwen_9_qs; + logic mio_pad_attr_regwen_9_wd; + logic mio_pad_attr_regwen_10_we; + logic mio_pad_attr_regwen_10_qs; + logic mio_pad_attr_regwen_10_wd; + logic mio_pad_attr_regwen_11_we; + logic mio_pad_attr_regwen_11_qs; + logic mio_pad_attr_regwen_11_wd; + logic mio_pad_attr_0_re; + logic mio_pad_attr_0_we; + logic mio_pad_attr_0_invert_0_qs; + logic mio_pad_attr_0_invert_0_wd; + logic mio_pad_attr_0_virtual_od_en_0_qs; + logic mio_pad_attr_0_virtual_od_en_0_wd; + logic mio_pad_attr_0_pull_en_0_qs; + logic mio_pad_attr_0_pull_en_0_wd; + logic mio_pad_attr_0_pull_select_0_qs; + logic mio_pad_attr_0_pull_select_0_wd; + logic mio_pad_attr_0_keeper_en_0_qs; + logic mio_pad_attr_0_keeper_en_0_wd; + logic mio_pad_attr_0_schmitt_en_0_qs; + logic mio_pad_attr_0_schmitt_en_0_wd; + logic mio_pad_attr_0_od_en_0_qs; + logic mio_pad_attr_0_od_en_0_wd; + logic mio_pad_attr_0_input_disable_0_qs; + logic mio_pad_attr_0_input_disable_0_wd; + logic [1:0] mio_pad_attr_0_slew_rate_0_qs; + logic [1:0] mio_pad_attr_0_slew_rate_0_wd; + logic [3:0] mio_pad_attr_0_drive_strength_0_qs; + logic [3:0] mio_pad_attr_0_drive_strength_0_wd; + logic mio_pad_attr_1_re; + logic mio_pad_attr_1_we; + logic mio_pad_attr_1_invert_1_qs; + logic mio_pad_attr_1_invert_1_wd; + logic mio_pad_attr_1_virtual_od_en_1_qs; + logic mio_pad_attr_1_virtual_od_en_1_wd; + logic mio_pad_attr_1_pull_en_1_qs; + logic mio_pad_attr_1_pull_en_1_wd; + logic mio_pad_attr_1_pull_select_1_qs; + logic mio_pad_attr_1_pull_select_1_wd; + logic mio_pad_attr_1_keeper_en_1_qs; + logic mio_pad_attr_1_keeper_en_1_wd; + logic mio_pad_attr_1_schmitt_en_1_qs; + logic mio_pad_attr_1_schmitt_en_1_wd; + logic mio_pad_attr_1_od_en_1_qs; + logic mio_pad_attr_1_od_en_1_wd; + logic mio_pad_attr_1_input_disable_1_qs; + logic mio_pad_attr_1_input_disable_1_wd; + logic [1:0] mio_pad_attr_1_slew_rate_1_qs; + logic [1:0] mio_pad_attr_1_slew_rate_1_wd; + logic [3:0] mio_pad_attr_1_drive_strength_1_qs; + logic [3:0] mio_pad_attr_1_drive_strength_1_wd; + logic mio_pad_attr_2_re; + logic mio_pad_attr_2_we; + logic mio_pad_attr_2_invert_2_qs; + logic mio_pad_attr_2_invert_2_wd; + logic mio_pad_attr_2_virtual_od_en_2_qs; + logic mio_pad_attr_2_virtual_od_en_2_wd; + logic mio_pad_attr_2_pull_en_2_qs; + logic mio_pad_attr_2_pull_en_2_wd; + logic mio_pad_attr_2_pull_select_2_qs; + logic mio_pad_attr_2_pull_select_2_wd; + logic mio_pad_attr_2_keeper_en_2_qs; + logic mio_pad_attr_2_keeper_en_2_wd; + logic mio_pad_attr_2_schmitt_en_2_qs; + logic mio_pad_attr_2_schmitt_en_2_wd; + logic mio_pad_attr_2_od_en_2_qs; + logic mio_pad_attr_2_od_en_2_wd; + logic mio_pad_attr_2_input_disable_2_qs; + logic mio_pad_attr_2_input_disable_2_wd; + logic [1:0] mio_pad_attr_2_slew_rate_2_qs; + logic [1:0] mio_pad_attr_2_slew_rate_2_wd; + logic [3:0] mio_pad_attr_2_drive_strength_2_qs; + logic [3:0] mio_pad_attr_2_drive_strength_2_wd; + logic mio_pad_attr_3_re; + logic mio_pad_attr_3_we; + logic mio_pad_attr_3_invert_3_qs; + logic mio_pad_attr_3_invert_3_wd; + logic mio_pad_attr_3_virtual_od_en_3_qs; + logic mio_pad_attr_3_virtual_od_en_3_wd; + logic mio_pad_attr_3_pull_en_3_qs; + logic mio_pad_attr_3_pull_en_3_wd; + logic mio_pad_attr_3_pull_select_3_qs; + logic mio_pad_attr_3_pull_select_3_wd; + logic mio_pad_attr_3_keeper_en_3_qs; + logic mio_pad_attr_3_keeper_en_3_wd; + logic mio_pad_attr_3_schmitt_en_3_qs; + logic mio_pad_attr_3_schmitt_en_3_wd; + logic mio_pad_attr_3_od_en_3_qs; + logic mio_pad_attr_3_od_en_3_wd; + logic mio_pad_attr_3_input_disable_3_qs; + logic mio_pad_attr_3_input_disable_3_wd; + logic [1:0] mio_pad_attr_3_slew_rate_3_qs; + logic [1:0] mio_pad_attr_3_slew_rate_3_wd; + logic [3:0] mio_pad_attr_3_drive_strength_3_qs; + logic [3:0] mio_pad_attr_3_drive_strength_3_wd; + logic mio_pad_attr_4_re; + logic mio_pad_attr_4_we; + logic mio_pad_attr_4_invert_4_qs; + logic mio_pad_attr_4_invert_4_wd; + logic mio_pad_attr_4_virtual_od_en_4_qs; + logic mio_pad_attr_4_virtual_od_en_4_wd; + logic mio_pad_attr_4_pull_en_4_qs; + logic mio_pad_attr_4_pull_en_4_wd; + logic mio_pad_attr_4_pull_select_4_qs; + logic mio_pad_attr_4_pull_select_4_wd; + logic mio_pad_attr_4_keeper_en_4_qs; + logic mio_pad_attr_4_keeper_en_4_wd; + logic mio_pad_attr_4_schmitt_en_4_qs; + logic mio_pad_attr_4_schmitt_en_4_wd; + logic mio_pad_attr_4_od_en_4_qs; + logic mio_pad_attr_4_od_en_4_wd; + logic mio_pad_attr_4_input_disable_4_qs; + logic mio_pad_attr_4_input_disable_4_wd; + logic [1:0] mio_pad_attr_4_slew_rate_4_qs; + logic [1:0] mio_pad_attr_4_slew_rate_4_wd; + logic [3:0] mio_pad_attr_4_drive_strength_4_qs; + logic [3:0] mio_pad_attr_4_drive_strength_4_wd; + logic mio_pad_attr_5_re; + logic mio_pad_attr_5_we; + logic mio_pad_attr_5_invert_5_qs; + logic mio_pad_attr_5_invert_5_wd; + logic mio_pad_attr_5_virtual_od_en_5_qs; + logic mio_pad_attr_5_virtual_od_en_5_wd; + logic mio_pad_attr_5_pull_en_5_qs; + logic mio_pad_attr_5_pull_en_5_wd; + logic mio_pad_attr_5_pull_select_5_qs; + logic mio_pad_attr_5_pull_select_5_wd; + logic mio_pad_attr_5_keeper_en_5_qs; + logic mio_pad_attr_5_keeper_en_5_wd; + logic mio_pad_attr_5_schmitt_en_5_qs; + logic mio_pad_attr_5_schmitt_en_5_wd; + logic mio_pad_attr_5_od_en_5_qs; + logic mio_pad_attr_5_od_en_5_wd; + logic mio_pad_attr_5_input_disable_5_qs; + logic mio_pad_attr_5_input_disable_5_wd; + logic [1:0] mio_pad_attr_5_slew_rate_5_qs; + logic [1:0] mio_pad_attr_5_slew_rate_5_wd; + logic [3:0] mio_pad_attr_5_drive_strength_5_qs; + logic [3:0] mio_pad_attr_5_drive_strength_5_wd; + logic mio_pad_attr_6_re; + logic mio_pad_attr_6_we; + logic mio_pad_attr_6_invert_6_qs; + logic mio_pad_attr_6_invert_6_wd; + logic mio_pad_attr_6_virtual_od_en_6_qs; + logic mio_pad_attr_6_virtual_od_en_6_wd; + logic mio_pad_attr_6_pull_en_6_qs; + logic mio_pad_attr_6_pull_en_6_wd; + logic mio_pad_attr_6_pull_select_6_qs; + logic mio_pad_attr_6_pull_select_6_wd; + logic mio_pad_attr_6_keeper_en_6_qs; + logic mio_pad_attr_6_keeper_en_6_wd; + logic mio_pad_attr_6_schmitt_en_6_qs; + logic mio_pad_attr_6_schmitt_en_6_wd; + logic mio_pad_attr_6_od_en_6_qs; + logic mio_pad_attr_6_od_en_6_wd; + logic mio_pad_attr_6_input_disable_6_qs; + logic mio_pad_attr_6_input_disable_6_wd; + logic [1:0] mio_pad_attr_6_slew_rate_6_qs; + logic [1:0] mio_pad_attr_6_slew_rate_6_wd; + logic [3:0] mio_pad_attr_6_drive_strength_6_qs; + logic [3:0] mio_pad_attr_6_drive_strength_6_wd; + logic mio_pad_attr_7_re; + logic mio_pad_attr_7_we; + logic mio_pad_attr_7_invert_7_qs; + logic mio_pad_attr_7_invert_7_wd; + logic mio_pad_attr_7_virtual_od_en_7_qs; + logic mio_pad_attr_7_virtual_od_en_7_wd; + logic mio_pad_attr_7_pull_en_7_qs; + logic mio_pad_attr_7_pull_en_7_wd; + logic mio_pad_attr_7_pull_select_7_qs; + logic mio_pad_attr_7_pull_select_7_wd; + logic mio_pad_attr_7_keeper_en_7_qs; + logic mio_pad_attr_7_keeper_en_7_wd; + logic mio_pad_attr_7_schmitt_en_7_qs; + logic mio_pad_attr_7_schmitt_en_7_wd; + logic mio_pad_attr_7_od_en_7_qs; + logic mio_pad_attr_7_od_en_7_wd; + logic mio_pad_attr_7_input_disable_7_qs; + logic mio_pad_attr_7_input_disable_7_wd; + logic [1:0] mio_pad_attr_7_slew_rate_7_qs; + logic [1:0] mio_pad_attr_7_slew_rate_7_wd; + logic [3:0] mio_pad_attr_7_drive_strength_7_qs; + logic [3:0] mio_pad_attr_7_drive_strength_7_wd; + logic mio_pad_attr_8_re; + logic mio_pad_attr_8_we; + logic mio_pad_attr_8_invert_8_qs; + logic mio_pad_attr_8_invert_8_wd; + logic mio_pad_attr_8_virtual_od_en_8_qs; + logic mio_pad_attr_8_virtual_od_en_8_wd; + logic mio_pad_attr_8_pull_en_8_qs; + logic mio_pad_attr_8_pull_en_8_wd; + logic mio_pad_attr_8_pull_select_8_qs; + logic mio_pad_attr_8_pull_select_8_wd; + logic mio_pad_attr_8_keeper_en_8_qs; + logic mio_pad_attr_8_keeper_en_8_wd; + logic mio_pad_attr_8_schmitt_en_8_qs; + logic mio_pad_attr_8_schmitt_en_8_wd; + logic mio_pad_attr_8_od_en_8_qs; + logic mio_pad_attr_8_od_en_8_wd; + logic mio_pad_attr_8_input_disable_8_qs; + logic mio_pad_attr_8_input_disable_8_wd; + logic [1:0] mio_pad_attr_8_slew_rate_8_qs; + logic [1:0] mio_pad_attr_8_slew_rate_8_wd; + logic [3:0] mio_pad_attr_8_drive_strength_8_qs; + logic [3:0] mio_pad_attr_8_drive_strength_8_wd; + logic mio_pad_attr_9_re; + logic mio_pad_attr_9_we; + logic mio_pad_attr_9_invert_9_qs; + logic mio_pad_attr_9_invert_9_wd; + logic mio_pad_attr_9_virtual_od_en_9_qs; + logic mio_pad_attr_9_virtual_od_en_9_wd; + logic mio_pad_attr_9_pull_en_9_qs; + logic mio_pad_attr_9_pull_en_9_wd; + logic mio_pad_attr_9_pull_select_9_qs; + logic mio_pad_attr_9_pull_select_9_wd; + logic mio_pad_attr_9_keeper_en_9_qs; + logic mio_pad_attr_9_keeper_en_9_wd; + logic mio_pad_attr_9_schmitt_en_9_qs; + logic mio_pad_attr_9_schmitt_en_9_wd; + logic mio_pad_attr_9_od_en_9_qs; + logic mio_pad_attr_9_od_en_9_wd; + logic mio_pad_attr_9_input_disable_9_qs; + logic mio_pad_attr_9_input_disable_9_wd; + logic [1:0] mio_pad_attr_9_slew_rate_9_qs; + logic [1:0] mio_pad_attr_9_slew_rate_9_wd; + logic [3:0] mio_pad_attr_9_drive_strength_9_qs; + logic [3:0] mio_pad_attr_9_drive_strength_9_wd; + logic mio_pad_attr_10_re; + logic mio_pad_attr_10_we; + logic mio_pad_attr_10_invert_10_qs; + logic mio_pad_attr_10_invert_10_wd; + logic mio_pad_attr_10_virtual_od_en_10_qs; + logic mio_pad_attr_10_virtual_od_en_10_wd; + logic mio_pad_attr_10_pull_en_10_qs; + logic mio_pad_attr_10_pull_en_10_wd; + logic mio_pad_attr_10_pull_select_10_qs; + logic mio_pad_attr_10_pull_select_10_wd; + logic mio_pad_attr_10_keeper_en_10_qs; + logic mio_pad_attr_10_keeper_en_10_wd; + logic mio_pad_attr_10_schmitt_en_10_qs; + logic mio_pad_attr_10_schmitt_en_10_wd; + logic mio_pad_attr_10_od_en_10_qs; + logic mio_pad_attr_10_od_en_10_wd; + logic mio_pad_attr_10_input_disable_10_qs; + logic mio_pad_attr_10_input_disable_10_wd; + logic [1:0] mio_pad_attr_10_slew_rate_10_qs; + logic [1:0] mio_pad_attr_10_slew_rate_10_wd; + logic [3:0] mio_pad_attr_10_drive_strength_10_qs; + logic [3:0] mio_pad_attr_10_drive_strength_10_wd; + logic mio_pad_attr_11_re; + logic mio_pad_attr_11_we; + logic mio_pad_attr_11_invert_11_qs; + logic mio_pad_attr_11_invert_11_wd; + logic mio_pad_attr_11_virtual_od_en_11_qs; + logic mio_pad_attr_11_virtual_od_en_11_wd; + logic mio_pad_attr_11_pull_en_11_qs; + logic mio_pad_attr_11_pull_en_11_wd; + logic mio_pad_attr_11_pull_select_11_qs; + logic mio_pad_attr_11_pull_select_11_wd; + logic mio_pad_attr_11_keeper_en_11_qs; + logic mio_pad_attr_11_keeper_en_11_wd; + logic mio_pad_attr_11_schmitt_en_11_qs; + logic mio_pad_attr_11_schmitt_en_11_wd; + logic mio_pad_attr_11_od_en_11_qs; + logic mio_pad_attr_11_od_en_11_wd; + logic mio_pad_attr_11_input_disable_11_qs; + logic mio_pad_attr_11_input_disable_11_wd; + logic [1:0] mio_pad_attr_11_slew_rate_11_qs; + logic [1:0] mio_pad_attr_11_slew_rate_11_wd; + logic [3:0] mio_pad_attr_11_drive_strength_11_qs; + logic [3:0] mio_pad_attr_11_drive_strength_11_wd; + logic dio_pad_attr_regwen_0_we; + logic dio_pad_attr_regwen_0_qs; + logic dio_pad_attr_regwen_0_wd; + logic dio_pad_attr_regwen_1_we; + logic dio_pad_attr_regwen_1_qs; + logic dio_pad_attr_regwen_1_wd; + logic dio_pad_attr_regwen_2_we; + logic dio_pad_attr_regwen_2_qs; + logic dio_pad_attr_regwen_2_wd; + logic dio_pad_attr_regwen_3_we; + logic dio_pad_attr_regwen_3_qs; + logic dio_pad_attr_regwen_3_wd; + logic dio_pad_attr_regwen_4_we; + logic dio_pad_attr_regwen_4_qs; + logic dio_pad_attr_regwen_4_wd; + logic dio_pad_attr_regwen_5_we; + logic dio_pad_attr_regwen_5_qs; + logic dio_pad_attr_regwen_5_wd; + logic dio_pad_attr_regwen_6_we; + logic dio_pad_attr_regwen_6_qs; + logic dio_pad_attr_regwen_6_wd; + logic dio_pad_attr_regwen_7_we; + logic dio_pad_attr_regwen_7_qs; + logic dio_pad_attr_regwen_7_wd; + logic dio_pad_attr_regwen_8_we; + logic dio_pad_attr_regwen_8_qs; + logic dio_pad_attr_regwen_8_wd; + logic dio_pad_attr_regwen_9_we; + logic dio_pad_attr_regwen_9_qs; + logic dio_pad_attr_regwen_9_wd; + logic dio_pad_attr_regwen_10_we; + logic dio_pad_attr_regwen_10_qs; + logic dio_pad_attr_regwen_10_wd; + logic dio_pad_attr_regwen_11_we; + logic dio_pad_attr_regwen_11_qs; + logic dio_pad_attr_regwen_11_wd; + logic dio_pad_attr_regwen_12_we; + logic dio_pad_attr_regwen_12_qs; + logic dio_pad_attr_regwen_12_wd; + logic dio_pad_attr_regwen_13_we; + logic dio_pad_attr_regwen_13_qs; + logic dio_pad_attr_regwen_13_wd; + logic dio_pad_attr_regwen_14_we; + logic dio_pad_attr_regwen_14_qs; + logic dio_pad_attr_regwen_14_wd; + logic dio_pad_attr_regwen_15_we; + logic dio_pad_attr_regwen_15_qs; + logic dio_pad_attr_regwen_15_wd; + logic dio_pad_attr_regwen_16_we; + logic dio_pad_attr_regwen_16_qs; + logic dio_pad_attr_regwen_16_wd; + logic dio_pad_attr_regwen_17_we; + logic dio_pad_attr_regwen_17_qs; + logic dio_pad_attr_regwen_17_wd; + logic dio_pad_attr_regwen_18_we; + logic dio_pad_attr_regwen_18_qs; + logic dio_pad_attr_regwen_18_wd; + logic dio_pad_attr_regwen_19_we; + logic dio_pad_attr_regwen_19_qs; + logic dio_pad_attr_regwen_19_wd; + logic dio_pad_attr_regwen_20_we; + logic dio_pad_attr_regwen_20_qs; + logic dio_pad_attr_regwen_20_wd; + logic dio_pad_attr_regwen_21_we; + logic dio_pad_attr_regwen_21_qs; + logic dio_pad_attr_regwen_21_wd; + logic dio_pad_attr_regwen_22_we; + logic dio_pad_attr_regwen_22_qs; + logic dio_pad_attr_regwen_22_wd; + logic dio_pad_attr_regwen_23_we; + logic dio_pad_attr_regwen_23_qs; + logic dio_pad_attr_regwen_23_wd; + logic dio_pad_attr_regwen_24_we; + logic dio_pad_attr_regwen_24_qs; + logic dio_pad_attr_regwen_24_wd; + logic dio_pad_attr_regwen_25_we; + logic dio_pad_attr_regwen_25_qs; + logic dio_pad_attr_regwen_25_wd; + logic dio_pad_attr_regwen_26_we; + logic dio_pad_attr_regwen_26_qs; + logic dio_pad_attr_regwen_26_wd; + logic dio_pad_attr_regwen_27_we; + logic dio_pad_attr_regwen_27_qs; + logic dio_pad_attr_regwen_27_wd; + logic dio_pad_attr_regwen_28_we; + logic dio_pad_attr_regwen_28_qs; + logic dio_pad_attr_regwen_28_wd; + logic dio_pad_attr_regwen_29_we; + logic dio_pad_attr_regwen_29_qs; + logic dio_pad_attr_regwen_29_wd; + logic dio_pad_attr_regwen_30_we; + logic dio_pad_attr_regwen_30_qs; + logic dio_pad_attr_regwen_30_wd; + logic dio_pad_attr_regwen_31_we; + logic dio_pad_attr_regwen_31_qs; + logic dio_pad_attr_regwen_31_wd; + logic dio_pad_attr_regwen_32_we; + logic dio_pad_attr_regwen_32_qs; + logic dio_pad_attr_regwen_32_wd; + logic dio_pad_attr_regwen_33_we; + logic dio_pad_attr_regwen_33_qs; + logic dio_pad_attr_regwen_33_wd; + logic dio_pad_attr_regwen_34_we; + logic dio_pad_attr_regwen_34_qs; + logic dio_pad_attr_regwen_34_wd; + logic dio_pad_attr_regwen_35_we; + logic dio_pad_attr_regwen_35_qs; + logic dio_pad_attr_regwen_35_wd; + logic dio_pad_attr_regwen_36_we; + logic dio_pad_attr_regwen_36_qs; + logic dio_pad_attr_regwen_36_wd; + logic dio_pad_attr_regwen_37_we; + logic dio_pad_attr_regwen_37_qs; + logic dio_pad_attr_regwen_37_wd; + logic dio_pad_attr_regwen_38_we; + logic dio_pad_attr_regwen_38_qs; + logic dio_pad_attr_regwen_38_wd; + logic dio_pad_attr_regwen_39_we; + logic dio_pad_attr_regwen_39_qs; + logic dio_pad_attr_regwen_39_wd; + logic dio_pad_attr_regwen_40_we; + logic dio_pad_attr_regwen_40_qs; + logic dio_pad_attr_regwen_40_wd; + logic dio_pad_attr_regwen_41_we; + logic dio_pad_attr_regwen_41_qs; + logic dio_pad_attr_regwen_41_wd; + logic dio_pad_attr_regwen_42_we; + logic dio_pad_attr_regwen_42_qs; + logic dio_pad_attr_regwen_42_wd; + logic dio_pad_attr_regwen_43_we; + logic dio_pad_attr_regwen_43_qs; + logic dio_pad_attr_regwen_43_wd; + logic dio_pad_attr_regwen_44_we; + logic dio_pad_attr_regwen_44_qs; + logic dio_pad_attr_regwen_44_wd; + logic dio_pad_attr_regwen_45_we; + logic dio_pad_attr_regwen_45_qs; + logic dio_pad_attr_regwen_45_wd; + logic dio_pad_attr_regwen_46_we; + logic dio_pad_attr_regwen_46_qs; + logic dio_pad_attr_regwen_46_wd; + logic dio_pad_attr_regwen_47_we; + logic dio_pad_attr_regwen_47_qs; + logic dio_pad_attr_regwen_47_wd; + logic dio_pad_attr_regwen_48_we; + logic dio_pad_attr_regwen_48_qs; + logic dio_pad_attr_regwen_48_wd; + logic dio_pad_attr_regwen_49_we; + logic dio_pad_attr_regwen_49_qs; + logic dio_pad_attr_regwen_49_wd; + logic dio_pad_attr_regwen_50_we; + logic dio_pad_attr_regwen_50_qs; + logic dio_pad_attr_regwen_50_wd; + logic dio_pad_attr_regwen_51_we; + logic dio_pad_attr_regwen_51_qs; + logic dio_pad_attr_regwen_51_wd; + logic dio_pad_attr_regwen_52_we; + logic dio_pad_attr_regwen_52_qs; + logic dio_pad_attr_regwen_52_wd; + logic dio_pad_attr_regwen_53_we; + logic dio_pad_attr_regwen_53_qs; + logic dio_pad_attr_regwen_53_wd; + logic dio_pad_attr_regwen_54_we; + logic dio_pad_attr_regwen_54_qs; + logic dio_pad_attr_regwen_54_wd; + logic dio_pad_attr_regwen_55_we; + logic dio_pad_attr_regwen_55_qs; + logic dio_pad_attr_regwen_55_wd; + logic dio_pad_attr_regwen_56_we; + logic dio_pad_attr_regwen_56_qs; + logic dio_pad_attr_regwen_56_wd; + logic dio_pad_attr_regwen_57_we; + logic dio_pad_attr_regwen_57_qs; + logic dio_pad_attr_regwen_57_wd; + logic dio_pad_attr_regwen_58_we; + logic dio_pad_attr_regwen_58_qs; + logic dio_pad_attr_regwen_58_wd; + logic dio_pad_attr_regwen_59_we; + logic dio_pad_attr_regwen_59_qs; + logic dio_pad_attr_regwen_59_wd; + logic dio_pad_attr_regwen_60_we; + logic dio_pad_attr_regwen_60_qs; + logic dio_pad_attr_regwen_60_wd; + logic dio_pad_attr_regwen_61_we; + logic dio_pad_attr_regwen_61_qs; + logic dio_pad_attr_regwen_61_wd; + logic dio_pad_attr_regwen_62_we; + logic dio_pad_attr_regwen_62_qs; + logic dio_pad_attr_regwen_62_wd; + logic dio_pad_attr_regwen_63_we; + logic dio_pad_attr_regwen_63_qs; + logic dio_pad_attr_regwen_63_wd; + logic dio_pad_attr_regwen_64_we; + logic dio_pad_attr_regwen_64_qs; + logic dio_pad_attr_regwen_64_wd; + logic dio_pad_attr_regwen_65_we; + logic dio_pad_attr_regwen_65_qs; + logic dio_pad_attr_regwen_65_wd; + logic dio_pad_attr_regwen_66_we; + logic dio_pad_attr_regwen_66_qs; + logic dio_pad_attr_regwen_66_wd; + logic dio_pad_attr_regwen_67_we; + logic dio_pad_attr_regwen_67_qs; + logic dio_pad_attr_regwen_67_wd; + logic dio_pad_attr_regwen_68_we; + logic dio_pad_attr_regwen_68_qs; + logic dio_pad_attr_regwen_68_wd; + logic dio_pad_attr_regwen_69_we; + logic dio_pad_attr_regwen_69_qs; + logic dio_pad_attr_regwen_69_wd; + logic dio_pad_attr_regwen_70_we; + logic dio_pad_attr_regwen_70_qs; + logic dio_pad_attr_regwen_70_wd; + logic dio_pad_attr_regwen_71_we; + logic dio_pad_attr_regwen_71_qs; + logic dio_pad_attr_regwen_71_wd; + logic dio_pad_attr_regwen_72_we; + logic dio_pad_attr_regwen_72_qs; + logic dio_pad_attr_regwen_72_wd; + logic dio_pad_attr_0_re; + logic dio_pad_attr_0_we; + logic dio_pad_attr_0_invert_0_qs; + logic dio_pad_attr_0_invert_0_wd; + logic dio_pad_attr_0_virtual_od_en_0_qs; + logic dio_pad_attr_0_virtual_od_en_0_wd; + logic dio_pad_attr_0_pull_en_0_qs; + logic dio_pad_attr_0_pull_en_0_wd; + logic dio_pad_attr_0_pull_select_0_qs; + logic dio_pad_attr_0_pull_select_0_wd; + logic dio_pad_attr_0_keeper_en_0_qs; + logic dio_pad_attr_0_keeper_en_0_wd; + logic dio_pad_attr_0_schmitt_en_0_qs; + logic dio_pad_attr_0_schmitt_en_0_wd; + logic dio_pad_attr_0_od_en_0_qs; + logic dio_pad_attr_0_od_en_0_wd; + logic dio_pad_attr_0_input_disable_0_qs; + logic dio_pad_attr_0_input_disable_0_wd; + logic [1:0] dio_pad_attr_0_slew_rate_0_qs; + logic [1:0] dio_pad_attr_0_slew_rate_0_wd; + logic [3:0] dio_pad_attr_0_drive_strength_0_qs; + logic [3:0] dio_pad_attr_0_drive_strength_0_wd; + logic dio_pad_attr_1_re; + logic dio_pad_attr_1_we; + logic dio_pad_attr_1_invert_1_qs; + logic dio_pad_attr_1_invert_1_wd; + logic dio_pad_attr_1_virtual_od_en_1_qs; + logic dio_pad_attr_1_virtual_od_en_1_wd; + logic dio_pad_attr_1_pull_en_1_qs; + logic dio_pad_attr_1_pull_en_1_wd; + logic dio_pad_attr_1_pull_select_1_qs; + logic dio_pad_attr_1_pull_select_1_wd; + logic dio_pad_attr_1_keeper_en_1_qs; + logic dio_pad_attr_1_keeper_en_1_wd; + logic dio_pad_attr_1_schmitt_en_1_qs; + logic dio_pad_attr_1_schmitt_en_1_wd; + logic dio_pad_attr_1_od_en_1_qs; + logic dio_pad_attr_1_od_en_1_wd; + logic dio_pad_attr_1_input_disable_1_qs; + logic dio_pad_attr_1_input_disable_1_wd; + logic [1:0] dio_pad_attr_1_slew_rate_1_qs; + logic [1:0] dio_pad_attr_1_slew_rate_1_wd; + logic [3:0] dio_pad_attr_1_drive_strength_1_qs; + logic [3:0] dio_pad_attr_1_drive_strength_1_wd; + logic dio_pad_attr_2_re; + logic dio_pad_attr_2_we; + logic dio_pad_attr_2_invert_2_qs; + logic dio_pad_attr_2_invert_2_wd; + logic dio_pad_attr_2_virtual_od_en_2_qs; + logic dio_pad_attr_2_virtual_od_en_2_wd; + logic dio_pad_attr_2_pull_en_2_qs; + logic dio_pad_attr_2_pull_en_2_wd; + logic dio_pad_attr_2_pull_select_2_qs; + logic dio_pad_attr_2_pull_select_2_wd; + logic dio_pad_attr_2_keeper_en_2_qs; + logic dio_pad_attr_2_keeper_en_2_wd; + logic dio_pad_attr_2_schmitt_en_2_qs; + logic dio_pad_attr_2_schmitt_en_2_wd; + logic dio_pad_attr_2_od_en_2_qs; + logic dio_pad_attr_2_od_en_2_wd; + logic dio_pad_attr_2_input_disable_2_qs; + logic dio_pad_attr_2_input_disable_2_wd; + logic [1:0] dio_pad_attr_2_slew_rate_2_qs; + logic [1:0] dio_pad_attr_2_slew_rate_2_wd; + logic [3:0] dio_pad_attr_2_drive_strength_2_qs; + logic [3:0] dio_pad_attr_2_drive_strength_2_wd; + logic dio_pad_attr_3_re; + logic dio_pad_attr_3_we; + logic dio_pad_attr_3_invert_3_qs; + logic dio_pad_attr_3_invert_3_wd; + logic dio_pad_attr_3_virtual_od_en_3_qs; + logic dio_pad_attr_3_virtual_od_en_3_wd; + logic dio_pad_attr_3_pull_en_3_qs; + logic dio_pad_attr_3_pull_en_3_wd; + logic dio_pad_attr_3_pull_select_3_qs; + logic dio_pad_attr_3_pull_select_3_wd; + logic dio_pad_attr_3_keeper_en_3_qs; + logic dio_pad_attr_3_keeper_en_3_wd; + logic dio_pad_attr_3_schmitt_en_3_qs; + logic dio_pad_attr_3_schmitt_en_3_wd; + logic dio_pad_attr_3_od_en_3_qs; + logic dio_pad_attr_3_od_en_3_wd; + logic dio_pad_attr_3_input_disable_3_qs; + logic dio_pad_attr_3_input_disable_3_wd; + logic [1:0] dio_pad_attr_3_slew_rate_3_qs; + logic [1:0] dio_pad_attr_3_slew_rate_3_wd; + logic [3:0] dio_pad_attr_3_drive_strength_3_qs; + logic [3:0] dio_pad_attr_3_drive_strength_3_wd; + logic dio_pad_attr_4_re; + logic dio_pad_attr_4_we; + logic dio_pad_attr_4_invert_4_qs; + logic dio_pad_attr_4_invert_4_wd; + logic dio_pad_attr_4_virtual_od_en_4_qs; + logic dio_pad_attr_4_virtual_od_en_4_wd; + logic dio_pad_attr_4_pull_en_4_qs; + logic dio_pad_attr_4_pull_en_4_wd; + logic dio_pad_attr_4_pull_select_4_qs; + logic dio_pad_attr_4_pull_select_4_wd; + logic dio_pad_attr_4_keeper_en_4_qs; + logic dio_pad_attr_4_keeper_en_4_wd; + logic dio_pad_attr_4_schmitt_en_4_qs; + logic dio_pad_attr_4_schmitt_en_4_wd; + logic dio_pad_attr_4_od_en_4_qs; + logic dio_pad_attr_4_od_en_4_wd; + logic dio_pad_attr_4_input_disable_4_qs; + logic dio_pad_attr_4_input_disable_4_wd; + logic [1:0] dio_pad_attr_4_slew_rate_4_qs; + logic [1:0] dio_pad_attr_4_slew_rate_4_wd; + logic [3:0] dio_pad_attr_4_drive_strength_4_qs; + logic [3:0] dio_pad_attr_4_drive_strength_4_wd; + logic dio_pad_attr_5_re; + logic dio_pad_attr_5_we; + logic dio_pad_attr_5_invert_5_qs; + logic dio_pad_attr_5_invert_5_wd; + logic dio_pad_attr_5_virtual_od_en_5_qs; + logic dio_pad_attr_5_virtual_od_en_5_wd; + logic dio_pad_attr_5_pull_en_5_qs; + logic dio_pad_attr_5_pull_en_5_wd; + logic dio_pad_attr_5_pull_select_5_qs; + logic dio_pad_attr_5_pull_select_5_wd; + logic dio_pad_attr_5_keeper_en_5_qs; + logic dio_pad_attr_5_keeper_en_5_wd; + logic dio_pad_attr_5_schmitt_en_5_qs; + logic dio_pad_attr_5_schmitt_en_5_wd; + logic dio_pad_attr_5_od_en_5_qs; + logic dio_pad_attr_5_od_en_5_wd; + logic dio_pad_attr_5_input_disable_5_qs; + logic dio_pad_attr_5_input_disable_5_wd; + logic [1:0] dio_pad_attr_5_slew_rate_5_qs; + logic [1:0] dio_pad_attr_5_slew_rate_5_wd; + logic [3:0] dio_pad_attr_5_drive_strength_5_qs; + logic [3:0] dio_pad_attr_5_drive_strength_5_wd; + logic dio_pad_attr_6_re; + logic dio_pad_attr_6_we; + logic dio_pad_attr_6_invert_6_qs; + logic dio_pad_attr_6_invert_6_wd; + logic dio_pad_attr_6_virtual_od_en_6_qs; + logic dio_pad_attr_6_virtual_od_en_6_wd; + logic dio_pad_attr_6_pull_en_6_qs; + logic dio_pad_attr_6_pull_en_6_wd; + logic dio_pad_attr_6_pull_select_6_qs; + logic dio_pad_attr_6_pull_select_6_wd; + logic dio_pad_attr_6_keeper_en_6_qs; + logic dio_pad_attr_6_keeper_en_6_wd; + logic dio_pad_attr_6_schmitt_en_6_qs; + logic dio_pad_attr_6_schmitt_en_6_wd; + logic dio_pad_attr_6_od_en_6_qs; + logic dio_pad_attr_6_od_en_6_wd; + logic dio_pad_attr_6_input_disable_6_qs; + logic dio_pad_attr_6_input_disable_6_wd; + logic [1:0] dio_pad_attr_6_slew_rate_6_qs; + logic [1:0] dio_pad_attr_6_slew_rate_6_wd; + logic [3:0] dio_pad_attr_6_drive_strength_6_qs; + logic [3:0] dio_pad_attr_6_drive_strength_6_wd; + logic dio_pad_attr_7_re; + logic dio_pad_attr_7_we; + logic dio_pad_attr_7_invert_7_qs; + logic dio_pad_attr_7_invert_7_wd; + logic dio_pad_attr_7_virtual_od_en_7_qs; + logic dio_pad_attr_7_virtual_od_en_7_wd; + logic dio_pad_attr_7_pull_en_7_qs; + logic dio_pad_attr_7_pull_en_7_wd; + logic dio_pad_attr_7_pull_select_7_qs; + logic dio_pad_attr_7_pull_select_7_wd; + logic dio_pad_attr_7_keeper_en_7_qs; + logic dio_pad_attr_7_keeper_en_7_wd; + logic dio_pad_attr_7_schmitt_en_7_qs; + logic dio_pad_attr_7_schmitt_en_7_wd; + logic dio_pad_attr_7_od_en_7_qs; + logic dio_pad_attr_7_od_en_7_wd; + logic dio_pad_attr_7_input_disable_7_qs; + logic dio_pad_attr_7_input_disable_7_wd; + logic [1:0] dio_pad_attr_7_slew_rate_7_qs; + logic [1:0] dio_pad_attr_7_slew_rate_7_wd; + logic [3:0] dio_pad_attr_7_drive_strength_7_qs; + logic [3:0] dio_pad_attr_7_drive_strength_7_wd; + logic dio_pad_attr_8_re; + logic dio_pad_attr_8_we; + logic dio_pad_attr_8_invert_8_qs; + logic dio_pad_attr_8_invert_8_wd; + logic dio_pad_attr_8_virtual_od_en_8_qs; + logic dio_pad_attr_8_virtual_od_en_8_wd; + logic dio_pad_attr_8_pull_en_8_qs; + logic dio_pad_attr_8_pull_en_8_wd; + logic dio_pad_attr_8_pull_select_8_qs; + logic dio_pad_attr_8_pull_select_8_wd; + logic dio_pad_attr_8_keeper_en_8_qs; + logic dio_pad_attr_8_keeper_en_8_wd; + logic dio_pad_attr_8_schmitt_en_8_qs; + logic dio_pad_attr_8_schmitt_en_8_wd; + logic dio_pad_attr_8_od_en_8_qs; + logic dio_pad_attr_8_od_en_8_wd; + logic dio_pad_attr_8_input_disable_8_qs; + logic dio_pad_attr_8_input_disable_8_wd; + logic [1:0] dio_pad_attr_8_slew_rate_8_qs; + logic [1:0] dio_pad_attr_8_slew_rate_8_wd; + logic [3:0] dio_pad_attr_8_drive_strength_8_qs; + logic [3:0] dio_pad_attr_8_drive_strength_8_wd; + logic dio_pad_attr_9_re; + logic dio_pad_attr_9_we; + logic dio_pad_attr_9_invert_9_qs; + logic dio_pad_attr_9_invert_9_wd; + logic dio_pad_attr_9_virtual_od_en_9_qs; + logic dio_pad_attr_9_virtual_od_en_9_wd; + logic dio_pad_attr_9_pull_en_9_qs; + logic dio_pad_attr_9_pull_en_9_wd; + logic dio_pad_attr_9_pull_select_9_qs; + logic dio_pad_attr_9_pull_select_9_wd; + logic dio_pad_attr_9_keeper_en_9_qs; + logic dio_pad_attr_9_keeper_en_9_wd; + logic dio_pad_attr_9_schmitt_en_9_qs; + logic dio_pad_attr_9_schmitt_en_9_wd; + logic dio_pad_attr_9_od_en_9_qs; + logic dio_pad_attr_9_od_en_9_wd; + logic dio_pad_attr_9_input_disable_9_qs; + logic dio_pad_attr_9_input_disable_9_wd; + logic [1:0] dio_pad_attr_9_slew_rate_9_qs; + logic [1:0] dio_pad_attr_9_slew_rate_9_wd; + logic [3:0] dio_pad_attr_9_drive_strength_9_qs; + logic [3:0] dio_pad_attr_9_drive_strength_9_wd; + logic dio_pad_attr_10_re; + logic dio_pad_attr_10_we; + logic dio_pad_attr_10_invert_10_qs; + logic dio_pad_attr_10_invert_10_wd; + logic dio_pad_attr_10_virtual_od_en_10_qs; + logic dio_pad_attr_10_virtual_od_en_10_wd; + logic dio_pad_attr_10_pull_en_10_qs; + logic dio_pad_attr_10_pull_en_10_wd; + logic dio_pad_attr_10_pull_select_10_qs; + logic dio_pad_attr_10_pull_select_10_wd; + logic dio_pad_attr_10_keeper_en_10_qs; + logic dio_pad_attr_10_keeper_en_10_wd; + logic dio_pad_attr_10_schmitt_en_10_qs; + logic dio_pad_attr_10_schmitt_en_10_wd; + logic dio_pad_attr_10_od_en_10_qs; + logic dio_pad_attr_10_od_en_10_wd; + logic dio_pad_attr_10_input_disable_10_qs; + logic dio_pad_attr_10_input_disable_10_wd; + logic [1:0] dio_pad_attr_10_slew_rate_10_qs; + logic [1:0] dio_pad_attr_10_slew_rate_10_wd; + logic [3:0] dio_pad_attr_10_drive_strength_10_qs; + logic [3:0] dio_pad_attr_10_drive_strength_10_wd; + logic dio_pad_attr_11_re; + logic dio_pad_attr_11_we; + logic dio_pad_attr_11_invert_11_qs; + logic dio_pad_attr_11_invert_11_wd; + logic dio_pad_attr_11_virtual_od_en_11_qs; + logic dio_pad_attr_11_virtual_od_en_11_wd; + logic dio_pad_attr_11_pull_en_11_qs; + logic dio_pad_attr_11_pull_en_11_wd; + logic dio_pad_attr_11_pull_select_11_qs; + logic dio_pad_attr_11_pull_select_11_wd; + logic dio_pad_attr_11_keeper_en_11_qs; + logic dio_pad_attr_11_keeper_en_11_wd; + logic dio_pad_attr_11_schmitt_en_11_qs; + logic dio_pad_attr_11_schmitt_en_11_wd; + logic dio_pad_attr_11_od_en_11_qs; + logic dio_pad_attr_11_od_en_11_wd; + logic dio_pad_attr_11_input_disable_11_qs; + logic dio_pad_attr_11_input_disable_11_wd; + logic [1:0] dio_pad_attr_11_slew_rate_11_qs; + logic [1:0] dio_pad_attr_11_slew_rate_11_wd; + logic [3:0] dio_pad_attr_11_drive_strength_11_qs; + logic [3:0] dio_pad_attr_11_drive_strength_11_wd; + logic dio_pad_attr_12_re; + logic dio_pad_attr_12_we; + logic dio_pad_attr_12_invert_12_qs; + logic dio_pad_attr_12_invert_12_wd; + logic dio_pad_attr_12_virtual_od_en_12_qs; + logic dio_pad_attr_12_virtual_od_en_12_wd; + logic dio_pad_attr_12_pull_en_12_qs; + logic dio_pad_attr_12_pull_en_12_wd; + logic dio_pad_attr_12_pull_select_12_qs; + logic dio_pad_attr_12_pull_select_12_wd; + logic dio_pad_attr_12_keeper_en_12_qs; + logic dio_pad_attr_12_keeper_en_12_wd; + logic dio_pad_attr_12_schmitt_en_12_qs; + logic dio_pad_attr_12_schmitt_en_12_wd; + logic dio_pad_attr_12_od_en_12_qs; + logic dio_pad_attr_12_od_en_12_wd; + logic dio_pad_attr_12_input_disable_12_qs; + logic dio_pad_attr_12_input_disable_12_wd; + logic [1:0] dio_pad_attr_12_slew_rate_12_qs; + logic [1:0] dio_pad_attr_12_slew_rate_12_wd; + logic [3:0] dio_pad_attr_12_drive_strength_12_qs; + logic [3:0] dio_pad_attr_12_drive_strength_12_wd; + logic dio_pad_attr_13_re; + logic dio_pad_attr_13_we; + logic dio_pad_attr_13_invert_13_qs; + logic dio_pad_attr_13_invert_13_wd; + logic dio_pad_attr_13_virtual_od_en_13_qs; + logic dio_pad_attr_13_virtual_od_en_13_wd; + logic dio_pad_attr_13_pull_en_13_qs; + logic dio_pad_attr_13_pull_en_13_wd; + logic dio_pad_attr_13_pull_select_13_qs; + logic dio_pad_attr_13_pull_select_13_wd; + logic dio_pad_attr_13_keeper_en_13_qs; + logic dio_pad_attr_13_keeper_en_13_wd; + logic dio_pad_attr_13_schmitt_en_13_qs; + logic dio_pad_attr_13_schmitt_en_13_wd; + logic dio_pad_attr_13_od_en_13_qs; + logic dio_pad_attr_13_od_en_13_wd; + logic dio_pad_attr_13_input_disable_13_qs; + logic dio_pad_attr_13_input_disable_13_wd; + logic [1:0] dio_pad_attr_13_slew_rate_13_qs; + logic [1:0] dio_pad_attr_13_slew_rate_13_wd; + logic [3:0] dio_pad_attr_13_drive_strength_13_qs; + logic [3:0] dio_pad_attr_13_drive_strength_13_wd; + logic dio_pad_attr_14_re; + logic dio_pad_attr_14_we; + logic dio_pad_attr_14_invert_14_qs; + logic dio_pad_attr_14_invert_14_wd; + logic dio_pad_attr_14_virtual_od_en_14_qs; + logic dio_pad_attr_14_virtual_od_en_14_wd; + logic dio_pad_attr_14_pull_en_14_qs; + logic dio_pad_attr_14_pull_en_14_wd; + logic dio_pad_attr_14_pull_select_14_qs; + logic dio_pad_attr_14_pull_select_14_wd; + logic dio_pad_attr_14_keeper_en_14_qs; + logic dio_pad_attr_14_keeper_en_14_wd; + logic dio_pad_attr_14_schmitt_en_14_qs; + logic dio_pad_attr_14_schmitt_en_14_wd; + logic dio_pad_attr_14_od_en_14_qs; + logic dio_pad_attr_14_od_en_14_wd; + logic dio_pad_attr_14_input_disable_14_qs; + logic dio_pad_attr_14_input_disable_14_wd; + logic [1:0] dio_pad_attr_14_slew_rate_14_qs; + logic [1:0] dio_pad_attr_14_slew_rate_14_wd; + logic [3:0] dio_pad_attr_14_drive_strength_14_qs; + logic [3:0] dio_pad_attr_14_drive_strength_14_wd; + logic dio_pad_attr_15_re; + logic dio_pad_attr_15_we; + logic dio_pad_attr_15_invert_15_qs; + logic dio_pad_attr_15_invert_15_wd; + logic dio_pad_attr_15_virtual_od_en_15_qs; + logic dio_pad_attr_15_virtual_od_en_15_wd; + logic dio_pad_attr_15_pull_en_15_qs; + logic dio_pad_attr_15_pull_en_15_wd; + logic dio_pad_attr_15_pull_select_15_qs; + logic dio_pad_attr_15_pull_select_15_wd; + logic dio_pad_attr_15_keeper_en_15_qs; + logic dio_pad_attr_15_keeper_en_15_wd; + logic dio_pad_attr_15_schmitt_en_15_qs; + logic dio_pad_attr_15_schmitt_en_15_wd; + logic dio_pad_attr_15_od_en_15_qs; + logic dio_pad_attr_15_od_en_15_wd; + logic dio_pad_attr_15_input_disable_15_qs; + logic dio_pad_attr_15_input_disable_15_wd; + logic [1:0] dio_pad_attr_15_slew_rate_15_qs; + logic [1:0] dio_pad_attr_15_slew_rate_15_wd; + logic [3:0] dio_pad_attr_15_drive_strength_15_qs; + logic [3:0] dio_pad_attr_15_drive_strength_15_wd; + logic dio_pad_attr_16_re; + logic dio_pad_attr_16_we; + logic dio_pad_attr_16_invert_16_qs; + logic dio_pad_attr_16_invert_16_wd; + logic dio_pad_attr_16_virtual_od_en_16_qs; + logic dio_pad_attr_16_virtual_od_en_16_wd; + logic dio_pad_attr_16_pull_en_16_qs; + logic dio_pad_attr_16_pull_en_16_wd; + logic dio_pad_attr_16_pull_select_16_qs; + logic dio_pad_attr_16_pull_select_16_wd; + logic dio_pad_attr_16_keeper_en_16_qs; + logic dio_pad_attr_16_keeper_en_16_wd; + logic dio_pad_attr_16_schmitt_en_16_qs; + logic dio_pad_attr_16_schmitt_en_16_wd; + logic dio_pad_attr_16_od_en_16_qs; + logic dio_pad_attr_16_od_en_16_wd; + logic dio_pad_attr_16_input_disable_16_qs; + logic dio_pad_attr_16_input_disable_16_wd; + logic [1:0] dio_pad_attr_16_slew_rate_16_qs; + logic [1:0] dio_pad_attr_16_slew_rate_16_wd; + logic [3:0] dio_pad_attr_16_drive_strength_16_qs; + logic [3:0] dio_pad_attr_16_drive_strength_16_wd; + logic dio_pad_attr_17_re; + logic dio_pad_attr_17_we; + logic dio_pad_attr_17_invert_17_qs; + logic dio_pad_attr_17_invert_17_wd; + logic dio_pad_attr_17_virtual_od_en_17_qs; + logic dio_pad_attr_17_virtual_od_en_17_wd; + logic dio_pad_attr_17_pull_en_17_qs; + logic dio_pad_attr_17_pull_en_17_wd; + logic dio_pad_attr_17_pull_select_17_qs; + logic dio_pad_attr_17_pull_select_17_wd; + logic dio_pad_attr_17_keeper_en_17_qs; + logic dio_pad_attr_17_keeper_en_17_wd; + logic dio_pad_attr_17_schmitt_en_17_qs; + logic dio_pad_attr_17_schmitt_en_17_wd; + logic dio_pad_attr_17_od_en_17_qs; + logic dio_pad_attr_17_od_en_17_wd; + logic dio_pad_attr_17_input_disable_17_qs; + logic dio_pad_attr_17_input_disable_17_wd; + logic [1:0] dio_pad_attr_17_slew_rate_17_qs; + logic [1:0] dio_pad_attr_17_slew_rate_17_wd; + logic [3:0] dio_pad_attr_17_drive_strength_17_qs; + logic [3:0] dio_pad_attr_17_drive_strength_17_wd; + logic dio_pad_attr_18_re; + logic dio_pad_attr_18_we; + logic dio_pad_attr_18_invert_18_qs; + logic dio_pad_attr_18_invert_18_wd; + logic dio_pad_attr_18_virtual_od_en_18_qs; + logic dio_pad_attr_18_virtual_od_en_18_wd; + logic dio_pad_attr_18_pull_en_18_qs; + logic dio_pad_attr_18_pull_en_18_wd; + logic dio_pad_attr_18_pull_select_18_qs; + logic dio_pad_attr_18_pull_select_18_wd; + logic dio_pad_attr_18_keeper_en_18_qs; + logic dio_pad_attr_18_keeper_en_18_wd; + logic dio_pad_attr_18_schmitt_en_18_qs; + logic dio_pad_attr_18_schmitt_en_18_wd; + logic dio_pad_attr_18_od_en_18_qs; + logic dio_pad_attr_18_od_en_18_wd; + logic dio_pad_attr_18_input_disable_18_qs; + logic dio_pad_attr_18_input_disable_18_wd; + logic [1:0] dio_pad_attr_18_slew_rate_18_qs; + logic [1:0] dio_pad_attr_18_slew_rate_18_wd; + logic [3:0] dio_pad_attr_18_drive_strength_18_qs; + logic [3:0] dio_pad_attr_18_drive_strength_18_wd; + logic dio_pad_attr_19_re; + logic dio_pad_attr_19_we; + logic dio_pad_attr_19_invert_19_qs; + logic dio_pad_attr_19_invert_19_wd; + logic dio_pad_attr_19_virtual_od_en_19_qs; + logic dio_pad_attr_19_virtual_od_en_19_wd; + logic dio_pad_attr_19_pull_en_19_qs; + logic dio_pad_attr_19_pull_en_19_wd; + logic dio_pad_attr_19_pull_select_19_qs; + logic dio_pad_attr_19_pull_select_19_wd; + logic dio_pad_attr_19_keeper_en_19_qs; + logic dio_pad_attr_19_keeper_en_19_wd; + logic dio_pad_attr_19_schmitt_en_19_qs; + logic dio_pad_attr_19_schmitt_en_19_wd; + logic dio_pad_attr_19_od_en_19_qs; + logic dio_pad_attr_19_od_en_19_wd; + logic dio_pad_attr_19_input_disable_19_qs; + logic dio_pad_attr_19_input_disable_19_wd; + logic [1:0] dio_pad_attr_19_slew_rate_19_qs; + logic [1:0] dio_pad_attr_19_slew_rate_19_wd; + logic [3:0] dio_pad_attr_19_drive_strength_19_qs; + logic [3:0] dio_pad_attr_19_drive_strength_19_wd; + logic dio_pad_attr_20_re; + logic dio_pad_attr_20_we; + logic dio_pad_attr_20_invert_20_qs; + logic dio_pad_attr_20_invert_20_wd; + logic dio_pad_attr_20_virtual_od_en_20_qs; + logic dio_pad_attr_20_virtual_od_en_20_wd; + logic dio_pad_attr_20_pull_en_20_qs; + logic dio_pad_attr_20_pull_en_20_wd; + logic dio_pad_attr_20_pull_select_20_qs; + logic dio_pad_attr_20_pull_select_20_wd; + logic dio_pad_attr_20_keeper_en_20_qs; + logic dio_pad_attr_20_keeper_en_20_wd; + logic dio_pad_attr_20_schmitt_en_20_qs; + logic dio_pad_attr_20_schmitt_en_20_wd; + logic dio_pad_attr_20_od_en_20_qs; + logic dio_pad_attr_20_od_en_20_wd; + logic dio_pad_attr_20_input_disable_20_qs; + logic dio_pad_attr_20_input_disable_20_wd; + logic [1:0] dio_pad_attr_20_slew_rate_20_qs; + logic [1:0] dio_pad_attr_20_slew_rate_20_wd; + logic [3:0] dio_pad_attr_20_drive_strength_20_qs; + logic [3:0] dio_pad_attr_20_drive_strength_20_wd; + logic dio_pad_attr_21_re; + logic dio_pad_attr_21_we; + logic dio_pad_attr_21_invert_21_qs; + logic dio_pad_attr_21_invert_21_wd; + logic dio_pad_attr_21_virtual_od_en_21_qs; + logic dio_pad_attr_21_virtual_od_en_21_wd; + logic dio_pad_attr_21_pull_en_21_qs; + logic dio_pad_attr_21_pull_en_21_wd; + logic dio_pad_attr_21_pull_select_21_qs; + logic dio_pad_attr_21_pull_select_21_wd; + logic dio_pad_attr_21_keeper_en_21_qs; + logic dio_pad_attr_21_keeper_en_21_wd; + logic dio_pad_attr_21_schmitt_en_21_qs; + logic dio_pad_attr_21_schmitt_en_21_wd; + logic dio_pad_attr_21_od_en_21_qs; + logic dio_pad_attr_21_od_en_21_wd; + logic dio_pad_attr_21_input_disable_21_qs; + logic dio_pad_attr_21_input_disable_21_wd; + logic [1:0] dio_pad_attr_21_slew_rate_21_qs; + logic [1:0] dio_pad_attr_21_slew_rate_21_wd; + logic [3:0] dio_pad_attr_21_drive_strength_21_qs; + logic [3:0] dio_pad_attr_21_drive_strength_21_wd; + logic dio_pad_attr_22_re; + logic dio_pad_attr_22_we; + logic dio_pad_attr_22_invert_22_qs; + logic dio_pad_attr_22_invert_22_wd; + logic dio_pad_attr_22_virtual_od_en_22_qs; + logic dio_pad_attr_22_virtual_od_en_22_wd; + logic dio_pad_attr_22_pull_en_22_qs; + logic dio_pad_attr_22_pull_en_22_wd; + logic dio_pad_attr_22_pull_select_22_qs; + logic dio_pad_attr_22_pull_select_22_wd; + logic dio_pad_attr_22_keeper_en_22_qs; + logic dio_pad_attr_22_keeper_en_22_wd; + logic dio_pad_attr_22_schmitt_en_22_qs; + logic dio_pad_attr_22_schmitt_en_22_wd; + logic dio_pad_attr_22_od_en_22_qs; + logic dio_pad_attr_22_od_en_22_wd; + logic dio_pad_attr_22_input_disable_22_qs; + logic dio_pad_attr_22_input_disable_22_wd; + logic [1:0] dio_pad_attr_22_slew_rate_22_qs; + logic [1:0] dio_pad_attr_22_slew_rate_22_wd; + logic [3:0] dio_pad_attr_22_drive_strength_22_qs; + logic [3:0] dio_pad_attr_22_drive_strength_22_wd; + logic dio_pad_attr_23_re; + logic dio_pad_attr_23_we; + logic dio_pad_attr_23_invert_23_qs; + logic dio_pad_attr_23_invert_23_wd; + logic dio_pad_attr_23_virtual_od_en_23_qs; + logic dio_pad_attr_23_virtual_od_en_23_wd; + logic dio_pad_attr_23_pull_en_23_qs; + logic dio_pad_attr_23_pull_en_23_wd; + logic dio_pad_attr_23_pull_select_23_qs; + logic dio_pad_attr_23_pull_select_23_wd; + logic dio_pad_attr_23_keeper_en_23_qs; + logic dio_pad_attr_23_keeper_en_23_wd; + logic dio_pad_attr_23_schmitt_en_23_qs; + logic dio_pad_attr_23_schmitt_en_23_wd; + logic dio_pad_attr_23_od_en_23_qs; + logic dio_pad_attr_23_od_en_23_wd; + logic dio_pad_attr_23_input_disable_23_qs; + logic dio_pad_attr_23_input_disable_23_wd; + logic [1:0] dio_pad_attr_23_slew_rate_23_qs; + logic [1:0] dio_pad_attr_23_slew_rate_23_wd; + logic [3:0] dio_pad_attr_23_drive_strength_23_qs; + logic [3:0] dio_pad_attr_23_drive_strength_23_wd; + logic dio_pad_attr_24_re; + logic dio_pad_attr_24_we; + logic dio_pad_attr_24_invert_24_qs; + logic dio_pad_attr_24_invert_24_wd; + logic dio_pad_attr_24_virtual_od_en_24_qs; + logic dio_pad_attr_24_virtual_od_en_24_wd; + logic dio_pad_attr_24_pull_en_24_qs; + logic dio_pad_attr_24_pull_en_24_wd; + logic dio_pad_attr_24_pull_select_24_qs; + logic dio_pad_attr_24_pull_select_24_wd; + logic dio_pad_attr_24_keeper_en_24_qs; + logic dio_pad_attr_24_keeper_en_24_wd; + logic dio_pad_attr_24_schmitt_en_24_qs; + logic dio_pad_attr_24_schmitt_en_24_wd; + logic dio_pad_attr_24_od_en_24_qs; + logic dio_pad_attr_24_od_en_24_wd; + logic dio_pad_attr_24_input_disable_24_qs; + logic dio_pad_attr_24_input_disable_24_wd; + logic [1:0] dio_pad_attr_24_slew_rate_24_qs; + logic [1:0] dio_pad_attr_24_slew_rate_24_wd; + logic [3:0] dio_pad_attr_24_drive_strength_24_qs; + logic [3:0] dio_pad_attr_24_drive_strength_24_wd; + logic dio_pad_attr_25_re; + logic dio_pad_attr_25_we; + logic dio_pad_attr_25_invert_25_qs; + logic dio_pad_attr_25_invert_25_wd; + logic dio_pad_attr_25_virtual_od_en_25_qs; + logic dio_pad_attr_25_virtual_od_en_25_wd; + logic dio_pad_attr_25_pull_en_25_qs; + logic dio_pad_attr_25_pull_en_25_wd; + logic dio_pad_attr_25_pull_select_25_qs; + logic dio_pad_attr_25_pull_select_25_wd; + logic dio_pad_attr_25_keeper_en_25_qs; + logic dio_pad_attr_25_keeper_en_25_wd; + logic dio_pad_attr_25_schmitt_en_25_qs; + logic dio_pad_attr_25_schmitt_en_25_wd; + logic dio_pad_attr_25_od_en_25_qs; + logic dio_pad_attr_25_od_en_25_wd; + logic dio_pad_attr_25_input_disable_25_qs; + logic dio_pad_attr_25_input_disable_25_wd; + logic [1:0] dio_pad_attr_25_slew_rate_25_qs; + logic [1:0] dio_pad_attr_25_slew_rate_25_wd; + logic [3:0] dio_pad_attr_25_drive_strength_25_qs; + logic [3:0] dio_pad_attr_25_drive_strength_25_wd; + logic dio_pad_attr_26_re; + logic dio_pad_attr_26_we; + logic dio_pad_attr_26_invert_26_qs; + logic dio_pad_attr_26_invert_26_wd; + logic dio_pad_attr_26_virtual_od_en_26_qs; + logic dio_pad_attr_26_virtual_od_en_26_wd; + logic dio_pad_attr_26_pull_en_26_qs; + logic dio_pad_attr_26_pull_en_26_wd; + logic dio_pad_attr_26_pull_select_26_qs; + logic dio_pad_attr_26_pull_select_26_wd; + logic dio_pad_attr_26_keeper_en_26_qs; + logic dio_pad_attr_26_keeper_en_26_wd; + logic dio_pad_attr_26_schmitt_en_26_qs; + logic dio_pad_attr_26_schmitt_en_26_wd; + logic dio_pad_attr_26_od_en_26_qs; + logic dio_pad_attr_26_od_en_26_wd; + logic dio_pad_attr_26_input_disable_26_qs; + logic dio_pad_attr_26_input_disable_26_wd; + logic [1:0] dio_pad_attr_26_slew_rate_26_qs; + logic [1:0] dio_pad_attr_26_slew_rate_26_wd; + logic [3:0] dio_pad_attr_26_drive_strength_26_qs; + logic [3:0] dio_pad_attr_26_drive_strength_26_wd; + logic dio_pad_attr_27_re; + logic dio_pad_attr_27_we; + logic dio_pad_attr_27_invert_27_qs; + logic dio_pad_attr_27_invert_27_wd; + logic dio_pad_attr_27_virtual_od_en_27_qs; + logic dio_pad_attr_27_virtual_od_en_27_wd; + logic dio_pad_attr_27_pull_en_27_qs; + logic dio_pad_attr_27_pull_en_27_wd; + logic dio_pad_attr_27_pull_select_27_qs; + logic dio_pad_attr_27_pull_select_27_wd; + logic dio_pad_attr_27_keeper_en_27_qs; + logic dio_pad_attr_27_keeper_en_27_wd; + logic dio_pad_attr_27_schmitt_en_27_qs; + logic dio_pad_attr_27_schmitt_en_27_wd; + logic dio_pad_attr_27_od_en_27_qs; + logic dio_pad_attr_27_od_en_27_wd; + logic dio_pad_attr_27_input_disable_27_qs; + logic dio_pad_attr_27_input_disable_27_wd; + logic [1:0] dio_pad_attr_27_slew_rate_27_qs; + logic [1:0] dio_pad_attr_27_slew_rate_27_wd; + logic [3:0] dio_pad_attr_27_drive_strength_27_qs; + logic [3:0] dio_pad_attr_27_drive_strength_27_wd; + logic dio_pad_attr_28_re; + logic dio_pad_attr_28_we; + logic dio_pad_attr_28_invert_28_qs; + logic dio_pad_attr_28_invert_28_wd; + logic dio_pad_attr_28_virtual_od_en_28_qs; + logic dio_pad_attr_28_virtual_od_en_28_wd; + logic dio_pad_attr_28_pull_en_28_qs; + logic dio_pad_attr_28_pull_en_28_wd; + logic dio_pad_attr_28_pull_select_28_qs; + logic dio_pad_attr_28_pull_select_28_wd; + logic dio_pad_attr_28_keeper_en_28_qs; + logic dio_pad_attr_28_keeper_en_28_wd; + logic dio_pad_attr_28_schmitt_en_28_qs; + logic dio_pad_attr_28_schmitt_en_28_wd; + logic dio_pad_attr_28_od_en_28_qs; + logic dio_pad_attr_28_od_en_28_wd; + logic dio_pad_attr_28_input_disable_28_qs; + logic dio_pad_attr_28_input_disable_28_wd; + logic [1:0] dio_pad_attr_28_slew_rate_28_qs; + logic [1:0] dio_pad_attr_28_slew_rate_28_wd; + logic [3:0] dio_pad_attr_28_drive_strength_28_qs; + logic [3:0] dio_pad_attr_28_drive_strength_28_wd; + logic dio_pad_attr_29_re; + logic dio_pad_attr_29_we; + logic dio_pad_attr_29_invert_29_qs; + logic dio_pad_attr_29_invert_29_wd; + logic dio_pad_attr_29_virtual_od_en_29_qs; + logic dio_pad_attr_29_virtual_od_en_29_wd; + logic dio_pad_attr_29_pull_en_29_qs; + logic dio_pad_attr_29_pull_en_29_wd; + logic dio_pad_attr_29_pull_select_29_qs; + logic dio_pad_attr_29_pull_select_29_wd; + logic dio_pad_attr_29_keeper_en_29_qs; + logic dio_pad_attr_29_keeper_en_29_wd; + logic dio_pad_attr_29_schmitt_en_29_qs; + logic dio_pad_attr_29_schmitt_en_29_wd; + logic dio_pad_attr_29_od_en_29_qs; + logic dio_pad_attr_29_od_en_29_wd; + logic dio_pad_attr_29_input_disable_29_qs; + logic dio_pad_attr_29_input_disable_29_wd; + logic [1:0] dio_pad_attr_29_slew_rate_29_qs; + logic [1:0] dio_pad_attr_29_slew_rate_29_wd; + logic [3:0] dio_pad_attr_29_drive_strength_29_qs; + logic [3:0] dio_pad_attr_29_drive_strength_29_wd; + logic dio_pad_attr_30_re; + logic dio_pad_attr_30_we; + logic dio_pad_attr_30_invert_30_qs; + logic dio_pad_attr_30_invert_30_wd; + logic dio_pad_attr_30_virtual_od_en_30_qs; + logic dio_pad_attr_30_virtual_od_en_30_wd; + logic dio_pad_attr_30_pull_en_30_qs; + logic dio_pad_attr_30_pull_en_30_wd; + logic dio_pad_attr_30_pull_select_30_qs; + logic dio_pad_attr_30_pull_select_30_wd; + logic dio_pad_attr_30_keeper_en_30_qs; + logic dio_pad_attr_30_keeper_en_30_wd; + logic dio_pad_attr_30_schmitt_en_30_qs; + logic dio_pad_attr_30_schmitt_en_30_wd; + logic dio_pad_attr_30_od_en_30_qs; + logic dio_pad_attr_30_od_en_30_wd; + logic dio_pad_attr_30_input_disable_30_qs; + logic dio_pad_attr_30_input_disable_30_wd; + logic [1:0] dio_pad_attr_30_slew_rate_30_qs; + logic [1:0] dio_pad_attr_30_slew_rate_30_wd; + logic [3:0] dio_pad_attr_30_drive_strength_30_qs; + logic [3:0] dio_pad_attr_30_drive_strength_30_wd; + logic dio_pad_attr_31_re; + logic dio_pad_attr_31_we; + logic dio_pad_attr_31_invert_31_qs; + logic dio_pad_attr_31_invert_31_wd; + logic dio_pad_attr_31_virtual_od_en_31_qs; + logic dio_pad_attr_31_virtual_od_en_31_wd; + logic dio_pad_attr_31_pull_en_31_qs; + logic dio_pad_attr_31_pull_en_31_wd; + logic dio_pad_attr_31_pull_select_31_qs; + logic dio_pad_attr_31_pull_select_31_wd; + logic dio_pad_attr_31_keeper_en_31_qs; + logic dio_pad_attr_31_keeper_en_31_wd; + logic dio_pad_attr_31_schmitt_en_31_qs; + logic dio_pad_attr_31_schmitt_en_31_wd; + logic dio_pad_attr_31_od_en_31_qs; + logic dio_pad_attr_31_od_en_31_wd; + logic dio_pad_attr_31_input_disable_31_qs; + logic dio_pad_attr_31_input_disable_31_wd; + logic [1:0] dio_pad_attr_31_slew_rate_31_qs; + logic [1:0] dio_pad_attr_31_slew_rate_31_wd; + logic [3:0] dio_pad_attr_31_drive_strength_31_qs; + logic [3:0] dio_pad_attr_31_drive_strength_31_wd; + logic dio_pad_attr_32_re; + logic dio_pad_attr_32_we; + logic dio_pad_attr_32_invert_32_qs; + logic dio_pad_attr_32_invert_32_wd; + logic dio_pad_attr_32_virtual_od_en_32_qs; + logic dio_pad_attr_32_virtual_od_en_32_wd; + logic dio_pad_attr_32_pull_en_32_qs; + logic dio_pad_attr_32_pull_en_32_wd; + logic dio_pad_attr_32_pull_select_32_qs; + logic dio_pad_attr_32_pull_select_32_wd; + logic dio_pad_attr_32_keeper_en_32_qs; + logic dio_pad_attr_32_keeper_en_32_wd; + logic dio_pad_attr_32_schmitt_en_32_qs; + logic dio_pad_attr_32_schmitt_en_32_wd; + logic dio_pad_attr_32_od_en_32_qs; + logic dio_pad_attr_32_od_en_32_wd; + logic dio_pad_attr_32_input_disable_32_qs; + logic dio_pad_attr_32_input_disable_32_wd; + logic [1:0] dio_pad_attr_32_slew_rate_32_qs; + logic [1:0] dio_pad_attr_32_slew_rate_32_wd; + logic [3:0] dio_pad_attr_32_drive_strength_32_qs; + logic [3:0] dio_pad_attr_32_drive_strength_32_wd; + logic dio_pad_attr_33_re; + logic dio_pad_attr_33_we; + logic dio_pad_attr_33_invert_33_qs; + logic dio_pad_attr_33_invert_33_wd; + logic dio_pad_attr_33_virtual_od_en_33_qs; + logic dio_pad_attr_33_virtual_od_en_33_wd; + logic dio_pad_attr_33_pull_en_33_qs; + logic dio_pad_attr_33_pull_en_33_wd; + logic dio_pad_attr_33_pull_select_33_qs; + logic dio_pad_attr_33_pull_select_33_wd; + logic dio_pad_attr_33_keeper_en_33_qs; + logic dio_pad_attr_33_keeper_en_33_wd; + logic dio_pad_attr_33_schmitt_en_33_qs; + logic dio_pad_attr_33_schmitt_en_33_wd; + logic dio_pad_attr_33_od_en_33_qs; + logic dio_pad_attr_33_od_en_33_wd; + logic dio_pad_attr_33_input_disable_33_qs; + logic dio_pad_attr_33_input_disable_33_wd; + logic [1:0] dio_pad_attr_33_slew_rate_33_qs; + logic [1:0] dio_pad_attr_33_slew_rate_33_wd; + logic [3:0] dio_pad_attr_33_drive_strength_33_qs; + logic [3:0] dio_pad_attr_33_drive_strength_33_wd; + logic dio_pad_attr_34_re; + logic dio_pad_attr_34_we; + logic dio_pad_attr_34_invert_34_qs; + logic dio_pad_attr_34_invert_34_wd; + logic dio_pad_attr_34_virtual_od_en_34_qs; + logic dio_pad_attr_34_virtual_od_en_34_wd; + logic dio_pad_attr_34_pull_en_34_qs; + logic dio_pad_attr_34_pull_en_34_wd; + logic dio_pad_attr_34_pull_select_34_qs; + logic dio_pad_attr_34_pull_select_34_wd; + logic dio_pad_attr_34_keeper_en_34_qs; + logic dio_pad_attr_34_keeper_en_34_wd; + logic dio_pad_attr_34_schmitt_en_34_qs; + logic dio_pad_attr_34_schmitt_en_34_wd; + logic dio_pad_attr_34_od_en_34_qs; + logic dio_pad_attr_34_od_en_34_wd; + logic dio_pad_attr_34_input_disable_34_qs; + logic dio_pad_attr_34_input_disable_34_wd; + logic [1:0] dio_pad_attr_34_slew_rate_34_qs; + logic [1:0] dio_pad_attr_34_slew_rate_34_wd; + logic [3:0] dio_pad_attr_34_drive_strength_34_qs; + logic [3:0] dio_pad_attr_34_drive_strength_34_wd; + logic dio_pad_attr_35_re; + logic dio_pad_attr_35_we; + logic dio_pad_attr_35_invert_35_qs; + logic dio_pad_attr_35_invert_35_wd; + logic dio_pad_attr_35_virtual_od_en_35_qs; + logic dio_pad_attr_35_virtual_od_en_35_wd; + logic dio_pad_attr_35_pull_en_35_qs; + logic dio_pad_attr_35_pull_en_35_wd; + logic dio_pad_attr_35_pull_select_35_qs; + logic dio_pad_attr_35_pull_select_35_wd; + logic dio_pad_attr_35_keeper_en_35_qs; + logic dio_pad_attr_35_keeper_en_35_wd; + logic dio_pad_attr_35_schmitt_en_35_qs; + logic dio_pad_attr_35_schmitt_en_35_wd; + logic dio_pad_attr_35_od_en_35_qs; + logic dio_pad_attr_35_od_en_35_wd; + logic dio_pad_attr_35_input_disable_35_qs; + logic dio_pad_attr_35_input_disable_35_wd; + logic [1:0] dio_pad_attr_35_slew_rate_35_qs; + logic [1:0] dio_pad_attr_35_slew_rate_35_wd; + logic [3:0] dio_pad_attr_35_drive_strength_35_qs; + logic [3:0] dio_pad_attr_35_drive_strength_35_wd; + logic dio_pad_attr_36_re; + logic dio_pad_attr_36_we; + logic dio_pad_attr_36_invert_36_qs; + logic dio_pad_attr_36_invert_36_wd; + logic dio_pad_attr_36_virtual_od_en_36_qs; + logic dio_pad_attr_36_virtual_od_en_36_wd; + logic dio_pad_attr_36_pull_en_36_qs; + logic dio_pad_attr_36_pull_en_36_wd; + logic dio_pad_attr_36_pull_select_36_qs; + logic dio_pad_attr_36_pull_select_36_wd; + logic dio_pad_attr_36_keeper_en_36_qs; + logic dio_pad_attr_36_keeper_en_36_wd; + logic dio_pad_attr_36_schmitt_en_36_qs; + logic dio_pad_attr_36_schmitt_en_36_wd; + logic dio_pad_attr_36_od_en_36_qs; + logic dio_pad_attr_36_od_en_36_wd; + logic dio_pad_attr_36_input_disable_36_qs; + logic dio_pad_attr_36_input_disable_36_wd; + logic [1:0] dio_pad_attr_36_slew_rate_36_qs; + logic [1:0] dio_pad_attr_36_slew_rate_36_wd; + logic [3:0] dio_pad_attr_36_drive_strength_36_qs; + logic [3:0] dio_pad_attr_36_drive_strength_36_wd; + logic dio_pad_attr_37_re; + logic dio_pad_attr_37_we; + logic dio_pad_attr_37_invert_37_qs; + logic dio_pad_attr_37_invert_37_wd; + logic dio_pad_attr_37_virtual_od_en_37_qs; + logic dio_pad_attr_37_virtual_od_en_37_wd; + logic dio_pad_attr_37_pull_en_37_qs; + logic dio_pad_attr_37_pull_en_37_wd; + logic dio_pad_attr_37_pull_select_37_qs; + logic dio_pad_attr_37_pull_select_37_wd; + logic dio_pad_attr_37_keeper_en_37_qs; + logic dio_pad_attr_37_keeper_en_37_wd; + logic dio_pad_attr_37_schmitt_en_37_qs; + logic dio_pad_attr_37_schmitt_en_37_wd; + logic dio_pad_attr_37_od_en_37_qs; + logic dio_pad_attr_37_od_en_37_wd; + logic dio_pad_attr_37_input_disable_37_qs; + logic dio_pad_attr_37_input_disable_37_wd; + logic [1:0] dio_pad_attr_37_slew_rate_37_qs; + logic [1:0] dio_pad_attr_37_slew_rate_37_wd; + logic [3:0] dio_pad_attr_37_drive_strength_37_qs; + logic [3:0] dio_pad_attr_37_drive_strength_37_wd; + logic dio_pad_attr_38_re; + logic dio_pad_attr_38_we; + logic dio_pad_attr_38_invert_38_qs; + logic dio_pad_attr_38_invert_38_wd; + logic dio_pad_attr_38_virtual_od_en_38_qs; + logic dio_pad_attr_38_virtual_od_en_38_wd; + logic dio_pad_attr_38_pull_en_38_qs; + logic dio_pad_attr_38_pull_en_38_wd; + logic dio_pad_attr_38_pull_select_38_qs; + logic dio_pad_attr_38_pull_select_38_wd; + logic dio_pad_attr_38_keeper_en_38_qs; + logic dio_pad_attr_38_keeper_en_38_wd; + logic dio_pad_attr_38_schmitt_en_38_qs; + logic dio_pad_attr_38_schmitt_en_38_wd; + logic dio_pad_attr_38_od_en_38_qs; + logic dio_pad_attr_38_od_en_38_wd; + logic dio_pad_attr_38_input_disable_38_qs; + logic dio_pad_attr_38_input_disable_38_wd; + logic [1:0] dio_pad_attr_38_slew_rate_38_qs; + logic [1:0] dio_pad_attr_38_slew_rate_38_wd; + logic [3:0] dio_pad_attr_38_drive_strength_38_qs; + logic [3:0] dio_pad_attr_38_drive_strength_38_wd; + logic dio_pad_attr_39_re; + logic dio_pad_attr_39_we; + logic dio_pad_attr_39_invert_39_qs; + logic dio_pad_attr_39_invert_39_wd; + logic dio_pad_attr_39_virtual_od_en_39_qs; + logic dio_pad_attr_39_virtual_od_en_39_wd; + logic dio_pad_attr_39_pull_en_39_qs; + logic dio_pad_attr_39_pull_en_39_wd; + logic dio_pad_attr_39_pull_select_39_qs; + logic dio_pad_attr_39_pull_select_39_wd; + logic dio_pad_attr_39_keeper_en_39_qs; + logic dio_pad_attr_39_keeper_en_39_wd; + logic dio_pad_attr_39_schmitt_en_39_qs; + logic dio_pad_attr_39_schmitt_en_39_wd; + logic dio_pad_attr_39_od_en_39_qs; + logic dio_pad_attr_39_od_en_39_wd; + logic dio_pad_attr_39_input_disable_39_qs; + logic dio_pad_attr_39_input_disable_39_wd; + logic [1:0] dio_pad_attr_39_slew_rate_39_qs; + logic [1:0] dio_pad_attr_39_slew_rate_39_wd; + logic [3:0] dio_pad_attr_39_drive_strength_39_qs; + logic [3:0] dio_pad_attr_39_drive_strength_39_wd; + logic dio_pad_attr_40_re; + logic dio_pad_attr_40_we; + logic dio_pad_attr_40_invert_40_qs; + logic dio_pad_attr_40_invert_40_wd; + logic dio_pad_attr_40_virtual_od_en_40_qs; + logic dio_pad_attr_40_virtual_od_en_40_wd; + logic dio_pad_attr_40_pull_en_40_qs; + logic dio_pad_attr_40_pull_en_40_wd; + logic dio_pad_attr_40_pull_select_40_qs; + logic dio_pad_attr_40_pull_select_40_wd; + logic dio_pad_attr_40_keeper_en_40_qs; + logic dio_pad_attr_40_keeper_en_40_wd; + logic dio_pad_attr_40_schmitt_en_40_qs; + logic dio_pad_attr_40_schmitt_en_40_wd; + logic dio_pad_attr_40_od_en_40_qs; + logic dio_pad_attr_40_od_en_40_wd; + logic dio_pad_attr_40_input_disable_40_qs; + logic dio_pad_attr_40_input_disable_40_wd; + logic [1:0] dio_pad_attr_40_slew_rate_40_qs; + logic [1:0] dio_pad_attr_40_slew_rate_40_wd; + logic [3:0] dio_pad_attr_40_drive_strength_40_qs; + logic [3:0] dio_pad_attr_40_drive_strength_40_wd; + logic dio_pad_attr_41_re; + logic dio_pad_attr_41_we; + logic dio_pad_attr_41_invert_41_qs; + logic dio_pad_attr_41_invert_41_wd; + logic dio_pad_attr_41_virtual_od_en_41_qs; + logic dio_pad_attr_41_virtual_od_en_41_wd; + logic dio_pad_attr_41_pull_en_41_qs; + logic dio_pad_attr_41_pull_en_41_wd; + logic dio_pad_attr_41_pull_select_41_qs; + logic dio_pad_attr_41_pull_select_41_wd; + logic dio_pad_attr_41_keeper_en_41_qs; + logic dio_pad_attr_41_keeper_en_41_wd; + logic dio_pad_attr_41_schmitt_en_41_qs; + logic dio_pad_attr_41_schmitt_en_41_wd; + logic dio_pad_attr_41_od_en_41_qs; + logic dio_pad_attr_41_od_en_41_wd; + logic dio_pad_attr_41_input_disable_41_qs; + logic dio_pad_attr_41_input_disable_41_wd; + logic [1:0] dio_pad_attr_41_slew_rate_41_qs; + logic [1:0] dio_pad_attr_41_slew_rate_41_wd; + logic [3:0] dio_pad_attr_41_drive_strength_41_qs; + logic [3:0] dio_pad_attr_41_drive_strength_41_wd; + logic dio_pad_attr_42_re; + logic dio_pad_attr_42_we; + logic dio_pad_attr_42_invert_42_qs; + logic dio_pad_attr_42_invert_42_wd; + logic dio_pad_attr_42_virtual_od_en_42_qs; + logic dio_pad_attr_42_virtual_od_en_42_wd; + logic dio_pad_attr_42_pull_en_42_qs; + logic dio_pad_attr_42_pull_en_42_wd; + logic dio_pad_attr_42_pull_select_42_qs; + logic dio_pad_attr_42_pull_select_42_wd; + logic dio_pad_attr_42_keeper_en_42_qs; + logic dio_pad_attr_42_keeper_en_42_wd; + logic dio_pad_attr_42_schmitt_en_42_qs; + logic dio_pad_attr_42_schmitt_en_42_wd; + logic dio_pad_attr_42_od_en_42_qs; + logic dio_pad_attr_42_od_en_42_wd; + logic dio_pad_attr_42_input_disable_42_qs; + logic dio_pad_attr_42_input_disable_42_wd; + logic [1:0] dio_pad_attr_42_slew_rate_42_qs; + logic [1:0] dio_pad_attr_42_slew_rate_42_wd; + logic [3:0] dio_pad_attr_42_drive_strength_42_qs; + logic [3:0] dio_pad_attr_42_drive_strength_42_wd; + logic dio_pad_attr_43_re; + logic dio_pad_attr_43_we; + logic dio_pad_attr_43_invert_43_qs; + logic dio_pad_attr_43_invert_43_wd; + logic dio_pad_attr_43_virtual_od_en_43_qs; + logic dio_pad_attr_43_virtual_od_en_43_wd; + logic dio_pad_attr_43_pull_en_43_qs; + logic dio_pad_attr_43_pull_en_43_wd; + logic dio_pad_attr_43_pull_select_43_qs; + logic dio_pad_attr_43_pull_select_43_wd; + logic dio_pad_attr_43_keeper_en_43_qs; + logic dio_pad_attr_43_keeper_en_43_wd; + logic dio_pad_attr_43_schmitt_en_43_qs; + logic dio_pad_attr_43_schmitt_en_43_wd; + logic dio_pad_attr_43_od_en_43_qs; + logic dio_pad_attr_43_od_en_43_wd; + logic dio_pad_attr_43_input_disable_43_qs; + logic dio_pad_attr_43_input_disable_43_wd; + logic [1:0] dio_pad_attr_43_slew_rate_43_qs; + logic [1:0] dio_pad_attr_43_slew_rate_43_wd; + logic [3:0] dio_pad_attr_43_drive_strength_43_qs; + logic [3:0] dio_pad_attr_43_drive_strength_43_wd; + logic dio_pad_attr_44_re; + logic dio_pad_attr_44_we; + logic dio_pad_attr_44_invert_44_qs; + logic dio_pad_attr_44_invert_44_wd; + logic dio_pad_attr_44_virtual_od_en_44_qs; + logic dio_pad_attr_44_virtual_od_en_44_wd; + logic dio_pad_attr_44_pull_en_44_qs; + logic dio_pad_attr_44_pull_en_44_wd; + logic dio_pad_attr_44_pull_select_44_qs; + logic dio_pad_attr_44_pull_select_44_wd; + logic dio_pad_attr_44_keeper_en_44_qs; + logic dio_pad_attr_44_keeper_en_44_wd; + logic dio_pad_attr_44_schmitt_en_44_qs; + logic dio_pad_attr_44_schmitt_en_44_wd; + logic dio_pad_attr_44_od_en_44_qs; + logic dio_pad_attr_44_od_en_44_wd; + logic dio_pad_attr_44_input_disable_44_qs; + logic dio_pad_attr_44_input_disable_44_wd; + logic [1:0] dio_pad_attr_44_slew_rate_44_qs; + logic [1:0] dio_pad_attr_44_slew_rate_44_wd; + logic [3:0] dio_pad_attr_44_drive_strength_44_qs; + logic [3:0] dio_pad_attr_44_drive_strength_44_wd; + logic dio_pad_attr_45_re; + logic dio_pad_attr_45_we; + logic dio_pad_attr_45_invert_45_qs; + logic dio_pad_attr_45_invert_45_wd; + logic dio_pad_attr_45_virtual_od_en_45_qs; + logic dio_pad_attr_45_virtual_od_en_45_wd; + logic dio_pad_attr_45_pull_en_45_qs; + logic dio_pad_attr_45_pull_en_45_wd; + logic dio_pad_attr_45_pull_select_45_qs; + logic dio_pad_attr_45_pull_select_45_wd; + logic dio_pad_attr_45_keeper_en_45_qs; + logic dio_pad_attr_45_keeper_en_45_wd; + logic dio_pad_attr_45_schmitt_en_45_qs; + logic dio_pad_attr_45_schmitt_en_45_wd; + logic dio_pad_attr_45_od_en_45_qs; + logic dio_pad_attr_45_od_en_45_wd; + logic dio_pad_attr_45_input_disable_45_qs; + logic dio_pad_attr_45_input_disable_45_wd; + logic [1:0] dio_pad_attr_45_slew_rate_45_qs; + logic [1:0] dio_pad_attr_45_slew_rate_45_wd; + logic [3:0] dio_pad_attr_45_drive_strength_45_qs; + logic [3:0] dio_pad_attr_45_drive_strength_45_wd; + logic dio_pad_attr_46_re; + logic dio_pad_attr_46_we; + logic dio_pad_attr_46_invert_46_qs; + logic dio_pad_attr_46_invert_46_wd; + logic dio_pad_attr_46_virtual_od_en_46_qs; + logic dio_pad_attr_46_virtual_od_en_46_wd; + logic dio_pad_attr_46_pull_en_46_qs; + logic dio_pad_attr_46_pull_en_46_wd; + logic dio_pad_attr_46_pull_select_46_qs; + logic dio_pad_attr_46_pull_select_46_wd; + logic dio_pad_attr_46_keeper_en_46_qs; + logic dio_pad_attr_46_keeper_en_46_wd; + logic dio_pad_attr_46_schmitt_en_46_qs; + logic dio_pad_attr_46_schmitt_en_46_wd; + logic dio_pad_attr_46_od_en_46_qs; + logic dio_pad_attr_46_od_en_46_wd; + logic dio_pad_attr_46_input_disable_46_qs; + logic dio_pad_attr_46_input_disable_46_wd; + logic [1:0] dio_pad_attr_46_slew_rate_46_qs; + logic [1:0] dio_pad_attr_46_slew_rate_46_wd; + logic [3:0] dio_pad_attr_46_drive_strength_46_qs; + logic [3:0] dio_pad_attr_46_drive_strength_46_wd; + logic dio_pad_attr_47_re; + logic dio_pad_attr_47_we; + logic dio_pad_attr_47_invert_47_qs; + logic dio_pad_attr_47_invert_47_wd; + logic dio_pad_attr_47_virtual_od_en_47_qs; + logic dio_pad_attr_47_virtual_od_en_47_wd; + logic dio_pad_attr_47_pull_en_47_qs; + logic dio_pad_attr_47_pull_en_47_wd; + logic dio_pad_attr_47_pull_select_47_qs; + logic dio_pad_attr_47_pull_select_47_wd; + logic dio_pad_attr_47_keeper_en_47_qs; + logic dio_pad_attr_47_keeper_en_47_wd; + logic dio_pad_attr_47_schmitt_en_47_qs; + logic dio_pad_attr_47_schmitt_en_47_wd; + logic dio_pad_attr_47_od_en_47_qs; + logic dio_pad_attr_47_od_en_47_wd; + logic dio_pad_attr_47_input_disable_47_qs; + logic dio_pad_attr_47_input_disable_47_wd; + logic [1:0] dio_pad_attr_47_slew_rate_47_qs; + logic [1:0] dio_pad_attr_47_slew_rate_47_wd; + logic [3:0] dio_pad_attr_47_drive_strength_47_qs; + logic [3:0] dio_pad_attr_47_drive_strength_47_wd; + logic dio_pad_attr_48_re; + logic dio_pad_attr_48_we; + logic dio_pad_attr_48_invert_48_qs; + logic dio_pad_attr_48_invert_48_wd; + logic dio_pad_attr_48_virtual_od_en_48_qs; + logic dio_pad_attr_48_virtual_od_en_48_wd; + logic dio_pad_attr_48_pull_en_48_qs; + logic dio_pad_attr_48_pull_en_48_wd; + logic dio_pad_attr_48_pull_select_48_qs; + logic dio_pad_attr_48_pull_select_48_wd; + logic dio_pad_attr_48_keeper_en_48_qs; + logic dio_pad_attr_48_keeper_en_48_wd; + logic dio_pad_attr_48_schmitt_en_48_qs; + logic dio_pad_attr_48_schmitt_en_48_wd; + logic dio_pad_attr_48_od_en_48_qs; + logic dio_pad_attr_48_od_en_48_wd; + logic dio_pad_attr_48_input_disable_48_qs; + logic dio_pad_attr_48_input_disable_48_wd; + logic [1:0] dio_pad_attr_48_slew_rate_48_qs; + logic [1:0] dio_pad_attr_48_slew_rate_48_wd; + logic [3:0] dio_pad_attr_48_drive_strength_48_qs; + logic [3:0] dio_pad_attr_48_drive_strength_48_wd; + logic dio_pad_attr_49_re; + logic dio_pad_attr_49_we; + logic dio_pad_attr_49_invert_49_qs; + logic dio_pad_attr_49_invert_49_wd; + logic dio_pad_attr_49_virtual_od_en_49_qs; + logic dio_pad_attr_49_virtual_od_en_49_wd; + logic dio_pad_attr_49_pull_en_49_qs; + logic dio_pad_attr_49_pull_en_49_wd; + logic dio_pad_attr_49_pull_select_49_qs; + logic dio_pad_attr_49_pull_select_49_wd; + logic dio_pad_attr_49_keeper_en_49_qs; + logic dio_pad_attr_49_keeper_en_49_wd; + logic dio_pad_attr_49_schmitt_en_49_qs; + logic dio_pad_attr_49_schmitt_en_49_wd; + logic dio_pad_attr_49_od_en_49_qs; + logic dio_pad_attr_49_od_en_49_wd; + logic dio_pad_attr_49_input_disable_49_qs; + logic dio_pad_attr_49_input_disable_49_wd; + logic [1:0] dio_pad_attr_49_slew_rate_49_qs; + logic [1:0] dio_pad_attr_49_slew_rate_49_wd; + logic [3:0] dio_pad_attr_49_drive_strength_49_qs; + logic [3:0] dio_pad_attr_49_drive_strength_49_wd; + logic dio_pad_attr_50_re; + logic dio_pad_attr_50_we; + logic dio_pad_attr_50_invert_50_qs; + logic dio_pad_attr_50_invert_50_wd; + logic dio_pad_attr_50_virtual_od_en_50_qs; + logic dio_pad_attr_50_virtual_od_en_50_wd; + logic dio_pad_attr_50_pull_en_50_qs; + logic dio_pad_attr_50_pull_en_50_wd; + logic dio_pad_attr_50_pull_select_50_qs; + logic dio_pad_attr_50_pull_select_50_wd; + logic dio_pad_attr_50_keeper_en_50_qs; + logic dio_pad_attr_50_keeper_en_50_wd; + logic dio_pad_attr_50_schmitt_en_50_qs; + logic dio_pad_attr_50_schmitt_en_50_wd; + logic dio_pad_attr_50_od_en_50_qs; + logic dio_pad_attr_50_od_en_50_wd; + logic dio_pad_attr_50_input_disable_50_qs; + logic dio_pad_attr_50_input_disable_50_wd; + logic [1:0] dio_pad_attr_50_slew_rate_50_qs; + logic [1:0] dio_pad_attr_50_slew_rate_50_wd; + logic [3:0] dio_pad_attr_50_drive_strength_50_qs; + logic [3:0] dio_pad_attr_50_drive_strength_50_wd; + logic dio_pad_attr_51_re; + logic dio_pad_attr_51_we; + logic dio_pad_attr_51_invert_51_qs; + logic dio_pad_attr_51_invert_51_wd; + logic dio_pad_attr_51_virtual_od_en_51_qs; + logic dio_pad_attr_51_virtual_od_en_51_wd; + logic dio_pad_attr_51_pull_en_51_qs; + logic dio_pad_attr_51_pull_en_51_wd; + logic dio_pad_attr_51_pull_select_51_qs; + logic dio_pad_attr_51_pull_select_51_wd; + logic dio_pad_attr_51_keeper_en_51_qs; + logic dio_pad_attr_51_keeper_en_51_wd; + logic dio_pad_attr_51_schmitt_en_51_qs; + logic dio_pad_attr_51_schmitt_en_51_wd; + logic dio_pad_attr_51_od_en_51_qs; + logic dio_pad_attr_51_od_en_51_wd; + logic dio_pad_attr_51_input_disable_51_qs; + logic dio_pad_attr_51_input_disable_51_wd; + logic [1:0] dio_pad_attr_51_slew_rate_51_qs; + logic [1:0] dio_pad_attr_51_slew_rate_51_wd; + logic [3:0] dio_pad_attr_51_drive_strength_51_qs; + logic [3:0] dio_pad_attr_51_drive_strength_51_wd; + logic dio_pad_attr_52_re; + logic dio_pad_attr_52_we; + logic dio_pad_attr_52_invert_52_qs; + logic dio_pad_attr_52_invert_52_wd; + logic dio_pad_attr_52_virtual_od_en_52_qs; + logic dio_pad_attr_52_virtual_od_en_52_wd; + logic dio_pad_attr_52_pull_en_52_qs; + logic dio_pad_attr_52_pull_en_52_wd; + logic dio_pad_attr_52_pull_select_52_qs; + logic dio_pad_attr_52_pull_select_52_wd; + logic dio_pad_attr_52_keeper_en_52_qs; + logic dio_pad_attr_52_keeper_en_52_wd; + logic dio_pad_attr_52_schmitt_en_52_qs; + logic dio_pad_attr_52_schmitt_en_52_wd; + logic dio_pad_attr_52_od_en_52_qs; + logic dio_pad_attr_52_od_en_52_wd; + logic dio_pad_attr_52_input_disable_52_qs; + logic dio_pad_attr_52_input_disable_52_wd; + logic [1:0] dio_pad_attr_52_slew_rate_52_qs; + logic [1:0] dio_pad_attr_52_slew_rate_52_wd; + logic [3:0] dio_pad_attr_52_drive_strength_52_qs; + logic [3:0] dio_pad_attr_52_drive_strength_52_wd; + logic dio_pad_attr_53_re; + logic dio_pad_attr_53_we; + logic dio_pad_attr_53_invert_53_qs; + logic dio_pad_attr_53_invert_53_wd; + logic dio_pad_attr_53_virtual_od_en_53_qs; + logic dio_pad_attr_53_virtual_od_en_53_wd; + logic dio_pad_attr_53_pull_en_53_qs; + logic dio_pad_attr_53_pull_en_53_wd; + logic dio_pad_attr_53_pull_select_53_qs; + logic dio_pad_attr_53_pull_select_53_wd; + logic dio_pad_attr_53_keeper_en_53_qs; + logic dio_pad_attr_53_keeper_en_53_wd; + logic dio_pad_attr_53_schmitt_en_53_qs; + logic dio_pad_attr_53_schmitt_en_53_wd; + logic dio_pad_attr_53_od_en_53_qs; + logic dio_pad_attr_53_od_en_53_wd; + logic dio_pad_attr_53_input_disable_53_qs; + logic dio_pad_attr_53_input_disable_53_wd; + logic [1:0] dio_pad_attr_53_slew_rate_53_qs; + logic [1:0] dio_pad_attr_53_slew_rate_53_wd; + logic [3:0] dio_pad_attr_53_drive_strength_53_qs; + logic [3:0] dio_pad_attr_53_drive_strength_53_wd; + logic dio_pad_attr_54_re; + logic dio_pad_attr_54_we; + logic dio_pad_attr_54_invert_54_qs; + logic dio_pad_attr_54_invert_54_wd; + logic dio_pad_attr_54_virtual_od_en_54_qs; + logic dio_pad_attr_54_virtual_od_en_54_wd; + logic dio_pad_attr_54_pull_en_54_qs; + logic dio_pad_attr_54_pull_en_54_wd; + logic dio_pad_attr_54_pull_select_54_qs; + logic dio_pad_attr_54_pull_select_54_wd; + logic dio_pad_attr_54_keeper_en_54_qs; + logic dio_pad_attr_54_keeper_en_54_wd; + logic dio_pad_attr_54_schmitt_en_54_qs; + logic dio_pad_attr_54_schmitt_en_54_wd; + logic dio_pad_attr_54_od_en_54_qs; + logic dio_pad_attr_54_od_en_54_wd; + logic dio_pad_attr_54_input_disable_54_qs; + logic dio_pad_attr_54_input_disable_54_wd; + logic [1:0] dio_pad_attr_54_slew_rate_54_qs; + logic [1:0] dio_pad_attr_54_slew_rate_54_wd; + logic [3:0] dio_pad_attr_54_drive_strength_54_qs; + logic [3:0] dio_pad_attr_54_drive_strength_54_wd; + logic dio_pad_attr_55_re; + logic dio_pad_attr_55_we; + logic dio_pad_attr_55_invert_55_qs; + logic dio_pad_attr_55_invert_55_wd; + logic dio_pad_attr_55_virtual_od_en_55_qs; + logic dio_pad_attr_55_virtual_od_en_55_wd; + logic dio_pad_attr_55_pull_en_55_qs; + logic dio_pad_attr_55_pull_en_55_wd; + logic dio_pad_attr_55_pull_select_55_qs; + logic dio_pad_attr_55_pull_select_55_wd; + logic dio_pad_attr_55_keeper_en_55_qs; + logic dio_pad_attr_55_keeper_en_55_wd; + logic dio_pad_attr_55_schmitt_en_55_qs; + logic dio_pad_attr_55_schmitt_en_55_wd; + logic dio_pad_attr_55_od_en_55_qs; + logic dio_pad_attr_55_od_en_55_wd; + logic dio_pad_attr_55_input_disable_55_qs; + logic dio_pad_attr_55_input_disable_55_wd; + logic [1:0] dio_pad_attr_55_slew_rate_55_qs; + logic [1:0] dio_pad_attr_55_slew_rate_55_wd; + logic [3:0] dio_pad_attr_55_drive_strength_55_qs; + logic [3:0] dio_pad_attr_55_drive_strength_55_wd; + logic dio_pad_attr_56_re; + logic dio_pad_attr_56_we; + logic dio_pad_attr_56_invert_56_qs; + logic dio_pad_attr_56_invert_56_wd; + logic dio_pad_attr_56_virtual_od_en_56_qs; + logic dio_pad_attr_56_virtual_od_en_56_wd; + logic dio_pad_attr_56_pull_en_56_qs; + logic dio_pad_attr_56_pull_en_56_wd; + logic dio_pad_attr_56_pull_select_56_qs; + logic dio_pad_attr_56_pull_select_56_wd; + logic dio_pad_attr_56_keeper_en_56_qs; + logic dio_pad_attr_56_keeper_en_56_wd; + logic dio_pad_attr_56_schmitt_en_56_qs; + logic dio_pad_attr_56_schmitt_en_56_wd; + logic dio_pad_attr_56_od_en_56_qs; + logic dio_pad_attr_56_od_en_56_wd; + logic dio_pad_attr_56_input_disable_56_qs; + logic dio_pad_attr_56_input_disable_56_wd; + logic [1:0] dio_pad_attr_56_slew_rate_56_qs; + logic [1:0] dio_pad_attr_56_slew_rate_56_wd; + logic [3:0] dio_pad_attr_56_drive_strength_56_qs; + logic [3:0] dio_pad_attr_56_drive_strength_56_wd; + logic dio_pad_attr_57_re; + logic dio_pad_attr_57_we; + logic dio_pad_attr_57_invert_57_qs; + logic dio_pad_attr_57_invert_57_wd; + logic dio_pad_attr_57_virtual_od_en_57_qs; + logic dio_pad_attr_57_virtual_od_en_57_wd; + logic dio_pad_attr_57_pull_en_57_qs; + logic dio_pad_attr_57_pull_en_57_wd; + logic dio_pad_attr_57_pull_select_57_qs; + logic dio_pad_attr_57_pull_select_57_wd; + logic dio_pad_attr_57_keeper_en_57_qs; + logic dio_pad_attr_57_keeper_en_57_wd; + logic dio_pad_attr_57_schmitt_en_57_qs; + logic dio_pad_attr_57_schmitt_en_57_wd; + logic dio_pad_attr_57_od_en_57_qs; + logic dio_pad_attr_57_od_en_57_wd; + logic dio_pad_attr_57_input_disable_57_qs; + logic dio_pad_attr_57_input_disable_57_wd; + logic [1:0] dio_pad_attr_57_slew_rate_57_qs; + logic [1:0] dio_pad_attr_57_slew_rate_57_wd; + logic [3:0] dio_pad_attr_57_drive_strength_57_qs; + logic [3:0] dio_pad_attr_57_drive_strength_57_wd; + logic dio_pad_attr_58_re; + logic dio_pad_attr_58_we; + logic dio_pad_attr_58_invert_58_qs; + logic dio_pad_attr_58_invert_58_wd; + logic dio_pad_attr_58_virtual_od_en_58_qs; + logic dio_pad_attr_58_virtual_od_en_58_wd; + logic dio_pad_attr_58_pull_en_58_qs; + logic dio_pad_attr_58_pull_en_58_wd; + logic dio_pad_attr_58_pull_select_58_qs; + logic dio_pad_attr_58_pull_select_58_wd; + logic dio_pad_attr_58_keeper_en_58_qs; + logic dio_pad_attr_58_keeper_en_58_wd; + logic dio_pad_attr_58_schmitt_en_58_qs; + logic dio_pad_attr_58_schmitt_en_58_wd; + logic dio_pad_attr_58_od_en_58_qs; + logic dio_pad_attr_58_od_en_58_wd; + logic dio_pad_attr_58_input_disable_58_qs; + logic dio_pad_attr_58_input_disable_58_wd; + logic [1:0] dio_pad_attr_58_slew_rate_58_qs; + logic [1:0] dio_pad_attr_58_slew_rate_58_wd; + logic [3:0] dio_pad_attr_58_drive_strength_58_qs; + logic [3:0] dio_pad_attr_58_drive_strength_58_wd; + logic dio_pad_attr_59_re; + logic dio_pad_attr_59_we; + logic dio_pad_attr_59_invert_59_qs; + logic dio_pad_attr_59_invert_59_wd; + logic dio_pad_attr_59_virtual_od_en_59_qs; + logic dio_pad_attr_59_virtual_od_en_59_wd; + logic dio_pad_attr_59_pull_en_59_qs; + logic dio_pad_attr_59_pull_en_59_wd; + logic dio_pad_attr_59_pull_select_59_qs; + logic dio_pad_attr_59_pull_select_59_wd; + logic dio_pad_attr_59_keeper_en_59_qs; + logic dio_pad_attr_59_keeper_en_59_wd; + logic dio_pad_attr_59_schmitt_en_59_qs; + logic dio_pad_attr_59_schmitt_en_59_wd; + logic dio_pad_attr_59_od_en_59_qs; + logic dio_pad_attr_59_od_en_59_wd; + logic dio_pad_attr_59_input_disable_59_qs; + logic dio_pad_attr_59_input_disable_59_wd; + logic [1:0] dio_pad_attr_59_slew_rate_59_qs; + logic [1:0] dio_pad_attr_59_slew_rate_59_wd; + logic [3:0] dio_pad_attr_59_drive_strength_59_qs; + logic [3:0] dio_pad_attr_59_drive_strength_59_wd; + logic dio_pad_attr_60_re; + logic dio_pad_attr_60_we; + logic dio_pad_attr_60_invert_60_qs; + logic dio_pad_attr_60_invert_60_wd; + logic dio_pad_attr_60_virtual_od_en_60_qs; + logic dio_pad_attr_60_virtual_od_en_60_wd; + logic dio_pad_attr_60_pull_en_60_qs; + logic dio_pad_attr_60_pull_en_60_wd; + logic dio_pad_attr_60_pull_select_60_qs; + logic dio_pad_attr_60_pull_select_60_wd; + logic dio_pad_attr_60_keeper_en_60_qs; + logic dio_pad_attr_60_keeper_en_60_wd; + logic dio_pad_attr_60_schmitt_en_60_qs; + logic dio_pad_attr_60_schmitt_en_60_wd; + logic dio_pad_attr_60_od_en_60_qs; + logic dio_pad_attr_60_od_en_60_wd; + logic dio_pad_attr_60_input_disable_60_qs; + logic dio_pad_attr_60_input_disable_60_wd; + logic [1:0] dio_pad_attr_60_slew_rate_60_qs; + logic [1:0] dio_pad_attr_60_slew_rate_60_wd; + logic [3:0] dio_pad_attr_60_drive_strength_60_qs; + logic [3:0] dio_pad_attr_60_drive_strength_60_wd; + logic dio_pad_attr_61_re; + logic dio_pad_attr_61_we; + logic dio_pad_attr_61_invert_61_qs; + logic dio_pad_attr_61_invert_61_wd; + logic dio_pad_attr_61_virtual_od_en_61_qs; + logic dio_pad_attr_61_virtual_od_en_61_wd; + logic dio_pad_attr_61_pull_en_61_qs; + logic dio_pad_attr_61_pull_en_61_wd; + logic dio_pad_attr_61_pull_select_61_qs; + logic dio_pad_attr_61_pull_select_61_wd; + logic dio_pad_attr_61_keeper_en_61_qs; + logic dio_pad_attr_61_keeper_en_61_wd; + logic dio_pad_attr_61_schmitt_en_61_qs; + logic dio_pad_attr_61_schmitt_en_61_wd; + logic dio_pad_attr_61_od_en_61_qs; + logic dio_pad_attr_61_od_en_61_wd; + logic dio_pad_attr_61_input_disable_61_qs; + logic dio_pad_attr_61_input_disable_61_wd; + logic [1:0] dio_pad_attr_61_slew_rate_61_qs; + logic [1:0] dio_pad_attr_61_slew_rate_61_wd; + logic [3:0] dio_pad_attr_61_drive_strength_61_qs; + logic [3:0] dio_pad_attr_61_drive_strength_61_wd; + logic dio_pad_attr_62_re; + logic dio_pad_attr_62_we; + logic dio_pad_attr_62_invert_62_qs; + logic dio_pad_attr_62_invert_62_wd; + logic dio_pad_attr_62_virtual_od_en_62_qs; + logic dio_pad_attr_62_virtual_od_en_62_wd; + logic dio_pad_attr_62_pull_en_62_qs; + logic dio_pad_attr_62_pull_en_62_wd; + logic dio_pad_attr_62_pull_select_62_qs; + logic dio_pad_attr_62_pull_select_62_wd; + logic dio_pad_attr_62_keeper_en_62_qs; + logic dio_pad_attr_62_keeper_en_62_wd; + logic dio_pad_attr_62_schmitt_en_62_qs; + logic dio_pad_attr_62_schmitt_en_62_wd; + logic dio_pad_attr_62_od_en_62_qs; + logic dio_pad_attr_62_od_en_62_wd; + logic dio_pad_attr_62_input_disable_62_qs; + logic dio_pad_attr_62_input_disable_62_wd; + logic [1:0] dio_pad_attr_62_slew_rate_62_qs; + logic [1:0] dio_pad_attr_62_slew_rate_62_wd; + logic [3:0] dio_pad_attr_62_drive_strength_62_qs; + logic [3:0] dio_pad_attr_62_drive_strength_62_wd; + logic dio_pad_attr_63_re; + logic dio_pad_attr_63_we; + logic dio_pad_attr_63_invert_63_qs; + logic dio_pad_attr_63_invert_63_wd; + logic dio_pad_attr_63_virtual_od_en_63_qs; + logic dio_pad_attr_63_virtual_od_en_63_wd; + logic dio_pad_attr_63_pull_en_63_qs; + logic dio_pad_attr_63_pull_en_63_wd; + logic dio_pad_attr_63_pull_select_63_qs; + logic dio_pad_attr_63_pull_select_63_wd; + logic dio_pad_attr_63_keeper_en_63_qs; + logic dio_pad_attr_63_keeper_en_63_wd; + logic dio_pad_attr_63_schmitt_en_63_qs; + logic dio_pad_attr_63_schmitt_en_63_wd; + logic dio_pad_attr_63_od_en_63_qs; + logic dio_pad_attr_63_od_en_63_wd; + logic dio_pad_attr_63_input_disable_63_qs; + logic dio_pad_attr_63_input_disable_63_wd; + logic [1:0] dio_pad_attr_63_slew_rate_63_qs; + logic [1:0] dio_pad_attr_63_slew_rate_63_wd; + logic [3:0] dio_pad_attr_63_drive_strength_63_qs; + logic [3:0] dio_pad_attr_63_drive_strength_63_wd; + logic dio_pad_attr_64_re; + logic dio_pad_attr_64_we; + logic dio_pad_attr_64_invert_64_qs; + logic dio_pad_attr_64_invert_64_wd; + logic dio_pad_attr_64_virtual_od_en_64_qs; + logic dio_pad_attr_64_virtual_od_en_64_wd; + logic dio_pad_attr_64_pull_en_64_qs; + logic dio_pad_attr_64_pull_en_64_wd; + logic dio_pad_attr_64_pull_select_64_qs; + logic dio_pad_attr_64_pull_select_64_wd; + logic dio_pad_attr_64_keeper_en_64_qs; + logic dio_pad_attr_64_keeper_en_64_wd; + logic dio_pad_attr_64_schmitt_en_64_qs; + logic dio_pad_attr_64_schmitt_en_64_wd; + logic dio_pad_attr_64_od_en_64_qs; + logic dio_pad_attr_64_od_en_64_wd; + logic dio_pad_attr_64_input_disable_64_qs; + logic dio_pad_attr_64_input_disable_64_wd; + logic [1:0] dio_pad_attr_64_slew_rate_64_qs; + logic [1:0] dio_pad_attr_64_slew_rate_64_wd; + logic [3:0] dio_pad_attr_64_drive_strength_64_qs; + logic [3:0] dio_pad_attr_64_drive_strength_64_wd; + logic dio_pad_attr_65_re; + logic dio_pad_attr_65_we; + logic dio_pad_attr_65_invert_65_qs; + logic dio_pad_attr_65_invert_65_wd; + logic dio_pad_attr_65_virtual_od_en_65_qs; + logic dio_pad_attr_65_virtual_od_en_65_wd; + logic dio_pad_attr_65_pull_en_65_qs; + logic dio_pad_attr_65_pull_en_65_wd; + logic dio_pad_attr_65_pull_select_65_qs; + logic dio_pad_attr_65_pull_select_65_wd; + logic dio_pad_attr_65_keeper_en_65_qs; + logic dio_pad_attr_65_keeper_en_65_wd; + logic dio_pad_attr_65_schmitt_en_65_qs; + logic dio_pad_attr_65_schmitt_en_65_wd; + logic dio_pad_attr_65_od_en_65_qs; + logic dio_pad_attr_65_od_en_65_wd; + logic dio_pad_attr_65_input_disable_65_qs; + logic dio_pad_attr_65_input_disable_65_wd; + logic [1:0] dio_pad_attr_65_slew_rate_65_qs; + logic [1:0] dio_pad_attr_65_slew_rate_65_wd; + logic [3:0] dio_pad_attr_65_drive_strength_65_qs; + logic [3:0] dio_pad_attr_65_drive_strength_65_wd; + logic dio_pad_attr_66_re; + logic dio_pad_attr_66_we; + logic dio_pad_attr_66_invert_66_qs; + logic dio_pad_attr_66_invert_66_wd; + logic dio_pad_attr_66_virtual_od_en_66_qs; + logic dio_pad_attr_66_virtual_od_en_66_wd; + logic dio_pad_attr_66_pull_en_66_qs; + logic dio_pad_attr_66_pull_en_66_wd; + logic dio_pad_attr_66_pull_select_66_qs; + logic dio_pad_attr_66_pull_select_66_wd; + logic dio_pad_attr_66_keeper_en_66_qs; + logic dio_pad_attr_66_keeper_en_66_wd; + logic dio_pad_attr_66_schmitt_en_66_qs; + logic dio_pad_attr_66_schmitt_en_66_wd; + logic dio_pad_attr_66_od_en_66_qs; + logic dio_pad_attr_66_od_en_66_wd; + logic dio_pad_attr_66_input_disable_66_qs; + logic dio_pad_attr_66_input_disable_66_wd; + logic [1:0] dio_pad_attr_66_slew_rate_66_qs; + logic [1:0] dio_pad_attr_66_slew_rate_66_wd; + logic [3:0] dio_pad_attr_66_drive_strength_66_qs; + logic [3:0] dio_pad_attr_66_drive_strength_66_wd; + logic dio_pad_attr_67_re; + logic dio_pad_attr_67_we; + logic dio_pad_attr_67_invert_67_qs; + logic dio_pad_attr_67_invert_67_wd; + logic dio_pad_attr_67_virtual_od_en_67_qs; + logic dio_pad_attr_67_virtual_od_en_67_wd; + logic dio_pad_attr_67_pull_en_67_qs; + logic dio_pad_attr_67_pull_en_67_wd; + logic dio_pad_attr_67_pull_select_67_qs; + logic dio_pad_attr_67_pull_select_67_wd; + logic dio_pad_attr_67_keeper_en_67_qs; + logic dio_pad_attr_67_keeper_en_67_wd; + logic dio_pad_attr_67_schmitt_en_67_qs; + logic dio_pad_attr_67_schmitt_en_67_wd; + logic dio_pad_attr_67_od_en_67_qs; + logic dio_pad_attr_67_od_en_67_wd; + logic dio_pad_attr_67_input_disable_67_qs; + logic dio_pad_attr_67_input_disable_67_wd; + logic [1:0] dio_pad_attr_67_slew_rate_67_qs; + logic [1:0] dio_pad_attr_67_slew_rate_67_wd; + logic [3:0] dio_pad_attr_67_drive_strength_67_qs; + logic [3:0] dio_pad_attr_67_drive_strength_67_wd; + logic dio_pad_attr_68_re; + logic dio_pad_attr_68_we; + logic dio_pad_attr_68_invert_68_qs; + logic dio_pad_attr_68_invert_68_wd; + logic dio_pad_attr_68_virtual_od_en_68_qs; + logic dio_pad_attr_68_virtual_od_en_68_wd; + logic dio_pad_attr_68_pull_en_68_qs; + logic dio_pad_attr_68_pull_en_68_wd; + logic dio_pad_attr_68_pull_select_68_qs; + logic dio_pad_attr_68_pull_select_68_wd; + logic dio_pad_attr_68_keeper_en_68_qs; + logic dio_pad_attr_68_keeper_en_68_wd; + logic dio_pad_attr_68_schmitt_en_68_qs; + logic dio_pad_attr_68_schmitt_en_68_wd; + logic dio_pad_attr_68_od_en_68_qs; + logic dio_pad_attr_68_od_en_68_wd; + logic dio_pad_attr_68_input_disable_68_qs; + logic dio_pad_attr_68_input_disable_68_wd; + logic [1:0] dio_pad_attr_68_slew_rate_68_qs; + logic [1:0] dio_pad_attr_68_slew_rate_68_wd; + logic [3:0] dio_pad_attr_68_drive_strength_68_qs; + logic [3:0] dio_pad_attr_68_drive_strength_68_wd; + logic dio_pad_attr_69_re; + logic dio_pad_attr_69_we; + logic dio_pad_attr_69_invert_69_qs; + logic dio_pad_attr_69_invert_69_wd; + logic dio_pad_attr_69_virtual_od_en_69_qs; + logic dio_pad_attr_69_virtual_od_en_69_wd; + logic dio_pad_attr_69_pull_en_69_qs; + logic dio_pad_attr_69_pull_en_69_wd; + logic dio_pad_attr_69_pull_select_69_qs; + logic dio_pad_attr_69_pull_select_69_wd; + logic dio_pad_attr_69_keeper_en_69_qs; + logic dio_pad_attr_69_keeper_en_69_wd; + logic dio_pad_attr_69_schmitt_en_69_qs; + logic dio_pad_attr_69_schmitt_en_69_wd; + logic dio_pad_attr_69_od_en_69_qs; + logic dio_pad_attr_69_od_en_69_wd; + logic dio_pad_attr_69_input_disable_69_qs; + logic dio_pad_attr_69_input_disable_69_wd; + logic [1:0] dio_pad_attr_69_slew_rate_69_qs; + logic [1:0] dio_pad_attr_69_slew_rate_69_wd; + logic [3:0] dio_pad_attr_69_drive_strength_69_qs; + logic [3:0] dio_pad_attr_69_drive_strength_69_wd; + logic dio_pad_attr_70_re; + logic dio_pad_attr_70_we; + logic dio_pad_attr_70_invert_70_qs; + logic dio_pad_attr_70_invert_70_wd; + logic dio_pad_attr_70_virtual_od_en_70_qs; + logic dio_pad_attr_70_virtual_od_en_70_wd; + logic dio_pad_attr_70_pull_en_70_qs; + logic dio_pad_attr_70_pull_en_70_wd; + logic dio_pad_attr_70_pull_select_70_qs; + logic dio_pad_attr_70_pull_select_70_wd; + logic dio_pad_attr_70_keeper_en_70_qs; + logic dio_pad_attr_70_keeper_en_70_wd; + logic dio_pad_attr_70_schmitt_en_70_qs; + logic dio_pad_attr_70_schmitt_en_70_wd; + logic dio_pad_attr_70_od_en_70_qs; + logic dio_pad_attr_70_od_en_70_wd; + logic dio_pad_attr_70_input_disable_70_qs; + logic dio_pad_attr_70_input_disable_70_wd; + logic [1:0] dio_pad_attr_70_slew_rate_70_qs; + logic [1:0] dio_pad_attr_70_slew_rate_70_wd; + logic [3:0] dio_pad_attr_70_drive_strength_70_qs; + logic [3:0] dio_pad_attr_70_drive_strength_70_wd; + logic dio_pad_attr_71_re; + logic dio_pad_attr_71_we; + logic dio_pad_attr_71_invert_71_qs; + logic dio_pad_attr_71_invert_71_wd; + logic dio_pad_attr_71_virtual_od_en_71_qs; + logic dio_pad_attr_71_virtual_od_en_71_wd; + logic dio_pad_attr_71_pull_en_71_qs; + logic dio_pad_attr_71_pull_en_71_wd; + logic dio_pad_attr_71_pull_select_71_qs; + logic dio_pad_attr_71_pull_select_71_wd; + logic dio_pad_attr_71_keeper_en_71_qs; + logic dio_pad_attr_71_keeper_en_71_wd; + logic dio_pad_attr_71_schmitt_en_71_qs; + logic dio_pad_attr_71_schmitt_en_71_wd; + logic dio_pad_attr_71_od_en_71_qs; + logic dio_pad_attr_71_od_en_71_wd; + logic dio_pad_attr_71_input_disable_71_qs; + logic dio_pad_attr_71_input_disable_71_wd; + logic [1:0] dio_pad_attr_71_slew_rate_71_qs; + logic [1:0] dio_pad_attr_71_slew_rate_71_wd; + logic [3:0] dio_pad_attr_71_drive_strength_71_qs; + logic [3:0] dio_pad_attr_71_drive_strength_71_wd; + logic dio_pad_attr_72_re; + logic dio_pad_attr_72_we; + logic dio_pad_attr_72_invert_72_qs; + logic dio_pad_attr_72_invert_72_wd; + logic dio_pad_attr_72_virtual_od_en_72_qs; + logic dio_pad_attr_72_virtual_od_en_72_wd; + logic dio_pad_attr_72_pull_en_72_qs; + logic dio_pad_attr_72_pull_en_72_wd; + logic dio_pad_attr_72_pull_select_72_qs; + logic dio_pad_attr_72_pull_select_72_wd; + logic dio_pad_attr_72_keeper_en_72_qs; + logic dio_pad_attr_72_keeper_en_72_wd; + logic dio_pad_attr_72_schmitt_en_72_qs; + logic dio_pad_attr_72_schmitt_en_72_wd; + logic dio_pad_attr_72_od_en_72_qs; + logic dio_pad_attr_72_od_en_72_wd; + logic dio_pad_attr_72_input_disable_72_qs; + logic dio_pad_attr_72_input_disable_72_wd; + logic [1:0] dio_pad_attr_72_slew_rate_72_qs; + logic [1:0] dio_pad_attr_72_slew_rate_72_wd; + logic [3:0] dio_pad_attr_72_drive_strength_72_qs; + logic [3:0] dio_pad_attr_72_drive_strength_72_wd; + logic mio_pad_sleep_status_we; + logic mio_pad_sleep_status_en_0_qs; + logic mio_pad_sleep_status_en_0_wd; + logic mio_pad_sleep_status_en_1_qs; + logic mio_pad_sleep_status_en_1_wd; + logic mio_pad_sleep_status_en_2_qs; + logic mio_pad_sleep_status_en_2_wd; + logic mio_pad_sleep_status_en_3_qs; + logic mio_pad_sleep_status_en_3_wd; + logic mio_pad_sleep_status_en_4_qs; + logic mio_pad_sleep_status_en_4_wd; + logic mio_pad_sleep_status_en_5_qs; + logic mio_pad_sleep_status_en_5_wd; + logic mio_pad_sleep_status_en_6_qs; + logic mio_pad_sleep_status_en_6_wd; + logic mio_pad_sleep_status_en_7_qs; + logic mio_pad_sleep_status_en_7_wd; + logic mio_pad_sleep_status_en_8_qs; + logic mio_pad_sleep_status_en_8_wd; + logic mio_pad_sleep_status_en_9_qs; + logic mio_pad_sleep_status_en_9_wd; + logic mio_pad_sleep_status_en_10_qs; + logic mio_pad_sleep_status_en_10_wd; + logic mio_pad_sleep_status_en_11_qs; + logic mio_pad_sleep_status_en_11_wd; + logic mio_pad_sleep_regwen_0_we; + logic mio_pad_sleep_regwen_0_qs; + logic mio_pad_sleep_regwen_0_wd; + logic mio_pad_sleep_regwen_1_we; + logic mio_pad_sleep_regwen_1_qs; + logic mio_pad_sleep_regwen_1_wd; + logic mio_pad_sleep_regwen_2_we; + logic mio_pad_sleep_regwen_2_qs; + logic mio_pad_sleep_regwen_2_wd; + logic mio_pad_sleep_regwen_3_we; + logic mio_pad_sleep_regwen_3_qs; + logic mio_pad_sleep_regwen_3_wd; + logic mio_pad_sleep_regwen_4_we; + logic mio_pad_sleep_regwen_4_qs; + logic mio_pad_sleep_regwen_4_wd; + logic mio_pad_sleep_regwen_5_we; + logic mio_pad_sleep_regwen_5_qs; + logic mio_pad_sleep_regwen_5_wd; + logic mio_pad_sleep_regwen_6_we; + logic mio_pad_sleep_regwen_6_qs; + logic mio_pad_sleep_regwen_6_wd; + logic mio_pad_sleep_regwen_7_we; + logic mio_pad_sleep_regwen_7_qs; + logic mio_pad_sleep_regwen_7_wd; + logic mio_pad_sleep_regwen_8_we; + logic mio_pad_sleep_regwen_8_qs; + logic mio_pad_sleep_regwen_8_wd; + logic mio_pad_sleep_regwen_9_we; + logic mio_pad_sleep_regwen_9_qs; + logic mio_pad_sleep_regwen_9_wd; + logic mio_pad_sleep_regwen_10_we; + logic mio_pad_sleep_regwen_10_qs; + logic mio_pad_sleep_regwen_10_wd; + logic mio_pad_sleep_regwen_11_we; + logic mio_pad_sleep_regwen_11_qs; + logic mio_pad_sleep_regwen_11_wd; + logic mio_pad_sleep_en_0_we; + logic mio_pad_sleep_en_0_qs; + logic mio_pad_sleep_en_0_wd; + logic mio_pad_sleep_en_1_we; + logic mio_pad_sleep_en_1_qs; + logic mio_pad_sleep_en_1_wd; + logic mio_pad_sleep_en_2_we; + logic mio_pad_sleep_en_2_qs; + logic mio_pad_sleep_en_2_wd; + logic mio_pad_sleep_en_3_we; + logic mio_pad_sleep_en_3_qs; + logic mio_pad_sleep_en_3_wd; + logic mio_pad_sleep_en_4_we; + logic mio_pad_sleep_en_4_qs; + logic mio_pad_sleep_en_4_wd; + logic mio_pad_sleep_en_5_we; + logic mio_pad_sleep_en_5_qs; + logic mio_pad_sleep_en_5_wd; + logic mio_pad_sleep_en_6_we; + logic mio_pad_sleep_en_6_qs; + logic mio_pad_sleep_en_6_wd; + logic mio_pad_sleep_en_7_we; + logic mio_pad_sleep_en_7_qs; + logic mio_pad_sleep_en_7_wd; + logic mio_pad_sleep_en_8_we; + logic mio_pad_sleep_en_8_qs; + logic mio_pad_sleep_en_8_wd; + logic mio_pad_sleep_en_9_we; + logic mio_pad_sleep_en_9_qs; + logic mio_pad_sleep_en_9_wd; + logic mio_pad_sleep_en_10_we; + logic mio_pad_sleep_en_10_qs; + logic mio_pad_sleep_en_10_wd; + logic mio_pad_sleep_en_11_we; + logic mio_pad_sleep_en_11_qs; + logic mio_pad_sleep_en_11_wd; + logic mio_pad_sleep_mode_0_we; + logic [1:0] mio_pad_sleep_mode_0_qs; + logic [1:0] mio_pad_sleep_mode_0_wd; + logic mio_pad_sleep_mode_1_we; + logic [1:0] mio_pad_sleep_mode_1_qs; + logic [1:0] mio_pad_sleep_mode_1_wd; + logic mio_pad_sleep_mode_2_we; + logic [1:0] mio_pad_sleep_mode_2_qs; + logic [1:0] mio_pad_sleep_mode_2_wd; + logic mio_pad_sleep_mode_3_we; + logic [1:0] mio_pad_sleep_mode_3_qs; + logic [1:0] mio_pad_sleep_mode_3_wd; + logic mio_pad_sleep_mode_4_we; + logic [1:0] mio_pad_sleep_mode_4_qs; + logic [1:0] mio_pad_sleep_mode_4_wd; + logic mio_pad_sleep_mode_5_we; + logic [1:0] mio_pad_sleep_mode_5_qs; + logic [1:0] mio_pad_sleep_mode_5_wd; + logic mio_pad_sleep_mode_6_we; + logic [1:0] mio_pad_sleep_mode_6_qs; + logic [1:0] mio_pad_sleep_mode_6_wd; + logic mio_pad_sleep_mode_7_we; + logic [1:0] mio_pad_sleep_mode_7_qs; + logic [1:0] mio_pad_sleep_mode_7_wd; + logic mio_pad_sleep_mode_8_we; + logic [1:0] mio_pad_sleep_mode_8_qs; + logic [1:0] mio_pad_sleep_mode_8_wd; + logic mio_pad_sleep_mode_9_we; + logic [1:0] mio_pad_sleep_mode_9_qs; + logic [1:0] mio_pad_sleep_mode_9_wd; + logic mio_pad_sleep_mode_10_we; + logic [1:0] mio_pad_sleep_mode_10_qs; + logic [1:0] mio_pad_sleep_mode_10_wd; + logic mio_pad_sleep_mode_11_we; + logic [1:0] mio_pad_sleep_mode_11_qs; + logic [1:0] mio_pad_sleep_mode_11_wd; + logic dio_pad_sleep_status_0_we; + logic dio_pad_sleep_status_0_en_0_qs; + logic dio_pad_sleep_status_0_en_0_wd; + logic dio_pad_sleep_status_0_en_1_qs; + logic dio_pad_sleep_status_0_en_1_wd; + logic dio_pad_sleep_status_0_en_2_qs; + logic dio_pad_sleep_status_0_en_2_wd; + logic dio_pad_sleep_status_0_en_3_qs; + logic dio_pad_sleep_status_0_en_3_wd; + logic dio_pad_sleep_status_0_en_4_qs; + logic dio_pad_sleep_status_0_en_4_wd; + logic dio_pad_sleep_status_0_en_5_qs; + logic dio_pad_sleep_status_0_en_5_wd; + logic dio_pad_sleep_status_0_en_6_qs; + logic dio_pad_sleep_status_0_en_6_wd; + logic dio_pad_sleep_status_0_en_7_qs; + logic dio_pad_sleep_status_0_en_7_wd; + logic dio_pad_sleep_status_0_en_8_qs; + logic dio_pad_sleep_status_0_en_8_wd; + logic dio_pad_sleep_status_0_en_9_qs; + logic dio_pad_sleep_status_0_en_9_wd; + logic dio_pad_sleep_status_0_en_10_qs; + logic dio_pad_sleep_status_0_en_10_wd; + logic dio_pad_sleep_status_0_en_11_qs; + logic dio_pad_sleep_status_0_en_11_wd; + logic dio_pad_sleep_status_0_en_12_qs; + logic dio_pad_sleep_status_0_en_12_wd; + logic dio_pad_sleep_status_0_en_13_qs; + logic dio_pad_sleep_status_0_en_13_wd; + logic dio_pad_sleep_status_0_en_14_qs; + logic dio_pad_sleep_status_0_en_14_wd; + logic dio_pad_sleep_status_0_en_15_qs; + logic dio_pad_sleep_status_0_en_15_wd; + logic dio_pad_sleep_status_0_en_16_qs; + logic dio_pad_sleep_status_0_en_16_wd; + logic dio_pad_sleep_status_0_en_17_qs; + logic dio_pad_sleep_status_0_en_17_wd; + logic dio_pad_sleep_status_0_en_18_qs; + logic dio_pad_sleep_status_0_en_18_wd; + logic dio_pad_sleep_status_0_en_19_qs; + logic dio_pad_sleep_status_0_en_19_wd; + logic dio_pad_sleep_status_0_en_20_qs; + logic dio_pad_sleep_status_0_en_20_wd; + logic dio_pad_sleep_status_0_en_21_qs; + logic dio_pad_sleep_status_0_en_21_wd; + logic dio_pad_sleep_status_0_en_22_qs; + logic dio_pad_sleep_status_0_en_22_wd; + logic dio_pad_sleep_status_0_en_23_qs; + logic dio_pad_sleep_status_0_en_23_wd; + logic dio_pad_sleep_status_0_en_24_qs; + logic dio_pad_sleep_status_0_en_24_wd; + logic dio_pad_sleep_status_0_en_25_qs; + logic dio_pad_sleep_status_0_en_25_wd; + logic dio_pad_sleep_status_0_en_26_qs; + logic dio_pad_sleep_status_0_en_26_wd; + logic dio_pad_sleep_status_0_en_27_qs; + logic dio_pad_sleep_status_0_en_27_wd; + logic dio_pad_sleep_status_0_en_28_qs; + logic dio_pad_sleep_status_0_en_28_wd; + logic dio_pad_sleep_status_0_en_29_qs; + logic dio_pad_sleep_status_0_en_29_wd; + logic dio_pad_sleep_status_0_en_30_qs; + logic dio_pad_sleep_status_0_en_30_wd; + logic dio_pad_sleep_status_0_en_31_qs; + logic dio_pad_sleep_status_0_en_31_wd; + logic dio_pad_sleep_status_1_we; + logic dio_pad_sleep_status_1_en_32_qs; + logic dio_pad_sleep_status_1_en_32_wd; + logic dio_pad_sleep_status_1_en_33_qs; + logic dio_pad_sleep_status_1_en_33_wd; + logic dio_pad_sleep_status_1_en_34_qs; + logic dio_pad_sleep_status_1_en_34_wd; + logic dio_pad_sleep_status_1_en_35_qs; + logic dio_pad_sleep_status_1_en_35_wd; + logic dio_pad_sleep_status_1_en_36_qs; + logic dio_pad_sleep_status_1_en_36_wd; + logic dio_pad_sleep_status_1_en_37_qs; + logic dio_pad_sleep_status_1_en_37_wd; + logic dio_pad_sleep_status_1_en_38_qs; + logic dio_pad_sleep_status_1_en_38_wd; + logic dio_pad_sleep_status_1_en_39_qs; + logic dio_pad_sleep_status_1_en_39_wd; + logic dio_pad_sleep_status_1_en_40_qs; + logic dio_pad_sleep_status_1_en_40_wd; + logic dio_pad_sleep_status_1_en_41_qs; + logic dio_pad_sleep_status_1_en_41_wd; + logic dio_pad_sleep_status_1_en_42_qs; + logic dio_pad_sleep_status_1_en_42_wd; + logic dio_pad_sleep_status_1_en_43_qs; + logic dio_pad_sleep_status_1_en_43_wd; + logic dio_pad_sleep_status_1_en_44_qs; + logic dio_pad_sleep_status_1_en_44_wd; + logic dio_pad_sleep_status_1_en_45_qs; + logic dio_pad_sleep_status_1_en_45_wd; + logic dio_pad_sleep_status_1_en_46_qs; + logic dio_pad_sleep_status_1_en_46_wd; + logic dio_pad_sleep_status_1_en_47_qs; + logic dio_pad_sleep_status_1_en_47_wd; + logic dio_pad_sleep_status_1_en_48_qs; + logic dio_pad_sleep_status_1_en_48_wd; + logic dio_pad_sleep_status_1_en_49_qs; + logic dio_pad_sleep_status_1_en_49_wd; + logic dio_pad_sleep_status_1_en_50_qs; + logic dio_pad_sleep_status_1_en_50_wd; + logic dio_pad_sleep_status_1_en_51_qs; + logic dio_pad_sleep_status_1_en_51_wd; + logic dio_pad_sleep_status_1_en_52_qs; + logic dio_pad_sleep_status_1_en_52_wd; + logic dio_pad_sleep_status_1_en_53_qs; + logic dio_pad_sleep_status_1_en_53_wd; + logic dio_pad_sleep_status_1_en_54_qs; + logic dio_pad_sleep_status_1_en_54_wd; + logic dio_pad_sleep_status_1_en_55_qs; + logic dio_pad_sleep_status_1_en_55_wd; + logic dio_pad_sleep_status_1_en_56_qs; + logic dio_pad_sleep_status_1_en_56_wd; + logic dio_pad_sleep_status_1_en_57_qs; + logic dio_pad_sleep_status_1_en_57_wd; + logic dio_pad_sleep_status_1_en_58_qs; + logic dio_pad_sleep_status_1_en_58_wd; + logic dio_pad_sleep_status_1_en_59_qs; + logic dio_pad_sleep_status_1_en_59_wd; + logic dio_pad_sleep_status_1_en_60_qs; + logic dio_pad_sleep_status_1_en_60_wd; + logic dio_pad_sleep_status_1_en_61_qs; + logic dio_pad_sleep_status_1_en_61_wd; + logic dio_pad_sleep_status_1_en_62_qs; + logic dio_pad_sleep_status_1_en_62_wd; + logic dio_pad_sleep_status_1_en_63_qs; + logic dio_pad_sleep_status_1_en_63_wd; + logic dio_pad_sleep_status_2_we; + logic dio_pad_sleep_status_2_en_64_qs; + logic dio_pad_sleep_status_2_en_64_wd; + logic dio_pad_sleep_status_2_en_65_qs; + logic dio_pad_sleep_status_2_en_65_wd; + logic dio_pad_sleep_status_2_en_66_qs; + logic dio_pad_sleep_status_2_en_66_wd; + logic dio_pad_sleep_status_2_en_67_qs; + logic dio_pad_sleep_status_2_en_67_wd; + logic dio_pad_sleep_status_2_en_68_qs; + logic dio_pad_sleep_status_2_en_68_wd; + logic dio_pad_sleep_status_2_en_69_qs; + logic dio_pad_sleep_status_2_en_69_wd; + logic dio_pad_sleep_status_2_en_70_qs; + logic dio_pad_sleep_status_2_en_70_wd; + logic dio_pad_sleep_status_2_en_71_qs; + logic dio_pad_sleep_status_2_en_71_wd; + logic dio_pad_sleep_status_2_en_72_qs; + logic dio_pad_sleep_status_2_en_72_wd; + logic dio_pad_sleep_regwen_0_we; + logic dio_pad_sleep_regwen_0_qs; + logic dio_pad_sleep_regwen_0_wd; + logic dio_pad_sleep_regwen_1_we; + logic dio_pad_sleep_regwen_1_qs; + logic dio_pad_sleep_regwen_1_wd; + logic dio_pad_sleep_regwen_2_we; + logic dio_pad_sleep_regwen_2_qs; + logic dio_pad_sleep_regwen_2_wd; + logic dio_pad_sleep_regwen_3_we; + logic dio_pad_sleep_regwen_3_qs; + logic dio_pad_sleep_regwen_3_wd; + logic dio_pad_sleep_regwen_4_we; + logic dio_pad_sleep_regwen_4_qs; + logic dio_pad_sleep_regwen_4_wd; + logic dio_pad_sleep_regwen_5_we; + logic dio_pad_sleep_regwen_5_qs; + logic dio_pad_sleep_regwen_5_wd; + logic dio_pad_sleep_regwen_6_we; + logic dio_pad_sleep_regwen_6_qs; + logic dio_pad_sleep_regwen_6_wd; + logic dio_pad_sleep_regwen_7_we; + logic dio_pad_sleep_regwen_7_qs; + logic dio_pad_sleep_regwen_7_wd; + logic dio_pad_sleep_regwen_8_we; + logic dio_pad_sleep_regwen_8_qs; + logic dio_pad_sleep_regwen_8_wd; + logic dio_pad_sleep_regwen_9_we; + logic dio_pad_sleep_regwen_9_qs; + logic dio_pad_sleep_regwen_9_wd; + logic dio_pad_sleep_regwen_10_we; + logic dio_pad_sleep_regwen_10_qs; + logic dio_pad_sleep_regwen_10_wd; + logic dio_pad_sleep_regwen_11_we; + logic dio_pad_sleep_regwen_11_qs; + logic dio_pad_sleep_regwen_11_wd; + logic dio_pad_sleep_regwen_12_we; + logic dio_pad_sleep_regwen_12_qs; + logic dio_pad_sleep_regwen_12_wd; + logic dio_pad_sleep_regwen_13_we; + logic dio_pad_sleep_regwen_13_qs; + logic dio_pad_sleep_regwen_13_wd; + logic dio_pad_sleep_regwen_14_we; + logic dio_pad_sleep_regwen_14_qs; + logic dio_pad_sleep_regwen_14_wd; + logic dio_pad_sleep_regwen_15_we; + logic dio_pad_sleep_regwen_15_qs; + logic dio_pad_sleep_regwen_15_wd; + logic dio_pad_sleep_regwen_16_we; + logic dio_pad_sleep_regwen_16_qs; + logic dio_pad_sleep_regwen_16_wd; + logic dio_pad_sleep_regwen_17_we; + logic dio_pad_sleep_regwen_17_qs; + logic dio_pad_sleep_regwen_17_wd; + logic dio_pad_sleep_regwen_18_we; + logic dio_pad_sleep_regwen_18_qs; + logic dio_pad_sleep_regwen_18_wd; + logic dio_pad_sleep_regwen_19_we; + logic dio_pad_sleep_regwen_19_qs; + logic dio_pad_sleep_regwen_19_wd; + logic dio_pad_sleep_regwen_20_we; + logic dio_pad_sleep_regwen_20_qs; + logic dio_pad_sleep_regwen_20_wd; + logic dio_pad_sleep_regwen_21_we; + logic dio_pad_sleep_regwen_21_qs; + logic dio_pad_sleep_regwen_21_wd; + logic dio_pad_sleep_regwen_22_we; + logic dio_pad_sleep_regwen_22_qs; + logic dio_pad_sleep_regwen_22_wd; + logic dio_pad_sleep_regwen_23_we; + logic dio_pad_sleep_regwen_23_qs; + logic dio_pad_sleep_regwen_23_wd; + logic dio_pad_sleep_regwen_24_we; + logic dio_pad_sleep_regwen_24_qs; + logic dio_pad_sleep_regwen_24_wd; + logic dio_pad_sleep_regwen_25_we; + logic dio_pad_sleep_regwen_25_qs; + logic dio_pad_sleep_regwen_25_wd; + logic dio_pad_sleep_regwen_26_we; + logic dio_pad_sleep_regwen_26_qs; + logic dio_pad_sleep_regwen_26_wd; + logic dio_pad_sleep_regwen_27_we; + logic dio_pad_sleep_regwen_27_qs; + logic dio_pad_sleep_regwen_27_wd; + logic dio_pad_sleep_regwen_28_we; + logic dio_pad_sleep_regwen_28_qs; + logic dio_pad_sleep_regwen_28_wd; + logic dio_pad_sleep_regwen_29_we; + logic dio_pad_sleep_regwen_29_qs; + logic dio_pad_sleep_regwen_29_wd; + logic dio_pad_sleep_regwen_30_we; + logic dio_pad_sleep_regwen_30_qs; + logic dio_pad_sleep_regwen_30_wd; + logic dio_pad_sleep_regwen_31_we; + logic dio_pad_sleep_regwen_31_qs; + logic dio_pad_sleep_regwen_31_wd; + logic dio_pad_sleep_regwen_32_we; + logic dio_pad_sleep_regwen_32_qs; + logic dio_pad_sleep_regwen_32_wd; + logic dio_pad_sleep_regwen_33_we; + logic dio_pad_sleep_regwen_33_qs; + logic dio_pad_sleep_regwen_33_wd; + logic dio_pad_sleep_regwen_34_we; + logic dio_pad_sleep_regwen_34_qs; + logic dio_pad_sleep_regwen_34_wd; + logic dio_pad_sleep_regwen_35_we; + logic dio_pad_sleep_regwen_35_qs; + logic dio_pad_sleep_regwen_35_wd; + logic dio_pad_sleep_regwen_36_we; + logic dio_pad_sleep_regwen_36_qs; + logic dio_pad_sleep_regwen_36_wd; + logic dio_pad_sleep_regwen_37_we; + logic dio_pad_sleep_regwen_37_qs; + logic dio_pad_sleep_regwen_37_wd; + logic dio_pad_sleep_regwen_38_we; + logic dio_pad_sleep_regwen_38_qs; + logic dio_pad_sleep_regwen_38_wd; + logic dio_pad_sleep_regwen_39_we; + logic dio_pad_sleep_regwen_39_qs; + logic dio_pad_sleep_regwen_39_wd; + logic dio_pad_sleep_regwen_40_we; + logic dio_pad_sleep_regwen_40_qs; + logic dio_pad_sleep_regwen_40_wd; + logic dio_pad_sleep_regwen_41_we; + logic dio_pad_sleep_regwen_41_qs; + logic dio_pad_sleep_regwen_41_wd; + logic dio_pad_sleep_regwen_42_we; + logic dio_pad_sleep_regwen_42_qs; + logic dio_pad_sleep_regwen_42_wd; + logic dio_pad_sleep_regwen_43_we; + logic dio_pad_sleep_regwen_43_qs; + logic dio_pad_sleep_regwen_43_wd; + logic dio_pad_sleep_regwen_44_we; + logic dio_pad_sleep_regwen_44_qs; + logic dio_pad_sleep_regwen_44_wd; + logic dio_pad_sleep_regwen_45_we; + logic dio_pad_sleep_regwen_45_qs; + logic dio_pad_sleep_regwen_45_wd; + logic dio_pad_sleep_regwen_46_we; + logic dio_pad_sleep_regwen_46_qs; + logic dio_pad_sleep_regwen_46_wd; + logic dio_pad_sleep_regwen_47_we; + logic dio_pad_sleep_regwen_47_qs; + logic dio_pad_sleep_regwen_47_wd; + logic dio_pad_sleep_regwen_48_we; + logic dio_pad_sleep_regwen_48_qs; + logic dio_pad_sleep_regwen_48_wd; + logic dio_pad_sleep_regwen_49_we; + logic dio_pad_sleep_regwen_49_qs; + logic dio_pad_sleep_regwen_49_wd; + logic dio_pad_sleep_regwen_50_we; + logic dio_pad_sleep_regwen_50_qs; + logic dio_pad_sleep_regwen_50_wd; + logic dio_pad_sleep_regwen_51_we; + logic dio_pad_sleep_regwen_51_qs; + logic dio_pad_sleep_regwen_51_wd; + logic dio_pad_sleep_regwen_52_we; + logic dio_pad_sleep_regwen_52_qs; + logic dio_pad_sleep_regwen_52_wd; + logic dio_pad_sleep_regwen_53_we; + logic dio_pad_sleep_regwen_53_qs; + logic dio_pad_sleep_regwen_53_wd; + logic dio_pad_sleep_regwen_54_we; + logic dio_pad_sleep_regwen_54_qs; + logic dio_pad_sleep_regwen_54_wd; + logic dio_pad_sleep_regwen_55_we; + logic dio_pad_sleep_regwen_55_qs; + logic dio_pad_sleep_regwen_55_wd; + logic dio_pad_sleep_regwen_56_we; + logic dio_pad_sleep_regwen_56_qs; + logic dio_pad_sleep_regwen_56_wd; + logic dio_pad_sleep_regwen_57_we; + logic dio_pad_sleep_regwen_57_qs; + logic dio_pad_sleep_regwen_57_wd; + logic dio_pad_sleep_regwen_58_we; + logic dio_pad_sleep_regwen_58_qs; + logic dio_pad_sleep_regwen_58_wd; + logic dio_pad_sleep_regwen_59_we; + logic dio_pad_sleep_regwen_59_qs; + logic dio_pad_sleep_regwen_59_wd; + logic dio_pad_sleep_regwen_60_we; + logic dio_pad_sleep_regwen_60_qs; + logic dio_pad_sleep_regwen_60_wd; + logic dio_pad_sleep_regwen_61_we; + logic dio_pad_sleep_regwen_61_qs; + logic dio_pad_sleep_regwen_61_wd; + logic dio_pad_sleep_regwen_62_we; + logic dio_pad_sleep_regwen_62_qs; + logic dio_pad_sleep_regwen_62_wd; + logic dio_pad_sleep_regwen_63_we; + logic dio_pad_sleep_regwen_63_qs; + logic dio_pad_sleep_regwen_63_wd; + logic dio_pad_sleep_regwen_64_we; + logic dio_pad_sleep_regwen_64_qs; + logic dio_pad_sleep_regwen_64_wd; + logic dio_pad_sleep_regwen_65_we; + logic dio_pad_sleep_regwen_65_qs; + logic dio_pad_sleep_regwen_65_wd; + logic dio_pad_sleep_regwen_66_we; + logic dio_pad_sleep_regwen_66_qs; + logic dio_pad_sleep_regwen_66_wd; + logic dio_pad_sleep_regwen_67_we; + logic dio_pad_sleep_regwen_67_qs; + logic dio_pad_sleep_regwen_67_wd; + logic dio_pad_sleep_regwen_68_we; + logic dio_pad_sleep_regwen_68_qs; + logic dio_pad_sleep_regwen_68_wd; + logic dio_pad_sleep_regwen_69_we; + logic dio_pad_sleep_regwen_69_qs; + logic dio_pad_sleep_regwen_69_wd; + logic dio_pad_sleep_regwen_70_we; + logic dio_pad_sleep_regwen_70_qs; + logic dio_pad_sleep_regwen_70_wd; + logic dio_pad_sleep_regwen_71_we; + logic dio_pad_sleep_regwen_71_qs; + logic dio_pad_sleep_regwen_71_wd; + logic dio_pad_sleep_regwen_72_we; + logic dio_pad_sleep_regwen_72_qs; + logic dio_pad_sleep_regwen_72_wd; + logic dio_pad_sleep_en_0_we; + logic dio_pad_sleep_en_0_qs; + logic dio_pad_sleep_en_0_wd; + logic dio_pad_sleep_en_1_we; + logic dio_pad_sleep_en_1_qs; + logic dio_pad_sleep_en_1_wd; + logic dio_pad_sleep_en_2_we; + logic dio_pad_sleep_en_2_qs; + logic dio_pad_sleep_en_2_wd; + logic dio_pad_sleep_en_3_we; + logic dio_pad_sleep_en_3_qs; + logic dio_pad_sleep_en_3_wd; + logic dio_pad_sleep_en_4_we; + logic dio_pad_sleep_en_4_qs; + logic dio_pad_sleep_en_4_wd; + logic dio_pad_sleep_en_5_we; + logic dio_pad_sleep_en_5_qs; + logic dio_pad_sleep_en_5_wd; + logic dio_pad_sleep_en_6_we; + logic dio_pad_sleep_en_6_qs; + logic dio_pad_sleep_en_6_wd; + logic dio_pad_sleep_en_7_we; + logic dio_pad_sleep_en_7_qs; + logic dio_pad_sleep_en_7_wd; + logic dio_pad_sleep_en_8_we; + logic dio_pad_sleep_en_8_qs; + logic dio_pad_sleep_en_8_wd; + logic dio_pad_sleep_en_9_we; + logic dio_pad_sleep_en_9_qs; + logic dio_pad_sleep_en_9_wd; + logic dio_pad_sleep_en_10_we; + logic dio_pad_sleep_en_10_qs; + logic dio_pad_sleep_en_10_wd; + logic dio_pad_sleep_en_11_we; + logic dio_pad_sleep_en_11_qs; + logic dio_pad_sleep_en_11_wd; + logic dio_pad_sleep_en_12_we; + logic dio_pad_sleep_en_12_qs; + logic dio_pad_sleep_en_12_wd; + logic dio_pad_sleep_en_13_we; + logic dio_pad_sleep_en_13_qs; + logic dio_pad_sleep_en_13_wd; + logic dio_pad_sleep_en_14_we; + logic dio_pad_sleep_en_14_qs; + logic dio_pad_sleep_en_14_wd; + logic dio_pad_sleep_en_15_we; + logic dio_pad_sleep_en_15_qs; + logic dio_pad_sleep_en_15_wd; + logic dio_pad_sleep_en_16_we; + logic dio_pad_sleep_en_16_qs; + logic dio_pad_sleep_en_16_wd; + logic dio_pad_sleep_en_17_we; + logic dio_pad_sleep_en_17_qs; + logic dio_pad_sleep_en_17_wd; + logic dio_pad_sleep_en_18_we; + logic dio_pad_sleep_en_18_qs; + logic dio_pad_sleep_en_18_wd; + logic dio_pad_sleep_en_19_we; + logic dio_pad_sleep_en_19_qs; + logic dio_pad_sleep_en_19_wd; + logic dio_pad_sleep_en_20_we; + logic dio_pad_sleep_en_20_qs; + logic dio_pad_sleep_en_20_wd; + logic dio_pad_sleep_en_21_we; + logic dio_pad_sleep_en_21_qs; + logic dio_pad_sleep_en_21_wd; + logic dio_pad_sleep_en_22_we; + logic dio_pad_sleep_en_22_qs; + logic dio_pad_sleep_en_22_wd; + logic dio_pad_sleep_en_23_we; + logic dio_pad_sleep_en_23_qs; + logic dio_pad_sleep_en_23_wd; + logic dio_pad_sleep_en_24_we; + logic dio_pad_sleep_en_24_qs; + logic dio_pad_sleep_en_24_wd; + logic dio_pad_sleep_en_25_we; + logic dio_pad_sleep_en_25_qs; + logic dio_pad_sleep_en_25_wd; + logic dio_pad_sleep_en_26_we; + logic dio_pad_sleep_en_26_qs; + logic dio_pad_sleep_en_26_wd; + logic dio_pad_sleep_en_27_we; + logic dio_pad_sleep_en_27_qs; + logic dio_pad_sleep_en_27_wd; + logic dio_pad_sleep_en_28_we; + logic dio_pad_sleep_en_28_qs; + logic dio_pad_sleep_en_28_wd; + logic dio_pad_sleep_en_29_we; + logic dio_pad_sleep_en_29_qs; + logic dio_pad_sleep_en_29_wd; + logic dio_pad_sleep_en_30_we; + logic dio_pad_sleep_en_30_qs; + logic dio_pad_sleep_en_30_wd; + logic dio_pad_sleep_en_31_we; + logic dio_pad_sleep_en_31_qs; + logic dio_pad_sleep_en_31_wd; + logic dio_pad_sleep_en_32_we; + logic dio_pad_sleep_en_32_qs; + logic dio_pad_sleep_en_32_wd; + logic dio_pad_sleep_en_33_we; + logic dio_pad_sleep_en_33_qs; + logic dio_pad_sleep_en_33_wd; + logic dio_pad_sleep_en_34_we; + logic dio_pad_sleep_en_34_qs; + logic dio_pad_sleep_en_34_wd; + logic dio_pad_sleep_en_35_we; + logic dio_pad_sleep_en_35_qs; + logic dio_pad_sleep_en_35_wd; + logic dio_pad_sleep_en_36_we; + logic dio_pad_sleep_en_36_qs; + logic dio_pad_sleep_en_36_wd; + logic dio_pad_sleep_en_37_we; + logic dio_pad_sleep_en_37_qs; + logic dio_pad_sleep_en_37_wd; + logic dio_pad_sleep_en_38_we; + logic dio_pad_sleep_en_38_qs; + logic dio_pad_sleep_en_38_wd; + logic dio_pad_sleep_en_39_we; + logic dio_pad_sleep_en_39_qs; + logic dio_pad_sleep_en_39_wd; + logic dio_pad_sleep_en_40_we; + logic dio_pad_sleep_en_40_qs; + logic dio_pad_sleep_en_40_wd; + logic dio_pad_sleep_en_41_we; + logic dio_pad_sleep_en_41_qs; + logic dio_pad_sleep_en_41_wd; + logic dio_pad_sleep_en_42_we; + logic dio_pad_sleep_en_42_qs; + logic dio_pad_sleep_en_42_wd; + logic dio_pad_sleep_en_43_we; + logic dio_pad_sleep_en_43_qs; + logic dio_pad_sleep_en_43_wd; + logic dio_pad_sleep_en_44_we; + logic dio_pad_sleep_en_44_qs; + logic dio_pad_sleep_en_44_wd; + logic dio_pad_sleep_en_45_we; + logic dio_pad_sleep_en_45_qs; + logic dio_pad_sleep_en_45_wd; + logic dio_pad_sleep_en_46_we; + logic dio_pad_sleep_en_46_qs; + logic dio_pad_sleep_en_46_wd; + logic dio_pad_sleep_en_47_we; + logic dio_pad_sleep_en_47_qs; + logic dio_pad_sleep_en_47_wd; + logic dio_pad_sleep_en_48_we; + logic dio_pad_sleep_en_48_qs; + logic dio_pad_sleep_en_48_wd; + logic dio_pad_sleep_en_49_we; + logic dio_pad_sleep_en_49_qs; + logic dio_pad_sleep_en_49_wd; + logic dio_pad_sleep_en_50_we; + logic dio_pad_sleep_en_50_qs; + logic dio_pad_sleep_en_50_wd; + logic dio_pad_sleep_en_51_we; + logic dio_pad_sleep_en_51_qs; + logic dio_pad_sleep_en_51_wd; + logic dio_pad_sleep_en_52_we; + logic dio_pad_sleep_en_52_qs; + logic dio_pad_sleep_en_52_wd; + logic dio_pad_sleep_en_53_we; + logic dio_pad_sleep_en_53_qs; + logic dio_pad_sleep_en_53_wd; + logic dio_pad_sleep_en_54_we; + logic dio_pad_sleep_en_54_qs; + logic dio_pad_sleep_en_54_wd; + logic dio_pad_sleep_en_55_we; + logic dio_pad_sleep_en_55_qs; + logic dio_pad_sleep_en_55_wd; + logic dio_pad_sleep_en_56_we; + logic dio_pad_sleep_en_56_qs; + logic dio_pad_sleep_en_56_wd; + logic dio_pad_sleep_en_57_we; + logic dio_pad_sleep_en_57_qs; + logic dio_pad_sleep_en_57_wd; + logic dio_pad_sleep_en_58_we; + logic dio_pad_sleep_en_58_qs; + logic dio_pad_sleep_en_58_wd; + logic dio_pad_sleep_en_59_we; + logic dio_pad_sleep_en_59_qs; + logic dio_pad_sleep_en_59_wd; + logic dio_pad_sleep_en_60_we; + logic dio_pad_sleep_en_60_qs; + logic dio_pad_sleep_en_60_wd; + logic dio_pad_sleep_en_61_we; + logic dio_pad_sleep_en_61_qs; + logic dio_pad_sleep_en_61_wd; + logic dio_pad_sleep_en_62_we; + logic dio_pad_sleep_en_62_qs; + logic dio_pad_sleep_en_62_wd; + logic dio_pad_sleep_en_63_we; + logic dio_pad_sleep_en_63_qs; + logic dio_pad_sleep_en_63_wd; + logic dio_pad_sleep_en_64_we; + logic dio_pad_sleep_en_64_qs; + logic dio_pad_sleep_en_64_wd; + logic dio_pad_sleep_en_65_we; + logic dio_pad_sleep_en_65_qs; + logic dio_pad_sleep_en_65_wd; + logic dio_pad_sleep_en_66_we; + logic dio_pad_sleep_en_66_qs; + logic dio_pad_sleep_en_66_wd; + logic dio_pad_sleep_en_67_we; + logic dio_pad_sleep_en_67_qs; + logic dio_pad_sleep_en_67_wd; + logic dio_pad_sleep_en_68_we; + logic dio_pad_sleep_en_68_qs; + logic dio_pad_sleep_en_68_wd; + logic dio_pad_sleep_en_69_we; + logic dio_pad_sleep_en_69_qs; + logic dio_pad_sleep_en_69_wd; + logic dio_pad_sleep_en_70_we; + logic dio_pad_sleep_en_70_qs; + logic dio_pad_sleep_en_70_wd; + logic dio_pad_sleep_en_71_we; + logic dio_pad_sleep_en_71_qs; + logic dio_pad_sleep_en_71_wd; + logic dio_pad_sleep_en_72_we; + logic dio_pad_sleep_en_72_qs; + logic dio_pad_sleep_en_72_wd; + logic dio_pad_sleep_mode_0_we; + logic [1:0] dio_pad_sleep_mode_0_qs; + logic [1:0] dio_pad_sleep_mode_0_wd; + logic dio_pad_sleep_mode_1_we; + logic [1:0] dio_pad_sleep_mode_1_qs; + logic [1:0] dio_pad_sleep_mode_1_wd; + logic dio_pad_sleep_mode_2_we; + logic [1:0] dio_pad_sleep_mode_2_qs; + logic [1:0] dio_pad_sleep_mode_2_wd; + logic dio_pad_sleep_mode_3_we; + logic [1:0] dio_pad_sleep_mode_3_qs; + logic [1:0] dio_pad_sleep_mode_3_wd; + logic dio_pad_sleep_mode_4_we; + logic [1:0] dio_pad_sleep_mode_4_qs; + logic [1:0] dio_pad_sleep_mode_4_wd; + logic dio_pad_sleep_mode_5_we; + logic [1:0] dio_pad_sleep_mode_5_qs; + logic [1:0] dio_pad_sleep_mode_5_wd; + logic dio_pad_sleep_mode_6_we; + logic [1:0] dio_pad_sleep_mode_6_qs; + logic [1:0] dio_pad_sleep_mode_6_wd; + logic dio_pad_sleep_mode_7_we; + logic [1:0] dio_pad_sleep_mode_7_qs; + logic [1:0] dio_pad_sleep_mode_7_wd; + logic dio_pad_sleep_mode_8_we; + logic [1:0] dio_pad_sleep_mode_8_qs; + logic [1:0] dio_pad_sleep_mode_8_wd; + logic dio_pad_sleep_mode_9_we; + logic [1:0] dio_pad_sleep_mode_9_qs; + logic [1:0] dio_pad_sleep_mode_9_wd; + logic dio_pad_sleep_mode_10_we; + logic [1:0] dio_pad_sleep_mode_10_qs; + logic [1:0] dio_pad_sleep_mode_10_wd; + logic dio_pad_sleep_mode_11_we; + logic [1:0] dio_pad_sleep_mode_11_qs; + logic [1:0] dio_pad_sleep_mode_11_wd; + logic dio_pad_sleep_mode_12_we; + logic [1:0] dio_pad_sleep_mode_12_qs; + logic [1:0] dio_pad_sleep_mode_12_wd; + logic dio_pad_sleep_mode_13_we; + logic [1:0] dio_pad_sleep_mode_13_qs; + logic [1:0] dio_pad_sleep_mode_13_wd; + logic dio_pad_sleep_mode_14_we; + logic [1:0] dio_pad_sleep_mode_14_qs; + logic [1:0] dio_pad_sleep_mode_14_wd; + logic dio_pad_sleep_mode_15_we; + logic [1:0] dio_pad_sleep_mode_15_qs; + logic [1:0] dio_pad_sleep_mode_15_wd; + logic dio_pad_sleep_mode_16_we; + logic [1:0] dio_pad_sleep_mode_16_qs; + logic [1:0] dio_pad_sleep_mode_16_wd; + logic dio_pad_sleep_mode_17_we; + logic [1:0] dio_pad_sleep_mode_17_qs; + logic [1:0] dio_pad_sleep_mode_17_wd; + logic dio_pad_sleep_mode_18_we; + logic [1:0] dio_pad_sleep_mode_18_qs; + logic [1:0] dio_pad_sleep_mode_18_wd; + logic dio_pad_sleep_mode_19_we; + logic [1:0] dio_pad_sleep_mode_19_qs; + logic [1:0] dio_pad_sleep_mode_19_wd; + logic dio_pad_sleep_mode_20_we; + logic [1:0] dio_pad_sleep_mode_20_qs; + logic [1:0] dio_pad_sleep_mode_20_wd; + logic dio_pad_sleep_mode_21_we; + logic [1:0] dio_pad_sleep_mode_21_qs; + logic [1:0] dio_pad_sleep_mode_21_wd; + logic dio_pad_sleep_mode_22_we; + logic [1:0] dio_pad_sleep_mode_22_qs; + logic [1:0] dio_pad_sleep_mode_22_wd; + logic dio_pad_sleep_mode_23_we; + logic [1:0] dio_pad_sleep_mode_23_qs; + logic [1:0] dio_pad_sleep_mode_23_wd; + logic dio_pad_sleep_mode_24_we; + logic [1:0] dio_pad_sleep_mode_24_qs; + logic [1:0] dio_pad_sleep_mode_24_wd; + logic dio_pad_sleep_mode_25_we; + logic [1:0] dio_pad_sleep_mode_25_qs; + logic [1:0] dio_pad_sleep_mode_25_wd; + logic dio_pad_sleep_mode_26_we; + logic [1:0] dio_pad_sleep_mode_26_qs; + logic [1:0] dio_pad_sleep_mode_26_wd; + logic dio_pad_sleep_mode_27_we; + logic [1:0] dio_pad_sleep_mode_27_qs; + logic [1:0] dio_pad_sleep_mode_27_wd; + logic dio_pad_sleep_mode_28_we; + logic [1:0] dio_pad_sleep_mode_28_qs; + logic [1:0] dio_pad_sleep_mode_28_wd; + logic dio_pad_sleep_mode_29_we; + logic [1:0] dio_pad_sleep_mode_29_qs; + logic [1:0] dio_pad_sleep_mode_29_wd; + logic dio_pad_sleep_mode_30_we; + logic [1:0] dio_pad_sleep_mode_30_qs; + logic [1:0] dio_pad_sleep_mode_30_wd; + logic dio_pad_sleep_mode_31_we; + logic [1:0] dio_pad_sleep_mode_31_qs; + logic [1:0] dio_pad_sleep_mode_31_wd; + logic dio_pad_sleep_mode_32_we; + logic [1:0] dio_pad_sleep_mode_32_qs; + logic [1:0] dio_pad_sleep_mode_32_wd; + logic dio_pad_sleep_mode_33_we; + logic [1:0] dio_pad_sleep_mode_33_qs; + logic [1:0] dio_pad_sleep_mode_33_wd; + logic dio_pad_sleep_mode_34_we; + logic [1:0] dio_pad_sleep_mode_34_qs; + logic [1:0] dio_pad_sleep_mode_34_wd; + logic dio_pad_sleep_mode_35_we; + logic [1:0] dio_pad_sleep_mode_35_qs; + logic [1:0] dio_pad_sleep_mode_35_wd; + logic dio_pad_sleep_mode_36_we; + logic [1:0] dio_pad_sleep_mode_36_qs; + logic [1:0] dio_pad_sleep_mode_36_wd; + logic dio_pad_sleep_mode_37_we; + logic [1:0] dio_pad_sleep_mode_37_qs; + logic [1:0] dio_pad_sleep_mode_37_wd; + logic dio_pad_sleep_mode_38_we; + logic [1:0] dio_pad_sleep_mode_38_qs; + logic [1:0] dio_pad_sleep_mode_38_wd; + logic dio_pad_sleep_mode_39_we; + logic [1:0] dio_pad_sleep_mode_39_qs; + logic [1:0] dio_pad_sleep_mode_39_wd; + logic dio_pad_sleep_mode_40_we; + logic [1:0] dio_pad_sleep_mode_40_qs; + logic [1:0] dio_pad_sleep_mode_40_wd; + logic dio_pad_sleep_mode_41_we; + logic [1:0] dio_pad_sleep_mode_41_qs; + logic [1:0] dio_pad_sleep_mode_41_wd; + logic dio_pad_sleep_mode_42_we; + logic [1:0] dio_pad_sleep_mode_42_qs; + logic [1:0] dio_pad_sleep_mode_42_wd; + logic dio_pad_sleep_mode_43_we; + logic [1:0] dio_pad_sleep_mode_43_qs; + logic [1:0] dio_pad_sleep_mode_43_wd; + logic dio_pad_sleep_mode_44_we; + logic [1:0] dio_pad_sleep_mode_44_qs; + logic [1:0] dio_pad_sleep_mode_44_wd; + logic dio_pad_sleep_mode_45_we; + logic [1:0] dio_pad_sleep_mode_45_qs; + logic [1:0] dio_pad_sleep_mode_45_wd; + logic dio_pad_sleep_mode_46_we; + logic [1:0] dio_pad_sleep_mode_46_qs; + logic [1:0] dio_pad_sleep_mode_46_wd; + logic dio_pad_sleep_mode_47_we; + logic [1:0] dio_pad_sleep_mode_47_qs; + logic [1:0] dio_pad_sleep_mode_47_wd; + logic dio_pad_sleep_mode_48_we; + logic [1:0] dio_pad_sleep_mode_48_qs; + logic [1:0] dio_pad_sleep_mode_48_wd; + logic dio_pad_sleep_mode_49_we; + logic [1:0] dio_pad_sleep_mode_49_qs; + logic [1:0] dio_pad_sleep_mode_49_wd; + logic dio_pad_sleep_mode_50_we; + logic [1:0] dio_pad_sleep_mode_50_qs; + logic [1:0] dio_pad_sleep_mode_50_wd; + logic dio_pad_sleep_mode_51_we; + logic [1:0] dio_pad_sleep_mode_51_qs; + logic [1:0] dio_pad_sleep_mode_51_wd; + logic dio_pad_sleep_mode_52_we; + logic [1:0] dio_pad_sleep_mode_52_qs; + logic [1:0] dio_pad_sleep_mode_52_wd; + logic dio_pad_sleep_mode_53_we; + logic [1:0] dio_pad_sleep_mode_53_qs; + logic [1:0] dio_pad_sleep_mode_53_wd; + logic dio_pad_sleep_mode_54_we; + logic [1:0] dio_pad_sleep_mode_54_qs; + logic [1:0] dio_pad_sleep_mode_54_wd; + logic dio_pad_sleep_mode_55_we; + logic [1:0] dio_pad_sleep_mode_55_qs; + logic [1:0] dio_pad_sleep_mode_55_wd; + logic dio_pad_sleep_mode_56_we; + logic [1:0] dio_pad_sleep_mode_56_qs; + logic [1:0] dio_pad_sleep_mode_56_wd; + logic dio_pad_sleep_mode_57_we; + logic [1:0] dio_pad_sleep_mode_57_qs; + logic [1:0] dio_pad_sleep_mode_57_wd; + logic dio_pad_sleep_mode_58_we; + logic [1:0] dio_pad_sleep_mode_58_qs; + logic [1:0] dio_pad_sleep_mode_58_wd; + logic dio_pad_sleep_mode_59_we; + logic [1:0] dio_pad_sleep_mode_59_qs; + logic [1:0] dio_pad_sleep_mode_59_wd; + logic dio_pad_sleep_mode_60_we; + logic [1:0] dio_pad_sleep_mode_60_qs; + logic [1:0] dio_pad_sleep_mode_60_wd; + logic dio_pad_sleep_mode_61_we; + logic [1:0] dio_pad_sleep_mode_61_qs; + logic [1:0] dio_pad_sleep_mode_61_wd; + logic dio_pad_sleep_mode_62_we; + logic [1:0] dio_pad_sleep_mode_62_qs; + logic [1:0] dio_pad_sleep_mode_62_wd; + logic dio_pad_sleep_mode_63_we; + logic [1:0] dio_pad_sleep_mode_63_qs; + logic [1:0] dio_pad_sleep_mode_63_wd; + logic dio_pad_sleep_mode_64_we; + logic [1:0] dio_pad_sleep_mode_64_qs; + logic [1:0] dio_pad_sleep_mode_64_wd; + logic dio_pad_sleep_mode_65_we; + logic [1:0] dio_pad_sleep_mode_65_qs; + logic [1:0] dio_pad_sleep_mode_65_wd; + logic dio_pad_sleep_mode_66_we; + logic [1:0] dio_pad_sleep_mode_66_qs; + logic [1:0] dio_pad_sleep_mode_66_wd; + logic dio_pad_sleep_mode_67_we; + logic [1:0] dio_pad_sleep_mode_67_qs; + logic [1:0] dio_pad_sleep_mode_67_wd; + logic dio_pad_sleep_mode_68_we; + logic [1:0] dio_pad_sleep_mode_68_qs; + logic [1:0] dio_pad_sleep_mode_68_wd; + logic dio_pad_sleep_mode_69_we; + logic [1:0] dio_pad_sleep_mode_69_qs; + logic [1:0] dio_pad_sleep_mode_69_wd; + logic dio_pad_sleep_mode_70_we; + logic [1:0] dio_pad_sleep_mode_70_qs; + logic [1:0] dio_pad_sleep_mode_70_wd; + logic dio_pad_sleep_mode_71_we; + logic [1:0] dio_pad_sleep_mode_71_qs; + logic [1:0] dio_pad_sleep_mode_71_wd; + logic dio_pad_sleep_mode_72_we; + logic [1:0] dio_pad_sleep_mode_72_qs; + logic [1:0] dio_pad_sleep_mode_72_wd; + logic wkup_detector_regwen_0_we; + logic wkup_detector_regwen_0_qs; + logic wkup_detector_regwen_0_wd; + logic wkup_detector_regwen_1_we; + logic wkup_detector_regwen_1_qs; + logic wkup_detector_regwen_1_wd; + logic wkup_detector_regwen_2_we; + logic wkup_detector_regwen_2_qs; + logic wkup_detector_regwen_2_wd; + logic wkup_detector_regwen_3_we; + logic wkup_detector_regwen_3_qs; + logic wkup_detector_regwen_3_wd; + logic wkup_detector_regwen_4_we; + logic wkup_detector_regwen_4_qs; + logic wkup_detector_regwen_4_wd; + logic wkup_detector_regwen_5_we; + logic wkup_detector_regwen_5_qs; + logic wkup_detector_regwen_5_wd; + logic wkup_detector_regwen_6_we; + logic wkup_detector_regwen_6_qs; + logic wkup_detector_regwen_6_wd; + logic wkup_detector_regwen_7_we; + logic wkup_detector_regwen_7_qs; + logic wkup_detector_regwen_7_wd; + logic wkup_detector_en_0_we; + logic [0:0] wkup_detector_en_0_qs; + logic wkup_detector_en_0_busy; + logic wkup_detector_en_1_we; + logic [0:0] wkup_detector_en_1_qs; + logic wkup_detector_en_1_busy; + logic wkup_detector_en_2_we; + logic [0:0] wkup_detector_en_2_qs; + logic wkup_detector_en_2_busy; + logic wkup_detector_en_3_we; + logic [0:0] wkup_detector_en_3_qs; + logic wkup_detector_en_3_busy; + logic wkup_detector_en_4_we; + logic [0:0] wkup_detector_en_4_qs; + logic wkup_detector_en_4_busy; + logic wkup_detector_en_5_we; + logic [0:0] wkup_detector_en_5_qs; + logic wkup_detector_en_5_busy; + logic wkup_detector_en_6_we; + logic [0:0] wkup_detector_en_6_qs; + logic wkup_detector_en_6_busy; + logic wkup_detector_en_7_we; + logic [0:0] wkup_detector_en_7_qs; + logic wkup_detector_en_7_busy; + logic wkup_detector_0_we; + logic [4:0] wkup_detector_0_qs; + logic wkup_detector_0_busy; + logic wkup_detector_1_we; + logic [4:0] wkup_detector_1_qs; + logic wkup_detector_1_busy; + logic wkup_detector_2_we; + logic [4:0] wkup_detector_2_qs; + logic wkup_detector_2_busy; + logic wkup_detector_3_we; + logic [4:0] wkup_detector_3_qs; + logic wkup_detector_3_busy; + logic wkup_detector_4_we; + logic [4:0] wkup_detector_4_qs; + logic wkup_detector_4_busy; + logic wkup_detector_5_we; + logic [4:0] wkup_detector_5_qs; + logic wkup_detector_5_busy; + logic wkup_detector_6_we; + logic [4:0] wkup_detector_6_qs; + logic wkup_detector_6_busy; + logic wkup_detector_7_we; + logic [4:0] wkup_detector_7_qs; + logic wkup_detector_7_busy; + logic wkup_detector_cnt_th_0_we; + logic [7:0] wkup_detector_cnt_th_0_qs; + logic wkup_detector_cnt_th_0_busy; + logic wkup_detector_cnt_th_1_we; + logic [7:0] wkup_detector_cnt_th_1_qs; + logic wkup_detector_cnt_th_1_busy; + logic wkup_detector_cnt_th_2_we; + logic [7:0] wkup_detector_cnt_th_2_qs; + logic wkup_detector_cnt_th_2_busy; + logic wkup_detector_cnt_th_3_we; + logic [7:0] wkup_detector_cnt_th_3_qs; + logic wkup_detector_cnt_th_3_busy; + logic wkup_detector_cnt_th_4_we; + logic [7:0] wkup_detector_cnt_th_4_qs; + logic wkup_detector_cnt_th_4_busy; + logic wkup_detector_cnt_th_5_we; + logic [7:0] wkup_detector_cnt_th_5_qs; + logic wkup_detector_cnt_th_5_busy; + logic wkup_detector_cnt_th_6_we; + logic [7:0] wkup_detector_cnt_th_6_qs; + logic wkup_detector_cnt_th_6_busy; + logic wkup_detector_cnt_th_7_we; + logic [7:0] wkup_detector_cnt_th_7_qs; + logic wkup_detector_cnt_th_7_busy; + logic wkup_detector_padsel_0_we; + logic [5:0] wkup_detector_padsel_0_qs; + logic [5:0] wkup_detector_padsel_0_wd; + logic wkup_detector_padsel_1_we; + logic [5:0] wkup_detector_padsel_1_qs; + logic [5:0] wkup_detector_padsel_1_wd; + logic wkup_detector_padsel_2_we; + logic [5:0] wkup_detector_padsel_2_qs; + logic [5:0] wkup_detector_padsel_2_wd; + logic wkup_detector_padsel_3_we; + logic [5:0] wkup_detector_padsel_3_qs; + logic [5:0] wkup_detector_padsel_3_wd; + logic wkup_detector_padsel_4_we; + logic [5:0] wkup_detector_padsel_4_qs; + logic [5:0] wkup_detector_padsel_4_wd; + logic wkup_detector_padsel_5_we; + logic [5:0] wkup_detector_padsel_5_qs; + logic [5:0] wkup_detector_padsel_5_wd; + logic wkup_detector_padsel_6_we; + logic [5:0] wkup_detector_padsel_6_qs; + logic [5:0] wkup_detector_padsel_6_wd; + logic wkup_detector_padsel_7_we; + logic [5:0] wkup_detector_padsel_7_qs; + logic [5:0] wkup_detector_padsel_7_wd; + logic wkup_cause_we; + logic [7:0] wkup_cause_qs; + logic wkup_cause_busy; + // Define register CDC handling. + // CDC handling is done on a per-reg instead of per-field boundary. + + logic aon_wkup_detector_en_0_qs_int; + logic [0:0] aon_wkup_detector_en_0_qs; + logic [0:0] aon_wkup_detector_en_0_wdata; + logic aon_wkup_detector_en_0_we; + logic unused_aon_wkup_detector_en_0_wdata; + logic aon_wkup_detector_en_0_regwen; + + always_comb begin + aon_wkup_detector_en_0_qs = 1'h0; + aon_wkup_detector_en_0_qs = aon_wkup_detector_en_0_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_0_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_0_qs), + .src_we_i (wkup_detector_en_0_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_0_busy), + .src_qs_o (wkup_detector_en_0_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_0_qs), + .dst_we_o (aon_wkup_detector_en_0_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_0_regwen), + .dst_wd_o (aon_wkup_detector_en_0_wdata) + ); + assign unused_aon_wkup_detector_en_0_wdata = + ^aon_wkup_detector_en_0_wdata; + + logic aon_wkup_detector_en_1_qs_int; + logic [0:0] aon_wkup_detector_en_1_qs; + logic [0:0] aon_wkup_detector_en_1_wdata; + logic aon_wkup_detector_en_1_we; + logic unused_aon_wkup_detector_en_1_wdata; + logic aon_wkup_detector_en_1_regwen; + + always_comb begin + aon_wkup_detector_en_1_qs = 1'h0; + aon_wkup_detector_en_1_qs = aon_wkup_detector_en_1_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_1_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_1_qs), + .src_we_i (wkup_detector_en_1_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_1_busy), + .src_qs_o (wkup_detector_en_1_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_1_qs), + .dst_we_o (aon_wkup_detector_en_1_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_1_regwen), + .dst_wd_o (aon_wkup_detector_en_1_wdata) + ); + assign unused_aon_wkup_detector_en_1_wdata = + ^aon_wkup_detector_en_1_wdata; + + logic aon_wkup_detector_en_2_qs_int; + logic [0:0] aon_wkup_detector_en_2_qs; + logic [0:0] aon_wkup_detector_en_2_wdata; + logic aon_wkup_detector_en_2_we; + logic unused_aon_wkup_detector_en_2_wdata; + logic aon_wkup_detector_en_2_regwen; + + always_comb begin + aon_wkup_detector_en_2_qs = 1'h0; + aon_wkup_detector_en_2_qs = aon_wkup_detector_en_2_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_2_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_2_qs), + .src_we_i (wkup_detector_en_2_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_2_busy), + .src_qs_o (wkup_detector_en_2_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_2_qs), + .dst_we_o (aon_wkup_detector_en_2_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_2_regwen), + .dst_wd_o (aon_wkup_detector_en_2_wdata) + ); + assign unused_aon_wkup_detector_en_2_wdata = + ^aon_wkup_detector_en_2_wdata; + + logic aon_wkup_detector_en_3_qs_int; + logic [0:0] aon_wkup_detector_en_3_qs; + logic [0:0] aon_wkup_detector_en_3_wdata; + logic aon_wkup_detector_en_3_we; + logic unused_aon_wkup_detector_en_3_wdata; + logic aon_wkup_detector_en_3_regwen; + + always_comb begin + aon_wkup_detector_en_3_qs = 1'h0; + aon_wkup_detector_en_3_qs = aon_wkup_detector_en_3_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_3_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_3_qs), + .src_we_i (wkup_detector_en_3_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_3_busy), + .src_qs_o (wkup_detector_en_3_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_3_qs), + .dst_we_o (aon_wkup_detector_en_3_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_3_regwen), + .dst_wd_o (aon_wkup_detector_en_3_wdata) + ); + assign unused_aon_wkup_detector_en_3_wdata = + ^aon_wkup_detector_en_3_wdata; + + logic aon_wkup_detector_en_4_qs_int; + logic [0:0] aon_wkup_detector_en_4_qs; + logic [0:0] aon_wkup_detector_en_4_wdata; + logic aon_wkup_detector_en_4_we; + logic unused_aon_wkup_detector_en_4_wdata; + logic aon_wkup_detector_en_4_regwen; + + always_comb begin + aon_wkup_detector_en_4_qs = 1'h0; + aon_wkup_detector_en_4_qs = aon_wkup_detector_en_4_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_4_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_4_qs), + .src_we_i (wkup_detector_en_4_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_4_busy), + .src_qs_o (wkup_detector_en_4_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_4_qs), + .dst_we_o (aon_wkup_detector_en_4_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_4_regwen), + .dst_wd_o (aon_wkup_detector_en_4_wdata) + ); + assign unused_aon_wkup_detector_en_4_wdata = + ^aon_wkup_detector_en_4_wdata; + + logic aon_wkup_detector_en_5_qs_int; + logic [0:0] aon_wkup_detector_en_5_qs; + logic [0:0] aon_wkup_detector_en_5_wdata; + logic aon_wkup_detector_en_5_we; + logic unused_aon_wkup_detector_en_5_wdata; + logic aon_wkup_detector_en_5_regwen; + + always_comb begin + aon_wkup_detector_en_5_qs = 1'h0; + aon_wkup_detector_en_5_qs = aon_wkup_detector_en_5_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_5_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_5_qs), + .src_we_i (wkup_detector_en_5_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_5_busy), + .src_qs_o (wkup_detector_en_5_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_5_qs), + .dst_we_o (aon_wkup_detector_en_5_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_5_regwen), + .dst_wd_o (aon_wkup_detector_en_5_wdata) + ); + assign unused_aon_wkup_detector_en_5_wdata = + ^aon_wkup_detector_en_5_wdata; + + logic aon_wkup_detector_en_6_qs_int; + logic [0:0] aon_wkup_detector_en_6_qs; + logic [0:0] aon_wkup_detector_en_6_wdata; + logic aon_wkup_detector_en_6_we; + logic unused_aon_wkup_detector_en_6_wdata; + logic aon_wkup_detector_en_6_regwen; + + always_comb begin + aon_wkup_detector_en_6_qs = 1'h0; + aon_wkup_detector_en_6_qs = aon_wkup_detector_en_6_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_6_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_6_qs), + .src_we_i (wkup_detector_en_6_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_6_busy), + .src_qs_o (wkup_detector_en_6_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_6_qs), + .dst_we_o (aon_wkup_detector_en_6_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_6_regwen), + .dst_wd_o (aon_wkup_detector_en_6_wdata) + ); + assign unused_aon_wkup_detector_en_6_wdata = + ^aon_wkup_detector_en_6_wdata; + + logic aon_wkup_detector_en_7_qs_int; + logic [0:0] aon_wkup_detector_en_7_qs; + logic [0:0] aon_wkup_detector_en_7_wdata; + logic aon_wkup_detector_en_7_we; + logic unused_aon_wkup_detector_en_7_wdata; + logic aon_wkup_detector_en_7_regwen; + + always_comb begin + aon_wkup_detector_en_7_qs = 1'h0; + aon_wkup_detector_en_7_qs = aon_wkup_detector_en_7_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_7_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_7_qs), + .src_we_i (wkup_detector_en_7_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_7_busy), + .src_qs_o (wkup_detector_en_7_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_7_qs), + .dst_we_o (aon_wkup_detector_en_7_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_7_regwen), + .dst_wd_o (aon_wkup_detector_en_7_wdata) + ); + assign unused_aon_wkup_detector_en_7_wdata = + ^aon_wkup_detector_en_7_wdata; + + logic [2:0] aon_wkup_detector_0_mode_0_qs_int; + logic aon_wkup_detector_0_filter_0_qs_int; + logic aon_wkup_detector_0_miodio_0_qs_int; + logic [4:0] aon_wkup_detector_0_qs; + logic [4:0] aon_wkup_detector_0_wdata; + logic aon_wkup_detector_0_we; + logic unused_aon_wkup_detector_0_wdata; + logic aon_wkup_detector_0_regwen; + + always_comb begin + aon_wkup_detector_0_qs = 5'h0; + aon_wkup_detector_0_qs[2:0] = aon_wkup_detector_0_mode_0_qs_int; + aon_wkup_detector_0_qs[3] = aon_wkup_detector_0_filter_0_qs_int; + aon_wkup_detector_0_qs[4] = aon_wkup_detector_0_miodio_0_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_0_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_0_qs), + .src_we_i (wkup_detector_0_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_0_busy), + .src_qs_o (wkup_detector_0_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_0_qs), + .dst_we_o (aon_wkup_detector_0_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_0_regwen), + .dst_wd_o (aon_wkup_detector_0_wdata) + ); + assign unused_aon_wkup_detector_0_wdata = + ^aon_wkup_detector_0_wdata; + + logic [2:0] aon_wkup_detector_1_mode_1_qs_int; + logic aon_wkup_detector_1_filter_1_qs_int; + logic aon_wkup_detector_1_miodio_1_qs_int; + logic [4:0] aon_wkup_detector_1_qs; + logic [4:0] aon_wkup_detector_1_wdata; + logic aon_wkup_detector_1_we; + logic unused_aon_wkup_detector_1_wdata; + logic aon_wkup_detector_1_regwen; + + always_comb begin + aon_wkup_detector_1_qs = 5'h0; + aon_wkup_detector_1_qs[2:0] = aon_wkup_detector_1_mode_1_qs_int; + aon_wkup_detector_1_qs[3] = aon_wkup_detector_1_filter_1_qs_int; + aon_wkup_detector_1_qs[4] = aon_wkup_detector_1_miodio_1_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_1_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_1_qs), + .src_we_i (wkup_detector_1_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_1_busy), + .src_qs_o (wkup_detector_1_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_1_qs), + .dst_we_o (aon_wkup_detector_1_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_1_regwen), + .dst_wd_o (aon_wkup_detector_1_wdata) + ); + assign unused_aon_wkup_detector_1_wdata = + ^aon_wkup_detector_1_wdata; + + logic [2:0] aon_wkup_detector_2_mode_2_qs_int; + logic aon_wkup_detector_2_filter_2_qs_int; + logic aon_wkup_detector_2_miodio_2_qs_int; + logic [4:0] aon_wkup_detector_2_qs; + logic [4:0] aon_wkup_detector_2_wdata; + logic aon_wkup_detector_2_we; + logic unused_aon_wkup_detector_2_wdata; + logic aon_wkup_detector_2_regwen; + + always_comb begin + aon_wkup_detector_2_qs = 5'h0; + aon_wkup_detector_2_qs[2:0] = aon_wkup_detector_2_mode_2_qs_int; + aon_wkup_detector_2_qs[3] = aon_wkup_detector_2_filter_2_qs_int; + aon_wkup_detector_2_qs[4] = aon_wkup_detector_2_miodio_2_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_2_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_2_qs), + .src_we_i (wkup_detector_2_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_2_busy), + .src_qs_o (wkup_detector_2_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_2_qs), + .dst_we_o (aon_wkup_detector_2_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_2_regwen), + .dst_wd_o (aon_wkup_detector_2_wdata) + ); + assign unused_aon_wkup_detector_2_wdata = + ^aon_wkup_detector_2_wdata; + + logic [2:0] aon_wkup_detector_3_mode_3_qs_int; + logic aon_wkup_detector_3_filter_3_qs_int; + logic aon_wkup_detector_3_miodio_3_qs_int; + logic [4:0] aon_wkup_detector_3_qs; + logic [4:0] aon_wkup_detector_3_wdata; + logic aon_wkup_detector_3_we; + logic unused_aon_wkup_detector_3_wdata; + logic aon_wkup_detector_3_regwen; + + always_comb begin + aon_wkup_detector_3_qs = 5'h0; + aon_wkup_detector_3_qs[2:0] = aon_wkup_detector_3_mode_3_qs_int; + aon_wkup_detector_3_qs[3] = aon_wkup_detector_3_filter_3_qs_int; + aon_wkup_detector_3_qs[4] = aon_wkup_detector_3_miodio_3_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_3_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_3_qs), + .src_we_i (wkup_detector_3_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_3_busy), + .src_qs_o (wkup_detector_3_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_3_qs), + .dst_we_o (aon_wkup_detector_3_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_3_regwen), + .dst_wd_o (aon_wkup_detector_3_wdata) + ); + assign unused_aon_wkup_detector_3_wdata = + ^aon_wkup_detector_3_wdata; + + logic [2:0] aon_wkup_detector_4_mode_4_qs_int; + logic aon_wkup_detector_4_filter_4_qs_int; + logic aon_wkup_detector_4_miodio_4_qs_int; + logic [4:0] aon_wkup_detector_4_qs; + logic [4:0] aon_wkup_detector_4_wdata; + logic aon_wkup_detector_4_we; + logic unused_aon_wkup_detector_4_wdata; + logic aon_wkup_detector_4_regwen; + + always_comb begin + aon_wkup_detector_4_qs = 5'h0; + aon_wkup_detector_4_qs[2:0] = aon_wkup_detector_4_mode_4_qs_int; + aon_wkup_detector_4_qs[3] = aon_wkup_detector_4_filter_4_qs_int; + aon_wkup_detector_4_qs[4] = aon_wkup_detector_4_miodio_4_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_4_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_4_qs), + .src_we_i (wkup_detector_4_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_4_busy), + .src_qs_o (wkup_detector_4_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_4_qs), + .dst_we_o (aon_wkup_detector_4_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_4_regwen), + .dst_wd_o (aon_wkup_detector_4_wdata) + ); + assign unused_aon_wkup_detector_4_wdata = + ^aon_wkup_detector_4_wdata; + + logic [2:0] aon_wkup_detector_5_mode_5_qs_int; + logic aon_wkup_detector_5_filter_5_qs_int; + logic aon_wkup_detector_5_miodio_5_qs_int; + logic [4:0] aon_wkup_detector_5_qs; + logic [4:0] aon_wkup_detector_5_wdata; + logic aon_wkup_detector_5_we; + logic unused_aon_wkup_detector_5_wdata; + logic aon_wkup_detector_5_regwen; + + always_comb begin + aon_wkup_detector_5_qs = 5'h0; + aon_wkup_detector_5_qs[2:0] = aon_wkup_detector_5_mode_5_qs_int; + aon_wkup_detector_5_qs[3] = aon_wkup_detector_5_filter_5_qs_int; + aon_wkup_detector_5_qs[4] = aon_wkup_detector_5_miodio_5_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_5_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_5_qs), + .src_we_i (wkup_detector_5_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_5_busy), + .src_qs_o (wkup_detector_5_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_5_qs), + .dst_we_o (aon_wkup_detector_5_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_5_regwen), + .dst_wd_o (aon_wkup_detector_5_wdata) + ); + assign unused_aon_wkup_detector_5_wdata = + ^aon_wkup_detector_5_wdata; + + logic [2:0] aon_wkup_detector_6_mode_6_qs_int; + logic aon_wkup_detector_6_filter_6_qs_int; + logic aon_wkup_detector_6_miodio_6_qs_int; + logic [4:0] aon_wkup_detector_6_qs; + logic [4:0] aon_wkup_detector_6_wdata; + logic aon_wkup_detector_6_we; + logic unused_aon_wkup_detector_6_wdata; + logic aon_wkup_detector_6_regwen; + + always_comb begin + aon_wkup_detector_6_qs = 5'h0; + aon_wkup_detector_6_qs[2:0] = aon_wkup_detector_6_mode_6_qs_int; + aon_wkup_detector_6_qs[3] = aon_wkup_detector_6_filter_6_qs_int; + aon_wkup_detector_6_qs[4] = aon_wkup_detector_6_miodio_6_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_6_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_6_qs), + .src_we_i (wkup_detector_6_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_6_busy), + .src_qs_o (wkup_detector_6_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_6_qs), + .dst_we_o (aon_wkup_detector_6_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_6_regwen), + .dst_wd_o (aon_wkup_detector_6_wdata) + ); + assign unused_aon_wkup_detector_6_wdata = + ^aon_wkup_detector_6_wdata; + + logic [2:0] aon_wkup_detector_7_mode_7_qs_int; + logic aon_wkup_detector_7_filter_7_qs_int; + logic aon_wkup_detector_7_miodio_7_qs_int; + logic [4:0] aon_wkup_detector_7_qs; + logic [4:0] aon_wkup_detector_7_wdata; + logic aon_wkup_detector_7_we; + logic unused_aon_wkup_detector_7_wdata; + logic aon_wkup_detector_7_regwen; + + always_comb begin + aon_wkup_detector_7_qs = 5'h0; + aon_wkup_detector_7_qs[2:0] = aon_wkup_detector_7_mode_7_qs_int; + aon_wkup_detector_7_qs[3] = aon_wkup_detector_7_filter_7_qs_int; + aon_wkup_detector_7_qs[4] = aon_wkup_detector_7_miodio_7_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_7_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_7_qs), + .src_we_i (wkup_detector_7_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_7_busy), + .src_qs_o (wkup_detector_7_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_7_qs), + .dst_we_o (aon_wkup_detector_7_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_7_regwen), + .dst_wd_o (aon_wkup_detector_7_wdata) + ); + assign unused_aon_wkup_detector_7_wdata = + ^aon_wkup_detector_7_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_0_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_0_qs; + logic [7:0] aon_wkup_detector_cnt_th_0_wdata; + logic aon_wkup_detector_cnt_th_0_we; + logic unused_aon_wkup_detector_cnt_th_0_wdata; + logic aon_wkup_detector_cnt_th_0_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_0_qs = 8'h0; + aon_wkup_detector_cnt_th_0_qs = aon_wkup_detector_cnt_th_0_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_0_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_0_qs), + .src_we_i (wkup_detector_cnt_th_0_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_0_busy), + .src_qs_o (wkup_detector_cnt_th_0_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_0_qs), + .dst_we_o (aon_wkup_detector_cnt_th_0_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_0_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_0_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_0_wdata = + ^aon_wkup_detector_cnt_th_0_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_1_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_1_qs; + logic [7:0] aon_wkup_detector_cnt_th_1_wdata; + logic aon_wkup_detector_cnt_th_1_we; + logic unused_aon_wkup_detector_cnt_th_1_wdata; + logic aon_wkup_detector_cnt_th_1_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_1_qs = 8'h0; + aon_wkup_detector_cnt_th_1_qs = aon_wkup_detector_cnt_th_1_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_1_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_1_qs), + .src_we_i (wkup_detector_cnt_th_1_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_1_busy), + .src_qs_o (wkup_detector_cnt_th_1_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_1_qs), + .dst_we_o (aon_wkup_detector_cnt_th_1_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_1_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_1_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_1_wdata = + ^aon_wkup_detector_cnt_th_1_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_2_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_2_qs; + logic [7:0] aon_wkup_detector_cnt_th_2_wdata; + logic aon_wkup_detector_cnt_th_2_we; + logic unused_aon_wkup_detector_cnt_th_2_wdata; + logic aon_wkup_detector_cnt_th_2_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_2_qs = 8'h0; + aon_wkup_detector_cnt_th_2_qs = aon_wkup_detector_cnt_th_2_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_2_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_2_qs), + .src_we_i (wkup_detector_cnt_th_2_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_2_busy), + .src_qs_o (wkup_detector_cnt_th_2_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_2_qs), + .dst_we_o (aon_wkup_detector_cnt_th_2_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_2_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_2_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_2_wdata = + ^aon_wkup_detector_cnt_th_2_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_3_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_3_qs; + logic [7:0] aon_wkup_detector_cnt_th_3_wdata; + logic aon_wkup_detector_cnt_th_3_we; + logic unused_aon_wkup_detector_cnt_th_3_wdata; + logic aon_wkup_detector_cnt_th_3_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_3_qs = 8'h0; + aon_wkup_detector_cnt_th_3_qs = aon_wkup_detector_cnt_th_3_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_3_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_3_qs), + .src_we_i (wkup_detector_cnt_th_3_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_3_busy), + .src_qs_o (wkup_detector_cnt_th_3_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_3_qs), + .dst_we_o (aon_wkup_detector_cnt_th_3_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_3_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_3_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_3_wdata = + ^aon_wkup_detector_cnt_th_3_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_4_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_4_qs; + logic [7:0] aon_wkup_detector_cnt_th_4_wdata; + logic aon_wkup_detector_cnt_th_4_we; + logic unused_aon_wkup_detector_cnt_th_4_wdata; + logic aon_wkup_detector_cnt_th_4_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_4_qs = 8'h0; + aon_wkup_detector_cnt_th_4_qs = aon_wkup_detector_cnt_th_4_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_4_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_4_qs), + .src_we_i (wkup_detector_cnt_th_4_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_4_busy), + .src_qs_o (wkup_detector_cnt_th_4_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_4_qs), + .dst_we_o (aon_wkup_detector_cnt_th_4_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_4_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_4_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_4_wdata = + ^aon_wkup_detector_cnt_th_4_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_5_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_5_qs; + logic [7:0] aon_wkup_detector_cnt_th_5_wdata; + logic aon_wkup_detector_cnt_th_5_we; + logic unused_aon_wkup_detector_cnt_th_5_wdata; + logic aon_wkup_detector_cnt_th_5_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_5_qs = 8'h0; + aon_wkup_detector_cnt_th_5_qs = aon_wkup_detector_cnt_th_5_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_5_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_5_qs), + .src_we_i (wkup_detector_cnt_th_5_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_5_busy), + .src_qs_o (wkup_detector_cnt_th_5_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_5_qs), + .dst_we_o (aon_wkup_detector_cnt_th_5_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_5_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_5_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_5_wdata = + ^aon_wkup_detector_cnt_th_5_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_6_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_6_qs; + logic [7:0] aon_wkup_detector_cnt_th_6_wdata; + logic aon_wkup_detector_cnt_th_6_we; + logic unused_aon_wkup_detector_cnt_th_6_wdata; + logic aon_wkup_detector_cnt_th_6_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_6_qs = 8'h0; + aon_wkup_detector_cnt_th_6_qs = aon_wkup_detector_cnt_th_6_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_6_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_6_qs), + .src_we_i (wkup_detector_cnt_th_6_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_6_busy), + .src_qs_o (wkup_detector_cnt_th_6_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_6_qs), + .dst_we_o (aon_wkup_detector_cnt_th_6_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_6_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_6_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_6_wdata = + ^aon_wkup_detector_cnt_th_6_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_7_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_7_qs; + logic [7:0] aon_wkup_detector_cnt_th_7_wdata; + logic aon_wkup_detector_cnt_th_7_we; + logic unused_aon_wkup_detector_cnt_th_7_wdata; + logic aon_wkup_detector_cnt_th_7_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_7_qs = 8'h0; + aon_wkup_detector_cnt_th_7_qs = aon_wkup_detector_cnt_th_7_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_7_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_7_qs), + .src_we_i (wkup_detector_cnt_th_7_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_7_busy), + .src_qs_o (wkup_detector_cnt_th_7_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_7_qs), + .dst_we_o (aon_wkup_detector_cnt_th_7_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_7_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_7_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_7_wdata = + ^aon_wkup_detector_cnt_th_7_wdata; + + logic aon_wkup_cause_cause_0_ds_int; + logic aon_wkup_cause_cause_0_qs_int; + logic aon_wkup_cause_cause_1_ds_int; + logic aon_wkup_cause_cause_1_qs_int; + logic aon_wkup_cause_cause_2_ds_int; + logic aon_wkup_cause_cause_2_qs_int; + logic aon_wkup_cause_cause_3_ds_int; + logic aon_wkup_cause_cause_3_qs_int; + logic aon_wkup_cause_cause_4_ds_int; + logic aon_wkup_cause_cause_4_qs_int; + logic aon_wkup_cause_cause_5_ds_int; + logic aon_wkup_cause_cause_5_qs_int; + logic aon_wkup_cause_cause_6_ds_int; + logic aon_wkup_cause_cause_6_qs_int; + logic aon_wkup_cause_cause_7_ds_int; + logic aon_wkup_cause_cause_7_qs_int; + logic [7:0] aon_wkup_cause_ds; + logic aon_wkup_cause_qe; + logic [7:0] aon_wkup_cause_qs; + logic [7:0] aon_wkup_cause_wdata; + logic aon_wkup_cause_we; + logic unused_aon_wkup_cause_wdata; + + always_comb begin + aon_wkup_cause_qs = 8'h0; + aon_wkup_cause_ds = 8'h0; + aon_wkup_cause_ds[0] = aon_wkup_cause_cause_0_ds_int; + aon_wkup_cause_qs[0] = aon_wkup_cause_cause_0_qs_int; + aon_wkup_cause_ds[1] = aon_wkup_cause_cause_1_ds_int; + aon_wkup_cause_qs[1] = aon_wkup_cause_cause_1_qs_int; + aon_wkup_cause_ds[2] = aon_wkup_cause_cause_2_ds_int; + aon_wkup_cause_qs[2] = aon_wkup_cause_cause_2_qs_int; + aon_wkup_cause_ds[3] = aon_wkup_cause_cause_3_ds_int; + aon_wkup_cause_qs[3] = aon_wkup_cause_cause_3_qs_int; + aon_wkup_cause_ds[4] = aon_wkup_cause_cause_4_ds_int; + aon_wkup_cause_qs[4] = aon_wkup_cause_cause_4_qs_int; + aon_wkup_cause_ds[5] = aon_wkup_cause_cause_5_ds_int; + aon_wkup_cause_qs[5] = aon_wkup_cause_cause_5_qs_int; + aon_wkup_cause_ds[6] = aon_wkup_cause_cause_6_ds_int; + aon_wkup_cause_qs[6] = aon_wkup_cause_cause_6_qs_int; + aon_wkup_cause_ds[7] = aon_wkup_cause_cause_7_ds_int; + aon_wkup_cause_qs[7] = aon_wkup_cause_cause_7_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(1) + ) u_wkup_cause_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i ('0), + .src_we_i (wkup_cause_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_cause_busy), + .src_qs_o (wkup_cause_qs), // for software read back + .dst_update_i (aon_wkup_cause_qe), + .dst_ds_i (aon_wkup_cause_ds), + .dst_qs_i (aon_wkup_cause_qs), + .dst_we_o (aon_wkup_cause_we), + .dst_re_o (), + .dst_regwen_o (), + .dst_wd_o (aon_wkup_cause_wdata) + ); + assign unused_aon_wkup_cause_wdata = + ^aon_wkup_cause_wdata; + + // Register instances + // R[alert_test]: V(True) + logic alert_test_qe; + logic [0:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_alert_test ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.qe = alert_test_qe; + + + // Subregister 0 of Multireg mio_periph_insel_regwen + // R[mio_periph_insel_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_periph_insel_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_regwen_0_we), + .wd (mio_periph_insel_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_regwen_0_qs) + ); + + + // Subregister 1 of Multireg mio_periph_insel_regwen + // R[mio_periph_insel_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_periph_insel_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_regwen_1_we), + .wd (mio_periph_insel_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_regwen_1_qs) + ); + + + // Subregister 2 of Multireg mio_periph_insel_regwen + // R[mio_periph_insel_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_periph_insel_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_regwen_2_we), + .wd (mio_periph_insel_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_regwen_2_qs) + ); + + + // Subregister 3 of Multireg mio_periph_insel_regwen + // R[mio_periph_insel_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_periph_insel_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_regwen_3_we), + .wd (mio_periph_insel_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_regwen_3_qs) + ); + + + // Subregister 0 of Multireg mio_periph_insel + // R[mio_periph_insel_0]: V(False) + // Create REGWEN-gated WE signal + logic mio_periph_insel_0_gated_we; + assign mio_periph_insel_0_gated_we = mio_periph_insel_0_we & mio_periph_insel_regwen_0_qs; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_mio_periph_insel_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_0_gated_we), + .wd (mio_periph_insel_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_periph_insel[0].q), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_0_qs) + ); + + + // Subregister 1 of Multireg mio_periph_insel + // R[mio_periph_insel_1]: V(False) + // Create REGWEN-gated WE signal + logic mio_periph_insel_1_gated_we; + assign mio_periph_insel_1_gated_we = mio_periph_insel_1_we & mio_periph_insel_regwen_1_qs; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_mio_periph_insel_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_1_gated_we), + .wd (mio_periph_insel_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_periph_insel[1].q), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_1_qs) + ); + + + // Subregister 2 of Multireg mio_periph_insel + // R[mio_periph_insel_2]: V(False) + // Create REGWEN-gated WE signal + logic mio_periph_insel_2_gated_we; + assign mio_periph_insel_2_gated_we = mio_periph_insel_2_we & mio_periph_insel_regwen_2_qs; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_mio_periph_insel_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_2_gated_we), + .wd (mio_periph_insel_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_periph_insel[2].q), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_2_qs) + ); + + + // Subregister 3 of Multireg mio_periph_insel + // R[mio_periph_insel_3]: V(False) + // Create REGWEN-gated WE signal + logic mio_periph_insel_3_gated_we; + assign mio_periph_insel_3_gated_we = mio_periph_insel_3_we & mio_periph_insel_regwen_3_qs; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_mio_periph_insel_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_3_gated_we), + .wd (mio_periph_insel_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_periph_insel[3].q), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_3_qs) + ); + + + // Subregister 0 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_0_we), + .wd (mio_outsel_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_0_qs) + ); + + + // Subregister 1 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_1_we), + .wd (mio_outsel_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_1_qs) + ); + + + // Subregister 2 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_2_we), + .wd (mio_outsel_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_2_qs) + ); + + + // Subregister 3 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_3_we), + .wd (mio_outsel_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_3_qs) + ); + + + // Subregister 4 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_4_we), + .wd (mio_outsel_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_4_qs) + ); + + + // Subregister 5 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_5_we), + .wd (mio_outsel_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_5_qs) + ); + + + // Subregister 6 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_6_we), + .wd (mio_outsel_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_6_qs) + ); + + + // Subregister 7 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_7_we), + .wd (mio_outsel_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_7_qs) + ); + + + // Subregister 8 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_8_we), + .wd (mio_outsel_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_8_qs) + ); + + + // Subregister 9 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_9_we), + .wd (mio_outsel_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_9_qs) + ); + + + // Subregister 10 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_10_we), + .wd (mio_outsel_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_10_qs) + ); + + + // Subregister 11 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_11_we), + .wd (mio_outsel_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_11_qs) + ); + + + // Subregister 0 of Multireg mio_outsel + // R[mio_outsel_0]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_0_gated_we; + assign mio_outsel_0_gated_we = mio_outsel_0_we & mio_outsel_regwen_0_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_0_gated_we), + .wd (mio_outsel_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[0].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_0_qs) + ); + + + // Subregister 1 of Multireg mio_outsel + // R[mio_outsel_1]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_1_gated_we; + assign mio_outsel_1_gated_we = mio_outsel_1_we & mio_outsel_regwen_1_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_1_gated_we), + .wd (mio_outsel_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[1].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_1_qs) + ); + + + // Subregister 2 of Multireg mio_outsel + // R[mio_outsel_2]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_2_gated_we; + assign mio_outsel_2_gated_we = mio_outsel_2_we & mio_outsel_regwen_2_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_2_gated_we), + .wd (mio_outsel_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[2].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_2_qs) + ); + + + // Subregister 3 of Multireg mio_outsel + // R[mio_outsel_3]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_3_gated_we; + assign mio_outsel_3_gated_we = mio_outsel_3_we & mio_outsel_regwen_3_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_3_gated_we), + .wd (mio_outsel_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[3].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_3_qs) + ); + + + // Subregister 4 of Multireg mio_outsel + // R[mio_outsel_4]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_4_gated_we; + assign mio_outsel_4_gated_we = mio_outsel_4_we & mio_outsel_regwen_4_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_4_gated_we), + .wd (mio_outsel_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[4].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_4_qs) + ); + + + // Subregister 5 of Multireg mio_outsel + // R[mio_outsel_5]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_5_gated_we; + assign mio_outsel_5_gated_we = mio_outsel_5_we & mio_outsel_regwen_5_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_5_gated_we), + .wd (mio_outsel_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[5].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_5_qs) + ); + + + // Subregister 6 of Multireg mio_outsel + // R[mio_outsel_6]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_6_gated_we; + assign mio_outsel_6_gated_we = mio_outsel_6_we & mio_outsel_regwen_6_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_6_gated_we), + .wd (mio_outsel_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[6].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_6_qs) + ); + + + // Subregister 7 of Multireg mio_outsel + // R[mio_outsel_7]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_7_gated_we; + assign mio_outsel_7_gated_we = mio_outsel_7_we & mio_outsel_regwen_7_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_7_gated_we), + .wd (mio_outsel_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[7].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_7_qs) + ); + + + // Subregister 8 of Multireg mio_outsel + // R[mio_outsel_8]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_8_gated_we; + assign mio_outsel_8_gated_we = mio_outsel_8_we & mio_outsel_regwen_8_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_8_gated_we), + .wd (mio_outsel_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[8].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_8_qs) + ); + + + // Subregister 9 of Multireg mio_outsel + // R[mio_outsel_9]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_9_gated_we; + assign mio_outsel_9_gated_we = mio_outsel_9_we & mio_outsel_regwen_9_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_9_gated_we), + .wd (mio_outsel_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[9].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_9_qs) + ); + + + // Subregister 10 of Multireg mio_outsel + // R[mio_outsel_10]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_10_gated_we; + assign mio_outsel_10_gated_we = mio_outsel_10_we & mio_outsel_regwen_10_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_10_gated_we), + .wd (mio_outsel_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[10].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_10_qs) + ); + + + // Subregister 11 of Multireg mio_outsel + // R[mio_outsel_11]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_11_gated_we; + assign mio_outsel_11_gated_we = mio_outsel_11_we & mio_outsel_regwen_11_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_11_gated_we), + .wd (mio_outsel_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[11].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_11_qs) + ); + + + // Subregister 0 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_0_we), + .wd (mio_pad_attr_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_0_qs) + ); + + + // Subregister 1 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_1_we), + .wd (mio_pad_attr_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_1_qs) + ); + + + // Subregister 2 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_2_we), + .wd (mio_pad_attr_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_2_qs) + ); + + + // Subregister 3 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_3_we), + .wd (mio_pad_attr_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_3_qs) + ); + + + // Subregister 4 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_4_we), + .wd (mio_pad_attr_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_4_qs) + ); + + + // Subregister 5 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_5_we), + .wd (mio_pad_attr_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_5_qs) + ); + + + // Subregister 6 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_6_we), + .wd (mio_pad_attr_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_6_qs) + ); + + + // Subregister 7 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_7_we), + .wd (mio_pad_attr_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_7_qs) + ); + + + // Subregister 8 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_8_we), + .wd (mio_pad_attr_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_8_qs) + ); + + + // Subregister 9 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_9_we), + .wd (mio_pad_attr_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_9_qs) + ); + + + // Subregister 10 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_10_we), + .wd (mio_pad_attr_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_10_qs) + ); + + + // Subregister 11 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_11_we), + .wd (mio_pad_attr_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_11_qs) + ); + + + // Subregister 0 of Multireg mio_pad_attr + // R[mio_pad_attr_0]: V(True) + logic mio_pad_attr_0_qe; + logic [9:0] mio_pad_attr_0_flds_we; + assign mio_pad_attr_0_qe = &mio_pad_attr_0_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_0_gated_we; + assign mio_pad_attr_0_gated_we = mio_pad_attr_0_we & mio_pad_attr_regwen_0_qs; + // F[invert_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_invert_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_invert_0_wd), + .d (hw2reg.mio_pad_attr[0].invert.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[0]), + .q (reg2hw.mio_pad_attr[0].invert.q), + .ds (), + .qs (mio_pad_attr_0_invert_0_qs) + ); + assign reg2hw.mio_pad_attr[0].invert.qe = mio_pad_attr_0_qe; + + // F[virtual_od_en_0]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_virtual_od_en_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_virtual_od_en_0_wd), + .d (hw2reg.mio_pad_attr[0].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[1]), + .q (reg2hw.mio_pad_attr[0].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_0_virtual_od_en_0_qs) + ); + assign reg2hw.mio_pad_attr[0].virtual_od_en.qe = mio_pad_attr_0_qe; + + // F[pull_en_0]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_pull_en_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_pull_en_0_wd), + .d (hw2reg.mio_pad_attr[0].pull_en.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[2]), + .q (reg2hw.mio_pad_attr[0].pull_en.q), + .ds (), + .qs (mio_pad_attr_0_pull_en_0_qs) + ); + assign reg2hw.mio_pad_attr[0].pull_en.qe = mio_pad_attr_0_qe; + + // F[pull_select_0]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_pull_select_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_pull_select_0_wd), + .d (hw2reg.mio_pad_attr[0].pull_select.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[3]), + .q (reg2hw.mio_pad_attr[0].pull_select.q), + .ds (), + .qs (mio_pad_attr_0_pull_select_0_qs) + ); + assign reg2hw.mio_pad_attr[0].pull_select.qe = mio_pad_attr_0_qe; + + // F[keeper_en_0]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_keeper_en_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_keeper_en_0_wd), + .d (hw2reg.mio_pad_attr[0].keeper_en.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[4]), + .q (reg2hw.mio_pad_attr[0].keeper_en.q), + .ds (), + .qs (mio_pad_attr_0_keeper_en_0_qs) + ); + assign reg2hw.mio_pad_attr[0].keeper_en.qe = mio_pad_attr_0_qe; + + // F[schmitt_en_0]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_schmitt_en_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_schmitt_en_0_wd), + .d (hw2reg.mio_pad_attr[0].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[5]), + .q (reg2hw.mio_pad_attr[0].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_0_schmitt_en_0_qs) + ); + assign reg2hw.mio_pad_attr[0].schmitt_en.qe = mio_pad_attr_0_qe; + + // F[od_en_0]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_od_en_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_od_en_0_wd), + .d (hw2reg.mio_pad_attr[0].od_en.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[6]), + .q (reg2hw.mio_pad_attr[0].od_en.q), + .ds (), + .qs (mio_pad_attr_0_od_en_0_qs) + ); + assign reg2hw.mio_pad_attr[0].od_en.qe = mio_pad_attr_0_qe; + + // F[input_disable_0]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_input_disable_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_input_disable_0_wd), + .d (hw2reg.mio_pad_attr[0].input_disable.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[7]), + .q (reg2hw.mio_pad_attr[0].input_disable.q), + .ds (), + .qs (mio_pad_attr_0_input_disable_0_qs) + ); + assign reg2hw.mio_pad_attr[0].input_disable.qe = mio_pad_attr_0_qe; + + // F[slew_rate_0]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_0_slew_rate_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_slew_rate_0_wd), + .d (hw2reg.mio_pad_attr[0].slew_rate.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[8]), + .q (reg2hw.mio_pad_attr[0].slew_rate.q), + .ds (), + .qs (mio_pad_attr_0_slew_rate_0_qs) + ); + assign reg2hw.mio_pad_attr[0].slew_rate.qe = mio_pad_attr_0_qe; + + // F[drive_strength_0]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_0_drive_strength_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_drive_strength_0_wd), + .d (hw2reg.mio_pad_attr[0].drive_strength.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[9]), + .q (reg2hw.mio_pad_attr[0].drive_strength.q), + .ds (), + .qs (mio_pad_attr_0_drive_strength_0_qs) + ); + assign reg2hw.mio_pad_attr[0].drive_strength.qe = mio_pad_attr_0_qe; + + + // Subregister 1 of Multireg mio_pad_attr + // R[mio_pad_attr_1]: V(True) + logic mio_pad_attr_1_qe; + logic [9:0] mio_pad_attr_1_flds_we; + assign mio_pad_attr_1_qe = &mio_pad_attr_1_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_1_gated_we; + assign mio_pad_attr_1_gated_we = mio_pad_attr_1_we & mio_pad_attr_regwen_1_qs; + // F[invert_1]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_invert_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_invert_1_wd), + .d (hw2reg.mio_pad_attr[1].invert.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[0]), + .q (reg2hw.mio_pad_attr[1].invert.q), + .ds (), + .qs (mio_pad_attr_1_invert_1_qs) + ); + assign reg2hw.mio_pad_attr[1].invert.qe = mio_pad_attr_1_qe; + + // F[virtual_od_en_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_virtual_od_en_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_virtual_od_en_1_wd), + .d (hw2reg.mio_pad_attr[1].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[1]), + .q (reg2hw.mio_pad_attr[1].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_1_virtual_od_en_1_qs) + ); + assign reg2hw.mio_pad_attr[1].virtual_od_en.qe = mio_pad_attr_1_qe; + + // F[pull_en_1]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_pull_en_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_pull_en_1_wd), + .d (hw2reg.mio_pad_attr[1].pull_en.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[2]), + .q (reg2hw.mio_pad_attr[1].pull_en.q), + .ds (), + .qs (mio_pad_attr_1_pull_en_1_qs) + ); + assign reg2hw.mio_pad_attr[1].pull_en.qe = mio_pad_attr_1_qe; + + // F[pull_select_1]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_pull_select_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_pull_select_1_wd), + .d (hw2reg.mio_pad_attr[1].pull_select.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[3]), + .q (reg2hw.mio_pad_attr[1].pull_select.q), + .ds (), + .qs (mio_pad_attr_1_pull_select_1_qs) + ); + assign reg2hw.mio_pad_attr[1].pull_select.qe = mio_pad_attr_1_qe; + + // F[keeper_en_1]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_keeper_en_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_keeper_en_1_wd), + .d (hw2reg.mio_pad_attr[1].keeper_en.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[4]), + .q (reg2hw.mio_pad_attr[1].keeper_en.q), + .ds (), + .qs (mio_pad_attr_1_keeper_en_1_qs) + ); + assign reg2hw.mio_pad_attr[1].keeper_en.qe = mio_pad_attr_1_qe; + + // F[schmitt_en_1]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_schmitt_en_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_schmitt_en_1_wd), + .d (hw2reg.mio_pad_attr[1].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[5]), + .q (reg2hw.mio_pad_attr[1].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_1_schmitt_en_1_qs) + ); + assign reg2hw.mio_pad_attr[1].schmitt_en.qe = mio_pad_attr_1_qe; + + // F[od_en_1]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_od_en_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_od_en_1_wd), + .d (hw2reg.mio_pad_attr[1].od_en.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[6]), + .q (reg2hw.mio_pad_attr[1].od_en.q), + .ds (), + .qs (mio_pad_attr_1_od_en_1_qs) + ); + assign reg2hw.mio_pad_attr[1].od_en.qe = mio_pad_attr_1_qe; + + // F[input_disable_1]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_input_disable_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_input_disable_1_wd), + .d (hw2reg.mio_pad_attr[1].input_disable.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[7]), + .q (reg2hw.mio_pad_attr[1].input_disable.q), + .ds (), + .qs (mio_pad_attr_1_input_disable_1_qs) + ); + assign reg2hw.mio_pad_attr[1].input_disable.qe = mio_pad_attr_1_qe; + + // F[slew_rate_1]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_1_slew_rate_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_slew_rate_1_wd), + .d (hw2reg.mio_pad_attr[1].slew_rate.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[8]), + .q (reg2hw.mio_pad_attr[1].slew_rate.q), + .ds (), + .qs (mio_pad_attr_1_slew_rate_1_qs) + ); + assign reg2hw.mio_pad_attr[1].slew_rate.qe = mio_pad_attr_1_qe; + + // F[drive_strength_1]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_1_drive_strength_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_drive_strength_1_wd), + .d (hw2reg.mio_pad_attr[1].drive_strength.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[9]), + .q (reg2hw.mio_pad_attr[1].drive_strength.q), + .ds (), + .qs (mio_pad_attr_1_drive_strength_1_qs) + ); + assign reg2hw.mio_pad_attr[1].drive_strength.qe = mio_pad_attr_1_qe; + + + // Subregister 2 of Multireg mio_pad_attr + // R[mio_pad_attr_2]: V(True) + logic mio_pad_attr_2_qe; + logic [9:0] mio_pad_attr_2_flds_we; + assign mio_pad_attr_2_qe = &mio_pad_attr_2_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_2_gated_we; + assign mio_pad_attr_2_gated_we = mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs; + // F[invert_2]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_invert_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_invert_2_wd), + .d (hw2reg.mio_pad_attr[2].invert.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[0]), + .q (reg2hw.mio_pad_attr[2].invert.q), + .ds (), + .qs (mio_pad_attr_2_invert_2_qs) + ); + assign reg2hw.mio_pad_attr[2].invert.qe = mio_pad_attr_2_qe; + + // F[virtual_od_en_2]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_virtual_od_en_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_virtual_od_en_2_wd), + .d (hw2reg.mio_pad_attr[2].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[1]), + .q (reg2hw.mio_pad_attr[2].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_2_virtual_od_en_2_qs) + ); + assign reg2hw.mio_pad_attr[2].virtual_od_en.qe = mio_pad_attr_2_qe; + + // F[pull_en_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_pull_en_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_pull_en_2_wd), + .d (hw2reg.mio_pad_attr[2].pull_en.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[2]), + .q (reg2hw.mio_pad_attr[2].pull_en.q), + .ds (), + .qs (mio_pad_attr_2_pull_en_2_qs) + ); + assign reg2hw.mio_pad_attr[2].pull_en.qe = mio_pad_attr_2_qe; + + // F[pull_select_2]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_pull_select_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_pull_select_2_wd), + .d (hw2reg.mio_pad_attr[2].pull_select.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[3]), + .q (reg2hw.mio_pad_attr[2].pull_select.q), + .ds (), + .qs (mio_pad_attr_2_pull_select_2_qs) + ); + assign reg2hw.mio_pad_attr[2].pull_select.qe = mio_pad_attr_2_qe; + + // F[keeper_en_2]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_keeper_en_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_keeper_en_2_wd), + .d (hw2reg.mio_pad_attr[2].keeper_en.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[4]), + .q (reg2hw.mio_pad_attr[2].keeper_en.q), + .ds (), + .qs (mio_pad_attr_2_keeper_en_2_qs) + ); + assign reg2hw.mio_pad_attr[2].keeper_en.qe = mio_pad_attr_2_qe; + + // F[schmitt_en_2]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_schmitt_en_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_schmitt_en_2_wd), + .d (hw2reg.mio_pad_attr[2].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[5]), + .q (reg2hw.mio_pad_attr[2].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_2_schmitt_en_2_qs) + ); + assign reg2hw.mio_pad_attr[2].schmitt_en.qe = mio_pad_attr_2_qe; + + // F[od_en_2]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_od_en_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_od_en_2_wd), + .d (hw2reg.mio_pad_attr[2].od_en.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[6]), + .q (reg2hw.mio_pad_attr[2].od_en.q), + .ds (), + .qs (mio_pad_attr_2_od_en_2_qs) + ); + assign reg2hw.mio_pad_attr[2].od_en.qe = mio_pad_attr_2_qe; + + // F[input_disable_2]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_input_disable_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_input_disable_2_wd), + .d (hw2reg.mio_pad_attr[2].input_disable.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[7]), + .q (reg2hw.mio_pad_attr[2].input_disable.q), + .ds (), + .qs (mio_pad_attr_2_input_disable_2_qs) + ); + assign reg2hw.mio_pad_attr[2].input_disable.qe = mio_pad_attr_2_qe; + + // F[slew_rate_2]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_2_slew_rate_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_slew_rate_2_wd), + .d (hw2reg.mio_pad_attr[2].slew_rate.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[8]), + .q (reg2hw.mio_pad_attr[2].slew_rate.q), + .ds (), + .qs (mio_pad_attr_2_slew_rate_2_qs) + ); + assign reg2hw.mio_pad_attr[2].slew_rate.qe = mio_pad_attr_2_qe; + + // F[drive_strength_2]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_2_drive_strength_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_drive_strength_2_wd), + .d (hw2reg.mio_pad_attr[2].drive_strength.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[9]), + .q (reg2hw.mio_pad_attr[2].drive_strength.q), + .ds (), + .qs (mio_pad_attr_2_drive_strength_2_qs) + ); + assign reg2hw.mio_pad_attr[2].drive_strength.qe = mio_pad_attr_2_qe; + + + // Subregister 3 of Multireg mio_pad_attr + // R[mio_pad_attr_3]: V(True) + logic mio_pad_attr_3_qe; + logic [9:0] mio_pad_attr_3_flds_we; + assign mio_pad_attr_3_qe = &mio_pad_attr_3_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_3_gated_we; + assign mio_pad_attr_3_gated_we = mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs; + // F[invert_3]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_invert_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_invert_3_wd), + .d (hw2reg.mio_pad_attr[3].invert.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[0]), + .q (reg2hw.mio_pad_attr[3].invert.q), + .ds (), + .qs (mio_pad_attr_3_invert_3_qs) + ); + assign reg2hw.mio_pad_attr[3].invert.qe = mio_pad_attr_3_qe; + + // F[virtual_od_en_3]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_virtual_od_en_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_virtual_od_en_3_wd), + .d (hw2reg.mio_pad_attr[3].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[1]), + .q (reg2hw.mio_pad_attr[3].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_3_virtual_od_en_3_qs) + ); + assign reg2hw.mio_pad_attr[3].virtual_od_en.qe = mio_pad_attr_3_qe; + + // F[pull_en_3]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_pull_en_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_pull_en_3_wd), + .d (hw2reg.mio_pad_attr[3].pull_en.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[2]), + .q (reg2hw.mio_pad_attr[3].pull_en.q), + .ds (), + .qs (mio_pad_attr_3_pull_en_3_qs) + ); + assign reg2hw.mio_pad_attr[3].pull_en.qe = mio_pad_attr_3_qe; + + // F[pull_select_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_pull_select_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_pull_select_3_wd), + .d (hw2reg.mio_pad_attr[3].pull_select.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[3]), + .q (reg2hw.mio_pad_attr[3].pull_select.q), + .ds (), + .qs (mio_pad_attr_3_pull_select_3_qs) + ); + assign reg2hw.mio_pad_attr[3].pull_select.qe = mio_pad_attr_3_qe; + + // F[keeper_en_3]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_keeper_en_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_keeper_en_3_wd), + .d (hw2reg.mio_pad_attr[3].keeper_en.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[4]), + .q (reg2hw.mio_pad_attr[3].keeper_en.q), + .ds (), + .qs (mio_pad_attr_3_keeper_en_3_qs) + ); + assign reg2hw.mio_pad_attr[3].keeper_en.qe = mio_pad_attr_3_qe; + + // F[schmitt_en_3]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_schmitt_en_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_schmitt_en_3_wd), + .d (hw2reg.mio_pad_attr[3].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[5]), + .q (reg2hw.mio_pad_attr[3].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_3_schmitt_en_3_qs) + ); + assign reg2hw.mio_pad_attr[3].schmitt_en.qe = mio_pad_attr_3_qe; + + // F[od_en_3]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_od_en_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_od_en_3_wd), + .d (hw2reg.mio_pad_attr[3].od_en.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[6]), + .q (reg2hw.mio_pad_attr[3].od_en.q), + .ds (), + .qs (mio_pad_attr_3_od_en_3_qs) + ); + assign reg2hw.mio_pad_attr[3].od_en.qe = mio_pad_attr_3_qe; + + // F[input_disable_3]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_input_disable_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_input_disable_3_wd), + .d (hw2reg.mio_pad_attr[3].input_disable.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[7]), + .q (reg2hw.mio_pad_attr[3].input_disable.q), + .ds (), + .qs (mio_pad_attr_3_input_disable_3_qs) + ); + assign reg2hw.mio_pad_attr[3].input_disable.qe = mio_pad_attr_3_qe; + + // F[slew_rate_3]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_3_slew_rate_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_slew_rate_3_wd), + .d (hw2reg.mio_pad_attr[3].slew_rate.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[8]), + .q (reg2hw.mio_pad_attr[3].slew_rate.q), + .ds (), + .qs (mio_pad_attr_3_slew_rate_3_qs) + ); + assign reg2hw.mio_pad_attr[3].slew_rate.qe = mio_pad_attr_3_qe; + + // F[drive_strength_3]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_3_drive_strength_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_drive_strength_3_wd), + .d (hw2reg.mio_pad_attr[3].drive_strength.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[9]), + .q (reg2hw.mio_pad_attr[3].drive_strength.q), + .ds (), + .qs (mio_pad_attr_3_drive_strength_3_qs) + ); + assign reg2hw.mio_pad_attr[3].drive_strength.qe = mio_pad_attr_3_qe; + + + // Subregister 4 of Multireg mio_pad_attr + // R[mio_pad_attr_4]: V(True) + logic mio_pad_attr_4_qe; + logic [9:0] mio_pad_attr_4_flds_we; + assign mio_pad_attr_4_qe = &mio_pad_attr_4_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_4_gated_we; + assign mio_pad_attr_4_gated_we = mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs; + // F[invert_4]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_invert_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_invert_4_wd), + .d (hw2reg.mio_pad_attr[4].invert.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[0]), + .q (reg2hw.mio_pad_attr[4].invert.q), + .ds (), + .qs (mio_pad_attr_4_invert_4_qs) + ); + assign reg2hw.mio_pad_attr[4].invert.qe = mio_pad_attr_4_qe; + + // F[virtual_od_en_4]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_virtual_od_en_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_virtual_od_en_4_wd), + .d (hw2reg.mio_pad_attr[4].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[1]), + .q (reg2hw.mio_pad_attr[4].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_4_virtual_od_en_4_qs) + ); + assign reg2hw.mio_pad_attr[4].virtual_od_en.qe = mio_pad_attr_4_qe; + + // F[pull_en_4]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_pull_en_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_pull_en_4_wd), + .d (hw2reg.mio_pad_attr[4].pull_en.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[2]), + .q (reg2hw.mio_pad_attr[4].pull_en.q), + .ds (), + .qs (mio_pad_attr_4_pull_en_4_qs) + ); + assign reg2hw.mio_pad_attr[4].pull_en.qe = mio_pad_attr_4_qe; + + // F[pull_select_4]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_pull_select_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_pull_select_4_wd), + .d (hw2reg.mio_pad_attr[4].pull_select.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[3]), + .q (reg2hw.mio_pad_attr[4].pull_select.q), + .ds (), + .qs (mio_pad_attr_4_pull_select_4_qs) + ); + assign reg2hw.mio_pad_attr[4].pull_select.qe = mio_pad_attr_4_qe; + + // F[keeper_en_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_keeper_en_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_keeper_en_4_wd), + .d (hw2reg.mio_pad_attr[4].keeper_en.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[4]), + .q (reg2hw.mio_pad_attr[4].keeper_en.q), + .ds (), + .qs (mio_pad_attr_4_keeper_en_4_qs) + ); + assign reg2hw.mio_pad_attr[4].keeper_en.qe = mio_pad_attr_4_qe; + + // F[schmitt_en_4]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_schmitt_en_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_schmitt_en_4_wd), + .d (hw2reg.mio_pad_attr[4].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[5]), + .q (reg2hw.mio_pad_attr[4].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_4_schmitt_en_4_qs) + ); + assign reg2hw.mio_pad_attr[4].schmitt_en.qe = mio_pad_attr_4_qe; + + // F[od_en_4]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_od_en_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_od_en_4_wd), + .d (hw2reg.mio_pad_attr[4].od_en.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[6]), + .q (reg2hw.mio_pad_attr[4].od_en.q), + .ds (), + .qs (mio_pad_attr_4_od_en_4_qs) + ); + assign reg2hw.mio_pad_attr[4].od_en.qe = mio_pad_attr_4_qe; + + // F[input_disable_4]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_input_disable_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_input_disable_4_wd), + .d (hw2reg.mio_pad_attr[4].input_disable.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[7]), + .q (reg2hw.mio_pad_attr[4].input_disable.q), + .ds (), + .qs (mio_pad_attr_4_input_disable_4_qs) + ); + assign reg2hw.mio_pad_attr[4].input_disable.qe = mio_pad_attr_4_qe; + + // F[slew_rate_4]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_4_slew_rate_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_slew_rate_4_wd), + .d (hw2reg.mio_pad_attr[4].slew_rate.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[8]), + .q (reg2hw.mio_pad_attr[4].slew_rate.q), + .ds (), + .qs (mio_pad_attr_4_slew_rate_4_qs) + ); + assign reg2hw.mio_pad_attr[4].slew_rate.qe = mio_pad_attr_4_qe; + + // F[drive_strength_4]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_4_drive_strength_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_drive_strength_4_wd), + .d (hw2reg.mio_pad_attr[4].drive_strength.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[9]), + .q (reg2hw.mio_pad_attr[4].drive_strength.q), + .ds (), + .qs (mio_pad_attr_4_drive_strength_4_qs) + ); + assign reg2hw.mio_pad_attr[4].drive_strength.qe = mio_pad_attr_4_qe; + + + // Subregister 5 of Multireg mio_pad_attr + // R[mio_pad_attr_5]: V(True) + logic mio_pad_attr_5_qe; + logic [9:0] mio_pad_attr_5_flds_we; + assign mio_pad_attr_5_qe = &mio_pad_attr_5_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_5_gated_we; + assign mio_pad_attr_5_gated_we = mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs; + // F[invert_5]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_invert_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_invert_5_wd), + .d (hw2reg.mio_pad_attr[5].invert.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[0]), + .q (reg2hw.mio_pad_attr[5].invert.q), + .ds (), + .qs (mio_pad_attr_5_invert_5_qs) + ); + assign reg2hw.mio_pad_attr[5].invert.qe = mio_pad_attr_5_qe; + + // F[virtual_od_en_5]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_virtual_od_en_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_virtual_od_en_5_wd), + .d (hw2reg.mio_pad_attr[5].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[1]), + .q (reg2hw.mio_pad_attr[5].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_5_virtual_od_en_5_qs) + ); + assign reg2hw.mio_pad_attr[5].virtual_od_en.qe = mio_pad_attr_5_qe; + + // F[pull_en_5]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_pull_en_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_pull_en_5_wd), + .d (hw2reg.mio_pad_attr[5].pull_en.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[2]), + .q (reg2hw.mio_pad_attr[5].pull_en.q), + .ds (), + .qs (mio_pad_attr_5_pull_en_5_qs) + ); + assign reg2hw.mio_pad_attr[5].pull_en.qe = mio_pad_attr_5_qe; + + // F[pull_select_5]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_pull_select_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_pull_select_5_wd), + .d (hw2reg.mio_pad_attr[5].pull_select.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[3]), + .q (reg2hw.mio_pad_attr[5].pull_select.q), + .ds (), + .qs (mio_pad_attr_5_pull_select_5_qs) + ); + assign reg2hw.mio_pad_attr[5].pull_select.qe = mio_pad_attr_5_qe; + + // F[keeper_en_5]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_keeper_en_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_keeper_en_5_wd), + .d (hw2reg.mio_pad_attr[5].keeper_en.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[4]), + .q (reg2hw.mio_pad_attr[5].keeper_en.q), + .ds (), + .qs (mio_pad_attr_5_keeper_en_5_qs) + ); + assign reg2hw.mio_pad_attr[5].keeper_en.qe = mio_pad_attr_5_qe; + + // F[schmitt_en_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_schmitt_en_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_schmitt_en_5_wd), + .d (hw2reg.mio_pad_attr[5].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[5]), + .q (reg2hw.mio_pad_attr[5].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_5_schmitt_en_5_qs) + ); + assign reg2hw.mio_pad_attr[5].schmitt_en.qe = mio_pad_attr_5_qe; + + // F[od_en_5]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_od_en_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_od_en_5_wd), + .d (hw2reg.mio_pad_attr[5].od_en.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[6]), + .q (reg2hw.mio_pad_attr[5].od_en.q), + .ds (), + .qs (mio_pad_attr_5_od_en_5_qs) + ); + assign reg2hw.mio_pad_attr[5].od_en.qe = mio_pad_attr_5_qe; + + // F[input_disable_5]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_input_disable_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_input_disable_5_wd), + .d (hw2reg.mio_pad_attr[5].input_disable.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[7]), + .q (reg2hw.mio_pad_attr[5].input_disable.q), + .ds (), + .qs (mio_pad_attr_5_input_disable_5_qs) + ); + assign reg2hw.mio_pad_attr[5].input_disable.qe = mio_pad_attr_5_qe; + + // F[slew_rate_5]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_5_slew_rate_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_slew_rate_5_wd), + .d (hw2reg.mio_pad_attr[5].slew_rate.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[8]), + .q (reg2hw.mio_pad_attr[5].slew_rate.q), + .ds (), + .qs (mio_pad_attr_5_slew_rate_5_qs) + ); + assign reg2hw.mio_pad_attr[5].slew_rate.qe = mio_pad_attr_5_qe; + + // F[drive_strength_5]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_5_drive_strength_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_drive_strength_5_wd), + .d (hw2reg.mio_pad_attr[5].drive_strength.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[9]), + .q (reg2hw.mio_pad_attr[5].drive_strength.q), + .ds (), + .qs (mio_pad_attr_5_drive_strength_5_qs) + ); + assign reg2hw.mio_pad_attr[5].drive_strength.qe = mio_pad_attr_5_qe; + + + // Subregister 6 of Multireg mio_pad_attr + // R[mio_pad_attr_6]: V(True) + logic mio_pad_attr_6_qe; + logic [9:0] mio_pad_attr_6_flds_we; + assign mio_pad_attr_6_qe = &mio_pad_attr_6_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_6_gated_we; + assign mio_pad_attr_6_gated_we = mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs; + // F[invert_6]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_invert_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_invert_6_wd), + .d (hw2reg.mio_pad_attr[6].invert.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[0]), + .q (reg2hw.mio_pad_attr[6].invert.q), + .ds (), + .qs (mio_pad_attr_6_invert_6_qs) + ); + assign reg2hw.mio_pad_attr[6].invert.qe = mio_pad_attr_6_qe; + + // F[virtual_od_en_6]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_virtual_od_en_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_virtual_od_en_6_wd), + .d (hw2reg.mio_pad_attr[6].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[1]), + .q (reg2hw.mio_pad_attr[6].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_6_virtual_od_en_6_qs) + ); + assign reg2hw.mio_pad_attr[6].virtual_od_en.qe = mio_pad_attr_6_qe; + + // F[pull_en_6]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_pull_en_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_pull_en_6_wd), + .d (hw2reg.mio_pad_attr[6].pull_en.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[2]), + .q (reg2hw.mio_pad_attr[6].pull_en.q), + .ds (), + .qs (mio_pad_attr_6_pull_en_6_qs) + ); + assign reg2hw.mio_pad_attr[6].pull_en.qe = mio_pad_attr_6_qe; + + // F[pull_select_6]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_pull_select_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_pull_select_6_wd), + .d (hw2reg.mio_pad_attr[6].pull_select.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[3]), + .q (reg2hw.mio_pad_attr[6].pull_select.q), + .ds (), + .qs (mio_pad_attr_6_pull_select_6_qs) + ); + assign reg2hw.mio_pad_attr[6].pull_select.qe = mio_pad_attr_6_qe; + + // F[keeper_en_6]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_keeper_en_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_keeper_en_6_wd), + .d (hw2reg.mio_pad_attr[6].keeper_en.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[4]), + .q (reg2hw.mio_pad_attr[6].keeper_en.q), + .ds (), + .qs (mio_pad_attr_6_keeper_en_6_qs) + ); + assign reg2hw.mio_pad_attr[6].keeper_en.qe = mio_pad_attr_6_qe; + + // F[schmitt_en_6]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_schmitt_en_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_schmitt_en_6_wd), + .d (hw2reg.mio_pad_attr[6].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[5]), + .q (reg2hw.mio_pad_attr[6].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_6_schmitt_en_6_qs) + ); + assign reg2hw.mio_pad_attr[6].schmitt_en.qe = mio_pad_attr_6_qe; + + // F[od_en_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_od_en_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_od_en_6_wd), + .d (hw2reg.mio_pad_attr[6].od_en.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[6]), + .q (reg2hw.mio_pad_attr[6].od_en.q), + .ds (), + .qs (mio_pad_attr_6_od_en_6_qs) + ); + assign reg2hw.mio_pad_attr[6].od_en.qe = mio_pad_attr_6_qe; + + // F[input_disable_6]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_input_disable_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_input_disable_6_wd), + .d (hw2reg.mio_pad_attr[6].input_disable.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[7]), + .q (reg2hw.mio_pad_attr[6].input_disable.q), + .ds (), + .qs (mio_pad_attr_6_input_disable_6_qs) + ); + assign reg2hw.mio_pad_attr[6].input_disable.qe = mio_pad_attr_6_qe; + + // F[slew_rate_6]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_6_slew_rate_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_slew_rate_6_wd), + .d (hw2reg.mio_pad_attr[6].slew_rate.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[8]), + .q (reg2hw.mio_pad_attr[6].slew_rate.q), + .ds (), + .qs (mio_pad_attr_6_slew_rate_6_qs) + ); + assign reg2hw.mio_pad_attr[6].slew_rate.qe = mio_pad_attr_6_qe; + + // F[drive_strength_6]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_6_drive_strength_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_drive_strength_6_wd), + .d (hw2reg.mio_pad_attr[6].drive_strength.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[9]), + .q (reg2hw.mio_pad_attr[6].drive_strength.q), + .ds (), + .qs (mio_pad_attr_6_drive_strength_6_qs) + ); + assign reg2hw.mio_pad_attr[6].drive_strength.qe = mio_pad_attr_6_qe; + + + // Subregister 7 of Multireg mio_pad_attr + // R[mio_pad_attr_7]: V(True) + logic mio_pad_attr_7_qe; + logic [9:0] mio_pad_attr_7_flds_we; + assign mio_pad_attr_7_qe = &mio_pad_attr_7_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_7_gated_we; + assign mio_pad_attr_7_gated_we = mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs; + // F[invert_7]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_invert_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_invert_7_wd), + .d (hw2reg.mio_pad_attr[7].invert.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[0]), + .q (reg2hw.mio_pad_attr[7].invert.q), + .ds (), + .qs (mio_pad_attr_7_invert_7_qs) + ); + assign reg2hw.mio_pad_attr[7].invert.qe = mio_pad_attr_7_qe; + + // F[virtual_od_en_7]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_virtual_od_en_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_virtual_od_en_7_wd), + .d (hw2reg.mio_pad_attr[7].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[1]), + .q (reg2hw.mio_pad_attr[7].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_7_virtual_od_en_7_qs) + ); + assign reg2hw.mio_pad_attr[7].virtual_od_en.qe = mio_pad_attr_7_qe; + + // F[pull_en_7]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_pull_en_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_pull_en_7_wd), + .d (hw2reg.mio_pad_attr[7].pull_en.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[2]), + .q (reg2hw.mio_pad_attr[7].pull_en.q), + .ds (), + .qs (mio_pad_attr_7_pull_en_7_qs) + ); + assign reg2hw.mio_pad_attr[7].pull_en.qe = mio_pad_attr_7_qe; + + // F[pull_select_7]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_pull_select_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_pull_select_7_wd), + .d (hw2reg.mio_pad_attr[7].pull_select.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[3]), + .q (reg2hw.mio_pad_attr[7].pull_select.q), + .ds (), + .qs (mio_pad_attr_7_pull_select_7_qs) + ); + assign reg2hw.mio_pad_attr[7].pull_select.qe = mio_pad_attr_7_qe; + + // F[keeper_en_7]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_keeper_en_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_keeper_en_7_wd), + .d (hw2reg.mio_pad_attr[7].keeper_en.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[4]), + .q (reg2hw.mio_pad_attr[7].keeper_en.q), + .ds (), + .qs (mio_pad_attr_7_keeper_en_7_qs) + ); + assign reg2hw.mio_pad_attr[7].keeper_en.qe = mio_pad_attr_7_qe; + + // F[schmitt_en_7]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_schmitt_en_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_schmitt_en_7_wd), + .d (hw2reg.mio_pad_attr[7].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[5]), + .q (reg2hw.mio_pad_attr[7].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_7_schmitt_en_7_qs) + ); + assign reg2hw.mio_pad_attr[7].schmitt_en.qe = mio_pad_attr_7_qe; + + // F[od_en_7]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_od_en_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_od_en_7_wd), + .d (hw2reg.mio_pad_attr[7].od_en.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[6]), + .q (reg2hw.mio_pad_attr[7].od_en.q), + .ds (), + .qs (mio_pad_attr_7_od_en_7_qs) + ); + assign reg2hw.mio_pad_attr[7].od_en.qe = mio_pad_attr_7_qe; + + // F[input_disable_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_input_disable_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_input_disable_7_wd), + .d (hw2reg.mio_pad_attr[7].input_disable.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[7]), + .q (reg2hw.mio_pad_attr[7].input_disable.q), + .ds (), + .qs (mio_pad_attr_7_input_disable_7_qs) + ); + assign reg2hw.mio_pad_attr[7].input_disable.qe = mio_pad_attr_7_qe; + + // F[slew_rate_7]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_7_slew_rate_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_slew_rate_7_wd), + .d (hw2reg.mio_pad_attr[7].slew_rate.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[8]), + .q (reg2hw.mio_pad_attr[7].slew_rate.q), + .ds (), + .qs (mio_pad_attr_7_slew_rate_7_qs) + ); + assign reg2hw.mio_pad_attr[7].slew_rate.qe = mio_pad_attr_7_qe; + + // F[drive_strength_7]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_7_drive_strength_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_drive_strength_7_wd), + .d (hw2reg.mio_pad_attr[7].drive_strength.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[9]), + .q (reg2hw.mio_pad_attr[7].drive_strength.q), + .ds (), + .qs (mio_pad_attr_7_drive_strength_7_qs) + ); + assign reg2hw.mio_pad_attr[7].drive_strength.qe = mio_pad_attr_7_qe; + + + // Subregister 8 of Multireg mio_pad_attr + // R[mio_pad_attr_8]: V(True) + logic mio_pad_attr_8_qe; + logic [9:0] mio_pad_attr_8_flds_we; + assign mio_pad_attr_8_qe = &mio_pad_attr_8_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_8_gated_we; + assign mio_pad_attr_8_gated_we = mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs; + // F[invert_8]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_invert_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_invert_8_wd), + .d (hw2reg.mio_pad_attr[8].invert.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[0]), + .q (reg2hw.mio_pad_attr[8].invert.q), + .ds (), + .qs (mio_pad_attr_8_invert_8_qs) + ); + assign reg2hw.mio_pad_attr[8].invert.qe = mio_pad_attr_8_qe; + + // F[virtual_od_en_8]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_virtual_od_en_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_virtual_od_en_8_wd), + .d (hw2reg.mio_pad_attr[8].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[1]), + .q (reg2hw.mio_pad_attr[8].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_8_virtual_od_en_8_qs) + ); + assign reg2hw.mio_pad_attr[8].virtual_od_en.qe = mio_pad_attr_8_qe; + + // F[pull_en_8]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_pull_en_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_pull_en_8_wd), + .d (hw2reg.mio_pad_attr[8].pull_en.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[2]), + .q (reg2hw.mio_pad_attr[8].pull_en.q), + .ds (), + .qs (mio_pad_attr_8_pull_en_8_qs) + ); + assign reg2hw.mio_pad_attr[8].pull_en.qe = mio_pad_attr_8_qe; + + // F[pull_select_8]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_pull_select_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_pull_select_8_wd), + .d (hw2reg.mio_pad_attr[8].pull_select.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[3]), + .q (reg2hw.mio_pad_attr[8].pull_select.q), + .ds (), + .qs (mio_pad_attr_8_pull_select_8_qs) + ); + assign reg2hw.mio_pad_attr[8].pull_select.qe = mio_pad_attr_8_qe; + + // F[keeper_en_8]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_keeper_en_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_keeper_en_8_wd), + .d (hw2reg.mio_pad_attr[8].keeper_en.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[4]), + .q (reg2hw.mio_pad_attr[8].keeper_en.q), + .ds (), + .qs (mio_pad_attr_8_keeper_en_8_qs) + ); + assign reg2hw.mio_pad_attr[8].keeper_en.qe = mio_pad_attr_8_qe; + + // F[schmitt_en_8]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_schmitt_en_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_schmitt_en_8_wd), + .d (hw2reg.mio_pad_attr[8].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[5]), + .q (reg2hw.mio_pad_attr[8].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_8_schmitt_en_8_qs) + ); + assign reg2hw.mio_pad_attr[8].schmitt_en.qe = mio_pad_attr_8_qe; + + // F[od_en_8]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_od_en_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_od_en_8_wd), + .d (hw2reg.mio_pad_attr[8].od_en.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[6]), + .q (reg2hw.mio_pad_attr[8].od_en.q), + .ds (), + .qs (mio_pad_attr_8_od_en_8_qs) + ); + assign reg2hw.mio_pad_attr[8].od_en.qe = mio_pad_attr_8_qe; + + // F[input_disable_8]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_input_disable_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_input_disable_8_wd), + .d (hw2reg.mio_pad_attr[8].input_disable.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[7]), + .q (reg2hw.mio_pad_attr[8].input_disable.q), + .ds (), + .qs (mio_pad_attr_8_input_disable_8_qs) + ); + assign reg2hw.mio_pad_attr[8].input_disable.qe = mio_pad_attr_8_qe; + + // F[slew_rate_8]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_8_slew_rate_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_slew_rate_8_wd), + .d (hw2reg.mio_pad_attr[8].slew_rate.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[8]), + .q (reg2hw.mio_pad_attr[8].slew_rate.q), + .ds (), + .qs (mio_pad_attr_8_slew_rate_8_qs) + ); + assign reg2hw.mio_pad_attr[8].slew_rate.qe = mio_pad_attr_8_qe; + + // F[drive_strength_8]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_8_drive_strength_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_drive_strength_8_wd), + .d (hw2reg.mio_pad_attr[8].drive_strength.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[9]), + .q (reg2hw.mio_pad_attr[8].drive_strength.q), + .ds (), + .qs (mio_pad_attr_8_drive_strength_8_qs) + ); + assign reg2hw.mio_pad_attr[8].drive_strength.qe = mio_pad_attr_8_qe; + + + // Subregister 9 of Multireg mio_pad_attr + // R[mio_pad_attr_9]: V(True) + logic mio_pad_attr_9_qe; + logic [9:0] mio_pad_attr_9_flds_we; + assign mio_pad_attr_9_qe = &mio_pad_attr_9_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_9_gated_we; + assign mio_pad_attr_9_gated_we = mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs; + // F[invert_9]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_invert_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_invert_9_wd), + .d (hw2reg.mio_pad_attr[9].invert.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[0]), + .q (reg2hw.mio_pad_attr[9].invert.q), + .ds (), + .qs (mio_pad_attr_9_invert_9_qs) + ); + assign reg2hw.mio_pad_attr[9].invert.qe = mio_pad_attr_9_qe; + + // F[virtual_od_en_9]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_virtual_od_en_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_virtual_od_en_9_wd), + .d (hw2reg.mio_pad_attr[9].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[1]), + .q (reg2hw.mio_pad_attr[9].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_9_virtual_od_en_9_qs) + ); + assign reg2hw.mio_pad_attr[9].virtual_od_en.qe = mio_pad_attr_9_qe; + + // F[pull_en_9]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_pull_en_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_pull_en_9_wd), + .d (hw2reg.mio_pad_attr[9].pull_en.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[2]), + .q (reg2hw.mio_pad_attr[9].pull_en.q), + .ds (), + .qs (mio_pad_attr_9_pull_en_9_qs) + ); + assign reg2hw.mio_pad_attr[9].pull_en.qe = mio_pad_attr_9_qe; + + // F[pull_select_9]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_pull_select_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_pull_select_9_wd), + .d (hw2reg.mio_pad_attr[9].pull_select.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[3]), + .q (reg2hw.mio_pad_attr[9].pull_select.q), + .ds (), + .qs (mio_pad_attr_9_pull_select_9_qs) + ); + assign reg2hw.mio_pad_attr[9].pull_select.qe = mio_pad_attr_9_qe; + + // F[keeper_en_9]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_keeper_en_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_keeper_en_9_wd), + .d (hw2reg.mio_pad_attr[9].keeper_en.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[4]), + .q (reg2hw.mio_pad_attr[9].keeper_en.q), + .ds (), + .qs (mio_pad_attr_9_keeper_en_9_qs) + ); + assign reg2hw.mio_pad_attr[9].keeper_en.qe = mio_pad_attr_9_qe; + + // F[schmitt_en_9]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_schmitt_en_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_schmitt_en_9_wd), + .d (hw2reg.mio_pad_attr[9].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[5]), + .q (reg2hw.mio_pad_attr[9].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_9_schmitt_en_9_qs) + ); + assign reg2hw.mio_pad_attr[9].schmitt_en.qe = mio_pad_attr_9_qe; + + // F[od_en_9]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_od_en_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_od_en_9_wd), + .d (hw2reg.mio_pad_attr[9].od_en.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[6]), + .q (reg2hw.mio_pad_attr[9].od_en.q), + .ds (), + .qs (mio_pad_attr_9_od_en_9_qs) + ); + assign reg2hw.mio_pad_attr[9].od_en.qe = mio_pad_attr_9_qe; + + // F[input_disable_9]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_input_disable_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_input_disable_9_wd), + .d (hw2reg.mio_pad_attr[9].input_disable.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[7]), + .q (reg2hw.mio_pad_attr[9].input_disable.q), + .ds (), + .qs (mio_pad_attr_9_input_disable_9_qs) + ); + assign reg2hw.mio_pad_attr[9].input_disable.qe = mio_pad_attr_9_qe; + + // F[slew_rate_9]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_9_slew_rate_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_slew_rate_9_wd), + .d (hw2reg.mio_pad_attr[9].slew_rate.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[8]), + .q (reg2hw.mio_pad_attr[9].slew_rate.q), + .ds (), + .qs (mio_pad_attr_9_slew_rate_9_qs) + ); + assign reg2hw.mio_pad_attr[9].slew_rate.qe = mio_pad_attr_9_qe; + + // F[drive_strength_9]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_9_drive_strength_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_drive_strength_9_wd), + .d (hw2reg.mio_pad_attr[9].drive_strength.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[9]), + .q (reg2hw.mio_pad_attr[9].drive_strength.q), + .ds (), + .qs (mio_pad_attr_9_drive_strength_9_qs) + ); + assign reg2hw.mio_pad_attr[9].drive_strength.qe = mio_pad_attr_9_qe; + + + // Subregister 10 of Multireg mio_pad_attr + // R[mio_pad_attr_10]: V(True) + logic mio_pad_attr_10_qe; + logic [9:0] mio_pad_attr_10_flds_we; + assign mio_pad_attr_10_qe = &mio_pad_attr_10_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_10_gated_we; + assign mio_pad_attr_10_gated_we = mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs; + // F[invert_10]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_invert_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_invert_10_wd), + .d (hw2reg.mio_pad_attr[10].invert.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[0]), + .q (reg2hw.mio_pad_attr[10].invert.q), + .ds (), + .qs (mio_pad_attr_10_invert_10_qs) + ); + assign reg2hw.mio_pad_attr[10].invert.qe = mio_pad_attr_10_qe; + + // F[virtual_od_en_10]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_virtual_od_en_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_virtual_od_en_10_wd), + .d (hw2reg.mio_pad_attr[10].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[1]), + .q (reg2hw.mio_pad_attr[10].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_10_virtual_od_en_10_qs) + ); + assign reg2hw.mio_pad_attr[10].virtual_od_en.qe = mio_pad_attr_10_qe; + + // F[pull_en_10]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_pull_en_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_pull_en_10_wd), + .d (hw2reg.mio_pad_attr[10].pull_en.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[2]), + .q (reg2hw.mio_pad_attr[10].pull_en.q), + .ds (), + .qs (mio_pad_attr_10_pull_en_10_qs) + ); + assign reg2hw.mio_pad_attr[10].pull_en.qe = mio_pad_attr_10_qe; + + // F[pull_select_10]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_pull_select_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_pull_select_10_wd), + .d (hw2reg.mio_pad_attr[10].pull_select.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[3]), + .q (reg2hw.mio_pad_attr[10].pull_select.q), + .ds (), + .qs (mio_pad_attr_10_pull_select_10_qs) + ); + assign reg2hw.mio_pad_attr[10].pull_select.qe = mio_pad_attr_10_qe; + + // F[keeper_en_10]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_keeper_en_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_keeper_en_10_wd), + .d (hw2reg.mio_pad_attr[10].keeper_en.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[4]), + .q (reg2hw.mio_pad_attr[10].keeper_en.q), + .ds (), + .qs (mio_pad_attr_10_keeper_en_10_qs) + ); + assign reg2hw.mio_pad_attr[10].keeper_en.qe = mio_pad_attr_10_qe; + + // F[schmitt_en_10]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_schmitt_en_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_schmitt_en_10_wd), + .d (hw2reg.mio_pad_attr[10].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[5]), + .q (reg2hw.mio_pad_attr[10].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_10_schmitt_en_10_qs) + ); + assign reg2hw.mio_pad_attr[10].schmitt_en.qe = mio_pad_attr_10_qe; + + // F[od_en_10]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_od_en_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_od_en_10_wd), + .d (hw2reg.mio_pad_attr[10].od_en.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[6]), + .q (reg2hw.mio_pad_attr[10].od_en.q), + .ds (), + .qs (mio_pad_attr_10_od_en_10_qs) + ); + assign reg2hw.mio_pad_attr[10].od_en.qe = mio_pad_attr_10_qe; + + // F[input_disable_10]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_input_disable_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_input_disable_10_wd), + .d (hw2reg.mio_pad_attr[10].input_disable.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[7]), + .q (reg2hw.mio_pad_attr[10].input_disable.q), + .ds (), + .qs (mio_pad_attr_10_input_disable_10_qs) + ); + assign reg2hw.mio_pad_attr[10].input_disable.qe = mio_pad_attr_10_qe; + + // F[slew_rate_10]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_10_slew_rate_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_slew_rate_10_wd), + .d (hw2reg.mio_pad_attr[10].slew_rate.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[8]), + .q (reg2hw.mio_pad_attr[10].slew_rate.q), + .ds (), + .qs (mio_pad_attr_10_slew_rate_10_qs) + ); + assign reg2hw.mio_pad_attr[10].slew_rate.qe = mio_pad_attr_10_qe; + + // F[drive_strength_10]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_10_drive_strength_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_drive_strength_10_wd), + .d (hw2reg.mio_pad_attr[10].drive_strength.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[9]), + .q (reg2hw.mio_pad_attr[10].drive_strength.q), + .ds (), + .qs (mio_pad_attr_10_drive_strength_10_qs) + ); + assign reg2hw.mio_pad_attr[10].drive_strength.qe = mio_pad_attr_10_qe; + + + // Subregister 11 of Multireg mio_pad_attr + // R[mio_pad_attr_11]: V(True) + logic mio_pad_attr_11_qe; + logic [9:0] mio_pad_attr_11_flds_we; + assign mio_pad_attr_11_qe = &mio_pad_attr_11_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_11_gated_we; + assign mio_pad_attr_11_gated_we = mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs; + // F[invert_11]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_invert_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_invert_11_wd), + .d (hw2reg.mio_pad_attr[11].invert.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[0]), + .q (reg2hw.mio_pad_attr[11].invert.q), + .ds (), + .qs (mio_pad_attr_11_invert_11_qs) + ); + assign reg2hw.mio_pad_attr[11].invert.qe = mio_pad_attr_11_qe; + + // F[virtual_od_en_11]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_virtual_od_en_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_virtual_od_en_11_wd), + .d (hw2reg.mio_pad_attr[11].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[1]), + .q (reg2hw.mio_pad_attr[11].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_11_virtual_od_en_11_qs) + ); + assign reg2hw.mio_pad_attr[11].virtual_od_en.qe = mio_pad_attr_11_qe; + + // F[pull_en_11]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_pull_en_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_pull_en_11_wd), + .d (hw2reg.mio_pad_attr[11].pull_en.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[2]), + .q (reg2hw.mio_pad_attr[11].pull_en.q), + .ds (), + .qs (mio_pad_attr_11_pull_en_11_qs) + ); + assign reg2hw.mio_pad_attr[11].pull_en.qe = mio_pad_attr_11_qe; + + // F[pull_select_11]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_pull_select_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_pull_select_11_wd), + .d (hw2reg.mio_pad_attr[11].pull_select.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[3]), + .q (reg2hw.mio_pad_attr[11].pull_select.q), + .ds (), + .qs (mio_pad_attr_11_pull_select_11_qs) + ); + assign reg2hw.mio_pad_attr[11].pull_select.qe = mio_pad_attr_11_qe; + + // F[keeper_en_11]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_keeper_en_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_keeper_en_11_wd), + .d (hw2reg.mio_pad_attr[11].keeper_en.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[4]), + .q (reg2hw.mio_pad_attr[11].keeper_en.q), + .ds (), + .qs (mio_pad_attr_11_keeper_en_11_qs) + ); + assign reg2hw.mio_pad_attr[11].keeper_en.qe = mio_pad_attr_11_qe; + + // F[schmitt_en_11]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_schmitt_en_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_schmitt_en_11_wd), + .d (hw2reg.mio_pad_attr[11].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[5]), + .q (reg2hw.mio_pad_attr[11].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_11_schmitt_en_11_qs) + ); + assign reg2hw.mio_pad_attr[11].schmitt_en.qe = mio_pad_attr_11_qe; + + // F[od_en_11]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_od_en_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_od_en_11_wd), + .d (hw2reg.mio_pad_attr[11].od_en.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[6]), + .q (reg2hw.mio_pad_attr[11].od_en.q), + .ds (), + .qs (mio_pad_attr_11_od_en_11_qs) + ); + assign reg2hw.mio_pad_attr[11].od_en.qe = mio_pad_attr_11_qe; + + // F[input_disable_11]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_input_disable_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_input_disable_11_wd), + .d (hw2reg.mio_pad_attr[11].input_disable.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[7]), + .q (reg2hw.mio_pad_attr[11].input_disable.q), + .ds (), + .qs (mio_pad_attr_11_input_disable_11_qs) + ); + assign reg2hw.mio_pad_attr[11].input_disable.qe = mio_pad_attr_11_qe; + + // F[slew_rate_11]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_11_slew_rate_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_slew_rate_11_wd), + .d (hw2reg.mio_pad_attr[11].slew_rate.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[8]), + .q (reg2hw.mio_pad_attr[11].slew_rate.q), + .ds (), + .qs (mio_pad_attr_11_slew_rate_11_qs) + ); + assign reg2hw.mio_pad_attr[11].slew_rate.qe = mio_pad_attr_11_qe; + + // F[drive_strength_11]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_11_drive_strength_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_drive_strength_11_wd), + .d (hw2reg.mio_pad_attr[11].drive_strength.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[9]), + .q (reg2hw.mio_pad_attr[11].drive_strength.q), + .ds (), + .qs (mio_pad_attr_11_drive_strength_11_qs) + ); + assign reg2hw.mio_pad_attr[11].drive_strength.qe = mio_pad_attr_11_qe; + + + // Subregister 0 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_0_we), + .wd (dio_pad_attr_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_0_qs) + ); + + + // Subregister 1 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_1_we), + .wd (dio_pad_attr_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_1_qs) + ); + + + // Subregister 2 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_2_we), + .wd (dio_pad_attr_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_2_qs) + ); + + + // Subregister 3 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_3_we), + .wd (dio_pad_attr_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_3_qs) + ); + + + // Subregister 4 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_4_we), + .wd (dio_pad_attr_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_4_qs) + ); + + + // Subregister 5 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_5_we), + .wd (dio_pad_attr_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_5_qs) + ); + + + // Subregister 6 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_6_we), + .wd (dio_pad_attr_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_6_qs) + ); + + + // Subregister 7 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_7_we), + .wd (dio_pad_attr_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_7_qs) + ); + + + // Subregister 8 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_8_we), + .wd (dio_pad_attr_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_8_qs) + ); + + + // Subregister 9 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_9_we), + .wd (dio_pad_attr_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_9_qs) + ); + + + // Subregister 10 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_10_we), + .wd (dio_pad_attr_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_10_qs) + ); + + + // Subregister 11 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_11_we), + .wd (dio_pad_attr_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_11_qs) + ); + + + // Subregister 12 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_12]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_12_we), + .wd (dio_pad_attr_regwen_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_12_qs) + ); + + + // Subregister 13 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_13]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_13_we), + .wd (dio_pad_attr_regwen_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_13_qs) + ); + + + // Subregister 14 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_14]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_14_we), + .wd (dio_pad_attr_regwen_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_14_qs) + ); + + + // Subregister 15 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_15]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_15_we), + .wd (dio_pad_attr_regwen_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_15_qs) + ); + + + // Subregister 16 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_16]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_16_we), + .wd (dio_pad_attr_regwen_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_16_qs) + ); + + + // Subregister 17 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_17]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_17_we), + .wd (dio_pad_attr_regwen_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_17_qs) + ); + + + // Subregister 18 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_18]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_18_we), + .wd (dio_pad_attr_regwen_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_18_qs) + ); + + + // Subregister 19 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_19]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_19_we), + .wd (dio_pad_attr_regwen_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_19_qs) + ); + + + // Subregister 20 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_20]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_20_we), + .wd (dio_pad_attr_regwen_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_20_qs) + ); + + + // Subregister 21 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_21]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_21_we), + .wd (dio_pad_attr_regwen_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_21_qs) + ); + + + // Subregister 22 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_22]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_22_we), + .wd (dio_pad_attr_regwen_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_22_qs) + ); + + + // Subregister 23 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_23]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_23_we), + .wd (dio_pad_attr_regwen_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_23_qs) + ); + + + // Subregister 24 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_24]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_24_we), + .wd (dio_pad_attr_regwen_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_24_qs) + ); + + + // Subregister 25 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_25]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_25_we), + .wd (dio_pad_attr_regwen_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_25_qs) + ); + + + // Subregister 26 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_26]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_26_we), + .wd (dio_pad_attr_regwen_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_26_qs) + ); + + + // Subregister 27 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_27]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_27_we), + .wd (dio_pad_attr_regwen_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_27_qs) + ); + + + // Subregister 28 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_28]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_28_we), + .wd (dio_pad_attr_regwen_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_28_qs) + ); + + + // Subregister 29 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_29]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_29_we), + .wd (dio_pad_attr_regwen_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_29_qs) + ); + + + // Subregister 30 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_30]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_30_we), + .wd (dio_pad_attr_regwen_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_30_qs) + ); + + + // Subregister 31 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_31]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_31_we), + .wd (dio_pad_attr_regwen_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_31_qs) + ); + + + // Subregister 32 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_32]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_32_we), + .wd (dio_pad_attr_regwen_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_32_qs) + ); + + + // Subregister 33 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_33]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_33_we), + .wd (dio_pad_attr_regwen_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_33_qs) + ); + + + // Subregister 34 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_34]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_34_we), + .wd (dio_pad_attr_regwen_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_34_qs) + ); + + + // Subregister 35 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_35]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_35_we), + .wd (dio_pad_attr_regwen_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_35_qs) + ); + + + // Subregister 36 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_36]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_36_we), + .wd (dio_pad_attr_regwen_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_36_qs) + ); + + + // Subregister 37 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_37]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_37_we), + .wd (dio_pad_attr_regwen_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_37_qs) + ); + + + // Subregister 38 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_38]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_38_we), + .wd (dio_pad_attr_regwen_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_38_qs) + ); + + + // Subregister 39 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_39]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_39_we), + .wd (dio_pad_attr_regwen_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_39_qs) + ); + + + // Subregister 40 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_40]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_40_we), + .wd (dio_pad_attr_regwen_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_40_qs) + ); + + + // Subregister 41 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_41]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_41_we), + .wd (dio_pad_attr_regwen_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_41_qs) + ); + + + // Subregister 42 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_42]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_42_we), + .wd (dio_pad_attr_regwen_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_42_qs) + ); + + + // Subregister 43 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_43]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_43_we), + .wd (dio_pad_attr_regwen_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_43_qs) + ); + + + // Subregister 44 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_44]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_44_we), + .wd (dio_pad_attr_regwen_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_44_qs) + ); + + + // Subregister 45 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_45]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_45_we), + .wd (dio_pad_attr_regwen_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_45_qs) + ); + + + // Subregister 46 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_46]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_46_we), + .wd (dio_pad_attr_regwen_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_46_qs) + ); + + + // Subregister 47 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_47]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_47_we), + .wd (dio_pad_attr_regwen_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_47_qs) + ); + + + // Subregister 48 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_48]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_48_we), + .wd (dio_pad_attr_regwen_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_48_qs) + ); + + + // Subregister 49 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_49]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_49_we), + .wd (dio_pad_attr_regwen_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_49_qs) + ); + + + // Subregister 50 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_50]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_50_we), + .wd (dio_pad_attr_regwen_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_50_qs) + ); + + + // Subregister 51 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_51]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_51_we), + .wd (dio_pad_attr_regwen_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_51_qs) + ); + + + // Subregister 52 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_52]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_52_we), + .wd (dio_pad_attr_regwen_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_52_qs) + ); + + + // Subregister 53 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_53]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_53_we), + .wd (dio_pad_attr_regwen_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_53_qs) + ); + + + // Subregister 54 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_54]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_54_we), + .wd (dio_pad_attr_regwen_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_54_qs) + ); + + + // Subregister 55 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_55]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_55_we), + .wd (dio_pad_attr_regwen_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_55_qs) + ); + + + // Subregister 56 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_56]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_56_we), + .wd (dio_pad_attr_regwen_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_56_qs) + ); + + + // Subregister 57 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_57]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_57_we), + .wd (dio_pad_attr_regwen_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_57_qs) + ); + + + // Subregister 58 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_58]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_58_we), + .wd (dio_pad_attr_regwen_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_58_qs) + ); + + + // Subregister 59 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_59]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_59_we), + .wd (dio_pad_attr_regwen_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_59_qs) + ); + + + // Subregister 60 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_60]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_60_we), + .wd (dio_pad_attr_regwen_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_60_qs) + ); + + + // Subregister 61 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_61]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_61_we), + .wd (dio_pad_attr_regwen_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_61_qs) + ); + + + // Subregister 62 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_62]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_62_we), + .wd (dio_pad_attr_regwen_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_62_qs) + ); + + + // Subregister 63 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_63]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_63_we), + .wd (dio_pad_attr_regwen_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_63_qs) + ); + + + // Subregister 64 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_64]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_64_we), + .wd (dio_pad_attr_regwen_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_64_qs) + ); + + + // Subregister 65 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_65]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_65_we), + .wd (dio_pad_attr_regwen_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_65_qs) + ); + + + // Subregister 66 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_66]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_66_we), + .wd (dio_pad_attr_regwen_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_66_qs) + ); + + + // Subregister 67 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_67]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_67_we), + .wd (dio_pad_attr_regwen_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_67_qs) + ); + + + // Subregister 68 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_68]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_68_we), + .wd (dio_pad_attr_regwen_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_68_qs) + ); + + + // Subregister 69 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_69]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_69_we), + .wd (dio_pad_attr_regwen_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_69_qs) + ); + + + // Subregister 70 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_70]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_70_we), + .wd (dio_pad_attr_regwen_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_70_qs) + ); + + + // Subregister 71 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_71]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_71_we), + .wd (dio_pad_attr_regwen_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_71_qs) + ); + + + // Subregister 72 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_72]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_72_we), + .wd (dio_pad_attr_regwen_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_72_qs) + ); + + + // Subregister 0 of Multireg dio_pad_attr + // R[dio_pad_attr_0]: V(True) + logic dio_pad_attr_0_qe; + logic [9:0] dio_pad_attr_0_flds_we; + assign dio_pad_attr_0_qe = &dio_pad_attr_0_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_0_gated_we; + assign dio_pad_attr_0_gated_we = dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs; + // F[invert_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_invert_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_invert_0_wd), + .d (hw2reg.dio_pad_attr[0].invert.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[0]), + .q (reg2hw.dio_pad_attr[0].invert.q), + .ds (), + .qs (dio_pad_attr_0_invert_0_qs) + ); + assign reg2hw.dio_pad_attr[0].invert.qe = dio_pad_attr_0_qe; + + // F[virtual_od_en_0]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_virtual_od_en_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_virtual_od_en_0_wd), + .d (hw2reg.dio_pad_attr[0].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[1]), + .q (reg2hw.dio_pad_attr[0].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_0_virtual_od_en_0_qs) + ); + assign reg2hw.dio_pad_attr[0].virtual_od_en.qe = dio_pad_attr_0_qe; + + // F[pull_en_0]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_pull_en_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_pull_en_0_wd), + .d (hw2reg.dio_pad_attr[0].pull_en.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[2]), + .q (reg2hw.dio_pad_attr[0].pull_en.q), + .ds (), + .qs (dio_pad_attr_0_pull_en_0_qs) + ); + assign reg2hw.dio_pad_attr[0].pull_en.qe = dio_pad_attr_0_qe; + + // F[pull_select_0]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_pull_select_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_pull_select_0_wd), + .d (hw2reg.dio_pad_attr[0].pull_select.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[3]), + .q (reg2hw.dio_pad_attr[0].pull_select.q), + .ds (), + .qs (dio_pad_attr_0_pull_select_0_qs) + ); + assign reg2hw.dio_pad_attr[0].pull_select.qe = dio_pad_attr_0_qe; + + // F[keeper_en_0]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_keeper_en_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_keeper_en_0_wd), + .d (hw2reg.dio_pad_attr[0].keeper_en.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[4]), + .q (reg2hw.dio_pad_attr[0].keeper_en.q), + .ds (), + .qs (dio_pad_attr_0_keeper_en_0_qs) + ); + assign reg2hw.dio_pad_attr[0].keeper_en.qe = dio_pad_attr_0_qe; + + // F[schmitt_en_0]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_schmitt_en_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_schmitt_en_0_wd), + .d (hw2reg.dio_pad_attr[0].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[5]), + .q (reg2hw.dio_pad_attr[0].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_0_schmitt_en_0_qs) + ); + assign reg2hw.dio_pad_attr[0].schmitt_en.qe = dio_pad_attr_0_qe; + + // F[od_en_0]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_od_en_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_od_en_0_wd), + .d (hw2reg.dio_pad_attr[0].od_en.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[6]), + .q (reg2hw.dio_pad_attr[0].od_en.q), + .ds (), + .qs (dio_pad_attr_0_od_en_0_qs) + ); + assign reg2hw.dio_pad_attr[0].od_en.qe = dio_pad_attr_0_qe; + + // F[input_disable_0]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_input_disable_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_input_disable_0_wd), + .d (hw2reg.dio_pad_attr[0].input_disable.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[7]), + .q (reg2hw.dio_pad_attr[0].input_disable.q), + .ds (), + .qs (dio_pad_attr_0_input_disable_0_qs) + ); + assign reg2hw.dio_pad_attr[0].input_disable.qe = dio_pad_attr_0_qe; + + // F[slew_rate_0]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_0_slew_rate_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_slew_rate_0_wd), + .d (hw2reg.dio_pad_attr[0].slew_rate.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[8]), + .q (reg2hw.dio_pad_attr[0].slew_rate.q), + .ds (), + .qs (dio_pad_attr_0_slew_rate_0_qs) + ); + assign reg2hw.dio_pad_attr[0].slew_rate.qe = dio_pad_attr_0_qe; + + // F[drive_strength_0]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_0_drive_strength_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_drive_strength_0_wd), + .d (hw2reg.dio_pad_attr[0].drive_strength.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[9]), + .q (reg2hw.dio_pad_attr[0].drive_strength.q), + .ds (), + .qs (dio_pad_attr_0_drive_strength_0_qs) + ); + assign reg2hw.dio_pad_attr[0].drive_strength.qe = dio_pad_attr_0_qe; + + + // Subregister 1 of Multireg dio_pad_attr + // R[dio_pad_attr_1]: V(True) + logic dio_pad_attr_1_qe; + logic [9:0] dio_pad_attr_1_flds_we; + assign dio_pad_attr_1_qe = &dio_pad_attr_1_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_1_gated_we; + assign dio_pad_attr_1_gated_we = dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs; + // F[invert_1]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_invert_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_invert_1_wd), + .d (hw2reg.dio_pad_attr[1].invert.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[0]), + .q (reg2hw.dio_pad_attr[1].invert.q), + .ds (), + .qs (dio_pad_attr_1_invert_1_qs) + ); + assign reg2hw.dio_pad_attr[1].invert.qe = dio_pad_attr_1_qe; + + // F[virtual_od_en_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_virtual_od_en_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_virtual_od_en_1_wd), + .d (hw2reg.dio_pad_attr[1].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[1]), + .q (reg2hw.dio_pad_attr[1].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_1_virtual_od_en_1_qs) + ); + assign reg2hw.dio_pad_attr[1].virtual_od_en.qe = dio_pad_attr_1_qe; + + // F[pull_en_1]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_pull_en_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_pull_en_1_wd), + .d (hw2reg.dio_pad_attr[1].pull_en.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[2]), + .q (reg2hw.dio_pad_attr[1].pull_en.q), + .ds (), + .qs (dio_pad_attr_1_pull_en_1_qs) + ); + assign reg2hw.dio_pad_attr[1].pull_en.qe = dio_pad_attr_1_qe; + + // F[pull_select_1]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_pull_select_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_pull_select_1_wd), + .d (hw2reg.dio_pad_attr[1].pull_select.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[3]), + .q (reg2hw.dio_pad_attr[1].pull_select.q), + .ds (), + .qs (dio_pad_attr_1_pull_select_1_qs) + ); + assign reg2hw.dio_pad_attr[1].pull_select.qe = dio_pad_attr_1_qe; + + // F[keeper_en_1]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_keeper_en_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_keeper_en_1_wd), + .d (hw2reg.dio_pad_attr[1].keeper_en.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[4]), + .q (reg2hw.dio_pad_attr[1].keeper_en.q), + .ds (), + .qs (dio_pad_attr_1_keeper_en_1_qs) + ); + assign reg2hw.dio_pad_attr[1].keeper_en.qe = dio_pad_attr_1_qe; + + // F[schmitt_en_1]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_schmitt_en_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_schmitt_en_1_wd), + .d (hw2reg.dio_pad_attr[1].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[5]), + .q (reg2hw.dio_pad_attr[1].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_1_schmitt_en_1_qs) + ); + assign reg2hw.dio_pad_attr[1].schmitt_en.qe = dio_pad_attr_1_qe; + + // F[od_en_1]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_od_en_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_od_en_1_wd), + .d (hw2reg.dio_pad_attr[1].od_en.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[6]), + .q (reg2hw.dio_pad_attr[1].od_en.q), + .ds (), + .qs (dio_pad_attr_1_od_en_1_qs) + ); + assign reg2hw.dio_pad_attr[1].od_en.qe = dio_pad_attr_1_qe; + + // F[input_disable_1]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_input_disable_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_input_disable_1_wd), + .d (hw2reg.dio_pad_attr[1].input_disable.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[7]), + .q (reg2hw.dio_pad_attr[1].input_disable.q), + .ds (), + .qs (dio_pad_attr_1_input_disable_1_qs) + ); + assign reg2hw.dio_pad_attr[1].input_disable.qe = dio_pad_attr_1_qe; + + // F[slew_rate_1]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_1_slew_rate_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_slew_rate_1_wd), + .d (hw2reg.dio_pad_attr[1].slew_rate.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[8]), + .q (reg2hw.dio_pad_attr[1].slew_rate.q), + .ds (), + .qs (dio_pad_attr_1_slew_rate_1_qs) + ); + assign reg2hw.dio_pad_attr[1].slew_rate.qe = dio_pad_attr_1_qe; + + // F[drive_strength_1]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_1_drive_strength_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_drive_strength_1_wd), + .d (hw2reg.dio_pad_attr[1].drive_strength.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[9]), + .q (reg2hw.dio_pad_attr[1].drive_strength.q), + .ds (), + .qs (dio_pad_attr_1_drive_strength_1_qs) + ); + assign reg2hw.dio_pad_attr[1].drive_strength.qe = dio_pad_attr_1_qe; + + + // Subregister 2 of Multireg dio_pad_attr + // R[dio_pad_attr_2]: V(True) + logic dio_pad_attr_2_qe; + logic [9:0] dio_pad_attr_2_flds_we; + assign dio_pad_attr_2_qe = &dio_pad_attr_2_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_2_gated_we; + assign dio_pad_attr_2_gated_we = dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs; + // F[invert_2]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_invert_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_invert_2_wd), + .d (hw2reg.dio_pad_attr[2].invert.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[0]), + .q (reg2hw.dio_pad_attr[2].invert.q), + .ds (), + .qs (dio_pad_attr_2_invert_2_qs) + ); + assign reg2hw.dio_pad_attr[2].invert.qe = dio_pad_attr_2_qe; + + // F[virtual_od_en_2]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_virtual_od_en_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_virtual_od_en_2_wd), + .d (hw2reg.dio_pad_attr[2].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[1]), + .q (reg2hw.dio_pad_attr[2].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_2_virtual_od_en_2_qs) + ); + assign reg2hw.dio_pad_attr[2].virtual_od_en.qe = dio_pad_attr_2_qe; + + // F[pull_en_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_pull_en_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_pull_en_2_wd), + .d (hw2reg.dio_pad_attr[2].pull_en.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[2]), + .q (reg2hw.dio_pad_attr[2].pull_en.q), + .ds (), + .qs (dio_pad_attr_2_pull_en_2_qs) + ); + assign reg2hw.dio_pad_attr[2].pull_en.qe = dio_pad_attr_2_qe; + + // F[pull_select_2]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_pull_select_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_pull_select_2_wd), + .d (hw2reg.dio_pad_attr[2].pull_select.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[3]), + .q (reg2hw.dio_pad_attr[2].pull_select.q), + .ds (), + .qs (dio_pad_attr_2_pull_select_2_qs) + ); + assign reg2hw.dio_pad_attr[2].pull_select.qe = dio_pad_attr_2_qe; + + // F[keeper_en_2]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_keeper_en_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_keeper_en_2_wd), + .d (hw2reg.dio_pad_attr[2].keeper_en.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[4]), + .q (reg2hw.dio_pad_attr[2].keeper_en.q), + .ds (), + .qs (dio_pad_attr_2_keeper_en_2_qs) + ); + assign reg2hw.dio_pad_attr[2].keeper_en.qe = dio_pad_attr_2_qe; + + // F[schmitt_en_2]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_schmitt_en_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_schmitt_en_2_wd), + .d (hw2reg.dio_pad_attr[2].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[5]), + .q (reg2hw.dio_pad_attr[2].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_2_schmitt_en_2_qs) + ); + assign reg2hw.dio_pad_attr[2].schmitt_en.qe = dio_pad_attr_2_qe; + + // F[od_en_2]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_od_en_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_od_en_2_wd), + .d (hw2reg.dio_pad_attr[2].od_en.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[6]), + .q (reg2hw.dio_pad_attr[2].od_en.q), + .ds (), + .qs (dio_pad_attr_2_od_en_2_qs) + ); + assign reg2hw.dio_pad_attr[2].od_en.qe = dio_pad_attr_2_qe; + + // F[input_disable_2]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_input_disable_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_input_disable_2_wd), + .d (hw2reg.dio_pad_attr[2].input_disable.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[7]), + .q (reg2hw.dio_pad_attr[2].input_disable.q), + .ds (), + .qs (dio_pad_attr_2_input_disable_2_qs) + ); + assign reg2hw.dio_pad_attr[2].input_disable.qe = dio_pad_attr_2_qe; + + // F[slew_rate_2]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_2_slew_rate_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_slew_rate_2_wd), + .d (hw2reg.dio_pad_attr[2].slew_rate.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[8]), + .q (reg2hw.dio_pad_attr[2].slew_rate.q), + .ds (), + .qs (dio_pad_attr_2_slew_rate_2_qs) + ); + assign reg2hw.dio_pad_attr[2].slew_rate.qe = dio_pad_attr_2_qe; + + // F[drive_strength_2]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_2_drive_strength_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_drive_strength_2_wd), + .d (hw2reg.dio_pad_attr[2].drive_strength.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[9]), + .q (reg2hw.dio_pad_attr[2].drive_strength.q), + .ds (), + .qs (dio_pad_attr_2_drive_strength_2_qs) + ); + assign reg2hw.dio_pad_attr[2].drive_strength.qe = dio_pad_attr_2_qe; + + + // Subregister 3 of Multireg dio_pad_attr + // R[dio_pad_attr_3]: V(True) + logic dio_pad_attr_3_qe; + logic [9:0] dio_pad_attr_3_flds_we; + assign dio_pad_attr_3_qe = &dio_pad_attr_3_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_3_gated_we; + assign dio_pad_attr_3_gated_we = dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs; + // F[invert_3]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_invert_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_invert_3_wd), + .d (hw2reg.dio_pad_attr[3].invert.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[0]), + .q (reg2hw.dio_pad_attr[3].invert.q), + .ds (), + .qs (dio_pad_attr_3_invert_3_qs) + ); + assign reg2hw.dio_pad_attr[3].invert.qe = dio_pad_attr_3_qe; + + // F[virtual_od_en_3]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_virtual_od_en_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_virtual_od_en_3_wd), + .d (hw2reg.dio_pad_attr[3].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[1]), + .q (reg2hw.dio_pad_attr[3].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_3_virtual_od_en_3_qs) + ); + assign reg2hw.dio_pad_attr[3].virtual_od_en.qe = dio_pad_attr_3_qe; + + // F[pull_en_3]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_pull_en_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_pull_en_3_wd), + .d (hw2reg.dio_pad_attr[3].pull_en.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[2]), + .q (reg2hw.dio_pad_attr[3].pull_en.q), + .ds (), + .qs (dio_pad_attr_3_pull_en_3_qs) + ); + assign reg2hw.dio_pad_attr[3].pull_en.qe = dio_pad_attr_3_qe; + + // F[pull_select_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_pull_select_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_pull_select_3_wd), + .d (hw2reg.dio_pad_attr[3].pull_select.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[3]), + .q (reg2hw.dio_pad_attr[3].pull_select.q), + .ds (), + .qs (dio_pad_attr_3_pull_select_3_qs) + ); + assign reg2hw.dio_pad_attr[3].pull_select.qe = dio_pad_attr_3_qe; + + // F[keeper_en_3]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_keeper_en_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_keeper_en_3_wd), + .d (hw2reg.dio_pad_attr[3].keeper_en.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[4]), + .q (reg2hw.dio_pad_attr[3].keeper_en.q), + .ds (), + .qs (dio_pad_attr_3_keeper_en_3_qs) + ); + assign reg2hw.dio_pad_attr[3].keeper_en.qe = dio_pad_attr_3_qe; + + // F[schmitt_en_3]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_schmitt_en_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_schmitt_en_3_wd), + .d (hw2reg.dio_pad_attr[3].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[5]), + .q (reg2hw.dio_pad_attr[3].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_3_schmitt_en_3_qs) + ); + assign reg2hw.dio_pad_attr[3].schmitt_en.qe = dio_pad_attr_3_qe; + + // F[od_en_3]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_od_en_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_od_en_3_wd), + .d (hw2reg.dio_pad_attr[3].od_en.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[6]), + .q (reg2hw.dio_pad_attr[3].od_en.q), + .ds (), + .qs (dio_pad_attr_3_od_en_3_qs) + ); + assign reg2hw.dio_pad_attr[3].od_en.qe = dio_pad_attr_3_qe; + + // F[input_disable_3]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_input_disable_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_input_disable_3_wd), + .d (hw2reg.dio_pad_attr[3].input_disable.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[7]), + .q (reg2hw.dio_pad_attr[3].input_disable.q), + .ds (), + .qs (dio_pad_attr_3_input_disable_3_qs) + ); + assign reg2hw.dio_pad_attr[3].input_disable.qe = dio_pad_attr_3_qe; + + // F[slew_rate_3]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_3_slew_rate_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_slew_rate_3_wd), + .d (hw2reg.dio_pad_attr[3].slew_rate.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[8]), + .q (reg2hw.dio_pad_attr[3].slew_rate.q), + .ds (), + .qs (dio_pad_attr_3_slew_rate_3_qs) + ); + assign reg2hw.dio_pad_attr[3].slew_rate.qe = dio_pad_attr_3_qe; + + // F[drive_strength_3]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_3_drive_strength_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_drive_strength_3_wd), + .d (hw2reg.dio_pad_attr[3].drive_strength.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[9]), + .q (reg2hw.dio_pad_attr[3].drive_strength.q), + .ds (), + .qs (dio_pad_attr_3_drive_strength_3_qs) + ); + assign reg2hw.dio_pad_attr[3].drive_strength.qe = dio_pad_attr_3_qe; + + + // Subregister 4 of Multireg dio_pad_attr + // R[dio_pad_attr_4]: V(True) + logic dio_pad_attr_4_qe; + logic [9:0] dio_pad_attr_4_flds_we; + assign dio_pad_attr_4_qe = &dio_pad_attr_4_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_4_gated_we; + assign dio_pad_attr_4_gated_we = dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs; + // F[invert_4]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_invert_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_invert_4_wd), + .d (hw2reg.dio_pad_attr[4].invert.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[0]), + .q (reg2hw.dio_pad_attr[4].invert.q), + .ds (), + .qs (dio_pad_attr_4_invert_4_qs) + ); + assign reg2hw.dio_pad_attr[4].invert.qe = dio_pad_attr_4_qe; + + // F[virtual_od_en_4]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_virtual_od_en_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_virtual_od_en_4_wd), + .d (hw2reg.dio_pad_attr[4].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[1]), + .q (reg2hw.dio_pad_attr[4].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_4_virtual_od_en_4_qs) + ); + assign reg2hw.dio_pad_attr[4].virtual_od_en.qe = dio_pad_attr_4_qe; + + // F[pull_en_4]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_pull_en_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_pull_en_4_wd), + .d (hw2reg.dio_pad_attr[4].pull_en.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[2]), + .q (reg2hw.dio_pad_attr[4].pull_en.q), + .ds (), + .qs (dio_pad_attr_4_pull_en_4_qs) + ); + assign reg2hw.dio_pad_attr[4].pull_en.qe = dio_pad_attr_4_qe; + + // F[pull_select_4]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_pull_select_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_pull_select_4_wd), + .d (hw2reg.dio_pad_attr[4].pull_select.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[3]), + .q (reg2hw.dio_pad_attr[4].pull_select.q), + .ds (), + .qs (dio_pad_attr_4_pull_select_4_qs) + ); + assign reg2hw.dio_pad_attr[4].pull_select.qe = dio_pad_attr_4_qe; + + // F[keeper_en_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_keeper_en_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_keeper_en_4_wd), + .d (hw2reg.dio_pad_attr[4].keeper_en.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[4]), + .q (reg2hw.dio_pad_attr[4].keeper_en.q), + .ds (), + .qs (dio_pad_attr_4_keeper_en_4_qs) + ); + assign reg2hw.dio_pad_attr[4].keeper_en.qe = dio_pad_attr_4_qe; + + // F[schmitt_en_4]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_schmitt_en_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_schmitt_en_4_wd), + .d (hw2reg.dio_pad_attr[4].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[5]), + .q (reg2hw.dio_pad_attr[4].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_4_schmitt_en_4_qs) + ); + assign reg2hw.dio_pad_attr[4].schmitt_en.qe = dio_pad_attr_4_qe; + + // F[od_en_4]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_od_en_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_od_en_4_wd), + .d (hw2reg.dio_pad_attr[4].od_en.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[6]), + .q (reg2hw.dio_pad_attr[4].od_en.q), + .ds (), + .qs (dio_pad_attr_4_od_en_4_qs) + ); + assign reg2hw.dio_pad_attr[4].od_en.qe = dio_pad_attr_4_qe; + + // F[input_disable_4]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_input_disable_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_input_disable_4_wd), + .d (hw2reg.dio_pad_attr[4].input_disable.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[7]), + .q (reg2hw.dio_pad_attr[4].input_disable.q), + .ds (), + .qs (dio_pad_attr_4_input_disable_4_qs) + ); + assign reg2hw.dio_pad_attr[4].input_disable.qe = dio_pad_attr_4_qe; + + // F[slew_rate_4]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_4_slew_rate_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_slew_rate_4_wd), + .d (hw2reg.dio_pad_attr[4].slew_rate.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[8]), + .q (reg2hw.dio_pad_attr[4].slew_rate.q), + .ds (), + .qs (dio_pad_attr_4_slew_rate_4_qs) + ); + assign reg2hw.dio_pad_attr[4].slew_rate.qe = dio_pad_attr_4_qe; + + // F[drive_strength_4]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_4_drive_strength_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_drive_strength_4_wd), + .d (hw2reg.dio_pad_attr[4].drive_strength.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[9]), + .q (reg2hw.dio_pad_attr[4].drive_strength.q), + .ds (), + .qs (dio_pad_attr_4_drive_strength_4_qs) + ); + assign reg2hw.dio_pad_attr[4].drive_strength.qe = dio_pad_attr_4_qe; + + + // Subregister 5 of Multireg dio_pad_attr + // R[dio_pad_attr_5]: V(True) + logic dio_pad_attr_5_qe; + logic [9:0] dio_pad_attr_5_flds_we; + assign dio_pad_attr_5_qe = &dio_pad_attr_5_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_5_gated_we; + assign dio_pad_attr_5_gated_we = dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs; + // F[invert_5]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_invert_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_invert_5_wd), + .d (hw2reg.dio_pad_attr[5].invert.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[0]), + .q (reg2hw.dio_pad_attr[5].invert.q), + .ds (), + .qs (dio_pad_attr_5_invert_5_qs) + ); + assign reg2hw.dio_pad_attr[5].invert.qe = dio_pad_attr_5_qe; + + // F[virtual_od_en_5]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_virtual_od_en_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_virtual_od_en_5_wd), + .d (hw2reg.dio_pad_attr[5].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[1]), + .q (reg2hw.dio_pad_attr[5].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_5_virtual_od_en_5_qs) + ); + assign reg2hw.dio_pad_attr[5].virtual_od_en.qe = dio_pad_attr_5_qe; + + // F[pull_en_5]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_pull_en_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_pull_en_5_wd), + .d (hw2reg.dio_pad_attr[5].pull_en.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[2]), + .q (reg2hw.dio_pad_attr[5].pull_en.q), + .ds (), + .qs (dio_pad_attr_5_pull_en_5_qs) + ); + assign reg2hw.dio_pad_attr[5].pull_en.qe = dio_pad_attr_5_qe; + + // F[pull_select_5]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_pull_select_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_pull_select_5_wd), + .d (hw2reg.dio_pad_attr[5].pull_select.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[3]), + .q (reg2hw.dio_pad_attr[5].pull_select.q), + .ds (), + .qs (dio_pad_attr_5_pull_select_5_qs) + ); + assign reg2hw.dio_pad_attr[5].pull_select.qe = dio_pad_attr_5_qe; + + // F[keeper_en_5]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_keeper_en_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_keeper_en_5_wd), + .d (hw2reg.dio_pad_attr[5].keeper_en.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[4]), + .q (reg2hw.dio_pad_attr[5].keeper_en.q), + .ds (), + .qs (dio_pad_attr_5_keeper_en_5_qs) + ); + assign reg2hw.dio_pad_attr[5].keeper_en.qe = dio_pad_attr_5_qe; + + // F[schmitt_en_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_schmitt_en_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_schmitt_en_5_wd), + .d (hw2reg.dio_pad_attr[5].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[5]), + .q (reg2hw.dio_pad_attr[5].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_5_schmitt_en_5_qs) + ); + assign reg2hw.dio_pad_attr[5].schmitt_en.qe = dio_pad_attr_5_qe; + + // F[od_en_5]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_od_en_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_od_en_5_wd), + .d (hw2reg.dio_pad_attr[5].od_en.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[6]), + .q (reg2hw.dio_pad_attr[5].od_en.q), + .ds (), + .qs (dio_pad_attr_5_od_en_5_qs) + ); + assign reg2hw.dio_pad_attr[5].od_en.qe = dio_pad_attr_5_qe; + + // F[input_disable_5]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_input_disable_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_input_disable_5_wd), + .d (hw2reg.dio_pad_attr[5].input_disable.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[7]), + .q (reg2hw.dio_pad_attr[5].input_disable.q), + .ds (), + .qs (dio_pad_attr_5_input_disable_5_qs) + ); + assign reg2hw.dio_pad_attr[5].input_disable.qe = dio_pad_attr_5_qe; + + // F[slew_rate_5]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_5_slew_rate_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_slew_rate_5_wd), + .d (hw2reg.dio_pad_attr[5].slew_rate.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[8]), + .q (reg2hw.dio_pad_attr[5].slew_rate.q), + .ds (), + .qs (dio_pad_attr_5_slew_rate_5_qs) + ); + assign reg2hw.dio_pad_attr[5].slew_rate.qe = dio_pad_attr_5_qe; + + // F[drive_strength_5]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_5_drive_strength_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_drive_strength_5_wd), + .d (hw2reg.dio_pad_attr[5].drive_strength.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[9]), + .q (reg2hw.dio_pad_attr[5].drive_strength.q), + .ds (), + .qs (dio_pad_attr_5_drive_strength_5_qs) + ); + assign reg2hw.dio_pad_attr[5].drive_strength.qe = dio_pad_attr_5_qe; + + + // Subregister 6 of Multireg dio_pad_attr + // R[dio_pad_attr_6]: V(True) + logic dio_pad_attr_6_qe; + logic [9:0] dio_pad_attr_6_flds_we; + assign dio_pad_attr_6_qe = &dio_pad_attr_6_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_6_gated_we; + assign dio_pad_attr_6_gated_we = dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs; + // F[invert_6]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_invert_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_invert_6_wd), + .d (hw2reg.dio_pad_attr[6].invert.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[0]), + .q (reg2hw.dio_pad_attr[6].invert.q), + .ds (), + .qs (dio_pad_attr_6_invert_6_qs) + ); + assign reg2hw.dio_pad_attr[6].invert.qe = dio_pad_attr_6_qe; + + // F[virtual_od_en_6]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_virtual_od_en_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_virtual_od_en_6_wd), + .d (hw2reg.dio_pad_attr[6].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[1]), + .q (reg2hw.dio_pad_attr[6].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_6_virtual_od_en_6_qs) + ); + assign reg2hw.dio_pad_attr[6].virtual_od_en.qe = dio_pad_attr_6_qe; + + // F[pull_en_6]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_pull_en_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_pull_en_6_wd), + .d (hw2reg.dio_pad_attr[6].pull_en.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[2]), + .q (reg2hw.dio_pad_attr[6].pull_en.q), + .ds (), + .qs (dio_pad_attr_6_pull_en_6_qs) + ); + assign reg2hw.dio_pad_attr[6].pull_en.qe = dio_pad_attr_6_qe; + + // F[pull_select_6]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_pull_select_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_pull_select_6_wd), + .d (hw2reg.dio_pad_attr[6].pull_select.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[3]), + .q (reg2hw.dio_pad_attr[6].pull_select.q), + .ds (), + .qs (dio_pad_attr_6_pull_select_6_qs) + ); + assign reg2hw.dio_pad_attr[6].pull_select.qe = dio_pad_attr_6_qe; + + // F[keeper_en_6]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_keeper_en_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_keeper_en_6_wd), + .d (hw2reg.dio_pad_attr[6].keeper_en.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[4]), + .q (reg2hw.dio_pad_attr[6].keeper_en.q), + .ds (), + .qs (dio_pad_attr_6_keeper_en_6_qs) + ); + assign reg2hw.dio_pad_attr[6].keeper_en.qe = dio_pad_attr_6_qe; + + // F[schmitt_en_6]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_schmitt_en_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_schmitt_en_6_wd), + .d (hw2reg.dio_pad_attr[6].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[5]), + .q (reg2hw.dio_pad_attr[6].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_6_schmitt_en_6_qs) + ); + assign reg2hw.dio_pad_attr[6].schmitt_en.qe = dio_pad_attr_6_qe; + + // F[od_en_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_od_en_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_od_en_6_wd), + .d (hw2reg.dio_pad_attr[6].od_en.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[6]), + .q (reg2hw.dio_pad_attr[6].od_en.q), + .ds (), + .qs (dio_pad_attr_6_od_en_6_qs) + ); + assign reg2hw.dio_pad_attr[6].od_en.qe = dio_pad_attr_6_qe; + + // F[input_disable_6]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_input_disable_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_input_disable_6_wd), + .d (hw2reg.dio_pad_attr[6].input_disable.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[7]), + .q (reg2hw.dio_pad_attr[6].input_disable.q), + .ds (), + .qs (dio_pad_attr_6_input_disable_6_qs) + ); + assign reg2hw.dio_pad_attr[6].input_disable.qe = dio_pad_attr_6_qe; + + // F[slew_rate_6]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_6_slew_rate_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_slew_rate_6_wd), + .d (hw2reg.dio_pad_attr[6].slew_rate.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[8]), + .q (reg2hw.dio_pad_attr[6].slew_rate.q), + .ds (), + .qs (dio_pad_attr_6_slew_rate_6_qs) + ); + assign reg2hw.dio_pad_attr[6].slew_rate.qe = dio_pad_attr_6_qe; + + // F[drive_strength_6]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_6_drive_strength_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_drive_strength_6_wd), + .d (hw2reg.dio_pad_attr[6].drive_strength.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[9]), + .q (reg2hw.dio_pad_attr[6].drive_strength.q), + .ds (), + .qs (dio_pad_attr_6_drive_strength_6_qs) + ); + assign reg2hw.dio_pad_attr[6].drive_strength.qe = dio_pad_attr_6_qe; + + + // Subregister 7 of Multireg dio_pad_attr + // R[dio_pad_attr_7]: V(True) + logic dio_pad_attr_7_qe; + logic [9:0] dio_pad_attr_7_flds_we; + assign dio_pad_attr_7_qe = &dio_pad_attr_7_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_7_gated_we; + assign dio_pad_attr_7_gated_we = dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs; + // F[invert_7]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_invert_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_invert_7_wd), + .d (hw2reg.dio_pad_attr[7].invert.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[0]), + .q (reg2hw.dio_pad_attr[7].invert.q), + .ds (), + .qs (dio_pad_attr_7_invert_7_qs) + ); + assign reg2hw.dio_pad_attr[7].invert.qe = dio_pad_attr_7_qe; + + // F[virtual_od_en_7]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_virtual_od_en_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_virtual_od_en_7_wd), + .d (hw2reg.dio_pad_attr[7].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[1]), + .q (reg2hw.dio_pad_attr[7].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_7_virtual_od_en_7_qs) + ); + assign reg2hw.dio_pad_attr[7].virtual_od_en.qe = dio_pad_attr_7_qe; + + // F[pull_en_7]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_pull_en_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_pull_en_7_wd), + .d (hw2reg.dio_pad_attr[7].pull_en.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[2]), + .q (reg2hw.dio_pad_attr[7].pull_en.q), + .ds (), + .qs (dio_pad_attr_7_pull_en_7_qs) + ); + assign reg2hw.dio_pad_attr[7].pull_en.qe = dio_pad_attr_7_qe; + + // F[pull_select_7]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_pull_select_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_pull_select_7_wd), + .d (hw2reg.dio_pad_attr[7].pull_select.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[3]), + .q (reg2hw.dio_pad_attr[7].pull_select.q), + .ds (), + .qs (dio_pad_attr_7_pull_select_7_qs) + ); + assign reg2hw.dio_pad_attr[7].pull_select.qe = dio_pad_attr_7_qe; + + // F[keeper_en_7]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_keeper_en_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_keeper_en_7_wd), + .d (hw2reg.dio_pad_attr[7].keeper_en.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[4]), + .q (reg2hw.dio_pad_attr[7].keeper_en.q), + .ds (), + .qs (dio_pad_attr_7_keeper_en_7_qs) + ); + assign reg2hw.dio_pad_attr[7].keeper_en.qe = dio_pad_attr_7_qe; + + // F[schmitt_en_7]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_schmitt_en_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_schmitt_en_7_wd), + .d (hw2reg.dio_pad_attr[7].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[5]), + .q (reg2hw.dio_pad_attr[7].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_7_schmitt_en_7_qs) + ); + assign reg2hw.dio_pad_attr[7].schmitt_en.qe = dio_pad_attr_7_qe; + + // F[od_en_7]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_od_en_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_od_en_7_wd), + .d (hw2reg.dio_pad_attr[7].od_en.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[6]), + .q (reg2hw.dio_pad_attr[7].od_en.q), + .ds (), + .qs (dio_pad_attr_7_od_en_7_qs) + ); + assign reg2hw.dio_pad_attr[7].od_en.qe = dio_pad_attr_7_qe; + + // F[input_disable_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_input_disable_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_input_disable_7_wd), + .d (hw2reg.dio_pad_attr[7].input_disable.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[7]), + .q (reg2hw.dio_pad_attr[7].input_disable.q), + .ds (), + .qs (dio_pad_attr_7_input_disable_7_qs) + ); + assign reg2hw.dio_pad_attr[7].input_disable.qe = dio_pad_attr_7_qe; + + // F[slew_rate_7]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_7_slew_rate_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_slew_rate_7_wd), + .d (hw2reg.dio_pad_attr[7].slew_rate.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[8]), + .q (reg2hw.dio_pad_attr[7].slew_rate.q), + .ds (), + .qs (dio_pad_attr_7_slew_rate_7_qs) + ); + assign reg2hw.dio_pad_attr[7].slew_rate.qe = dio_pad_attr_7_qe; + + // F[drive_strength_7]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_7_drive_strength_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_drive_strength_7_wd), + .d (hw2reg.dio_pad_attr[7].drive_strength.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[9]), + .q (reg2hw.dio_pad_attr[7].drive_strength.q), + .ds (), + .qs (dio_pad_attr_7_drive_strength_7_qs) + ); + assign reg2hw.dio_pad_attr[7].drive_strength.qe = dio_pad_attr_7_qe; + + + // Subregister 8 of Multireg dio_pad_attr + // R[dio_pad_attr_8]: V(True) + logic dio_pad_attr_8_qe; + logic [9:0] dio_pad_attr_8_flds_we; + assign dio_pad_attr_8_qe = &dio_pad_attr_8_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_8_gated_we; + assign dio_pad_attr_8_gated_we = dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs; + // F[invert_8]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_invert_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_invert_8_wd), + .d (hw2reg.dio_pad_attr[8].invert.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[0]), + .q (reg2hw.dio_pad_attr[8].invert.q), + .ds (), + .qs (dio_pad_attr_8_invert_8_qs) + ); + assign reg2hw.dio_pad_attr[8].invert.qe = dio_pad_attr_8_qe; + + // F[virtual_od_en_8]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_virtual_od_en_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_virtual_od_en_8_wd), + .d (hw2reg.dio_pad_attr[8].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[1]), + .q (reg2hw.dio_pad_attr[8].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_8_virtual_od_en_8_qs) + ); + assign reg2hw.dio_pad_attr[8].virtual_od_en.qe = dio_pad_attr_8_qe; + + // F[pull_en_8]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_pull_en_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_pull_en_8_wd), + .d (hw2reg.dio_pad_attr[8].pull_en.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[2]), + .q (reg2hw.dio_pad_attr[8].pull_en.q), + .ds (), + .qs (dio_pad_attr_8_pull_en_8_qs) + ); + assign reg2hw.dio_pad_attr[8].pull_en.qe = dio_pad_attr_8_qe; + + // F[pull_select_8]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_pull_select_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_pull_select_8_wd), + .d (hw2reg.dio_pad_attr[8].pull_select.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[3]), + .q (reg2hw.dio_pad_attr[8].pull_select.q), + .ds (), + .qs (dio_pad_attr_8_pull_select_8_qs) + ); + assign reg2hw.dio_pad_attr[8].pull_select.qe = dio_pad_attr_8_qe; + + // F[keeper_en_8]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_keeper_en_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_keeper_en_8_wd), + .d (hw2reg.dio_pad_attr[8].keeper_en.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[4]), + .q (reg2hw.dio_pad_attr[8].keeper_en.q), + .ds (), + .qs (dio_pad_attr_8_keeper_en_8_qs) + ); + assign reg2hw.dio_pad_attr[8].keeper_en.qe = dio_pad_attr_8_qe; + + // F[schmitt_en_8]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_schmitt_en_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_schmitt_en_8_wd), + .d (hw2reg.dio_pad_attr[8].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[5]), + .q (reg2hw.dio_pad_attr[8].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_8_schmitt_en_8_qs) + ); + assign reg2hw.dio_pad_attr[8].schmitt_en.qe = dio_pad_attr_8_qe; + + // F[od_en_8]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_od_en_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_od_en_8_wd), + .d (hw2reg.dio_pad_attr[8].od_en.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[6]), + .q (reg2hw.dio_pad_attr[8].od_en.q), + .ds (), + .qs (dio_pad_attr_8_od_en_8_qs) + ); + assign reg2hw.dio_pad_attr[8].od_en.qe = dio_pad_attr_8_qe; + + // F[input_disable_8]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_input_disable_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_input_disable_8_wd), + .d (hw2reg.dio_pad_attr[8].input_disable.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[7]), + .q (reg2hw.dio_pad_attr[8].input_disable.q), + .ds (), + .qs (dio_pad_attr_8_input_disable_8_qs) + ); + assign reg2hw.dio_pad_attr[8].input_disable.qe = dio_pad_attr_8_qe; + + // F[slew_rate_8]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_8_slew_rate_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_slew_rate_8_wd), + .d (hw2reg.dio_pad_attr[8].slew_rate.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[8]), + .q (reg2hw.dio_pad_attr[8].slew_rate.q), + .ds (), + .qs (dio_pad_attr_8_slew_rate_8_qs) + ); + assign reg2hw.dio_pad_attr[8].slew_rate.qe = dio_pad_attr_8_qe; + + // F[drive_strength_8]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_8_drive_strength_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_drive_strength_8_wd), + .d (hw2reg.dio_pad_attr[8].drive_strength.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[9]), + .q (reg2hw.dio_pad_attr[8].drive_strength.q), + .ds (), + .qs (dio_pad_attr_8_drive_strength_8_qs) + ); + assign reg2hw.dio_pad_attr[8].drive_strength.qe = dio_pad_attr_8_qe; + + + // Subregister 9 of Multireg dio_pad_attr + // R[dio_pad_attr_9]: V(True) + logic dio_pad_attr_9_qe; + logic [9:0] dio_pad_attr_9_flds_we; + assign dio_pad_attr_9_qe = &dio_pad_attr_9_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_9_gated_we; + assign dio_pad_attr_9_gated_we = dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs; + // F[invert_9]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_invert_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_invert_9_wd), + .d (hw2reg.dio_pad_attr[9].invert.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[0]), + .q (reg2hw.dio_pad_attr[9].invert.q), + .ds (), + .qs (dio_pad_attr_9_invert_9_qs) + ); + assign reg2hw.dio_pad_attr[9].invert.qe = dio_pad_attr_9_qe; + + // F[virtual_od_en_9]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_virtual_od_en_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_virtual_od_en_9_wd), + .d (hw2reg.dio_pad_attr[9].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[1]), + .q (reg2hw.dio_pad_attr[9].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_9_virtual_od_en_9_qs) + ); + assign reg2hw.dio_pad_attr[9].virtual_od_en.qe = dio_pad_attr_9_qe; + + // F[pull_en_9]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_pull_en_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_pull_en_9_wd), + .d (hw2reg.dio_pad_attr[9].pull_en.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[2]), + .q (reg2hw.dio_pad_attr[9].pull_en.q), + .ds (), + .qs (dio_pad_attr_9_pull_en_9_qs) + ); + assign reg2hw.dio_pad_attr[9].pull_en.qe = dio_pad_attr_9_qe; + + // F[pull_select_9]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_pull_select_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_pull_select_9_wd), + .d (hw2reg.dio_pad_attr[9].pull_select.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[3]), + .q (reg2hw.dio_pad_attr[9].pull_select.q), + .ds (), + .qs (dio_pad_attr_9_pull_select_9_qs) + ); + assign reg2hw.dio_pad_attr[9].pull_select.qe = dio_pad_attr_9_qe; + + // F[keeper_en_9]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_keeper_en_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_keeper_en_9_wd), + .d (hw2reg.dio_pad_attr[9].keeper_en.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[4]), + .q (reg2hw.dio_pad_attr[9].keeper_en.q), + .ds (), + .qs (dio_pad_attr_9_keeper_en_9_qs) + ); + assign reg2hw.dio_pad_attr[9].keeper_en.qe = dio_pad_attr_9_qe; + + // F[schmitt_en_9]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_schmitt_en_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_schmitt_en_9_wd), + .d (hw2reg.dio_pad_attr[9].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[5]), + .q (reg2hw.dio_pad_attr[9].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_9_schmitt_en_9_qs) + ); + assign reg2hw.dio_pad_attr[9].schmitt_en.qe = dio_pad_attr_9_qe; + + // F[od_en_9]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_od_en_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_od_en_9_wd), + .d (hw2reg.dio_pad_attr[9].od_en.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[6]), + .q (reg2hw.dio_pad_attr[9].od_en.q), + .ds (), + .qs (dio_pad_attr_9_od_en_9_qs) + ); + assign reg2hw.dio_pad_attr[9].od_en.qe = dio_pad_attr_9_qe; + + // F[input_disable_9]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_input_disable_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_input_disable_9_wd), + .d (hw2reg.dio_pad_attr[9].input_disable.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[7]), + .q (reg2hw.dio_pad_attr[9].input_disable.q), + .ds (), + .qs (dio_pad_attr_9_input_disable_9_qs) + ); + assign reg2hw.dio_pad_attr[9].input_disable.qe = dio_pad_attr_9_qe; + + // F[slew_rate_9]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_9_slew_rate_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_slew_rate_9_wd), + .d (hw2reg.dio_pad_attr[9].slew_rate.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[8]), + .q (reg2hw.dio_pad_attr[9].slew_rate.q), + .ds (), + .qs (dio_pad_attr_9_slew_rate_9_qs) + ); + assign reg2hw.dio_pad_attr[9].slew_rate.qe = dio_pad_attr_9_qe; + + // F[drive_strength_9]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_9_drive_strength_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_drive_strength_9_wd), + .d (hw2reg.dio_pad_attr[9].drive_strength.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[9]), + .q (reg2hw.dio_pad_attr[9].drive_strength.q), + .ds (), + .qs (dio_pad_attr_9_drive_strength_9_qs) + ); + assign reg2hw.dio_pad_attr[9].drive_strength.qe = dio_pad_attr_9_qe; + + + // Subregister 10 of Multireg dio_pad_attr + // R[dio_pad_attr_10]: V(True) + logic dio_pad_attr_10_qe; + logic [9:0] dio_pad_attr_10_flds_we; + assign dio_pad_attr_10_qe = &dio_pad_attr_10_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_10_gated_we; + assign dio_pad_attr_10_gated_we = dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs; + // F[invert_10]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_invert_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_invert_10_wd), + .d (hw2reg.dio_pad_attr[10].invert.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[0]), + .q (reg2hw.dio_pad_attr[10].invert.q), + .ds (), + .qs (dio_pad_attr_10_invert_10_qs) + ); + assign reg2hw.dio_pad_attr[10].invert.qe = dio_pad_attr_10_qe; + + // F[virtual_od_en_10]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_virtual_od_en_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_virtual_od_en_10_wd), + .d (hw2reg.dio_pad_attr[10].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[1]), + .q (reg2hw.dio_pad_attr[10].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_10_virtual_od_en_10_qs) + ); + assign reg2hw.dio_pad_attr[10].virtual_od_en.qe = dio_pad_attr_10_qe; + + // F[pull_en_10]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_pull_en_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_pull_en_10_wd), + .d (hw2reg.dio_pad_attr[10].pull_en.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[2]), + .q (reg2hw.dio_pad_attr[10].pull_en.q), + .ds (), + .qs (dio_pad_attr_10_pull_en_10_qs) + ); + assign reg2hw.dio_pad_attr[10].pull_en.qe = dio_pad_attr_10_qe; + + // F[pull_select_10]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_pull_select_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_pull_select_10_wd), + .d (hw2reg.dio_pad_attr[10].pull_select.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[3]), + .q (reg2hw.dio_pad_attr[10].pull_select.q), + .ds (), + .qs (dio_pad_attr_10_pull_select_10_qs) + ); + assign reg2hw.dio_pad_attr[10].pull_select.qe = dio_pad_attr_10_qe; + + // F[keeper_en_10]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_keeper_en_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_keeper_en_10_wd), + .d (hw2reg.dio_pad_attr[10].keeper_en.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[4]), + .q (reg2hw.dio_pad_attr[10].keeper_en.q), + .ds (), + .qs (dio_pad_attr_10_keeper_en_10_qs) + ); + assign reg2hw.dio_pad_attr[10].keeper_en.qe = dio_pad_attr_10_qe; + + // F[schmitt_en_10]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_schmitt_en_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_schmitt_en_10_wd), + .d (hw2reg.dio_pad_attr[10].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[5]), + .q (reg2hw.dio_pad_attr[10].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_10_schmitt_en_10_qs) + ); + assign reg2hw.dio_pad_attr[10].schmitt_en.qe = dio_pad_attr_10_qe; + + // F[od_en_10]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_od_en_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_od_en_10_wd), + .d (hw2reg.dio_pad_attr[10].od_en.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[6]), + .q (reg2hw.dio_pad_attr[10].od_en.q), + .ds (), + .qs (dio_pad_attr_10_od_en_10_qs) + ); + assign reg2hw.dio_pad_attr[10].od_en.qe = dio_pad_attr_10_qe; + + // F[input_disable_10]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_input_disable_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_input_disable_10_wd), + .d (hw2reg.dio_pad_attr[10].input_disable.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[7]), + .q (reg2hw.dio_pad_attr[10].input_disable.q), + .ds (), + .qs (dio_pad_attr_10_input_disable_10_qs) + ); + assign reg2hw.dio_pad_attr[10].input_disable.qe = dio_pad_attr_10_qe; + + // F[slew_rate_10]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_10_slew_rate_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_slew_rate_10_wd), + .d (hw2reg.dio_pad_attr[10].slew_rate.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[8]), + .q (reg2hw.dio_pad_attr[10].slew_rate.q), + .ds (), + .qs (dio_pad_attr_10_slew_rate_10_qs) + ); + assign reg2hw.dio_pad_attr[10].slew_rate.qe = dio_pad_attr_10_qe; + + // F[drive_strength_10]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_10_drive_strength_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_drive_strength_10_wd), + .d (hw2reg.dio_pad_attr[10].drive_strength.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[9]), + .q (reg2hw.dio_pad_attr[10].drive_strength.q), + .ds (), + .qs (dio_pad_attr_10_drive_strength_10_qs) + ); + assign reg2hw.dio_pad_attr[10].drive_strength.qe = dio_pad_attr_10_qe; + + + // Subregister 11 of Multireg dio_pad_attr + // R[dio_pad_attr_11]: V(True) + logic dio_pad_attr_11_qe; + logic [9:0] dio_pad_attr_11_flds_we; + assign dio_pad_attr_11_qe = &dio_pad_attr_11_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_11_gated_we; + assign dio_pad_attr_11_gated_we = dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs; + // F[invert_11]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_invert_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_invert_11_wd), + .d (hw2reg.dio_pad_attr[11].invert.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[0]), + .q (reg2hw.dio_pad_attr[11].invert.q), + .ds (), + .qs (dio_pad_attr_11_invert_11_qs) + ); + assign reg2hw.dio_pad_attr[11].invert.qe = dio_pad_attr_11_qe; + + // F[virtual_od_en_11]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_virtual_od_en_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_virtual_od_en_11_wd), + .d (hw2reg.dio_pad_attr[11].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[1]), + .q (reg2hw.dio_pad_attr[11].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_11_virtual_od_en_11_qs) + ); + assign reg2hw.dio_pad_attr[11].virtual_od_en.qe = dio_pad_attr_11_qe; + + // F[pull_en_11]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_pull_en_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_pull_en_11_wd), + .d (hw2reg.dio_pad_attr[11].pull_en.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[2]), + .q (reg2hw.dio_pad_attr[11].pull_en.q), + .ds (), + .qs (dio_pad_attr_11_pull_en_11_qs) + ); + assign reg2hw.dio_pad_attr[11].pull_en.qe = dio_pad_attr_11_qe; + + // F[pull_select_11]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_pull_select_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_pull_select_11_wd), + .d (hw2reg.dio_pad_attr[11].pull_select.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[3]), + .q (reg2hw.dio_pad_attr[11].pull_select.q), + .ds (), + .qs (dio_pad_attr_11_pull_select_11_qs) + ); + assign reg2hw.dio_pad_attr[11].pull_select.qe = dio_pad_attr_11_qe; + + // F[keeper_en_11]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_keeper_en_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_keeper_en_11_wd), + .d (hw2reg.dio_pad_attr[11].keeper_en.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[4]), + .q (reg2hw.dio_pad_attr[11].keeper_en.q), + .ds (), + .qs (dio_pad_attr_11_keeper_en_11_qs) + ); + assign reg2hw.dio_pad_attr[11].keeper_en.qe = dio_pad_attr_11_qe; + + // F[schmitt_en_11]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_schmitt_en_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_schmitt_en_11_wd), + .d (hw2reg.dio_pad_attr[11].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[5]), + .q (reg2hw.dio_pad_attr[11].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_11_schmitt_en_11_qs) + ); + assign reg2hw.dio_pad_attr[11].schmitt_en.qe = dio_pad_attr_11_qe; + + // F[od_en_11]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_od_en_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_od_en_11_wd), + .d (hw2reg.dio_pad_attr[11].od_en.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[6]), + .q (reg2hw.dio_pad_attr[11].od_en.q), + .ds (), + .qs (dio_pad_attr_11_od_en_11_qs) + ); + assign reg2hw.dio_pad_attr[11].od_en.qe = dio_pad_attr_11_qe; + + // F[input_disable_11]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_input_disable_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_input_disable_11_wd), + .d (hw2reg.dio_pad_attr[11].input_disable.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[7]), + .q (reg2hw.dio_pad_attr[11].input_disable.q), + .ds (), + .qs (dio_pad_attr_11_input_disable_11_qs) + ); + assign reg2hw.dio_pad_attr[11].input_disable.qe = dio_pad_attr_11_qe; + + // F[slew_rate_11]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_11_slew_rate_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_slew_rate_11_wd), + .d (hw2reg.dio_pad_attr[11].slew_rate.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[8]), + .q (reg2hw.dio_pad_attr[11].slew_rate.q), + .ds (), + .qs (dio_pad_attr_11_slew_rate_11_qs) + ); + assign reg2hw.dio_pad_attr[11].slew_rate.qe = dio_pad_attr_11_qe; + + // F[drive_strength_11]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_11_drive_strength_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_drive_strength_11_wd), + .d (hw2reg.dio_pad_attr[11].drive_strength.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[9]), + .q (reg2hw.dio_pad_attr[11].drive_strength.q), + .ds (), + .qs (dio_pad_attr_11_drive_strength_11_qs) + ); + assign reg2hw.dio_pad_attr[11].drive_strength.qe = dio_pad_attr_11_qe; + + + // Subregister 12 of Multireg dio_pad_attr + // R[dio_pad_attr_12]: V(True) + logic dio_pad_attr_12_qe; + logic [9:0] dio_pad_attr_12_flds_we; + assign dio_pad_attr_12_qe = &dio_pad_attr_12_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_12_gated_we; + assign dio_pad_attr_12_gated_we = dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs; + // F[invert_12]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_invert_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_invert_12_wd), + .d (hw2reg.dio_pad_attr[12].invert.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[0]), + .q (reg2hw.dio_pad_attr[12].invert.q), + .ds (), + .qs (dio_pad_attr_12_invert_12_qs) + ); + assign reg2hw.dio_pad_attr[12].invert.qe = dio_pad_attr_12_qe; + + // F[virtual_od_en_12]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_virtual_od_en_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_virtual_od_en_12_wd), + .d (hw2reg.dio_pad_attr[12].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[1]), + .q (reg2hw.dio_pad_attr[12].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_12_virtual_od_en_12_qs) + ); + assign reg2hw.dio_pad_attr[12].virtual_od_en.qe = dio_pad_attr_12_qe; + + // F[pull_en_12]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_pull_en_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_pull_en_12_wd), + .d (hw2reg.dio_pad_attr[12].pull_en.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[2]), + .q (reg2hw.dio_pad_attr[12].pull_en.q), + .ds (), + .qs (dio_pad_attr_12_pull_en_12_qs) + ); + assign reg2hw.dio_pad_attr[12].pull_en.qe = dio_pad_attr_12_qe; + + // F[pull_select_12]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_pull_select_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_pull_select_12_wd), + .d (hw2reg.dio_pad_attr[12].pull_select.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[3]), + .q (reg2hw.dio_pad_attr[12].pull_select.q), + .ds (), + .qs (dio_pad_attr_12_pull_select_12_qs) + ); + assign reg2hw.dio_pad_attr[12].pull_select.qe = dio_pad_attr_12_qe; + + // F[keeper_en_12]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_keeper_en_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_keeper_en_12_wd), + .d (hw2reg.dio_pad_attr[12].keeper_en.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[4]), + .q (reg2hw.dio_pad_attr[12].keeper_en.q), + .ds (), + .qs (dio_pad_attr_12_keeper_en_12_qs) + ); + assign reg2hw.dio_pad_attr[12].keeper_en.qe = dio_pad_attr_12_qe; + + // F[schmitt_en_12]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_schmitt_en_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_schmitt_en_12_wd), + .d (hw2reg.dio_pad_attr[12].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[5]), + .q (reg2hw.dio_pad_attr[12].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_12_schmitt_en_12_qs) + ); + assign reg2hw.dio_pad_attr[12].schmitt_en.qe = dio_pad_attr_12_qe; + + // F[od_en_12]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_od_en_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_od_en_12_wd), + .d (hw2reg.dio_pad_attr[12].od_en.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[6]), + .q (reg2hw.dio_pad_attr[12].od_en.q), + .ds (), + .qs (dio_pad_attr_12_od_en_12_qs) + ); + assign reg2hw.dio_pad_attr[12].od_en.qe = dio_pad_attr_12_qe; + + // F[input_disable_12]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_input_disable_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_input_disable_12_wd), + .d (hw2reg.dio_pad_attr[12].input_disable.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[7]), + .q (reg2hw.dio_pad_attr[12].input_disable.q), + .ds (), + .qs (dio_pad_attr_12_input_disable_12_qs) + ); + assign reg2hw.dio_pad_attr[12].input_disable.qe = dio_pad_attr_12_qe; + + // F[slew_rate_12]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_12_slew_rate_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_slew_rate_12_wd), + .d (hw2reg.dio_pad_attr[12].slew_rate.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[8]), + .q (reg2hw.dio_pad_attr[12].slew_rate.q), + .ds (), + .qs (dio_pad_attr_12_slew_rate_12_qs) + ); + assign reg2hw.dio_pad_attr[12].slew_rate.qe = dio_pad_attr_12_qe; + + // F[drive_strength_12]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_12_drive_strength_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_drive_strength_12_wd), + .d (hw2reg.dio_pad_attr[12].drive_strength.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[9]), + .q (reg2hw.dio_pad_attr[12].drive_strength.q), + .ds (), + .qs (dio_pad_attr_12_drive_strength_12_qs) + ); + assign reg2hw.dio_pad_attr[12].drive_strength.qe = dio_pad_attr_12_qe; + + + // Subregister 13 of Multireg dio_pad_attr + // R[dio_pad_attr_13]: V(True) + logic dio_pad_attr_13_qe; + logic [9:0] dio_pad_attr_13_flds_we; + assign dio_pad_attr_13_qe = &dio_pad_attr_13_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_13_gated_we; + assign dio_pad_attr_13_gated_we = dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs; + // F[invert_13]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_invert_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_invert_13_wd), + .d (hw2reg.dio_pad_attr[13].invert.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[0]), + .q (reg2hw.dio_pad_attr[13].invert.q), + .ds (), + .qs (dio_pad_attr_13_invert_13_qs) + ); + assign reg2hw.dio_pad_attr[13].invert.qe = dio_pad_attr_13_qe; + + // F[virtual_od_en_13]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_virtual_od_en_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_virtual_od_en_13_wd), + .d (hw2reg.dio_pad_attr[13].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[1]), + .q (reg2hw.dio_pad_attr[13].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_13_virtual_od_en_13_qs) + ); + assign reg2hw.dio_pad_attr[13].virtual_od_en.qe = dio_pad_attr_13_qe; + + // F[pull_en_13]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_pull_en_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_pull_en_13_wd), + .d (hw2reg.dio_pad_attr[13].pull_en.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[2]), + .q (reg2hw.dio_pad_attr[13].pull_en.q), + .ds (), + .qs (dio_pad_attr_13_pull_en_13_qs) + ); + assign reg2hw.dio_pad_attr[13].pull_en.qe = dio_pad_attr_13_qe; + + // F[pull_select_13]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_pull_select_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_pull_select_13_wd), + .d (hw2reg.dio_pad_attr[13].pull_select.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[3]), + .q (reg2hw.dio_pad_attr[13].pull_select.q), + .ds (), + .qs (dio_pad_attr_13_pull_select_13_qs) + ); + assign reg2hw.dio_pad_attr[13].pull_select.qe = dio_pad_attr_13_qe; + + // F[keeper_en_13]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_keeper_en_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_keeper_en_13_wd), + .d (hw2reg.dio_pad_attr[13].keeper_en.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[4]), + .q (reg2hw.dio_pad_attr[13].keeper_en.q), + .ds (), + .qs (dio_pad_attr_13_keeper_en_13_qs) + ); + assign reg2hw.dio_pad_attr[13].keeper_en.qe = dio_pad_attr_13_qe; + + // F[schmitt_en_13]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_schmitt_en_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_schmitt_en_13_wd), + .d (hw2reg.dio_pad_attr[13].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[5]), + .q (reg2hw.dio_pad_attr[13].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_13_schmitt_en_13_qs) + ); + assign reg2hw.dio_pad_attr[13].schmitt_en.qe = dio_pad_attr_13_qe; + + // F[od_en_13]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_od_en_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_od_en_13_wd), + .d (hw2reg.dio_pad_attr[13].od_en.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[6]), + .q (reg2hw.dio_pad_attr[13].od_en.q), + .ds (), + .qs (dio_pad_attr_13_od_en_13_qs) + ); + assign reg2hw.dio_pad_attr[13].od_en.qe = dio_pad_attr_13_qe; + + // F[input_disable_13]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_input_disable_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_input_disable_13_wd), + .d (hw2reg.dio_pad_attr[13].input_disable.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[7]), + .q (reg2hw.dio_pad_attr[13].input_disable.q), + .ds (), + .qs (dio_pad_attr_13_input_disable_13_qs) + ); + assign reg2hw.dio_pad_attr[13].input_disable.qe = dio_pad_attr_13_qe; + + // F[slew_rate_13]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_13_slew_rate_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_slew_rate_13_wd), + .d (hw2reg.dio_pad_attr[13].slew_rate.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[8]), + .q (reg2hw.dio_pad_attr[13].slew_rate.q), + .ds (), + .qs (dio_pad_attr_13_slew_rate_13_qs) + ); + assign reg2hw.dio_pad_attr[13].slew_rate.qe = dio_pad_attr_13_qe; + + // F[drive_strength_13]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_13_drive_strength_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_drive_strength_13_wd), + .d (hw2reg.dio_pad_attr[13].drive_strength.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[9]), + .q (reg2hw.dio_pad_attr[13].drive_strength.q), + .ds (), + .qs (dio_pad_attr_13_drive_strength_13_qs) + ); + assign reg2hw.dio_pad_attr[13].drive_strength.qe = dio_pad_attr_13_qe; + + + // Subregister 14 of Multireg dio_pad_attr + // R[dio_pad_attr_14]: V(True) + logic dio_pad_attr_14_qe; + logic [9:0] dio_pad_attr_14_flds_we; + assign dio_pad_attr_14_qe = &dio_pad_attr_14_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_14_gated_we; + assign dio_pad_attr_14_gated_we = dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs; + // F[invert_14]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_invert_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_invert_14_wd), + .d (hw2reg.dio_pad_attr[14].invert.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[0]), + .q (reg2hw.dio_pad_attr[14].invert.q), + .ds (), + .qs (dio_pad_attr_14_invert_14_qs) + ); + assign reg2hw.dio_pad_attr[14].invert.qe = dio_pad_attr_14_qe; + + // F[virtual_od_en_14]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_virtual_od_en_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_virtual_od_en_14_wd), + .d (hw2reg.dio_pad_attr[14].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[1]), + .q (reg2hw.dio_pad_attr[14].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_14_virtual_od_en_14_qs) + ); + assign reg2hw.dio_pad_attr[14].virtual_od_en.qe = dio_pad_attr_14_qe; + + // F[pull_en_14]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_pull_en_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_pull_en_14_wd), + .d (hw2reg.dio_pad_attr[14].pull_en.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[2]), + .q (reg2hw.dio_pad_attr[14].pull_en.q), + .ds (), + .qs (dio_pad_attr_14_pull_en_14_qs) + ); + assign reg2hw.dio_pad_attr[14].pull_en.qe = dio_pad_attr_14_qe; + + // F[pull_select_14]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_pull_select_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_pull_select_14_wd), + .d (hw2reg.dio_pad_attr[14].pull_select.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[3]), + .q (reg2hw.dio_pad_attr[14].pull_select.q), + .ds (), + .qs (dio_pad_attr_14_pull_select_14_qs) + ); + assign reg2hw.dio_pad_attr[14].pull_select.qe = dio_pad_attr_14_qe; + + // F[keeper_en_14]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_keeper_en_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_keeper_en_14_wd), + .d (hw2reg.dio_pad_attr[14].keeper_en.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[4]), + .q (reg2hw.dio_pad_attr[14].keeper_en.q), + .ds (), + .qs (dio_pad_attr_14_keeper_en_14_qs) + ); + assign reg2hw.dio_pad_attr[14].keeper_en.qe = dio_pad_attr_14_qe; + + // F[schmitt_en_14]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_schmitt_en_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_schmitt_en_14_wd), + .d (hw2reg.dio_pad_attr[14].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[5]), + .q (reg2hw.dio_pad_attr[14].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_14_schmitt_en_14_qs) + ); + assign reg2hw.dio_pad_attr[14].schmitt_en.qe = dio_pad_attr_14_qe; + + // F[od_en_14]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_od_en_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_od_en_14_wd), + .d (hw2reg.dio_pad_attr[14].od_en.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[6]), + .q (reg2hw.dio_pad_attr[14].od_en.q), + .ds (), + .qs (dio_pad_attr_14_od_en_14_qs) + ); + assign reg2hw.dio_pad_attr[14].od_en.qe = dio_pad_attr_14_qe; + + // F[input_disable_14]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_input_disable_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_input_disable_14_wd), + .d (hw2reg.dio_pad_attr[14].input_disable.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[7]), + .q (reg2hw.dio_pad_attr[14].input_disable.q), + .ds (), + .qs (dio_pad_attr_14_input_disable_14_qs) + ); + assign reg2hw.dio_pad_attr[14].input_disable.qe = dio_pad_attr_14_qe; + + // F[slew_rate_14]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_14_slew_rate_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_slew_rate_14_wd), + .d (hw2reg.dio_pad_attr[14].slew_rate.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[8]), + .q (reg2hw.dio_pad_attr[14].slew_rate.q), + .ds (), + .qs (dio_pad_attr_14_slew_rate_14_qs) + ); + assign reg2hw.dio_pad_attr[14].slew_rate.qe = dio_pad_attr_14_qe; + + // F[drive_strength_14]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_14_drive_strength_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_drive_strength_14_wd), + .d (hw2reg.dio_pad_attr[14].drive_strength.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[9]), + .q (reg2hw.dio_pad_attr[14].drive_strength.q), + .ds (), + .qs (dio_pad_attr_14_drive_strength_14_qs) + ); + assign reg2hw.dio_pad_attr[14].drive_strength.qe = dio_pad_attr_14_qe; + + + // Subregister 15 of Multireg dio_pad_attr + // R[dio_pad_attr_15]: V(True) + logic dio_pad_attr_15_qe; + logic [9:0] dio_pad_attr_15_flds_we; + assign dio_pad_attr_15_qe = &dio_pad_attr_15_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_15_gated_we; + assign dio_pad_attr_15_gated_we = dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs; + // F[invert_15]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_invert_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_invert_15_wd), + .d (hw2reg.dio_pad_attr[15].invert.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[0]), + .q (reg2hw.dio_pad_attr[15].invert.q), + .ds (), + .qs (dio_pad_attr_15_invert_15_qs) + ); + assign reg2hw.dio_pad_attr[15].invert.qe = dio_pad_attr_15_qe; + + // F[virtual_od_en_15]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_virtual_od_en_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_virtual_od_en_15_wd), + .d (hw2reg.dio_pad_attr[15].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[1]), + .q (reg2hw.dio_pad_attr[15].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_15_virtual_od_en_15_qs) + ); + assign reg2hw.dio_pad_attr[15].virtual_od_en.qe = dio_pad_attr_15_qe; + + // F[pull_en_15]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_pull_en_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_pull_en_15_wd), + .d (hw2reg.dio_pad_attr[15].pull_en.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[2]), + .q (reg2hw.dio_pad_attr[15].pull_en.q), + .ds (), + .qs (dio_pad_attr_15_pull_en_15_qs) + ); + assign reg2hw.dio_pad_attr[15].pull_en.qe = dio_pad_attr_15_qe; + + // F[pull_select_15]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_pull_select_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_pull_select_15_wd), + .d (hw2reg.dio_pad_attr[15].pull_select.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[3]), + .q (reg2hw.dio_pad_attr[15].pull_select.q), + .ds (), + .qs (dio_pad_attr_15_pull_select_15_qs) + ); + assign reg2hw.dio_pad_attr[15].pull_select.qe = dio_pad_attr_15_qe; + + // F[keeper_en_15]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_keeper_en_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_keeper_en_15_wd), + .d (hw2reg.dio_pad_attr[15].keeper_en.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[4]), + .q (reg2hw.dio_pad_attr[15].keeper_en.q), + .ds (), + .qs (dio_pad_attr_15_keeper_en_15_qs) + ); + assign reg2hw.dio_pad_attr[15].keeper_en.qe = dio_pad_attr_15_qe; + + // F[schmitt_en_15]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_schmitt_en_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_schmitt_en_15_wd), + .d (hw2reg.dio_pad_attr[15].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[5]), + .q (reg2hw.dio_pad_attr[15].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_15_schmitt_en_15_qs) + ); + assign reg2hw.dio_pad_attr[15].schmitt_en.qe = dio_pad_attr_15_qe; + + // F[od_en_15]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_od_en_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_od_en_15_wd), + .d (hw2reg.dio_pad_attr[15].od_en.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[6]), + .q (reg2hw.dio_pad_attr[15].od_en.q), + .ds (), + .qs (dio_pad_attr_15_od_en_15_qs) + ); + assign reg2hw.dio_pad_attr[15].od_en.qe = dio_pad_attr_15_qe; + + // F[input_disable_15]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_input_disable_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_input_disable_15_wd), + .d (hw2reg.dio_pad_attr[15].input_disable.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[7]), + .q (reg2hw.dio_pad_attr[15].input_disable.q), + .ds (), + .qs (dio_pad_attr_15_input_disable_15_qs) + ); + assign reg2hw.dio_pad_attr[15].input_disable.qe = dio_pad_attr_15_qe; + + // F[slew_rate_15]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_15_slew_rate_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_slew_rate_15_wd), + .d (hw2reg.dio_pad_attr[15].slew_rate.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[8]), + .q (reg2hw.dio_pad_attr[15].slew_rate.q), + .ds (), + .qs (dio_pad_attr_15_slew_rate_15_qs) + ); + assign reg2hw.dio_pad_attr[15].slew_rate.qe = dio_pad_attr_15_qe; + + // F[drive_strength_15]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_15_drive_strength_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_drive_strength_15_wd), + .d (hw2reg.dio_pad_attr[15].drive_strength.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[9]), + .q (reg2hw.dio_pad_attr[15].drive_strength.q), + .ds (), + .qs (dio_pad_attr_15_drive_strength_15_qs) + ); + assign reg2hw.dio_pad_attr[15].drive_strength.qe = dio_pad_attr_15_qe; + + + // Subregister 16 of Multireg dio_pad_attr + // R[dio_pad_attr_16]: V(True) + logic dio_pad_attr_16_qe; + logic [9:0] dio_pad_attr_16_flds_we; + assign dio_pad_attr_16_qe = &dio_pad_attr_16_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_16_gated_we; + assign dio_pad_attr_16_gated_we = dio_pad_attr_16_we & dio_pad_attr_regwen_16_qs; + // F[invert_16]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_invert_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_invert_16_wd), + .d (hw2reg.dio_pad_attr[16].invert.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[0]), + .q (reg2hw.dio_pad_attr[16].invert.q), + .ds (), + .qs (dio_pad_attr_16_invert_16_qs) + ); + assign reg2hw.dio_pad_attr[16].invert.qe = dio_pad_attr_16_qe; + + // F[virtual_od_en_16]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_virtual_od_en_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_virtual_od_en_16_wd), + .d (hw2reg.dio_pad_attr[16].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[1]), + .q (reg2hw.dio_pad_attr[16].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_16_virtual_od_en_16_qs) + ); + assign reg2hw.dio_pad_attr[16].virtual_od_en.qe = dio_pad_attr_16_qe; + + // F[pull_en_16]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_pull_en_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_pull_en_16_wd), + .d (hw2reg.dio_pad_attr[16].pull_en.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[2]), + .q (reg2hw.dio_pad_attr[16].pull_en.q), + .ds (), + .qs (dio_pad_attr_16_pull_en_16_qs) + ); + assign reg2hw.dio_pad_attr[16].pull_en.qe = dio_pad_attr_16_qe; + + // F[pull_select_16]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_pull_select_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_pull_select_16_wd), + .d (hw2reg.dio_pad_attr[16].pull_select.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[3]), + .q (reg2hw.dio_pad_attr[16].pull_select.q), + .ds (), + .qs (dio_pad_attr_16_pull_select_16_qs) + ); + assign reg2hw.dio_pad_attr[16].pull_select.qe = dio_pad_attr_16_qe; + + // F[keeper_en_16]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_keeper_en_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_keeper_en_16_wd), + .d (hw2reg.dio_pad_attr[16].keeper_en.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[4]), + .q (reg2hw.dio_pad_attr[16].keeper_en.q), + .ds (), + .qs (dio_pad_attr_16_keeper_en_16_qs) + ); + assign reg2hw.dio_pad_attr[16].keeper_en.qe = dio_pad_attr_16_qe; + + // F[schmitt_en_16]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_schmitt_en_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_schmitt_en_16_wd), + .d (hw2reg.dio_pad_attr[16].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[5]), + .q (reg2hw.dio_pad_attr[16].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_16_schmitt_en_16_qs) + ); + assign reg2hw.dio_pad_attr[16].schmitt_en.qe = dio_pad_attr_16_qe; + + // F[od_en_16]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_od_en_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_od_en_16_wd), + .d (hw2reg.dio_pad_attr[16].od_en.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[6]), + .q (reg2hw.dio_pad_attr[16].od_en.q), + .ds (), + .qs (dio_pad_attr_16_od_en_16_qs) + ); + assign reg2hw.dio_pad_attr[16].od_en.qe = dio_pad_attr_16_qe; + + // F[input_disable_16]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_input_disable_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_input_disable_16_wd), + .d (hw2reg.dio_pad_attr[16].input_disable.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[7]), + .q (reg2hw.dio_pad_attr[16].input_disable.q), + .ds (), + .qs (dio_pad_attr_16_input_disable_16_qs) + ); + assign reg2hw.dio_pad_attr[16].input_disable.qe = dio_pad_attr_16_qe; + + // F[slew_rate_16]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_16_slew_rate_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_slew_rate_16_wd), + .d (hw2reg.dio_pad_attr[16].slew_rate.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[8]), + .q (reg2hw.dio_pad_attr[16].slew_rate.q), + .ds (), + .qs (dio_pad_attr_16_slew_rate_16_qs) + ); + assign reg2hw.dio_pad_attr[16].slew_rate.qe = dio_pad_attr_16_qe; + + // F[drive_strength_16]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_16_drive_strength_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_drive_strength_16_wd), + .d (hw2reg.dio_pad_attr[16].drive_strength.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[9]), + .q (reg2hw.dio_pad_attr[16].drive_strength.q), + .ds (), + .qs (dio_pad_attr_16_drive_strength_16_qs) + ); + assign reg2hw.dio_pad_attr[16].drive_strength.qe = dio_pad_attr_16_qe; + + + // Subregister 17 of Multireg dio_pad_attr + // R[dio_pad_attr_17]: V(True) + logic dio_pad_attr_17_qe; + logic [9:0] dio_pad_attr_17_flds_we; + assign dio_pad_attr_17_qe = &dio_pad_attr_17_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_17_gated_we; + assign dio_pad_attr_17_gated_we = dio_pad_attr_17_we & dio_pad_attr_regwen_17_qs; + // F[invert_17]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_invert_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_invert_17_wd), + .d (hw2reg.dio_pad_attr[17].invert.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[0]), + .q (reg2hw.dio_pad_attr[17].invert.q), + .ds (), + .qs (dio_pad_attr_17_invert_17_qs) + ); + assign reg2hw.dio_pad_attr[17].invert.qe = dio_pad_attr_17_qe; + + // F[virtual_od_en_17]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_virtual_od_en_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_virtual_od_en_17_wd), + .d (hw2reg.dio_pad_attr[17].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[1]), + .q (reg2hw.dio_pad_attr[17].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_17_virtual_od_en_17_qs) + ); + assign reg2hw.dio_pad_attr[17].virtual_od_en.qe = dio_pad_attr_17_qe; + + // F[pull_en_17]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_pull_en_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_pull_en_17_wd), + .d (hw2reg.dio_pad_attr[17].pull_en.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[2]), + .q (reg2hw.dio_pad_attr[17].pull_en.q), + .ds (), + .qs (dio_pad_attr_17_pull_en_17_qs) + ); + assign reg2hw.dio_pad_attr[17].pull_en.qe = dio_pad_attr_17_qe; + + // F[pull_select_17]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_pull_select_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_pull_select_17_wd), + .d (hw2reg.dio_pad_attr[17].pull_select.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[3]), + .q (reg2hw.dio_pad_attr[17].pull_select.q), + .ds (), + .qs (dio_pad_attr_17_pull_select_17_qs) + ); + assign reg2hw.dio_pad_attr[17].pull_select.qe = dio_pad_attr_17_qe; + + // F[keeper_en_17]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_keeper_en_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_keeper_en_17_wd), + .d (hw2reg.dio_pad_attr[17].keeper_en.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[4]), + .q (reg2hw.dio_pad_attr[17].keeper_en.q), + .ds (), + .qs (dio_pad_attr_17_keeper_en_17_qs) + ); + assign reg2hw.dio_pad_attr[17].keeper_en.qe = dio_pad_attr_17_qe; + + // F[schmitt_en_17]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_schmitt_en_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_schmitt_en_17_wd), + .d (hw2reg.dio_pad_attr[17].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[5]), + .q (reg2hw.dio_pad_attr[17].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_17_schmitt_en_17_qs) + ); + assign reg2hw.dio_pad_attr[17].schmitt_en.qe = dio_pad_attr_17_qe; + + // F[od_en_17]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_od_en_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_od_en_17_wd), + .d (hw2reg.dio_pad_attr[17].od_en.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[6]), + .q (reg2hw.dio_pad_attr[17].od_en.q), + .ds (), + .qs (dio_pad_attr_17_od_en_17_qs) + ); + assign reg2hw.dio_pad_attr[17].od_en.qe = dio_pad_attr_17_qe; + + // F[input_disable_17]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_input_disable_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_input_disable_17_wd), + .d (hw2reg.dio_pad_attr[17].input_disable.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[7]), + .q (reg2hw.dio_pad_attr[17].input_disable.q), + .ds (), + .qs (dio_pad_attr_17_input_disable_17_qs) + ); + assign reg2hw.dio_pad_attr[17].input_disable.qe = dio_pad_attr_17_qe; + + // F[slew_rate_17]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_17_slew_rate_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_slew_rate_17_wd), + .d (hw2reg.dio_pad_attr[17].slew_rate.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[8]), + .q (reg2hw.dio_pad_attr[17].slew_rate.q), + .ds (), + .qs (dio_pad_attr_17_slew_rate_17_qs) + ); + assign reg2hw.dio_pad_attr[17].slew_rate.qe = dio_pad_attr_17_qe; + + // F[drive_strength_17]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_17_drive_strength_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_drive_strength_17_wd), + .d (hw2reg.dio_pad_attr[17].drive_strength.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[9]), + .q (reg2hw.dio_pad_attr[17].drive_strength.q), + .ds (), + .qs (dio_pad_attr_17_drive_strength_17_qs) + ); + assign reg2hw.dio_pad_attr[17].drive_strength.qe = dio_pad_attr_17_qe; + + + // Subregister 18 of Multireg dio_pad_attr + // R[dio_pad_attr_18]: V(True) + logic dio_pad_attr_18_qe; + logic [9:0] dio_pad_attr_18_flds_we; + assign dio_pad_attr_18_qe = &dio_pad_attr_18_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_18_gated_we; + assign dio_pad_attr_18_gated_we = dio_pad_attr_18_we & dio_pad_attr_regwen_18_qs; + // F[invert_18]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_invert_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_invert_18_wd), + .d (hw2reg.dio_pad_attr[18].invert.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[0]), + .q (reg2hw.dio_pad_attr[18].invert.q), + .ds (), + .qs (dio_pad_attr_18_invert_18_qs) + ); + assign reg2hw.dio_pad_attr[18].invert.qe = dio_pad_attr_18_qe; + + // F[virtual_od_en_18]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_virtual_od_en_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_virtual_od_en_18_wd), + .d (hw2reg.dio_pad_attr[18].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[1]), + .q (reg2hw.dio_pad_attr[18].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_18_virtual_od_en_18_qs) + ); + assign reg2hw.dio_pad_attr[18].virtual_od_en.qe = dio_pad_attr_18_qe; + + // F[pull_en_18]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_pull_en_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_pull_en_18_wd), + .d (hw2reg.dio_pad_attr[18].pull_en.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[2]), + .q (reg2hw.dio_pad_attr[18].pull_en.q), + .ds (), + .qs (dio_pad_attr_18_pull_en_18_qs) + ); + assign reg2hw.dio_pad_attr[18].pull_en.qe = dio_pad_attr_18_qe; + + // F[pull_select_18]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_pull_select_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_pull_select_18_wd), + .d (hw2reg.dio_pad_attr[18].pull_select.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[3]), + .q (reg2hw.dio_pad_attr[18].pull_select.q), + .ds (), + .qs (dio_pad_attr_18_pull_select_18_qs) + ); + assign reg2hw.dio_pad_attr[18].pull_select.qe = dio_pad_attr_18_qe; + + // F[keeper_en_18]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_keeper_en_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_keeper_en_18_wd), + .d (hw2reg.dio_pad_attr[18].keeper_en.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[4]), + .q (reg2hw.dio_pad_attr[18].keeper_en.q), + .ds (), + .qs (dio_pad_attr_18_keeper_en_18_qs) + ); + assign reg2hw.dio_pad_attr[18].keeper_en.qe = dio_pad_attr_18_qe; + + // F[schmitt_en_18]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_schmitt_en_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_schmitt_en_18_wd), + .d (hw2reg.dio_pad_attr[18].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[5]), + .q (reg2hw.dio_pad_attr[18].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_18_schmitt_en_18_qs) + ); + assign reg2hw.dio_pad_attr[18].schmitt_en.qe = dio_pad_attr_18_qe; + + // F[od_en_18]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_od_en_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_od_en_18_wd), + .d (hw2reg.dio_pad_attr[18].od_en.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[6]), + .q (reg2hw.dio_pad_attr[18].od_en.q), + .ds (), + .qs (dio_pad_attr_18_od_en_18_qs) + ); + assign reg2hw.dio_pad_attr[18].od_en.qe = dio_pad_attr_18_qe; + + // F[input_disable_18]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_input_disable_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_input_disable_18_wd), + .d (hw2reg.dio_pad_attr[18].input_disable.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[7]), + .q (reg2hw.dio_pad_attr[18].input_disable.q), + .ds (), + .qs (dio_pad_attr_18_input_disable_18_qs) + ); + assign reg2hw.dio_pad_attr[18].input_disable.qe = dio_pad_attr_18_qe; + + // F[slew_rate_18]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_18_slew_rate_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_slew_rate_18_wd), + .d (hw2reg.dio_pad_attr[18].slew_rate.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[8]), + .q (reg2hw.dio_pad_attr[18].slew_rate.q), + .ds (), + .qs (dio_pad_attr_18_slew_rate_18_qs) + ); + assign reg2hw.dio_pad_attr[18].slew_rate.qe = dio_pad_attr_18_qe; + + // F[drive_strength_18]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_18_drive_strength_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_drive_strength_18_wd), + .d (hw2reg.dio_pad_attr[18].drive_strength.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[9]), + .q (reg2hw.dio_pad_attr[18].drive_strength.q), + .ds (), + .qs (dio_pad_attr_18_drive_strength_18_qs) + ); + assign reg2hw.dio_pad_attr[18].drive_strength.qe = dio_pad_attr_18_qe; + + + // Subregister 19 of Multireg dio_pad_attr + // R[dio_pad_attr_19]: V(True) + logic dio_pad_attr_19_qe; + logic [9:0] dio_pad_attr_19_flds_we; + assign dio_pad_attr_19_qe = &dio_pad_attr_19_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_19_gated_we; + assign dio_pad_attr_19_gated_we = dio_pad_attr_19_we & dio_pad_attr_regwen_19_qs; + // F[invert_19]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_invert_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_invert_19_wd), + .d (hw2reg.dio_pad_attr[19].invert.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[0]), + .q (reg2hw.dio_pad_attr[19].invert.q), + .ds (), + .qs (dio_pad_attr_19_invert_19_qs) + ); + assign reg2hw.dio_pad_attr[19].invert.qe = dio_pad_attr_19_qe; + + // F[virtual_od_en_19]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_virtual_od_en_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_virtual_od_en_19_wd), + .d (hw2reg.dio_pad_attr[19].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[1]), + .q (reg2hw.dio_pad_attr[19].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_19_virtual_od_en_19_qs) + ); + assign reg2hw.dio_pad_attr[19].virtual_od_en.qe = dio_pad_attr_19_qe; + + // F[pull_en_19]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_pull_en_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_pull_en_19_wd), + .d (hw2reg.dio_pad_attr[19].pull_en.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[2]), + .q (reg2hw.dio_pad_attr[19].pull_en.q), + .ds (), + .qs (dio_pad_attr_19_pull_en_19_qs) + ); + assign reg2hw.dio_pad_attr[19].pull_en.qe = dio_pad_attr_19_qe; + + // F[pull_select_19]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_pull_select_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_pull_select_19_wd), + .d (hw2reg.dio_pad_attr[19].pull_select.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[3]), + .q (reg2hw.dio_pad_attr[19].pull_select.q), + .ds (), + .qs (dio_pad_attr_19_pull_select_19_qs) + ); + assign reg2hw.dio_pad_attr[19].pull_select.qe = dio_pad_attr_19_qe; + + // F[keeper_en_19]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_keeper_en_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_keeper_en_19_wd), + .d (hw2reg.dio_pad_attr[19].keeper_en.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[4]), + .q (reg2hw.dio_pad_attr[19].keeper_en.q), + .ds (), + .qs (dio_pad_attr_19_keeper_en_19_qs) + ); + assign reg2hw.dio_pad_attr[19].keeper_en.qe = dio_pad_attr_19_qe; + + // F[schmitt_en_19]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_schmitt_en_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_schmitt_en_19_wd), + .d (hw2reg.dio_pad_attr[19].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[5]), + .q (reg2hw.dio_pad_attr[19].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_19_schmitt_en_19_qs) + ); + assign reg2hw.dio_pad_attr[19].schmitt_en.qe = dio_pad_attr_19_qe; + + // F[od_en_19]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_od_en_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_od_en_19_wd), + .d (hw2reg.dio_pad_attr[19].od_en.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[6]), + .q (reg2hw.dio_pad_attr[19].od_en.q), + .ds (), + .qs (dio_pad_attr_19_od_en_19_qs) + ); + assign reg2hw.dio_pad_attr[19].od_en.qe = dio_pad_attr_19_qe; + + // F[input_disable_19]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_input_disable_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_input_disable_19_wd), + .d (hw2reg.dio_pad_attr[19].input_disable.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[7]), + .q (reg2hw.dio_pad_attr[19].input_disable.q), + .ds (), + .qs (dio_pad_attr_19_input_disable_19_qs) + ); + assign reg2hw.dio_pad_attr[19].input_disable.qe = dio_pad_attr_19_qe; + + // F[slew_rate_19]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_19_slew_rate_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_slew_rate_19_wd), + .d (hw2reg.dio_pad_attr[19].slew_rate.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[8]), + .q (reg2hw.dio_pad_attr[19].slew_rate.q), + .ds (), + .qs (dio_pad_attr_19_slew_rate_19_qs) + ); + assign reg2hw.dio_pad_attr[19].slew_rate.qe = dio_pad_attr_19_qe; + + // F[drive_strength_19]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_19_drive_strength_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_drive_strength_19_wd), + .d (hw2reg.dio_pad_attr[19].drive_strength.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[9]), + .q (reg2hw.dio_pad_attr[19].drive_strength.q), + .ds (), + .qs (dio_pad_attr_19_drive_strength_19_qs) + ); + assign reg2hw.dio_pad_attr[19].drive_strength.qe = dio_pad_attr_19_qe; + + + // Subregister 20 of Multireg dio_pad_attr + // R[dio_pad_attr_20]: V(True) + logic dio_pad_attr_20_qe; + logic [9:0] dio_pad_attr_20_flds_we; + assign dio_pad_attr_20_qe = &dio_pad_attr_20_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_20_gated_we; + assign dio_pad_attr_20_gated_we = dio_pad_attr_20_we & dio_pad_attr_regwen_20_qs; + // F[invert_20]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_invert_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_invert_20_wd), + .d (hw2reg.dio_pad_attr[20].invert.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[0]), + .q (reg2hw.dio_pad_attr[20].invert.q), + .ds (), + .qs (dio_pad_attr_20_invert_20_qs) + ); + assign reg2hw.dio_pad_attr[20].invert.qe = dio_pad_attr_20_qe; + + // F[virtual_od_en_20]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_virtual_od_en_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_virtual_od_en_20_wd), + .d (hw2reg.dio_pad_attr[20].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[1]), + .q (reg2hw.dio_pad_attr[20].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_20_virtual_od_en_20_qs) + ); + assign reg2hw.dio_pad_attr[20].virtual_od_en.qe = dio_pad_attr_20_qe; + + // F[pull_en_20]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_pull_en_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_pull_en_20_wd), + .d (hw2reg.dio_pad_attr[20].pull_en.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[2]), + .q (reg2hw.dio_pad_attr[20].pull_en.q), + .ds (), + .qs (dio_pad_attr_20_pull_en_20_qs) + ); + assign reg2hw.dio_pad_attr[20].pull_en.qe = dio_pad_attr_20_qe; + + // F[pull_select_20]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_pull_select_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_pull_select_20_wd), + .d (hw2reg.dio_pad_attr[20].pull_select.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[3]), + .q (reg2hw.dio_pad_attr[20].pull_select.q), + .ds (), + .qs (dio_pad_attr_20_pull_select_20_qs) + ); + assign reg2hw.dio_pad_attr[20].pull_select.qe = dio_pad_attr_20_qe; + + // F[keeper_en_20]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_keeper_en_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_keeper_en_20_wd), + .d (hw2reg.dio_pad_attr[20].keeper_en.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[4]), + .q (reg2hw.dio_pad_attr[20].keeper_en.q), + .ds (), + .qs (dio_pad_attr_20_keeper_en_20_qs) + ); + assign reg2hw.dio_pad_attr[20].keeper_en.qe = dio_pad_attr_20_qe; + + // F[schmitt_en_20]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_schmitt_en_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_schmitt_en_20_wd), + .d (hw2reg.dio_pad_attr[20].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[5]), + .q (reg2hw.dio_pad_attr[20].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_20_schmitt_en_20_qs) + ); + assign reg2hw.dio_pad_attr[20].schmitt_en.qe = dio_pad_attr_20_qe; + + // F[od_en_20]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_od_en_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_od_en_20_wd), + .d (hw2reg.dio_pad_attr[20].od_en.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[6]), + .q (reg2hw.dio_pad_attr[20].od_en.q), + .ds (), + .qs (dio_pad_attr_20_od_en_20_qs) + ); + assign reg2hw.dio_pad_attr[20].od_en.qe = dio_pad_attr_20_qe; + + // F[input_disable_20]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_input_disable_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_input_disable_20_wd), + .d (hw2reg.dio_pad_attr[20].input_disable.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[7]), + .q (reg2hw.dio_pad_attr[20].input_disable.q), + .ds (), + .qs (dio_pad_attr_20_input_disable_20_qs) + ); + assign reg2hw.dio_pad_attr[20].input_disable.qe = dio_pad_attr_20_qe; + + // F[slew_rate_20]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_20_slew_rate_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_slew_rate_20_wd), + .d (hw2reg.dio_pad_attr[20].slew_rate.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[8]), + .q (reg2hw.dio_pad_attr[20].slew_rate.q), + .ds (), + .qs (dio_pad_attr_20_slew_rate_20_qs) + ); + assign reg2hw.dio_pad_attr[20].slew_rate.qe = dio_pad_attr_20_qe; + + // F[drive_strength_20]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_20_drive_strength_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_drive_strength_20_wd), + .d (hw2reg.dio_pad_attr[20].drive_strength.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[9]), + .q (reg2hw.dio_pad_attr[20].drive_strength.q), + .ds (), + .qs (dio_pad_attr_20_drive_strength_20_qs) + ); + assign reg2hw.dio_pad_attr[20].drive_strength.qe = dio_pad_attr_20_qe; + + + // Subregister 21 of Multireg dio_pad_attr + // R[dio_pad_attr_21]: V(True) + logic dio_pad_attr_21_qe; + logic [9:0] dio_pad_attr_21_flds_we; + assign dio_pad_attr_21_qe = &dio_pad_attr_21_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_21_gated_we; + assign dio_pad_attr_21_gated_we = dio_pad_attr_21_we & dio_pad_attr_regwen_21_qs; + // F[invert_21]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_invert_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_invert_21_wd), + .d (hw2reg.dio_pad_attr[21].invert.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[0]), + .q (reg2hw.dio_pad_attr[21].invert.q), + .ds (), + .qs (dio_pad_attr_21_invert_21_qs) + ); + assign reg2hw.dio_pad_attr[21].invert.qe = dio_pad_attr_21_qe; + + // F[virtual_od_en_21]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_virtual_od_en_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_virtual_od_en_21_wd), + .d (hw2reg.dio_pad_attr[21].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[1]), + .q (reg2hw.dio_pad_attr[21].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_21_virtual_od_en_21_qs) + ); + assign reg2hw.dio_pad_attr[21].virtual_od_en.qe = dio_pad_attr_21_qe; + + // F[pull_en_21]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_pull_en_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_pull_en_21_wd), + .d (hw2reg.dio_pad_attr[21].pull_en.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[2]), + .q (reg2hw.dio_pad_attr[21].pull_en.q), + .ds (), + .qs (dio_pad_attr_21_pull_en_21_qs) + ); + assign reg2hw.dio_pad_attr[21].pull_en.qe = dio_pad_attr_21_qe; + + // F[pull_select_21]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_pull_select_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_pull_select_21_wd), + .d (hw2reg.dio_pad_attr[21].pull_select.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[3]), + .q (reg2hw.dio_pad_attr[21].pull_select.q), + .ds (), + .qs (dio_pad_attr_21_pull_select_21_qs) + ); + assign reg2hw.dio_pad_attr[21].pull_select.qe = dio_pad_attr_21_qe; + + // F[keeper_en_21]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_keeper_en_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_keeper_en_21_wd), + .d (hw2reg.dio_pad_attr[21].keeper_en.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[4]), + .q (reg2hw.dio_pad_attr[21].keeper_en.q), + .ds (), + .qs (dio_pad_attr_21_keeper_en_21_qs) + ); + assign reg2hw.dio_pad_attr[21].keeper_en.qe = dio_pad_attr_21_qe; + + // F[schmitt_en_21]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_schmitt_en_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_schmitt_en_21_wd), + .d (hw2reg.dio_pad_attr[21].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[5]), + .q (reg2hw.dio_pad_attr[21].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_21_schmitt_en_21_qs) + ); + assign reg2hw.dio_pad_attr[21].schmitt_en.qe = dio_pad_attr_21_qe; + + // F[od_en_21]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_od_en_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_od_en_21_wd), + .d (hw2reg.dio_pad_attr[21].od_en.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[6]), + .q (reg2hw.dio_pad_attr[21].od_en.q), + .ds (), + .qs (dio_pad_attr_21_od_en_21_qs) + ); + assign reg2hw.dio_pad_attr[21].od_en.qe = dio_pad_attr_21_qe; + + // F[input_disable_21]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_input_disable_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_input_disable_21_wd), + .d (hw2reg.dio_pad_attr[21].input_disable.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[7]), + .q (reg2hw.dio_pad_attr[21].input_disable.q), + .ds (), + .qs (dio_pad_attr_21_input_disable_21_qs) + ); + assign reg2hw.dio_pad_attr[21].input_disable.qe = dio_pad_attr_21_qe; + + // F[slew_rate_21]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_21_slew_rate_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_slew_rate_21_wd), + .d (hw2reg.dio_pad_attr[21].slew_rate.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[8]), + .q (reg2hw.dio_pad_attr[21].slew_rate.q), + .ds (), + .qs (dio_pad_attr_21_slew_rate_21_qs) + ); + assign reg2hw.dio_pad_attr[21].slew_rate.qe = dio_pad_attr_21_qe; + + // F[drive_strength_21]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_21_drive_strength_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_drive_strength_21_wd), + .d (hw2reg.dio_pad_attr[21].drive_strength.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[9]), + .q (reg2hw.dio_pad_attr[21].drive_strength.q), + .ds (), + .qs (dio_pad_attr_21_drive_strength_21_qs) + ); + assign reg2hw.dio_pad_attr[21].drive_strength.qe = dio_pad_attr_21_qe; + + + // Subregister 22 of Multireg dio_pad_attr + // R[dio_pad_attr_22]: V(True) + logic dio_pad_attr_22_qe; + logic [9:0] dio_pad_attr_22_flds_we; + assign dio_pad_attr_22_qe = &dio_pad_attr_22_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_22_gated_we; + assign dio_pad_attr_22_gated_we = dio_pad_attr_22_we & dio_pad_attr_regwen_22_qs; + // F[invert_22]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_invert_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_invert_22_wd), + .d (hw2reg.dio_pad_attr[22].invert.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[0]), + .q (reg2hw.dio_pad_attr[22].invert.q), + .ds (), + .qs (dio_pad_attr_22_invert_22_qs) + ); + assign reg2hw.dio_pad_attr[22].invert.qe = dio_pad_attr_22_qe; + + // F[virtual_od_en_22]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_virtual_od_en_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_virtual_od_en_22_wd), + .d (hw2reg.dio_pad_attr[22].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[1]), + .q (reg2hw.dio_pad_attr[22].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_22_virtual_od_en_22_qs) + ); + assign reg2hw.dio_pad_attr[22].virtual_od_en.qe = dio_pad_attr_22_qe; + + // F[pull_en_22]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_pull_en_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_pull_en_22_wd), + .d (hw2reg.dio_pad_attr[22].pull_en.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[2]), + .q (reg2hw.dio_pad_attr[22].pull_en.q), + .ds (), + .qs (dio_pad_attr_22_pull_en_22_qs) + ); + assign reg2hw.dio_pad_attr[22].pull_en.qe = dio_pad_attr_22_qe; + + // F[pull_select_22]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_pull_select_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_pull_select_22_wd), + .d (hw2reg.dio_pad_attr[22].pull_select.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[3]), + .q (reg2hw.dio_pad_attr[22].pull_select.q), + .ds (), + .qs (dio_pad_attr_22_pull_select_22_qs) + ); + assign reg2hw.dio_pad_attr[22].pull_select.qe = dio_pad_attr_22_qe; + + // F[keeper_en_22]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_keeper_en_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_keeper_en_22_wd), + .d (hw2reg.dio_pad_attr[22].keeper_en.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[4]), + .q (reg2hw.dio_pad_attr[22].keeper_en.q), + .ds (), + .qs (dio_pad_attr_22_keeper_en_22_qs) + ); + assign reg2hw.dio_pad_attr[22].keeper_en.qe = dio_pad_attr_22_qe; + + // F[schmitt_en_22]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_schmitt_en_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_schmitt_en_22_wd), + .d (hw2reg.dio_pad_attr[22].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[5]), + .q (reg2hw.dio_pad_attr[22].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_22_schmitt_en_22_qs) + ); + assign reg2hw.dio_pad_attr[22].schmitt_en.qe = dio_pad_attr_22_qe; + + // F[od_en_22]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_od_en_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_od_en_22_wd), + .d (hw2reg.dio_pad_attr[22].od_en.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[6]), + .q (reg2hw.dio_pad_attr[22].od_en.q), + .ds (), + .qs (dio_pad_attr_22_od_en_22_qs) + ); + assign reg2hw.dio_pad_attr[22].od_en.qe = dio_pad_attr_22_qe; + + // F[input_disable_22]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_input_disable_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_input_disable_22_wd), + .d (hw2reg.dio_pad_attr[22].input_disable.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[7]), + .q (reg2hw.dio_pad_attr[22].input_disable.q), + .ds (), + .qs (dio_pad_attr_22_input_disable_22_qs) + ); + assign reg2hw.dio_pad_attr[22].input_disable.qe = dio_pad_attr_22_qe; + + // F[slew_rate_22]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_22_slew_rate_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_slew_rate_22_wd), + .d (hw2reg.dio_pad_attr[22].slew_rate.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[8]), + .q (reg2hw.dio_pad_attr[22].slew_rate.q), + .ds (), + .qs (dio_pad_attr_22_slew_rate_22_qs) + ); + assign reg2hw.dio_pad_attr[22].slew_rate.qe = dio_pad_attr_22_qe; + + // F[drive_strength_22]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_22_drive_strength_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_drive_strength_22_wd), + .d (hw2reg.dio_pad_attr[22].drive_strength.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[9]), + .q (reg2hw.dio_pad_attr[22].drive_strength.q), + .ds (), + .qs (dio_pad_attr_22_drive_strength_22_qs) + ); + assign reg2hw.dio_pad_attr[22].drive_strength.qe = dio_pad_attr_22_qe; + + + // Subregister 23 of Multireg dio_pad_attr + // R[dio_pad_attr_23]: V(True) + logic dio_pad_attr_23_qe; + logic [9:0] dio_pad_attr_23_flds_we; + assign dio_pad_attr_23_qe = &dio_pad_attr_23_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_23_gated_we; + assign dio_pad_attr_23_gated_we = dio_pad_attr_23_we & dio_pad_attr_regwen_23_qs; + // F[invert_23]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_invert_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_invert_23_wd), + .d (hw2reg.dio_pad_attr[23].invert.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[0]), + .q (reg2hw.dio_pad_attr[23].invert.q), + .ds (), + .qs (dio_pad_attr_23_invert_23_qs) + ); + assign reg2hw.dio_pad_attr[23].invert.qe = dio_pad_attr_23_qe; + + // F[virtual_od_en_23]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_virtual_od_en_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_virtual_od_en_23_wd), + .d (hw2reg.dio_pad_attr[23].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[1]), + .q (reg2hw.dio_pad_attr[23].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_23_virtual_od_en_23_qs) + ); + assign reg2hw.dio_pad_attr[23].virtual_od_en.qe = dio_pad_attr_23_qe; + + // F[pull_en_23]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_pull_en_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_pull_en_23_wd), + .d (hw2reg.dio_pad_attr[23].pull_en.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[2]), + .q (reg2hw.dio_pad_attr[23].pull_en.q), + .ds (), + .qs (dio_pad_attr_23_pull_en_23_qs) + ); + assign reg2hw.dio_pad_attr[23].pull_en.qe = dio_pad_attr_23_qe; + + // F[pull_select_23]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_pull_select_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_pull_select_23_wd), + .d (hw2reg.dio_pad_attr[23].pull_select.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[3]), + .q (reg2hw.dio_pad_attr[23].pull_select.q), + .ds (), + .qs (dio_pad_attr_23_pull_select_23_qs) + ); + assign reg2hw.dio_pad_attr[23].pull_select.qe = dio_pad_attr_23_qe; + + // F[keeper_en_23]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_keeper_en_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_keeper_en_23_wd), + .d (hw2reg.dio_pad_attr[23].keeper_en.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[4]), + .q (reg2hw.dio_pad_attr[23].keeper_en.q), + .ds (), + .qs (dio_pad_attr_23_keeper_en_23_qs) + ); + assign reg2hw.dio_pad_attr[23].keeper_en.qe = dio_pad_attr_23_qe; + + // F[schmitt_en_23]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_schmitt_en_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_schmitt_en_23_wd), + .d (hw2reg.dio_pad_attr[23].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[5]), + .q (reg2hw.dio_pad_attr[23].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_23_schmitt_en_23_qs) + ); + assign reg2hw.dio_pad_attr[23].schmitt_en.qe = dio_pad_attr_23_qe; + + // F[od_en_23]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_od_en_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_od_en_23_wd), + .d (hw2reg.dio_pad_attr[23].od_en.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[6]), + .q (reg2hw.dio_pad_attr[23].od_en.q), + .ds (), + .qs (dio_pad_attr_23_od_en_23_qs) + ); + assign reg2hw.dio_pad_attr[23].od_en.qe = dio_pad_attr_23_qe; + + // F[input_disable_23]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_input_disable_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_input_disable_23_wd), + .d (hw2reg.dio_pad_attr[23].input_disable.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[7]), + .q (reg2hw.dio_pad_attr[23].input_disable.q), + .ds (), + .qs (dio_pad_attr_23_input_disable_23_qs) + ); + assign reg2hw.dio_pad_attr[23].input_disable.qe = dio_pad_attr_23_qe; + + // F[slew_rate_23]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_23_slew_rate_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_slew_rate_23_wd), + .d (hw2reg.dio_pad_attr[23].slew_rate.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[8]), + .q (reg2hw.dio_pad_attr[23].slew_rate.q), + .ds (), + .qs (dio_pad_attr_23_slew_rate_23_qs) + ); + assign reg2hw.dio_pad_attr[23].slew_rate.qe = dio_pad_attr_23_qe; + + // F[drive_strength_23]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_23_drive_strength_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_drive_strength_23_wd), + .d (hw2reg.dio_pad_attr[23].drive_strength.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[9]), + .q (reg2hw.dio_pad_attr[23].drive_strength.q), + .ds (), + .qs (dio_pad_attr_23_drive_strength_23_qs) + ); + assign reg2hw.dio_pad_attr[23].drive_strength.qe = dio_pad_attr_23_qe; + + + // Subregister 24 of Multireg dio_pad_attr + // R[dio_pad_attr_24]: V(True) + logic dio_pad_attr_24_qe; + logic [9:0] dio_pad_attr_24_flds_we; + assign dio_pad_attr_24_qe = &dio_pad_attr_24_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_24_gated_we; + assign dio_pad_attr_24_gated_we = dio_pad_attr_24_we & dio_pad_attr_regwen_24_qs; + // F[invert_24]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_invert_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_invert_24_wd), + .d (hw2reg.dio_pad_attr[24].invert.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[0]), + .q (reg2hw.dio_pad_attr[24].invert.q), + .ds (), + .qs (dio_pad_attr_24_invert_24_qs) + ); + assign reg2hw.dio_pad_attr[24].invert.qe = dio_pad_attr_24_qe; + + // F[virtual_od_en_24]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_virtual_od_en_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_virtual_od_en_24_wd), + .d (hw2reg.dio_pad_attr[24].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[1]), + .q (reg2hw.dio_pad_attr[24].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_24_virtual_od_en_24_qs) + ); + assign reg2hw.dio_pad_attr[24].virtual_od_en.qe = dio_pad_attr_24_qe; + + // F[pull_en_24]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_pull_en_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_pull_en_24_wd), + .d (hw2reg.dio_pad_attr[24].pull_en.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[2]), + .q (reg2hw.dio_pad_attr[24].pull_en.q), + .ds (), + .qs (dio_pad_attr_24_pull_en_24_qs) + ); + assign reg2hw.dio_pad_attr[24].pull_en.qe = dio_pad_attr_24_qe; + + // F[pull_select_24]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_pull_select_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_pull_select_24_wd), + .d (hw2reg.dio_pad_attr[24].pull_select.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[3]), + .q (reg2hw.dio_pad_attr[24].pull_select.q), + .ds (), + .qs (dio_pad_attr_24_pull_select_24_qs) + ); + assign reg2hw.dio_pad_attr[24].pull_select.qe = dio_pad_attr_24_qe; + + // F[keeper_en_24]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_keeper_en_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_keeper_en_24_wd), + .d (hw2reg.dio_pad_attr[24].keeper_en.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[4]), + .q (reg2hw.dio_pad_attr[24].keeper_en.q), + .ds (), + .qs (dio_pad_attr_24_keeper_en_24_qs) + ); + assign reg2hw.dio_pad_attr[24].keeper_en.qe = dio_pad_attr_24_qe; + + // F[schmitt_en_24]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_schmitt_en_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_schmitt_en_24_wd), + .d (hw2reg.dio_pad_attr[24].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[5]), + .q (reg2hw.dio_pad_attr[24].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_24_schmitt_en_24_qs) + ); + assign reg2hw.dio_pad_attr[24].schmitt_en.qe = dio_pad_attr_24_qe; + + // F[od_en_24]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_od_en_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_od_en_24_wd), + .d (hw2reg.dio_pad_attr[24].od_en.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[6]), + .q (reg2hw.dio_pad_attr[24].od_en.q), + .ds (), + .qs (dio_pad_attr_24_od_en_24_qs) + ); + assign reg2hw.dio_pad_attr[24].od_en.qe = dio_pad_attr_24_qe; + + // F[input_disable_24]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_input_disable_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_input_disable_24_wd), + .d (hw2reg.dio_pad_attr[24].input_disable.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[7]), + .q (reg2hw.dio_pad_attr[24].input_disable.q), + .ds (), + .qs (dio_pad_attr_24_input_disable_24_qs) + ); + assign reg2hw.dio_pad_attr[24].input_disable.qe = dio_pad_attr_24_qe; + + // F[slew_rate_24]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_24_slew_rate_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_slew_rate_24_wd), + .d (hw2reg.dio_pad_attr[24].slew_rate.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[8]), + .q (reg2hw.dio_pad_attr[24].slew_rate.q), + .ds (), + .qs (dio_pad_attr_24_slew_rate_24_qs) + ); + assign reg2hw.dio_pad_attr[24].slew_rate.qe = dio_pad_attr_24_qe; + + // F[drive_strength_24]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_24_drive_strength_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_drive_strength_24_wd), + .d (hw2reg.dio_pad_attr[24].drive_strength.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[9]), + .q (reg2hw.dio_pad_attr[24].drive_strength.q), + .ds (), + .qs (dio_pad_attr_24_drive_strength_24_qs) + ); + assign reg2hw.dio_pad_attr[24].drive_strength.qe = dio_pad_attr_24_qe; + + + // Subregister 25 of Multireg dio_pad_attr + // R[dio_pad_attr_25]: V(True) + logic dio_pad_attr_25_qe; + logic [9:0] dio_pad_attr_25_flds_we; + assign dio_pad_attr_25_qe = &dio_pad_attr_25_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_25_gated_we; + assign dio_pad_attr_25_gated_we = dio_pad_attr_25_we & dio_pad_attr_regwen_25_qs; + // F[invert_25]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_invert_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_invert_25_wd), + .d (hw2reg.dio_pad_attr[25].invert.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[0]), + .q (reg2hw.dio_pad_attr[25].invert.q), + .ds (), + .qs (dio_pad_attr_25_invert_25_qs) + ); + assign reg2hw.dio_pad_attr[25].invert.qe = dio_pad_attr_25_qe; + + // F[virtual_od_en_25]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_virtual_od_en_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_virtual_od_en_25_wd), + .d (hw2reg.dio_pad_attr[25].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[1]), + .q (reg2hw.dio_pad_attr[25].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_25_virtual_od_en_25_qs) + ); + assign reg2hw.dio_pad_attr[25].virtual_od_en.qe = dio_pad_attr_25_qe; + + // F[pull_en_25]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_pull_en_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_pull_en_25_wd), + .d (hw2reg.dio_pad_attr[25].pull_en.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[2]), + .q (reg2hw.dio_pad_attr[25].pull_en.q), + .ds (), + .qs (dio_pad_attr_25_pull_en_25_qs) + ); + assign reg2hw.dio_pad_attr[25].pull_en.qe = dio_pad_attr_25_qe; + + // F[pull_select_25]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_pull_select_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_pull_select_25_wd), + .d (hw2reg.dio_pad_attr[25].pull_select.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[3]), + .q (reg2hw.dio_pad_attr[25].pull_select.q), + .ds (), + .qs (dio_pad_attr_25_pull_select_25_qs) + ); + assign reg2hw.dio_pad_attr[25].pull_select.qe = dio_pad_attr_25_qe; + + // F[keeper_en_25]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_keeper_en_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_keeper_en_25_wd), + .d (hw2reg.dio_pad_attr[25].keeper_en.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[4]), + .q (reg2hw.dio_pad_attr[25].keeper_en.q), + .ds (), + .qs (dio_pad_attr_25_keeper_en_25_qs) + ); + assign reg2hw.dio_pad_attr[25].keeper_en.qe = dio_pad_attr_25_qe; + + // F[schmitt_en_25]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_schmitt_en_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_schmitt_en_25_wd), + .d (hw2reg.dio_pad_attr[25].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[5]), + .q (reg2hw.dio_pad_attr[25].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_25_schmitt_en_25_qs) + ); + assign reg2hw.dio_pad_attr[25].schmitt_en.qe = dio_pad_attr_25_qe; + + // F[od_en_25]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_od_en_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_od_en_25_wd), + .d (hw2reg.dio_pad_attr[25].od_en.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[6]), + .q (reg2hw.dio_pad_attr[25].od_en.q), + .ds (), + .qs (dio_pad_attr_25_od_en_25_qs) + ); + assign reg2hw.dio_pad_attr[25].od_en.qe = dio_pad_attr_25_qe; + + // F[input_disable_25]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_input_disable_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_input_disable_25_wd), + .d (hw2reg.dio_pad_attr[25].input_disable.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[7]), + .q (reg2hw.dio_pad_attr[25].input_disable.q), + .ds (), + .qs (dio_pad_attr_25_input_disable_25_qs) + ); + assign reg2hw.dio_pad_attr[25].input_disable.qe = dio_pad_attr_25_qe; + + // F[slew_rate_25]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_25_slew_rate_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_slew_rate_25_wd), + .d (hw2reg.dio_pad_attr[25].slew_rate.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[8]), + .q (reg2hw.dio_pad_attr[25].slew_rate.q), + .ds (), + .qs (dio_pad_attr_25_slew_rate_25_qs) + ); + assign reg2hw.dio_pad_attr[25].slew_rate.qe = dio_pad_attr_25_qe; + + // F[drive_strength_25]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_25_drive_strength_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_drive_strength_25_wd), + .d (hw2reg.dio_pad_attr[25].drive_strength.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[9]), + .q (reg2hw.dio_pad_attr[25].drive_strength.q), + .ds (), + .qs (dio_pad_attr_25_drive_strength_25_qs) + ); + assign reg2hw.dio_pad_attr[25].drive_strength.qe = dio_pad_attr_25_qe; + + + // Subregister 26 of Multireg dio_pad_attr + // R[dio_pad_attr_26]: V(True) + logic dio_pad_attr_26_qe; + logic [9:0] dio_pad_attr_26_flds_we; + assign dio_pad_attr_26_qe = &dio_pad_attr_26_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_26_gated_we; + assign dio_pad_attr_26_gated_we = dio_pad_attr_26_we & dio_pad_attr_regwen_26_qs; + // F[invert_26]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_invert_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_invert_26_wd), + .d (hw2reg.dio_pad_attr[26].invert.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[0]), + .q (reg2hw.dio_pad_attr[26].invert.q), + .ds (), + .qs (dio_pad_attr_26_invert_26_qs) + ); + assign reg2hw.dio_pad_attr[26].invert.qe = dio_pad_attr_26_qe; + + // F[virtual_od_en_26]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_virtual_od_en_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_virtual_od_en_26_wd), + .d (hw2reg.dio_pad_attr[26].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[1]), + .q (reg2hw.dio_pad_attr[26].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_26_virtual_od_en_26_qs) + ); + assign reg2hw.dio_pad_attr[26].virtual_od_en.qe = dio_pad_attr_26_qe; + + // F[pull_en_26]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_pull_en_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_pull_en_26_wd), + .d (hw2reg.dio_pad_attr[26].pull_en.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[2]), + .q (reg2hw.dio_pad_attr[26].pull_en.q), + .ds (), + .qs (dio_pad_attr_26_pull_en_26_qs) + ); + assign reg2hw.dio_pad_attr[26].pull_en.qe = dio_pad_attr_26_qe; + + // F[pull_select_26]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_pull_select_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_pull_select_26_wd), + .d (hw2reg.dio_pad_attr[26].pull_select.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[3]), + .q (reg2hw.dio_pad_attr[26].pull_select.q), + .ds (), + .qs (dio_pad_attr_26_pull_select_26_qs) + ); + assign reg2hw.dio_pad_attr[26].pull_select.qe = dio_pad_attr_26_qe; + + // F[keeper_en_26]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_keeper_en_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_keeper_en_26_wd), + .d (hw2reg.dio_pad_attr[26].keeper_en.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[4]), + .q (reg2hw.dio_pad_attr[26].keeper_en.q), + .ds (), + .qs (dio_pad_attr_26_keeper_en_26_qs) + ); + assign reg2hw.dio_pad_attr[26].keeper_en.qe = dio_pad_attr_26_qe; + + // F[schmitt_en_26]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_schmitt_en_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_schmitt_en_26_wd), + .d (hw2reg.dio_pad_attr[26].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[5]), + .q (reg2hw.dio_pad_attr[26].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_26_schmitt_en_26_qs) + ); + assign reg2hw.dio_pad_attr[26].schmitt_en.qe = dio_pad_attr_26_qe; + + // F[od_en_26]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_od_en_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_od_en_26_wd), + .d (hw2reg.dio_pad_attr[26].od_en.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[6]), + .q (reg2hw.dio_pad_attr[26].od_en.q), + .ds (), + .qs (dio_pad_attr_26_od_en_26_qs) + ); + assign reg2hw.dio_pad_attr[26].od_en.qe = dio_pad_attr_26_qe; + + // F[input_disable_26]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_input_disable_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_input_disable_26_wd), + .d (hw2reg.dio_pad_attr[26].input_disable.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[7]), + .q (reg2hw.dio_pad_attr[26].input_disable.q), + .ds (), + .qs (dio_pad_attr_26_input_disable_26_qs) + ); + assign reg2hw.dio_pad_attr[26].input_disable.qe = dio_pad_attr_26_qe; + + // F[slew_rate_26]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_26_slew_rate_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_slew_rate_26_wd), + .d (hw2reg.dio_pad_attr[26].slew_rate.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[8]), + .q (reg2hw.dio_pad_attr[26].slew_rate.q), + .ds (), + .qs (dio_pad_attr_26_slew_rate_26_qs) + ); + assign reg2hw.dio_pad_attr[26].slew_rate.qe = dio_pad_attr_26_qe; + + // F[drive_strength_26]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_26_drive_strength_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_drive_strength_26_wd), + .d (hw2reg.dio_pad_attr[26].drive_strength.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[9]), + .q (reg2hw.dio_pad_attr[26].drive_strength.q), + .ds (), + .qs (dio_pad_attr_26_drive_strength_26_qs) + ); + assign reg2hw.dio_pad_attr[26].drive_strength.qe = dio_pad_attr_26_qe; + + + // Subregister 27 of Multireg dio_pad_attr + // R[dio_pad_attr_27]: V(True) + logic dio_pad_attr_27_qe; + logic [9:0] dio_pad_attr_27_flds_we; + assign dio_pad_attr_27_qe = &dio_pad_attr_27_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_27_gated_we; + assign dio_pad_attr_27_gated_we = dio_pad_attr_27_we & dio_pad_attr_regwen_27_qs; + // F[invert_27]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_invert_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_invert_27_wd), + .d (hw2reg.dio_pad_attr[27].invert.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[0]), + .q (reg2hw.dio_pad_attr[27].invert.q), + .ds (), + .qs (dio_pad_attr_27_invert_27_qs) + ); + assign reg2hw.dio_pad_attr[27].invert.qe = dio_pad_attr_27_qe; + + // F[virtual_od_en_27]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_virtual_od_en_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_virtual_od_en_27_wd), + .d (hw2reg.dio_pad_attr[27].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[1]), + .q (reg2hw.dio_pad_attr[27].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_27_virtual_od_en_27_qs) + ); + assign reg2hw.dio_pad_attr[27].virtual_od_en.qe = dio_pad_attr_27_qe; + + // F[pull_en_27]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_pull_en_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_pull_en_27_wd), + .d (hw2reg.dio_pad_attr[27].pull_en.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[2]), + .q (reg2hw.dio_pad_attr[27].pull_en.q), + .ds (), + .qs (dio_pad_attr_27_pull_en_27_qs) + ); + assign reg2hw.dio_pad_attr[27].pull_en.qe = dio_pad_attr_27_qe; + + // F[pull_select_27]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_pull_select_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_pull_select_27_wd), + .d (hw2reg.dio_pad_attr[27].pull_select.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[3]), + .q (reg2hw.dio_pad_attr[27].pull_select.q), + .ds (), + .qs (dio_pad_attr_27_pull_select_27_qs) + ); + assign reg2hw.dio_pad_attr[27].pull_select.qe = dio_pad_attr_27_qe; + + // F[keeper_en_27]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_keeper_en_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_keeper_en_27_wd), + .d (hw2reg.dio_pad_attr[27].keeper_en.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[4]), + .q (reg2hw.dio_pad_attr[27].keeper_en.q), + .ds (), + .qs (dio_pad_attr_27_keeper_en_27_qs) + ); + assign reg2hw.dio_pad_attr[27].keeper_en.qe = dio_pad_attr_27_qe; + + // F[schmitt_en_27]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_schmitt_en_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_schmitt_en_27_wd), + .d (hw2reg.dio_pad_attr[27].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[5]), + .q (reg2hw.dio_pad_attr[27].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_27_schmitt_en_27_qs) + ); + assign reg2hw.dio_pad_attr[27].schmitt_en.qe = dio_pad_attr_27_qe; + + // F[od_en_27]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_od_en_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_od_en_27_wd), + .d (hw2reg.dio_pad_attr[27].od_en.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[6]), + .q (reg2hw.dio_pad_attr[27].od_en.q), + .ds (), + .qs (dio_pad_attr_27_od_en_27_qs) + ); + assign reg2hw.dio_pad_attr[27].od_en.qe = dio_pad_attr_27_qe; + + // F[input_disable_27]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_input_disable_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_input_disable_27_wd), + .d (hw2reg.dio_pad_attr[27].input_disable.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[7]), + .q (reg2hw.dio_pad_attr[27].input_disable.q), + .ds (), + .qs (dio_pad_attr_27_input_disable_27_qs) + ); + assign reg2hw.dio_pad_attr[27].input_disable.qe = dio_pad_attr_27_qe; + + // F[slew_rate_27]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_27_slew_rate_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_slew_rate_27_wd), + .d (hw2reg.dio_pad_attr[27].slew_rate.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[8]), + .q (reg2hw.dio_pad_attr[27].slew_rate.q), + .ds (), + .qs (dio_pad_attr_27_slew_rate_27_qs) + ); + assign reg2hw.dio_pad_attr[27].slew_rate.qe = dio_pad_attr_27_qe; + + // F[drive_strength_27]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_27_drive_strength_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_drive_strength_27_wd), + .d (hw2reg.dio_pad_attr[27].drive_strength.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[9]), + .q (reg2hw.dio_pad_attr[27].drive_strength.q), + .ds (), + .qs (dio_pad_attr_27_drive_strength_27_qs) + ); + assign reg2hw.dio_pad_attr[27].drive_strength.qe = dio_pad_attr_27_qe; + + + // Subregister 28 of Multireg dio_pad_attr + // R[dio_pad_attr_28]: V(True) + logic dio_pad_attr_28_qe; + logic [9:0] dio_pad_attr_28_flds_we; + assign dio_pad_attr_28_qe = &dio_pad_attr_28_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_28_gated_we; + assign dio_pad_attr_28_gated_we = dio_pad_attr_28_we & dio_pad_attr_regwen_28_qs; + // F[invert_28]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_invert_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_invert_28_wd), + .d (hw2reg.dio_pad_attr[28].invert.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[0]), + .q (reg2hw.dio_pad_attr[28].invert.q), + .ds (), + .qs (dio_pad_attr_28_invert_28_qs) + ); + assign reg2hw.dio_pad_attr[28].invert.qe = dio_pad_attr_28_qe; + + // F[virtual_od_en_28]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_virtual_od_en_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_virtual_od_en_28_wd), + .d (hw2reg.dio_pad_attr[28].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[1]), + .q (reg2hw.dio_pad_attr[28].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_28_virtual_od_en_28_qs) + ); + assign reg2hw.dio_pad_attr[28].virtual_od_en.qe = dio_pad_attr_28_qe; + + // F[pull_en_28]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_pull_en_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_pull_en_28_wd), + .d (hw2reg.dio_pad_attr[28].pull_en.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[2]), + .q (reg2hw.dio_pad_attr[28].pull_en.q), + .ds (), + .qs (dio_pad_attr_28_pull_en_28_qs) + ); + assign reg2hw.dio_pad_attr[28].pull_en.qe = dio_pad_attr_28_qe; + + // F[pull_select_28]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_pull_select_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_pull_select_28_wd), + .d (hw2reg.dio_pad_attr[28].pull_select.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[3]), + .q (reg2hw.dio_pad_attr[28].pull_select.q), + .ds (), + .qs (dio_pad_attr_28_pull_select_28_qs) + ); + assign reg2hw.dio_pad_attr[28].pull_select.qe = dio_pad_attr_28_qe; + + // F[keeper_en_28]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_keeper_en_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_keeper_en_28_wd), + .d (hw2reg.dio_pad_attr[28].keeper_en.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[4]), + .q (reg2hw.dio_pad_attr[28].keeper_en.q), + .ds (), + .qs (dio_pad_attr_28_keeper_en_28_qs) + ); + assign reg2hw.dio_pad_attr[28].keeper_en.qe = dio_pad_attr_28_qe; + + // F[schmitt_en_28]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_schmitt_en_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_schmitt_en_28_wd), + .d (hw2reg.dio_pad_attr[28].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[5]), + .q (reg2hw.dio_pad_attr[28].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_28_schmitt_en_28_qs) + ); + assign reg2hw.dio_pad_attr[28].schmitt_en.qe = dio_pad_attr_28_qe; + + // F[od_en_28]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_od_en_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_od_en_28_wd), + .d (hw2reg.dio_pad_attr[28].od_en.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[6]), + .q (reg2hw.dio_pad_attr[28].od_en.q), + .ds (), + .qs (dio_pad_attr_28_od_en_28_qs) + ); + assign reg2hw.dio_pad_attr[28].od_en.qe = dio_pad_attr_28_qe; + + // F[input_disable_28]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_input_disable_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_input_disable_28_wd), + .d (hw2reg.dio_pad_attr[28].input_disable.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[7]), + .q (reg2hw.dio_pad_attr[28].input_disable.q), + .ds (), + .qs (dio_pad_attr_28_input_disable_28_qs) + ); + assign reg2hw.dio_pad_attr[28].input_disable.qe = dio_pad_attr_28_qe; + + // F[slew_rate_28]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_28_slew_rate_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_slew_rate_28_wd), + .d (hw2reg.dio_pad_attr[28].slew_rate.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[8]), + .q (reg2hw.dio_pad_attr[28].slew_rate.q), + .ds (), + .qs (dio_pad_attr_28_slew_rate_28_qs) + ); + assign reg2hw.dio_pad_attr[28].slew_rate.qe = dio_pad_attr_28_qe; + + // F[drive_strength_28]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_28_drive_strength_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_drive_strength_28_wd), + .d (hw2reg.dio_pad_attr[28].drive_strength.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[9]), + .q (reg2hw.dio_pad_attr[28].drive_strength.q), + .ds (), + .qs (dio_pad_attr_28_drive_strength_28_qs) + ); + assign reg2hw.dio_pad_attr[28].drive_strength.qe = dio_pad_attr_28_qe; + + + // Subregister 29 of Multireg dio_pad_attr + // R[dio_pad_attr_29]: V(True) + logic dio_pad_attr_29_qe; + logic [9:0] dio_pad_attr_29_flds_we; + assign dio_pad_attr_29_qe = &dio_pad_attr_29_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_29_gated_we; + assign dio_pad_attr_29_gated_we = dio_pad_attr_29_we & dio_pad_attr_regwen_29_qs; + // F[invert_29]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_invert_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_invert_29_wd), + .d (hw2reg.dio_pad_attr[29].invert.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[0]), + .q (reg2hw.dio_pad_attr[29].invert.q), + .ds (), + .qs (dio_pad_attr_29_invert_29_qs) + ); + assign reg2hw.dio_pad_attr[29].invert.qe = dio_pad_attr_29_qe; + + // F[virtual_od_en_29]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_virtual_od_en_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_virtual_od_en_29_wd), + .d (hw2reg.dio_pad_attr[29].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[1]), + .q (reg2hw.dio_pad_attr[29].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_29_virtual_od_en_29_qs) + ); + assign reg2hw.dio_pad_attr[29].virtual_od_en.qe = dio_pad_attr_29_qe; + + // F[pull_en_29]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_pull_en_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_pull_en_29_wd), + .d (hw2reg.dio_pad_attr[29].pull_en.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[2]), + .q (reg2hw.dio_pad_attr[29].pull_en.q), + .ds (), + .qs (dio_pad_attr_29_pull_en_29_qs) + ); + assign reg2hw.dio_pad_attr[29].pull_en.qe = dio_pad_attr_29_qe; + + // F[pull_select_29]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_pull_select_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_pull_select_29_wd), + .d (hw2reg.dio_pad_attr[29].pull_select.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[3]), + .q (reg2hw.dio_pad_attr[29].pull_select.q), + .ds (), + .qs (dio_pad_attr_29_pull_select_29_qs) + ); + assign reg2hw.dio_pad_attr[29].pull_select.qe = dio_pad_attr_29_qe; + + // F[keeper_en_29]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_keeper_en_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_keeper_en_29_wd), + .d (hw2reg.dio_pad_attr[29].keeper_en.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[4]), + .q (reg2hw.dio_pad_attr[29].keeper_en.q), + .ds (), + .qs (dio_pad_attr_29_keeper_en_29_qs) + ); + assign reg2hw.dio_pad_attr[29].keeper_en.qe = dio_pad_attr_29_qe; + + // F[schmitt_en_29]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_schmitt_en_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_schmitt_en_29_wd), + .d (hw2reg.dio_pad_attr[29].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[5]), + .q (reg2hw.dio_pad_attr[29].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_29_schmitt_en_29_qs) + ); + assign reg2hw.dio_pad_attr[29].schmitt_en.qe = dio_pad_attr_29_qe; + + // F[od_en_29]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_od_en_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_od_en_29_wd), + .d (hw2reg.dio_pad_attr[29].od_en.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[6]), + .q (reg2hw.dio_pad_attr[29].od_en.q), + .ds (), + .qs (dio_pad_attr_29_od_en_29_qs) + ); + assign reg2hw.dio_pad_attr[29].od_en.qe = dio_pad_attr_29_qe; + + // F[input_disable_29]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_input_disable_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_input_disable_29_wd), + .d (hw2reg.dio_pad_attr[29].input_disable.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[7]), + .q (reg2hw.dio_pad_attr[29].input_disable.q), + .ds (), + .qs (dio_pad_attr_29_input_disable_29_qs) + ); + assign reg2hw.dio_pad_attr[29].input_disable.qe = dio_pad_attr_29_qe; + + // F[slew_rate_29]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_29_slew_rate_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_slew_rate_29_wd), + .d (hw2reg.dio_pad_attr[29].slew_rate.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[8]), + .q (reg2hw.dio_pad_attr[29].slew_rate.q), + .ds (), + .qs (dio_pad_attr_29_slew_rate_29_qs) + ); + assign reg2hw.dio_pad_attr[29].slew_rate.qe = dio_pad_attr_29_qe; + + // F[drive_strength_29]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_29_drive_strength_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_drive_strength_29_wd), + .d (hw2reg.dio_pad_attr[29].drive_strength.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[9]), + .q (reg2hw.dio_pad_attr[29].drive_strength.q), + .ds (), + .qs (dio_pad_attr_29_drive_strength_29_qs) + ); + assign reg2hw.dio_pad_attr[29].drive_strength.qe = dio_pad_attr_29_qe; + + + // Subregister 30 of Multireg dio_pad_attr + // R[dio_pad_attr_30]: V(True) + logic dio_pad_attr_30_qe; + logic [9:0] dio_pad_attr_30_flds_we; + assign dio_pad_attr_30_qe = &dio_pad_attr_30_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_30_gated_we; + assign dio_pad_attr_30_gated_we = dio_pad_attr_30_we & dio_pad_attr_regwen_30_qs; + // F[invert_30]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_invert_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_invert_30_wd), + .d (hw2reg.dio_pad_attr[30].invert.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[0]), + .q (reg2hw.dio_pad_attr[30].invert.q), + .ds (), + .qs (dio_pad_attr_30_invert_30_qs) + ); + assign reg2hw.dio_pad_attr[30].invert.qe = dio_pad_attr_30_qe; + + // F[virtual_od_en_30]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_virtual_od_en_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_virtual_od_en_30_wd), + .d (hw2reg.dio_pad_attr[30].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[1]), + .q (reg2hw.dio_pad_attr[30].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_30_virtual_od_en_30_qs) + ); + assign reg2hw.dio_pad_attr[30].virtual_od_en.qe = dio_pad_attr_30_qe; + + // F[pull_en_30]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_pull_en_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_pull_en_30_wd), + .d (hw2reg.dio_pad_attr[30].pull_en.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[2]), + .q (reg2hw.dio_pad_attr[30].pull_en.q), + .ds (), + .qs (dio_pad_attr_30_pull_en_30_qs) + ); + assign reg2hw.dio_pad_attr[30].pull_en.qe = dio_pad_attr_30_qe; + + // F[pull_select_30]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_pull_select_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_pull_select_30_wd), + .d (hw2reg.dio_pad_attr[30].pull_select.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[3]), + .q (reg2hw.dio_pad_attr[30].pull_select.q), + .ds (), + .qs (dio_pad_attr_30_pull_select_30_qs) + ); + assign reg2hw.dio_pad_attr[30].pull_select.qe = dio_pad_attr_30_qe; + + // F[keeper_en_30]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_keeper_en_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_keeper_en_30_wd), + .d (hw2reg.dio_pad_attr[30].keeper_en.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[4]), + .q (reg2hw.dio_pad_attr[30].keeper_en.q), + .ds (), + .qs (dio_pad_attr_30_keeper_en_30_qs) + ); + assign reg2hw.dio_pad_attr[30].keeper_en.qe = dio_pad_attr_30_qe; + + // F[schmitt_en_30]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_schmitt_en_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_schmitt_en_30_wd), + .d (hw2reg.dio_pad_attr[30].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[5]), + .q (reg2hw.dio_pad_attr[30].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_30_schmitt_en_30_qs) + ); + assign reg2hw.dio_pad_attr[30].schmitt_en.qe = dio_pad_attr_30_qe; + + // F[od_en_30]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_od_en_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_od_en_30_wd), + .d (hw2reg.dio_pad_attr[30].od_en.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[6]), + .q (reg2hw.dio_pad_attr[30].od_en.q), + .ds (), + .qs (dio_pad_attr_30_od_en_30_qs) + ); + assign reg2hw.dio_pad_attr[30].od_en.qe = dio_pad_attr_30_qe; + + // F[input_disable_30]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_input_disable_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_input_disable_30_wd), + .d (hw2reg.dio_pad_attr[30].input_disable.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[7]), + .q (reg2hw.dio_pad_attr[30].input_disable.q), + .ds (), + .qs (dio_pad_attr_30_input_disable_30_qs) + ); + assign reg2hw.dio_pad_attr[30].input_disable.qe = dio_pad_attr_30_qe; + + // F[slew_rate_30]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_30_slew_rate_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_slew_rate_30_wd), + .d (hw2reg.dio_pad_attr[30].slew_rate.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[8]), + .q (reg2hw.dio_pad_attr[30].slew_rate.q), + .ds (), + .qs (dio_pad_attr_30_slew_rate_30_qs) + ); + assign reg2hw.dio_pad_attr[30].slew_rate.qe = dio_pad_attr_30_qe; + + // F[drive_strength_30]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_30_drive_strength_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_drive_strength_30_wd), + .d (hw2reg.dio_pad_attr[30].drive_strength.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[9]), + .q (reg2hw.dio_pad_attr[30].drive_strength.q), + .ds (), + .qs (dio_pad_attr_30_drive_strength_30_qs) + ); + assign reg2hw.dio_pad_attr[30].drive_strength.qe = dio_pad_attr_30_qe; + + + // Subregister 31 of Multireg dio_pad_attr + // R[dio_pad_attr_31]: V(True) + logic dio_pad_attr_31_qe; + logic [9:0] dio_pad_attr_31_flds_we; + assign dio_pad_attr_31_qe = &dio_pad_attr_31_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_31_gated_we; + assign dio_pad_attr_31_gated_we = dio_pad_attr_31_we & dio_pad_attr_regwen_31_qs; + // F[invert_31]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_invert_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_invert_31_wd), + .d (hw2reg.dio_pad_attr[31].invert.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[0]), + .q (reg2hw.dio_pad_attr[31].invert.q), + .ds (), + .qs (dio_pad_attr_31_invert_31_qs) + ); + assign reg2hw.dio_pad_attr[31].invert.qe = dio_pad_attr_31_qe; + + // F[virtual_od_en_31]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_virtual_od_en_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_virtual_od_en_31_wd), + .d (hw2reg.dio_pad_attr[31].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[1]), + .q (reg2hw.dio_pad_attr[31].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_31_virtual_od_en_31_qs) + ); + assign reg2hw.dio_pad_attr[31].virtual_od_en.qe = dio_pad_attr_31_qe; + + // F[pull_en_31]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_pull_en_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_pull_en_31_wd), + .d (hw2reg.dio_pad_attr[31].pull_en.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[2]), + .q (reg2hw.dio_pad_attr[31].pull_en.q), + .ds (), + .qs (dio_pad_attr_31_pull_en_31_qs) + ); + assign reg2hw.dio_pad_attr[31].pull_en.qe = dio_pad_attr_31_qe; + + // F[pull_select_31]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_pull_select_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_pull_select_31_wd), + .d (hw2reg.dio_pad_attr[31].pull_select.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[3]), + .q (reg2hw.dio_pad_attr[31].pull_select.q), + .ds (), + .qs (dio_pad_attr_31_pull_select_31_qs) + ); + assign reg2hw.dio_pad_attr[31].pull_select.qe = dio_pad_attr_31_qe; + + // F[keeper_en_31]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_keeper_en_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_keeper_en_31_wd), + .d (hw2reg.dio_pad_attr[31].keeper_en.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[4]), + .q (reg2hw.dio_pad_attr[31].keeper_en.q), + .ds (), + .qs (dio_pad_attr_31_keeper_en_31_qs) + ); + assign reg2hw.dio_pad_attr[31].keeper_en.qe = dio_pad_attr_31_qe; + + // F[schmitt_en_31]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_schmitt_en_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_schmitt_en_31_wd), + .d (hw2reg.dio_pad_attr[31].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[5]), + .q (reg2hw.dio_pad_attr[31].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_31_schmitt_en_31_qs) + ); + assign reg2hw.dio_pad_attr[31].schmitt_en.qe = dio_pad_attr_31_qe; + + // F[od_en_31]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_od_en_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_od_en_31_wd), + .d (hw2reg.dio_pad_attr[31].od_en.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[6]), + .q (reg2hw.dio_pad_attr[31].od_en.q), + .ds (), + .qs (dio_pad_attr_31_od_en_31_qs) + ); + assign reg2hw.dio_pad_attr[31].od_en.qe = dio_pad_attr_31_qe; + + // F[input_disable_31]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_input_disable_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_input_disable_31_wd), + .d (hw2reg.dio_pad_attr[31].input_disable.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[7]), + .q (reg2hw.dio_pad_attr[31].input_disable.q), + .ds (), + .qs (dio_pad_attr_31_input_disable_31_qs) + ); + assign reg2hw.dio_pad_attr[31].input_disable.qe = dio_pad_attr_31_qe; + + // F[slew_rate_31]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_31_slew_rate_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_slew_rate_31_wd), + .d (hw2reg.dio_pad_attr[31].slew_rate.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[8]), + .q (reg2hw.dio_pad_attr[31].slew_rate.q), + .ds (), + .qs (dio_pad_attr_31_slew_rate_31_qs) + ); + assign reg2hw.dio_pad_attr[31].slew_rate.qe = dio_pad_attr_31_qe; + + // F[drive_strength_31]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_31_drive_strength_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_drive_strength_31_wd), + .d (hw2reg.dio_pad_attr[31].drive_strength.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[9]), + .q (reg2hw.dio_pad_attr[31].drive_strength.q), + .ds (), + .qs (dio_pad_attr_31_drive_strength_31_qs) + ); + assign reg2hw.dio_pad_attr[31].drive_strength.qe = dio_pad_attr_31_qe; + + + // Subregister 32 of Multireg dio_pad_attr + // R[dio_pad_attr_32]: V(True) + logic dio_pad_attr_32_qe; + logic [9:0] dio_pad_attr_32_flds_we; + assign dio_pad_attr_32_qe = &dio_pad_attr_32_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_32_gated_we; + assign dio_pad_attr_32_gated_we = dio_pad_attr_32_we & dio_pad_attr_regwen_32_qs; + // F[invert_32]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_invert_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_invert_32_wd), + .d (hw2reg.dio_pad_attr[32].invert.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[0]), + .q (reg2hw.dio_pad_attr[32].invert.q), + .ds (), + .qs (dio_pad_attr_32_invert_32_qs) + ); + assign reg2hw.dio_pad_attr[32].invert.qe = dio_pad_attr_32_qe; + + // F[virtual_od_en_32]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_virtual_od_en_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_virtual_od_en_32_wd), + .d (hw2reg.dio_pad_attr[32].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[1]), + .q (reg2hw.dio_pad_attr[32].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_32_virtual_od_en_32_qs) + ); + assign reg2hw.dio_pad_attr[32].virtual_od_en.qe = dio_pad_attr_32_qe; + + // F[pull_en_32]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_pull_en_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_pull_en_32_wd), + .d (hw2reg.dio_pad_attr[32].pull_en.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[2]), + .q (reg2hw.dio_pad_attr[32].pull_en.q), + .ds (), + .qs (dio_pad_attr_32_pull_en_32_qs) + ); + assign reg2hw.dio_pad_attr[32].pull_en.qe = dio_pad_attr_32_qe; + + // F[pull_select_32]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_pull_select_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_pull_select_32_wd), + .d (hw2reg.dio_pad_attr[32].pull_select.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[3]), + .q (reg2hw.dio_pad_attr[32].pull_select.q), + .ds (), + .qs (dio_pad_attr_32_pull_select_32_qs) + ); + assign reg2hw.dio_pad_attr[32].pull_select.qe = dio_pad_attr_32_qe; + + // F[keeper_en_32]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_keeper_en_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_keeper_en_32_wd), + .d (hw2reg.dio_pad_attr[32].keeper_en.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[4]), + .q (reg2hw.dio_pad_attr[32].keeper_en.q), + .ds (), + .qs (dio_pad_attr_32_keeper_en_32_qs) + ); + assign reg2hw.dio_pad_attr[32].keeper_en.qe = dio_pad_attr_32_qe; + + // F[schmitt_en_32]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_schmitt_en_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_schmitt_en_32_wd), + .d (hw2reg.dio_pad_attr[32].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[5]), + .q (reg2hw.dio_pad_attr[32].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_32_schmitt_en_32_qs) + ); + assign reg2hw.dio_pad_attr[32].schmitt_en.qe = dio_pad_attr_32_qe; + + // F[od_en_32]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_od_en_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_od_en_32_wd), + .d (hw2reg.dio_pad_attr[32].od_en.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[6]), + .q (reg2hw.dio_pad_attr[32].od_en.q), + .ds (), + .qs (dio_pad_attr_32_od_en_32_qs) + ); + assign reg2hw.dio_pad_attr[32].od_en.qe = dio_pad_attr_32_qe; + + // F[input_disable_32]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_input_disable_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_input_disable_32_wd), + .d (hw2reg.dio_pad_attr[32].input_disable.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[7]), + .q (reg2hw.dio_pad_attr[32].input_disable.q), + .ds (), + .qs (dio_pad_attr_32_input_disable_32_qs) + ); + assign reg2hw.dio_pad_attr[32].input_disable.qe = dio_pad_attr_32_qe; + + // F[slew_rate_32]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_32_slew_rate_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_slew_rate_32_wd), + .d (hw2reg.dio_pad_attr[32].slew_rate.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[8]), + .q (reg2hw.dio_pad_attr[32].slew_rate.q), + .ds (), + .qs (dio_pad_attr_32_slew_rate_32_qs) + ); + assign reg2hw.dio_pad_attr[32].slew_rate.qe = dio_pad_attr_32_qe; + + // F[drive_strength_32]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_32_drive_strength_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_drive_strength_32_wd), + .d (hw2reg.dio_pad_attr[32].drive_strength.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[9]), + .q (reg2hw.dio_pad_attr[32].drive_strength.q), + .ds (), + .qs (dio_pad_attr_32_drive_strength_32_qs) + ); + assign reg2hw.dio_pad_attr[32].drive_strength.qe = dio_pad_attr_32_qe; + + + // Subregister 33 of Multireg dio_pad_attr + // R[dio_pad_attr_33]: V(True) + logic dio_pad_attr_33_qe; + logic [9:0] dio_pad_attr_33_flds_we; + assign dio_pad_attr_33_qe = &dio_pad_attr_33_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_33_gated_we; + assign dio_pad_attr_33_gated_we = dio_pad_attr_33_we & dio_pad_attr_regwen_33_qs; + // F[invert_33]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_invert_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_invert_33_wd), + .d (hw2reg.dio_pad_attr[33].invert.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[0]), + .q (reg2hw.dio_pad_attr[33].invert.q), + .ds (), + .qs (dio_pad_attr_33_invert_33_qs) + ); + assign reg2hw.dio_pad_attr[33].invert.qe = dio_pad_attr_33_qe; + + // F[virtual_od_en_33]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_virtual_od_en_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_virtual_od_en_33_wd), + .d (hw2reg.dio_pad_attr[33].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[1]), + .q (reg2hw.dio_pad_attr[33].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_33_virtual_od_en_33_qs) + ); + assign reg2hw.dio_pad_attr[33].virtual_od_en.qe = dio_pad_attr_33_qe; + + // F[pull_en_33]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_pull_en_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_pull_en_33_wd), + .d (hw2reg.dio_pad_attr[33].pull_en.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[2]), + .q (reg2hw.dio_pad_attr[33].pull_en.q), + .ds (), + .qs (dio_pad_attr_33_pull_en_33_qs) + ); + assign reg2hw.dio_pad_attr[33].pull_en.qe = dio_pad_attr_33_qe; + + // F[pull_select_33]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_pull_select_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_pull_select_33_wd), + .d (hw2reg.dio_pad_attr[33].pull_select.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[3]), + .q (reg2hw.dio_pad_attr[33].pull_select.q), + .ds (), + .qs (dio_pad_attr_33_pull_select_33_qs) + ); + assign reg2hw.dio_pad_attr[33].pull_select.qe = dio_pad_attr_33_qe; + + // F[keeper_en_33]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_keeper_en_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_keeper_en_33_wd), + .d (hw2reg.dio_pad_attr[33].keeper_en.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[4]), + .q (reg2hw.dio_pad_attr[33].keeper_en.q), + .ds (), + .qs (dio_pad_attr_33_keeper_en_33_qs) + ); + assign reg2hw.dio_pad_attr[33].keeper_en.qe = dio_pad_attr_33_qe; + + // F[schmitt_en_33]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_schmitt_en_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_schmitt_en_33_wd), + .d (hw2reg.dio_pad_attr[33].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[5]), + .q (reg2hw.dio_pad_attr[33].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_33_schmitt_en_33_qs) + ); + assign reg2hw.dio_pad_attr[33].schmitt_en.qe = dio_pad_attr_33_qe; + + // F[od_en_33]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_od_en_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_od_en_33_wd), + .d (hw2reg.dio_pad_attr[33].od_en.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[6]), + .q (reg2hw.dio_pad_attr[33].od_en.q), + .ds (), + .qs (dio_pad_attr_33_od_en_33_qs) + ); + assign reg2hw.dio_pad_attr[33].od_en.qe = dio_pad_attr_33_qe; + + // F[input_disable_33]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_input_disable_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_input_disable_33_wd), + .d (hw2reg.dio_pad_attr[33].input_disable.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[7]), + .q (reg2hw.dio_pad_attr[33].input_disable.q), + .ds (), + .qs (dio_pad_attr_33_input_disable_33_qs) + ); + assign reg2hw.dio_pad_attr[33].input_disable.qe = dio_pad_attr_33_qe; + + // F[slew_rate_33]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_33_slew_rate_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_slew_rate_33_wd), + .d (hw2reg.dio_pad_attr[33].slew_rate.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[8]), + .q (reg2hw.dio_pad_attr[33].slew_rate.q), + .ds (), + .qs (dio_pad_attr_33_slew_rate_33_qs) + ); + assign reg2hw.dio_pad_attr[33].slew_rate.qe = dio_pad_attr_33_qe; + + // F[drive_strength_33]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_33_drive_strength_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_drive_strength_33_wd), + .d (hw2reg.dio_pad_attr[33].drive_strength.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[9]), + .q (reg2hw.dio_pad_attr[33].drive_strength.q), + .ds (), + .qs (dio_pad_attr_33_drive_strength_33_qs) + ); + assign reg2hw.dio_pad_attr[33].drive_strength.qe = dio_pad_attr_33_qe; + + + // Subregister 34 of Multireg dio_pad_attr + // R[dio_pad_attr_34]: V(True) + logic dio_pad_attr_34_qe; + logic [9:0] dio_pad_attr_34_flds_we; + assign dio_pad_attr_34_qe = &dio_pad_attr_34_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_34_gated_we; + assign dio_pad_attr_34_gated_we = dio_pad_attr_34_we & dio_pad_attr_regwen_34_qs; + // F[invert_34]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_invert_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_invert_34_wd), + .d (hw2reg.dio_pad_attr[34].invert.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[0]), + .q (reg2hw.dio_pad_attr[34].invert.q), + .ds (), + .qs (dio_pad_attr_34_invert_34_qs) + ); + assign reg2hw.dio_pad_attr[34].invert.qe = dio_pad_attr_34_qe; + + // F[virtual_od_en_34]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_virtual_od_en_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_virtual_od_en_34_wd), + .d (hw2reg.dio_pad_attr[34].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[1]), + .q (reg2hw.dio_pad_attr[34].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_34_virtual_od_en_34_qs) + ); + assign reg2hw.dio_pad_attr[34].virtual_od_en.qe = dio_pad_attr_34_qe; + + // F[pull_en_34]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_pull_en_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_pull_en_34_wd), + .d (hw2reg.dio_pad_attr[34].pull_en.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[2]), + .q (reg2hw.dio_pad_attr[34].pull_en.q), + .ds (), + .qs (dio_pad_attr_34_pull_en_34_qs) + ); + assign reg2hw.dio_pad_attr[34].pull_en.qe = dio_pad_attr_34_qe; + + // F[pull_select_34]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_pull_select_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_pull_select_34_wd), + .d (hw2reg.dio_pad_attr[34].pull_select.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[3]), + .q (reg2hw.dio_pad_attr[34].pull_select.q), + .ds (), + .qs (dio_pad_attr_34_pull_select_34_qs) + ); + assign reg2hw.dio_pad_attr[34].pull_select.qe = dio_pad_attr_34_qe; + + // F[keeper_en_34]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_keeper_en_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_keeper_en_34_wd), + .d (hw2reg.dio_pad_attr[34].keeper_en.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[4]), + .q (reg2hw.dio_pad_attr[34].keeper_en.q), + .ds (), + .qs (dio_pad_attr_34_keeper_en_34_qs) + ); + assign reg2hw.dio_pad_attr[34].keeper_en.qe = dio_pad_attr_34_qe; + + // F[schmitt_en_34]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_schmitt_en_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_schmitt_en_34_wd), + .d (hw2reg.dio_pad_attr[34].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[5]), + .q (reg2hw.dio_pad_attr[34].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_34_schmitt_en_34_qs) + ); + assign reg2hw.dio_pad_attr[34].schmitt_en.qe = dio_pad_attr_34_qe; + + // F[od_en_34]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_od_en_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_od_en_34_wd), + .d (hw2reg.dio_pad_attr[34].od_en.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[6]), + .q (reg2hw.dio_pad_attr[34].od_en.q), + .ds (), + .qs (dio_pad_attr_34_od_en_34_qs) + ); + assign reg2hw.dio_pad_attr[34].od_en.qe = dio_pad_attr_34_qe; + + // F[input_disable_34]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_input_disable_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_input_disable_34_wd), + .d (hw2reg.dio_pad_attr[34].input_disable.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[7]), + .q (reg2hw.dio_pad_attr[34].input_disable.q), + .ds (), + .qs (dio_pad_attr_34_input_disable_34_qs) + ); + assign reg2hw.dio_pad_attr[34].input_disable.qe = dio_pad_attr_34_qe; + + // F[slew_rate_34]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_34_slew_rate_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_slew_rate_34_wd), + .d (hw2reg.dio_pad_attr[34].slew_rate.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[8]), + .q (reg2hw.dio_pad_attr[34].slew_rate.q), + .ds (), + .qs (dio_pad_attr_34_slew_rate_34_qs) + ); + assign reg2hw.dio_pad_attr[34].slew_rate.qe = dio_pad_attr_34_qe; + + // F[drive_strength_34]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_34_drive_strength_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_drive_strength_34_wd), + .d (hw2reg.dio_pad_attr[34].drive_strength.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[9]), + .q (reg2hw.dio_pad_attr[34].drive_strength.q), + .ds (), + .qs (dio_pad_attr_34_drive_strength_34_qs) + ); + assign reg2hw.dio_pad_attr[34].drive_strength.qe = dio_pad_attr_34_qe; + + + // Subregister 35 of Multireg dio_pad_attr + // R[dio_pad_attr_35]: V(True) + logic dio_pad_attr_35_qe; + logic [9:0] dio_pad_attr_35_flds_we; + assign dio_pad_attr_35_qe = &dio_pad_attr_35_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_35_gated_we; + assign dio_pad_attr_35_gated_we = dio_pad_attr_35_we & dio_pad_attr_regwen_35_qs; + // F[invert_35]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_invert_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_invert_35_wd), + .d (hw2reg.dio_pad_attr[35].invert.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[0]), + .q (reg2hw.dio_pad_attr[35].invert.q), + .ds (), + .qs (dio_pad_attr_35_invert_35_qs) + ); + assign reg2hw.dio_pad_attr[35].invert.qe = dio_pad_attr_35_qe; + + // F[virtual_od_en_35]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_virtual_od_en_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_virtual_od_en_35_wd), + .d (hw2reg.dio_pad_attr[35].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[1]), + .q (reg2hw.dio_pad_attr[35].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_35_virtual_od_en_35_qs) + ); + assign reg2hw.dio_pad_attr[35].virtual_od_en.qe = dio_pad_attr_35_qe; + + // F[pull_en_35]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_pull_en_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_pull_en_35_wd), + .d (hw2reg.dio_pad_attr[35].pull_en.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[2]), + .q (reg2hw.dio_pad_attr[35].pull_en.q), + .ds (), + .qs (dio_pad_attr_35_pull_en_35_qs) + ); + assign reg2hw.dio_pad_attr[35].pull_en.qe = dio_pad_attr_35_qe; + + // F[pull_select_35]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_pull_select_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_pull_select_35_wd), + .d (hw2reg.dio_pad_attr[35].pull_select.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[3]), + .q (reg2hw.dio_pad_attr[35].pull_select.q), + .ds (), + .qs (dio_pad_attr_35_pull_select_35_qs) + ); + assign reg2hw.dio_pad_attr[35].pull_select.qe = dio_pad_attr_35_qe; + + // F[keeper_en_35]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_keeper_en_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_keeper_en_35_wd), + .d (hw2reg.dio_pad_attr[35].keeper_en.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[4]), + .q (reg2hw.dio_pad_attr[35].keeper_en.q), + .ds (), + .qs (dio_pad_attr_35_keeper_en_35_qs) + ); + assign reg2hw.dio_pad_attr[35].keeper_en.qe = dio_pad_attr_35_qe; + + // F[schmitt_en_35]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_schmitt_en_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_schmitt_en_35_wd), + .d (hw2reg.dio_pad_attr[35].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[5]), + .q (reg2hw.dio_pad_attr[35].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_35_schmitt_en_35_qs) + ); + assign reg2hw.dio_pad_attr[35].schmitt_en.qe = dio_pad_attr_35_qe; + + // F[od_en_35]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_od_en_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_od_en_35_wd), + .d (hw2reg.dio_pad_attr[35].od_en.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[6]), + .q (reg2hw.dio_pad_attr[35].od_en.q), + .ds (), + .qs (dio_pad_attr_35_od_en_35_qs) + ); + assign reg2hw.dio_pad_attr[35].od_en.qe = dio_pad_attr_35_qe; + + // F[input_disable_35]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_input_disable_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_input_disable_35_wd), + .d (hw2reg.dio_pad_attr[35].input_disable.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[7]), + .q (reg2hw.dio_pad_attr[35].input_disable.q), + .ds (), + .qs (dio_pad_attr_35_input_disable_35_qs) + ); + assign reg2hw.dio_pad_attr[35].input_disable.qe = dio_pad_attr_35_qe; + + // F[slew_rate_35]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_35_slew_rate_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_slew_rate_35_wd), + .d (hw2reg.dio_pad_attr[35].slew_rate.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[8]), + .q (reg2hw.dio_pad_attr[35].slew_rate.q), + .ds (), + .qs (dio_pad_attr_35_slew_rate_35_qs) + ); + assign reg2hw.dio_pad_attr[35].slew_rate.qe = dio_pad_attr_35_qe; + + // F[drive_strength_35]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_35_drive_strength_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_drive_strength_35_wd), + .d (hw2reg.dio_pad_attr[35].drive_strength.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[9]), + .q (reg2hw.dio_pad_attr[35].drive_strength.q), + .ds (), + .qs (dio_pad_attr_35_drive_strength_35_qs) + ); + assign reg2hw.dio_pad_attr[35].drive_strength.qe = dio_pad_attr_35_qe; + + + // Subregister 36 of Multireg dio_pad_attr + // R[dio_pad_attr_36]: V(True) + logic dio_pad_attr_36_qe; + logic [9:0] dio_pad_attr_36_flds_we; + assign dio_pad_attr_36_qe = &dio_pad_attr_36_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_36_gated_we; + assign dio_pad_attr_36_gated_we = dio_pad_attr_36_we & dio_pad_attr_regwen_36_qs; + // F[invert_36]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_invert_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_invert_36_wd), + .d (hw2reg.dio_pad_attr[36].invert.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[0]), + .q (reg2hw.dio_pad_attr[36].invert.q), + .ds (), + .qs (dio_pad_attr_36_invert_36_qs) + ); + assign reg2hw.dio_pad_attr[36].invert.qe = dio_pad_attr_36_qe; + + // F[virtual_od_en_36]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_virtual_od_en_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_virtual_od_en_36_wd), + .d (hw2reg.dio_pad_attr[36].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[1]), + .q (reg2hw.dio_pad_attr[36].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_36_virtual_od_en_36_qs) + ); + assign reg2hw.dio_pad_attr[36].virtual_od_en.qe = dio_pad_attr_36_qe; + + // F[pull_en_36]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_pull_en_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_pull_en_36_wd), + .d (hw2reg.dio_pad_attr[36].pull_en.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[2]), + .q (reg2hw.dio_pad_attr[36].pull_en.q), + .ds (), + .qs (dio_pad_attr_36_pull_en_36_qs) + ); + assign reg2hw.dio_pad_attr[36].pull_en.qe = dio_pad_attr_36_qe; + + // F[pull_select_36]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_pull_select_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_pull_select_36_wd), + .d (hw2reg.dio_pad_attr[36].pull_select.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[3]), + .q (reg2hw.dio_pad_attr[36].pull_select.q), + .ds (), + .qs (dio_pad_attr_36_pull_select_36_qs) + ); + assign reg2hw.dio_pad_attr[36].pull_select.qe = dio_pad_attr_36_qe; + + // F[keeper_en_36]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_keeper_en_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_keeper_en_36_wd), + .d (hw2reg.dio_pad_attr[36].keeper_en.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[4]), + .q (reg2hw.dio_pad_attr[36].keeper_en.q), + .ds (), + .qs (dio_pad_attr_36_keeper_en_36_qs) + ); + assign reg2hw.dio_pad_attr[36].keeper_en.qe = dio_pad_attr_36_qe; + + // F[schmitt_en_36]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_schmitt_en_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_schmitt_en_36_wd), + .d (hw2reg.dio_pad_attr[36].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[5]), + .q (reg2hw.dio_pad_attr[36].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_36_schmitt_en_36_qs) + ); + assign reg2hw.dio_pad_attr[36].schmitt_en.qe = dio_pad_attr_36_qe; + + // F[od_en_36]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_od_en_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_od_en_36_wd), + .d (hw2reg.dio_pad_attr[36].od_en.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[6]), + .q (reg2hw.dio_pad_attr[36].od_en.q), + .ds (), + .qs (dio_pad_attr_36_od_en_36_qs) + ); + assign reg2hw.dio_pad_attr[36].od_en.qe = dio_pad_attr_36_qe; + + // F[input_disable_36]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_input_disable_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_input_disable_36_wd), + .d (hw2reg.dio_pad_attr[36].input_disable.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[7]), + .q (reg2hw.dio_pad_attr[36].input_disable.q), + .ds (), + .qs (dio_pad_attr_36_input_disable_36_qs) + ); + assign reg2hw.dio_pad_attr[36].input_disable.qe = dio_pad_attr_36_qe; + + // F[slew_rate_36]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_36_slew_rate_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_slew_rate_36_wd), + .d (hw2reg.dio_pad_attr[36].slew_rate.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[8]), + .q (reg2hw.dio_pad_attr[36].slew_rate.q), + .ds (), + .qs (dio_pad_attr_36_slew_rate_36_qs) + ); + assign reg2hw.dio_pad_attr[36].slew_rate.qe = dio_pad_attr_36_qe; + + // F[drive_strength_36]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_36_drive_strength_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_drive_strength_36_wd), + .d (hw2reg.dio_pad_attr[36].drive_strength.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[9]), + .q (reg2hw.dio_pad_attr[36].drive_strength.q), + .ds (), + .qs (dio_pad_attr_36_drive_strength_36_qs) + ); + assign reg2hw.dio_pad_attr[36].drive_strength.qe = dio_pad_attr_36_qe; + + + // Subregister 37 of Multireg dio_pad_attr + // R[dio_pad_attr_37]: V(True) + logic dio_pad_attr_37_qe; + logic [9:0] dio_pad_attr_37_flds_we; + assign dio_pad_attr_37_qe = &dio_pad_attr_37_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_37_gated_we; + assign dio_pad_attr_37_gated_we = dio_pad_attr_37_we & dio_pad_attr_regwen_37_qs; + // F[invert_37]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_invert_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_invert_37_wd), + .d (hw2reg.dio_pad_attr[37].invert.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[0]), + .q (reg2hw.dio_pad_attr[37].invert.q), + .ds (), + .qs (dio_pad_attr_37_invert_37_qs) + ); + assign reg2hw.dio_pad_attr[37].invert.qe = dio_pad_attr_37_qe; + + // F[virtual_od_en_37]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_virtual_od_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_virtual_od_en_37_wd), + .d (hw2reg.dio_pad_attr[37].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[1]), + .q (reg2hw.dio_pad_attr[37].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_37_virtual_od_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].virtual_od_en.qe = dio_pad_attr_37_qe; + + // F[pull_en_37]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_pull_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_pull_en_37_wd), + .d (hw2reg.dio_pad_attr[37].pull_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[2]), + .q (reg2hw.dio_pad_attr[37].pull_en.q), + .ds (), + .qs (dio_pad_attr_37_pull_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].pull_en.qe = dio_pad_attr_37_qe; + + // F[pull_select_37]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_pull_select_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_pull_select_37_wd), + .d (hw2reg.dio_pad_attr[37].pull_select.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[3]), + .q (reg2hw.dio_pad_attr[37].pull_select.q), + .ds (), + .qs (dio_pad_attr_37_pull_select_37_qs) + ); + assign reg2hw.dio_pad_attr[37].pull_select.qe = dio_pad_attr_37_qe; + + // F[keeper_en_37]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_keeper_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_keeper_en_37_wd), + .d (hw2reg.dio_pad_attr[37].keeper_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[4]), + .q (reg2hw.dio_pad_attr[37].keeper_en.q), + .ds (), + .qs (dio_pad_attr_37_keeper_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].keeper_en.qe = dio_pad_attr_37_qe; + + // F[schmitt_en_37]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_schmitt_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_schmitt_en_37_wd), + .d (hw2reg.dio_pad_attr[37].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[5]), + .q (reg2hw.dio_pad_attr[37].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_37_schmitt_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].schmitt_en.qe = dio_pad_attr_37_qe; + + // F[od_en_37]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_od_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_od_en_37_wd), + .d (hw2reg.dio_pad_attr[37].od_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[6]), + .q (reg2hw.dio_pad_attr[37].od_en.q), + .ds (), + .qs (dio_pad_attr_37_od_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].od_en.qe = dio_pad_attr_37_qe; + + // F[input_disable_37]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_input_disable_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_input_disable_37_wd), + .d (hw2reg.dio_pad_attr[37].input_disable.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[7]), + .q (reg2hw.dio_pad_attr[37].input_disable.q), + .ds (), + .qs (dio_pad_attr_37_input_disable_37_qs) + ); + assign reg2hw.dio_pad_attr[37].input_disable.qe = dio_pad_attr_37_qe; + + // F[slew_rate_37]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_37_slew_rate_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_slew_rate_37_wd), + .d (hw2reg.dio_pad_attr[37].slew_rate.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[8]), + .q (reg2hw.dio_pad_attr[37].slew_rate.q), + .ds (), + .qs (dio_pad_attr_37_slew_rate_37_qs) + ); + assign reg2hw.dio_pad_attr[37].slew_rate.qe = dio_pad_attr_37_qe; + + // F[drive_strength_37]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_37_drive_strength_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_drive_strength_37_wd), + .d (hw2reg.dio_pad_attr[37].drive_strength.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[9]), + .q (reg2hw.dio_pad_attr[37].drive_strength.q), + .ds (), + .qs (dio_pad_attr_37_drive_strength_37_qs) + ); + assign reg2hw.dio_pad_attr[37].drive_strength.qe = dio_pad_attr_37_qe; + + + // Subregister 38 of Multireg dio_pad_attr + // R[dio_pad_attr_38]: V(True) + logic dio_pad_attr_38_qe; + logic [9:0] dio_pad_attr_38_flds_we; + assign dio_pad_attr_38_qe = &dio_pad_attr_38_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_38_gated_we; + assign dio_pad_attr_38_gated_we = dio_pad_attr_38_we & dio_pad_attr_regwen_38_qs; + // F[invert_38]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_invert_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_invert_38_wd), + .d (hw2reg.dio_pad_attr[38].invert.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[0]), + .q (reg2hw.dio_pad_attr[38].invert.q), + .ds (), + .qs (dio_pad_attr_38_invert_38_qs) + ); + assign reg2hw.dio_pad_attr[38].invert.qe = dio_pad_attr_38_qe; + + // F[virtual_od_en_38]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_virtual_od_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_virtual_od_en_38_wd), + .d (hw2reg.dio_pad_attr[38].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[1]), + .q (reg2hw.dio_pad_attr[38].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_38_virtual_od_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].virtual_od_en.qe = dio_pad_attr_38_qe; + + // F[pull_en_38]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_pull_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_pull_en_38_wd), + .d (hw2reg.dio_pad_attr[38].pull_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[2]), + .q (reg2hw.dio_pad_attr[38].pull_en.q), + .ds (), + .qs (dio_pad_attr_38_pull_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].pull_en.qe = dio_pad_attr_38_qe; + + // F[pull_select_38]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_pull_select_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_pull_select_38_wd), + .d (hw2reg.dio_pad_attr[38].pull_select.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[3]), + .q (reg2hw.dio_pad_attr[38].pull_select.q), + .ds (), + .qs (dio_pad_attr_38_pull_select_38_qs) + ); + assign reg2hw.dio_pad_attr[38].pull_select.qe = dio_pad_attr_38_qe; + + // F[keeper_en_38]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_keeper_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_keeper_en_38_wd), + .d (hw2reg.dio_pad_attr[38].keeper_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[4]), + .q (reg2hw.dio_pad_attr[38].keeper_en.q), + .ds (), + .qs (dio_pad_attr_38_keeper_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].keeper_en.qe = dio_pad_attr_38_qe; + + // F[schmitt_en_38]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_schmitt_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_schmitt_en_38_wd), + .d (hw2reg.dio_pad_attr[38].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[5]), + .q (reg2hw.dio_pad_attr[38].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_38_schmitt_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].schmitt_en.qe = dio_pad_attr_38_qe; + + // F[od_en_38]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_od_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_od_en_38_wd), + .d (hw2reg.dio_pad_attr[38].od_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[6]), + .q (reg2hw.dio_pad_attr[38].od_en.q), + .ds (), + .qs (dio_pad_attr_38_od_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].od_en.qe = dio_pad_attr_38_qe; + + // F[input_disable_38]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_input_disable_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_input_disable_38_wd), + .d (hw2reg.dio_pad_attr[38].input_disable.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[7]), + .q (reg2hw.dio_pad_attr[38].input_disable.q), + .ds (), + .qs (dio_pad_attr_38_input_disable_38_qs) + ); + assign reg2hw.dio_pad_attr[38].input_disable.qe = dio_pad_attr_38_qe; + + // F[slew_rate_38]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_38_slew_rate_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_slew_rate_38_wd), + .d (hw2reg.dio_pad_attr[38].slew_rate.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[8]), + .q (reg2hw.dio_pad_attr[38].slew_rate.q), + .ds (), + .qs (dio_pad_attr_38_slew_rate_38_qs) + ); + assign reg2hw.dio_pad_attr[38].slew_rate.qe = dio_pad_attr_38_qe; + + // F[drive_strength_38]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_38_drive_strength_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_drive_strength_38_wd), + .d (hw2reg.dio_pad_attr[38].drive_strength.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[9]), + .q (reg2hw.dio_pad_attr[38].drive_strength.q), + .ds (), + .qs (dio_pad_attr_38_drive_strength_38_qs) + ); + assign reg2hw.dio_pad_attr[38].drive_strength.qe = dio_pad_attr_38_qe; + + + // Subregister 39 of Multireg dio_pad_attr + // R[dio_pad_attr_39]: V(True) + logic dio_pad_attr_39_qe; + logic [9:0] dio_pad_attr_39_flds_we; + assign dio_pad_attr_39_qe = &dio_pad_attr_39_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_39_gated_we; + assign dio_pad_attr_39_gated_we = dio_pad_attr_39_we & dio_pad_attr_regwen_39_qs; + // F[invert_39]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_invert_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_invert_39_wd), + .d (hw2reg.dio_pad_attr[39].invert.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[0]), + .q (reg2hw.dio_pad_attr[39].invert.q), + .ds (), + .qs (dio_pad_attr_39_invert_39_qs) + ); + assign reg2hw.dio_pad_attr[39].invert.qe = dio_pad_attr_39_qe; + + // F[virtual_od_en_39]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_virtual_od_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_virtual_od_en_39_wd), + .d (hw2reg.dio_pad_attr[39].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[1]), + .q (reg2hw.dio_pad_attr[39].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_39_virtual_od_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].virtual_od_en.qe = dio_pad_attr_39_qe; + + // F[pull_en_39]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_pull_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_pull_en_39_wd), + .d (hw2reg.dio_pad_attr[39].pull_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[2]), + .q (reg2hw.dio_pad_attr[39].pull_en.q), + .ds (), + .qs (dio_pad_attr_39_pull_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].pull_en.qe = dio_pad_attr_39_qe; + + // F[pull_select_39]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_pull_select_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_pull_select_39_wd), + .d (hw2reg.dio_pad_attr[39].pull_select.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[3]), + .q (reg2hw.dio_pad_attr[39].pull_select.q), + .ds (), + .qs (dio_pad_attr_39_pull_select_39_qs) + ); + assign reg2hw.dio_pad_attr[39].pull_select.qe = dio_pad_attr_39_qe; + + // F[keeper_en_39]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_keeper_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_keeper_en_39_wd), + .d (hw2reg.dio_pad_attr[39].keeper_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[4]), + .q (reg2hw.dio_pad_attr[39].keeper_en.q), + .ds (), + .qs (dio_pad_attr_39_keeper_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].keeper_en.qe = dio_pad_attr_39_qe; + + // F[schmitt_en_39]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_schmitt_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_schmitt_en_39_wd), + .d (hw2reg.dio_pad_attr[39].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[5]), + .q (reg2hw.dio_pad_attr[39].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_39_schmitt_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].schmitt_en.qe = dio_pad_attr_39_qe; + + // F[od_en_39]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_od_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_od_en_39_wd), + .d (hw2reg.dio_pad_attr[39].od_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[6]), + .q (reg2hw.dio_pad_attr[39].od_en.q), + .ds (), + .qs (dio_pad_attr_39_od_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].od_en.qe = dio_pad_attr_39_qe; + + // F[input_disable_39]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_input_disable_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_input_disable_39_wd), + .d (hw2reg.dio_pad_attr[39].input_disable.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[7]), + .q (reg2hw.dio_pad_attr[39].input_disable.q), + .ds (), + .qs (dio_pad_attr_39_input_disable_39_qs) + ); + assign reg2hw.dio_pad_attr[39].input_disable.qe = dio_pad_attr_39_qe; + + // F[slew_rate_39]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_39_slew_rate_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_slew_rate_39_wd), + .d (hw2reg.dio_pad_attr[39].slew_rate.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[8]), + .q (reg2hw.dio_pad_attr[39].slew_rate.q), + .ds (), + .qs (dio_pad_attr_39_slew_rate_39_qs) + ); + assign reg2hw.dio_pad_attr[39].slew_rate.qe = dio_pad_attr_39_qe; + + // F[drive_strength_39]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_39_drive_strength_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_drive_strength_39_wd), + .d (hw2reg.dio_pad_attr[39].drive_strength.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[9]), + .q (reg2hw.dio_pad_attr[39].drive_strength.q), + .ds (), + .qs (dio_pad_attr_39_drive_strength_39_qs) + ); + assign reg2hw.dio_pad_attr[39].drive_strength.qe = dio_pad_attr_39_qe; + + + // Subregister 40 of Multireg dio_pad_attr + // R[dio_pad_attr_40]: V(True) + logic dio_pad_attr_40_qe; + logic [9:0] dio_pad_attr_40_flds_we; + assign dio_pad_attr_40_qe = &dio_pad_attr_40_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_40_gated_we; + assign dio_pad_attr_40_gated_we = dio_pad_attr_40_we & dio_pad_attr_regwen_40_qs; + // F[invert_40]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_invert_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_invert_40_wd), + .d (hw2reg.dio_pad_attr[40].invert.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[0]), + .q (reg2hw.dio_pad_attr[40].invert.q), + .ds (), + .qs (dio_pad_attr_40_invert_40_qs) + ); + assign reg2hw.dio_pad_attr[40].invert.qe = dio_pad_attr_40_qe; + + // F[virtual_od_en_40]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_virtual_od_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_virtual_od_en_40_wd), + .d (hw2reg.dio_pad_attr[40].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[1]), + .q (reg2hw.dio_pad_attr[40].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_40_virtual_od_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].virtual_od_en.qe = dio_pad_attr_40_qe; + + // F[pull_en_40]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_pull_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_pull_en_40_wd), + .d (hw2reg.dio_pad_attr[40].pull_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[2]), + .q (reg2hw.dio_pad_attr[40].pull_en.q), + .ds (), + .qs (dio_pad_attr_40_pull_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].pull_en.qe = dio_pad_attr_40_qe; + + // F[pull_select_40]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_pull_select_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_pull_select_40_wd), + .d (hw2reg.dio_pad_attr[40].pull_select.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[3]), + .q (reg2hw.dio_pad_attr[40].pull_select.q), + .ds (), + .qs (dio_pad_attr_40_pull_select_40_qs) + ); + assign reg2hw.dio_pad_attr[40].pull_select.qe = dio_pad_attr_40_qe; + + // F[keeper_en_40]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_keeper_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_keeper_en_40_wd), + .d (hw2reg.dio_pad_attr[40].keeper_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[4]), + .q (reg2hw.dio_pad_attr[40].keeper_en.q), + .ds (), + .qs (dio_pad_attr_40_keeper_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].keeper_en.qe = dio_pad_attr_40_qe; + + // F[schmitt_en_40]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_schmitt_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_schmitt_en_40_wd), + .d (hw2reg.dio_pad_attr[40].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[5]), + .q (reg2hw.dio_pad_attr[40].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_40_schmitt_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].schmitt_en.qe = dio_pad_attr_40_qe; + + // F[od_en_40]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_od_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_od_en_40_wd), + .d (hw2reg.dio_pad_attr[40].od_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[6]), + .q (reg2hw.dio_pad_attr[40].od_en.q), + .ds (), + .qs (dio_pad_attr_40_od_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].od_en.qe = dio_pad_attr_40_qe; + + // F[input_disable_40]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_input_disable_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_input_disable_40_wd), + .d (hw2reg.dio_pad_attr[40].input_disable.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[7]), + .q (reg2hw.dio_pad_attr[40].input_disable.q), + .ds (), + .qs (dio_pad_attr_40_input_disable_40_qs) + ); + assign reg2hw.dio_pad_attr[40].input_disable.qe = dio_pad_attr_40_qe; + + // F[slew_rate_40]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_40_slew_rate_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_slew_rate_40_wd), + .d (hw2reg.dio_pad_attr[40].slew_rate.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[8]), + .q (reg2hw.dio_pad_attr[40].slew_rate.q), + .ds (), + .qs (dio_pad_attr_40_slew_rate_40_qs) + ); + assign reg2hw.dio_pad_attr[40].slew_rate.qe = dio_pad_attr_40_qe; + + // F[drive_strength_40]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_40_drive_strength_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_drive_strength_40_wd), + .d (hw2reg.dio_pad_attr[40].drive_strength.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[9]), + .q (reg2hw.dio_pad_attr[40].drive_strength.q), + .ds (), + .qs (dio_pad_attr_40_drive_strength_40_qs) + ); + assign reg2hw.dio_pad_attr[40].drive_strength.qe = dio_pad_attr_40_qe; + + + // Subregister 41 of Multireg dio_pad_attr + // R[dio_pad_attr_41]: V(True) + logic dio_pad_attr_41_qe; + logic [9:0] dio_pad_attr_41_flds_we; + assign dio_pad_attr_41_qe = &dio_pad_attr_41_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_41_gated_we; + assign dio_pad_attr_41_gated_we = dio_pad_attr_41_we & dio_pad_attr_regwen_41_qs; + // F[invert_41]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_invert_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_invert_41_wd), + .d (hw2reg.dio_pad_attr[41].invert.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[0]), + .q (reg2hw.dio_pad_attr[41].invert.q), + .ds (), + .qs (dio_pad_attr_41_invert_41_qs) + ); + assign reg2hw.dio_pad_attr[41].invert.qe = dio_pad_attr_41_qe; + + // F[virtual_od_en_41]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_virtual_od_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_virtual_od_en_41_wd), + .d (hw2reg.dio_pad_attr[41].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[1]), + .q (reg2hw.dio_pad_attr[41].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_41_virtual_od_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].virtual_od_en.qe = dio_pad_attr_41_qe; + + // F[pull_en_41]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_pull_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_pull_en_41_wd), + .d (hw2reg.dio_pad_attr[41].pull_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[2]), + .q (reg2hw.dio_pad_attr[41].pull_en.q), + .ds (), + .qs (dio_pad_attr_41_pull_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].pull_en.qe = dio_pad_attr_41_qe; + + // F[pull_select_41]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_pull_select_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_pull_select_41_wd), + .d (hw2reg.dio_pad_attr[41].pull_select.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[3]), + .q (reg2hw.dio_pad_attr[41].pull_select.q), + .ds (), + .qs (dio_pad_attr_41_pull_select_41_qs) + ); + assign reg2hw.dio_pad_attr[41].pull_select.qe = dio_pad_attr_41_qe; + + // F[keeper_en_41]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_keeper_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_keeper_en_41_wd), + .d (hw2reg.dio_pad_attr[41].keeper_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[4]), + .q (reg2hw.dio_pad_attr[41].keeper_en.q), + .ds (), + .qs (dio_pad_attr_41_keeper_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].keeper_en.qe = dio_pad_attr_41_qe; + + // F[schmitt_en_41]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_schmitt_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_schmitt_en_41_wd), + .d (hw2reg.dio_pad_attr[41].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[5]), + .q (reg2hw.dio_pad_attr[41].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_41_schmitt_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].schmitt_en.qe = dio_pad_attr_41_qe; + + // F[od_en_41]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_od_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_od_en_41_wd), + .d (hw2reg.dio_pad_attr[41].od_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[6]), + .q (reg2hw.dio_pad_attr[41].od_en.q), + .ds (), + .qs (dio_pad_attr_41_od_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].od_en.qe = dio_pad_attr_41_qe; + + // F[input_disable_41]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_input_disable_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_input_disable_41_wd), + .d (hw2reg.dio_pad_attr[41].input_disable.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[7]), + .q (reg2hw.dio_pad_attr[41].input_disable.q), + .ds (), + .qs (dio_pad_attr_41_input_disable_41_qs) + ); + assign reg2hw.dio_pad_attr[41].input_disable.qe = dio_pad_attr_41_qe; + + // F[slew_rate_41]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_41_slew_rate_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_slew_rate_41_wd), + .d (hw2reg.dio_pad_attr[41].slew_rate.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[8]), + .q (reg2hw.dio_pad_attr[41].slew_rate.q), + .ds (), + .qs (dio_pad_attr_41_slew_rate_41_qs) + ); + assign reg2hw.dio_pad_attr[41].slew_rate.qe = dio_pad_attr_41_qe; + + // F[drive_strength_41]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_41_drive_strength_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_drive_strength_41_wd), + .d (hw2reg.dio_pad_attr[41].drive_strength.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[9]), + .q (reg2hw.dio_pad_attr[41].drive_strength.q), + .ds (), + .qs (dio_pad_attr_41_drive_strength_41_qs) + ); + assign reg2hw.dio_pad_attr[41].drive_strength.qe = dio_pad_attr_41_qe; + + + // Subregister 42 of Multireg dio_pad_attr + // R[dio_pad_attr_42]: V(True) + logic dio_pad_attr_42_qe; + logic [9:0] dio_pad_attr_42_flds_we; + assign dio_pad_attr_42_qe = &dio_pad_attr_42_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_42_gated_we; + assign dio_pad_attr_42_gated_we = dio_pad_attr_42_we & dio_pad_attr_regwen_42_qs; + // F[invert_42]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_invert_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_invert_42_wd), + .d (hw2reg.dio_pad_attr[42].invert.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[0]), + .q (reg2hw.dio_pad_attr[42].invert.q), + .ds (), + .qs (dio_pad_attr_42_invert_42_qs) + ); + assign reg2hw.dio_pad_attr[42].invert.qe = dio_pad_attr_42_qe; + + // F[virtual_od_en_42]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_virtual_od_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_virtual_od_en_42_wd), + .d (hw2reg.dio_pad_attr[42].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[1]), + .q (reg2hw.dio_pad_attr[42].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_42_virtual_od_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].virtual_od_en.qe = dio_pad_attr_42_qe; + + // F[pull_en_42]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_pull_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_pull_en_42_wd), + .d (hw2reg.dio_pad_attr[42].pull_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[2]), + .q (reg2hw.dio_pad_attr[42].pull_en.q), + .ds (), + .qs (dio_pad_attr_42_pull_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].pull_en.qe = dio_pad_attr_42_qe; + + // F[pull_select_42]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_pull_select_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_pull_select_42_wd), + .d (hw2reg.dio_pad_attr[42].pull_select.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[3]), + .q (reg2hw.dio_pad_attr[42].pull_select.q), + .ds (), + .qs (dio_pad_attr_42_pull_select_42_qs) + ); + assign reg2hw.dio_pad_attr[42].pull_select.qe = dio_pad_attr_42_qe; + + // F[keeper_en_42]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_keeper_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_keeper_en_42_wd), + .d (hw2reg.dio_pad_attr[42].keeper_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[4]), + .q (reg2hw.dio_pad_attr[42].keeper_en.q), + .ds (), + .qs (dio_pad_attr_42_keeper_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].keeper_en.qe = dio_pad_attr_42_qe; + + // F[schmitt_en_42]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_schmitt_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_schmitt_en_42_wd), + .d (hw2reg.dio_pad_attr[42].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[5]), + .q (reg2hw.dio_pad_attr[42].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_42_schmitt_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].schmitt_en.qe = dio_pad_attr_42_qe; + + // F[od_en_42]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_od_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_od_en_42_wd), + .d (hw2reg.dio_pad_attr[42].od_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[6]), + .q (reg2hw.dio_pad_attr[42].od_en.q), + .ds (), + .qs (dio_pad_attr_42_od_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].od_en.qe = dio_pad_attr_42_qe; + + // F[input_disable_42]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_input_disable_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_input_disable_42_wd), + .d (hw2reg.dio_pad_attr[42].input_disable.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[7]), + .q (reg2hw.dio_pad_attr[42].input_disable.q), + .ds (), + .qs (dio_pad_attr_42_input_disable_42_qs) + ); + assign reg2hw.dio_pad_attr[42].input_disable.qe = dio_pad_attr_42_qe; + + // F[slew_rate_42]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_42_slew_rate_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_slew_rate_42_wd), + .d (hw2reg.dio_pad_attr[42].slew_rate.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[8]), + .q (reg2hw.dio_pad_attr[42].slew_rate.q), + .ds (), + .qs (dio_pad_attr_42_slew_rate_42_qs) + ); + assign reg2hw.dio_pad_attr[42].slew_rate.qe = dio_pad_attr_42_qe; + + // F[drive_strength_42]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_42_drive_strength_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_drive_strength_42_wd), + .d (hw2reg.dio_pad_attr[42].drive_strength.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[9]), + .q (reg2hw.dio_pad_attr[42].drive_strength.q), + .ds (), + .qs (dio_pad_attr_42_drive_strength_42_qs) + ); + assign reg2hw.dio_pad_attr[42].drive_strength.qe = dio_pad_attr_42_qe; + + + // Subregister 43 of Multireg dio_pad_attr + // R[dio_pad_attr_43]: V(True) + logic dio_pad_attr_43_qe; + logic [9:0] dio_pad_attr_43_flds_we; + assign dio_pad_attr_43_qe = &dio_pad_attr_43_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_43_gated_we; + assign dio_pad_attr_43_gated_we = dio_pad_attr_43_we & dio_pad_attr_regwen_43_qs; + // F[invert_43]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_invert_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_invert_43_wd), + .d (hw2reg.dio_pad_attr[43].invert.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[0]), + .q (reg2hw.dio_pad_attr[43].invert.q), + .ds (), + .qs (dio_pad_attr_43_invert_43_qs) + ); + assign reg2hw.dio_pad_attr[43].invert.qe = dio_pad_attr_43_qe; + + // F[virtual_od_en_43]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_virtual_od_en_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_virtual_od_en_43_wd), + .d (hw2reg.dio_pad_attr[43].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[1]), + .q (reg2hw.dio_pad_attr[43].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_43_virtual_od_en_43_qs) + ); + assign reg2hw.dio_pad_attr[43].virtual_od_en.qe = dio_pad_attr_43_qe; + + // F[pull_en_43]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_pull_en_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_pull_en_43_wd), + .d (hw2reg.dio_pad_attr[43].pull_en.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[2]), + .q (reg2hw.dio_pad_attr[43].pull_en.q), + .ds (), + .qs (dio_pad_attr_43_pull_en_43_qs) + ); + assign reg2hw.dio_pad_attr[43].pull_en.qe = dio_pad_attr_43_qe; + + // F[pull_select_43]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_pull_select_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_pull_select_43_wd), + .d (hw2reg.dio_pad_attr[43].pull_select.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[3]), + .q (reg2hw.dio_pad_attr[43].pull_select.q), + .ds (), + .qs (dio_pad_attr_43_pull_select_43_qs) + ); + assign reg2hw.dio_pad_attr[43].pull_select.qe = dio_pad_attr_43_qe; + + // F[keeper_en_43]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_keeper_en_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_keeper_en_43_wd), + .d (hw2reg.dio_pad_attr[43].keeper_en.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[4]), + .q (reg2hw.dio_pad_attr[43].keeper_en.q), + .ds (), + .qs (dio_pad_attr_43_keeper_en_43_qs) + ); + assign reg2hw.dio_pad_attr[43].keeper_en.qe = dio_pad_attr_43_qe; + + // F[schmitt_en_43]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_schmitt_en_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_schmitt_en_43_wd), + .d (hw2reg.dio_pad_attr[43].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[5]), + .q (reg2hw.dio_pad_attr[43].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_43_schmitt_en_43_qs) + ); + assign reg2hw.dio_pad_attr[43].schmitt_en.qe = dio_pad_attr_43_qe; + + // F[od_en_43]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_od_en_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_od_en_43_wd), + .d (hw2reg.dio_pad_attr[43].od_en.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[6]), + .q (reg2hw.dio_pad_attr[43].od_en.q), + .ds (), + .qs (dio_pad_attr_43_od_en_43_qs) + ); + assign reg2hw.dio_pad_attr[43].od_en.qe = dio_pad_attr_43_qe; + + // F[input_disable_43]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_input_disable_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_input_disable_43_wd), + .d (hw2reg.dio_pad_attr[43].input_disable.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[7]), + .q (reg2hw.dio_pad_attr[43].input_disable.q), + .ds (), + .qs (dio_pad_attr_43_input_disable_43_qs) + ); + assign reg2hw.dio_pad_attr[43].input_disable.qe = dio_pad_attr_43_qe; + + // F[slew_rate_43]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_43_slew_rate_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_slew_rate_43_wd), + .d (hw2reg.dio_pad_attr[43].slew_rate.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[8]), + .q (reg2hw.dio_pad_attr[43].slew_rate.q), + .ds (), + .qs (dio_pad_attr_43_slew_rate_43_qs) + ); + assign reg2hw.dio_pad_attr[43].slew_rate.qe = dio_pad_attr_43_qe; + + // F[drive_strength_43]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_43_drive_strength_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_drive_strength_43_wd), + .d (hw2reg.dio_pad_attr[43].drive_strength.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[9]), + .q (reg2hw.dio_pad_attr[43].drive_strength.q), + .ds (), + .qs (dio_pad_attr_43_drive_strength_43_qs) + ); + assign reg2hw.dio_pad_attr[43].drive_strength.qe = dio_pad_attr_43_qe; + + + // Subregister 44 of Multireg dio_pad_attr + // R[dio_pad_attr_44]: V(True) + logic dio_pad_attr_44_qe; + logic [9:0] dio_pad_attr_44_flds_we; + assign dio_pad_attr_44_qe = &dio_pad_attr_44_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_44_gated_we; + assign dio_pad_attr_44_gated_we = dio_pad_attr_44_we & dio_pad_attr_regwen_44_qs; + // F[invert_44]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_invert_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_invert_44_wd), + .d (hw2reg.dio_pad_attr[44].invert.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[0]), + .q (reg2hw.dio_pad_attr[44].invert.q), + .ds (), + .qs (dio_pad_attr_44_invert_44_qs) + ); + assign reg2hw.dio_pad_attr[44].invert.qe = dio_pad_attr_44_qe; + + // F[virtual_od_en_44]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_virtual_od_en_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_virtual_od_en_44_wd), + .d (hw2reg.dio_pad_attr[44].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[1]), + .q (reg2hw.dio_pad_attr[44].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_44_virtual_od_en_44_qs) + ); + assign reg2hw.dio_pad_attr[44].virtual_od_en.qe = dio_pad_attr_44_qe; + + // F[pull_en_44]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_pull_en_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_pull_en_44_wd), + .d (hw2reg.dio_pad_attr[44].pull_en.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[2]), + .q (reg2hw.dio_pad_attr[44].pull_en.q), + .ds (), + .qs (dio_pad_attr_44_pull_en_44_qs) + ); + assign reg2hw.dio_pad_attr[44].pull_en.qe = dio_pad_attr_44_qe; + + // F[pull_select_44]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_pull_select_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_pull_select_44_wd), + .d (hw2reg.dio_pad_attr[44].pull_select.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[3]), + .q (reg2hw.dio_pad_attr[44].pull_select.q), + .ds (), + .qs (dio_pad_attr_44_pull_select_44_qs) + ); + assign reg2hw.dio_pad_attr[44].pull_select.qe = dio_pad_attr_44_qe; + + // F[keeper_en_44]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_keeper_en_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_keeper_en_44_wd), + .d (hw2reg.dio_pad_attr[44].keeper_en.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[4]), + .q (reg2hw.dio_pad_attr[44].keeper_en.q), + .ds (), + .qs (dio_pad_attr_44_keeper_en_44_qs) + ); + assign reg2hw.dio_pad_attr[44].keeper_en.qe = dio_pad_attr_44_qe; + + // F[schmitt_en_44]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_schmitt_en_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_schmitt_en_44_wd), + .d (hw2reg.dio_pad_attr[44].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[5]), + .q (reg2hw.dio_pad_attr[44].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_44_schmitt_en_44_qs) + ); + assign reg2hw.dio_pad_attr[44].schmitt_en.qe = dio_pad_attr_44_qe; + + // F[od_en_44]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_od_en_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_od_en_44_wd), + .d (hw2reg.dio_pad_attr[44].od_en.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[6]), + .q (reg2hw.dio_pad_attr[44].od_en.q), + .ds (), + .qs (dio_pad_attr_44_od_en_44_qs) + ); + assign reg2hw.dio_pad_attr[44].od_en.qe = dio_pad_attr_44_qe; + + // F[input_disable_44]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_input_disable_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_input_disable_44_wd), + .d (hw2reg.dio_pad_attr[44].input_disable.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[7]), + .q (reg2hw.dio_pad_attr[44].input_disable.q), + .ds (), + .qs (dio_pad_attr_44_input_disable_44_qs) + ); + assign reg2hw.dio_pad_attr[44].input_disable.qe = dio_pad_attr_44_qe; + + // F[slew_rate_44]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_44_slew_rate_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_slew_rate_44_wd), + .d (hw2reg.dio_pad_attr[44].slew_rate.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[8]), + .q (reg2hw.dio_pad_attr[44].slew_rate.q), + .ds (), + .qs (dio_pad_attr_44_slew_rate_44_qs) + ); + assign reg2hw.dio_pad_attr[44].slew_rate.qe = dio_pad_attr_44_qe; + + // F[drive_strength_44]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_44_drive_strength_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_drive_strength_44_wd), + .d (hw2reg.dio_pad_attr[44].drive_strength.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[9]), + .q (reg2hw.dio_pad_attr[44].drive_strength.q), + .ds (), + .qs (dio_pad_attr_44_drive_strength_44_qs) + ); + assign reg2hw.dio_pad_attr[44].drive_strength.qe = dio_pad_attr_44_qe; + + + // Subregister 45 of Multireg dio_pad_attr + // R[dio_pad_attr_45]: V(True) + logic dio_pad_attr_45_qe; + logic [9:0] dio_pad_attr_45_flds_we; + assign dio_pad_attr_45_qe = &dio_pad_attr_45_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_45_gated_we; + assign dio_pad_attr_45_gated_we = dio_pad_attr_45_we & dio_pad_attr_regwen_45_qs; + // F[invert_45]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_invert_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_invert_45_wd), + .d (hw2reg.dio_pad_attr[45].invert.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[0]), + .q (reg2hw.dio_pad_attr[45].invert.q), + .ds (), + .qs (dio_pad_attr_45_invert_45_qs) + ); + assign reg2hw.dio_pad_attr[45].invert.qe = dio_pad_attr_45_qe; + + // F[virtual_od_en_45]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_virtual_od_en_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_virtual_od_en_45_wd), + .d (hw2reg.dio_pad_attr[45].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[1]), + .q (reg2hw.dio_pad_attr[45].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_45_virtual_od_en_45_qs) + ); + assign reg2hw.dio_pad_attr[45].virtual_od_en.qe = dio_pad_attr_45_qe; + + // F[pull_en_45]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_pull_en_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_pull_en_45_wd), + .d (hw2reg.dio_pad_attr[45].pull_en.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[2]), + .q (reg2hw.dio_pad_attr[45].pull_en.q), + .ds (), + .qs (dio_pad_attr_45_pull_en_45_qs) + ); + assign reg2hw.dio_pad_attr[45].pull_en.qe = dio_pad_attr_45_qe; + + // F[pull_select_45]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_pull_select_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_pull_select_45_wd), + .d (hw2reg.dio_pad_attr[45].pull_select.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[3]), + .q (reg2hw.dio_pad_attr[45].pull_select.q), + .ds (), + .qs (dio_pad_attr_45_pull_select_45_qs) + ); + assign reg2hw.dio_pad_attr[45].pull_select.qe = dio_pad_attr_45_qe; + + // F[keeper_en_45]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_keeper_en_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_keeper_en_45_wd), + .d (hw2reg.dio_pad_attr[45].keeper_en.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[4]), + .q (reg2hw.dio_pad_attr[45].keeper_en.q), + .ds (), + .qs (dio_pad_attr_45_keeper_en_45_qs) + ); + assign reg2hw.dio_pad_attr[45].keeper_en.qe = dio_pad_attr_45_qe; + + // F[schmitt_en_45]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_schmitt_en_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_schmitt_en_45_wd), + .d (hw2reg.dio_pad_attr[45].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[5]), + .q (reg2hw.dio_pad_attr[45].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_45_schmitt_en_45_qs) + ); + assign reg2hw.dio_pad_attr[45].schmitt_en.qe = dio_pad_attr_45_qe; + + // F[od_en_45]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_od_en_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_od_en_45_wd), + .d (hw2reg.dio_pad_attr[45].od_en.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[6]), + .q (reg2hw.dio_pad_attr[45].od_en.q), + .ds (), + .qs (dio_pad_attr_45_od_en_45_qs) + ); + assign reg2hw.dio_pad_attr[45].od_en.qe = dio_pad_attr_45_qe; + + // F[input_disable_45]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_input_disable_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_input_disable_45_wd), + .d (hw2reg.dio_pad_attr[45].input_disable.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[7]), + .q (reg2hw.dio_pad_attr[45].input_disable.q), + .ds (), + .qs (dio_pad_attr_45_input_disable_45_qs) + ); + assign reg2hw.dio_pad_attr[45].input_disable.qe = dio_pad_attr_45_qe; + + // F[slew_rate_45]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_45_slew_rate_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_slew_rate_45_wd), + .d (hw2reg.dio_pad_attr[45].slew_rate.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[8]), + .q (reg2hw.dio_pad_attr[45].slew_rate.q), + .ds (), + .qs (dio_pad_attr_45_slew_rate_45_qs) + ); + assign reg2hw.dio_pad_attr[45].slew_rate.qe = dio_pad_attr_45_qe; + + // F[drive_strength_45]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_45_drive_strength_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_drive_strength_45_wd), + .d (hw2reg.dio_pad_attr[45].drive_strength.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[9]), + .q (reg2hw.dio_pad_attr[45].drive_strength.q), + .ds (), + .qs (dio_pad_attr_45_drive_strength_45_qs) + ); + assign reg2hw.dio_pad_attr[45].drive_strength.qe = dio_pad_attr_45_qe; + + + // Subregister 46 of Multireg dio_pad_attr + // R[dio_pad_attr_46]: V(True) + logic dio_pad_attr_46_qe; + logic [9:0] dio_pad_attr_46_flds_we; + assign dio_pad_attr_46_qe = &dio_pad_attr_46_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_46_gated_we; + assign dio_pad_attr_46_gated_we = dio_pad_attr_46_we & dio_pad_attr_regwen_46_qs; + // F[invert_46]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_invert_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_invert_46_wd), + .d (hw2reg.dio_pad_attr[46].invert.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[0]), + .q (reg2hw.dio_pad_attr[46].invert.q), + .ds (), + .qs (dio_pad_attr_46_invert_46_qs) + ); + assign reg2hw.dio_pad_attr[46].invert.qe = dio_pad_attr_46_qe; + + // F[virtual_od_en_46]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_virtual_od_en_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_virtual_od_en_46_wd), + .d (hw2reg.dio_pad_attr[46].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[1]), + .q (reg2hw.dio_pad_attr[46].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_46_virtual_od_en_46_qs) + ); + assign reg2hw.dio_pad_attr[46].virtual_od_en.qe = dio_pad_attr_46_qe; + + // F[pull_en_46]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_pull_en_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_pull_en_46_wd), + .d (hw2reg.dio_pad_attr[46].pull_en.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[2]), + .q (reg2hw.dio_pad_attr[46].pull_en.q), + .ds (), + .qs (dio_pad_attr_46_pull_en_46_qs) + ); + assign reg2hw.dio_pad_attr[46].pull_en.qe = dio_pad_attr_46_qe; + + // F[pull_select_46]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_pull_select_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_pull_select_46_wd), + .d (hw2reg.dio_pad_attr[46].pull_select.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[3]), + .q (reg2hw.dio_pad_attr[46].pull_select.q), + .ds (), + .qs (dio_pad_attr_46_pull_select_46_qs) + ); + assign reg2hw.dio_pad_attr[46].pull_select.qe = dio_pad_attr_46_qe; + + // F[keeper_en_46]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_keeper_en_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_keeper_en_46_wd), + .d (hw2reg.dio_pad_attr[46].keeper_en.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[4]), + .q (reg2hw.dio_pad_attr[46].keeper_en.q), + .ds (), + .qs (dio_pad_attr_46_keeper_en_46_qs) + ); + assign reg2hw.dio_pad_attr[46].keeper_en.qe = dio_pad_attr_46_qe; + + // F[schmitt_en_46]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_schmitt_en_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_schmitt_en_46_wd), + .d (hw2reg.dio_pad_attr[46].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[5]), + .q (reg2hw.dio_pad_attr[46].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_46_schmitt_en_46_qs) + ); + assign reg2hw.dio_pad_attr[46].schmitt_en.qe = dio_pad_attr_46_qe; + + // F[od_en_46]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_od_en_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_od_en_46_wd), + .d (hw2reg.dio_pad_attr[46].od_en.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[6]), + .q (reg2hw.dio_pad_attr[46].od_en.q), + .ds (), + .qs (dio_pad_attr_46_od_en_46_qs) + ); + assign reg2hw.dio_pad_attr[46].od_en.qe = dio_pad_attr_46_qe; + + // F[input_disable_46]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_input_disable_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_input_disable_46_wd), + .d (hw2reg.dio_pad_attr[46].input_disable.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[7]), + .q (reg2hw.dio_pad_attr[46].input_disable.q), + .ds (), + .qs (dio_pad_attr_46_input_disable_46_qs) + ); + assign reg2hw.dio_pad_attr[46].input_disable.qe = dio_pad_attr_46_qe; + + // F[slew_rate_46]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_46_slew_rate_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_slew_rate_46_wd), + .d (hw2reg.dio_pad_attr[46].slew_rate.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[8]), + .q (reg2hw.dio_pad_attr[46].slew_rate.q), + .ds (), + .qs (dio_pad_attr_46_slew_rate_46_qs) + ); + assign reg2hw.dio_pad_attr[46].slew_rate.qe = dio_pad_attr_46_qe; + + // F[drive_strength_46]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_46_drive_strength_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_drive_strength_46_wd), + .d (hw2reg.dio_pad_attr[46].drive_strength.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[9]), + .q (reg2hw.dio_pad_attr[46].drive_strength.q), + .ds (), + .qs (dio_pad_attr_46_drive_strength_46_qs) + ); + assign reg2hw.dio_pad_attr[46].drive_strength.qe = dio_pad_attr_46_qe; + + + // Subregister 47 of Multireg dio_pad_attr + // R[dio_pad_attr_47]: V(True) + logic dio_pad_attr_47_qe; + logic [9:0] dio_pad_attr_47_flds_we; + assign dio_pad_attr_47_qe = &dio_pad_attr_47_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_47_gated_we; + assign dio_pad_attr_47_gated_we = dio_pad_attr_47_we & dio_pad_attr_regwen_47_qs; + // F[invert_47]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_invert_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_invert_47_wd), + .d (hw2reg.dio_pad_attr[47].invert.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[0]), + .q (reg2hw.dio_pad_attr[47].invert.q), + .ds (), + .qs (dio_pad_attr_47_invert_47_qs) + ); + assign reg2hw.dio_pad_attr[47].invert.qe = dio_pad_attr_47_qe; + + // F[virtual_od_en_47]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_virtual_od_en_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_virtual_od_en_47_wd), + .d (hw2reg.dio_pad_attr[47].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[1]), + .q (reg2hw.dio_pad_attr[47].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_47_virtual_od_en_47_qs) + ); + assign reg2hw.dio_pad_attr[47].virtual_od_en.qe = dio_pad_attr_47_qe; + + // F[pull_en_47]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_pull_en_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_pull_en_47_wd), + .d (hw2reg.dio_pad_attr[47].pull_en.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[2]), + .q (reg2hw.dio_pad_attr[47].pull_en.q), + .ds (), + .qs (dio_pad_attr_47_pull_en_47_qs) + ); + assign reg2hw.dio_pad_attr[47].pull_en.qe = dio_pad_attr_47_qe; + + // F[pull_select_47]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_pull_select_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_pull_select_47_wd), + .d (hw2reg.dio_pad_attr[47].pull_select.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[3]), + .q (reg2hw.dio_pad_attr[47].pull_select.q), + .ds (), + .qs (dio_pad_attr_47_pull_select_47_qs) + ); + assign reg2hw.dio_pad_attr[47].pull_select.qe = dio_pad_attr_47_qe; + + // F[keeper_en_47]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_keeper_en_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_keeper_en_47_wd), + .d (hw2reg.dio_pad_attr[47].keeper_en.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[4]), + .q (reg2hw.dio_pad_attr[47].keeper_en.q), + .ds (), + .qs (dio_pad_attr_47_keeper_en_47_qs) + ); + assign reg2hw.dio_pad_attr[47].keeper_en.qe = dio_pad_attr_47_qe; + + // F[schmitt_en_47]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_schmitt_en_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_schmitt_en_47_wd), + .d (hw2reg.dio_pad_attr[47].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[5]), + .q (reg2hw.dio_pad_attr[47].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_47_schmitt_en_47_qs) + ); + assign reg2hw.dio_pad_attr[47].schmitt_en.qe = dio_pad_attr_47_qe; + + // F[od_en_47]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_od_en_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_od_en_47_wd), + .d (hw2reg.dio_pad_attr[47].od_en.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[6]), + .q (reg2hw.dio_pad_attr[47].od_en.q), + .ds (), + .qs (dio_pad_attr_47_od_en_47_qs) + ); + assign reg2hw.dio_pad_attr[47].od_en.qe = dio_pad_attr_47_qe; + + // F[input_disable_47]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_input_disable_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_input_disable_47_wd), + .d (hw2reg.dio_pad_attr[47].input_disable.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[7]), + .q (reg2hw.dio_pad_attr[47].input_disable.q), + .ds (), + .qs (dio_pad_attr_47_input_disable_47_qs) + ); + assign reg2hw.dio_pad_attr[47].input_disable.qe = dio_pad_attr_47_qe; + + // F[slew_rate_47]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_47_slew_rate_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_slew_rate_47_wd), + .d (hw2reg.dio_pad_attr[47].slew_rate.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[8]), + .q (reg2hw.dio_pad_attr[47].slew_rate.q), + .ds (), + .qs (dio_pad_attr_47_slew_rate_47_qs) + ); + assign reg2hw.dio_pad_attr[47].slew_rate.qe = dio_pad_attr_47_qe; + + // F[drive_strength_47]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_47_drive_strength_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_drive_strength_47_wd), + .d (hw2reg.dio_pad_attr[47].drive_strength.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[9]), + .q (reg2hw.dio_pad_attr[47].drive_strength.q), + .ds (), + .qs (dio_pad_attr_47_drive_strength_47_qs) + ); + assign reg2hw.dio_pad_attr[47].drive_strength.qe = dio_pad_attr_47_qe; + + + // Subregister 48 of Multireg dio_pad_attr + // R[dio_pad_attr_48]: V(True) + logic dio_pad_attr_48_qe; + logic [9:0] dio_pad_attr_48_flds_we; + assign dio_pad_attr_48_qe = &dio_pad_attr_48_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_48_gated_we; + assign dio_pad_attr_48_gated_we = dio_pad_attr_48_we & dio_pad_attr_regwen_48_qs; + // F[invert_48]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_invert_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_invert_48_wd), + .d (hw2reg.dio_pad_attr[48].invert.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[0]), + .q (reg2hw.dio_pad_attr[48].invert.q), + .ds (), + .qs (dio_pad_attr_48_invert_48_qs) + ); + assign reg2hw.dio_pad_attr[48].invert.qe = dio_pad_attr_48_qe; + + // F[virtual_od_en_48]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_virtual_od_en_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_virtual_od_en_48_wd), + .d (hw2reg.dio_pad_attr[48].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[1]), + .q (reg2hw.dio_pad_attr[48].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_48_virtual_od_en_48_qs) + ); + assign reg2hw.dio_pad_attr[48].virtual_od_en.qe = dio_pad_attr_48_qe; + + // F[pull_en_48]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_pull_en_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_pull_en_48_wd), + .d (hw2reg.dio_pad_attr[48].pull_en.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[2]), + .q (reg2hw.dio_pad_attr[48].pull_en.q), + .ds (), + .qs (dio_pad_attr_48_pull_en_48_qs) + ); + assign reg2hw.dio_pad_attr[48].pull_en.qe = dio_pad_attr_48_qe; + + // F[pull_select_48]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_pull_select_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_pull_select_48_wd), + .d (hw2reg.dio_pad_attr[48].pull_select.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[3]), + .q (reg2hw.dio_pad_attr[48].pull_select.q), + .ds (), + .qs (dio_pad_attr_48_pull_select_48_qs) + ); + assign reg2hw.dio_pad_attr[48].pull_select.qe = dio_pad_attr_48_qe; + + // F[keeper_en_48]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_keeper_en_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_keeper_en_48_wd), + .d (hw2reg.dio_pad_attr[48].keeper_en.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[4]), + .q (reg2hw.dio_pad_attr[48].keeper_en.q), + .ds (), + .qs (dio_pad_attr_48_keeper_en_48_qs) + ); + assign reg2hw.dio_pad_attr[48].keeper_en.qe = dio_pad_attr_48_qe; + + // F[schmitt_en_48]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_schmitt_en_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_schmitt_en_48_wd), + .d (hw2reg.dio_pad_attr[48].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[5]), + .q (reg2hw.dio_pad_attr[48].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_48_schmitt_en_48_qs) + ); + assign reg2hw.dio_pad_attr[48].schmitt_en.qe = dio_pad_attr_48_qe; + + // F[od_en_48]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_od_en_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_od_en_48_wd), + .d (hw2reg.dio_pad_attr[48].od_en.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[6]), + .q (reg2hw.dio_pad_attr[48].od_en.q), + .ds (), + .qs (dio_pad_attr_48_od_en_48_qs) + ); + assign reg2hw.dio_pad_attr[48].od_en.qe = dio_pad_attr_48_qe; + + // F[input_disable_48]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_input_disable_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_input_disable_48_wd), + .d (hw2reg.dio_pad_attr[48].input_disable.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[7]), + .q (reg2hw.dio_pad_attr[48].input_disable.q), + .ds (), + .qs (dio_pad_attr_48_input_disable_48_qs) + ); + assign reg2hw.dio_pad_attr[48].input_disable.qe = dio_pad_attr_48_qe; + + // F[slew_rate_48]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_48_slew_rate_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_slew_rate_48_wd), + .d (hw2reg.dio_pad_attr[48].slew_rate.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[8]), + .q (reg2hw.dio_pad_attr[48].slew_rate.q), + .ds (), + .qs (dio_pad_attr_48_slew_rate_48_qs) + ); + assign reg2hw.dio_pad_attr[48].slew_rate.qe = dio_pad_attr_48_qe; + + // F[drive_strength_48]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_48_drive_strength_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_drive_strength_48_wd), + .d (hw2reg.dio_pad_attr[48].drive_strength.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[9]), + .q (reg2hw.dio_pad_attr[48].drive_strength.q), + .ds (), + .qs (dio_pad_attr_48_drive_strength_48_qs) + ); + assign reg2hw.dio_pad_attr[48].drive_strength.qe = dio_pad_attr_48_qe; + + + // Subregister 49 of Multireg dio_pad_attr + // R[dio_pad_attr_49]: V(True) + logic dio_pad_attr_49_qe; + logic [9:0] dio_pad_attr_49_flds_we; + assign dio_pad_attr_49_qe = &dio_pad_attr_49_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_49_gated_we; + assign dio_pad_attr_49_gated_we = dio_pad_attr_49_we & dio_pad_attr_regwen_49_qs; + // F[invert_49]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_invert_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_invert_49_wd), + .d (hw2reg.dio_pad_attr[49].invert.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[0]), + .q (reg2hw.dio_pad_attr[49].invert.q), + .ds (), + .qs (dio_pad_attr_49_invert_49_qs) + ); + assign reg2hw.dio_pad_attr[49].invert.qe = dio_pad_attr_49_qe; + + // F[virtual_od_en_49]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_virtual_od_en_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_virtual_od_en_49_wd), + .d (hw2reg.dio_pad_attr[49].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[1]), + .q (reg2hw.dio_pad_attr[49].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_49_virtual_od_en_49_qs) + ); + assign reg2hw.dio_pad_attr[49].virtual_od_en.qe = dio_pad_attr_49_qe; + + // F[pull_en_49]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_pull_en_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_pull_en_49_wd), + .d (hw2reg.dio_pad_attr[49].pull_en.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[2]), + .q (reg2hw.dio_pad_attr[49].pull_en.q), + .ds (), + .qs (dio_pad_attr_49_pull_en_49_qs) + ); + assign reg2hw.dio_pad_attr[49].pull_en.qe = dio_pad_attr_49_qe; + + // F[pull_select_49]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_pull_select_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_pull_select_49_wd), + .d (hw2reg.dio_pad_attr[49].pull_select.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[3]), + .q (reg2hw.dio_pad_attr[49].pull_select.q), + .ds (), + .qs (dio_pad_attr_49_pull_select_49_qs) + ); + assign reg2hw.dio_pad_attr[49].pull_select.qe = dio_pad_attr_49_qe; + + // F[keeper_en_49]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_keeper_en_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_keeper_en_49_wd), + .d (hw2reg.dio_pad_attr[49].keeper_en.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[4]), + .q (reg2hw.dio_pad_attr[49].keeper_en.q), + .ds (), + .qs (dio_pad_attr_49_keeper_en_49_qs) + ); + assign reg2hw.dio_pad_attr[49].keeper_en.qe = dio_pad_attr_49_qe; + + // F[schmitt_en_49]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_schmitt_en_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_schmitt_en_49_wd), + .d (hw2reg.dio_pad_attr[49].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[5]), + .q (reg2hw.dio_pad_attr[49].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_49_schmitt_en_49_qs) + ); + assign reg2hw.dio_pad_attr[49].schmitt_en.qe = dio_pad_attr_49_qe; + + // F[od_en_49]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_od_en_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_od_en_49_wd), + .d (hw2reg.dio_pad_attr[49].od_en.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[6]), + .q (reg2hw.dio_pad_attr[49].od_en.q), + .ds (), + .qs (dio_pad_attr_49_od_en_49_qs) + ); + assign reg2hw.dio_pad_attr[49].od_en.qe = dio_pad_attr_49_qe; + + // F[input_disable_49]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_input_disable_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_input_disable_49_wd), + .d (hw2reg.dio_pad_attr[49].input_disable.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[7]), + .q (reg2hw.dio_pad_attr[49].input_disable.q), + .ds (), + .qs (dio_pad_attr_49_input_disable_49_qs) + ); + assign reg2hw.dio_pad_attr[49].input_disable.qe = dio_pad_attr_49_qe; + + // F[slew_rate_49]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_49_slew_rate_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_slew_rate_49_wd), + .d (hw2reg.dio_pad_attr[49].slew_rate.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[8]), + .q (reg2hw.dio_pad_attr[49].slew_rate.q), + .ds (), + .qs (dio_pad_attr_49_slew_rate_49_qs) + ); + assign reg2hw.dio_pad_attr[49].slew_rate.qe = dio_pad_attr_49_qe; + + // F[drive_strength_49]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_49_drive_strength_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_drive_strength_49_wd), + .d (hw2reg.dio_pad_attr[49].drive_strength.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[9]), + .q (reg2hw.dio_pad_attr[49].drive_strength.q), + .ds (), + .qs (dio_pad_attr_49_drive_strength_49_qs) + ); + assign reg2hw.dio_pad_attr[49].drive_strength.qe = dio_pad_attr_49_qe; + + + // Subregister 50 of Multireg dio_pad_attr + // R[dio_pad_attr_50]: V(True) + logic dio_pad_attr_50_qe; + logic [9:0] dio_pad_attr_50_flds_we; + assign dio_pad_attr_50_qe = &dio_pad_attr_50_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_50_gated_we; + assign dio_pad_attr_50_gated_we = dio_pad_attr_50_we & dio_pad_attr_regwen_50_qs; + // F[invert_50]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_invert_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_invert_50_wd), + .d (hw2reg.dio_pad_attr[50].invert.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[0]), + .q (reg2hw.dio_pad_attr[50].invert.q), + .ds (), + .qs (dio_pad_attr_50_invert_50_qs) + ); + assign reg2hw.dio_pad_attr[50].invert.qe = dio_pad_attr_50_qe; + + // F[virtual_od_en_50]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_virtual_od_en_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_virtual_od_en_50_wd), + .d (hw2reg.dio_pad_attr[50].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[1]), + .q (reg2hw.dio_pad_attr[50].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_50_virtual_od_en_50_qs) + ); + assign reg2hw.dio_pad_attr[50].virtual_od_en.qe = dio_pad_attr_50_qe; + + // F[pull_en_50]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_pull_en_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_pull_en_50_wd), + .d (hw2reg.dio_pad_attr[50].pull_en.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[2]), + .q (reg2hw.dio_pad_attr[50].pull_en.q), + .ds (), + .qs (dio_pad_attr_50_pull_en_50_qs) + ); + assign reg2hw.dio_pad_attr[50].pull_en.qe = dio_pad_attr_50_qe; + + // F[pull_select_50]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_pull_select_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_pull_select_50_wd), + .d (hw2reg.dio_pad_attr[50].pull_select.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[3]), + .q (reg2hw.dio_pad_attr[50].pull_select.q), + .ds (), + .qs (dio_pad_attr_50_pull_select_50_qs) + ); + assign reg2hw.dio_pad_attr[50].pull_select.qe = dio_pad_attr_50_qe; + + // F[keeper_en_50]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_keeper_en_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_keeper_en_50_wd), + .d (hw2reg.dio_pad_attr[50].keeper_en.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[4]), + .q (reg2hw.dio_pad_attr[50].keeper_en.q), + .ds (), + .qs (dio_pad_attr_50_keeper_en_50_qs) + ); + assign reg2hw.dio_pad_attr[50].keeper_en.qe = dio_pad_attr_50_qe; + + // F[schmitt_en_50]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_schmitt_en_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_schmitt_en_50_wd), + .d (hw2reg.dio_pad_attr[50].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[5]), + .q (reg2hw.dio_pad_attr[50].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_50_schmitt_en_50_qs) + ); + assign reg2hw.dio_pad_attr[50].schmitt_en.qe = dio_pad_attr_50_qe; + + // F[od_en_50]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_od_en_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_od_en_50_wd), + .d (hw2reg.dio_pad_attr[50].od_en.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[6]), + .q (reg2hw.dio_pad_attr[50].od_en.q), + .ds (), + .qs (dio_pad_attr_50_od_en_50_qs) + ); + assign reg2hw.dio_pad_attr[50].od_en.qe = dio_pad_attr_50_qe; + + // F[input_disable_50]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_input_disable_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_input_disable_50_wd), + .d (hw2reg.dio_pad_attr[50].input_disable.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[7]), + .q (reg2hw.dio_pad_attr[50].input_disable.q), + .ds (), + .qs (dio_pad_attr_50_input_disable_50_qs) + ); + assign reg2hw.dio_pad_attr[50].input_disable.qe = dio_pad_attr_50_qe; + + // F[slew_rate_50]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_50_slew_rate_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_slew_rate_50_wd), + .d (hw2reg.dio_pad_attr[50].slew_rate.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[8]), + .q (reg2hw.dio_pad_attr[50].slew_rate.q), + .ds (), + .qs (dio_pad_attr_50_slew_rate_50_qs) + ); + assign reg2hw.dio_pad_attr[50].slew_rate.qe = dio_pad_attr_50_qe; + + // F[drive_strength_50]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_50_drive_strength_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_drive_strength_50_wd), + .d (hw2reg.dio_pad_attr[50].drive_strength.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[9]), + .q (reg2hw.dio_pad_attr[50].drive_strength.q), + .ds (), + .qs (dio_pad_attr_50_drive_strength_50_qs) + ); + assign reg2hw.dio_pad_attr[50].drive_strength.qe = dio_pad_attr_50_qe; + + + // Subregister 51 of Multireg dio_pad_attr + // R[dio_pad_attr_51]: V(True) + logic dio_pad_attr_51_qe; + logic [9:0] dio_pad_attr_51_flds_we; + assign dio_pad_attr_51_qe = &dio_pad_attr_51_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_51_gated_we; + assign dio_pad_attr_51_gated_we = dio_pad_attr_51_we & dio_pad_attr_regwen_51_qs; + // F[invert_51]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_invert_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_invert_51_wd), + .d (hw2reg.dio_pad_attr[51].invert.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[0]), + .q (reg2hw.dio_pad_attr[51].invert.q), + .ds (), + .qs (dio_pad_attr_51_invert_51_qs) + ); + assign reg2hw.dio_pad_attr[51].invert.qe = dio_pad_attr_51_qe; + + // F[virtual_od_en_51]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_virtual_od_en_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_virtual_od_en_51_wd), + .d (hw2reg.dio_pad_attr[51].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[1]), + .q (reg2hw.dio_pad_attr[51].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_51_virtual_od_en_51_qs) + ); + assign reg2hw.dio_pad_attr[51].virtual_od_en.qe = dio_pad_attr_51_qe; + + // F[pull_en_51]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_pull_en_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_pull_en_51_wd), + .d (hw2reg.dio_pad_attr[51].pull_en.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[2]), + .q (reg2hw.dio_pad_attr[51].pull_en.q), + .ds (), + .qs (dio_pad_attr_51_pull_en_51_qs) + ); + assign reg2hw.dio_pad_attr[51].pull_en.qe = dio_pad_attr_51_qe; + + // F[pull_select_51]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_pull_select_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_pull_select_51_wd), + .d (hw2reg.dio_pad_attr[51].pull_select.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[3]), + .q (reg2hw.dio_pad_attr[51].pull_select.q), + .ds (), + .qs (dio_pad_attr_51_pull_select_51_qs) + ); + assign reg2hw.dio_pad_attr[51].pull_select.qe = dio_pad_attr_51_qe; + + // F[keeper_en_51]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_keeper_en_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_keeper_en_51_wd), + .d (hw2reg.dio_pad_attr[51].keeper_en.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[4]), + .q (reg2hw.dio_pad_attr[51].keeper_en.q), + .ds (), + .qs (dio_pad_attr_51_keeper_en_51_qs) + ); + assign reg2hw.dio_pad_attr[51].keeper_en.qe = dio_pad_attr_51_qe; + + // F[schmitt_en_51]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_schmitt_en_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_schmitt_en_51_wd), + .d (hw2reg.dio_pad_attr[51].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[5]), + .q (reg2hw.dio_pad_attr[51].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_51_schmitt_en_51_qs) + ); + assign reg2hw.dio_pad_attr[51].schmitt_en.qe = dio_pad_attr_51_qe; + + // F[od_en_51]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_od_en_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_od_en_51_wd), + .d (hw2reg.dio_pad_attr[51].od_en.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[6]), + .q (reg2hw.dio_pad_attr[51].od_en.q), + .ds (), + .qs (dio_pad_attr_51_od_en_51_qs) + ); + assign reg2hw.dio_pad_attr[51].od_en.qe = dio_pad_attr_51_qe; + + // F[input_disable_51]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_input_disable_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_input_disable_51_wd), + .d (hw2reg.dio_pad_attr[51].input_disable.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[7]), + .q (reg2hw.dio_pad_attr[51].input_disable.q), + .ds (), + .qs (dio_pad_attr_51_input_disable_51_qs) + ); + assign reg2hw.dio_pad_attr[51].input_disable.qe = dio_pad_attr_51_qe; + + // F[slew_rate_51]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_51_slew_rate_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_slew_rate_51_wd), + .d (hw2reg.dio_pad_attr[51].slew_rate.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[8]), + .q (reg2hw.dio_pad_attr[51].slew_rate.q), + .ds (), + .qs (dio_pad_attr_51_slew_rate_51_qs) + ); + assign reg2hw.dio_pad_attr[51].slew_rate.qe = dio_pad_attr_51_qe; + + // F[drive_strength_51]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_51_drive_strength_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_drive_strength_51_wd), + .d (hw2reg.dio_pad_attr[51].drive_strength.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[9]), + .q (reg2hw.dio_pad_attr[51].drive_strength.q), + .ds (), + .qs (dio_pad_attr_51_drive_strength_51_qs) + ); + assign reg2hw.dio_pad_attr[51].drive_strength.qe = dio_pad_attr_51_qe; + + + // Subregister 52 of Multireg dio_pad_attr + // R[dio_pad_attr_52]: V(True) + logic dio_pad_attr_52_qe; + logic [9:0] dio_pad_attr_52_flds_we; + assign dio_pad_attr_52_qe = &dio_pad_attr_52_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_52_gated_we; + assign dio_pad_attr_52_gated_we = dio_pad_attr_52_we & dio_pad_attr_regwen_52_qs; + // F[invert_52]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_invert_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_invert_52_wd), + .d (hw2reg.dio_pad_attr[52].invert.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[0]), + .q (reg2hw.dio_pad_attr[52].invert.q), + .ds (), + .qs (dio_pad_attr_52_invert_52_qs) + ); + assign reg2hw.dio_pad_attr[52].invert.qe = dio_pad_attr_52_qe; + + // F[virtual_od_en_52]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_virtual_od_en_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_virtual_od_en_52_wd), + .d (hw2reg.dio_pad_attr[52].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[1]), + .q (reg2hw.dio_pad_attr[52].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_52_virtual_od_en_52_qs) + ); + assign reg2hw.dio_pad_attr[52].virtual_od_en.qe = dio_pad_attr_52_qe; + + // F[pull_en_52]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_pull_en_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_pull_en_52_wd), + .d (hw2reg.dio_pad_attr[52].pull_en.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[2]), + .q (reg2hw.dio_pad_attr[52].pull_en.q), + .ds (), + .qs (dio_pad_attr_52_pull_en_52_qs) + ); + assign reg2hw.dio_pad_attr[52].pull_en.qe = dio_pad_attr_52_qe; + + // F[pull_select_52]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_pull_select_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_pull_select_52_wd), + .d (hw2reg.dio_pad_attr[52].pull_select.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[3]), + .q (reg2hw.dio_pad_attr[52].pull_select.q), + .ds (), + .qs (dio_pad_attr_52_pull_select_52_qs) + ); + assign reg2hw.dio_pad_attr[52].pull_select.qe = dio_pad_attr_52_qe; + + // F[keeper_en_52]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_keeper_en_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_keeper_en_52_wd), + .d (hw2reg.dio_pad_attr[52].keeper_en.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[4]), + .q (reg2hw.dio_pad_attr[52].keeper_en.q), + .ds (), + .qs (dio_pad_attr_52_keeper_en_52_qs) + ); + assign reg2hw.dio_pad_attr[52].keeper_en.qe = dio_pad_attr_52_qe; + + // F[schmitt_en_52]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_schmitt_en_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_schmitt_en_52_wd), + .d (hw2reg.dio_pad_attr[52].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[5]), + .q (reg2hw.dio_pad_attr[52].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_52_schmitt_en_52_qs) + ); + assign reg2hw.dio_pad_attr[52].schmitt_en.qe = dio_pad_attr_52_qe; + + // F[od_en_52]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_od_en_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_od_en_52_wd), + .d (hw2reg.dio_pad_attr[52].od_en.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[6]), + .q (reg2hw.dio_pad_attr[52].od_en.q), + .ds (), + .qs (dio_pad_attr_52_od_en_52_qs) + ); + assign reg2hw.dio_pad_attr[52].od_en.qe = dio_pad_attr_52_qe; + + // F[input_disable_52]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_input_disable_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_input_disable_52_wd), + .d (hw2reg.dio_pad_attr[52].input_disable.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[7]), + .q (reg2hw.dio_pad_attr[52].input_disable.q), + .ds (), + .qs (dio_pad_attr_52_input_disable_52_qs) + ); + assign reg2hw.dio_pad_attr[52].input_disable.qe = dio_pad_attr_52_qe; + + // F[slew_rate_52]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_52_slew_rate_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_slew_rate_52_wd), + .d (hw2reg.dio_pad_attr[52].slew_rate.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[8]), + .q (reg2hw.dio_pad_attr[52].slew_rate.q), + .ds (), + .qs (dio_pad_attr_52_slew_rate_52_qs) + ); + assign reg2hw.dio_pad_attr[52].slew_rate.qe = dio_pad_attr_52_qe; + + // F[drive_strength_52]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_52_drive_strength_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_drive_strength_52_wd), + .d (hw2reg.dio_pad_attr[52].drive_strength.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[9]), + .q (reg2hw.dio_pad_attr[52].drive_strength.q), + .ds (), + .qs (dio_pad_attr_52_drive_strength_52_qs) + ); + assign reg2hw.dio_pad_attr[52].drive_strength.qe = dio_pad_attr_52_qe; + + + // Subregister 53 of Multireg dio_pad_attr + // R[dio_pad_attr_53]: V(True) + logic dio_pad_attr_53_qe; + logic [9:0] dio_pad_attr_53_flds_we; + assign dio_pad_attr_53_qe = &dio_pad_attr_53_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_53_gated_we; + assign dio_pad_attr_53_gated_we = dio_pad_attr_53_we & dio_pad_attr_regwen_53_qs; + // F[invert_53]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_invert_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_invert_53_wd), + .d (hw2reg.dio_pad_attr[53].invert.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[0]), + .q (reg2hw.dio_pad_attr[53].invert.q), + .ds (), + .qs (dio_pad_attr_53_invert_53_qs) + ); + assign reg2hw.dio_pad_attr[53].invert.qe = dio_pad_attr_53_qe; + + // F[virtual_od_en_53]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_virtual_od_en_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_virtual_od_en_53_wd), + .d (hw2reg.dio_pad_attr[53].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[1]), + .q (reg2hw.dio_pad_attr[53].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_53_virtual_od_en_53_qs) + ); + assign reg2hw.dio_pad_attr[53].virtual_od_en.qe = dio_pad_attr_53_qe; + + // F[pull_en_53]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_pull_en_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_pull_en_53_wd), + .d (hw2reg.dio_pad_attr[53].pull_en.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[2]), + .q (reg2hw.dio_pad_attr[53].pull_en.q), + .ds (), + .qs (dio_pad_attr_53_pull_en_53_qs) + ); + assign reg2hw.dio_pad_attr[53].pull_en.qe = dio_pad_attr_53_qe; + + // F[pull_select_53]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_pull_select_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_pull_select_53_wd), + .d (hw2reg.dio_pad_attr[53].pull_select.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[3]), + .q (reg2hw.dio_pad_attr[53].pull_select.q), + .ds (), + .qs (dio_pad_attr_53_pull_select_53_qs) + ); + assign reg2hw.dio_pad_attr[53].pull_select.qe = dio_pad_attr_53_qe; + + // F[keeper_en_53]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_keeper_en_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_keeper_en_53_wd), + .d (hw2reg.dio_pad_attr[53].keeper_en.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[4]), + .q (reg2hw.dio_pad_attr[53].keeper_en.q), + .ds (), + .qs (dio_pad_attr_53_keeper_en_53_qs) + ); + assign reg2hw.dio_pad_attr[53].keeper_en.qe = dio_pad_attr_53_qe; + + // F[schmitt_en_53]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_schmitt_en_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_schmitt_en_53_wd), + .d (hw2reg.dio_pad_attr[53].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[5]), + .q (reg2hw.dio_pad_attr[53].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_53_schmitt_en_53_qs) + ); + assign reg2hw.dio_pad_attr[53].schmitt_en.qe = dio_pad_attr_53_qe; + + // F[od_en_53]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_od_en_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_od_en_53_wd), + .d (hw2reg.dio_pad_attr[53].od_en.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[6]), + .q (reg2hw.dio_pad_attr[53].od_en.q), + .ds (), + .qs (dio_pad_attr_53_od_en_53_qs) + ); + assign reg2hw.dio_pad_attr[53].od_en.qe = dio_pad_attr_53_qe; + + // F[input_disable_53]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_input_disable_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_input_disable_53_wd), + .d (hw2reg.dio_pad_attr[53].input_disable.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[7]), + .q (reg2hw.dio_pad_attr[53].input_disable.q), + .ds (), + .qs (dio_pad_attr_53_input_disable_53_qs) + ); + assign reg2hw.dio_pad_attr[53].input_disable.qe = dio_pad_attr_53_qe; + + // F[slew_rate_53]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_53_slew_rate_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_slew_rate_53_wd), + .d (hw2reg.dio_pad_attr[53].slew_rate.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[8]), + .q (reg2hw.dio_pad_attr[53].slew_rate.q), + .ds (), + .qs (dio_pad_attr_53_slew_rate_53_qs) + ); + assign reg2hw.dio_pad_attr[53].slew_rate.qe = dio_pad_attr_53_qe; + + // F[drive_strength_53]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_53_drive_strength_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_drive_strength_53_wd), + .d (hw2reg.dio_pad_attr[53].drive_strength.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[9]), + .q (reg2hw.dio_pad_attr[53].drive_strength.q), + .ds (), + .qs (dio_pad_attr_53_drive_strength_53_qs) + ); + assign reg2hw.dio_pad_attr[53].drive_strength.qe = dio_pad_attr_53_qe; + + + // Subregister 54 of Multireg dio_pad_attr + // R[dio_pad_attr_54]: V(True) + logic dio_pad_attr_54_qe; + logic [9:0] dio_pad_attr_54_flds_we; + assign dio_pad_attr_54_qe = &dio_pad_attr_54_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_54_gated_we; + assign dio_pad_attr_54_gated_we = dio_pad_attr_54_we & dio_pad_attr_regwen_54_qs; + // F[invert_54]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_invert_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_invert_54_wd), + .d (hw2reg.dio_pad_attr[54].invert.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[0]), + .q (reg2hw.dio_pad_attr[54].invert.q), + .ds (), + .qs (dio_pad_attr_54_invert_54_qs) + ); + assign reg2hw.dio_pad_attr[54].invert.qe = dio_pad_attr_54_qe; + + // F[virtual_od_en_54]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_virtual_od_en_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_virtual_od_en_54_wd), + .d (hw2reg.dio_pad_attr[54].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[1]), + .q (reg2hw.dio_pad_attr[54].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_54_virtual_od_en_54_qs) + ); + assign reg2hw.dio_pad_attr[54].virtual_od_en.qe = dio_pad_attr_54_qe; + + // F[pull_en_54]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_pull_en_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_pull_en_54_wd), + .d (hw2reg.dio_pad_attr[54].pull_en.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[2]), + .q (reg2hw.dio_pad_attr[54].pull_en.q), + .ds (), + .qs (dio_pad_attr_54_pull_en_54_qs) + ); + assign reg2hw.dio_pad_attr[54].pull_en.qe = dio_pad_attr_54_qe; + + // F[pull_select_54]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_pull_select_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_pull_select_54_wd), + .d (hw2reg.dio_pad_attr[54].pull_select.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[3]), + .q (reg2hw.dio_pad_attr[54].pull_select.q), + .ds (), + .qs (dio_pad_attr_54_pull_select_54_qs) + ); + assign reg2hw.dio_pad_attr[54].pull_select.qe = dio_pad_attr_54_qe; + + // F[keeper_en_54]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_keeper_en_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_keeper_en_54_wd), + .d (hw2reg.dio_pad_attr[54].keeper_en.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[4]), + .q (reg2hw.dio_pad_attr[54].keeper_en.q), + .ds (), + .qs (dio_pad_attr_54_keeper_en_54_qs) + ); + assign reg2hw.dio_pad_attr[54].keeper_en.qe = dio_pad_attr_54_qe; + + // F[schmitt_en_54]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_schmitt_en_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_schmitt_en_54_wd), + .d (hw2reg.dio_pad_attr[54].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[5]), + .q (reg2hw.dio_pad_attr[54].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_54_schmitt_en_54_qs) + ); + assign reg2hw.dio_pad_attr[54].schmitt_en.qe = dio_pad_attr_54_qe; + + // F[od_en_54]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_od_en_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_od_en_54_wd), + .d (hw2reg.dio_pad_attr[54].od_en.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[6]), + .q (reg2hw.dio_pad_attr[54].od_en.q), + .ds (), + .qs (dio_pad_attr_54_od_en_54_qs) + ); + assign reg2hw.dio_pad_attr[54].od_en.qe = dio_pad_attr_54_qe; + + // F[input_disable_54]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_input_disable_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_input_disable_54_wd), + .d (hw2reg.dio_pad_attr[54].input_disable.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[7]), + .q (reg2hw.dio_pad_attr[54].input_disable.q), + .ds (), + .qs (dio_pad_attr_54_input_disable_54_qs) + ); + assign reg2hw.dio_pad_attr[54].input_disable.qe = dio_pad_attr_54_qe; + + // F[slew_rate_54]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_54_slew_rate_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_slew_rate_54_wd), + .d (hw2reg.dio_pad_attr[54].slew_rate.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[8]), + .q (reg2hw.dio_pad_attr[54].slew_rate.q), + .ds (), + .qs (dio_pad_attr_54_slew_rate_54_qs) + ); + assign reg2hw.dio_pad_attr[54].slew_rate.qe = dio_pad_attr_54_qe; + + // F[drive_strength_54]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_54_drive_strength_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_drive_strength_54_wd), + .d (hw2reg.dio_pad_attr[54].drive_strength.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[9]), + .q (reg2hw.dio_pad_attr[54].drive_strength.q), + .ds (), + .qs (dio_pad_attr_54_drive_strength_54_qs) + ); + assign reg2hw.dio_pad_attr[54].drive_strength.qe = dio_pad_attr_54_qe; + + + // Subregister 55 of Multireg dio_pad_attr + // R[dio_pad_attr_55]: V(True) + logic dio_pad_attr_55_qe; + logic [9:0] dio_pad_attr_55_flds_we; + assign dio_pad_attr_55_qe = &dio_pad_attr_55_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_55_gated_we; + assign dio_pad_attr_55_gated_we = dio_pad_attr_55_we & dio_pad_attr_regwen_55_qs; + // F[invert_55]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_invert_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_invert_55_wd), + .d (hw2reg.dio_pad_attr[55].invert.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[0]), + .q (reg2hw.dio_pad_attr[55].invert.q), + .ds (), + .qs (dio_pad_attr_55_invert_55_qs) + ); + assign reg2hw.dio_pad_attr[55].invert.qe = dio_pad_attr_55_qe; + + // F[virtual_od_en_55]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_virtual_od_en_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_virtual_od_en_55_wd), + .d (hw2reg.dio_pad_attr[55].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[1]), + .q (reg2hw.dio_pad_attr[55].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_55_virtual_od_en_55_qs) + ); + assign reg2hw.dio_pad_attr[55].virtual_od_en.qe = dio_pad_attr_55_qe; + + // F[pull_en_55]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_pull_en_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_pull_en_55_wd), + .d (hw2reg.dio_pad_attr[55].pull_en.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[2]), + .q (reg2hw.dio_pad_attr[55].pull_en.q), + .ds (), + .qs (dio_pad_attr_55_pull_en_55_qs) + ); + assign reg2hw.dio_pad_attr[55].pull_en.qe = dio_pad_attr_55_qe; + + // F[pull_select_55]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_pull_select_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_pull_select_55_wd), + .d (hw2reg.dio_pad_attr[55].pull_select.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[3]), + .q (reg2hw.dio_pad_attr[55].pull_select.q), + .ds (), + .qs (dio_pad_attr_55_pull_select_55_qs) + ); + assign reg2hw.dio_pad_attr[55].pull_select.qe = dio_pad_attr_55_qe; + + // F[keeper_en_55]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_keeper_en_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_keeper_en_55_wd), + .d (hw2reg.dio_pad_attr[55].keeper_en.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[4]), + .q (reg2hw.dio_pad_attr[55].keeper_en.q), + .ds (), + .qs (dio_pad_attr_55_keeper_en_55_qs) + ); + assign reg2hw.dio_pad_attr[55].keeper_en.qe = dio_pad_attr_55_qe; + + // F[schmitt_en_55]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_schmitt_en_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_schmitt_en_55_wd), + .d (hw2reg.dio_pad_attr[55].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[5]), + .q (reg2hw.dio_pad_attr[55].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_55_schmitt_en_55_qs) + ); + assign reg2hw.dio_pad_attr[55].schmitt_en.qe = dio_pad_attr_55_qe; + + // F[od_en_55]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_od_en_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_od_en_55_wd), + .d (hw2reg.dio_pad_attr[55].od_en.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[6]), + .q (reg2hw.dio_pad_attr[55].od_en.q), + .ds (), + .qs (dio_pad_attr_55_od_en_55_qs) + ); + assign reg2hw.dio_pad_attr[55].od_en.qe = dio_pad_attr_55_qe; + + // F[input_disable_55]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_input_disable_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_input_disable_55_wd), + .d (hw2reg.dio_pad_attr[55].input_disable.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[7]), + .q (reg2hw.dio_pad_attr[55].input_disable.q), + .ds (), + .qs (dio_pad_attr_55_input_disable_55_qs) + ); + assign reg2hw.dio_pad_attr[55].input_disable.qe = dio_pad_attr_55_qe; + + // F[slew_rate_55]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_55_slew_rate_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_slew_rate_55_wd), + .d (hw2reg.dio_pad_attr[55].slew_rate.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[8]), + .q (reg2hw.dio_pad_attr[55].slew_rate.q), + .ds (), + .qs (dio_pad_attr_55_slew_rate_55_qs) + ); + assign reg2hw.dio_pad_attr[55].slew_rate.qe = dio_pad_attr_55_qe; + + // F[drive_strength_55]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_55_drive_strength_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_drive_strength_55_wd), + .d (hw2reg.dio_pad_attr[55].drive_strength.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[9]), + .q (reg2hw.dio_pad_attr[55].drive_strength.q), + .ds (), + .qs (dio_pad_attr_55_drive_strength_55_qs) + ); + assign reg2hw.dio_pad_attr[55].drive_strength.qe = dio_pad_attr_55_qe; + + + // Subregister 56 of Multireg dio_pad_attr + // R[dio_pad_attr_56]: V(True) + logic dio_pad_attr_56_qe; + logic [9:0] dio_pad_attr_56_flds_we; + assign dio_pad_attr_56_qe = &dio_pad_attr_56_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_56_gated_we; + assign dio_pad_attr_56_gated_we = dio_pad_attr_56_we & dio_pad_attr_regwen_56_qs; + // F[invert_56]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_invert_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_invert_56_wd), + .d (hw2reg.dio_pad_attr[56].invert.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[0]), + .q (reg2hw.dio_pad_attr[56].invert.q), + .ds (), + .qs (dio_pad_attr_56_invert_56_qs) + ); + assign reg2hw.dio_pad_attr[56].invert.qe = dio_pad_attr_56_qe; + + // F[virtual_od_en_56]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_virtual_od_en_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_virtual_od_en_56_wd), + .d (hw2reg.dio_pad_attr[56].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[1]), + .q (reg2hw.dio_pad_attr[56].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_56_virtual_od_en_56_qs) + ); + assign reg2hw.dio_pad_attr[56].virtual_od_en.qe = dio_pad_attr_56_qe; + + // F[pull_en_56]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_pull_en_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_pull_en_56_wd), + .d (hw2reg.dio_pad_attr[56].pull_en.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[2]), + .q (reg2hw.dio_pad_attr[56].pull_en.q), + .ds (), + .qs (dio_pad_attr_56_pull_en_56_qs) + ); + assign reg2hw.dio_pad_attr[56].pull_en.qe = dio_pad_attr_56_qe; + + // F[pull_select_56]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_pull_select_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_pull_select_56_wd), + .d (hw2reg.dio_pad_attr[56].pull_select.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[3]), + .q (reg2hw.dio_pad_attr[56].pull_select.q), + .ds (), + .qs (dio_pad_attr_56_pull_select_56_qs) + ); + assign reg2hw.dio_pad_attr[56].pull_select.qe = dio_pad_attr_56_qe; + + // F[keeper_en_56]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_keeper_en_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_keeper_en_56_wd), + .d (hw2reg.dio_pad_attr[56].keeper_en.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[4]), + .q (reg2hw.dio_pad_attr[56].keeper_en.q), + .ds (), + .qs (dio_pad_attr_56_keeper_en_56_qs) + ); + assign reg2hw.dio_pad_attr[56].keeper_en.qe = dio_pad_attr_56_qe; + + // F[schmitt_en_56]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_schmitt_en_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_schmitt_en_56_wd), + .d (hw2reg.dio_pad_attr[56].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[5]), + .q (reg2hw.dio_pad_attr[56].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_56_schmitt_en_56_qs) + ); + assign reg2hw.dio_pad_attr[56].schmitt_en.qe = dio_pad_attr_56_qe; + + // F[od_en_56]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_od_en_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_od_en_56_wd), + .d (hw2reg.dio_pad_attr[56].od_en.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[6]), + .q (reg2hw.dio_pad_attr[56].od_en.q), + .ds (), + .qs (dio_pad_attr_56_od_en_56_qs) + ); + assign reg2hw.dio_pad_attr[56].od_en.qe = dio_pad_attr_56_qe; + + // F[input_disable_56]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_input_disable_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_input_disable_56_wd), + .d (hw2reg.dio_pad_attr[56].input_disable.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[7]), + .q (reg2hw.dio_pad_attr[56].input_disable.q), + .ds (), + .qs (dio_pad_attr_56_input_disable_56_qs) + ); + assign reg2hw.dio_pad_attr[56].input_disable.qe = dio_pad_attr_56_qe; + + // F[slew_rate_56]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_56_slew_rate_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_slew_rate_56_wd), + .d (hw2reg.dio_pad_attr[56].slew_rate.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[8]), + .q (reg2hw.dio_pad_attr[56].slew_rate.q), + .ds (), + .qs (dio_pad_attr_56_slew_rate_56_qs) + ); + assign reg2hw.dio_pad_attr[56].slew_rate.qe = dio_pad_attr_56_qe; + + // F[drive_strength_56]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_56_drive_strength_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_drive_strength_56_wd), + .d (hw2reg.dio_pad_attr[56].drive_strength.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[9]), + .q (reg2hw.dio_pad_attr[56].drive_strength.q), + .ds (), + .qs (dio_pad_attr_56_drive_strength_56_qs) + ); + assign reg2hw.dio_pad_attr[56].drive_strength.qe = dio_pad_attr_56_qe; + + + // Subregister 57 of Multireg dio_pad_attr + // R[dio_pad_attr_57]: V(True) + logic dio_pad_attr_57_qe; + logic [9:0] dio_pad_attr_57_flds_we; + assign dio_pad_attr_57_qe = &dio_pad_attr_57_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_57_gated_we; + assign dio_pad_attr_57_gated_we = dio_pad_attr_57_we & dio_pad_attr_regwen_57_qs; + // F[invert_57]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_invert_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_invert_57_wd), + .d (hw2reg.dio_pad_attr[57].invert.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[0]), + .q (reg2hw.dio_pad_attr[57].invert.q), + .ds (), + .qs (dio_pad_attr_57_invert_57_qs) + ); + assign reg2hw.dio_pad_attr[57].invert.qe = dio_pad_attr_57_qe; + + // F[virtual_od_en_57]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_virtual_od_en_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_virtual_od_en_57_wd), + .d (hw2reg.dio_pad_attr[57].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[1]), + .q (reg2hw.dio_pad_attr[57].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_57_virtual_od_en_57_qs) + ); + assign reg2hw.dio_pad_attr[57].virtual_od_en.qe = dio_pad_attr_57_qe; + + // F[pull_en_57]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_pull_en_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_pull_en_57_wd), + .d (hw2reg.dio_pad_attr[57].pull_en.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[2]), + .q (reg2hw.dio_pad_attr[57].pull_en.q), + .ds (), + .qs (dio_pad_attr_57_pull_en_57_qs) + ); + assign reg2hw.dio_pad_attr[57].pull_en.qe = dio_pad_attr_57_qe; + + // F[pull_select_57]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_pull_select_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_pull_select_57_wd), + .d (hw2reg.dio_pad_attr[57].pull_select.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[3]), + .q (reg2hw.dio_pad_attr[57].pull_select.q), + .ds (), + .qs (dio_pad_attr_57_pull_select_57_qs) + ); + assign reg2hw.dio_pad_attr[57].pull_select.qe = dio_pad_attr_57_qe; + + // F[keeper_en_57]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_keeper_en_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_keeper_en_57_wd), + .d (hw2reg.dio_pad_attr[57].keeper_en.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[4]), + .q (reg2hw.dio_pad_attr[57].keeper_en.q), + .ds (), + .qs (dio_pad_attr_57_keeper_en_57_qs) + ); + assign reg2hw.dio_pad_attr[57].keeper_en.qe = dio_pad_attr_57_qe; + + // F[schmitt_en_57]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_schmitt_en_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_schmitt_en_57_wd), + .d (hw2reg.dio_pad_attr[57].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[5]), + .q (reg2hw.dio_pad_attr[57].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_57_schmitt_en_57_qs) + ); + assign reg2hw.dio_pad_attr[57].schmitt_en.qe = dio_pad_attr_57_qe; + + // F[od_en_57]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_od_en_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_od_en_57_wd), + .d (hw2reg.dio_pad_attr[57].od_en.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[6]), + .q (reg2hw.dio_pad_attr[57].od_en.q), + .ds (), + .qs (dio_pad_attr_57_od_en_57_qs) + ); + assign reg2hw.dio_pad_attr[57].od_en.qe = dio_pad_attr_57_qe; + + // F[input_disable_57]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_input_disable_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_input_disable_57_wd), + .d (hw2reg.dio_pad_attr[57].input_disable.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[7]), + .q (reg2hw.dio_pad_attr[57].input_disable.q), + .ds (), + .qs (dio_pad_attr_57_input_disable_57_qs) + ); + assign reg2hw.dio_pad_attr[57].input_disable.qe = dio_pad_attr_57_qe; + + // F[slew_rate_57]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_57_slew_rate_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_slew_rate_57_wd), + .d (hw2reg.dio_pad_attr[57].slew_rate.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[8]), + .q (reg2hw.dio_pad_attr[57].slew_rate.q), + .ds (), + .qs (dio_pad_attr_57_slew_rate_57_qs) + ); + assign reg2hw.dio_pad_attr[57].slew_rate.qe = dio_pad_attr_57_qe; + + // F[drive_strength_57]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_57_drive_strength_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_drive_strength_57_wd), + .d (hw2reg.dio_pad_attr[57].drive_strength.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[9]), + .q (reg2hw.dio_pad_attr[57].drive_strength.q), + .ds (), + .qs (dio_pad_attr_57_drive_strength_57_qs) + ); + assign reg2hw.dio_pad_attr[57].drive_strength.qe = dio_pad_attr_57_qe; + + + // Subregister 58 of Multireg dio_pad_attr + // R[dio_pad_attr_58]: V(True) + logic dio_pad_attr_58_qe; + logic [9:0] dio_pad_attr_58_flds_we; + assign dio_pad_attr_58_qe = &dio_pad_attr_58_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_58_gated_we; + assign dio_pad_attr_58_gated_we = dio_pad_attr_58_we & dio_pad_attr_regwen_58_qs; + // F[invert_58]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_invert_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_invert_58_wd), + .d (hw2reg.dio_pad_attr[58].invert.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[0]), + .q (reg2hw.dio_pad_attr[58].invert.q), + .ds (), + .qs (dio_pad_attr_58_invert_58_qs) + ); + assign reg2hw.dio_pad_attr[58].invert.qe = dio_pad_attr_58_qe; + + // F[virtual_od_en_58]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_virtual_od_en_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_virtual_od_en_58_wd), + .d (hw2reg.dio_pad_attr[58].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[1]), + .q (reg2hw.dio_pad_attr[58].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_58_virtual_od_en_58_qs) + ); + assign reg2hw.dio_pad_attr[58].virtual_od_en.qe = dio_pad_attr_58_qe; + + // F[pull_en_58]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_pull_en_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_pull_en_58_wd), + .d (hw2reg.dio_pad_attr[58].pull_en.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[2]), + .q (reg2hw.dio_pad_attr[58].pull_en.q), + .ds (), + .qs (dio_pad_attr_58_pull_en_58_qs) + ); + assign reg2hw.dio_pad_attr[58].pull_en.qe = dio_pad_attr_58_qe; + + // F[pull_select_58]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_pull_select_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_pull_select_58_wd), + .d (hw2reg.dio_pad_attr[58].pull_select.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[3]), + .q (reg2hw.dio_pad_attr[58].pull_select.q), + .ds (), + .qs (dio_pad_attr_58_pull_select_58_qs) + ); + assign reg2hw.dio_pad_attr[58].pull_select.qe = dio_pad_attr_58_qe; + + // F[keeper_en_58]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_keeper_en_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_keeper_en_58_wd), + .d (hw2reg.dio_pad_attr[58].keeper_en.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[4]), + .q (reg2hw.dio_pad_attr[58].keeper_en.q), + .ds (), + .qs (dio_pad_attr_58_keeper_en_58_qs) + ); + assign reg2hw.dio_pad_attr[58].keeper_en.qe = dio_pad_attr_58_qe; + + // F[schmitt_en_58]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_schmitt_en_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_schmitt_en_58_wd), + .d (hw2reg.dio_pad_attr[58].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[5]), + .q (reg2hw.dio_pad_attr[58].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_58_schmitt_en_58_qs) + ); + assign reg2hw.dio_pad_attr[58].schmitt_en.qe = dio_pad_attr_58_qe; + + // F[od_en_58]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_od_en_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_od_en_58_wd), + .d (hw2reg.dio_pad_attr[58].od_en.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[6]), + .q (reg2hw.dio_pad_attr[58].od_en.q), + .ds (), + .qs (dio_pad_attr_58_od_en_58_qs) + ); + assign reg2hw.dio_pad_attr[58].od_en.qe = dio_pad_attr_58_qe; + + // F[input_disable_58]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_input_disable_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_input_disable_58_wd), + .d (hw2reg.dio_pad_attr[58].input_disable.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[7]), + .q (reg2hw.dio_pad_attr[58].input_disable.q), + .ds (), + .qs (dio_pad_attr_58_input_disable_58_qs) + ); + assign reg2hw.dio_pad_attr[58].input_disable.qe = dio_pad_attr_58_qe; + + // F[slew_rate_58]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_58_slew_rate_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_slew_rate_58_wd), + .d (hw2reg.dio_pad_attr[58].slew_rate.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[8]), + .q (reg2hw.dio_pad_attr[58].slew_rate.q), + .ds (), + .qs (dio_pad_attr_58_slew_rate_58_qs) + ); + assign reg2hw.dio_pad_attr[58].slew_rate.qe = dio_pad_attr_58_qe; + + // F[drive_strength_58]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_58_drive_strength_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_drive_strength_58_wd), + .d (hw2reg.dio_pad_attr[58].drive_strength.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[9]), + .q (reg2hw.dio_pad_attr[58].drive_strength.q), + .ds (), + .qs (dio_pad_attr_58_drive_strength_58_qs) + ); + assign reg2hw.dio_pad_attr[58].drive_strength.qe = dio_pad_attr_58_qe; + + + // Subregister 59 of Multireg dio_pad_attr + // R[dio_pad_attr_59]: V(True) + logic dio_pad_attr_59_qe; + logic [9:0] dio_pad_attr_59_flds_we; + assign dio_pad_attr_59_qe = &dio_pad_attr_59_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_59_gated_we; + assign dio_pad_attr_59_gated_we = dio_pad_attr_59_we & dio_pad_attr_regwen_59_qs; + // F[invert_59]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_invert_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_invert_59_wd), + .d (hw2reg.dio_pad_attr[59].invert.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[0]), + .q (reg2hw.dio_pad_attr[59].invert.q), + .ds (), + .qs (dio_pad_attr_59_invert_59_qs) + ); + assign reg2hw.dio_pad_attr[59].invert.qe = dio_pad_attr_59_qe; + + // F[virtual_od_en_59]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_virtual_od_en_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_virtual_od_en_59_wd), + .d (hw2reg.dio_pad_attr[59].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[1]), + .q (reg2hw.dio_pad_attr[59].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_59_virtual_od_en_59_qs) + ); + assign reg2hw.dio_pad_attr[59].virtual_od_en.qe = dio_pad_attr_59_qe; + + // F[pull_en_59]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_pull_en_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_pull_en_59_wd), + .d (hw2reg.dio_pad_attr[59].pull_en.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[2]), + .q (reg2hw.dio_pad_attr[59].pull_en.q), + .ds (), + .qs (dio_pad_attr_59_pull_en_59_qs) + ); + assign reg2hw.dio_pad_attr[59].pull_en.qe = dio_pad_attr_59_qe; + + // F[pull_select_59]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_pull_select_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_pull_select_59_wd), + .d (hw2reg.dio_pad_attr[59].pull_select.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[3]), + .q (reg2hw.dio_pad_attr[59].pull_select.q), + .ds (), + .qs (dio_pad_attr_59_pull_select_59_qs) + ); + assign reg2hw.dio_pad_attr[59].pull_select.qe = dio_pad_attr_59_qe; + + // F[keeper_en_59]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_keeper_en_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_keeper_en_59_wd), + .d (hw2reg.dio_pad_attr[59].keeper_en.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[4]), + .q (reg2hw.dio_pad_attr[59].keeper_en.q), + .ds (), + .qs (dio_pad_attr_59_keeper_en_59_qs) + ); + assign reg2hw.dio_pad_attr[59].keeper_en.qe = dio_pad_attr_59_qe; + + // F[schmitt_en_59]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_schmitt_en_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_schmitt_en_59_wd), + .d (hw2reg.dio_pad_attr[59].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[5]), + .q (reg2hw.dio_pad_attr[59].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_59_schmitt_en_59_qs) + ); + assign reg2hw.dio_pad_attr[59].schmitt_en.qe = dio_pad_attr_59_qe; + + // F[od_en_59]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_od_en_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_od_en_59_wd), + .d (hw2reg.dio_pad_attr[59].od_en.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[6]), + .q (reg2hw.dio_pad_attr[59].od_en.q), + .ds (), + .qs (dio_pad_attr_59_od_en_59_qs) + ); + assign reg2hw.dio_pad_attr[59].od_en.qe = dio_pad_attr_59_qe; + + // F[input_disable_59]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_input_disable_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_input_disable_59_wd), + .d (hw2reg.dio_pad_attr[59].input_disable.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[7]), + .q (reg2hw.dio_pad_attr[59].input_disable.q), + .ds (), + .qs (dio_pad_attr_59_input_disable_59_qs) + ); + assign reg2hw.dio_pad_attr[59].input_disable.qe = dio_pad_attr_59_qe; + + // F[slew_rate_59]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_59_slew_rate_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_slew_rate_59_wd), + .d (hw2reg.dio_pad_attr[59].slew_rate.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[8]), + .q (reg2hw.dio_pad_attr[59].slew_rate.q), + .ds (), + .qs (dio_pad_attr_59_slew_rate_59_qs) + ); + assign reg2hw.dio_pad_attr[59].slew_rate.qe = dio_pad_attr_59_qe; + + // F[drive_strength_59]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_59_drive_strength_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_drive_strength_59_wd), + .d (hw2reg.dio_pad_attr[59].drive_strength.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[9]), + .q (reg2hw.dio_pad_attr[59].drive_strength.q), + .ds (), + .qs (dio_pad_attr_59_drive_strength_59_qs) + ); + assign reg2hw.dio_pad_attr[59].drive_strength.qe = dio_pad_attr_59_qe; + + + // Subregister 60 of Multireg dio_pad_attr + // R[dio_pad_attr_60]: V(True) + logic dio_pad_attr_60_qe; + logic [9:0] dio_pad_attr_60_flds_we; + assign dio_pad_attr_60_qe = &dio_pad_attr_60_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_60_gated_we; + assign dio_pad_attr_60_gated_we = dio_pad_attr_60_we & dio_pad_attr_regwen_60_qs; + // F[invert_60]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_invert_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_invert_60_wd), + .d (hw2reg.dio_pad_attr[60].invert.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[0]), + .q (reg2hw.dio_pad_attr[60].invert.q), + .ds (), + .qs (dio_pad_attr_60_invert_60_qs) + ); + assign reg2hw.dio_pad_attr[60].invert.qe = dio_pad_attr_60_qe; + + // F[virtual_od_en_60]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_virtual_od_en_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_virtual_od_en_60_wd), + .d (hw2reg.dio_pad_attr[60].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[1]), + .q (reg2hw.dio_pad_attr[60].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_60_virtual_od_en_60_qs) + ); + assign reg2hw.dio_pad_attr[60].virtual_od_en.qe = dio_pad_attr_60_qe; + + // F[pull_en_60]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_pull_en_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_pull_en_60_wd), + .d (hw2reg.dio_pad_attr[60].pull_en.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[2]), + .q (reg2hw.dio_pad_attr[60].pull_en.q), + .ds (), + .qs (dio_pad_attr_60_pull_en_60_qs) + ); + assign reg2hw.dio_pad_attr[60].pull_en.qe = dio_pad_attr_60_qe; + + // F[pull_select_60]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_pull_select_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_pull_select_60_wd), + .d (hw2reg.dio_pad_attr[60].pull_select.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[3]), + .q (reg2hw.dio_pad_attr[60].pull_select.q), + .ds (), + .qs (dio_pad_attr_60_pull_select_60_qs) + ); + assign reg2hw.dio_pad_attr[60].pull_select.qe = dio_pad_attr_60_qe; + + // F[keeper_en_60]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_keeper_en_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_keeper_en_60_wd), + .d (hw2reg.dio_pad_attr[60].keeper_en.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[4]), + .q (reg2hw.dio_pad_attr[60].keeper_en.q), + .ds (), + .qs (dio_pad_attr_60_keeper_en_60_qs) + ); + assign reg2hw.dio_pad_attr[60].keeper_en.qe = dio_pad_attr_60_qe; + + // F[schmitt_en_60]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_schmitt_en_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_schmitt_en_60_wd), + .d (hw2reg.dio_pad_attr[60].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[5]), + .q (reg2hw.dio_pad_attr[60].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_60_schmitt_en_60_qs) + ); + assign reg2hw.dio_pad_attr[60].schmitt_en.qe = dio_pad_attr_60_qe; + + // F[od_en_60]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_od_en_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_od_en_60_wd), + .d (hw2reg.dio_pad_attr[60].od_en.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[6]), + .q (reg2hw.dio_pad_attr[60].od_en.q), + .ds (), + .qs (dio_pad_attr_60_od_en_60_qs) + ); + assign reg2hw.dio_pad_attr[60].od_en.qe = dio_pad_attr_60_qe; + + // F[input_disable_60]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_input_disable_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_input_disable_60_wd), + .d (hw2reg.dio_pad_attr[60].input_disable.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[7]), + .q (reg2hw.dio_pad_attr[60].input_disable.q), + .ds (), + .qs (dio_pad_attr_60_input_disable_60_qs) + ); + assign reg2hw.dio_pad_attr[60].input_disable.qe = dio_pad_attr_60_qe; + + // F[slew_rate_60]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_60_slew_rate_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_slew_rate_60_wd), + .d (hw2reg.dio_pad_attr[60].slew_rate.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[8]), + .q (reg2hw.dio_pad_attr[60].slew_rate.q), + .ds (), + .qs (dio_pad_attr_60_slew_rate_60_qs) + ); + assign reg2hw.dio_pad_attr[60].slew_rate.qe = dio_pad_attr_60_qe; + + // F[drive_strength_60]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_60_drive_strength_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_drive_strength_60_wd), + .d (hw2reg.dio_pad_attr[60].drive_strength.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[9]), + .q (reg2hw.dio_pad_attr[60].drive_strength.q), + .ds (), + .qs (dio_pad_attr_60_drive_strength_60_qs) + ); + assign reg2hw.dio_pad_attr[60].drive_strength.qe = dio_pad_attr_60_qe; + + + // Subregister 61 of Multireg dio_pad_attr + // R[dio_pad_attr_61]: V(True) + logic dio_pad_attr_61_qe; + logic [9:0] dio_pad_attr_61_flds_we; + assign dio_pad_attr_61_qe = &dio_pad_attr_61_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_61_gated_we; + assign dio_pad_attr_61_gated_we = dio_pad_attr_61_we & dio_pad_attr_regwen_61_qs; + // F[invert_61]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_invert_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_invert_61_wd), + .d (hw2reg.dio_pad_attr[61].invert.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[0]), + .q (reg2hw.dio_pad_attr[61].invert.q), + .ds (), + .qs (dio_pad_attr_61_invert_61_qs) + ); + assign reg2hw.dio_pad_attr[61].invert.qe = dio_pad_attr_61_qe; + + // F[virtual_od_en_61]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_virtual_od_en_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_virtual_od_en_61_wd), + .d (hw2reg.dio_pad_attr[61].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[1]), + .q (reg2hw.dio_pad_attr[61].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_61_virtual_od_en_61_qs) + ); + assign reg2hw.dio_pad_attr[61].virtual_od_en.qe = dio_pad_attr_61_qe; + + // F[pull_en_61]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_pull_en_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_pull_en_61_wd), + .d (hw2reg.dio_pad_attr[61].pull_en.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[2]), + .q (reg2hw.dio_pad_attr[61].pull_en.q), + .ds (), + .qs (dio_pad_attr_61_pull_en_61_qs) + ); + assign reg2hw.dio_pad_attr[61].pull_en.qe = dio_pad_attr_61_qe; + + // F[pull_select_61]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_pull_select_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_pull_select_61_wd), + .d (hw2reg.dio_pad_attr[61].pull_select.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[3]), + .q (reg2hw.dio_pad_attr[61].pull_select.q), + .ds (), + .qs (dio_pad_attr_61_pull_select_61_qs) + ); + assign reg2hw.dio_pad_attr[61].pull_select.qe = dio_pad_attr_61_qe; + + // F[keeper_en_61]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_keeper_en_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_keeper_en_61_wd), + .d (hw2reg.dio_pad_attr[61].keeper_en.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[4]), + .q (reg2hw.dio_pad_attr[61].keeper_en.q), + .ds (), + .qs (dio_pad_attr_61_keeper_en_61_qs) + ); + assign reg2hw.dio_pad_attr[61].keeper_en.qe = dio_pad_attr_61_qe; + + // F[schmitt_en_61]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_schmitt_en_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_schmitt_en_61_wd), + .d (hw2reg.dio_pad_attr[61].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[5]), + .q (reg2hw.dio_pad_attr[61].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_61_schmitt_en_61_qs) + ); + assign reg2hw.dio_pad_attr[61].schmitt_en.qe = dio_pad_attr_61_qe; + + // F[od_en_61]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_od_en_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_od_en_61_wd), + .d (hw2reg.dio_pad_attr[61].od_en.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[6]), + .q (reg2hw.dio_pad_attr[61].od_en.q), + .ds (), + .qs (dio_pad_attr_61_od_en_61_qs) + ); + assign reg2hw.dio_pad_attr[61].od_en.qe = dio_pad_attr_61_qe; + + // F[input_disable_61]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_input_disable_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_input_disable_61_wd), + .d (hw2reg.dio_pad_attr[61].input_disable.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[7]), + .q (reg2hw.dio_pad_attr[61].input_disable.q), + .ds (), + .qs (dio_pad_attr_61_input_disable_61_qs) + ); + assign reg2hw.dio_pad_attr[61].input_disable.qe = dio_pad_attr_61_qe; + + // F[slew_rate_61]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_61_slew_rate_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_slew_rate_61_wd), + .d (hw2reg.dio_pad_attr[61].slew_rate.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[8]), + .q (reg2hw.dio_pad_attr[61].slew_rate.q), + .ds (), + .qs (dio_pad_attr_61_slew_rate_61_qs) + ); + assign reg2hw.dio_pad_attr[61].slew_rate.qe = dio_pad_attr_61_qe; + + // F[drive_strength_61]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_61_drive_strength_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_drive_strength_61_wd), + .d (hw2reg.dio_pad_attr[61].drive_strength.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[9]), + .q (reg2hw.dio_pad_attr[61].drive_strength.q), + .ds (), + .qs (dio_pad_attr_61_drive_strength_61_qs) + ); + assign reg2hw.dio_pad_attr[61].drive_strength.qe = dio_pad_attr_61_qe; + + + // Subregister 62 of Multireg dio_pad_attr + // R[dio_pad_attr_62]: V(True) + logic dio_pad_attr_62_qe; + logic [9:0] dio_pad_attr_62_flds_we; + assign dio_pad_attr_62_qe = &dio_pad_attr_62_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_62_gated_we; + assign dio_pad_attr_62_gated_we = dio_pad_attr_62_we & dio_pad_attr_regwen_62_qs; + // F[invert_62]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_invert_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_invert_62_wd), + .d (hw2reg.dio_pad_attr[62].invert.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[0]), + .q (reg2hw.dio_pad_attr[62].invert.q), + .ds (), + .qs (dio_pad_attr_62_invert_62_qs) + ); + assign reg2hw.dio_pad_attr[62].invert.qe = dio_pad_attr_62_qe; + + // F[virtual_od_en_62]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_virtual_od_en_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_virtual_od_en_62_wd), + .d (hw2reg.dio_pad_attr[62].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[1]), + .q (reg2hw.dio_pad_attr[62].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_62_virtual_od_en_62_qs) + ); + assign reg2hw.dio_pad_attr[62].virtual_od_en.qe = dio_pad_attr_62_qe; + + // F[pull_en_62]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_pull_en_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_pull_en_62_wd), + .d (hw2reg.dio_pad_attr[62].pull_en.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[2]), + .q (reg2hw.dio_pad_attr[62].pull_en.q), + .ds (), + .qs (dio_pad_attr_62_pull_en_62_qs) + ); + assign reg2hw.dio_pad_attr[62].pull_en.qe = dio_pad_attr_62_qe; + + // F[pull_select_62]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_pull_select_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_pull_select_62_wd), + .d (hw2reg.dio_pad_attr[62].pull_select.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[3]), + .q (reg2hw.dio_pad_attr[62].pull_select.q), + .ds (), + .qs (dio_pad_attr_62_pull_select_62_qs) + ); + assign reg2hw.dio_pad_attr[62].pull_select.qe = dio_pad_attr_62_qe; + + // F[keeper_en_62]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_keeper_en_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_keeper_en_62_wd), + .d (hw2reg.dio_pad_attr[62].keeper_en.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[4]), + .q (reg2hw.dio_pad_attr[62].keeper_en.q), + .ds (), + .qs (dio_pad_attr_62_keeper_en_62_qs) + ); + assign reg2hw.dio_pad_attr[62].keeper_en.qe = dio_pad_attr_62_qe; + + // F[schmitt_en_62]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_schmitt_en_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_schmitt_en_62_wd), + .d (hw2reg.dio_pad_attr[62].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[5]), + .q (reg2hw.dio_pad_attr[62].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_62_schmitt_en_62_qs) + ); + assign reg2hw.dio_pad_attr[62].schmitt_en.qe = dio_pad_attr_62_qe; + + // F[od_en_62]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_od_en_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_od_en_62_wd), + .d (hw2reg.dio_pad_attr[62].od_en.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[6]), + .q (reg2hw.dio_pad_attr[62].od_en.q), + .ds (), + .qs (dio_pad_attr_62_od_en_62_qs) + ); + assign reg2hw.dio_pad_attr[62].od_en.qe = dio_pad_attr_62_qe; + + // F[input_disable_62]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_input_disable_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_input_disable_62_wd), + .d (hw2reg.dio_pad_attr[62].input_disable.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[7]), + .q (reg2hw.dio_pad_attr[62].input_disable.q), + .ds (), + .qs (dio_pad_attr_62_input_disable_62_qs) + ); + assign reg2hw.dio_pad_attr[62].input_disable.qe = dio_pad_attr_62_qe; + + // F[slew_rate_62]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_62_slew_rate_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_slew_rate_62_wd), + .d (hw2reg.dio_pad_attr[62].slew_rate.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[8]), + .q (reg2hw.dio_pad_attr[62].slew_rate.q), + .ds (), + .qs (dio_pad_attr_62_slew_rate_62_qs) + ); + assign reg2hw.dio_pad_attr[62].slew_rate.qe = dio_pad_attr_62_qe; + + // F[drive_strength_62]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_62_drive_strength_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_drive_strength_62_wd), + .d (hw2reg.dio_pad_attr[62].drive_strength.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[9]), + .q (reg2hw.dio_pad_attr[62].drive_strength.q), + .ds (), + .qs (dio_pad_attr_62_drive_strength_62_qs) + ); + assign reg2hw.dio_pad_attr[62].drive_strength.qe = dio_pad_attr_62_qe; + + + // Subregister 63 of Multireg dio_pad_attr + // R[dio_pad_attr_63]: V(True) + logic dio_pad_attr_63_qe; + logic [9:0] dio_pad_attr_63_flds_we; + assign dio_pad_attr_63_qe = &dio_pad_attr_63_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_63_gated_we; + assign dio_pad_attr_63_gated_we = dio_pad_attr_63_we & dio_pad_attr_regwen_63_qs; + // F[invert_63]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_invert_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_invert_63_wd), + .d (hw2reg.dio_pad_attr[63].invert.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[0]), + .q (reg2hw.dio_pad_attr[63].invert.q), + .ds (), + .qs (dio_pad_attr_63_invert_63_qs) + ); + assign reg2hw.dio_pad_attr[63].invert.qe = dio_pad_attr_63_qe; + + // F[virtual_od_en_63]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_virtual_od_en_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_virtual_od_en_63_wd), + .d (hw2reg.dio_pad_attr[63].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[1]), + .q (reg2hw.dio_pad_attr[63].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_63_virtual_od_en_63_qs) + ); + assign reg2hw.dio_pad_attr[63].virtual_od_en.qe = dio_pad_attr_63_qe; + + // F[pull_en_63]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_pull_en_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_pull_en_63_wd), + .d (hw2reg.dio_pad_attr[63].pull_en.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[2]), + .q (reg2hw.dio_pad_attr[63].pull_en.q), + .ds (), + .qs (dio_pad_attr_63_pull_en_63_qs) + ); + assign reg2hw.dio_pad_attr[63].pull_en.qe = dio_pad_attr_63_qe; + + // F[pull_select_63]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_pull_select_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_pull_select_63_wd), + .d (hw2reg.dio_pad_attr[63].pull_select.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[3]), + .q (reg2hw.dio_pad_attr[63].pull_select.q), + .ds (), + .qs (dio_pad_attr_63_pull_select_63_qs) + ); + assign reg2hw.dio_pad_attr[63].pull_select.qe = dio_pad_attr_63_qe; + + // F[keeper_en_63]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_keeper_en_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_keeper_en_63_wd), + .d (hw2reg.dio_pad_attr[63].keeper_en.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[4]), + .q (reg2hw.dio_pad_attr[63].keeper_en.q), + .ds (), + .qs (dio_pad_attr_63_keeper_en_63_qs) + ); + assign reg2hw.dio_pad_attr[63].keeper_en.qe = dio_pad_attr_63_qe; + + // F[schmitt_en_63]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_schmitt_en_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_schmitt_en_63_wd), + .d (hw2reg.dio_pad_attr[63].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[5]), + .q (reg2hw.dio_pad_attr[63].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_63_schmitt_en_63_qs) + ); + assign reg2hw.dio_pad_attr[63].schmitt_en.qe = dio_pad_attr_63_qe; + + // F[od_en_63]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_od_en_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_od_en_63_wd), + .d (hw2reg.dio_pad_attr[63].od_en.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[6]), + .q (reg2hw.dio_pad_attr[63].od_en.q), + .ds (), + .qs (dio_pad_attr_63_od_en_63_qs) + ); + assign reg2hw.dio_pad_attr[63].od_en.qe = dio_pad_attr_63_qe; + + // F[input_disable_63]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_input_disable_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_input_disable_63_wd), + .d (hw2reg.dio_pad_attr[63].input_disable.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[7]), + .q (reg2hw.dio_pad_attr[63].input_disable.q), + .ds (), + .qs (dio_pad_attr_63_input_disable_63_qs) + ); + assign reg2hw.dio_pad_attr[63].input_disable.qe = dio_pad_attr_63_qe; + + // F[slew_rate_63]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_63_slew_rate_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_slew_rate_63_wd), + .d (hw2reg.dio_pad_attr[63].slew_rate.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[8]), + .q (reg2hw.dio_pad_attr[63].slew_rate.q), + .ds (), + .qs (dio_pad_attr_63_slew_rate_63_qs) + ); + assign reg2hw.dio_pad_attr[63].slew_rate.qe = dio_pad_attr_63_qe; + + // F[drive_strength_63]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_63_drive_strength_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_drive_strength_63_wd), + .d (hw2reg.dio_pad_attr[63].drive_strength.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[9]), + .q (reg2hw.dio_pad_attr[63].drive_strength.q), + .ds (), + .qs (dio_pad_attr_63_drive_strength_63_qs) + ); + assign reg2hw.dio_pad_attr[63].drive_strength.qe = dio_pad_attr_63_qe; + + + // Subregister 64 of Multireg dio_pad_attr + // R[dio_pad_attr_64]: V(True) + logic dio_pad_attr_64_qe; + logic [9:0] dio_pad_attr_64_flds_we; + assign dio_pad_attr_64_qe = &dio_pad_attr_64_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_64_gated_we; + assign dio_pad_attr_64_gated_we = dio_pad_attr_64_we & dio_pad_attr_regwen_64_qs; + // F[invert_64]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_invert_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_invert_64_wd), + .d (hw2reg.dio_pad_attr[64].invert.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[0]), + .q (reg2hw.dio_pad_attr[64].invert.q), + .ds (), + .qs (dio_pad_attr_64_invert_64_qs) + ); + assign reg2hw.dio_pad_attr[64].invert.qe = dio_pad_attr_64_qe; + + // F[virtual_od_en_64]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_virtual_od_en_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_virtual_od_en_64_wd), + .d (hw2reg.dio_pad_attr[64].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[1]), + .q (reg2hw.dio_pad_attr[64].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_64_virtual_od_en_64_qs) + ); + assign reg2hw.dio_pad_attr[64].virtual_od_en.qe = dio_pad_attr_64_qe; + + // F[pull_en_64]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_pull_en_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_pull_en_64_wd), + .d (hw2reg.dio_pad_attr[64].pull_en.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[2]), + .q (reg2hw.dio_pad_attr[64].pull_en.q), + .ds (), + .qs (dio_pad_attr_64_pull_en_64_qs) + ); + assign reg2hw.dio_pad_attr[64].pull_en.qe = dio_pad_attr_64_qe; + + // F[pull_select_64]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_pull_select_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_pull_select_64_wd), + .d (hw2reg.dio_pad_attr[64].pull_select.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[3]), + .q (reg2hw.dio_pad_attr[64].pull_select.q), + .ds (), + .qs (dio_pad_attr_64_pull_select_64_qs) + ); + assign reg2hw.dio_pad_attr[64].pull_select.qe = dio_pad_attr_64_qe; + + // F[keeper_en_64]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_keeper_en_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_keeper_en_64_wd), + .d (hw2reg.dio_pad_attr[64].keeper_en.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[4]), + .q (reg2hw.dio_pad_attr[64].keeper_en.q), + .ds (), + .qs (dio_pad_attr_64_keeper_en_64_qs) + ); + assign reg2hw.dio_pad_attr[64].keeper_en.qe = dio_pad_attr_64_qe; + + // F[schmitt_en_64]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_schmitt_en_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_schmitt_en_64_wd), + .d (hw2reg.dio_pad_attr[64].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[5]), + .q (reg2hw.dio_pad_attr[64].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_64_schmitt_en_64_qs) + ); + assign reg2hw.dio_pad_attr[64].schmitt_en.qe = dio_pad_attr_64_qe; + + // F[od_en_64]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_od_en_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_od_en_64_wd), + .d (hw2reg.dio_pad_attr[64].od_en.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[6]), + .q (reg2hw.dio_pad_attr[64].od_en.q), + .ds (), + .qs (dio_pad_attr_64_od_en_64_qs) + ); + assign reg2hw.dio_pad_attr[64].od_en.qe = dio_pad_attr_64_qe; + + // F[input_disable_64]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_input_disable_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_input_disable_64_wd), + .d (hw2reg.dio_pad_attr[64].input_disable.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[7]), + .q (reg2hw.dio_pad_attr[64].input_disable.q), + .ds (), + .qs (dio_pad_attr_64_input_disable_64_qs) + ); + assign reg2hw.dio_pad_attr[64].input_disable.qe = dio_pad_attr_64_qe; + + // F[slew_rate_64]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_64_slew_rate_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_slew_rate_64_wd), + .d (hw2reg.dio_pad_attr[64].slew_rate.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[8]), + .q (reg2hw.dio_pad_attr[64].slew_rate.q), + .ds (), + .qs (dio_pad_attr_64_slew_rate_64_qs) + ); + assign reg2hw.dio_pad_attr[64].slew_rate.qe = dio_pad_attr_64_qe; + + // F[drive_strength_64]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_64_drive_strength_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_drive_strength_64_wd), + .d (hw2reg.dio_pad_attr[64].drive_strength.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[9]), + .q (reg2hw.dio_pad_attr[64].drive_strength.q), + .ds (), + .qs (dio_pad_attr_64_drive_strength_64_qs) + ); + assign reg2hw.dio_pad_attr[64].drive_strength.qe = dio_pad_attr_64_qe; + + + // Subregister 65 of Multireg dio_pad_attr + // R[dio_pad_attr_65]: V(True) + logic dio_pad_attr_65_qe; + logic [9:0] dio_pad_attr_65_flds_we; + assign dio_pad_attr_65_qe = &dio_pad_attr_65_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_65_gated_we; + assign dio_pad_attr_65_gated_we = dio_pad_attr_65_we & dio_pad_attr_regwen_65_qs; + // F[invert_65]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_invert_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_invert_65_wd), + .d (hw2reg.dio_pad_attr[65].invert.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[0]), + .q (reg2hw.dio_pad_attr[65].invert.q), + .ds (), + .qs (dio_pad_attr_65_invert_65_qs) + ); + assign reg2hw.dio_pad_attr[65].invert.qe = dio_pad_attr_65_qe; + + // F[virtual_od_en_65]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_virtual_od_en_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_virtual_od_en_65_wd), + .d (hw2reg.dio_pad_attr[65].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[1]), + .q (reg2hw.dio_pad_attr[65].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_65_virtual_od_en_65_qs) + ); + assign reg2hw.dio_pad_attr[65].virtual_od_en.qe = dio_pad_attr_65_qe; + + // F[pull_en_65]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_pull_en_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_pull_en_65_wd), + .d (hw2reg.dio_pad_attr[65].pull_en.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[2]), + .q (reg2hw.dio_pad_attr[65].pull_en.q), + .ds (), + .qs (dio_pad_attr_65_pull_en_65_qs) + ); + assign reg2hw.dio_pad_attr[65].pull_en.qe = dio_pad_attr_65_qe; + + // F[pull_select_65]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_pull_select_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_pull_select_65_wd), + .d (hw2reg.dio_pad_attr[65].pull_select.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[3]), + .q (reg2hw.dio_pad_attr[65].pull_select.q), + .ds (), + .qs (dio_pad_attr_65_pull_select_65_qs) + ); + assign reg2hw.dio_pad_attr[65].pull_select.qe = dio_pad_attr_65_qe; + + // F[keeper_en_65]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_keeper_en_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_keeper_en_65_wd), + .d (hw2reg.dio_pad_attr[65].keeper_en.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[4]), + .q (reg2hw.dio_pad_attr[65].keeper_en.q), + .ds (), + .qs (dio_pad_attr_65_keeper_en_65_qs) + ); + assign reg2hw.dio_pad_attr[65].keeper_en.qe = dio_pad_attr_65_qe; + + // F[schmitt_en_65]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_schmitt_en_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_schmitt_en_65_wd), + .d (hw2reg.dio_pad_attr[65].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[5]), + .q (reg2hw.dio_pad_attr[65].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_65_schmitt_en_65_qs) + ); + assign reg2hw.dio_pad_attr[65].schmitt_en.qe = dio_pad_attr_65_qe; + + // F[od_en_65]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_od_en_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_od_en_65_wd), + .d (hw2reg.dio_pad_attr[65].od_en.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[6]), + .q (reg2hw.dio_pad_attr[65].od_en.q), + .ds (), + .qs (dio_pad_attr_65_od_en_65_qs) + ); + assign reg2hw.dio_pad_attr[65].od_en.qe = dio_pad_attr_65_qe; + + // F[input_disable_65]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_input_disable_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_input_disable_65_wd), + .d (hw2reg.dio_pad_attr[65].input_disable.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[7]), + .q (reg2hw.dio_pad_attr[65].input_disable.q), + .ds (), + .qs (dio_pad_attr_65_input_disable_65_qs) + ); + assign reg2hw.dio_pad_attr[65].input_disable.qe = dio_pad_attr_65_qe; + + // F[slew_rate_65]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_65_slew_rate_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_slew_rate_65_wd), + .d (hw2reg.dio_pad_attr[65].slew_rate.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[8]), + .q (reg2hw.dio_pad_attr[65].slew_rate.q), + .ds (), + .qs (dio_pad_attr_65_slew_rate_65_qs) + ); + assign reg2hw.dio_pad_attr[65].slew_rate.qe = dio_pad_attr_65_qe; + + // F[drive_strength_65]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_65_drive_strength_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_drive_strength_65_wd), + .d (hw2reg.dio_pad_attr[65].drive_strength.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[9]), + .q (reg2hw.dio_pad_attr[65].drive_strength.q), + .ds (), + .qs (dio_pad_attr_65_drive_strength_65_qs) + ); + assign reg2hw.dio_pad_attr[65].drive_strength.qe = dio_pad_attr_65_qe; + + + // Subregister 66 of Multireg dio_pad_attr + // R[dio_pad_attr_66]: V(True) + logic dio_pad_attr_66_qe; + logic [9:0] dio_pad_attr_66_flds_we; + assign dio_pad_attr_66_qe = &dio_pad_attr_66_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_66_gated_we; + assign dio_pad_attr_66_gated_we = dio_pad_attr_66_we & dio_pad_attr_regwen_66_qs; + // F[invert_66]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_invert_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_invert_66_wd), + .d (hw2reg.dio_pad_attr[66].invert.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[0]), + .q (reg2hw.dio_pad_attr[66].invert.q), + .ds (), + .qs (dio_pad_attr_66_invert_66_qs) + ); + assign reg2hw.dio_pad_attr[66].invert.qe = dio_pad_attr_66_qe; + + // F[virtual_od_en_66]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_virtual_od_en_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_virtual_od_en_66_wd), + .d (hw2reg.dio_pad_attr[66].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[1]), + .q (reg2hw.dio_pad_attr[66].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_66_virtual_od_en_66_qs) + ); + assign reg2hw.dio_pad_attr[66].virtual_od_en.qe = dio_pad_attr_66_qe; + + // F[pull_en_66]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_pull_en_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_pull_en_66_wd), + .d (hw2reg.dio_pad_attr[66].pull_en.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[2]), + .q (reg2hw.dio_pad_attr[66].pull_en.q), + .ds (), + .qs (dio_pad_attr_66_pull_en_66_qs) + ); + assign reg2hw.dio_pad_attr[66].pull_en.qe = dio_pad_attr_66_qe; + + // F[pull_select_66]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_pull_select_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_pull_select_66_wd), + .d (hw2reg.dio_pad_attr[66].pull_select.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[3]), + .q (reg2hw.dio_pad_attr[66].pull_select.q), + .ds (), + .qs (dio_pad_attr_66_pull_select_66_qs) + ); + assign reg2hw.dio_pad_attr[66].pull_select.qe = dio_pad_attr_66_qe; + + // F[keeper_en_66]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_keeper_en_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_keeper_en_66_wd), + .d (hw2reg.dio_pad_attr[66].keeper_en.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[4]), + .q (reg2hw.dio_pad_attr[66].keeper_en.q), + .ds (), + .qs (dio_pad_attr_66_keeper_en_66_qs) + ); + assign reg2hw.dio_pad_attr[66].keeper_en.qe = dio_pad_attr_66_qe; + + // F[schmitt_en_66]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_schmitt_en_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_schmitt_en_66_wd), + .d (hw2reg.dio_pad_attr[66].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[5]), + .q (reg2hw.dio_pad_attr[66].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_66_schmitt_en_66_qs) + ); + assign reg2hw.dio_pad_attr[66].schmitt_en.qe = dio_pad_attr_66_qe; + + // F[od_en_66]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_od_en_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_od_en_66_wd), + .d (hw2reg.dio_pad_attr[66].od_en.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[6]), + .q (reg2hw.dio_pad_attr[66].od_en.q), + .ds (), + .qs (dio_pad_attr_66_od_en_66_qs) + ); + assign reg2hw.dio_pad_attr[66].od_en.qe = dio_pad_attr_66_qe; + + // F[input_disable_66]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_input_disable_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_input_disable_66_wd), + .d (hw2reg.dio_pad_attr[66].input_disable.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[7]), + .q (reg2hw.dio_pad_attr[66].input_disable.q), + .ds (), + .qs (dio_pad_attr_66_input_disable_66_qs) + ); + assign reg2hw.dio_pad_attr[66].input_disable.qe = dio_pad_attr_66_qe; + + // F[slew_rate_66]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_66_slew_rate_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_slew_rate_66_wd), + .d (hw2reg.dio_pad_attr[66].slew_rate.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[8]), + .q (reg2hw.dio_pad_attr[66].slew_rate.q), + .ds (), + .qs (dio_pad_attr_66_slew_rate_66_qs) + ); + assign reg2hw.dio_pad_attr[66].slew_rate.qe = dio_pad_attr_66_qe; + + // F[drive_strength_66]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_66_drive_strength_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_drive_strength_66_wd), + .d (hw2reg.dio_pad_attr[66].drive_strength.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[9]), + .q (reg2hw.dio_pad_attr[66].drive_strength.q), + .ds (), + .qs (dio_pad_attr_66_drive_strength_66_qs) + ); + assign reg2hw.dio_pad_attr[66].drive_strength.qe = dio_pad_attr_66_qe; + + + // Subregister 67 of Multireg dio_pad_attr + // R[dio_pad_attr_67]: V(True) + logic dio_pad_attr_67_qe; + logic [9:0] dio_pad_attr_67_flds_we; + assign dio_pad_attr_67_qe = &dio_pad_attr_67_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_67_gated_we; + assign dio_pad_attr_67_gated_we = dio_pad_attr_67_we & dio_pad_attr_regwen_67_qs; + // F[invert_67]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_invert_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_invert_67_wd), + .d (hw2reg.dio_pad_attr[67].invert.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[0]), + .q (reg2hw.dio_pad_attr[67].invert.q), + .ds (), + .qs (dio_pad_attr_67_invert_67_qs) + ); + assign reg2hw.dio_pad_attr[67].invert.qe = dio_pad_attr_67_qe; + + // F[virtual_od_en_67]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_virtual_od_en_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_virtual_od_en_67_wd), + .d (hw2reg.dio_pad_attr[67].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[1]), + .q (reg2hw.dio_pad_attr[67].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_67_virtual_od_en_67_qs) + ); + assign reg2hw.dio_pad_attr[67].virtual_od_en.qe = dio_pad_attr_67_qe; + + // F[pull_en_67]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_pull_en_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_pull_en_67_wd), + .d (hw2reg.dio_pad_attr[67].pull_en.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[2]), + .q (reg2hw.dio_pad_attr[67].pull_en.q), + .ds (), + .qs (dio_pad_attr_67_pull_en_67_qs) + ); + assign reg2hw.dio_pad_attr[67].pull_en.qe = dio_pad_attr_67_qe; + + // F[pull_select_67]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_pull_select_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_pull_select_67_wd), + .d (hw2reg.dio_pad_attr[67].pull_select.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[3]), + .q (reg2hw.dio_pad_attr[67].pull_select.q), + .ds (), + .qs (dio_pad_attr_67_pull_select_67_qs) + ); + assign reg2hw.dio_pad_attr[67].pull_select.qe = dio_pad_attr_67_qe; + + // F[keeper_en_67]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_keeper_en_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_keeper_en_67_wd), + .d (hw2reg.dio_pad_attr[67].keeper_en.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[4]), + .q (reg2hw.dio_pad_attr[67].keeper_en.q), + .ds (), + .qs (dio_pad_attr_67_keeper_en_67_qs) + ); + assign reg2hw.dio_pad_attr[67].keeper_en.qe = dio_pad_attr_67_qe; + + // F[schmitt_en_67]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_schmitt_en_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_schmitt_en_67_wd), + .d (hw2reg.dio_pad_attr[67].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[5]), + .q (reg2hw.dio_pad_attr[67].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_67_schmitt_en_67_qs) + ); + assign reg2hw.dio_pad_attr[67].schmitt_en.qe = dio_pad_attr_67_qe; + + // F[od_en_67]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_od_en_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_od_en_67_wd), + .d (hw2reg.dio_pad_attr[67].od_en.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[6]), + .q (reg2hw.dio_pad_attr[67].od_en.q), + .ds (), + .qs (dio_pad_attr_67_od_en_67_qs) + ); + assign reg2hw.dio_pad_attr[67].od_en.qe = dio_pad_attr_67_qe; + + // F[input_disable_67]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_input_disable_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_input_disable_67_wd), + .d (hw2reg.dio_pad_attr[67].input_disable.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[7]), + .q (reg2hw.dio_pad_attr[67].input_disable.q), + .ds (), + .qs (dio_pad_attr_67_input_disable_67_qs) + ); + assign reg2hw.dio_pad_attr[67].input_disable.qe = dio_pad_attr_67_qe; + + // F[slew_rate_67]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_67_slew_rate_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_slew_rate_67_wd), + .d (hw2reg.dio_pad_attr[67].slew_rate.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[8]), + .q (reg2hw.dio_pad_attr[67].slew_rate.q), + .ds (), + .qs (dio_pad_attr_67_slew_rate_67_qs) + ); + assign reg2hw.dio_pad_attr[67].slew_rate.qe = dio_pad_attr_67_qe; + + // F[drive_strength_67]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_67_drive_strength_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_drive_strength_67_wd), + .d (hw2reg.dio_pad_attr[67].drive_strength.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[9]), + .q (reg2hw.dio_pad_attr[67].drive_strength.q), + .ds (), + .qs (dio_pad_attr_67_drive_strength_67_qs) + ); + assign reg2hw.dio_pad_attr[67].drive_strength.qe = dio_pad_attr_67_qe; + + + // Subregister 68 of Multireg dio_pad_attr + // R[dio_pad_attr_68]: V(True) + logic dio_pad_attr_68_qe; + logic [9:0] dio_pad_attr_68_flds_we; + assign dio_pad_attr_68_qe = &dio_pad_attr_68_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_68_gated_we; + assign dio_pad_attr_68_gated_we = dio_pad_attr_68_we & dio_pad_attr_regwen_68_qs; + // F[invert_68]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_invert_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_invert_68_wd), + .d (hw2reg.dio_pad_attr[68].invert.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[0]), + .q (reg2hw.dio_pad_attr[68].invert.q), + .ds (), + .qs (dio_pad_attr_68_invert_68_qs) + ); + assign reg2hw.dio_pad_attr[68].invert.qe = dio_pad_attr_68_qe; + + // F[virtual_od_en_68]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_virtual_od_en_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_virtual_od_en_68_wd), + .d (hw2reg.dio_pad_attr[68].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[1]), + .q (reg2hw.dio_pad_attr[68].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_68_virtual_od_en_68_qs) + ); + assign reg2hw.dio_pad_attr[68].virtual_od_en.qe = dio_pad_attr_68_qe; + + // F[pull_en_68]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_pull_en_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_pull_en_68_wd), + .d (hw2reg.dio_pad_attr[68].pull_en.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[2]), + .q (reg2hw.dio_pad_attr[68].pull_en.q), + .ds (), + .qs (dio_pad_attr_68_pull_en_68_qs) + ); + assign reg2hw.dio_pad_attr[68].pull_en.qe = dio_pad_attr_68_qe; + + // F[pull_select_68]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_pull_select_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_pull_select_68_wd), + .d (hw2reg.dio_pad_attr[68].pull_select.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[3]), + .q (reg2hw.dio_pad_attr[68].pull_select.q), + .ds (), + .qs (dio_pad_attr_68_pull_select_68_qs) + ); + assign reg2hw.dio_pad_attr[68].pull_select.qe = dio_pad_attr_68_qe; + + // F[keeper_en_68]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_keeper_en_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_keeper_en_68_wd), + .d (hw2reg.dio_pad_attr[68].keeper_en.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[4]), + .q (reg2hw.dio_pad_attr[68].keeper_en.q), + .ds (), + .qs (dio_pad_attr_68_keeper_en_68_qs) + ); + assign reg2hw.dio_pad_attr[68].keeper_en.qe = dio_pad_attr_68_qe; + + // F[schmitt_en_68]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_schmitt_en_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_schmitt_en_68_wd), + .d (hw2reg.dio_pad_attr[68].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[5]), + .q (reg2hw.dio_pad_attr[68].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_68_schmitt_en_68_qs) + ); + assign reg2hw.dio_pad_attr[68].schmitt_en.qe = dio_pad_attr_68_qe; + + // F[od_en_68]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_od_en_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_od_en_68_wd), + .d (hw2reg.dio_pad_attr[68].od_en.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[6]), + .q (reg2hw.dio_pad_attr[68].od_en.q), + .ds (), + .qs (dio_pad_attr_68_od_en_68_qs) + ); + assign reg2hw.dio_pad_attr[68].od_en.qe = dio_pad_attr_68_qe; + + // F[input_disable_68]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_input_disable_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_input_disable_68_wd), + .d (hw2reg.dio_pad_attr[68].input_disable.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[7]), + .q (reg2hw.dio_pad_attr[68].input_disable.q), + .ds (), + .qs (dio_pad_attr_68_input_disable_68_qs) + ); + assign reg2hw.dio_pad_attr[68].input_disable.qe = dio_pad_attr_68_qe; + + // F[slew_rate_68]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_68_slew_rate_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_slew_rate_68_wd), + .d (hw2reg.dio_pad_attr[68].slew_rate.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[8]), + .q (reg2hw.dio_pad_attr[68].slew_rate.q), + .ds (), + .qs (dio_pad_attr_68_slew_rate_68_qs) + ); + assign reg2hw.dio_pad_attr[68].slew_rate.qe = dio_pad_attr_68_qe; + + // F[drive_strength_68]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_68_drive_strength_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_drive_strength_68_wd), + .d (hw2reg.dio_pad_attr[68].drive_strength.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[9]), + .q (reg2hw.dio_pad_attr[68].drive_strength.q), + .ds (), + .qs (dio_pad_attr_68_drive_strength_68_qs) + ); + assign reg2hw.dio_pad_attr[68].drive_strength.qe = dio_pad_attr_68_qe; + + + // Subregister 69 of Multireg dio_pad_attr + // R[dio_pad_attr_69]: V(True) + logic dio_pad_attr_69_qe; + logic [9:0] dio_pad_attr_69_flds_we; + assign dio_pad_attr_69_qe = &dio_pad_attr_69_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_69_gated_we; + assign dio_pad_attr_69_gated_we = dio_pad_attr_69_we & dio_pad_attr_regwen_69_qs; + // F[invert_69]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_invert_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_invert_69_wd), + .d (hw2reg.dio_pad_attr[69].invert.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[0]), + .q (reg2hw.dio_pad_attr[69].invert.q), + .ds (), + .qs (dio_pad_attr_69_invert_69_qs) + ); + assign reg2hw.dio_pad_attr[69].invert.qe = dio_pad_attr_69_qe; + + // F[virtual_od_en_69]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_virtual_od_en_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_virtual_od_en_69_wd), + .d (hw2reg.dio_pad_attr[69].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[1]), + .q (reg2hw.dio_pad_attr[69].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_69_virtual_od_en_69_qs) + ); + assign reg2hw.dio_pad_attr[69].virtual_od_en.qe = dio_pad_attr_69_qe; + + // F[pull_en_69]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_pull_en_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_pull_en_69_wd), + .d (hw2reg.dio_pad_attr[69].pull_en.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[2]), + .q (reg2hw.dio_pad_attr[69].pull_en.q), + .ds (), + .qs (dio_pad_attr_69_pull_en_69_qs) + ); + assign reg2hw.dio_pad_attr[69].pull_en.qe = dio_pad_attr_69_qe; + + // F[pull_select_69]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_pull_select_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_pull_select_69_wd), + .d (hw2reg.dio_pad_attr[69].pull_select.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[3]), + .q (reg2hw.dio_pad_attr[69].pull_select.q), + .ds (), + .qs (dio_pad_attr_69_pull_select_69_qs) + ); + assign reg2hw.dio_pad_attr[69].pull_select.qe = dio_pad_attr_69_qe; + + // F[keeper_en_69]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_keeper_en_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_keeper_en_69_wd), + .d (hw2reg.dio_pad_attr[69].keeper_en.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[4]), + .q (reg2hw.dio_pad_attr[69].keeper_en.q), + .ds (), + .qs (dio_pad_attr_69_keeper_en_69_qs) + ); + assign reg2hw.dio_pad_attr[69].keeper_en.qe = dio_pad_attr_69_qe; + + // F[schmitt_en_69]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_schmitt_en_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_schmitt_en_69_wd), + .d (hw2reg.dio_pad_attr[69].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[5]), + .q (reg2hw.dio_pad_attr[69].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_69_schmitt_en_69_qs) + ); + assign reg2hw.dio_pad_attr[69].schmitt_en.qe = dio_pad_attr_69_qe; + + // F[od_en_69]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_od_en_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_od_en_69_wd), + .d (hw2reg.dio_pad_attr[69].od_en.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[6]), + .q (reg2hw.dio_pad_attr[69].od_en.q), + .ds (), + .qs (dio_pad_attr_69_od_en_69_qs) + ); + assign reg2hw.dio_pad_attr[69].od_en.qe = dio_pad_attr_69_qe; + + // F[input_disable_69]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_input_disable_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_input_disable_69_wd), + .d (hw2reg.dio_pad_attr[69].input_disable.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[7]), + .q (reg2hw.dio_pad_attr[69].input_disable.q), + .ds (), + .qs (dio_pad_attr_69_input_disable_69_qs) + ); + assign reg2hw.dio_pad_attr[69].input_disable.qe = dio_pad_attr_69_qe; + + // F[slew_rate_69]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_69_slew_rate_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_slew_rate_69_wd), + .d (hw2reg.dio_pad_attr[69].slew_rate.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[8]), + .q (reg2hw.dio_pad_attr[69].slew_rate.q), + .ds (), + .qs (dio_pad_attr_69_slew_rate_69_qs) + ); + assign reg2hw.dio_pad_attr[69].slew_rate.qe = dio_pad_attr_69_qe; + + // F[drive_strength_69]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_69_drive_strength_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_drive_strength_69_wd), + .d (hw2reg.dio_pad_attr[69].drive_strength.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[9]), + .q (reg2hw.dio_pad_attr[69].drive_strength.q), + .ds (), + .qs (dio_pad_attr_69_drive_strength_69_qs) + ); + assign reg2hw.dio_pad_attr[69].drive_strength.qe = dio_pad_attr_69_qe; + + + // Subregister 70 of Multireg dio_pad_attr + // R[dio_pad_attr_70]: V(True) + logic dio_pad_attr_70_qe; + logic [9:0] dio_pad_attr_70_flds_we; + assign dio_pad_attr_70_qe = &dio_pad_attr_70_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_70_gated_we; + assign dio_pad_attr_70_gated_we = dio_pad_attr_70_we & dio_pad_attr_regwen_70_qs; + // F[invert_70]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_invert_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_invert_70_wd), + .d (hw2reg.dio_pad_attr[70].invert.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[0]), + .q (reg2hw.dio_pad_attr[70].invert.q), + .ds (), + .qs (dio_pad_attr_70_invert_70_qs) + ); + assign reg2hw.dio_pad_attr[70].invert.qe = dio_pad_attr_70_qe; + + // F[virtual_od_en_70]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_virtual_od_en_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_virtual_od_en_70_wd), + .d (hw2reg.dio_pad_attr[70].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[1]), + .q (reg2hw.dio_pad_attr[70].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_70_virtual_od_en_70_qs) + ); + assign reg2hw.dio_pad_attr[70].virtual_od_en.qe = dio_pad_attr_70_qe; + + // F[pull_en_70]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_pull_en_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_pull_en_70_wd), + .d (hw2reg.dio_pad_attr[70].pull_en.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[2]), + .q (reg2hw.dio_pad_attr[70].pull_en.q), + .ds (), + .qs (dio_pad_attr_70_pull_en_70_qs) + ); + assign reg2hw.dio_pad_attr[70].pull_en.qe = dio_pad_attr_70_qe; + + // F[pull_select_70]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_pull_select_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_pull_select_70_wd), + .d (hw2reg.dio_pad_attr[70].pull_select.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[3]), + .q (reg2hw.dio_pad_attr[70].pull_select.q), + .ds (), + .qs (dio_pad_attr_70_pull_select_70_qs) + ); + assign reg2hw.dio_pad_attr[70].pull_select.qe = dio_pad_attr_70_qe; + + // F[keeper_en_70]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_keeper_en_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_keeper_en_70_wd), + .d (hw2reg.dio_pad_attr[70].keeper_en.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[4]), + .q (reg2hw.dio_pad_attr[70].keeper_en.q), + .ds (), + .qs (dio_pad_attr_70_keeper_en_70_qs) + ); + assign reg2hw.dio_pad_attr[70].keeper_en.qe = dio_pad_attr_70_qe; + + // F[schmitt_en_70]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_schmitt_en_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_schmitt_en_70_wd), + .d (hw2reg.dio_pad_attr[70].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[5]), + .q (reg2hw.dio_pad_attr[70].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_70_schmitt_en_70_qs) + ); + assign reg2hw.dio_pad_attr[70].schmitt_en.qe = dio_pad_attr_70_qe; + + // F[od_en_70]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_od_en_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_od_en_70_wd), + .d (hw2reg.dio_pad_attr[70].od_en.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[6]), + .q (reg2hw.dio_pad_attr[70].od_en.q), + .ds (), + .qs (dio_pad_attr_70_od_en_70_qs) + ); + assign reg2hw.dio_pad_attr[70].od_en.qe = dio_pad_attr_70_qe; + + // F[input_disable_70]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_input_disable_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_input_disable_70_wd), + .d (hw2reg.dio_pad_attr[70].input_disable.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[7]), + .q (reg2hw.dio_pad_attr[70].input_disable.q), + .ds (), + .qs (dio_pad_attr_70_input_disable_70_qs) + ); + assign reg2hw.dio_pad_attr[70].input_disable.qe = dio_pad_attr_70_qe; + + // F[slew_rate_70]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_70_slew_rate_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_slew_rate_70_wd), + .d (hw2reg.dio_pad_attr[70].slew_rate.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[8]), + .q (reg2hw.dio_pad_attr[70].slew_rate.q), + .ds (), + .qs (dio_pad_attr_70_slew_rate_70_qs) + ); + assign reg2hw.dio_pad_attr[70].slew_rate.qe = dio_pad_attr_70_qe; + + // F[drive_strength_70]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_70_drive_strength_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_drive_strength_70_wd), + .d (hw2reg.dio_pad_attr[70].drive_strength.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[9]), + .q (reg2hw.dio_pad_attr[70].drive_strength.q), + .ds (), + .qs (dio_pad_attr_70_drive_strength_70_qs) + ); + assign reg2hw.dio_pad_attr[70].drive_strength.qe = dio_pad_attr_70_qe; + + + // Subregister 71 of Multireg dio_pad_attr + // R[dio_pad_attr_71]: V(True) + logic dio_pad_attr_71_qe; + logic [9:0] dio_pad_attr_71_flds_we; + assign dio_pad_attr_71_qe = &dio_pad_attr_71_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_71_gated_we; + assign dio_pad_attr_71_gated_we = dio_pad_attr_71_we & dio_pad_attr_regwen_71_qs; + // F[invert_71]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_invert_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_invert_71_wd), + .d (hw2reg.dio_pad_attr[71].invert.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[0]), + .q (reg2hw.dio_pad_attr[71].invert.q), + .ds (), + .qs (dio_pad_attr_71_invert_71_qs) + ); + assign reg2hw.dio_pad_attr[71].invert.qe = dio_pad_attr_71_qe; + + // F[virtual_od_en_71]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_virtual_od_en_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_virtual_od_en_71_wd), + .d (hw2reg.dio_pad_attr[71].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[1]), + .q (reg2hw.dio_pad_attr[71].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_71_virtual_od_en_71_qs) + ); + assign reg2hw.dio_pad_attr[71].virtual_od_en.qe = dio_pad_attr_71_qe; + + // F[pull_en_71]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_pull_en_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_pull_en_71_wd), + .d (hw2reg.dio_pad_attr[71].pull_en.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[2]), + .q (reg2hw.dio_pad_attr[71].pull_en.q), + .ds (), + .qs (dio_pad_attr_71_pull_en_71_qs) + ); + assign reg2hw.dio_pad_attr[71].pull_en.qe = dio_pad_attr_71_qe; + + // F[pull_select_71]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_pull_select_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_pull_select_71_wd), + .d (hw2reg.dio_pad_attr[71].pull_select.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[3]), + .q (reg2hw.dio_pad_attr[71].pull_select.q), + .ds (), + .qs (dio_pad_attr_71_pull_select_71_qs) + ); + assign reg2hw.dio_pad_attr[71].pull_select.qe = dio_pad_attr_71_qe; + + // F[keeper_en_71]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_keeper_en_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_keeper_en_71_wd), + .d (hw2reg.dio_pad_attr[71].keeper_en.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[4]), + .q (reg2hw.dio_pad_attr[71].keeper_en.q), + .ds (), + .qs (dio_pad_attr_71_keeper_en_71_qs) + ); + assign reg2hw.dio_pad_attr[71].keeper_en.qe = dio_pad_attr_71_qe; + + // F[schmitt_en_71]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_schmitt_en_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_schmitt_en_71_wd), + .d (hw2reg.dio_pad_attr[71].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[5]), + .q (reg2hw.dio_pad_attr[71].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_71_schmitt_en_71_qs) + ); + assign reg2hw.dio_pad_attr[71].schmitt_en.qe = dio_pad_attr_71_qe; + + // F[od_en_71]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_od_en_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_od_en_71_wd), + .d (hw2reg.dio_pad_attr[71].od_en.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[6]), + .q (reg2hw.dio_pad_attr[71].od_en.q), + .ds (), + .qs (dio_pad_attr_71_od_en_71_qs) + ); + assign reg2hw.dio_pad_attr[71].od_en.qe = dio_pad_attr_71_qe; + + // F[input_disable_71]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_input_disable_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_input_disable_71_wd), + .d (hw2reg.dio_pad_attr[71].input_disable.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[7]), + .q (reg2hw.dio_pad_attr[71].input_disable.q), + .ds (), + .qs (dio_pad_attr_71_input_disable_71_qs) + ); + assign reg2hw.dio_pad_attr[71].input_disable.qe = dio_pad_attr_71_qe; + + // F[slew_rate_71]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_71_slew_rate_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_slew_rate_71_wd), + .d (hw2reg.dio_pad_attr[71].slew_rate.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[8]), + .q (reg2hw.dio_pad_attr[71].slew_rate.q), + .ds (), + .qs (dio_pad_attr_71_slew_rate_71_qs) + ); + assign reg2hw.dio_pad_attr[71].slew_rate.qe = dio_pad_attr_71_qe; + + // F[drive_strength_71]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_71_drive_strength_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_drive_strength_71_wd), + .d (hw2reg.dio_pad_attr[71].drive_strength.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[9]), + .q (reg2hw.dio_pad_attr[71].drive_strength.q), + .ds (), + .qs (dio_pad_attr_71_drive_strength_71_qs) + ); + assign reg2hw.dio_pad_attr[71].drive_strength.qe = dio_pad_attr_71_qe; + + + // Subregister 72 of Multireg dio_pad_attr + // R[dio_pad_attr_72]: V(True) + logic dio_pad_attr_72_qe; + logic [9:0] dio_pad_attr_72_flds_we; + assign dio_pad_attr_72_qe = &dio_pad_attr_72_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_72_gated_we; + assign dio_pad_attr_72_gated_we = dio_pad_attr_72_we & dio_pad_attr_regwen_72_qs; + // F[invert_72]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_invert_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_invert_72_wd), + .d (hw2reg.dio_pad_attr[72].invert.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[0]), + .q (reg2hw.dio_pad_attr[72].invert.q), + .ds (), + .qs (dio_pad_attr_72_invert_72_qs) + ); + assign reg2hw.dio_pad_attr[72].invert.qe = dio_pad_attr_72_qe; + + // F[virtual_od_en_72]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_virtual_od_en_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_virtual_od_en_72_wd), + .d (hw2reg.dio_pad_attr[72].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[1]), + .q (reg2hw.dio_pad_attr[72].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_72_virtual_od_en_72_qs) + ); + assign reg2hw.dio_pad_attr[72].virtual_od_en.qe = dio_pad_attr_72_qe; + + // F[pull_en_72]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_pull_en_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_pull_en_72_wd), + .d (hw2reg.dio_pad_attr[72].pull_en.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[2]), + .q (reg2hw.dio_pad_attr[72].pull_en.q), + .ds (), + .qs (dio_pad_attr_72_pull_en_72_qs) + ); + assign reg2hw.dio_pad_attr[72].pull_en.qe = dio_pad_attr_72_qe; + + // F[pull_select_72]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_pull_select_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_pull_select_72_wd), + .d (hw2reg.dio_pad_attr[72].pull_select.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[3]), + .q (reg2hw.dio_pad_attr[72].pull_select.q), + .ds (), + .qs (dio_pad_attr_72_pull_select_72_qs) + ); + assign reg2hw.dio_pad_attr[72].pull_select.qe = dio_pad_attr_72_qe; + + // F[keeper_en_72]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_keeper_en_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_keeper_en_72_wd), + .d (hw2reg.dio_pad_attr[72].keeper_en.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[4]), + .q (reg2hw.dio_pad_attr[72].keeper_en.q), + .ds (), + .qs (dio_pad_attr_72_keeper_en_72_qs) + ); + assign reg2hw.dio_pad_attr[72].keeper_en.qe = dio_pad_attr_72_qe; + + // F[schmitt_en_72]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_schmitt_en_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_schmitt_en_72_wd), + .d (hw2reg.dio_pad_attr[72].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[5]), + .q (reg2hw.dio_pad_attr[72].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_72_schmitt_en_72_qs) + ); + assign reg2hw.dio_pad_attr[72].schmitt_en.qe = dio_pad_attr_72_qe; + + // F[od_en_72]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_od_en_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_od_en_72_wd), + .d (hw2reg.dio_pad_attr[72].od_en.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[6]), + .q (reg2hw.dio_pad_attr[72].od_en.q), + .ds (), + .qs (dio_pad_attr_72_od_en_72_qs) + ); + assign reg2hw.dio_pad_attr[72].od_en.qe = dio_pad_attr_72_qe; + + // F[input_disable_72]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_input_disable_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_input_disable_72_wd), + .d (hw2reg.dio_pad_attr[72].input_disable.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[7]), + .q (reg2hw.dio_pad_attr[72].input_disable.q), + .ds (), + .qs (dio_pad_attr_72_input_disable_72_qs) + ); + assign reg2hw.dio_pad_attr[72].input_disable.qe = dio_pad_attr_72_qe; + + // F[slew_rate_72]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_72_slew_rate_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_slew_rate_72_wd), + .d (hw2reg.dio_pad_attr[72].slew_rate.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[8]), + .q (reg2hw.dio_pad_attr[72].slew_rate.q), + .ds (), + .qs (dio_pad_attr_72_slew_rate_72_qs) + ); + assign reg2hw.dio_pad_attr[72].slew_rate.qe = dio_pad_attr_72_qe; + + // F[drive_strength_72]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_72_drive_strength_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_drive_strength_72_wd), + .d (hw2reg.dio_pad_attr[72].drive_strength.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[9]), + .q (reg2hw.dio_pad_attr[72].drive_strength.q), + .ds (), + .qs (dio_pad_attr_72_drive_strength_72_qs) + ); + assign reg2hw.dio_pad_attr[72].drive_strength.qe = dio_pad_attr_72_qe; + + + // Subregister 0 of Multireg mio_pad_sleep_status + // R[mio_pad_sleep_status]: V(False) + // F[en_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_0_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[0].de), + .d (hw2reg.mio_pad_sleep_status[0].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[0].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_0_qs) + ); + + // F[en_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_1_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[1].de), + .d (hw2reg.mio_pad_sleep_status[1].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[1].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_1_qs) + ); + + // F[en_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_2_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[2].de), + .d (hw2reg.mio_pad_sleep_status[2].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[2].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_2_qs) + ); + + // F[en_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_3_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[3].de), + .d (hw2reg.mio_pad_sleep_status[3].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[3].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_3_qs) + ); + + // F[en_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_4_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[4].de), + .d (hw2reg.mio_pad_sleep_status[4].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[4].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_4_qs) + ); + + // F[en_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_5_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[5].de), + .d (hw2reg.mio_pad_sleep_status[5].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[5].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_5_qs) + ); + + // F[en_6]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_6_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[6].de), + .d (hw2reg.mio_pad_sleep_status[6].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[6].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_6_qs) + ); + + // F[en_7]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_7_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[7].de), + .d (hw2reg.mio_pad_sleep_status[7].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[7].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_7_qs) + ); + + // F[en_8]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_8_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[8].de), + .d (hw2reg.mio_pad_sleep_status[8].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[8].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_8_qs) + ); + + // F[en_9]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_9_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[9].de), + .d (hw2reg.mio_pad_sleep_status[9].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[9].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_9_qs) + ); + + // F[en_10]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_10_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[10].de), + .d (hw2reg.mio_pad_sleep_status[10].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[10].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_10_qs) + ); + + // F[en_11]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_11_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[11].de), + .d (hw2reg.mio_pad_sleep_status[11].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[11].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_11_qs) + ); + + + // Subregister 0 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_0_we), + .wd (mio_pad_sleep_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_0_qs) + ); + + + // Subregister 1 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_1_we), + .wd (mio_pad_sleep_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_1_qs) + ); + + + // Subregister 2 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_2_we), + .wd (mio_pad_sleep_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_2_qs) + ); + + + // Subregister 3 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_3_we), + .wd (mio_pad_sleep_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_3_qs) + ); + + + // Subregister 4 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_4_we), + .wd (mio_pad_sleep_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_4_qs) + ); + + + // Subregister 5 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_5_we), + .wd (mio_pad_sleep_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_5_qs) + ); + + + // Subregister 6 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_6_we), + .wd (mio_pad_sleep_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_6_qs) + ); + + + // Subregister 7 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_7_we), + .wd (mio_pad_sleep_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_7_qs) + ); + + + // Subregister 8 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_8_we), + .wd (mio_pad_sleep_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_8_qs) + ); + + + // Subregister 9 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_9_we), + .wd (mio_pad_sleep_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_9_qs) + ); + + + // Subregister 10 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_10_we), + .wd (mio_pad_sleep_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_10_qs) + ); + + + // Subregister 11 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_11_we), + .wd (mio_pad_sleep_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_11_qs) + ); + + + // Subregister 0 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_0]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_0_gated_we; + assign mio_pad_sleep_en_0_gated_we = mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_0_gated_we), + .wd (mio_pad_sleep_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[0].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_0_qs) + ); + + + // Subregister 1 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_1]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_1_gated_we; + assign mio_pad_sleep_en_1_gated_we = mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_1_gated_we), + .wd (mio_pad_sleep_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[1].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_1_qs) + ); + + + // Subregister 2 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_2]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_2_gated_we; + assign mio_pad_sleep_en_2_gated_we = mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_2_gated_we), + .wd (mio_pad_sleep_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[2].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_2_qs) + ); + + + // Subregister 3 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_3]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_3_gated_we; + assign mio_pad_sleep_en_3_gated_we = mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_3_gated_we), + .wd (mio_pad_sleep_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[3].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_3_qs) + ); + + + // Subregister 4 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_4]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_4_gated_we; + assign mio_pad_sleep_en_4_gated_we = mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_4_gated_we), + .wd (mio_pad_sleep_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[4].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_4_qs) + ); + + + // Subregister 5 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_5]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_5_gated_we; + assign mio_pad_sleep_en_5_gated_we = mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_5_gated_we), + .wd (mio_pad_sleep_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[5].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_5_qs) + ); + + + // Subregister 6 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_6]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_6_gated_we; + assign mio_pad_sleep_en_6_gated_we = mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_6_gated_we), + .wd (mio_pad_sleep_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[6].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_6_qs) + ); + + + // Subregister 7 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_7]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_7_gated_we; + assign mio_pad_sleep_en_7_gated_we = mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_7_gated_we), + .wd (mio_pad_sleep_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[7].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_7_qs) + ); + + + // Subregister 8 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_8]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_8_gated_we; + assign mio_pad_sleep_en_8_gated_we = mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_8_gated_we), + .wd (mio_pad_sleep_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[8].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_8_qs) + ); + + + // Subregister 9 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_9]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_9_gated_we; + assign mio_pad_sleep_en_9_gated_we = mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_9_gated_we), + .wd (mio_pad_sleep_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[9].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_9_qs) + ); + + + // Subregister 10 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_10]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_10_gated_we; + assign mio_pad_sleep_en_10_gated_we = mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_10_gated_we), + .wd (mio_pad_sleep_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[10].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_10_qs) + ); + + + // Subregister 11 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_11]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_11_gated_we; + assign mio_pad_sleep_en_11_gated_we = mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_11_gated_we), + .wd (mio_pad_sleep_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[11].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_11_qs) + ); + + + // Subregister 0 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_0]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_0_gated_we; + assign mio_pad_sleep_mode_0_gated_we = mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_0_gated_we), + .wd (mio_pad_sleep_mode_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[0].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_0_qs) + ); + + + // Subregister 1 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_1]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_1_gated_we; + assign mio_pad_sleep_mode_1_gated_we = mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_1_gated_we), + .wd (mio_pad_sleep_mode_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[1].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_1_qs) + ); + + + // Subregister 2 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_2]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_2_gated_we; + assign mio_pad_sleep_mode_2_gated_we = mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_2_gated_we), + .wd (mio_pad_sleep_mode_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[2].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_2_qs) + ); + + + // Subregister 3 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_3]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_3_gated_we; + assign mio_pad_sleep_mode_3_gated_we = mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_3_gated_we), + .wd (mio_pad_sleep_mode_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[3].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_3_qs) + ); + + + // Subregister 4 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_4]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_4_gated_we; + assign mio_pad_sleep_mode_4_gated_we = mio_pad_sleep_mode_4_we & mio_pad_sleep_regwen_4_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_4_gated_we), + .wd (mio_pad_sleep_mode_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[4].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_4_qs) + ); + + + // Subregister 5 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_5]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_5_gated_we; + assign mio_pad_sleep_mode_5_gated_we = mio_pad_sleep_mode_5_we & mio_pad_sleep_regwen_5_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_5_gated_we), + .wd (mio_pad_sleep_mode_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[5].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_5_qs) + ); + + + // Subregister 6 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_6]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_6_gated_we; + assign mio_pad_sleep_mode_6_gated_we = mio_pad_sleep_mode_6_we & mio_pad_sleep_regwen_6_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_6_gated_we), + .wd (mio_pad_sleep_mode_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[6].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_6_qs) + ); + + + // Subregister 7 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_7]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_7_gated_we; + assign mio_pad_sleep_mode_7_gated_we = mio_pad_sleep_mode_7_we & mio_pad_sleep_regwen_7_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_7_gated_we), + .wd (mio_pad_sleep_mode_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[7].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_7_qs) + ); + + + // Subregister 8 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_8]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_8_gated_we; + assign mio_pad_sleep_mode_8_gated_we = mio_pad_sleep_mode_8_we & mio_pad_sleep_regwen_8_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_8_gated_we), + .wd (mio_pad_sleep_mode_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[8].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_8_qs) + ); + + + // Subregister 9 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_9]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_9_gated_we; + assign mio_pad_sleep_mode_9_gated_we = mio_pad_sleep_mode_9_we & mio_pad_sleep_regwen_9_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_9_gated_we), + .wd (mio_pad_sleep_mode_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[9].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_9_qs) + ); + + + // Subregister 10 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_10]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_10_gated_we; + assign mio_pad_sleep_mode_10_gated_we = mio_pad_sleep_mode_10_we & mio_pad_sleep_regwen_10_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_10_gated_we), + .wd (mio_pad_sleep_mode_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[10].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_10_qs) + ); + + + // Subregister 11 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_11]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_11_gated_we; + assign mio_pad_sleep_mode_11_gated_we = mio_pad_sleep_mode_11_we & mio_pad_sleep_regwen_11_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_11_gated_we), + .wd (mio_pad_sleep_mode_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[11].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_11_qs) + ); + + + // Subregister 0 of Multireg dio_pad_sleep_status + // R[dio_pad_sleep_status_0]: V(False) + // F[en_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_0_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[0].de), + .d (hw2reg.dio_pad_sleep_status[0].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[0].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_0_qs) + ); + + // F[en_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_1_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[1].de), + .d (hw2reg.dio_pad_sleep_status[1].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[1].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_1_qs) + ); + + // F[en_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_2_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[2].de), + .d (hw2reg.dio_pad_sleep_status[2].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[2].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_2_qs) + ); + + // F[en_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_3_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[3].de), + .d (hw2reg.dio_pad_sleep_status[3].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[3].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_3_qs) + ); + + // F[en_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_4_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[4].de), + .d (hw2reg.dio_pad_sleep_status[4].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[4].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_4_qs) + ); + + // F[en_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_5_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[5].de), + .d (hw2reg.dio_pad_sleep_status[5].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[5].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_5_qs) + ); + + // F[en_6]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_6_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[6].de), + .d (hw2reg.dio_pad_sleep_status[6].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[6].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_6_qs) + ); + + // F[en_7]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_7_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[7].de), + .d (hw2reg.dio_pad_sleep_status[7].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[7].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_7_qs) + ); + + // F[en_8]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_8_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[8].de), + .d (hw2reg.dio_pad_sleep_status[8].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[8].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_8_qs) + ); + + // F[en_9]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_9_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[9].de), + .d (hw2reg.dio_pad_sleep_status[9].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[9].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_9_qs) + ); + + // F[en_10]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_10_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[10].de), + .d (hw2reg.dio_pad_sleep_status[10].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[10].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_10_qs) + ); + + // F[en_11]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_11_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[11].de), + .d (hw2reg.dio_pad_sleep_status[11].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[11].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_11_qs) + ); + + // F[en_12]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_12_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[12].de), + .d (hw2reg.dio_pad_sleep_status[12].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[12].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_12_qs) + ); + + // F[en_13]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_13_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[13].de), + .d (hw2reg.dio_pad_sleep_status[13].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[13].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_13_qs) + ); + + // F[en_14]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_14_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[14].de), + .d (hw2reg.dio_pad_sleep_status[14].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[14].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_14_qs) + ); + + // F[en_15]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_15_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[15].de), + .d (hw2reg.dio_pad_sleep_status[15].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[15].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_15_qs) + ); + + // F[en_16]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_16_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[16].de), + .d (hw2reg.dio_pad_sleep_status[16].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[16].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_16_qs) + ); + + // F[en_17]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_17_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[17].de), + .d (hw2reg.dio_pad_sleep_status[17].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[17].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_17_qs) + ); + + // F[en_18]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_18_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[18].de), + .d (hw2reg.dio_pad_sleep_status[18].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[18].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_18_qs) + ); + + // F[en_19]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_19_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[19].de), + .d (hw2reg.dio_pad_sleep_status[19].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[19].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_19_qs) + ); + + // F[en_20]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_20_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[20].de), + .d (hw2reg.dio_pad_sleep_status[20].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[20].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_20_qs) + ); + + // F[en_21]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_21_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[21].de), + .d (hw2reg.dio_pad_sleep_status[21].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[21].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_21_qs) + ); + + // F[en_22]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_22_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[22].de), + .d (hw2reg.dio_pad_sleep_status[22].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[22].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_22_qs) + ); + + // F[en_23]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_23_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[23].de), + .d (hw2reg.dio_pad_sleep_status[23].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[23].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_23_qs) + ); + + // F[en_24]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_24_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[24].de), + .d (hw2reg.dio_pad_sleep_status[24].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[24].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_24_qs) + ); + + // F[en_25]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_25_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[25].de), + .d (hw2reg.dio_pad_sleep_status[25].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[25].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_25_qs) + ); + + // F[en_26]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_26_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[26].de), + .d (hw2reg.dio_pad_sleep_status[26].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[26].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_26_qs) + ); + + // F[en_27]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_27_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[27].de), + .d (hw2reg.dio_pad_sleep_status[27].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[27].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_27_qs) + ); + + // F[en_28]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_28_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[28].de), + .d (hw2reg.dio_pad_sleep_status[28].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[28].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_28_qs) + ); + + // F[en_29]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_29_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[29].de), + .d (hw2reg.dio_pad_sleep_status[29].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[29].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_29_qs) + ); + + // F[en_30]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_30_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[30].de), + .d (hw2reg.dio_pad_sleep_status[30].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[30].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_30_qs) + ); + + // F[en_31]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_31_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[31].de), + .d (hw2reg.dio_pad_sleep_status[31].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[31].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_31_qs) + ); + + + // Subregister 1 of Multireg dio_pad_sleep_status + // R[dio_pad_sleep_status_1]: V(False) + // F[en_32]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_32_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[32].de), + .d (hw2reg.dio_pad_sleep_status[32].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[32].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_32_qs) + ); + + // F[en_33]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_33_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[33].de), + .d (hw2reg.dio_pad_sleep_status[33].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[33].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_33_qs) + ); + + // F[en_34]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_34_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[34].de), + .d (hw2reg.dio_pad_sleep_status[34].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[34].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_34_qs) + ); + + // F[en_35]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_35_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[35].de), + .d (hw2reg.dio_pad_sleep_status[35].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[35].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_35_qs) + ); + + // F[en_36]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_36_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[36].de), + .d (hw2reg.dio_pad_sleep_status[36].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[36].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_36_qs) + ); + + // F[en_37]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_37_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[37].de), + .d (hw2reg.dio_pad_sleep_status[37].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[37].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_37_qs) + ); + + // F[en_38]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_38_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[38].de), + .d (hw2reg.dio_pad_sleep_status[38].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[38].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_38_qs) + ); + + // F[en_39]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_39_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[39].de), + .d (hw2reg.dio_pad_sleep_status[39].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[39].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_39_qs) + ); + + // F[en_40]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_40_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[40].de), + .d (hw2reg.dio_pad_sleep_status[40].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[40].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_40_qs) + ); + + // F[en_41]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_41_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[41].de), + .d (hw2reg.dio_pad_sleep_status[41].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[41].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_41_qs) + ); + + // F[en_42]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_42_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[42].de), + .d (hw2reg.dio_pad_sleep_status[42].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[42].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_42_qs) + ); + + // F[en_43]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_43_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[43].de), + .d (hw2reg.dio_pad_sleep_status[43].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[43].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_43_qs) + ); + + // F[en_44]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_44_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[44].de), + .d (hw2reg.dio_pad_sleep_status[44].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[44].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_44_qs) + ); + + // F[en_45]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_45_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[45].de), + .d (hw2reg.dio_pad_sleep_status[45].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[45].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_45_qs) + ); + + // F[en_46]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_46_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[46].de), + .d (hw2reg.dio_pad_sleep_status[46].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[46].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_46_qs) + ); + + // F[en_47]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_47_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[47].de), + .d (hw2reg.dio_pad_sleep_status[47].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[47].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_47_qs) + ); + + // F[en_48]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_48_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[48].de), + .d (hw2reg.dio_pad_sleep_status[48].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[48].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_48_qs) + ); + + // F[en_49]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_49_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[49].de), + .d (hw2reg.dio_pad_sleep_status[49].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[49].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_49_qs) + ); + + // F[en_50]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_50_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[50].de), + .d (hw2reg.dio_pad_sleep_status[50].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[50].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_50_qs) + ); + + // F[en_51]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_51_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[51].de), + .d (hw2reg.dio_pad_sleep_status[51].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[51].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_51_qs) + ); + + // F[en_52]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_52_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[52].de), + .d (hw2reg.dio_pad_sleep_status[52].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[52].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_52_qs) + ); + + // F[en_53]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_53_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[53].de), + .d (hw2reg.dio_pad_sleep_status[53].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[53].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_53_qs) + ); + + // F[en_54]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_54_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[54].de), + .d (hw2reg.dio_pad_sleep_status[54].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[54].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_54_qs) + ); + + // F[en_55]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_55_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[55].de), + .d (hw2reg.dio_pad_sleep_status[55].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[55].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_55_qs) + ); + + // F[en_56]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_56_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[56].de), + .d (hw2reg.dio_pad_sleep_status[56].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[56].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_56_qs) + ); + + // F[en_57]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_57_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[57].de), + .d (hw2reg.dio_pad_sleep_status[57].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[57].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_57_qs) + ); + + // F[en_58]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_58_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[58].de), + .d (hw2reg.dio_pad_sleep_status[58].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[58].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_58_qs) + ); + + // F[en_59]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_59_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[59].de), + .d (hw2reg.dio_pad_sleep_status[59].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[59].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_59_qs) + ); + + // F[en_60]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_60_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[60].de), + .d (hw2reg.dio_pad_sleep_status[60].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[60].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_60_qs) + ); + + // F[en_61]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_61_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[61].de), + .d (hw2reg.dio_pad_sleep_status[61].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[61].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_61_qs) + ); + + // F[en_62]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_62_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[62].de), + .d (hw2reg.dio_pad_sleep_status[62].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[62].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_62_qs) + ); + + // F[en_63]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_63_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[63].de), + .d (hw2reg.dio_pad_sleep_status[63].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[63].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_63_qs) + ); + + + // Subregister 2 of Multireg dio_pad_sleep_status + // R[dio_pad_sleep_status_2]: V(False) + // F[en_64]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_64_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[64].de), + .d (hw2reg.dio_pad_sleep_status[64].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[64].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_64_qs) + ); + + // F[en_65]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_65_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[65].de), + .d (hw2reg.dio_pad_sleep_status[65].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[65].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_65_qs) + ); + + // F[en_66]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_66_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[66].de), + .d (hw2reg.dio_pad_sleep_status[66].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[66].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_66_qs) + ); + + // F[en_67]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_67_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[67].de), + .d (hw2reg.dio_pad_sleep_status[67].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[67].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_67_qs) + ); + + // F[en_68]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_68_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[68].de), + .d (hw2reg.dio_pad_sleep_status[68].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[68].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_68_qs) + ); + + // F[en_69]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_69_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[69].de), + .d (hw2reg.dio_pad_sleep_status[69].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[69].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_69_qs) + ); + + // F[en_70]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_70_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[70].de), + .d (hw2reg.dio_pad_sleep_status[70].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[70].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_70_qs) + ); + + // F[en_71]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_71_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[71].de), + .d (hw2reg.dio_pad_sleep_status[71].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[71].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_71_qs) + ); + + // F[en_72]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_72_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[72].de), + .d (hw2reg.dio_pad_sleep_status[72].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[72].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_72_qs) + ); + + + // Subregister 0 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_0_we), + .wd (dio_pad_sleep_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_0_qs) + ); + + + // Subregister 1 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_1_we), + .wd (dio_pad_sleep_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_1_qs) + ); + + + // Subregister 2 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_2_we), + .wd (dio_pad_sleep_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_2_qs) + ); + + + // Subregister 3 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_3_we), + .wd (dio_pad_sleep_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_3_qs) + ); + + + // Subregister 4 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_4_we), + .wd (dio_pad_sleep_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_4_qs) + ); + + + // Subregister 5 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_5_we), + .wd (dio_pad_sleep_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_5_qs) + ); + + + // Subregister 6 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_6_we), + .wd (dio_pad_sleep_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_6_qs) + ); + + + // Subregister 7 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_7_we), + .wd (dio_pad_sleep_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_7_qs) + ); + + + // Subregister 8 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_8_we), + .wd (dio_pad_sleep_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_8_qs) + ); + + + // Subregister 9 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_9_we), + .wd (dio_pad_sleep_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_9_qs) + ); + + + // Subregister 10 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_10_we), + .wd (dio_pad_sleep_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_10_qs) + ); + + + // Subregister 11 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_11_we), + .wd (dio_pad_sleep_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_11_qs) + ); + + + // Subregister 12 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_12]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_12_we), + .wd (dio_pad_sleep_regwen_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_12_qs) + ); + + + // Subregister 13 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_13]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_13_we), + .wd (dio_pad_sleep_regwen_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_13_qs) + ); + + + // Subregister 14 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_14]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_14_we), + .wd (dio_pad_sleep_regwen_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_14_qs) + ); + + + // Subregister 15 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_15]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_15_we), + .wd (dio_pad_sleep_regwen_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_15_qs) + ); + + + // Subregister 16 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_16]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_16_we), + .wd (dio_pad_sleep_regwen_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_16_qs) + ); + + + // Subregister 17 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_17]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_17_we), + .wd (dio_pad_sleep_regwen_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_17_qs) + ); + + + // Subregister 18 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_18]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_18_we), + .wd (dio_pad_sleep_regwen_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_18_qs) + ); + + + // Subregister 19 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_19]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_19_we), + .wd (dio_pad_sleep_regwen_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_19_qs) + ); + + + // Subregister 20 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_20]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_20_we), + .wd (dio_pad_sleep_regwen_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_20_qs) + ); + + + // Subregister 21 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_21]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_21_we), + .wd (dio_pad_sleep_regwen_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_21_qs) + ); + + + // Subregister 22 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_22]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_22_we), + .wd (dio_pad_sleep_regwen_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_22_qs) + ); + + + // Subregister 23 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_23]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_23_we), + .wd (dio_pad_sleep_regwen_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_23_qs) + ); + + + // Subregister 24 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_24]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_24_we), + .wd (dio_pad_sleep_regwen_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_24_qs) + ); + + + // Subregister 25 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_25]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_25_we), + .wd (dio_pad_sleep_regwen_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_25_qs) + ); + + + // Subregister 26 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_26]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_26_we), + .wd (dio_pad_sleep_regwen_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_26_qs) + ); + + + // Subregister 27 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_27]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_27_we), + .wd (dio_pad_sleep_regwen_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_27_qs) + ); + + + // Subregister 28 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_28]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_28_we), + .wd (dio_pad_sleep_regwen_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_28_qs) + ); + + + // Subregister 29 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_29]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_29_we), + .wd (dio_pad_sleep_regwen_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_29_qs) + ); + + + // Subregister 30 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_30]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_30_we), + .wd (dio_pad_sleep_regwen_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_30_qs) + ); + + + // Subregister 31 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_31]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_31_we), + .wd (dio_pad_sleep_regwen_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_31_qs) + ); + + + // Subregister 32 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_32]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_32_we), + .wd (dio_pad_sleep_regwen_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_32_qs) + ); + + + // Subregister 33 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_33]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_33_we), + .wd (dio_pad_sleep_regwen_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_33_qs) + ); + + + // Subregister 34 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_34]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_34_we), + .wd (dio_pad_sleep_regwen_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_34_qs) + ); + + + // Subregister 35 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_35]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_35_we), + .wd (dio_pad_sleep_regwen_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_35_qs) + ); + + + // Subregister 36 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_36]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_36_we), + .wd (dio_pad_sleep_regwen_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_36_qs) + ); + + + // Subregister 37 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_37]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_37_we), + .wd (dio_pad_sleep_regwen_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_37_qs) + ); + + + // Subregister 38 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_38]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_38_we), + .wd (dio_pad_sleep_regwen_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_38_qs) + ); + + + // Subregister 39 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_39]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_39_we), + .wd (dio_pad_sleep_regwen_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_39_qs) + ); + + + // Subregister 40 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_40]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_40_we), + .wd (dio_pad_sleep_regwen_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_40_qs) + ); + + + // Subregister 41 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_41]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_41_we), + .wd (dio_pad_sleep_regwen_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_41_qs) + ); + + + // Subregister 42 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_42]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_42_we), + .wd (dio_pad_sleep_regwen_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_42_qs) + ); + + + // Subregister 43 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_43]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_43_we), + .wd (dio_pad_sleep_regwen_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_43_qs) + ); + + + // Subregister 44 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_44]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_44_we), + .wd (dio_pad_sleep_regwen_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_44_qs) + ); + + + // Subregister 45 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_45]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_45_we), + .wd (dio_pad_sleep_regwen_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_45_qs) + ); + + + // Subregister 46 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_46]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_46_we), + .wd (dio_pad_sleep_regwen_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_46_qs) + ); + + + // Subregister 47 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_47]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_47_we), + .wd (dio_pad_sleep_regwen_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_47_qs) + ); + + + // Subregister 48 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_48]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_48_we), + .wd (dio_pad_sleep_regwen_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_48_qs) + ); + + + // Subregister 49 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_49]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_49_we), + .wd (dio_pad_sleep_regwen_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_49_qs) + ); + + + // Subregister 50 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_50]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_50_we), + .wd (dio_pad_sleep_regwen_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_50_qs) + ); + + + // Subregister 51 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_51]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_51_we), + .wd (dio_pad_sleep_regwen_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_51_qs) + ); + + + // Subregister 52 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_52]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_52_we), + .wd (dio_pad_sleep_regwen_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_52_qs) + ); + + + // Subregister 53 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_53]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_53_we), + .wd (dio_pad_sleep_regwen_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_53_qs) + ); + + + // Subregister 54 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_54]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_54_we), + .wd (dio_pad_sleep_regwen_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_54_qs) + ); + + + // Subregister 55 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_55]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_55_we), + .wd (dio_pad_sleep_regwen_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_55_qs) + ); + + + // Subregister 56 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_56]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_56_we), + .wd (dio_pad_sleep_regwen_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_56_qs) + ); + + + // Subregister 57 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_57]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_57_we), + .wd (dio_pad_sleep_regwen_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_57_qs) + ); + + + // Subregister 58 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_58]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_58_we), + .wd (dio_pad_sleep_regwen_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_58_qs) + ); + + + // Subregister 59 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_59]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_59_we), + .wd (dio_pad_sleep_regwen_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_59_qs) + ); + + + // Subregister 60 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_60]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_60_we), + .wd (dio_pad_sleep_regwen_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_60_qs) + ); + + + // Subregister 61 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_61]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_61_we), + .wd (dio_pad_sleep_regwen_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_61_qs) + ); + + + // Subregister 62 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_62]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_62_we), + .wd (dio_pad_sleep_regwen_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_62_qs) + ); + + + // Subregister 63 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_63]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_63_we), + .wd (dio_pad_sleep_regwen_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_63_qs) + ); + + + // Subregister 64 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_64]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_64_we), + .wd (dio_pad_sleep_regwen_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_64_qs) + ); + + + // Subregister 65 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_65]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_65_we), + .wd (dio_pad_sleep_regwen_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_65_qs) + ); + + + // Subregister 66 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_66]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_66_we), + .wd (dio_pad_sleep_regwen_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_66_qs) + ); + + + // Subregister 67 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_67]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_67_we), + .wd (dio_pad_sleep_regwen_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_67_qs) + ); + + + // Subregister 68 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_68]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_68_we), + .wd (dio_pad_sleep_regwen_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_68_qs) + ); + + + // Subregister 69 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_69]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_69_we), + .wd (dio_pad_sleep_regwen_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_69_qs) + ); + + + // Subregister 70 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_70]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_70_we), + .wd (dio_pad_sleep_regwen_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_70_qs) + ); + + + // Subregister 71 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_71]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_71_we), + .wd (dio_pad_sleep_regwen_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_71_qs) + ); + + + // Subregister 72 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_72]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_72_we), + .wd (dio_pad_sleep_regwen_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_72_qs) + ); + + + // Subregister 0 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_0]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_0_gated_we; + assign dio_pad_sleep_en_0_gated_we = dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_0_gated_we), + .wd (dio_pad_sleep_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[0].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_0_qs) + ); + + + // Subregister 1 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_1]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_1_gated_we; + assign dio_pad_sleep_en_1_gated_we = dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_1_gated_we), + .wd (dio_pad_sleep_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[1].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_1_qs) + ); + + + // Subregister 2 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_2]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_2_gated_we; + assign dio_pad_sleep_en_2_gated_we = dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_2_gated_we), + .wd (dio_pad_sleep_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[2].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_2_qs) + ); + + + // Subregister 3 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_3]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_3_gated_we; + assign dio_pad_sleep_en_3_gated_we = dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_3_gated_we), + .wd (dio_pad_sleep_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[3].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_3_qs) + ); + + + // Subregister 4 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_4]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_4_gated_we; + assign dio_pad_sleep_en_4_gated_we = dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_4_gated_we), + .wd (dio_pad_sleep_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[4].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_4_qs) + ); + + + // Subregister 5 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_5]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_5_gated_we; + assign dio_pad_sleep_en_5_gated_we = dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_5_gated_we), + .wd (dio_pad_sleep_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[5].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_5_qs) + ); + + + // Subregister 6 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_6]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_6_gated_we; + assign dio_pad_sleep_en_6_gated_we = dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_6_gated_we), + .wd (dio_pad_sleep_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[6].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_6_qs) + ); + + + // Subregister 7 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_7]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_7_gated_we; + assign dio_pad_sleep_en_7_gated_we = dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_7_gated_we), + .wd (dio_pad_sleep_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[7].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_7_qs) + ); + + + // Subregister 8 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_8]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_8_gated_we; + assign dio_pad_sleep_en_8_gated_we = dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_8_gated_we), + .wd (dio_pad_sleep_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[8].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_8_qs) + ); + + + // Subregister 9 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_9]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_9_gated_we; + assign dio_pad_sleep_en_9_gated_we = dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_9_gated_we), + .wd (dio_pad_sleep_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[9].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_9_qs) + ); + + + // Subregister 10 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_10]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_10_gated_we; + assign dio_pad_sleep_en_10_gated_we = dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_10_gated_we), + .wd (dio_pad_sleep_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[10].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_10_qs) + ); + + + // Subregister 11 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_11]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_11_gated_we; + assign dio_pad_sleep_en_11_gated_we = dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_11_gated_we), + .wd (dio_pad_sleep_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[11].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_11_qs) + ); + + + // Subregister 12 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_12]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_12_gated_we; + assign dio_pad_sleep_en_12_gated_we = dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_12_gated_we), + .wd (dio_pad_sleep_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[12].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_12_qs) + ); + + + // Subregister 13 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_13]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_13_gated_we; + assign dio_pad_sleep_en_13_gated_we = dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_13_gated_we), + .wd (dio_pad_sleep_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[13].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_13_qs) + ); + + + // Subregister 14 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_14]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_14_gated_we; + assign dio_pad_sleep_en_14_gated_we = dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_14_gated_we), + .wd (dio_pad_sleep_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[14].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_14_qs) + ); + + + // Subregister 15 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_15]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_15_gated_we; + assign dio_pad_sleep_en_15_gated_we = dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_15_gated_we), + .wd (dio_pad_sleep_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[15].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_15_qs) + ); + + + // Subregister 16 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_16]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_16_gated_we; + assign dio_pad_sleep_en_16_gated_we = dio_pad_sleep_en_16_we & dio_pad_sleep_regwen_16_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_16_gated_we), + .wd (dio_pad_sleep_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[16].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_16_qs) + ); + + + // Subregister 17 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_17]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_17_gated_we; + assign dio_pad_sleep_en_17_gated_we = dio_pad_sleep_en_17_we & dio_pad_sleep_regwen_17_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_17_gated_we), + .wd (dio_pad_sleep_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[17].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_17_qs) + ); + + + // Subregister 18 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_18]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_18_gated_we; + assign dio_pad_sleep_en_18_gated_we = dio_pad_sleep_en_18_we & dio_pad_sleep_regwen_18_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_18_gated_we), + .wd (dio_pad_sleep_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[18].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_18_qs) + ); + + + // Subregister 19 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_19]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_19_gated_we; + assign dio_pad_sleep_en_19_gated_we = dio_pad_sleep_en_19_we & dio_pad_sleep_regwen_19_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_19_gated_we), + .wd (dio_pad_sleep_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[19].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_19_qs) + ); + + + // Subregister 20 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_20]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_20_gated_we; + assign dio_pad_sleep_en_20_gated_we = dio_pad_sleep_en_20_we & dio_pad_sleep_regwen_20_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_20_gated_we), + .wd (dio_pad_sleep_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[20].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_20_qs) + ); + + + // Subregister 21 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_21]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_21_gated_we; + assign dio_pad_sleep_en_21_gated_we = dio_pad_sleep_en_21_we & dio_pad_sleep_regwen_21_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_21_gated_we), + .wd (dio_pad_sleep_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[21].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_21_qs) + ); + + + // Subregister 22 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_22]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_22_gated_we; + assign dio_pad_sleep_en_22_gated_we = dio_pad_sleep_en_22_we & dio_pad_sleep_regwen_22_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_22_gated_we), + .wd (dio_pad_sleep_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[22].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_22_qs) + ); + + + // Subregister 23 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_23]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_23_gated_we; + assign dio_pad_sleep_en_23_gated_we = dio_pad_sleep_en_23_we & dio_pad_sleep_regwen_23_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_23_gated_we), + .wd (dio_pad_sleep_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[23].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_23_qs) + ); + + + // Subregister 24 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_24]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_24_gated_we; + assign dio_pad_sleep_en_24_gated_we = dio_pad_sleep_en_24_we & dio_pad_sleep_regwen_24_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_24_gated_we), + .wd (dio_pad_sleep_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[24].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_24_qs) + ); + + + // Subregister 25 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_25]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_25_gated_we; + assign dio_pad_sleep_en_25_gated_we = dio_pad_sleep_en_25_we & dio_pad_sleep_regwen_25_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_25_gated_we), + .wd (dio_pad_sleep_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[25].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_25_qs) + ); + + + // Subregister 26 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_26]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_26_gated_we; + assign dio_pad_sleep_en_26_gated_we = dio_pad_sleep_en_26_we & dio_pad_sleep_regwen_26_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_26_gated_we), + .wd (dio_pad_sleep_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[26].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_26_qs) + ); + + + // Subregister 27 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_27]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_27_gated_we; + assign dio_pad_sleep_en_27_gated_we = dio_pad_sleep_en_27_we & dio_pad_sleep_regwen_27_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_27_gated_we), + .wd (dio_pad_sleep_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[27].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_27_qs) + ); + + + // Subregister 28 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_28]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_28_gated_we; + assign dio_pad_sleep_en_28_gated_we = dio_pad_sleep_en_28_we & dio_pad_sleep_regwen_28_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_28_gated_we), + .wd (dio_pad_sleep_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[28].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_28_qs) + ); + + + // Subregister 29 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_29]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_29_gated_we; + assign dio_pad_sleep_en_29_gated_we = dio_pad_sleep_en_29_we & dio_pad_sleep_regwen_29_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_29_gated_we), + .wd (dio_pad_sleep_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[29].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_29_qs) + ); + + + // Subregister 30 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_30]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_30_gated_we; + assign dio_pad_sleep_en_30_gated_we = dio_pad_sleep_en_30_we & dio_pad_sleep_regwen_30_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_30_gated_we), + .wd (dio_pad_sleep_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[30].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_30_qs) + ); + + + // Subregister 31 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_31]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_31_gated_we; + assign dio_pad_sleep_en_31_gated_we = dio_pad_sleep_en_31_we & dio_pad_sleep_regwen_31_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_31_gated_we), + .wd (dio_pad_sleep_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[31].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_31_qs) + ); + + + // Subregister 32 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_32]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_32_gated_we; + assign dio_pad_sleep_en_32_gated_we = dio_pad_sleep_en_32_we & dio_pad_sleep_regwen_32_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_32_gated_we), + .wd (dio_pad_sleep_en_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[32].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_32_qs) + ); + + + // Subregister 33 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_33]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_33_gated_we; + assign dio_pad_sleep_en_33_gated_we = dio_pad_sleep_en_33_we & dio_pad_sleep_regwen_33_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_33_gated_we), + .wd (dio_pad_sleep_en_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[33].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_33_qs) + ); + + + // Subregister 34 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_34]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_34_gated_we; + assign dio_pad_sleep_en_34_gated_we = dio_pad_sleep_en_34_we & dio_pad_sleep_regwen_34_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_34_gated_we), + .wd (dio_pad_sleep_en_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[34].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_34_qs) + ); + + + // Subregister 35 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_35]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_35_gated_we; + assign dio_pad_sleep_en_35_gated_we = dio_pad_sleep_en_35_we & dio_pad_sleep_regwen_35_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_35_gated_we), + .wd (dio_pad_sleep_en_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[35].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_35_qs) + ); + + + // Subregister 36 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_36]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_36_gated_we; + assign dio_pad_sleep_en_36_gated_we = dio_pad_sleep_en_36_we & dio_pad_sleep_regwen_36_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_36_gated_we), + .wd (dio_pad_sleep_en_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[36].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_36_qs) + ); + + + // Subregister 37 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_37]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_37_gated_we; + assign dio_pad_sleep_en_37_gated_we = dio_pad_sleep_en_37_we & dio_pad_sleep_regwen_37_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_37_gated_we), + .wd (dio_pad_sleep_en_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[37].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_37_qs) + ); + + + // Subregister 38 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_38]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_38_gated_we; + assign dio_pad_sleep_en_38_gated_we = dio_pad_sleep_en_38_we & dio_pad_sleep_regwen_38_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_38_gated_we), + .wd (dio_pad_sleep_en_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[38].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_38_qs) + ); + + + // Subregister 39 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_39]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_39_gated_we; + assign dio_pad_sleep_en_39_gated_we = dio_pad_sleep_en_39_we & dio_pad_sleep_regwen_39_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_39_gated_we), + .wd (dio_pad_sleep_en_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[39].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_39_qs) + ); + + + // Subregister 40 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_40]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_40_gated_we; + assign dio_pad_sleep_en_40_gated_we = dio_pad_sleep_en_40_we & dio_pad_sleep_regwen_40_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_40_gated_we), + .wd (dio_pad_sleep_en_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[40].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_40_qs) + ); + + + // Subregister 41 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_41]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_41_gated_we; + assign dio_pad_sleep_en_41_gated_we = dio_pad_sleep_en_41_we & dio_pad_sleep_regwen_41_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_41_gated_we), + .wd (dio_pad_sleep_en_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[41].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_41_qs) + ); + + + // Subregister 42 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_42]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_42_gated_we; + assign dio_pad_sleep_en_42_gated_we = dio_pad_sleep_en_42_we & dio_pad_sleep_regwen_42_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_42_gated_we), + .wd (dio_pad_sleep_en_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[42].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_42_qs) + ); + + + // Subregister 43 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_43]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_43_gated_we; + assign dio_pad_sleep_en_43_gated_we = dio_pad_sleep_en_43_we & dio_pad_sleep_regwen_43_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_43_gated_we), + .wd (dio_pad_sleep_en_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[43].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_43_qs) + ); + + + // Subregister 44 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_44]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_44_gated_we; + assign dio_pad_sleep_en_44_gated_we = dio_pad_sleep_en_44_we & dio_pad_sleep_regwen_44_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_44_gated_we), + .wd (dio_pad_sleep_en_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[44].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_44_qs) + ); + + + // Subregister 45 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_45]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_45_gated_we; + assign dio_pad_sleep_en_45_gated_we = dio_pad_sleep_en_45_we & dio_pad_sleep_regwen_45_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_45_gated_we), + .wd (dio_pad_sleep_en_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[45].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_45_qs) + ); + + + // Subregister 46 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_46]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_46_gated_we; + assign dio_pad_sleep_en_46_gated_we = dio_pad_sleep_en_46_we & dio_pad_sleep_regwen_46_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_46_gated_we), + .wd (dio_pad_sleep_en_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[46].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_46_qs) + ); + + + // Subregister 47 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_47]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_47_gated_we; + assign dio_pad_sleep_en_47_gated_we = dio_pad_sleep_en_47_we & dio_pad_sleep_regwen_47_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_47_gated_we), + .wd (dio_pad_sleep_en_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[47].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_47_qs) + ); + + + // Subregister 48 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_48]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_48_gated_we; + assign dio_pad_sleep_en_48_gated_we = dio_pad_sleep_en_48_we & dio_pad_sleep_regwen_48_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_48_gated_we), + .wd (dio_pad_sleep_en_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[48].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_48_qs) + ); + + + // Subregister 49 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_49]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_49_gated_we; + assign dio_pad_sleep_en_49_gated_we = dio_pad_sleep_en_49_we & dio_pad_sleep_regwen_49_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_49_gated_we), + .wd (dio_pad_sleep_en_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[49].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_49_qs) + ); + + + // Subregister 50 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_50]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_50_gated_we; + assign dio_pad_sleep_en_50_gated_we = dio_pad_sleep_en_50_we & dio_pad_sleep_regwen_50_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_50_gated_we), + .wd (dio_pad_sleep_en_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[50].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_50_qs) + ); + + + // Subregister 51 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_51]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_51_gated_we; + assign dio_pad_sleep_en_51_gated_we = dio_pad_sleep_en_51_we & dio_pad_sleep_regwen_51_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_51_gated_we), + .wd (dio_pad_sleep_en_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[51].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_51_qs) + ); + + + // Subregister 52 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_52]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_52_gated_we; + assign dio_pad_sleep_en_52_gated_we = dio_pad_sleep_en_52_we & dio_pad_sleep_regwen_52_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_52_gated_we), + .wd (dio_pad_sleep_en_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[52].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_52_qs) + ); + + + // Subregister 53 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_53]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_53_gated_we; + assign dio_pad_sleep_en_53_gated_we = dio_pad_sleep_en_53_we & dio_pad_sleep_regwen_53_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_53_gated_we), + .wd (dio_pad_sleep_en_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[53].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_53_qs) + ); + + + // Subregister 54 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_54]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_54_gated_we; + assign dio_pad_sleep_en_54_gated_we = dio_pad_sleep_en_54_we & dio_pad_sleep_regwen_54_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_54_gated_we), + .wd (dio_pad_sleep_en_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[54].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_54_qs) + ); + + + // Subregister 55 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_55]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_55_gated_we; + assign dio_pad_sleep_en_55_gated_we = dio_pad_sleep_en_55_we & dio_pad_sleep_regwen_55_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_55_gated_we), + .wd (dio_pad_sleep_en_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[55].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_55_qs) + ); + + + // Subregister 56 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_56]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_56_gated_we; + assign dio_pad_sleep_en_56_gated_we = dio_pad_sleep_en_56_we & dio_pad_sleep_regwen_56_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_56_gated_we), + .wd (dio_pad_sleep_en_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[56].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_56_qs) + ); + + + // Subregister 57 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_57]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_57_gated_we; + assign dio_pad_sleep_en_57_gated_we = dio_pad_sleep_en_57_we & dio_pad_sleep_regwen_57_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_57_gated_we), + .wd (dio_pad_sleep_en_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[57].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_57_qs) + ); + + + // Subregister 58 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_58]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_58_gated_we; + assign dio_pad_sleep_en_58_gated_we = dio_pad_sleep_en_58_we & dio_pad_sleep_regwen_58_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_58_gated_we), + .wd (dio_pad_sleep_en_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[58].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_58_qs) + ); + + + // Subregister 59 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_59]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_59_gated_we; + assign dio_pad_sleep_en_59_gated_we = dio_pad_sleep_en_59_we & dio_pad_sleep_regwen_59_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_59_gated_we), + .wd (dio_pad_sleep_en_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[59].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_59_qs) + ); + + + // Subregister 60 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_60]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_60_gated_we; + assign dio_pad_sleep_en_60_gated_we = dio_pad_sleep_en_60_we & dio_pad_sleep_regwen_60_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_60_gated_we), + .wd (dio_pad_sleep_en_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[60].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_60_qs) + ); + + + // Subregister 61 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_61]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_61_gated_we; + assign dio_pad_sleep_en_61_gated_we = dio_pad_sleep_en_61_we & dio_pad_sleep_regwen_61_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_61_gated_we), + .wd (dio_pad_sleep_en_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[61].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_61_qs) + ); + + + // Subregister 62 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_62]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_62_gated_we; + assign dio_pad_sleep_en_62_gated_we = dio_pad_sleep_en_62_we & dio_pad_sleep_regwen_62_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_62_gated_we), + .wd (dio_pad_sleep_en_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[62].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_62_qs) + ); + + + // Subregister 63 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_63]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_63_gated_we; + assign dio_pad_sleep_en_63_gated_we = dio_pad_sleep_en_63_we & dio_pad_sleep_regwen_63_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_63_gated_we), + .wd (dio_pad_sleep_en_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[63].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_63_qs) + ); + + + // Subregister 64 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_64]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_64_gated_we; + assign dio_pad_sleep_en_64_gated_we = dio_pad_sleep_en_64_we & dio_pad_sleep_regwen_64_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_64_gated_we), + .wd (dio_pad_sleep_en_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[64].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_64_qs) + ); + + + // Subregister 65 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_65]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_65_gated_we; + assign dio_pad_sleep_en_65_gated_we = dio_pad_sleep_en_65_we & dio_pad_sleep_regwen_65_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_65_gated_we), + .wd (dio_pad_sleep_en_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[65].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_65_qs) + ); + + + // Subregister 66 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_66]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_66_gated_we; + assign dio_pad_sleep_en_66_gated_we = dio_pad_sleep_en_66_we & dio_pad_sleep_regwen_66_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_66_gated_we), + .wd (dio_pad_sleep_en_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[66].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_66_qs) + ); + + + // Subregister 67 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_67]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_67_gated_we; + assign dio_pad_sleep_en_67_gated_we = dio_pad_sleep_en_67_we & dio_pad_sleep_regwen_67_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_67_gated_we), + .wd (dio_pad_sleep_en_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[67].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_67_qs) + ); + + + // Subregister 68 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_68]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_68_gated_we; + assign dio_pad_sleep_en_68_gated_we = dio_pad_sleep_en_68_we & dio_pad_sleep_regwen_68_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_68_gated_we), + .wd (dio_pad_sleep_en_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[68].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_68_qs) + ); + + + // Subregister 69 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_69]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_69_gated_we; + assign dio_pad_sleep_en_69_gated_we = dio_pad_sleep_en_69_we & dio_pad_sleep_regwen_69_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_69_gated_we), + .wd (dio_pad_sleep_en_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[69].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_69_qs) + ); + + + // Subregister 70 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_70]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_70_gated_we; + assign dio_pad_sleep_en_70_gated_we = dio_pad_sleep_en_70_we & dio_pad_sleep_regwen_70_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_70_gated_we), + .wd (dio_pad_sleep_en_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[70].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_70_qs) + ); + + + // Subregister 71 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_71]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_71_gated_we; + assign dio_pad_sleep_en_71_gated_we = dio_pad_sleep_en_71_we & dio_pad_sleep_regwen_71_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_71_gated_we), + .wd (dio_pad_sleep_en_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[71].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_71_qs) + ); + + + // Subregister 72 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_72]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_72_gated_we; + assign dio_pad_sleep_en_72_gated_we = dio_pad_sleep_en_72_we & dio_pad_sleep_regwen_72_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_72_gated_we), + .wd (dio_pad_sleep_en_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[72].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_72_qs) + ); + + + // Subregister 0 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_0]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_0_gated_we; + assign dio_pad_sleep_mode_0_gated_we = dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_0_gated_we), + .wd (dio_pad_sleep_mode_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[0].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_0_qs) + ); + + + // Subregister 1 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_1]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_1_gated_we; + assign dio_pad_sleep_mode_1_gated_we = dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_1_gated_we), + .wd (dio_pad_sleep_mode_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[1].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_1_qs) + ); + + + // Subregister 2 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_2]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_2_gated_we; + assign dio_pad_sleep_mode_2_gated_we = dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_2_gated_we), + .wd (dio_pad_sleep_mode_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[2].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_2_qs) + ); + + + // Subregister 3 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_3]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_3_gated_we; + assign dio_pad_sleep_mode_3_gated_we = dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_3_gated_we), + .wd (dio_pad_sleep_mode_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[3].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_3_qs) + ); + + + // Subregister 4 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_4]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_4_gated_we; + assign dio_pad_sleep_mode_4_gated_we = dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_4_gated_we), + .wd (dio_pad_sleep_mode_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[4].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_4_qs) + ); + + + // Subregister 5 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_5]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_5_gated_we; + assign dio_pad_sleep_mode_5_gated_we = dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_5_gated_we), + .wd (dio_pad_sleep_mode_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[5].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_5_qs) + ); + + + // Subregister 6 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_6]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_6_gated_we; + assign dio_pad_sleep_mode_6_gated_we = dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_6_gated_we), + .wd (dio_pad_sleep_mode_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[6].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_6_qs) + ); + + + // Subregister 7 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_7]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_7_gated_we; + assign dio_pad_sleep_mode_7_gated_we = dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_7_gated_we), + .wd (dio_pad_sleep_mode_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[7].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_7_qs) + ); + + + // Subregister 8 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_8]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_8_gated_we; + assign dio_pad_sleep_mode_8_gated_we = dio_pad_sleep_mode_8_we & dio_pad_sleep_regwen_8_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_8_gated_we), + .wd (dio_pad_sleep_mode_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[8].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_8_qs) + ); + + + // Subregister 9 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_9]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_9_gated_we; + assign dio_pad_sleep_mode_9_gated_we = dio_pad_sleep_mode_9_we & dio_pad_sleep_regwen_9_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_9_gated_we), + .wd (dio_pad_sleep_mode_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[9].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_9_qs) + ); + + + // Subregister 10 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_10]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_10_gated_we; + assign dio_pad_sleep_mode_10_gated_we = dio_pad_sleep_mode_10_we & dio_pad_sleep_regwen_10_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_10_gated_we), + .wd (dio_pad_sleep_mode_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[10].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_10_qs) + ); + + + // Subregister 11 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_11]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_11_gated_we; + assign dio_pad_sleep_mode_11_gated_we = dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_11_gated_we), + .wd (dio_pad_sleep_mode_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[11].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_11_qs) + ); + + + // Subregister 12 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_12]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_12_gated_we; + assign dio_pad_sleep_mode_12_gated_we = dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_12_gated_we), + .wd (dio_pad_sleep_mode_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[12].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_12_qs) + ); + + + // Subregister 13 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_13]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_13_gated_we; + assign dio_pad_sleep_mode_13_gated_we = dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_13_gated_we), + .wd (dio_pad_sleep_mode_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[13].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_13_qs) + ); + + + // Subregister 14 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_14]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_14_gated_we; + assign dio_pad_sleep_mode_14_gated_we = dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_14_gated_we), + .wd (dio_pad_sleep_mode_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[14].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_14_qs) + ); + + + // Subregister 15 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_15]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_15_gated_we; + assign dio_pad_sleep_mode_15_gated_we = dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_15_gated_we), + .wd (dio_pad_sleep_mode_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[15].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_15_qs) + ); + + + // Subregister 16 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_16]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_16_gated_we; + assign dio_pad_sleep_mode_16_gated_we = dio_pad_sleep_mode_16_we & dio_pad_sleep_regwen_16_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_16_gated_we), + .wd (dio_pad_sleep_mode_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[16].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_16_qs) + ); + + + // Subregister 17 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_17]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_17_gated_we; + assign dio_pad_sleep_mode_17_gated_we = dio_pad_sleep_mode_17_we & dio_pad_sleep_regwen_17_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_17_gated_we), + .wd (dio_pad_sleep_mode_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[17].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_17_qs) + ); + + + // Subregister 18 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_18]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_18_gated_we; + assign dio_pad_sleep_mode_18_gated_we = dio_pad_sleep_mode_18_we & dio_pad_sleep_regwen_18_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_18_gated_we), + .wd (dio_pad_sleep_mode_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[18].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_18_qs) + ); + + + // Subregister 19 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_19]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_19_gated_we; + assign dio_pad_sleep_mode_19_gated_we = dio_pad_sleep_mode_19_we & dio_pad_sleep_regwen_19_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_19_gated_we), + .wd (dio_pad_sleep_mode_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[19].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_19_qs) + ); + + + // Subregister 20 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_20]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_20_gated_we; + assign dio_pad_sleep_mode_20_gated_we = dio_pad_sleep_mode_20_we & dio_pad_sleep_regwen_20_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_20_gated_we), + .wd (dio_pad_sleep_mode_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[20].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_20_qs) + ); + + + // Subregister 21 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_21]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_21_gated_we; + assign dio_pad_sleep_mode_21_gated_we = dio_pad_sleep_mode_21_we & dio_pad_sleep_regwen_21_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_21_gated_we), + .wd (dio_pad_sleep_mode_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[21].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_21_qs) + ); + + + // Subregister 22 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_22]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_22_gated_we; + assign dio_pad_sleep_mode_22_gated_we = dio_pad_sleep_mode_22_we & dio_pad_sleep_regwen_22_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_22_gated_we), + .wd (dio_pad_sleep_mode_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[22].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_22_qs) + ); + + + // Subregister 23 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_23]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_23_gated_we; + assign dio_pad_sleep_mode_23_gated_we = dio_pad_sleep_mode_23_we & dio_pad_sleep_regwen_23_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_23_gated_we), + .wd (dio_pad_sleep_mode_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[23].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_23_qs) + ); + + + // Subregister 24 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_24]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_24_gated_we; + assign dio_pad_sleep_mode_24_gated_we = dio_pad_sleep_mode_24_we & dio_pad_sleep_regwen_24_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_24_gated_we), + .wd (dio_pad_sleep_mode_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[24].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_24_qs) + ); + + + // Subregister 25 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_25]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_25_gated_we; + assign dio_pad_sleep_mode_25_gated_we = dio_pad_sleep_mode_25_we & dio_pad_sleep_regwen_25_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_25_gated_we), + .wd (dio_pad_sleep_mode_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[25].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_25_qs) + ); + + + // Subregister 26 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_26]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_26_gated_we; + assign dio_pad_sleep_mode_26_gated_we = dio_pad_sleep_mode_26_we & dio_pad_sleep_regwen_26_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_26_gated_we), + .wd (dio_pad_sleep_mode_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[26].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_26_qs) + ); + + + // Subregister 27 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_27]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_27_gated_we; + assign dio_pad_sleep_mode_27_gated_we = dio_pad_sleep_mode_27_we & dio_pad_sleep_regwen_27_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_27_gated_we), + .wd (dio_pad_sleep_mode_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[27].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_27_qs) + ); + + + // Subregister 28 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_28]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_28_gated_we; + assign dio_pad_sleep_mode_28_gated_we = dio_pad_sleep_mode_28_we & dio_pad_sleep_regwen_28_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_28_gated_we), + .wd (dio_pad_sleep_mode_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[28].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_28_qs) + ); + + + // Subregister 29 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_29]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_29_gated_we; + assign dio_pad_sleep_mode_29_gated_we = dio_pad_sleep_mode_29_we & dio_pad_sleep_regwen_29_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_29_gated_we), + .wd (dio_pad_sleep_mode_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[29].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_29_qs) + ); + + + // Subregister 30 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_30]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_30_gated_we; + assign dio_pad_sleep_mode_30_gated_we = dio_pad_sleep_mode_30_we & dio_pad_sleep_regwen_30_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_30_gated_we), + .wd (dio_pad_sleep_mode_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[30].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_30_qs) + ); + + + // Subregister 31 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_31]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_31_gated_we; + assign dio_pad_sleep_mode_31_gated_we = dio_pad_sleep_mode_31_we & dio_pad_sleep_regwen_31_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_31_gated_we), + .wd (dio_pad_sleep_mode_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[31].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_31_qs) + ); + + + // Subregister 32 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_32]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_32_gated_we; + assign dio_pad_sleep_mode_32_gated_we = dio_pad_sleep_mode_32_we & dio_pad_sleep_regwen_32_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_32_gated_we), + .wd (dio_pad_sleep_mode_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[32].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_32_qs) + ); + + + // Subregister 33 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_33]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_33_gated_we; + assign dio_pad_sleep_mode_33_gated_we = dio_pad_sleep_mode_33_we & dio_pad_sleep_regwen_33_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_33_gated_we), + .wd (dio_pad_sleep_mode_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[33].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_33_qs) + ); + + + // Subregister 34 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_34]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_34_gated_we; + assign dio_pad_sleep_mode_34_gated_we = dio_pad_sleep_mode_34_we & dio_pad_sleep_regwen_34_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_34_gated_we), + .wd (dio_pad_sleep_mode_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[34].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_34_qs) + ); + + + // Subregister 35 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_35]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_35_gated_we; + assign dio_pad_sleep_mode_35_gated_we = dio_pad_sleep_mode_35_we & dio_pad_sleep_regwen_35_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_35_gated_we), + .wd (dio_pad_sleep_mode_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[35].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_35_qs) + ); + + + // Subregister 36 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_36]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_36_gated_we; + assign dio_pad_sleep_mode_36_gated_we = dio_pad_sleep_mode_36_we & dio_pad_sleep_regwen_36_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_36_gated_we), + .wd (dio_pad_sleep_mode_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[36].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_36_qs) + ); + + + // Subregister 37 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_37]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_37_gated_we; + assign dio_pad_sleep_mode_37_gated_we = dio_pad_sleep_mode_37_we & dio_pad_sleep_regwen_37_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_37_gated_we), + .wd (dio_pad_sleep_mode_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[37].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_37_qs) + ); + + + // Subregister 38 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_38]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_38_gated_we; + assign dio_pad_sleep_mode_38_gated_we = dio_pad_sleep_mode_38_we & dio_pad_sleep_regwen_38_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_38_gated_we), + .wd (dio_pad_sleep_mode_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[38].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_38_qs) + ); + + + // Subregister 39 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_39]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_39_gated_we; + assign dio_pad_sleep_mode_39_gated_we = dio_pad_sleep_mode_39_we & dio_pad_sleep_regwen_39_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_39_gated_we), + .wd (dio_pad_sleep_mode_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[39].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_39_qs) + ); + + + // Subregister 40 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_40]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_40_gated_we; + assign dio_pad_sleep_mode_40_gated_we = dio_pad_sleep_mode_40_we & dio_pad_sleep_regwen_40_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_40_gated_we), + .wd (dio_pad_sleep_mode_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[40].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_40_qs) + ); + + + // Subregister 41 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_41]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_41_gated_we; + assign dio_pad_sleep_mode_41_gated_we = dio_pad_sleep_mode_41_we & dio_pad_sleep_regwen_41_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_41_gated_we), + .wd (dio_pad_sleep_mode_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[41].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_41_qs) + ); + + + // Subregister 42 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_42]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_42_gated_we; + assign dio_pad_sleep_mode_42_gated_we = dio_pad_sleep_mode_42_we & dio_pad_sleep_regwen_42_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_42_gated_we), + .wd (dio_pad_sleep_mode_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[42].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_42_qs) + ); + + + // Subregister 43 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_43]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_43_gated_we; + assign dio_pad_sleep_mode_43_gated_we = dio_pad_sleep_mode_43_we & dio_pad_sleep_regwen_43_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_43_gated_we), + .wd (dio_pad_sleep_mode_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[43].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_43_qs) + ); + + + // Subregister 44 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_44]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_44_gated_we; + assign dio_pad_sleep_mode_44_gated_we = dio_pad_sleep_mode_44_we & dio_pad_sleep_regwen_44_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_44_gated_we), + .wd (dio_pad_sleep_mode_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[44].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_44_qs) + ); + + + // Subregister 45 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_45]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_45_gated_we; + assign dio_pad_sleep_mode_45_gated_we = dio_pad_sleep_mode_45_we & dio_pad_sleep_regwen_45_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_45_gated_we), + .wd (dio_pad_sleep_mode_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[45].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_45_qs) + ); + + + // Subregister 46 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_46]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_46_gated_we; + assign dio_pad_sleep_mode_46_gated_we = dio_pad_sleep_mode_46_we & dio_pad_sleep_regwen_46_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_46_gated_we), + .wd (dio_pad_sleep_mode_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[46].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_46_qs) + ); + + + // Subregister 47 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_47]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_47_gated_we; + assign dio_pad_sleep_mode_47_gated_we = dio_pad_sleep_mode_47_we & dio_pad_sleep_regwen_47_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_47_gated_we), + .wd (dio_pad_sleep_mode_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[47].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_47_qs) + ); + + + // Subregister 48 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_48]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_48_gated_we; + assign dio_pad_sleep_mode_48_gated_we = dio_pad_sleep_mode_48_we & dio_pad_sleep_regwen_48_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_48_gated_we), + .wd (dio_pad_sleep_mode_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[48].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_48_qs) + ); + + + // Subregister 49 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_49]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_49_gated_we; + assign dio_pad_sleep_mode_49_gated_we = dio_pad_sleep_mode_49_we & dio_pad_sleep_regwen_49_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_49_gated_we), + .wd (dio_pad_sleep_mode_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[49].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_49_qs) + ); + + + // Subregister 50 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_50]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_50_gated_we; + assign dio_pad_sleep_mode_50_gated_we = dio_pad_sleep_mode_50_we & dio_pad_sleep_regwen_50_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_50_gated_we), + .wd (dio_pad_sleep_mode_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[50].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_50_qs) + ); + + + // Subregister 51 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_51]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_51_gated_we; + assign dio_pad_sleep_mode_51_gated_we = dio_pad_sleep_mode_51_we & dio_pad_sleep_regwen_51_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_51_gated_we), + .wd (dio_pad_sleep_mode_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[51].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_51_qs) + ); + + + // Subregister 52 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_52]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_52_gated_we; + assign dio_pad_sleep_mode_52_gated_we = dio_pad_sleep_mode_52_we & dio_pad_sleep_regwen_52_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_52_gated_we), + .wd (dio_pad_sleep_mode_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[52].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_52_qs) + ); + + + // Subregister 53 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_53]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_53_gated_we; + assign dio_pad_sleep_mode_53_gated_we = dio_pad_sleep_mode_53_we & dio_pad_sleep_regwen_53_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_53_gated_we), + .wd (dio_pad_sleep_mode_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[53].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_53_qs) + ); + + + // Subregister 54 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_54]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_54_gated_we; + assign dio_pad_sleep_mode_54_gated_we = dio_pad_sleep_mode_54_we & dio_pad_sleep_regwen_54_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_54_gated_we), + .wd (dio_pad_sleep_mode_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[54].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_54_qs) + ); + + + // Subregister 55 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_55]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_55_gated_we; + assign dio_pad_sleep_mode_55_gated_we = dio_pad_sleep_mode_55_we & dio_pad_sleep_regwen_55_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_55_gated_we), + .wd (dio_pad_sleep_mode_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[55].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_55_qs) + ); + + + // Subregister 56 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_56]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_56_gated_we; + assign dio_pad_sleep_mode_56_gated_we = dio_pad_sleep_mode_56_we & dio_pad_sleep_regwen_56_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_56_gated_we), + .wd (dio_pad_sleep_mode_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[56].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_56_qs) + ); + + + // Subregister 57 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_57]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_57_gated_we; + assign dio_pad_sleep_mode_57_gated_we = dio_pad_sleep_mode_57_we & dio_pad_sleep_regwen_57_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_57_gated_we), + .wd (dio_pad_sleep_mode_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[57].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_57_qs) + ); + + + // Subregister 58 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_58]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_58_gated_we; + assign dio_pad_sleep_mode_58_gated_we = dio_pad_sleep_mode_58_we & dio_pad_sleep_regwen_58_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_58_gated_we), + .wd (dio_pad_sleep_mode_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[58].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_58_qs) + ); + + + // Subregister 59 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_59]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_59_gated_we; + assign dio_pad_sleep_mode_59_gated_we = dio_pad_sleep_mode_59_we & dio_pad_sleep_regwen_59_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_59_gated_we), + .wd (dio_pad_sleep_mode_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[59].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_59_qs) + ); + + + // Subregister 60 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_60]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_60_gated_we; + assign dio_pad_sleep_mode_60_gated_we = dio_pad_sleep_mode_60_we & dio_pad_sleep_regwen_60_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_60_gated_we), + .wd (dio_pad_sleep_mode_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[60].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_60_qs) + ); + + + // Subregister 61 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_61]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_61_gated_we; + assign dio_pad_sleep_mode_61_gated_we = dio_pad_sleep_mode_61_we & dio_pad_sleep_regwen_61_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_61_gated_we), + .wd (dio_pad_sleep_mode_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[61].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_61_qs) + ); + + + // Subregister 62 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_62]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_62_gated_we; + assign dio_pad_sleep_mode_62_gated_we = dio_pad_sleep_mode_62_we & dio_pad_sleep_regwen_62_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_62_gated_we), + .wd (dio_pad_sleep_mode_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[62].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_62_qs) + ); + + + // Subregister 63 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_63]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_63_gated_we; + assign dio_pad_sleep_mode_63_gated_we = dio_pad_sleep_mode_63_we & dio_pad_sleep_regwen_63_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_63_gated_we), + .wd (dio_pad_sleep_mode_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[63].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_63_qs) + ); + + + // Subregister 64 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_64]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_64_gated_we; + assign dio_pad_sleep_mode_64_gated_we = dio_pad_sleep_mode_64_we & dio_pad_sleep_regwen_64_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_64_gated_we), + .wd (dio_pad_sleep_mode_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[64].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_64_qs) + ); + + + // Subregister 65 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_65]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_65_gated_we; + assign dio_pad_sleep_mode_65_gated_we = dio_pad_sleep_mode_65_we & dio_pad_sleep_regwen_65_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_65_gated_we), + .wd (dio_pad_sleep_mode_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[65].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_65_qs) + ); + + + // Subregister 66 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_66]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_66_gated_we; + assign dio_pad_sleep_mode_66_gated_we = dio_pad_sleep_mode_66_we & dio_pad_sleep_regwen_66_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_66_gated_we), + .wd (dio_pad_sleep_mode_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[66].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_66_qs) + ); + + + // Subregister 67 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_67]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_67_gated_we; + assign dio_pad_sleep_mode_67_gated_we = dio_pad_sleep_mode_67_we & dio_pad_sleep_regwen_67_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_67_gated_we), + .wd (dio_pad_sleep_mode_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[67].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_67_qs) + ); + + + // Subregister 68 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_68]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_68_gated_we; + assign dio_pad_sleep_mode_68_gated_we = dio_pad_sleep_mode_68_we & dio_pad_sleep_regwen_68_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_68_gated_we), + .wd (dio_pad_sleep_mode_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[68].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_68_qs) + ); + + + // Subregister 69 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_69]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_69_gated_we; + assign dio_pad_sleep_mode_69_gated_we = dio_pad_sleep_mode_69_we & dio_pad_sleep_regwen_69_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_69_gated_we), + .wd (dio_pad_sleep_mode_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[69].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_69_qs) + ); + + + // Subregister 70 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_70]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_70_gated_we; + assign dio_pad_sleep_mode_70_gated_we = dio_pad_sleep_mode_70_we & dio_pad_sleep_regwen_70_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_70_gated_we), + .wd (dio_pad_sleep_mode_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[70].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_70_qs) + ); + + + // Subregister 71 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_71]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_71_gated_we; + assign dio_pad_sleep_mode_71_gated_we = dio_pad_sleep_mode_71_we & dio_pad_sleep_regwen_71_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_71_gated_we), + .wd (dio_pad_sleep_mode_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[71].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_71_qs) + ); + + + // Subregister 72 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_72]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_72_gated_we; + assign dio_pad_sleep_mode_72_gated_we = dio_pad_sleep_mode_72_we & dio_pad_sleep_regwen_72_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_72_gated_we), + .wd (dio_pad_sleep_mode_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[72].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_72_qs) + ); + + + // Subregister 0 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_0_we), + .wd (wkup_detector_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_0_qs) + ); + + + // Subregister 1 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_1_we), + .wd (wkup_detector_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_1_qs) + ); + + + // Subregister 2 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_2_we), + .wd (wkup_detector_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_2_qs) + ); + + + // Subregister 3 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_3_we), + .wd (wkup_detector_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_3_qs) + ); + + + // Subregister 4 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_4_we), + .wd (wkup_detector_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_4_qs) + ); + + + // Subregister 5 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_5_we), + .wd (wkup_detector_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_5_qs) + ); + + + // Subregister 6 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_6_we), + .wd (wkup_detector_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_6_qs) + ); + + + // Subregister 7 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_7_we), + .wd (wkup_detector_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_7_qs) + ); + + + // Subregister 0 of Multireg wkup_detector_en + // R[wkup_detector_en_0]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_0_gated_we; + assign aon_wkup_detector_en_0_gated_we = + aon_wkup_detector_en_0_we & aon_wkup_detector_en_0_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_0 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_0_gated_we), + .wd (aon_wkup_detector_en_0_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[0].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_0_qs_int) + ); + + + // Subregister 1 of Multireg wkup_detector_en + // R[wkup_detector_en_1]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_1_gated_we; + assign aon_wkup_detector_en_1_gated_we = + aon_wkup_detector_en_1_we & aon_wkup_detector_en_1_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_1 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_1_gated_we), + .wd (aon_wkup_detector_en_1_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[1].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_1_qs_int) + ); + + + // Subregister 2 of Multireg wkup_detector_en + // R[wkup_detector_en_2]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_2_gated_we; + assign aon_wkup_detector_en_2_gated_we = + aon_wkup_detector_en_2_we & aon_wkup_detector_en_2_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_2 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_2_gated_we), + .wd (aon_wkup_detector_en_2_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[2].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_2_qs_int) + ); + + + // Subregister 3 of Multireg wkup_detector_en + // R[wkup_detector_en_3]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_3_gated_we; + assign aon_wkup_detector_en_3_gated_we = + aon_wkup_detector_en_3_we & aon_wkup_detector_en_3_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_3 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_3_gated_we), + .wd (aon_wkup_detector_en_3_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[3].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_3_qs_int) + ); + + + // Subregister 4 of Multireg wkup_detector_en + // R[wkup_detector_en_4]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_4_gated_we; + assign aon_wkup_detector_en_4_gated_we = + aon_wkup_detector_en_4_we & aon_wkup_detector_en_4_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_4 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_4_gated_we), + .wd (aon_wkup_detector_en_4_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[4].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_4_qs_int) + ); + + + // Subregister 5 of Multireg wkup_detector_en + // R[wkup_detector_en_5]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_5_gated_we; + assign aon_wkup_detector_en_5_gated_we = + aon_wkup_detector_en_5_we & aon_wkup_detector_en_5_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_5 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_5_gated_we), + .wd (aon_wkup_detector_en_5_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[5].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_5_qs_int) + ); + + + // Subregister 6 of Multireg wkup_detector_en + // R[wkup_detector_en_6]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_6_gated_we; + assign aon_wkup_detector_en_6_gated_we = + aon_wkup_detector_en_6_we & aon_wkup_detector_en_6_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_6 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_6_gated_we), + .wd (aon_wkup_detector_en_6_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[6].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_6_qs_int) + ); + + + // Subregister 7 of Multireg wkup_detector_en + // R[wkup_detector_en_7]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_7_gated_we; + assign aon_wkup_detector_en_7_gated_we = + aon_wkup_detector_en_7_we & aon_wkup_detector_en_7_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_7 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_7_gated_we), + .wd (aon_wkup_detector_en_7_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[7].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_7_qs_int) + ); + + + // Subregister 0 of Multireg wkup_detector + // R[wkup_detector_0]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_0_gated_we; + assign aon_wkup_detector_0_gated_we = aon_wkup_detector_0_we & aon_wkup_detector_0_regwen; + // F[mode_0]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_0_mode_0 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_0_gated_we), + .wd (aon_wkup_detector_0_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[0].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_0_mode_0_qs_int) + ); + + // F[filter_0]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_0_filter_0 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_0_gated_we), + .wd (aon_wkup_detector_0_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[0].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_0_filter_0_qs_int) + ); + + // F[miodio_0]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_0_miodio_0 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_0_gated_we), + .wd (aon_wkup_detector_0_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[0].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_0_miodio_0_qs_int) + ); + + + // Subregister 1 of Multireg wkup_detector + // R[wkup_detector_1]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_1_gated_we; + assign aon_wkup_detector_1_gated_we = aon_wkup_detector_1_we & aon_wkup_detector_1_regwen; + // F[mode_1]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_1_mode_1 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_1_gated_we), + .wd (aon_wkup_detector_1_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[1].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_1_mode_1_qs_int) + ); + + // F[filter_1]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_1_filter_1 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_1_gated_we), + .wd (aon_wkup_detector_1_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[1].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_1_filter_1_qs_int) + ); + + // F[miodio_1]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_1_miodio_1 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_1_gated_we), + .wd (aon_wkup_detector_1_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[1].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_1_miodio_1_qs_int) + ); + + + // Subregister 2 of Multireg wkup_detector + // R[wkup_detector_2]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_2_gated_we; + assign aon_wkup_detector_2_gated_we = aon_wkup_detector_2_we & aon_wkup_detector_2_regwen; + // F[mode_2]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_2_mode_2 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_2_gated_we), + .wd (aon_wkup_detector_2_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[2].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_2_mode_2_qs_int) + ); + + // F[filter_2]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_2_filter_2 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_2_gated_we), + .wd (aon_wkup_detector_2_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[2].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_2_filter_2_qs_int) + ); + + // F[miodio_2]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_2_miodio_2 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_2_gated_we), + .wd (aon_wkup_detector_2_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[2].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_2_miodio_2_qs_int) + ); + + + // Subregister 3 of Multireg wkup_detector + // R[wkup_detector_3]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_3_gated_we; + assign aon_wkup_detector_3_gated_we = aon_wkup_detector_3_we & aon_wkup_detector_3_regwen; + // F[mode_3]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_3_mode_3 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_3_gated_we), + .wd (aon_wkup_detector_3_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[3].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_3_mode_3_qs_int) + ); + + // F[filter_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_3_filter_3 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_3_gated_we), + .wd (aon_wkup_detector_3_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[3].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_3_filter_3_qs_int) + ); + + // F[miodio_3]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_3_miodio_3 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_3_gated_we), + .wd (aon_wkup_detector_3_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[3].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_3_miodio_3_qs_int) + ); + + + // Subregister 4 of Multireg wkup_detector + // R[wkup_detector_4]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_4_gated_we; + assign aon_wkup_detector_4_gated_we = aon_wkup_detector_4_we & aon_wkup_detector_4_regwen; + // F[mode_4]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_4_mode_4 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_4_gated_we), + .wd (aon_wkup_detector_4_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[4].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_4_mode_4_qs_int) + ); + + // F[filter_4]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_4_filter_4 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_4_gated_we), + .wd (aon_wkup_detector_4_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[4].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_4_filter_4_qs_int) + ); + + // F[miodio_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_4_miodio_4 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_4_gated_we), + .wd (aon_wkup_detector_4_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[4].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_4_miodio_4_qs_int) + ); + + + // Subregister 5 of Multireg wkup_detector + // R[wkup_detector_5]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_5_gated_we; + assign aon_wkup_detector_5_gated_we = aon_wkup_detector_5_we & aon_wkup_detector_5_regwen; + // F[mode_5]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_5_mode_5 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_5_gated_we), + .wd (aon_wkup_detector_5_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[5].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_5_mode_5_qs_int) + ); + + // F[filter_5]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_5_filter_5 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_5_gated_we), + .wd (aon_wkup_detector_5_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[5].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_5_filter_5_qs_int) + ); + + // F[miodio_5]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_5_miodio_5 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_5_gated_we), + .wd (aon_wkup_detector_5_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[5].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_5_miodio_5_qs_int) + ); + + + // Subregister 6 of Multireg wkup_detector + // R[wkup_detector_6]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_6_gated_we; + assign aon_wkup_detector_6_gated_we = aon_wkup_detector_6_we & aon_wkup_detector_6_regwen; + // F[mode_6]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_6_mode_6 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_6_gated_we), + .wd (aon_wkup_detector_6_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[6].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_6_mode_6_qs_int) + ); + + // F[filter_6]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_6_filter_6 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_6_gated_we), + .wd (aon_wkup_detector_6_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[6].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_6_filter_6_qs_int) + ); + + // F[miodio_6]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_6_miodio_6 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_6_gated_we), + .wd (aon_wkup_detector_6_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[6].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_6_miodio_6_qs_int) + ); + + + // Subregister 7 of Multireg wkup_detector + // R[wkup_detector_7]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_7_gated_we; + assign aon_wkup_detector_7_gated_we = aon_wkup_detector_7_we & aon_wkup_detector_7_regwen; + // F[mode_7]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_7_mode_7 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_7_gated_we), + .wd (aon_wkup_detector_7_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[7].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_7_mode_7_qs_int) + ); + + // F[filter_7]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_7_filter_7 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_7_gated_we), + .wd (aon_wkup_detector_7_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[7].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_7_filter_7_qs_int) + ); + + // F[miodio_7]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_7_miodio_7 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_7_gated_we), + .wd (aon_wkup_detector_7_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[7].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_7_miodio_7_qs_int) + ); + + + // Subregister 0 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_0]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_0_gated_we; + assign aon_wkup_detector_cnt_th_0_gated_we = + aon_wkup_detector_cnt_th_0_we & aon_wkup_detector_cnt_th_0_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_0 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_0_gated_we), + .wd (aon_wkup_detector_cnt_th_0_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[0].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_0_qs_int) + ); + + + // Subregister 1 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_1]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_1_gated_we; + assign aon_wkup_detector_cnt_th_1_gated_we = + aon_wkup_detector_cnt_th_1_we & aon_wkup_detector_cnt_th_1_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_1 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_1_gated_we), + .wd (aon_wkup_detector_cnt_th_1_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[1].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_1_qs_int) + ); + + + // Subregister 2 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_2]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_2_gated_we; + assign aon_wkup_detector_cnt_th_2_gated_we = + aon_wkup_detector_cnt_th_2_we & aon_wkup_detector_cnt_th_2_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_2 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_2_gated_we), + .wd (aon_wkup_detector_cnt_th_2_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[2].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_2_qs_int) + ); + + + // Subregister 3 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_3]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_3_gated_we; + assign aon_wkup_detector_cnt_th_3_gated_we = + aon_wkup_detector_cnt_th_3_we & aon_wkup_detector_cnt_th_3_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_3 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_3_gated_we), + .wd (aon_wkup_detector_cnt_th_3_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[3].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_3_qs_int) + ); + + + // Subregister 4 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_4]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_4_gated_we; + assign aon_wkup_detector_cnt_th_4_gated_we = + aon_wkup_detector_cnt_th_4_we & aon_wkup_detector_cnt_th_4_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_4 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_4_gated_we), + .wd (aon_wkup_detector_cnt_th_4_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[4].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_4_qs_int) + ); + + + // Subregister 5 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_5]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_5_gated_we; + assign aon_wkup_detector_cnt_th_5_gated_we = + aon_wkup_detector_cnt_th_5_we & aon_wkup_detector_cnt_th_5_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_5 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_5_gated_we), + .wd (aon_wkup_detector_cnt_th_5_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[5].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_5_qs_int) + ); + + + // Subregister 6 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_6]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_6_gated_we; + assign aon_wkup_detector_cnt_th_6_gated_we = + aon_wkup_detector_cnt_th_6_we & aon_wkup_detector_cnt_th_6_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_6 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_6_gated_we), + .wd (aon_wkup_detector_cnt_th_6_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[6].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_6_qs_int) + ); + + + // Subregister 7 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_7]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_7_gated_we; + assign aon_wkup_detector_cnt_th_7_gated_we = + aon_wkup_detector_cnt_th_7_we & aon_wkup_detector_cnt_th_7_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_7 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_7_gated_we), + .wd (aon_wkup_detector_cnt_th_7_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[7].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_7_qs_int) + ); + + + // Subregister 0 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_0]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_0_gated_we; + assign wkup_detector_padsel_0_gated_we = wkup_detector_padsel_0_we & wkup_detector_regwen_0_qs; + prim_subreg #( + .DW (6), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_0_gated_we), + .wd (wkup_detector_padsel_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[0].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_0_qs) + ); + + + // Subregister 1 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_1]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_1_gated_we; + assign wkup_detector_padsel_1_gated_we = wkup_detector_padsel_1_we & wkup_detector_regwen_1_qs; + prim_subreg #( + .DW (6), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_1_gated_we), + .wd (wkup_detector_padsel_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[1].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_1_qs) + ); + + + // Subregister 2 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_2]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_2_gated_we; + assign wkup_detector_padsel_2_gated_we = wkup_detector_padsel_2_we & wkup_detector_regwen_2_qs; + prim_subreg #( + .DW (6), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_2_gated_we), + .wd (wkup_detector_padsel_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[2].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_2_qs) + ); + + + // Subregister 3 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_3]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_3_gated_we; + assign wkup_detector_padsel_3_gated_we = wkup_detector_padsel_3_we & wkup_detector_regwen_3_qs; + prim_subreg #( + .DW (6), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_3_gated_we), + .wd (wkup_detector_padsel_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[3].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_3_qs) + ); + + + // Subregister 4 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_4]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_4_gated_we; + assign wkup_detector_padsel_4_gated_we = wkup_detector_padsel_4_we & wkup_detector_regwen_4_qs; + prim_subreg #( + .DW (6), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_4_gated_we), + .wd (wkup_detector_padsel_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[4].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_4_qs) + ); + + + // Subregister 5 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_5]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_5_gated_we; + assign wkup_detector_padsel_5_gated_we = wkup_detector_padsel_5_we & wkup_detector_regwen_5_qs; + prim_subreg #( + .DW (6), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_5_gated_we), + .wd (wkup_detector_padsel_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[5].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_5_qs) + ); + + + // Subregister 6 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_6]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_6_gated_we; + assign wkup_detector_padsel_6_gated_we = wkup_detector_padsel_6_we & wkup_detector_regwen_6_qs; + prim_subreg #( + .DW (6), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_6_gated_we), + .wd (wkup_detector_padsel_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[6].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_6_qs) + ); + + + // Subregister 7 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_7]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_7_gated_we; + assign wkup_detector_padsel_7_gated_we = wkup_detector_padsel_7_we & wkup_detector_regwen_7_qs; + prim_subreg #( + .DW (6), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (6'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_7_gated_we), + .wd (wkup_detector_padsel_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[7].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_7_qs) + ); + + + // Subregister 0 of Multireg wkup_cause + // R[wkup_cause]: V(False) + logic [7:0] wkup_cause_flds_we; + assign aon_wkup_cause_qe = |wkup_cause_flds_we; + // F[cause_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_0 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[0]), + + // from internal hardware + .de (hw2reg.wkup_cause[0].de), + .d (hw2reg.wkup_cause[0].d), + + // to internal hardware + .qe (wkup_cause_flds_we[0]), + .q (reg2hw.wkup_cause[0].q), + .ds (aon_wkup_cause_cause_0_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_0_qs_int) + ); + + // F[cause_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_1 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[1]), + + // from internal hardware + .de (hw2reg.wkup_cause[1].de), + .d (hw2reg.wkup_cause[1].d), + + // to internal hardware + .qe (wkup_cause_flds_we[1]), + .q (reg2hw.wkup_cause[1].q), + .ds (aon_wkup_cause_cause_1_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_1_qs_int) + ); + + // F[cause_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_2 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[2]), + + // from internal hardware + .de (hw2reg.wkup_cause[2].de), + .d (hw2reg.wkup_cause[2].d), + + // to internal hardware + .qe (wkup_cause_flds_we[2]), + .q (reg2hw.wkup_cause[2].q), + .ds (aon_wkup_cause_cause_2_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_2_qs_int) + ); + + // F[cause_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_3 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[3]), + + // from internal hardware + .de (hw2reg.wkup_cause[3].de), + .d (hw2reg.wkup_cause[3].d), + + // to internal hardware + .qe (wkup_cause_flds_we[3]), + .q (reg2hw.wkup_cause[3].q), + .ds (aon_wkup_cause_cause_3_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_3_qs_int) + ); + + // F[cause_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_4 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[4]), + + // from internal hardware + .de (hw2reg.wkup_cause[4].de), + .d (hw2reg.wkup_cause[4].d), + + // to internal hardware + .qe (wkup_cause_flds_we[4]), + .q (reg2hw.wkup_cause[4].q), + .ds (aon_wkup_cause_cause_4_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_4_qs_int) + ); + + // F[cause_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_5 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[5]), + + // from internal hardware + .de (hw2reg.wkup_cause[5].de), + .d (hw2reg.wkup_cause[5].d), + + // to internal hardware + .qe (wkup_cause_flds_we[5]), + .q (reg2hw.wkup_cause[5].q), + .ds (aon_wkup_cause_cause_5_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_5_qs_int) + ); + + // F[cause_6]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_6 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[6]), + + // from internal hardware + .de (hw2reg.wkup_cause[6].de), + .d (hw2reg.wkup_cause[6].d), + + // to internal hardware + .qe (wkup_cause_flds_we[6]), + .q (reg2hw.wkup_cause[6].q), + .ds (aon_wkup_cause_cause_6_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_6_qs_int) + ); + + // F[cause_7]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_7 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[7]), + + // from internal hardware + .de (hw2reg.wkup_cause[7].de), + .d (hw2reg.wkup_cause[7].d), + + // to internal hardware + .qe (wkup_cause_flds_we[7]), + .q (reg2hw.wkup_cause[7].q), + .ds (aon_wkup_cause_cause_7_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_7_qs_int) + ); + + + + logic [502:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == PINMUX_ALERT_TEST_OFFSET); + addr_hit[ 1] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET); + addr_hit[ 2] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET); + addr_hit[ 3] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET); + addr_hit[ 4] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET); + addr_hit[ 5] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET); + addr_hit[ 6] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET); + addr_hit[ 7] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET); + addr_hit[ 8] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET); + addr_hit[ 9] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET); + addr_hit[ 10] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET); + addr_hit[ 11] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET); + addr_hit[ 12] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET); + addr_hit[ 13] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET); + addr_hit[ 14] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET); + addr_hit[ 15] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET); + addr_hit[ 16] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET); + addr_hit[ 17] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET); + addr_hit[ 18] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET); + addr_hit[ 19] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET); + addr_hit[ 20] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET); + addr_hit[ 21] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); + addr_hit[ 22] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); + addr_hit[ 23] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); + addr_hit[ 24] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); + addr_hit[ 25] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); + addr_hit[ 26] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); + addr_hit[ 27] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); + addr_hit[ 28] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET); + addr_hit[ 29] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET); + addr_hit[ 30] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET); + addr_hit[ 31] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET); + addr_hit[ 32] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET); + addr_hit[ 33] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[ 34] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[ 35] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[ 36] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[ 37] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[ 38] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[ 39] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[ 40] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[ 41] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[ 42] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[ 43] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[ 44] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[ 45] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); + addr_hit[ 46] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); + addr_hit[ 47] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); + addr_hit[ 48] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); + addr_hit[ 49] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); + addr_hit[ 50] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); + addr_hit[ 51] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); + addr_hit[ 52] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); + addr_hit[ 53] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); + addr_hit[ 54] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); + addr_hit[ 55] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); + addr_hit[ 56] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); + addr_hit[ 57] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[ 58] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[ 59] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[ 60] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[ 61] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[ 62] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[ 63] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[ 64] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[ 65] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[ 66] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[ 67] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[ 68] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[ 69] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[ 70] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[ 71] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[ 72] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[ 73] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET); + addr_hit[ 74] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET); + addr_hit[ 75] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET); + addr_hit[ 76] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET); + addr_hit[ 77] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET); + addr_hit[ 78] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET); + addr_hit[ 79] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET); + addr_hit[ 80] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_23_OFFSET); + addr_hit[ 81] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_24_OFFSET); + addr_hit[ 82] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_25_OFFSET); + addr_hit[ 83] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_26_OFFSET); + addr_hit[ 84] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_27_OFFSET); + addr_hit[ 85] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_28_OFFSET); + addr_hit[ 86] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_29_OFFSET); + addr_hit[ 87] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_30_OFFSET); + addr_hit[ 88] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_31_OFFSET); + addr_hit[ 89] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_32_OFFSET); + addr_hit[ 90] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_33_OFFSET); + addr_hit[ 91] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_34_OFFSET); + addr_hit[ 92] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_35_OFFSET); + addr_hit[ 93] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_36_OFFSET); + addr_hit[ 94] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_37_OFFSET); + addr_hit[ 95] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_38_OFFSET); + addr_hit[ 96] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_39_OFFSET); + addr_hit[ 97] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_40_OFFSET); + addr_hit[ 98] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_41_OFFSET); + addr_hit[ 99] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_42_OFFSET); + addr_hit[100] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_43_OFFSET); + addr_hit[101] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_44_OFFSET); + addr_hit[102] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_45_OFFSET); + addr_hit[103] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_46_OFFSET); + addr_hit[104] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_47_OFFSET); + addr_hit[105] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_48_OFFSET); + addr_hit[106] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_49_OFFSET); + addr_hit[107] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_50_OFFSET); + addr_hit[108] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_51_OFFSET); + addr_hit[109] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_52_OFFSET); + addr_hit[110] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_53_OFFSET); + addr_hit[111] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_54_OFFSET); + addr_hit[112] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_55_OFFSET); + addr_hit[113] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_56_OFFSET); + addr_hit[114] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_57_OFFSET); + addr_hit[115] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_58_OFFSET); + addr_hit[116] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_59_OFFSET); + addr_hit[117] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_60_OFFSET); + addr_hit[118] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_61_OFFSET); + addr_hit[119] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_62_OFFSET); + addr_hit[120] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_63_OFFSET); + addr_hit[121] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_64_OFFSET); + addr_hit[122] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_65_OFFSET); + addr_hit[123] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_66_OFFSET); + addr_hit[124] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_67_OFFSET); + addr_hit[125] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_68_OFFSET); + addr_hit[126] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_69_OFFSET); + addr_hit[127] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_70_OFFSET); + addr_hit[128] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_71_OFFSET); + addr_hit[129] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_72_OFFSET); + addr_hit[130] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); + addr_hit[131] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); + addr_hit[132] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); + addr_hit[133] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); + addr_hit[134] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); + addr_hit[135] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); + addr_hit[136] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); + addr_hit[137] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); + addr_hit[138] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); + addr_hit[139] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); + addr_hit[140] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); + addr_hit[141] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); + addr_hit[142] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); + addr_hit[143] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); + addr_hit[144] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET); + addr_hit[145] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET); + addr_hit[146] = (reg_addr == PINMUX_DIO_PAD_ATTR_16_OFFSET); + addr_hit[147] = (reg_addr == PINMUX_DIO_PAD_ATTR_17_OFFSET); + addr_hit[148] = (reg_addr == PINMUX_DIO_PAD_ATTR_18_OFFSET); + addr_hit[149] = (reg_addr == PINMUX_DIO_PAD_ATTR_19_OFFSET); + addr_hit[150] = (reg_addr == PINMUX_DIO_PAD_ATTR_20_OFFSET); + addr_hit[151] = (reg_addr == PINMUX_DIO_PAD_ATTR_21_OFFSET); + addr_hit[152] = (reg_addr == PINMUX_DIO_PAD_ATTR_22_OFFSET); + addr_hit[153] = (reg_addr == PINMUX_DIO_PAD_ATTR_23_OFFSET); + addr_hit[154] = (reg_addr == PINMUX_DIO_PAD_ATTR_24_OFFSET); + addr_hit[155] = (reg_addr == PINMUX_DIO_PAD_ATTR_25_OFFSET); + addr_hit[156] = (reg_addr == PINMUX_DIO_PAD_ATTR_26_OFFSET); + addr_hit[157] = (reg_addr == PINMUX_DIO_PAD_ATTR_27_OFFSET); + addr_hit[158] = (reg_addr == PINMUX_DIO_PAD_ATTR_28_OFFSET); + addr_hit[159] = (reg_addr == PINMUX_DIO_PAD_ATTR_29_OFFSET); + addr_hit[160] = (reg_addr == PINMUX_DIO_PAD_ATTR_30_OFFSET); + addr_hit[161] = (reg_addr == PINMUX_DIO_PAD_ATTR_31_OFFSET); + addr_hit[162] = (reg_addr == PINMUX_DIO_PAD_ATTR_32_OFFSET); + addr_hit[163] = (reg_addr == PINMUX_DIO_PAD_ATTR_33_OFFSET); + addr_hit[164] = (reg_addr == PINMUX_DIO_PAD_ATTR_34_OFFSET); + addr_hit[165] = (reg_addr == PINMUX_DIO_PAD_ATTR_35_OFFSET); + addr_hit[166] = (reg_addr == PINMUX_DIO_PAD_ATTR_36_OFFSET); + addr_hit[167] = (reg_addr == PINMUX_DIO_PAD_ATTR_37_OFFSET); + addr_hit[168] = (reg_addr == PINMUX_DIO_PAD_ATTR_38_OFFSET); + addr_hit[169] = (reg_addr == PINMUX_DIO_PAD_ATTR_39_OFFSET); + addr_hit[170] = (reg_addr == PINMUX_DIO_PAD_ATTR_40_OFFSET); + addr_hit[171] = (reg_addr == PINMUX_DIO_PAD_ATTR_41_OFFSET); + addr_hit[172] = (reg_addr == PINMUX_DIO_PAD_ATTR_42_OFFSET); + addr_hit[173] = (reg_addr == PINMUX_DIO_PAD_ATTR_43_OFFSET); + addr_hit[174] = (reg_addr == PINMUX_DIO_PAD_ATTR_44_OFFSET); + addr_hit[175] = (reg_addr == PINMUX_DIO_PAD_ATTR_45_OFFSET); + addr_hit[176] = (reg_addr == PINMUX_DIO_PAD_ATTR_46_OFFSET); + addr_hit[177] = (reg_addr == PINMUX_DIO_PAD_ATTR_47_OFFSET); + addr_hit[178] = (reg_addr == PINMUX_DIO_PAD_ATTR_48_OFFSET); + addr_hit[179] = (reg_addr == PINMUX_DIO_PAD_ATTR_49_OFFSET); + addr_hit[180] = (reg_addr == PINMUX_DIO_PAD_ATTR_50_OFFSET); + addr_hit[181] = (reg_addr == PINMUX_DIO_PAD_ATTR_51_OFFSET); + addr_hit[182] = (reg_addr == PINMUX_DIO_PAD_ATTR_52_OFFSET); + addr_hit[183] = (reg_addr == PINMUX_DIO_PAD_ATTR_53_OFFSET); + addr_hit[184] = (reg_addr == PINMUX_DIO_PAD_ATTR_54_OFFSET); + addr_hit[185] = (reg_addr == PINMUX_DIO_PAD_ATTR_55_OFFSET); + addr_hit[186] = (reg_addr == PINMUX_DIO_PAD_ATTR_56_OFFSET); + addr_hit[187] = (reg_addr == PINMUX_DIO_PAD_ATTR_57_OFFSET); + addr_hit[188] = (reg_addr == PINMUX_DIO_PAD_ATTR_58_OFFSET); + addr_hit[189] = (reg_addr == PINMUX_DIO_PAD_ATTR_59_OFFSET); + addr_hit[190] = (reg_addr == PINMUX_DIO_PAD_ATTR_60_OFFSET); + addr_hit[191] = (reg_addr == PINMUX_DIO_PAD_ATTR_61_OFFSET); + addr_hit[192] = (reg_addr == PINMUX_DIO_PAD_ATTR_62_OFFSET); + addr_hit[193] = (reg_addr == PINMUX_DIO_PAD_ATTR_63_OFFSET); + addr_hit[194] = (reg_addr == PINMUX_DIO_PAD_ATTR_64_OFFSET); + addr_hit[195] = (reg_addr == PINMUX_DIO_PAD_ATTR_65_OFFSET); + addr_hit[196] = (reg_addr == PINMUX_DIO_PAD_ATTR_66_OFFSET); + addr_hit[197] = (reg_addr == PINMUX_DIO_PAD_ATTR_67_OFFSET); + addr_hit[198] = (reg_addr == PINMUX_DIO_PAD_ATTR_68_OFFSET); + addr_hit[199] = (reg_addr == PINMUX_DIO_PAD_ATTR_69_OFFSET); + addr_hit[200] = (reg_addr == PINMUX_DIO_PAD_ATTR_70_OFFSET); + addr_hit[201] = (reg_addr == PINMUX_DIO_PAD_ATTR_71_OFFSET); + addr_hit[202] = (reg_addr == PINMUX_DIO_PAD_ATTR_72_OFFSET); + addr_hit[203] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET); + addr_hit[204] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[205] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[206] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[207] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[208] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[210] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[211] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[212] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[213] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[214] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[240] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_0_OFFSET); + addr_hit[241] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_1_OFFSET); + addr_hit[242] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_2_OFFSET); + addr_hit[243] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[244] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[245] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[246] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[247] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[248] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[249] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[250] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[251] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[252] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[253] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[254] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[255] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[256] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[257] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[258] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[259] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET); + addr_hit[260] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET); + addr_hit[261] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET); + addr_hit[262] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET); + addr_hit[263] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET); + addr_hit[264] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET); + addr_hit[265] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET); + addr_hit[266] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_23_OFFSET); + addr_hit[267] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_24_OFFSET); + addr_hit[268] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_25_OFFSET); + addr_hit[269] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_26_OFFSET); + addr_hit[270] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_27_OFFSET); + addr_hit[271] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_28_OFFSET); + addr_hit[272] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_29_OFFSET); + addr_hit[273] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_30_OFFSET); + addr_hit[274] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_31_OFFSET); + addr_hit[275] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_32_OFFSET); + addr_hit[276] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_33_OFFSET); + addr_hit[277] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_34_OFFSET); + addr_hit[278] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_35_OFFSET); + addr_hit[279] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_36_OFFSET); + addr_hit[280] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_37_OFFSET); + addr_hit[281] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_38_OFFSET); + addr_hit[282] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_39_OFFSET); + addr_hit[283] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_40_OFFSET); + addr_hit[284] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_41_OFFSET); + addr_hit[285] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_42_OFFSET); + addr_hit[286] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_43_OFFSET); + addr_hit[287] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_44_OFFSET); + addr_hit[288] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_45_OFFSET); + addr_hit[289] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_46_OFFSET); + addr_hit[290] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_47_OFFSET); + addr_hit[291] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_48_OFFSET); + addr_hit[292] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_49_OFFSET); + addr_hit[293] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_50_OFFSET); + addr_hit[294] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_51_OFFSET); + addr_hit[295] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_52_OFFSET); + addr_hit[296] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_53_OFFSET); + addr_hit[297] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_54_OFFSET); + addr_hit[298] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_55_OFFSET); + addr_hit[299] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_56_OFFSET); + addr_hit[300] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_57_OFFSET); + addr_hit[301] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_58_OFFSET); + addr_hit[302] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_59_OFFSET); + addr_hit[303] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_60_OFFSET); + addr_hit[304] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_61_OFFSET); + addr_hit[305] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_62_OFFSET); + addr_hit[306] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_63_OFFSET); + addr_hit[307] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_64_OFFSET); + addr_hit[308] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_65_OFFSET); + addr_hit[309] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_66_OFFSET); + addr_hit[310] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_67_OFFSET); + addr_hit[311] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_68_OFFSET); + addr_hit[312] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_69_OFFSET); + addr_hit[313] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_70_OFFSET); + addr_hit[314] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_71_OFFSET); + addr_hit[315] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_72_OFFSET); + addr_hit[316] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[317] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET); + addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET); + addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET); + addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET); + addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET); + addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET); + addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET); + addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_23_OFFSET); + addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_24_OFFSET); + addr_hit[341] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_25_OFFSET); + addr_hit[342] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_26_OFFSET); + addr_hit[343] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_27_OFFSET); + addr_hit[344] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_28_OFFSET); + addr_hit[345] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_29_OFFSET); + addr_hit[346] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_30_OFFSET); + addr_hit[347] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_31_OFFSET); + addr_hit[348] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_32_OFFSET); + addr_hit[349] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_33_OFFSET); + addr_hit[350] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_34_OFFSET); + addr_hit[351] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_35_OFFSET); + addr_hit[352] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_36_OFFSET); + addr_hit[353] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_37_OFFSET); + addr_hit[354] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_38_OFFSET); + addr_hit[355] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_39_OFFSET); + addr_hit[356] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_40_OFFSET); + addr_hit[357] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_41_OFFSET); + addr_hit[358] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_42_OFFSET); + addr_hit[359] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_43_OFFSET); + addr_hit[360] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_44_OFFSET); + addr_hit[361] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_45_OFFSET); + addr_hit[362] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_46_OFFSET); + addr_hit[363] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_47_OFFSET); + addr_hit[364] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_48_OFFSET); + addr_hit[365] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_49_OFFSET); + addr_hit[366] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_50_OFFSET); + addr_hit[367] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_51_OFFSET); + addr_hit[368] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_52_OFFSET); + addr_hit[369] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_53_OFFSET); + addr_hit[370] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_54_OFFSET); + addr_hit[371] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_55_OFFSET); + addr_hit[372] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_56_OFFSET); + addr_hit[373] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_57_OFFSET); + addr_hit[374] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_58_OFFSET); + addr_hit[375] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_59_OFFSET); + addr_hit[376] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_60_OFFSET); + addr_hit[377] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_61_OFFSET); + addr_hit[378] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_62_OFFSET); + addr_hit[379] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_63_OFFSET); + addr_hit[380] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_64_OFFSET); + addr_hit[381] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_65_OFFSET); + addr_hit[382] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_66_OFFSET); + addr_hit[383] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_67_OFFSET); + addr_hit[384] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_68_OFFSET); + addr_hit[385] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_69_OFFSET); + addr_hit[386] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_70_OFFSET); + addr_hit[387] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_71_OFFSET); + addr_hit[388] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_72_OFFSET); + addr_hit[389] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[390] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[391] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[392] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[393] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[394] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[395] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[396] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[397] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[398] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[399] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[400] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[401] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[402] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[403] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[404] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[405] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET); + addr_hit[406] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET); + addr_hit[407] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET); + addr_hit[408] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET); + addr_hit[409] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET); + addr_hit[410] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET); + addr_hit[411] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET); + addr_hit[412] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_23_OFFSET); + addr_hit[413] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_24_OFFSET); + addr_hit[414] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_25_OFFSET); + addr_hit[415] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_26_OFFSET); + addr_hit[416] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_27_OFFSET); + addr_hit[417] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_28_OFFSET); + addr_hit[418] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_29_OFFSET); + addr_hit[419] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_30_OFFSET); + addr_hit[420] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_31_OFFSET); + addr_hit[421] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_32_OFFSET); + addr_hit[422] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_33_OFFSET); + addr_hit[423] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_34_OFFSET); + addr_hit[424] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_35_OFFSET); + addr_hit[425] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_36_OFFSET); + addr_hit[426] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_37_OFFSET); + addr_hit[427] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_38_OFFSET); + addr_hit[428] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_39_OFFSET); + addr_hit[429] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_40_OFFSET); + addr_hit[430] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_41_OFFSET); + addr_hit[431] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_42_OFFSET); + addr_hit[432] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_43_OFFSET); + addr_hit[433] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_44_OFFSET); + addr_hit[434] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_45_OFFSET); + addr_hit[435] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_46_OFFSET); + addr_hit[436] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_47_OFFSET); + addr_hit[437] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_48_OFFSET); + addr_hit[438] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_49_OFFSET); + addr_hit[439] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_50_OFFSET); + addr_hit[440] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_51_OFFSET); + addr_hit[441] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_52_OFFSET); + addr_hit[442] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_53_OFFSET); + addr_hit[443] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_54_OFFSET); + addr_hit[444] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_55_OFFSET); + addr_hit[445] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_56_OFFSET); + addr_hit[446] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_57_OFFSET); + addr_hit[447] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_58_OFFSET); + addr_hit[448] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_59_OFFSET); + addr_hit[449] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_60_OFFSET); + addr_hit[450] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_61_OFFSET); + addr_hit[451] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_62_OFFSET); + addr_hit[452] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_63_OFFSET); + addr_hit[453] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_64_OFFSET); + addr_hit[454] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_65_OFFSET); + addr_hit[455] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_66_OFFSET); + addr_hit[456] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_67_OFFSET); + addr_hit[457] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_68_OFFSET); + addr_hit[458] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_69_OFFSET); + addr_hit[459] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_70_OFFSET); + addr_hit[460] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_71_OFFSET); + addr_hit[461] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_72_OFFSET); + addr_hit[462] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); + addr_hit[463] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); + addr_hit[464] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); + addr_hit[465] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); + addr_hit[466] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); + addr_hit[467] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); + addr_hit[468] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); + addr_hit[469] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); + addr_hit[470] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); + addr_hit[471] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); + addr_hit[472] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); + addr_hit[473] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); + addr_hit[474] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); + addr_hit[475] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); + addr_hit[476] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); + addr_hit[477] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); + addr_hit[478] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); + addr_hit[479] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); + addr_hit[480] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); + addr_hit[481] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); + addr_hit[482] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); + addr_hit[483] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); + addr_hit[484] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); + addr_hit[485] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); + addr_hit[486] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); + addr_hit[487] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); + addr_hit[488] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); + addr_hit[489] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); + addr_hit[490] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); + addr_hit[491] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); + addr_hit[492] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); + addr_hit[493] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); + addr_hit[494] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); + addr_hit[495] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); + addr_hit[496] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); + addr_hit[497] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); + addr_hit[498] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); + addr_hit[499] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); + addr_hit[500] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); + addr_hit[501] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); + addr_hit[502] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(PINMUX_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(PINMUX_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(PINMUX_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(PINMUX_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(PINMUX_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(PINMUX_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(PINMUX_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(PINMUX_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(PINMUX_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(PINMUX_PERMIT[ 9] & ~reg_be))) | + (addr_hit[ 10] & (|(PINMUX_PERMIT[ 10] & ~reg_be))) | + (addr_hit[ 11] & (|(PINMUX_PERMIT[ 11] & ~reg_be))) | + (addr_hit[ 12] & (|(PINMUX_PERMIT[ 12] & ~reg_be))) | + (addr_hit[ 13] & (|(PINMUX_PERMIT[ 13] & ~reg_be))) | + (addr_hit[ 14] & (|(PINMUX_PERMIT[ 14] & ~reg_be))) | + (addr_hit[ 15] & (|(PINMUX_PERMIT[ 15] & ~reg_be))) | + (addr_hit[ 16] & (|(PINMUX_PERMIT[ 16] & ~reg_be))) | + (addr_hit[ 17] & (|(PINMUX_PERMIT[ 17] & ~reg_be))) | + (addr_hit[ 18] & (|(PINMUX_PERMIT[ 18] & ~reg_be))) | + (addr_hit[ 19] & (|(PINMUX_PERMIT[ 19] & ~reg_be))) | + (addr_hit[ 20] & (|(PINMUX_PERMIT[ 20] & ~reg_be))) | + (addr_hit[ 21] & (|(PINMUX_PERMIT[ 21] & ~reg_be))) | + (addr_hit[ 22] & (|(PINMUX_PERMIT[ 22] & ~reg_be))) | + (addr_hit[ 23] & (|(PINMUX_PERMIT[ 23] & ~reg_be))) | + (addr_hit[ 24] & (|(PINMUX_PERMIT[ 24] & ~reg_be))) | + (addr_hit[ 25] & (|(PINMUX_PERMIT[ 25] & ~reg_be))) | + (addr_hit[ 26] & (|(PINMUX_PERMIT[ 26] & ~reg_be))) | + (addr_hit[ 27] & (|(PINMUX_PERMIT[ 27] & ~reg_be))) | + (addr_hit[ 28] & (|(PINMUX_PERMIT[ 28] & ~reg_be))) | + (addr_hit[ 29] & (|(PINMUX_PERMIT[ 29] & ~reg_be))) | + (addr_hit[ 30] & (|(PINMUX_PERMIT[ 30] & ~reg_be))) | + (addr_hit[ 31] & (|(PINMUX_PERMIT[ 31] & ~reg_be))) | + (addr_hit[ 32] & (|(PINMUX_PERMIT[ 32] & ~reg_be))) | + (addr_hit[ 33] & (|(PINMUX_PERMIT[ 33] & ~reg_be))) | + (addr_hit[ 34] & (|(PINMUX_PERMIT[ 34] & ~reg_be))) | + (addr_hit[ 35] & (|(PINMUX_PERMIT[ 35] & ~reg_be))) | + (addr_hit[ 36] & (|(PINMUX_PERMIT[ 36] & ~reg_be))) | + (addr_hit[ 37] & (|(PINMUX_PERMIT[ 37] & ~reg_be))) | + (addr_hit[ 38] & (|(PINMUX_PERMIT[ 38] & ~reg_be))) | + (addr_hit[ 39] & (|(PINMUX_PERMIT[ 39] & ~reg_be))) | + (addr_hit[ 40] & (|(PINMUX_PERMIT[ 40] & ~reg_be))) | + (addr_hit[ 41] & (|(PINMUX_PERMIT[ 41] & ~reg_be))) | + (addr_hit[ 42] & (|(PINMUX_PERMIT[ 42] & ~reg_be))) | + (addr_hit[ 43] & (|(PINMUX_PERMIT[ 43] & ~reg_be))) | + (addr_hit[ 44] & (|(PINMUX_PERMIT[ 44] & ~reg_be))) | + (addr_hit[ 45] & (|(PINMUX_PERMIT[ 45] & ~reg_be))) | + (addr_hit[ 46] & (|(PINMUX_PERMIT[ 46] & ~reg_be))) | + (addr_hit[ 47] & (|(PINMUX_PERMIT[ 47] & ~reg_be))) | + (addr_hit[ 48] & (|(PINMUX_PERMIT[ 48] & ~reg_be))) | + (addr_hit[ 49] & (|(PINMUX_PERMIT[ 49] & ~reg_be))) | + (addr_hit[ 50] & (|(PINMUX_PERMIT[ 50] & ~reg_be))) | + (addr_hit[ 51] & (|(PINMUX_PERMIT[ 51] & ~reg_be))) | + (addr_hit[ 52] & (|(PINMUX_PERMIT[ 52] & ~reg_be))) | + (addr_hit[ 53] & (|(PINMUX_PERMIT[ 53] & ~reg_be))) | + (addr_hit[ 54] & (|(PINMUX_PERMIT[ 54] & ~reg_be))) | + (addr_hit[ 55] & (|(PINMUX_PERMIT[ 55] & ~reg_be))) | + (addr_hit[ 56] & (|(PINMUX_PERMIT[ 56] & ~reg_be))) | + (addr_hit[ 57] & (|(PINMUX_PERMIT[ 57] & ~reg_be))) | + (addr_hit[ 58] & (|(PINMUX_PERMIT[ 58] & ~reg_be))) | + (addr_hit[ 59] & (|(PINMUX_PERMIT[ 59] & ~reg_be))) | + (addr_hit[ 60] & (|(PINMUX_PERMIT[ 60] & ~reg_be))) | + (addr_hit[ 61] & (|(PINMUX_PERMIT[ 61] & ~reg_be))) | + (addr_hit[ 62] & (|(PINMUX_PERMIT[ 62] & ~reg_be))) | + (addr_hit[ 63] & (|(PINMUX_PERMIT[ 63] & ~reg_be))) | + (addr_hit[ 64] & (|(PINMUX_PERMIT[ 64] & ~reg_be))) | + (addr_hit[ 65] & (|(PINMUX_PERMIT[ 65] & ~reg_be))) | + (addr_hit[ 66] & (|(PINMUX_PERMIT[ 66] & ~reg_be))) | + (addr_hit[ 67] & (|(PINMUX_PERMIT[ 67] & ~reg_be))) | + (addr_hit[ 68] & (|(PINMUX_PERMIT[ 68] & ~reg_be))) | + (addr_hit[ 69] & (|(PINMUX_PERMIT[ 69] & ~reg_be))) | + (addr_hit[ 70] & (|(PINMUX_PERMIT[ 70] & ~reg_be))) | + (addr_hit[ 71] & (|(PINMUX_PERMIT[ 71] & ~reg_be))) | + (addr_hit[ 72] & (|(PINMUX_PERMIT[ 72] & ~reg_be))) | + (addr_hit[ 73] & (|(PINMUX_PERMIT[ 73] & ~reg_be))) | + (addr_hit[ 74] & (|(PINMUX_PERMIT[ 74] & ~reg_be))) | + (addr_hit[ 75] & (|(PINMUX_PERMIT[ 75] & ~reg_be))) | + (addr_hit[ 76] & (|(PINMUX_PERMIT[ 76] & ~reg_be))) | + (addr_hit[ 77] & (|(PINMUX_PERMIT[ 77] & ~reg_be))) | + (addr_hit[ 78] & (|(PINMUX_PERMIT[ 78] & ~reg_be))) | + (addr_hit[ 79] & (|(PINMUX_PERMIT[ 79] & ~reg_be))) | + (addr_hit[ 80] & (|(PINMUX_PERMIT[ 80] & ~reg_be))) | + (addr_hit[ 81] & (|(PINMUX_PERMIT[ 81] & ~reg_be))) | + (addr_hit[ 82] & (|(PINMUX_PERMIT[ 82] & ~reg_be))) | + (addr_hit[ 83] & (|(PINMUX_PERMIT[ 83] & ~reg_be))) | + (addr_hit[ 84] & (|(PINMUX_PERMIT[ 84] & ~reg_be))) | + (addr_hit[ 85] & (|(PINMUX_PERMIT[ 85] & ~reg_be))) | + (addr_hit[ 86] & (|(PINMUX_PERMIT[ 86] & ~reg_be))) | + (addr_hit[ 87] & (|(PINMUX_PERMIT[ 87] & ~reg_be))) | + (addr_hit[ 88] & (|(PINMUX_PERMIT[ 88] & ~reg_be))) | + (addr_hit[ 89] & (|(PINMUX_PERMIT[ 89] & ~reg_be))) | + (addr_hit[ 90] & (|(PINMUX_PERMIT[ 90] & ~reg_be))) | + (addr_hit[ 91] & (|(PINMUX_PERMIT[ 91] & ~reg_be))) | + (addr_hit[ 92] & (|(PINMUX_PERMIT[ 92] & ~reg_be))) | + (addr_hit[ 93] & (|(PINMUX_PERMIT[ 93] & ~reg_be))) | + (addr_hit[ 94] & (|(PINMUX_PERMIT[ 94] & ~reg_be))) | + (addr_hit[ 95] & (|(PINMUX_PERMIT[ 95] & ~reg_be))) | + (addr_hit[ 96] & (|(PINMUX_PERMIT[ 96] & ~reg_be))) | + (addr_hit[ 97] & (|(PINMUX_PERMIT[ 97] & ~reg_be))) | + (addr_hit[ 98] & (|(PINMUX_PERMIT[ 98] & ~reg_be))) | + (addr_hit[ 99] & (|(PINMUX_PERMIT[ 99] & ~reg_be))) | + (addr_hit[100] & (|(PINMUX_PERMIT[100] & ~reg_be))) | + (addr_hit[101] & (|(PINMUX_PERMIT[101] & ~reg_be))) | + (addr_hit[102] & (|(PINMUX_PERMIT[102] & ~reg_be))) | + (addr_hit[103] & (|(PINMUX_PERMIT[103] & ~reg_be))) | + (addr_hit[104] & (|(PINMUX_PERMIT[104] & ~reg_be))) | + (addr_hit[105] & (|(PINMUX_PERMIT[105] & ~reg_be))) | + (addr_hit[106] & (|(PINMUX_PERMIT[106] & ~reg_be))) | + (addr_hit[107] & (|(PINMUX_PERMIT[107] & ~reg_be))) | + (addr_hit[108] & (|(PINMUX_PERMIT[108] & ~reg_be))) | + (addr_hit[109] & (|(PINMUX_PERMIT[109] & ~reg_be))) | + (addr_hit[110] & (|(PINMUX_PERMIT[110] & ~reg_be))) | + (addr_hit[111] & (|(PINMUX_PERMIT[111] & ~reg_be))) | + (addr_hit[112] & (|(PINMUX_PERMIT[112] & ~reg_be))) | + (addr_hit[113] & (|(PINMUX_PERMIT[113] & ~reg_be))) | + (addr_hit[114] & (|(PINMUX_PERMIT[114] & ~reg_be))) | + (addr_hit[115] & (|(PINMUX_PERMIT[115] & ~reg_be))) | + (addr_hit[116] & (|(PINMUX_PERMIT[116] & ~reg_be))) | + (addr_hit[117] & (|(PINMUX_PERMIT[117] & ~reg_be))) | + (addr_hit[118] & (|(PINMUX_PERMIT[118] & ~reg_be))) | + (addr_hit[119] & (|(PINMUX_PERMIT[119] & ~reg_be))) | + (addr_hit[120] & (|(PINMUX_PERMIT[120] & ~reg_be))) | + (addr_hit[121] & (|(PINMUX_PERMIT[121] & ~reg_be))) | + (addr_hit[122] & (|(PINMUX_PERMIT[122] & ~reg_be))) | + (addr_hit[123] & (|(PINMUX_PERMIT[123] & ~reg_be))) | + (addr_hit[124] & (|(PINMUX_PERMIT[124] & ~reg_be))) | + (addr_hit[125] & (|(PINMUX_PERMIT[125] & ~reg_be))) | + (addr_hit[126] & (|(PINMUX_PERMIT[126] & ~reg_be))) | + (addr_hit[127] & (|(PINMUX_PERMIT[127] & ~reg_be))) | + (addr_hit[128] & (|(PINMUX_PERMIT[128] & ~reg_be))) | + (addr_hit[129] & (|(PINMUX_PERMIT[129] & ~reg_be))) | + (addr_hit[130] & (|(PINMUX_PERMIT[130] & ~reg_be))) | + (addr_hit[131] & (|(PINMUX_PERMIT[131] & ~reg_be))) | + (addr_hit[132] & (|(PINMUX_PERMIT[132] & ~reg_be))) | + (addr_hit[133] & (|(PINMUX_PERMIT[133] & ~reg_be))) | + (addr_hit[134] & (|(PINMUX_PERMIT[134] & ~reg_be))) | + (addr_hit[135] & (|(PINMUX_PERMIT[135] & ~reg_be))) | + (addr_hit[136] & (|(PINMUX_PERMIT[136] & ~reg_be))) | + (addr_hit[137] & (|(PINMUX_PERMIT[137] & ~reg_be))) | + (addr_hit[138] & (|(PINMUX_PERMIT[138] & ~reg_be))) | + (addr_hit[139] & (|(PINMUX_PERMIT[139] & ~reg_be))) | + (addr_hit[140] & (|(PINMUX_PERMIT[140] & ~reg_be))) | + (addr_hit[141] & (|(PINMUX_PERMIT[141] & ~reg_be))) | + (addr_hit[142] & (|(PINMUX_PERMIT[142] & ~reg_be))) | + (addr_hit[143] & (|(PINMUX_PERMIT[143] & ~reg_be))) | + (addr_hit[144] & (|(PINMUX_PERMIT[144] & ~reg_be))) | + (addr_hit[145] & (|(PINMUX_PERMIT[145] & ~reg_be))) | + (addr_hit[146] & (|(PINMUX_PERMIT[146] & ~reg_be))) | + (addr_hit[147] & (|(PINMUX_PERMIT[147] & ~reg_be))) | + (addr_hit[148] & (|(PINMUX_PERMIT[148] & ~reg_be))) | + (addr_hit[149] & (|(PINMUX_PERMIT[149] & ~reg_be))) | + (addr_hit[150] & (|(PINMUX_PERMIT[150] & ~reg_be))) | + (addr_hit[151] & (|(PINMUX_PERMIT[151] & ~reg_be))) | + (addr_hit[152] & (|(PINMUX_PERMIT[152] & ~reg_be))) | + (addr_hit[153] & (|(PINMUX_PERMIT[153] & ~reg_be))) | + (addr_hit[154] & (|(PINMUX_PERMIT[154] & ~reg_be))) | + (addr_hit[155] & (|(PINMUX_PERMIT[155] & ~reg_be))) | + (addr_hit[156] & (|(PINMUX_PERMIT[156] & ~reg_be))) | + (addr_hit[157] & (|(PINMUX_PERMIT[157] & ~reg_be))) | + (addr_hit[158] & (|(PINMUX_PERMIT[158] & ~reg_be))) | + (addr_hit[159] & (|(PINMUX_PERMIT[159] & ~reg_be))) | + (addr_hit[160] & (|(PINMUX_PERMIT[160] & ~reg_be))) | + (addr_hit[161] & (|(PINMUX_PERMIT[161] & ~reg_be))) | + (addr_hit[162] & (|(PINMUX_PERMIT[162] & ~reg_be))) | + (addr_hit[163] & (|(PINMUX_PERMIT[163] & ~reg_be))) | + (addr_hit[164] & (|(PINMUX_PERMIT[164] & ~reg_be))) | + (addr_hit[165] & (|(PINMUX_PERMIT[165] & ~reg_be))) | + (addr_hit[166] & (|(PINMUX_PERMIT[166] & ~reg_be))) | + (addr_hit[167] & (|(PINMUX_PERMIT[167] & ~reg_be))) | + (addr_hit[168] & (|(PINMUX_PERMIT[168] & ~reg_be))) | + (addr_hit[169] & (|(PINMUX_PERMIT[169] & ~reg_be))) | + (addr_hit[170] & (|(PINMUX_PERMIT[170] & ~reg_be))) | + (addr_hit[171] & (|(PINMUX_PERMIT[171] & ~reg_be))) | + (addr_hit[172] & (|(PINMUX_PERMIT[172] & ~reg_be))) | + (addr_hit[173] & (|(PINMUX_PERMIT[173] & ~reg_be))) | + (addr_hit[174] & (|(PINMUX_PERMIT[174] & ~reg_be))) | + (addr_hit[175] & (|(PINMUX_PERMIT[175] & ~reg_be))) | + (addr_hit[176] & (|(PINMUX_PERMIT[176] & ~reg_be))) | + (addr_hit[177] & (|(PINMUX_PERMIT[177] & ~reg_be))) | + (addr_hit[178] & (|(PINMUX_PERMIT[178] & ~reg_be))) | + (addr_hit[179] & (|(PINMUX_PERMIT[179] & ~reg_be))) | + (addr_hit[180] & (|(PINMUX_PERMIT[180] & ~reg_be))) | + (addr_hit[181] & (|(PINMUX_PERMIT[181] & ~reg_be))) | + (addr_hit[182] & (|(PINMUX_PERMIT[182] & ~reg_be))) | + (addr_hit[183] & (|(PINMUX_PERMIT[183] & ~reg_be))) | + (addr_hit[184] & (|(PINMUX_PERMIT[184] & ~reg_be))) | + (addr_hit[185] & (|(PINMUX_PERMIT[185] & ~reg_be))) | + (addr_hit[186] & (|(PINMUX_PERMIT[186] & ~reg_be))) | + (addr_hit[187] & (|(PINMUX_PERMIT[187] & ~reg_be))) | + (addr_hit[188] & (|(PINMUX_PERMIT[188] & ~reg_be))) | + (addr_hit[189] & (|(PINMUX_PERMIT[189] & ~reg_be))) | + (addr_hit[190] & (|(PINMUX_PERMIT[190] & ~reg_be))) | + (addr_hit[191] & (|(PINMUX_PERMIT[191] & ~reg_be))) | + (addr_hit[192] & (|(PINMUX_PERMIT[192] & ~reg_be))) | + (addr_hit[193] & (|(PINMUX_PERMIT[193] & ~reg_be))) | + (addr_hit[194] & (|(PINMUX_PERMIT[194] & ~reg_be))) | + (addr_hit[195] & (|(PINMUX_PERMIT[195] & ~reg_be))) | + (addr_hit[196] & (|(PINMUX_PERMIT[196] & ~reg_be))) | + (addr_hit[197] & (|(PINMUX_PERMIT[197] & ~reg_be))) | + (addr_hit[198] & (|(PINMUX_PERMIT[198] & ~reg_be))) | + (addr_hit[199] & (|(PINMUX_PERMIT[199] & ~reg_be))) | + (addr_hit[200] & (|(PINMUX_PERMIT[200] & ~reg_be))) | + (addr_hit[201] & (|(PINMUX_PERMIT[201] & ~reg_be))) | + (addr_hit[202] & (|(PINMUX_PERMIT[202] & ~reg_be))) | + (addr_hit[203] & (|(PINMUX_PERMIT[203] & ~reg_be))) | + (addr_hit[204] & (|(PINMUX_PERMIT[204] & ~reg_be))) | + (addr_hit[205] & (|(PINMUX_PERMIT[205] & ~reg_be))) | + (addr_hit[206] & (|(PINMUX_PERMIT[206] & ~reg_be))) | + (addr_hit[207] & (|(PINMUX_PERMIT[207] & ~reg_be))) | + (addr_hit[208] & (|(PINMUX_PERMIT[208] & ~reg_be))) | + (addr_hit[209] & (|(PINMUX_PERMIT[209] & ~reg_be))) | + (addr_hit[210] & (|(PINMUX_PERMIT[210] & ~reg_be))) | + (addr_hit[211] & (|(PINMUX_PERMIT[211] & ~reg_be))) | + (addr_hit[212] & (|(PINMUX_PERMIT[212] & ~reg_be))) | + (addr_hit[213] & (|(PINMUX_PERMIT[213] & ~reg_be))) | + (addr_hit[214] & (|(PINMUX_PERMIT[214] & ~reg_be))) | + (addr_hit[215] & (|(PINMUX_PERMIT[215] & ~reg_be))) | + (addr_hit[216] & (|(PINMUX_PERMIT[216] & ~reg_be))) | + (addr_hit[217] & (|(PINMUX_PERMIT[217] & ~reg_be))) | + (addr_hit[218] & (|(PINMUX_PERMIT[218] & ~reg_be))) | + (addr_hit[219] & (|(PINMUX_PERMIT[219] & ~reg_be))) | + (addr_hit[220] & (|(PINMUX_PERMIT[220] & ~reg_be))) | + (addr_hit[221] & (|(PINMUX_PERMIT[221] & ~reg_be))) | + (addr_hit[222] & (|(PINMUX_PERMIT[222] & ~reg_be))) | + (addr_hit[223] & (|(PINMUX_PERMIT[223] & ~reg_be))) | + (addr_hit[224] & (|(PINMUX_PERMIT[224] & ~reg_be))) | + (addr_hit[225] & (|(PINMUX_PERMIT[225] & ~reg_be))) | + (addr_hit[226] & (|(PINMUX_PERMIT[226] & ~reg_be))) | + (addr_hit[227] & (|(PINMUX_PERMIT[227] & ~reg_be))) | + (addr_hit[228] & (|(PINMUX_PERMIT[228] & ~reg_be))) | + (addr_hit[229] & (|(PINMUX_PERMIT[229] & ~reg_be))) | + (addr_hit[230] & (|(PINMUX_PERMIT[230] & ~reg_be))) | + (addr_hit[231] & (|(PINMUX_PERMIT[231] & ~reg_be))) | + (addr_hit[232] & (|(PINMUX_PERMIT[232] & ~reg_be))) | + (addr_hit[233] & (|(PINMUX_PERMIT[233] & ~reg_be))) | + (addr_hit[234] & (|(PINMUX_PERMIT[234] & ~reg_be))) | + (addr_hit[235] & (|(PINMUX_PERMIT[235] & ~reg_be))) | + (addr_hit[236] & (|(PINMUX_PERMIT[236] & ~reg_be))) | + (addr_hit[237] & (|(PINMUX_PERMIT[237] & ~reg_be))) | + (addr_hit[238] & (|(PINMUX_PERMIT[238] & ~reg_be))) | + (addr_hit[239] & (|(PINMUX_PERMIT[239] & ~reg_be))) | + (addr_hit[240] & (|(PINMUX_PERMIT[240] & ~reg_be))) | + (addr_hit[241] & (|(PINMUX_PERMIT[241] & ~reg_be))) | + (addr_hit[242] & (|(PINMUX_PERMIT[242] & ~reg_be))) | + (addr_hit[243] & (|(PINMUX_PERMIT[243] & ~reg_be))) | + (addr_hit[244] & (|(PINMUX_PERMIT[244] & ~reg_be))) | + (addr_hit[245] & (|(PINMUX_PERMIT[245] & ~reg_be))) | + (addr_hit[246] & (|(PINMUX_PERMIT[246] & ~reg_be))) | + (addr_hit[247] & (|(PINMUX_PERMIT[247] & ~reg_be))) | + (addr_hit[248] & (|(PINMUX_PERMIT[248] & ~reg_be))) | + (addr_hit[249] & (|(PINMUX_PERMIT[249] & ~reg_be))) | + (addr_hit[250] & (|(PINMUX_PERMIT[250] & ~reg_be))) | + (addr_hit[251] & (|(PINMUX_PERMIT[251] & ~reg_be))) | + (addr_hit[252] & (|(PINMUX_PERMIT[252] & ~reg_be))) | + (addr_hit[253] & (|(PINMUX_PERMIT[253] & ~reg_be))) | + (addr_hit[254] & (|(PINMUX_PERMIT[254] & ~reg_be))) | + (addr_hit[255] & (|(PINMUX_PERMIT[255] & ~reg_be))) | + (addr_hit[256] & (|(PINMUX_PERMIT[256] & ~reg_be))) | + (addr_hit[257] & (|(PINMUX_PERMIT[257] & ~reg_be))) | + (addr_hit[258] & (|(PINMUX_PERMIT[258] & ~reg_be))) | + (addr_hit[259] & (|(PINMUX_PERMIT[259] & ~reg_be))) | + (addr_hit[260] & (|(PINMUX_PERMIT[260] & ~reg_be))) | + (addr_hit[261] & (|(PINMUX_PERMIT[261] & ~reg_be))) | + (addr_hit[262] & (|(PINMUX_PERMIT[262] & ~reg_be))) | + (addr_hit[263] & (|(PINMUX_PERMIT[263] & ~reg_be))) | + (addr_hit[264] & (|(PINMUX_PERMIT[264] & ~reg_be))) | + (addr_hit[265] & (|(PINMUX_PERMIT[265] & ~reg_be))) | + (addr_hit[266] & (|(PINMUX_PERMIT[266] & ~reg_be))) | + (addr_hit[267] & (|(PINMUX_PERMIT[267] & ~reg_be))) | + (addr_hit[268] & (|(PINMUX_PERMIT[268] & ~reg_be))) | + (addr_hit[269] & (|(PINMUX_PERMIT[269] & ~reg_be))) | + (addr_hit[270] & (|(PINMUX_PERMIT[270] & ~reg_be))) | + (addr_hit[271] & (|(PINMUX_PERMIT[271] & ~reg_be))) | + (addr_hit[272] & (|(PINMUX_PERMIT[272] & ~reg_be))) | + (addr_hit[273] & (|(PINMUX_PERMIT[273] & ~reg_be))) | + (addr_hit[274] & (|(PINMUX_PERMIT[274] & ~reg_be))) | + (addr_hit[275] & (|(PINMUX_PERMIT[275] & ~reg_be))) | + (addr_hit[276] & (|(PINMUX_PERMIT[276] & ~reg_be))) | + (addr_hit[277] & (|(PINMUX_PERMIT[277] & ~reg_be))) | + (addr_hit[278] & (|(PINMUX_PERMIT[278] & ~reg_be))) | + (addr_hit[279] & (|(PINMUX_PERMIT[279] & ~reg_be))) | + (addr_hit[280] & (|(PINMUX_PERMIT[280] & ~reg_be))) | + (addr_hit[281] & (|(PINMUX_PERMIT[281] & ~reg_be))) | + (addr_hit[282] & (|(PINMUX_PERMIT[282] & ~reg_be))) | + (addr_hit[283] & (|(PINMUX_PERMIT[283] & ~reg_be))) | + (addr_hit[284] & (|(PINMUX_PERMIT[284] & ~reg_be))) | + (addr_hit[285] & (|(PINMUX_PERMIT[285] & ~reg_be))) | + (addr_hit[286] & (|(PINMUX_PERMIT[286] & ~reg_be))) | + (addr_hit[287] & (|(PINMUX_PERMIT[287] & ~reg_be))) | + (addr_hit[288] & (|(PINMUX_PERMIT[288] & ~reg_be))) | + (addr_hit[289] & (|(PINMUX_PERMIT[289] & ~reg_be))) | + (addr_hit[290] & (|(PINMUX_PERMIT[290] & ~reg_be))) | + (addr_hit[291] & (|(PINMUX_PERMIT[291] & ~reg_be))) | + (addr_hit[292] & (|(PINMUX_PERMIT[292] & ~reg_be))) | + (addr_hit[293] & (|(PINMUX_PERMIT[293] & ~reg_be))) | + (addr_hit[294] & (|(PINMUX_PERMIT[294] & ~reg_be))) | + (addr_hit[295] & (|(PINMUX_PERMIT[295] & ~reg_be))) | + (addr_hit[296] & (|(PINMUX_PERMIT[296] & ~reg_be))) | + (addr_hit[297] & (|(PINMUX_PERMIT[297] & ~reg_be))) | + (addr_hit[298] & (|(PINMUX_PERMIT[298] & ~reg_be))) | + (addr_hit[299] & (|(PINMUX_PERMIT[299] & ~reg_be))) | + (addr_hit[300] & (|(PINMUX_PERMIT[300] & ~reg_be))) | + (addr_hit[301] & (|(PINMUX_PERMIT[301] & ~reg_be))) | + (addr_hit[302] & (|(PINMUX_PERMIT[302] & ~reg_be))) | + (addr_hit[303] & (|(PINMUX_PERMIT[303] & ~reg_be))) | + (addr_hit[304] & (|(PINMUX_PERMIT[304] & ~reg_be))) | + (addr_hit[305] & (|(PINMUX_PERMIT[305] & ~reg_be))) | + (addr_hit[306] & (|(PINMUX_PERMIT[306] & ~reg_be))) | + (addr_hit[307] & (|(PINMUX_PERMIT[307] & ~reg_be))) | + (addr_hit[308] & (|(PINMUX_PERMIT[308] & ~reg_be))) | + (addr_hit[309] & (|(PINMUX_PERMIT[309] & ~reg_be))) | + (addr_hit[310] & (|(PINMUX_PERMIT[310] & ~reg_be))) | + (addr_hit[311] & (|(PINMUX_PERMIT[311] & ~reg_be))) | + (addr_hit[312] & (|(PINMUX_PERMIT[312] & ~reg_be))) | + (addr_hit[313] & (|(PINMUX_PERMIT[313] & ~reg_be))) | + (addr_hit[314] & (|(PINMUX_PERMIT[314] & ~reg_be))) | + (addr_hit[315] & (|(PINMUX_PERMIT[315] & ~reg_be))) | + (addr_hit[316] & (|(PINMUX_PERMIT[316] & ~reg_be))) | + (addr_hit[317] & (|(PINMUX_PERMIT[317] & ~reg_be))) | + (addr_hit[318] & (|(PINMUX_PERMIT[318] & ~reg_be))) | + (addr_hit[319] & (|(PINMUX_PERMIT[319] & ~reg_be))) | + (addr_hit[320] & (|(PINMUX_PERMIT[320] & ~reg_be))) | + (addr_hit[321] & (|(PINMUX_PERMIT[321] & ~reg_be))) | + (addr_hit[322] & (|(PINMUX_PERMIT[322] & ~reg_be))) | + (addr_hit[323] & (|(PINMUX_PERMIT[323] & ~reg_be))) | + (addr_hit[324] & (|(PINMUX_PERMIT[324] & ~reg_be))) | + (addr_hit[325] & (|(PINMUX_PERMIT[325] & ~reg_be))) | + (addr_hit[326] & (|(PINMUX_PERMIT[326] & ~reg_be))) | + (addr_hit[327] & (|(PINMUX_PERMIT[327] & ~reg_be))) | + (addr_hit[328] & (|(PINMUX_PERMIT[328] & ~reg_be))) | + (addr_hit[329] & (|(PINMUX_PERMIT[329] & ~reg_be))) | + (addr_hit[330] & (|(PINMUX_PERMIT[330] & ~reg_be))) | + (addr_hit[331] & (|(PINMUX_PERMIT[331] & ~reg_be))) | + (addr_hit[332] & (|(PINMUX_PERMIT[332] & ~reg_be))) | + (addr_hit[333] & (|(PINMUX_PERMIT[333] & ~reg_be))) | + (addr_hit[334] & (|(PINMUX_PERMIT[334] & ~reg_be))) | + (addr_hit[335] & (|(PINMUX_PERMIT[335] & ~reg_be))) | + (addr_hit[336] & (|(PINMUX_PERMIT[336] & ~reg_be))) | + (addr_hit[337] & (|(PINMUX_PERMIT[337] & ~reg_be))) | + (addr_hit[338] & (|(PINMUX_PERMIT[338] & ~reg_be))) | + (addr_hit[339] & (|(PINMUX_PERMIT[339] & ~reg_be))) | + (addr_hit[340] & (|(PINMUX_PERMIT[340] & ~reg_be))) | + (addr_hit[341] & (|(PINMUX_PERMIT[341] & ~reg_be))) | + (addr_hit[342] & (|(PINMUX_PERMIT[342] & ~reg_be))) | + (addr_hit[343] & (|(PINMUX_PERMIT[343] & ~reg_be))) | + (addr_hit[344] & (|(PINMUX_PERMIT[344] & ~reg_be))) | + (addr_hit[345] & (|(PINMUX_PERMIT[345] & ~reg_be))) | + (addr_hit[346] & (|(PINMUX_PERMIT[346] & ~reg_be))) | + (addr_hit[347] & (|(PINMUX_PERMIT[347] & ~reg_be))) | + (addr_hit[348] & (|(PINMUX_PERMIT[348] & ~reg_be))) | + (addr_hit[349] & (|(PINMUX_PERMIT[349] & ~reg_be))) | + (addr_hit[350] & (|(PINMUX_PERMIT[350] & ~reg_be))) | + (addr_hit[351] & (|(PINMUX_PERMIT[351] & ~reg_be))) | + (addr_hit[352] & (|(PINMUX_PERMIT[352] & ~reg_be))) | + (addr_hit[353] & (|(PINMUX_PERMIT[353] & ~reg_be))) | + (addr_hit[354] & (|(PINMUX_PERMIT[354] & ~reg_be))) | + (addr_hit[355] & (|(PINMUX_PERMIT[355] & ~reg_be))) | + (addr_hit[356] & (|(PINMUX_PERMIT[356] & ~reg_be))) | + (addr_hit[357] & (|(PINMUX_PERMIT[357] & ~reg_be))) | + (addr_hit[358] & (|(PINMUX_PERMIT[358] & ~reg_be))) | + (addr_hit[359] & (|(PINMUX_PERMIT[359] & ~reg_be))) | + (addr_hit[360] & (|(PINMUX_PERMIT[360] & ~reg_be))) | + (addr_hit[361] & (|(PINMUX_PERMIT[361] & ~reg_be))) | + (addr_hit[362] & (|(PINMUX_PERMIT[362] & ~reg_be))) | + (addr_hit[363] & (|(PINMUX_PERMIT[363] & ~reg_be))) | + (addr_hit[364] & (|(PINMUX_PERMIT[364] & ~reg_be))) | + (addr_hit[365] & (|(PINMUX_PERMIT[365] & ~reg_be))) | + (addr_hit[366] & (|(PINMUX_PERMIT[366] & ~reg_be))) | + (addr_hit[367] & (|(PINMUX_PERMIT[367] & ~reg_be))) | + (addr_hit[368] & (|(PINMUX_PERMIT[368] & ~reg_be))) | + (addr_hit[369] & (|(PINMUX_PERMIT[369] & ~reg_be))) | + (addr_hit[370] & (|(PINMUX_PERMIT[370] & ~reg_be))) | + (addr_hit[371] & (|(PINMUX_PERMIT[371] & ~reg_be))) | + (addr_hit[372] & (|(PINMUX_PERMIT[372] & ~reg_be))) | + (addr_hit[373] & (|(PINMUX_PERMIT[373] & ~reg_be))) | + (addr_hit[374] & (|(PINMUX_PERMIT[374] & ~reg_be))) | + (addr_hit[375] & (|(PINMUX_PERMIT[375] & ~reg_be))) | + (addr_hit[376] & (|(PINMUX_PERMIT[376] & ~reg_be))) | + (addr_hit[377] & (|(PINMUX_PERMIT[377] & ~reg_be))) | + (addr_hit[378] & (|(PINMUX_PERMIT[378] & ~reg_be))) | + (addr_hit[379] & (|(PINMUX_PERMIT[379] & ~reg_be))) | + (addr_hit[380] & (|(PINMUX_PERMIT[380] & ~reg_be))) | + (addr_hit[381] & (|(PINMUX_PERMIT[381] & ~reg_be))) | + (addr_hit[382] & (|(PINMUX_PERMIT[382] & ~reg_be))) | + (addr_hit[383] & (|(PINMUX_PERMIT[383] & ~reg_be))) | + (addr_hit[384] & (|(PINMUX_PERMIT[384] & ~reg_be))) | + (addr_hit[385] & (|(PINMUX_PERMIT[385] & ~reg_be))) | + (addr_hit[386] & (|(PINMUX_PERMIT[386] & ~reg_be))) | + (addr_hit[387] & (|(PINMUX_PERMIT[387] & ~reg_be))) | + (addr_hit[388] & (|(PINMUX_PERMIT[388] & ~reg_be))) | + (addr_hit[389] & (|(PINMUX_PERMIT[389] & ~reg_be))) | + (addr_hit[390] & (|(PINMUX_PERMIT[390] & ~reg_be))) | + (addr_hit[391] & (|(PINMUX_PERMIT[391] & ~reg_be))) | + (addr_hit[392] & (|(PINMUX_PERMIT[392] & ~reg_be))) | + (addr_hit[393] & (|(PINMUX_PERMIT[393] & ~reg_be))) | + (addr_hit[394] & (|(PINMUX_PERMIT[394] & ~reg_be))) | + (addr_hit[395] & (|(PINMUX_PERMIT[395] & ~reg_be))) | + (addr_hit[396] & (|(PINMUX_PERMIT[396] & ~reg_be))) | + (addr_hit[397] & (|(PINMUX_PERMIT[397] & ~reg_be))) | + (addr_hit[398] & (|(PINMUX_PERMIT[398] & ~reg_be))) | + (addr_hit[399] & (|(PINMUX_PERMIT[399] & ~reg_be))) | + (addr_hit[400] & (|(PINMUX_PERMIT[400] & ~reg_be))) | + (addr_hit[401] & (|(PINMUX_PERMIT[401] & ~reg_be))) | + (addr_hit[402] & (|(PINMUX_PERMIT[402] & ~reg_be))) | + (addr_hit[403] & (|(PINMUX_PERMIT[403] & ~reg_be))) | + (addr_hit[404] & (|(PINMUX_PERMIT[404] & ~reg_be))) | + (addr_hit[405] & (|(PINMUX_PERMIT[405] & ~reg_be))) | + (addr_hit[406] & (|(PINMUX_PERMIT[406] & ~reg_be))) | + (addr_hit[407] & (|(PINMUX_PERMIT[407] & ~reg_be))) | + (addr_hit[408] & (|(PINMUX_PERMIT[408] & ~reg_be))) | + (addr_hit[409] & (|(PINMUX_PERMIT[409] & ~reg_be))) | + (addr_hit[410] & (|(PINMUX_PERMIT[410] & ~reg_be))) | + (addr_hit[411] & (|(PINMUX_PERMIT[411] & ~reg_be))) | + (addr_hit[412] & (|(PINMUX_PERMIT[412] & ~reg_be))) | + (addr_hit[413] & (|(PINMUX_PERMIT[413] & ~reg_be))) | + (addr_hit[414] & (|(PINMUX_PERMIT[414] & ~reg_be))) | + (addr_hit[415] & (|(PINMUX_PERMIT[415] & ~reg_be))) | + (addr_hit[416] & (|(PINMUX_PERMIT[416] & ~reg_be))) | + (addr_hit[417] & (|(PINMUX_PERMIT[417] & ~reg_be))) | + (addr_hit[418] & (|(PINMUX_PERMIT[418] & ~reg_be))) | + (addr_hit[419] & (|(PINMUX_PERMIT[419] & ~reg_be))) | + (addr_hit[420] & (|(PINMUX_PERMIT[420] & ~reg_be))) | + (addr_hit[421] & (|(PINMUX_PERMIT[421] & ~reg_be))) | + (addr_hit[422] & (|(PINMUX_PERMIT[422] & ~reg_be))) | + (addr_hit[423] & (|(PINMUX_PERMIT[423] & ~reg_be))) | + (addr_hit[424] & (|(PINMUX_PERMIT[424] & ~reg_be))) | + (addr_hit[425] & (|(PINMUX_PERMIT[425] & ~reg_be))) | + (addr_hit[426] & (|(PINMUX_PERMIT[426] & ~reg_be))) | + (addr_hit[427] & (|(PINMUX_PERMIT[427] & ~reg_be))) | + (addr_hit[428] & (|(PINMUX_PERMIT[428] & ~reg_be))) | + (addr_hit[429] & (|(PINMUX_PERMIT[429] & ~reg_be))) | + (addr_hit[430] & (|(PINMUX_PERMIT[430] & ~reg_be))) | + (addr_hit[431] & (|(PINMUX_PERMIT[431] & ~reg_be))) | + (addr_hit[432] & (|(PINMUX_PERMIT[432] & ~reg_be))) | + (addr_hit[433] & (|(PINMUX_PERMIT[433] & ~reg_be))) | + (addr_hit[434] & (|(PINMUX_PERMIT[434] & ~reg_be))) | + (addr_hit[435] & (|(PINMUX_PERMIT[435] & ~reg_be))) | + (addr_hit[436] & (|(PINMUX_PERMIT[436] & ~reg_be))) | + (addr_hit[437] & (|(PINMUX_PERMIT[437] & ~reg_be))) | + (addr_hit[438] & (|(PINMUX_PERMIT[438] & ~reg_be))) | + (addr_hit[439] & (|(PINMUX_PERMIT[439] & ~reg_be))) | + (addr_hit[440] & (|(PINMUX_PERMIT[440] & ~reg_be))) | + (addr_hit[441] & (|(PINMUX_PERMIT[441] & ~reg_be))) | + (addr_hit[442] & (|(PINMUX_PERMIT[442] & ~reg_be))) | + (addr_hit[443] & (|(PINMUX_PERMIT[443] & ~reg_be))) | + (addr_hit[444] & (|(PINMUX_PERMIT[444] & ~reg_be))) | + (addr_hit[445] & (|(PINMUX_PERMIT[445] & ~reg_be))) | + (addr_hit[446] & (|(PINMUX_PERMIT[446] & ~reg_be))) | + (addr_hit[447] & (|(PINMUX_PERMIT[447] & ~reg_be))) | + (addr_hit[448] & (|(PINMUX_PERMIT[448] & ~reg_be))) | + (addr_hit[449] & (|(PINMUX_PERMIT[449] & ~reg_be))) | + (addr_hit[450] & (|(PINMUX_PERMIT[450] & ~reg_be))) | + (addr_hit[451] & (|(PINMUX_PERMIT[451] & ~reg_be))) | + (addr_hit[452] & (|(PINMUX_PERMIT[452] & ~reg_be))) | + (addr_hit[453] & (|(PINMUX_PERMIT[453] & ~reg_be))) | + (addr_hit[454] & (|(PINMUX_PERMIT[454] & ~reg_be))) | + (addr_hit[455] & (|(PINMUX_PERMIT[455] & ~reg_be))) | + (addr_hit[456] & (|(PINMUX_PERMIT[456] & ~reg_be))) | + (addr_hit[457] & (|(PINMUX_PERMIT[457] & ~reg_be))) | + (addr_hit[458] & (|(PINMUX_PERMIT[458] & ~reg_be))) | + (addr_hit[459] & (|(PINMUX_PERMIT[459] & ~reg_be))) | + (addr_hit[460] & (|(PINMUX_PERMIT[460] & ~reg_be))) | + (addr_hit[461] & (|(PINMUX_PERMIT[461] & ~reg_be))) | + (addr_hit[462] & (|(PINMUX_PERMIT[462] & ~reg_be))) | + (addr_hit[463] & (|(PINMUX_PERMIT[463] & ~reg_be))) | + (addr_hit[464] & (|(PINMUX_PERMIT[464] & ~reg_be))) | + (addr_hit[465] & (|(PINMUX_PERMIT[465] & ~reg_be))) | + (addr_hit[466] & (|(PINMUX_PERMIT[466] & ~reg_be))) | + (addr_hit[467] & (|(PINMUX_PERMIT[467] & ~reg_be))) | + (addr_hit[468] & (|(PINMUX_PERMIT[468] & ~reg_be))) | + (addr_hit[469] & (|(PINMUX_PERMIT[469] & ~reg_be))) | + (addr_hit[470] & (|(PINMUX_PERMIT[470] & ~reg_be))) | + (addr_hit[471] & (|(PINMUX_PERMIT[471] & ~reg_be))) | + (addr_hit[472] & (|(PINMUX_PERMIT[472] & ~reg_be))) | + (addr_hit[473] & (|(PINMUX_PERMIT[473] & ~reg_be))) | + (addr_hit[474] & (|(PINMUX_PERMIT[474] & ~reg_be))) | + (addr_hit[475] & (|(PINMUX_PERMIT[475] & ~reg_be))) | + (addr_hit[476] & (|(PINMUX_PERMIT[476] & ~reg_be))) | + (addr_hit[477] & (|(PINMUX_PERMIT[477] & ~reg_be))) | + (addr_hit[478] & (|(PINMUX_PERMIT[478] & ~reg_be))) | + (addr_hit[479] & (|(PINMUX_PERMIT[479] & ~reg_be))) | + (addr_hit[480] & (|(PINMUX_PERMIT[480] & ~reg_be))) | + (addr_hit[481] & (|(PINMUX_PERMIT[481] & ~reg_be))) | + (addr_hit[482] & (|(PINMUX_PERMIT[482] & ~reg_be))) | + (addr_hit[483] & (|(PINMUX_PERMIT[483] & ~reg_be))) | + (addr_hit[484] & (|(PINMUX_PERMIT[484] & ~reg_be))) | + (addr_hit[485] & (|(PINMUX_PERMIT[485] & ~reg_be))) | + (addr_hit[486] & (|(PINMUX_PERMIT[486] & ~reg_be))) | + (addr_hit[487] & (|(PINMUX_PERMIT[487] & ~reg_be))) | + (addr_hit[488] & (|(PINMUX_PERMIT[488] & ~reg_be))) | + (addr_hit[489] & (|(PINMUX_PERMIT[489] & ~reg_be))) | + (addr_hit[490] & (|(PINMUX_PERMIT[490] & ~reg_be))) | + (addr_hit[491] & (|(PINMUX_PERMIT[491] & ~reg_be))) | + (addr_hit[492] & (|(PINMUX_PERMIT[492] & ~reg_be))) | + (addr_hit[493] & (|(PINMUX_PERMIT[493] & ~reg_be))) | + (addr_hit[494] & (|(PINMUX_PERMIT[494] & ~reg_be))) | + (addr_hit[495] & (|(PINMUX_PERMIT[495] & ~reg_be))) | + (addr_hit[496] & (|(PINMUX_PERMIT[496] & ~reg_be))) | + (addr_hit[497] & (|(PINMUX_PERMIT[497] & ~reg_be))) | + (addr_hit[498] & (|(PINMUX_PERMIT[498] & ~reg_be))) | + (addr_hit[499] & (|(PINMUX_PERMIT[499] & ~reg_be))) | + (addr_hit[500] & (|(PINMUX_PERMIT[500] & ~reg_be))) | + (addr_hit[501] & (|(PINMUX_PERMIT[501] & ~reg_be))) | + (addr_hit[502] & (|(PINMUX_PERMIT[502] & ~reg_be))))); + end + + // Generate write-enables + assign alert_test_we = addr_hit[0] & reg_we & !reg_error; + + assign alert_test_wd = reg_wdata[0]; + assign mio_periph_insel_regwen_0_we = addr_hit[1] & reg_we & !reg_error; + + assign mio_periph_insel_regwen_0_wd = reg_wdata[0]; + assign mio_periph_insel_regwen_1_we = addr_hit[2] & reg_we & !reg_error; + + assign mio_periph_insel_regwen_1_wd = reg_wdata[0]; + assign mio_periph_insel_regwen_2_we = addr_hit[3] & reg_we & !reg_error; + + assign mio_periph_insel_regwen_2_wd = reg_wdata[0]; + assign mio_periph_insel_regwen_3_we = addr_hit[4] & reg_we & !reg_error; + + assign mio_periph_insel_regwen_3_wd = reg_wdata[0]; + assign mio_periph_insel_0_we = addr_hit[5] & reg_we & !reg_error; + + assign mio_periph_insel_0_wd = reg_wdata[3:0]; + assign mio_periph_insel_1_we = addr_hit[6] & reg_we & !reg_error; + + assign mio_periph_insel_1_wd = reg_wdata[3:0]; + assign mio_periph_insel_2_we = addr_hit[7] & reg_we & !reg_error; + + assign mio_periph_insel_2_wd = reg_wdata[3:0]; + assign mio_periph_insel_3_we = addr_hit[8] & reg_we & !reg_error; + + assign mio_periph_insel_3_wd = reg_wdata[3:0]; + assign mio_outsel_regwen_0_we = addr_hit[9] & reg_we & !reg_error; + + assign mio_outsel_regwen_0_wd = reg_wdata[0]; + assign mio_outsel_regwen_1_we = addr_hit[10] & reg_we & !reg_error; + + assign mio_outsel_regwen_1_wd = reg_wdata[0]; + assign mio_outsel_regwen_2_we = addr_hit[11] & reg_we & !reg_error; + + assign mio_outsel_regwen_2_wd = reg_wdata[0]; + assign mio_outsel_regwen_3_we = addr_hit[12] & reg_we & !reg_error; + + assign mio_outsel_regwen_3_wd = reg_wdata[0]; + assign mio_outsel_regwen_4_we = addr_hit[13] & reg_we & !reg_error; + + assign mio_outsel_regwen_4_wd = reg_wdata[0]; + assign mio_outsel_regwen_5_we = addr_hit[14] & reg_we & !reg_error; + + assign mio_outsel_regwen_5_wd = reg_wdata[0]; + assign mio_outsel_regwen_6_we = addr_hit[15] & reg_we & !reg_error; + + assign mio_outsel_regwen_6_wd = reg_wdata[0]; + assign mio_outsel_regwen_7_we = addr_hit[16] & reg_we & !reg_error; + + assign mio_outsel_regwen_7_wd = reg_wdata[0]; + assign mio_outsel_regwen_8_we = addr_hit[17] & reg_we & !reg_error; + + assign mio_outsel_regwen_8_wd = reg_wdata[0]; + assign mio_outsel_regwen_9_we = addr_hit[18] & reg_we & !reg_error; + + assign mio_outsel_regwen_9_wd = reg_wdata[0]; + assign mio_outsel_regwen_10_we = addr_hit[19] & reg_we & !reg_error; + + assign mio_outsel_regwen_10_wd = reg_wdata[0]; + assign mio_outsel_regwen_11_we = addr_hit[20] & reg_we & !reg_error; + + assign mio_outsel_regwen_11_wd = reg_wdata[0]; + assign mio_outsel_0_we = addr_hit[21] & reg_we & !reg_error; + + assign mio_outsel_0_wd = reg_wdata[2:0]; + assign mio_outsel_1_we = addr_hit[22] & reg_we & !reg_error; + + assign mio_outsel_1_wd = reg_wdata[2:0]; + assign mio_outsel_2_we = addr_hit[23] & reg_we & !reg_error; + + assign mio_outsel_2_wd = reg_wdata[2:0]; + assign mio_outsel_3_we = addr_hit[24] & reg_we & !reg_error; + + assign mio_outsel_3_wd = reg_wdata[2:0]; + assign mio_outsel_4_we = addr_hit[25] & reg_we & !reg_error; + + assign mio_outsel_4_wd = reg_wdata[2:0]; + assign mio_outsel_5_we = addr_hit[26] & reg_we & !reg_error; + + assign mio_outsel_5_wd = reg_wdata[2:0]; + assign mio_outsel_6_we = addr_hit[27] & reg_we & !reg_error; + + assign mio_outsel_6_wd = reg_wdata[2:0]; + assign mio_outsel_7_we = addr_hit[28] & reg_we & !reg_error; + + assign mio_outsel_7_wd = reg_wdata[2:0]; + assign mio_outsel_8_we = addr_hit[29] & reg_we & !reg_error; + + assign mio_outsel_8_wd = reg_wdata[2:0]; + assign mio_outsel_9_we = addr_hit[30] & reg_we & !reg_error; + + assign mio_outsel_9_wd = reg_wdata[2:0]; + assign mio_outsel_10_we = addr_hit[31] & reg_we & !reg_error; + + assign mio_outsel_10_wd = reg_wdata[2:0]; + assign mio_outsel_11_we = addr_hit[32] & reg_we & !reg_error; + + assign mio_outsel_11_wd = reg_wdata[2:0]; + assign mio_pad_attr_regwen_0_we = addr_hit[33] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_0_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_1_we = addr_hit[34] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_1_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_2_we = addr_hit[35] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_2_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_3_we = addr_hit[36] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_3_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_4_we = addr_hit[37] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_4_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_5_we = addr_hit[38] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_5_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_6_we = addr_hit[39] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_6_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_7_we = addr_hit[40] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_7_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_8_we = addr_hit[41] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_8_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_9_we = addr_hit[42] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_9_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_10_we = addr_hit[43] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_10_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_11_we = addr_hit[44] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_11_wd = reg_wdata[0]; + assign mio_pad_attr_0_re = addr_hit[45] & reg_re & !reg_error; + assign mio_pad_attr_0_we = addr_hit[45] & reg_we & !reg_error; + + assign mio_pad_attr_0_invert_0_wd = reg_wdata[0]; + + assign mio_pad_attr_0_virtual_od_en_0_wd = reg_wdata[1]; + + assign mio_pad_attr_0_pull_en_0_wd = reg_wdata[2]; + + assign mio_pad_attr_0_pull_select_0_wd = reg_wdata[3]; + + assign mio_pad_attr_0_keeper_en_0_wd = reg_wdata[4]; + + assign mio_pad_attr_0_schmitt_en_0_wd = reg_wdata[5]; + + assign mio_pad_attr_0_od_en_0_wd = reg_wdata[6]; + + assign mio_pad_attr_0_input_disable_0_wd = reg_wdata[7]; + + assign mio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; + + assign mio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; + assign mio_pad_attr_1_re = addr_hit[46] & reg_re & !reg_error; + assign mio_pad_attr_1_we = addr_hit[46] & reg_we & !reg_error; + + assign mio_pad_attr_1_invert_1_wd = reg_wdata[0]; + + assign mio_pad_attr_1_virtual_od_en_1_wd = reg_wdata[1]; + + assign mio_pad_attr_1_pull_en_1_wd = reg_wdata[2]; + + assign mio_pad_attr_1_pull_select_1_wd = reg_wdata[3]; + + assign mio_pad_attr_1_keeper_en_1_wd = reg_wdata[4]; + + assign mio_pad_attr_1_schmitt_en_1_wd = reg_wdata[5]; + + assign mio_pad_attr_1_od_en_1_wd = reg_wdata[6]; + + assign mio_pad_attr_1_input_disable_1_wd = reg_wdata[7]; + + assign mio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; + + assign mio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; + assign mio_pad_attr_2_re = addr_hit[47] & reg_re & !reg_error; + assign mio_pad_attr_2_we = addr_hit[47] & reg_we & !reg_error; + + assign mio_pad_attr_2_invert_2_wd = reg_wdata[0]; + + assign mio_pad_attr_2_virtual_od_en_2_wd = reg_wdata[1]; + + assign mio_pad_attr_2_pull_en_2_wd = reg_wdata[2]; + + assign mio_pad_attr_2_pull_select_2_wd = reg_wdata[3]; + + assign mio_pad_attr_2_keeper_en_2_wd = reg_wdata[4]; + + assign mio_pad_attr_2_schmitt_en_2_wd = reg_wdata[5]; + + assign mio_pad_attr_2_od_en_2_wd = reg_wdata[6]; + + assign mio_pad_attr_2_input_disable_2_wd = reg_wdata[7]; + + assign mio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; + + assign mio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; + assign mio_pad_attr_3_re = addr_hit[48] & reg_re & !reg_error; + assign mio_pad_attr_3_we = addr_hit[48] & reg_we & !reg_error; + + assign mio_pad_attr_3_invert_3_wd = reg_wdata[0]; + + assign mio_pad_attr_3_virtual_od_en_3_wd = reg_wdata[1]; + + assign mio_pad_attr_3_pull_en_3_wd = reg_wdata[2]; + + assign mio_pad_attr_3_pull_select_3_wd = reg_wdata[3]; + + assign mio_pad_attr_3_keeper_en_3_wd = reg_wdata[4]; + + assign mio_pad_attr_3_schmitt_en_3_wd = reg_wdata[5]; + + assign mio_pad_attr_3_od_en_3_wd = reg_wdata[6]; + + assign mio_pad_attr_3_input_disable_3_wd = reg_wdata[7]; + + assign mio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; + + assign mio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; + assign mio_pad_attr_4_re = addr_hit[49] & reg_re & !reg_error; + assign mio_pad_attr_4_we = addr_hit[49] & reg_we & !reg_error; + + assign mio_pad_attr_4_invert_4_wd = reg_wdata[0]; + + assign mio_pad_attr_4_virtual_od_en_4_wd = reg_wdata[1]; + + assign mio_pad_attr_4_pull_en_4_wd = reg_wdata[2]; + + assign mio_pad_attr_4_pull_select_4_wd = reg_wdata[3]; + + assign mio_pad_attr_4_keeper_en_4_wd = reg_wdata[4]; + + assign mio_pad_attr_4_schmitt_en_4_wd = reg_wdata[5]; + + assign mio_pad_attr_4_od_en_4_wd = reg_wdata[6]; + + assign mio_pad_attr_4_input_disable_4_wd = reg_wdata[7]; + + assign mio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; + + assign mio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; + assign mio_pad_attr_5_re = addr_hit[50] & reg_re & !reg_error; + assign mio_pad_attr_5_we = addr_hit[50] & reg_we & !reg_error; + + assign mio_pad_attr_5_invert_5_wd = reg_wdata[0]; + + assign mio_pad_attr_5_virtual_od_en_5_wd = reg_wdata[1]; + + assign mio_pad_attr_5_pull_en_5_wd = reg_wdata[2]; + + assign mio_pad_attr_5_pull_select_5_wd = reg_wdata[3]; + + assign mio_pad_attr_5_keeper_en_5_wd = reg_wdata[4]; + + assign mio_pad_attr_5_schmitt_en_5_wd = reg_wdata[5]; + + assign mio_pad_attr_5_od_en_5_wd = reg_wdata[6]; + + assign mio_pad_attr_5_input_disable_5_wd = reg_wdata[7]; + + assign mio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; + + assign mio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; + assign mio_pad_attr_6_re = addr_hit[51] & reg_re & !reg_error; + assign mio_pad_attr_6_we = addr_hit[51] & reg_we & !reg_error; + + assign mio_pad_attr_6_invert_6_wd = reg_wdata[0]; + + assign mio_pad_attr_6_virtual_od_en_6_wd = reg_wdata[1]; + + assign mio_pad_attr_6_pull_en_6_wd = reg_wdata[2]; + + assign mio_pad_attr_6_pull_select_6_wd = reg_wdata[3]; + + assign mio_pad_attr_6_keeper_en_6_wd = reg_wdata[4]; + + assign mio_pad_attr_6_schmitt_en_6_wd = reg_wdata[5]; + + assign mio_pad_attr_6_od_en_6_wd = reg_wdata[6]; + + assign mio_pad_attr_6_input_disable_6_wd = reg_wdata[7]; + + assign mio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; + + assign mio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; + assign mio_pad_attr_7_re = addr_hit[52] & reg_re & !reg_error; + assign mio_pad_attr_7_we = addr_hit[52] & reg_we & !reg_error; + + assign mio_pad_attr_7_invert_7_wd = reg_wdata[0]; + + assign mio_pad_attr_7_virtual_od_en_7_wd = reg_wdata[1]; + + assign mio_pad_attr_7_pull_en_7_wd = reg_wdata[2]; + + assign mio_pad_attr_7_pull_select_7_wd = reg_wdata[3]; + + assign mio_pad_attr_7_keeper_en_7_wd = reg_wdata[4]; + + assign mio_pad_attr_7_schmitt_en_7_wd = reg_wdata[5]; + + assign mio_pad_attr_7_od_en_7_wd = reg_wdata[6]; + + assign mio_pad_attr_7_input_disable_7_wd = reg_wdata[7]; + + assign mio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; + + assign mio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; + assign mio_pad_attr_8_re = addr_hit[53] & reg_re & !reg_error; + assign mio_pad_attr_8_we = addr_hit[53] & reg_we & !reg_error; + + assign mio_pad_attr_8_invert_8_wd = reg_wdata[0]; + + assign mio_pad_attr_8_virtual_od_en_8_wd = reg_wdata[1]; + + assign mio_pad_attr_8_pull_en_8_wd = reg_wdata[2]; + + assign mio_pad_attr_8_pull_select_8_wd = reg_wdata[3]; + + assign mio_pad_attr_8_keeper_en_8_wd = reg_wdata[4]; + + assign mio_pad_attr_8_schmitt_en_8_wd = reg_wdata[5]; + + assign mio_pad_attr_8_od_en_8_wd = reg_wdata[6]; + + assign mio_pad_attr_8_input_disable_8_wd = reg_wdata[7]; + + assign mio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; + + assign mio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; + assign mio_pad_attr_9_re = addr_hit[54] & reg_re & !reg_error; + assign mio_pad_attr_9_we = addr_hit[54] & reg_we & !reg_error; + + assign mio_pad_attr_9_invert_9_wd = reg_wdata[0]; + + assign mio_pad_attr_9_virtual_od_en_9_wd = reg_wdata[1]; + + assign mio_pad_attr_9_pull_en_9_wd = reg_wdata[2]; + + assign mio_pad_attr_9_pull_select_9_wd = reg_wdata[3]; + + assign mio_pad_attr_9_keeper_en_9_wd = reg_wdata[4]; + + assign mio_pad_attr_9_schmitt_en_9_wd = reg_wdata[5]; + + assign mio_pad_attr_9_od_en_9_wd = reg_wdata[6]; + + assign mio_pad_attr_9_input_disable_9_wd = reg_wdata[7]; + + assign mio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; + + assign mio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; + assign mio_pad_attr_10_re = addr_hit[55] & reg_re & !reg_error; + assign mio_pad_attr_10_we = addr_hit[55] & reg_we & !reg_error; + + assign mio_pad_attr_10_invert_10_wd = reg_wdata[0]; + + assign mio_pad_attr_10_virtual_od_en_10_wd = reg_wdata[1]; + + assign mio_pad_attr_10_pull_en_10_wd = reg_wdata[2]; + + assign mio_pad_attr_10_pull_select_10_wd = reg_wdata[3]; + + assign mio_pad_attr_10_keeper_en_10_wd = reg_wdata[4]; + + assign mio_pad_attr_10_schmitt_en_10_wd = reg_wdata[5]; + + assign mio_pad_attr_10_od_en_10_wd = reg_wdata[6]; + + assign mio_pad_attr_10_input_disable_10_wd = reg_wdata[7]; + + assign mio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; + + assign mio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; + assign mio_pad_attr_11_re = addr_hit[56] & reg_re & !reg_error; + assign mio_pad_attr_11_we = addr_hit[56] & reg_we & !reg_error; + + assign mio_pad_attr_11_invert_11_wd = reg_wdata[0]; + + assign mio_pad_attr_11_virtual_od_en_11_wd = reg_wdata[1]; + + assign mio_pad_attr_11_pull_en_11_wd = reg_wdata[2]; + + assign mio_pad_attr_11_pull_select_11_wd = reg_wdata[3]; + + assign mio_pad_attr_11_keeper_en_11_wd = reg_wdata[4]; + + assign mio_pad_attr_11_schmitt_en_11_wd = reg_wdata[5]; + + assign mio_pad_attr_11_od_en_11_wd = reg_wdata[6]; + + assign mio_pad_attr_11_input_disable_11_wd = reg_wdata[7]; + + assign mio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; + + assign mio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; + assign dio_pad_attr_regwen_0_we = addr_hit[57] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_0_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_1_we = addr_hit[58] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_1_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_2_we = addr_hit[59] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_2_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_3_we = addr_hit[60] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_3_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_4_we = addr_hit[61] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_4_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_5_we = addr_hit[62] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_5_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_6_we = addr_hit[63] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_6_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_7_we = addr_hit[64] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_7_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_8_we = addr_hit[65] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_8_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_9_we = addr_hit[66] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_9_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_10_we = addr_hit[67] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_10_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_11_we = addr_hit[68] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_11_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_12_we = addr_hit[69] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_12_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_13_we = addr_hit[70] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_13_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_14_we = addr_hit[71] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_14_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_15_we = addr_hit[72] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_15_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_16_we = addr_hit[73] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_16_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_17_we = addr_hit[74] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_17_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_18_we = addr_hit[75] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_18_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_19_we = addr_hit[76] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_19_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_20_we = addr_hit[77] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_20_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_21_we = addr_hit[78] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_21_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_22_we = addr_hit[79] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_22_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_23_we = addr_hit[80] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_23_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_24_we = addr_hit[81] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_24_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_25_we = addr_hit[82] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_25_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_26_we = addr_hit[83] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_26_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_27_we = addr_hit[84] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_27_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_28_we = addr_hit[85] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_28_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_29_we = addr_hit[86] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_29_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_30_we = addr_hit[87] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_30_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_31_we = addr_hit[88] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_31_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_32_we = addr_hit[89] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_32_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_33_we = addr_hit[90] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_33_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_34_we = addr_hit[91] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_34_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_35_we = addr_hit[92] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_35_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_36_we = addr_hit[93] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_36_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_37_we = addr_hit[94] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_37_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_38_we = addr_hit[95] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_38_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_39_we = addr_hit[96] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_39_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_40_we = addr_hit[97] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_40_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_41_we = addr_hit[98] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_41_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_42_we = addr_hit[99] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_42_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_43_we = addr_hit[100] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_43_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_44_we = addr_hit[101] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_44_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_45_we = addr_hit[102] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_45_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_46_we = addr_hit[103] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_46_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_47_we = addr_hit[104] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_47_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_48_we = addr_hit[105] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_48_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_49_we = addr_hit[106] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_49_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_50_we = addr_hit[107] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_50_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_51_we = addr_hit[108] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_51_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_52_we = addr_hit[109] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_52_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_53_we = addr_hit[110] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_53_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_54_we = addr_hit[111] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_54_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_55_we = addr_hit[112] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_55_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_56_we = addr_hit[113] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_56_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_57_we = addr_hit[114] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_57_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_58_we = addr_hit[115] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_58_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_59_we = addr_hit[116] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_59_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_60_we = addr_hit[117] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_60_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_61_we = addr_hit[118] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_61_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_62_we = addr_hit[119] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_62_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_63_we = addr_hit[120] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_63_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_64_we = addr_hit[121] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_64_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_65_we = addr_hit[122] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_65_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_66_we = addr_hit[123] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_66_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_67_we = addr_hit[124] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_67_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_68_we = addr_hit[125] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_68_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_69_we = addr_hit[126] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_69_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_70_we = addr_hit[127] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_70_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_71_we = addr_hit[128] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_71_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_72_we = addr_hit[129] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_72_wd = reg_wdata[0]; + assign dio_pad_attr_0_re = addr_hit[130] & reg_re & !reg_error; + assign dio_pad_attr_0_we = addr_hit[130] & reg_we & !reg_error; + + assign dio_pad_attr_0_invert_0_wd = reg_wdata[0]; + + assign dio_pad_attr_0_virtual_od_en_0_wd = reg_wdata[1]; + + assign dio_pad_attr_0_pull_en_0_wd = reg_wdata[2]; + + assign dio_pad_attr_0_pull_select_0_wd = reg_wdata[3]; + + assign dio_pad_attr_0_keeper_en_0_wd = reg_wdata[4]; + + assign dio_pad_attr_0_schmitt_en_0_wd = reg_wdata[5]; + + assign dio_pad_attr_0_od_en_0_wd = reg_wdata[6]; + + assign dio_pad_attr_0_input_disable_0_wd = reg_wdata[7]; + + assign dio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; + + assign dio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; + assign dio_pad_attr_1_re = addr_hit[131] & reg_re & !reg_error; + assign dio_pad_attr_1_we = addr_hit[131] & reg_we & !reg_error; + + assign dio_pad_attr_1_invert_1_wd = reg_wdata[0]; + + assign dio_pad_attr_1_virtual_od_en_1_wd = reg_wdata[1]; + + assign dio_pad_attr_1_pull_en_1_wd = reg_wdata[2]; + + assign dio_pad_attr_1_pull_select_1_wd = reg_wdata[3]; + + assign dio_pad_attr_1_keeper_en_1_wd = reg_wdata[4]; + + assign dio_pad_attr_1_schmitt_en_1_wd = reg_wdata[5]; + + assign dio_pad_attr_1_od_en_1_wd = reg_wdata[6]; + + assign dio_pad_attr_1_input_disable_1_wd = reg_wdata[7]; + + assign dio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; + + assign dio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; + assign dio_pad_attr_2_re = addr_hit[132] & reg_re & !reg_error; + assign dio_pad_attr_2_we = addr_hit[132] & reg_we & !reg_error; + + assign dio_pad_attr_2_invert_2_wd = reg_wdata[0]; + + assign dio_pad_attr_2_virtual_od_en_2_wd = reg_wdata[1]; + + assign dio_pad_attr_2_pull_en_2_wd = reg_wdata[2]; + + assign dio_pad_attr_2_pull_select_2_wd = reg_wdata[3]; + + assign dio_pad_attr_2_keeper_en_2_wd = reg_wdata[4]; + + assign dio_pad_attr_2_schmitt_en_2_wd = reg_wdata[5]; + + assign dio_pad_attr_2_od_en_2_wd = reg_wdata[6]; + + assign dio_pad_attr_2_input_disable_2_wd = reg_wdata[7]; + + assign dio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; + + assign dio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; + assign dio_pad_attr_3_re = addr_hit[133] & reg_re & !reg_error; + assign dio_pad_attr_3_we = addr_hit[133] & reg_we & !reg_error; + + assign dio_pad_attr_3_invert_3_wd = reg_wdata[0]; + + assign dio_pad_attr_3_virtual_od_en_3_wd = reg_wdata[1]; + + assign dio_pad_attr_3_pull_en_3_wd = reg_wdata[2]; + + assign dio_pad_attr_3_pull_select_3_wd = reg_wdata[3]; + + assign dio_pad_attr_3_keeper_en_3_wd = reg_wdata[4]; + + assign dio_pad_attr_3_schmitt_en_3_wd = reg_wdata[5]; + + assign dio_pad_attr_3_od_en_3_wd = reg_wdata[6]; + + assign dio_pad_attr_3_input_disable_3_wd = reg_wdata[7]; + + assign dio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; + + assign dio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; + assign dio_pad_attr_4_re = addr_hit[134] & reg_re & !reg_error; + assign dio_pad_attr_4_we = addr_hit[134] & reg_we & !reg_error; + + assign dio_pad_attr_4_invert_4_wd = reg_wdata[0]; + + assign dio_pad_attr_4_virtual_od_en_4_wd = reg_wdata[1]; + + assign dio_pad_attr_4_pull_en_4_wd = reg_wdata[2]; + + assign dio_pad_attr_4_pull_select_4_wd = reg_wdata[3]; + + assign dio_pad_attr_4_keeper_en_4_wd = reg_wdata[4]; + + assign dio_pad_attr_4_schmitt_en_4_wd = reg_wdata[5]; + + assign dio_pad_attr_4_od_en_4_wd = reg_wdata[6]; + + assign dio_pad_attr_4_input_disable_4_wd = reg_wdata[7]; + + assign dio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; + + assign dio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; + assign dio_pad_attr_5_re = addr_hit[135] & reg_re & !reg_error; + assign dio_pad_attr_5_we = addr_hit[135] & reg_we & !reg_error; + + assign dio_pad_attr_5_invert_5_wd = reg_wdata[0]; + + assign dio_pad_attr_5_virtual_od_en_5_wd = reg_wdata[1]; + + assign dio_pad_attr_5_pull_en_5_wd = reg_wdata[2]; + + assign dio_pad_attr_5_pull_select_5_wd = reg_wdata[3]; + + assign dio_pad_attr_5_keeper_en_5_wd = reg_wdata[4]; + + assign dio_pad_attr_5_schmitt_en_5_wd = reg_wdata[5]; + + assign dio_pad_attr_5_od_en_5_wd = reg_wdata[6]; + + assign dio_pad_attr_5_input_disable_5_wd = reg_wdata[7]; + + assign dio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; + + assign dio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; + assign dio_pad_attr_6_re = addr_hit[136] & reg_re & !reg_error; + assign dio_pad_attr_6_we = addr_hit[136] & reg_we & !reg_error; + + assign dio_pad_attr_6_invert_6_wd = reg_wdata[0]; + + assign dio_pad_attr_6_virtual_od_en_6_wd = reg_wdata[1]; + + assign dio_pad_attr_6_pull_en_6_wd = reg_wdata[2]; + + assign dio_pad_attr_6_pull_select_6_wd = reg_wdata[3]; + + assign dio_pad_attr_6_keeper_en_6_wd = reg_wdata[4]; + + assign dio_pad_attr_6_schmitt_en_6_wd = reg_wdata[5]; + + assign dio_pad_attr_6_od_en_6_wd = reg_wdata[6]; + + assign dio_pad_attr_6_input_disable_6_wd = reg_wdata[7]; + + assign dio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; + + assign dio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; + assign dio_pad_attr_7_re = addr_hit[137] & reg_re & !reg_error; + assign dio_pad_attr_7_we = addr_hit[137] & reg_we & !reg_error; + + assign dio_pad_attr_7_invert_7_wd = reg_wdata[0]; + + assign dio_pad_attr_7_virtual_od_en_7_wd = reg_wdata[1]; + + assign dio_pad_attr_7_pull_en_7_wd = reg_wdata[2]; + + assign dio_pad_attr_7_pull_select_7_wd = reg_wdata[3]; + + assign dio_pad_attr_7_keeper_en_7_wd = reg_wdata[4]; + + assign dio_pad_attr_7_schmitt_en_7_wd = reg_wdata[5]; + + assign dio_pad_attr_7_od_en_7_wd = reg_wdata[6]; + + assign dio_pad_attr_7_input_disable_7_wd = reg_wdata[7]; + + assign dio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; + + assign dio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; + assign dio_pad_attr_8_re = addr_hit[138] & reg_re & !reg_error; + assign dio_pad_attr_8_we = addr_hit[138] & reg_we & !reg_error; + + assign dio_pad_attr_8_invert_8_wd = reg_wdata[0]; + + assign dio_pad_attr_8_virtual_od_en_8_wd = reg_wdata[1]; + + assign dio_pad_attr_8_pull_en_8_wd = reg_wdata[2]; + + assign dio_pad_attr_8_pull_select_8_wd = reg_wdata[3]; + + assign dio_pad_attr_8_keeper_en_8_wd = reg_wdata[4]; + + assign dio_pad_attr_8_schmitt_en_8_wd = reg_wdata[5]; + + assign dio_pad_attr_8_od_en_8_wd = reg_wdata[6]; + + assign dio_pad_attr_8_input_disable_8_wd = reg_wdata[7]; + + assign dio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; + + assign dio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; + assign dio_pad_attr_9_re = addr_hit[139] & reg_re & !reg_error; + assign dio_pad_attr_9_we = addr_hit[139] & reg_we & !reg_error; + + assign dio_pad_attr_9_invert_9_wd = reg_wdata[0]; + + assign dio_pad_attr_9_virtual_od_en_9_wd = reg_wdata[1]; + + assign dio_pad_attr_9_pull_en_9_wd = reg_wdata[2]; + + assign dio_pad_attr_9_pull_select_9_wd = reg_wdata[3]; + + assign dio_pad_attr_9_keeper_en_9_wd = reg_wdata[4]; + + assign dio_pad_attr_9_schmitt_en_9_wd = reg_wdata[5]; + + assign dio_pad_attr_9_od_en_9_wd = reg_wdata[6]; + + assign dio_pad_attr_9_input_disable_9_wd = reg_wdata[7]; + + assign dio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; + + assign dio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; + assign dio_pad_attr_10_re = addr_hit[140] & reg_re & !reg_error; + assign dio_pad_attr_10_we = addr_hit[140] & reg_we & !reg_error; + + assign dio_pad_attr_10_invert_10_wd = reg_wdata[0]; + + assign dio_pad_attr_10_virtual_od_en_10_wd = reg_wdata[1]; + + assign dio_pad_attr_10_pull_en_10_wd = reg_wdata[2]; + + assign dio_pad_attr_10_pull_select_10_wd = reg_wdata[3]; + + assign dio_pad_attr_10_keeper_en_10_wd = reg_wdata[4]; + + assign dio_pad_attr_10_schmitt_en_10_wd = reg_wdata[5]; + + assign dio_pad_attr_10_od_en_10_wd = reg_wdata[6]; + + assign dio_pad_attr_10_input_disable_10_wd = reg_wdata[7]; + + assign dio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; + + assign dio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; + assign dio_pad_attr_11_re = addr_hit[141] & reg_re & !reg_error; + assign dio_pad_attr_11_we = addr_hit[141] & reg_we & !reg_error; + + assign dio_pad_attr_11_invert_11_wd = reg_wdata[0]; + + assign dio_pad_attr_11_virtual_od_en_11_wd = reg_wdata[1]; + + assign dio_pad_attr_11_pull_en_11_wd = reg_wdata[2]; + + assign dio_pad_attr_11_pull_select_11_wd = reg_wdata[3]; + + assign dio_pad_attr_11_keeper_en_11_wd = reg_wdata[4]; + + assign dio_pad_attr_11_schmitt_en_11_wd = reg_wdata[5]; + + assign dio_pad_attr_11_od_en_11_wd = reg_wdata[6]; + + assign dio_pad_attr_11_input_disable_11_wd = reg_wdata[7]; + + assign dio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; + + assign dio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; + assign dio_pad_attr_12_re = addr_hit[142] & reg_re & !reg_error; + assign dio_pad_attr_12_we = addr_hit[142] & reg_we & !reg_error; + + assign dio_pad_attr_12_invert_12_wd = reg_wdata[0]; + + assign dio_pad_attr_12_virtual_od_en_12_wd = reg_wdata[1]; + + assign dio_pad_attr_12_pull_en_12_wd = reg_wdata[2]; + + assign dio_pad_attr_12_pull_select_12_wd = reg_wdata[3]; + + assign dio_pad_attr_12_keeper_en_12_wd = reg_wdata[4]; + + assign dio_pad_attr_12_schmitt_en_12_wd = reg_wdata[5]; + + assign dio_pad_attr_12_od_en_12_wd = reg_wdata[6]; + + assign dio_pad_attr_12_input_disable_12_wd = reg_wdata[7]; + + assign dio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16]; + + assign dio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20]; + assign dio_pad_attr_13_re = addr_hit[143] & reg_re & !reg_error; + assign dio_pad_attr_13_we = addr_hit[143] & reg_we & !reg_error; + + assign dio_pad_attr_13_invert_13_wd = reg_wdata[0]; + + assign dio_pad_attr_13_virtual_od_en_13_wd = reg_wdata[1]; + + assign dio_pad_attr_13_pull_en_13_wd = reg_wdata[2]; + + assign dio_pad_attr_13_pull_select_13_wd = reg_wdata[3]; + + assign dio_pad_attr_13_keeper_en_13_wd = reg_wdata[4]; + + assign dio_pad_attr_13_schmitt_en_13_wd = reg_wdata[5]; + + assign dio_pad_attr_13_od_en_13_wd = reg_wdata[6]; + + assign dio_pad_attr_13_input_disable_13_wd = reg_wdata[7]; + + assign dio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16]; + + assign dio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20]; + assign dio_pad_attr_14_re = addr_hit[144] & reg_re & !reg_error; + assign dio_pad_attr_14_we = addr_hit[144] & reg_we & !reg_error; + + assign dio_pad_attr_14_invert_14_wd = reg_wdata[0]; + + assign dio_pad_attr_14_virtual_od_en_14_wd = reg_wdata[1]; + + assign dio_pad_attr_14_pull_en_14_wd = reg_wdata[2]; + + assign dio_pad_attr_14_pull_select_14_wd = reg_wdata[3]; + + assign dio_pad_attr_14_keeper_en_14_wd = reg_wdata[4]; + + assign dio_pad_attr_14_schmitt_en_14_wd = reg_wdata[5]; + + assign dio_pad_attr_14_od_en_14_wd = reg_wdata[6]; + + assign dio_pad_attr_14_input_disable_14_wd = reg_wdata[7]; + + assign dio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16]; + + assign dio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20]; + assign dio_pad_attr_15_re = addr_hit[145] & reg_re & !reg_error; + assign dio_pad_attr_15_we = addr_hit[145] & reg_we & !reg_error; + + assign dio_pad_attr_15_invert_15_wd = reg_wdata[0]; + + assign dio_pad_attr_15_virtual_od_en_15_wd = reg_wdata[1]; + + assign dio_pad_attr_15_pull_en_15_wd = reg_wdata[2]; + + assign dio_pad_attr_15_pull_select_15_wd = reg_wdata[3]; + + assign dio_pad_attr_15_keeper_en_15_wd = reg_wdata[4]; + + assign dio_pad_attr_15_schmitt_en_15_wd = reg_wdata[5]; + + assign dio_pad_attr_15_od_en_15_wd = reg_wdata[6]; + + assign dio_pad_attr_15_input_disable_15_wd = reg_wdata[7]; + + assign dio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16]; + + assign dio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20]; + assign dio_pad_attr_16_re = addr_hit[146] & reg_re & !reg_error; + assign dio_pad_attr_16_we = addr_hit[146] & reg_we & !reg_error; + + assign dio_pad_attr_16_invert_16_wd = reg_wdata[0]; + + assign dio_pad_attr_16_virtual_od_en_16_wd = reg_wdata[1]; + + assign dio_pad_attr_16_pull_en_16_wd = reg_wdata[2]; + + assign dio_pad_attr_16_pull_select_16_wd = reg_wdata[3]; + + assign dio_pad_attr_16_keeper_en_16_wd = reg_wdata[4]; + + assign dio_pad_attr_16_schmitt_en_16_wd = reg_wdata[5]; + + assign dio_pad_attr_16_od_en_16_wd = reg_wdata[6]; + + assign dio_pad_attr_16_input_disable_16_wd = reg_wdata[7]; + + assign dio_pad_attr_16_slew_rate_16_wd = reg_wdata[17:16]; + + assign dio_pad_attr_16_drive_strength_16_wd = reg_wdata[23:20]; + assign dio_pad_attr_17_re = addr_hit[147] & reg_re & !reg_error; + assign dio_pad_attr_17_we = addr_hit[147] & reg_we & !reg_error; + + assign dio_pad_attr_17_invert_17_wd = reg_wdata[0]; + + assign dio_pad_attr_17_virtual_od_en_17_wd = reg_wdata[1]; + + assign dio_pad_attr_17_pull_en_17_wd = reg_wdata[2]; + + assign dio_pad_attr_17_pull_select_17_wd = reg_wdata[3]; + + assign dio_pad_attr_17_keeper_en_17_wd = reg_wdata[4]; + + assign dio_pad_attr_17_schmitt_en_17_wd = reg_wdata[5]; + + assign dio_pad_attr_17_od_en_17_wd = reg_wdata[6]; + + assign dio_pad_attr_17_input_disable_17_wd = reg_wdata[7]; + + assign dio_pad_attr_17_slew_rate_17_wd = reg_wdata[17:16]; + + assign dio_pad_attr_17_drive_strength_17_wd = reg_wdata[23:20]; + assign dio_pad_attr_18_re = addr_hit[148] & reg_re & !reg_error; + assign dio_pad_attr_18_we = addr_hit[148] & reg_we & !reg_error; + + assign dio_pad_attr_18_invert_18_wd = reg_wdata[0]; + + assign dio_pad_attr_18_virtual_od_en_18_wd = reg_wdata[1]; + + assign dio_pad_attr_18_pull_en_18_wd = reg_wdata[2]; + + assign dio_pad_attr_18_pull_select_18_wd = reg_wdata[3]; + + assign dio_pad_attr_18_keeper_en_18_wd = reg_wdata[4]; + + assign dio_pad_attr_18_schmitt_en_18_wd = reg_wdata[5]; + + assign dio_pad_attr_18_od_en_18_wd = reg_wdata[6]; + + assign dio_pad_attr_18_input_disable_18_wd = reg_wdata[7]; + + assign dio_pad_attr_18_slew_rate_18_wd = reg_wdata[17:16]; + + assign dio_pad_attr_18_drive_strength_18_wd = reg_wdata[23:20]; + assign dio_pad_attr_19_re = addr_hit[149] & reg_re & !reg_error; + assign dio_pad_attr_19_we = addr_hit[149] & reg_we & !reg_error; + + assign dio_pad_attr_19_invert_19_wd = reg_wdata[0]; + + assign dio_pad_attr_19_virtual_od_en_19_wd = reg_wdata[1]; + + assign dio_pad_attr_19_pull_en_19_wd = reg_wdata[2]; + + assign dio_pad_attr_19_pull_select_19_wd = reg_wdata[3]; + + assign dio_pad_attr_19_keeper_en_19_wd = reg_wdata[4]; + + assign dio_pad_attr_19_schmitt_en_19_wd = reg_wdata[5]; + + assign dio_pad_attr_19_od_en_19_wd = reg_wdata[6]; + + assign dio_pad_attr_19_input_disable_19_wd = reg_wdata[7]; + + assign dio_pad_attr_19_slew_rate_19_wd = reg_wdata[17:16]; + + assign dio_pad_attr_19_drive_strength_19_wd = reg_wdata[23:20]; + assign dio_pad_attr_20_re = addr_hit[150] & reg_re & !reg_error; + assign dio_pad_attr_20_we = addr_hit[150] & reg_we & !reg_error; + + assign dio_pad_attr_20_invert_20_wd = reg_wdata[0]; + + assign dio_pad_attr_20_virtual_od_en_20_wd = reg_wdata[1]; + + assign dio_pad_attr_20_pull_en_20_wd = reg_wdata[2]; + + assign dio_pad_attr_20_pull_select_20_wd = reg_wdata[3]; + + assign dio_pad_attr_20_keeper_en_20_wd = reg_wdata[4]; + + assign dio_pad_attr_20_schmitt_en_20_wd = reg_wdata[5]; + + assign dio_pad_attr_20_od_en_20_wd = reg_wdata[6]; + + assign dio_pad_attr_20_input_disable_20_wd = reg_wdata[7]; + + assign dio_pad_attr_20_slew_rate_20_wd = reg_wdata[17:16]; + + assign dio_pad_attr_20_drive_strength_20_wd = reg_wdata[23:20]; + assign dio_pad_attr_21_re = addr_hit[151] & reg_re & !reg_error; + assign dio_pad_attr_21_we = addr_hit[151] & reg_we & !reg_error; + + assign dio_pad_attr_21_invert_21_wd = reg_wdata[0]; + + assign dio_pad_attr_21_virtual_od_en_21_wd = reg_wdata[1]; + + assign dio_pad_attr_21_pull_en_21_wd = reg_wdata[2]; + + assign dio_pad_attr_21_pull_select_21_wd = reg_wdata[3]; + + assign dio_pad_attr_21_keeper_en_21_wd = reg_wdata[4]; + + assign dio_pad_attr_21_schmitt_en_21_wd = reg_wdata[5]; + + assign dio_pad_attr_21_od_en_21_wd = reg_wdata[6]; + + assign dio_pad_attr_21_input_disable_21_wd = reg_wdata[7]; + + assign dio_pad_attr_21_slew_rate_21_wd = reg_wdata[17:16]; + + assign dio_pad_attr_21_drive_strength_21_wd = reg_wdata[23:20]; + assign dio_pad_attr_22_re = addr_hit[152] & reg_re & !reg_error; + assign dio_pad_attr_22_we = addr_hit[152] & reg_we & !reg_error; + + assign dio_pad_attr_22_invert_22_wd = reg_wdata[0]; + + assign dio_pad_attr_22_virtual_od_en_22_wd = reg_wdata[1]; + + assign dio_pad_attr_22_pull_en_22_wd = reg_wdata[2]; + + assign dio_pad_attr_22_pull_select_22_wd = reg_wdata[3]; + + assign dio_pad_attr_22_keeper_en_22_wd = reg_wdata[4]; + + assign dio_pad_attr_22_schmitt_en_22_wd = reg_wdata[5]; + + assign dio_pad_attr_22_od_en_22_wd = reg_wdata[6]; + + assign dio_pad_attr_22_input_disable_22_wd = reg_wdata[7]; + + assign dio_pad_attr_22_slew_rate_22_wd = reg_wdata[17:16]; + + assign dio_pad_attr_22_drive_strength_22_wd = reg_wdata[23:20]; + assign dio_pad_attr_23_re = addr_hit[153] & reg_re & !reg_error; + assign dio_pad_attr_23_we = addr_hit[153] & reg_we & !reg_error; + + assign dio_pad_attr_23_invert_23_wd = reg_wdata[0]; + + assign dio_pad_attr_23_virtual_od_en_23_wd = reg_wdata[1]; + + assign dio_pad_attr_23_pull_en_23_wd = reg_wdata[2]; + + assign dio_pad_attr_23_pull_select_23_wd = reg_wdata[3]; + + assign dio_pad_attr_23_keeper_en_23_wd = reg_wdata[4]; + + assign dio_pad_attr_23_schmitt_en_23_wd = reg_wdata[5]; + + assign dio_pad_attr_23_od_en_23_wd = reg_wdata[6]; + + assign dio_pad_attr_23_input_disable_23_wd = reg_wdata[7]; + + assign dio_pad_attr_23_slew_rate_23_wd = reg_wdata[17:16]; + + assign dio_pad_attr_23_drive_strength_23_wd = reg_wdata[23:20]; + assign dio_pad_attr_24_re = addr_hit[154] & reg_re & !reg_error; + assign dio_pad_attr_24_we = addr_hit[154] & reg_we & !reg_error; + + assign dio_pad_attr_24_invert_24_wd = reg_wdata[0]; + + assign dio_pad_attr_24_virtual_od_en_24_wd = reg_wdata[1]; + + assign dio_pad_attr_24_pull_en_24_wd = reg_wdata[2]; + + assign dio_pad_attr_24_pull_select_24_wd = reg_wdata[3]; + + assign dio_pad_attr_24_keeper_en_24_wd = reg_wdata[4]; + + assign dio_pad_attr_24_schmitt_en_24_wd = reg_wdata[5]; + + assign dio_pad_attr_24_od_en_24_wd = reg_wdata[6]; + + assign dio_pad_attr_24_input_disable_24_wd = reg_wdata[7]; + + assign dio_pad_attr_24_slew_rate_24_wd = reg_wdata[17:16]; + + assign dio_pad_attr_24_drive_strength_24_wd = reg_wdata[23:20]; + assign dio_pad_attr_25_re = addr_hit[155] & reg_re & !reg_error; + assign dio_pad_attr_25_we = addr_hit[155] & reg_we & !reg_error; + + assign dio_pad_attr_25_invert_25_wd = reg_wdata[0]; + + assign dio_pad_attr_25_virtual_od_en_25_wd = reg_wdata[1]; + + assign dio_pad_attr_25_pull_en_25_wd = reg_wdata[2]; + + assign dio_pad_attr_25_pull_select_25_wd = reg_wdata[3]; + + assign dio_pad_attr_25_keeper_en_25_wd = reg_wdata[4]; + + assign dio_pad_attr_25_schmitt_en_25_wd = reg_wdata[5]; + + assign dio_pad_attr_25_od_en_25_wd = reg_wdata[6]; + + assign dio_pad_attr_25_input_disable_25_wd = reg_wdata[7]; + + assign dio_pad_attr_25_slew_rate_25_wd = reg_wdata[17:16]; + + assign dio_pad_attr_25_drive_strength_25_wd = reg_wdata[23:20]; + assign dio_pad_attr_26_re = addr_hit[156] & reg_re & !reg_error; + assign dio_pad_attr_26_we = addr_hit[156] & reg_we & !reg_error; + + assign dio_pad_attr_26_invert_26_wd = reg_wdata[0]; + + assign dio_pad_attr_26_virtual_od_en_26_wd = reg_wdata[1]; + + assign dio_pad_attr_26_pull_en_26_wd = reg_wdata[2]; + + assign dio_pad_attr_26_pull_select_26_wd = reg_wdata[3]; + + assign dio_pad_attr_26_keeper_en_26_wd = reg_wdata[4]; + + assign dio_pad_attr_26_schmitt_en_26_wd = reg_wdata[5]; + + assign dio_pad_attr_26_od_en_26_wd = reg_wdata[6]; + + assign dio_pad_attr_26_input_disable_26_wd = reg_wdata[7]; + + assign dio_pad_attr_26_slew_rate_26_wd = reg_wdata[17:16]; + + assign dio_pad_attr_26_drive_strength_26_wd = reg_wdata[23:20]; + assign dio_pad_attr_27_re = addr_hit[157] & reg_re & !reg_error; + assign dio_pad_attr_27_we = addr_hit[157] & reg_we & !reg_error; + + assign dio_pad_attr_27_invert_27_wd = reg_wdata[0]; + + assign dio_pad_attr_27_virtual_od_en_27_wd = reg_wdata[1]; + + assign dio_pad_attr_27_pull_en_27_wd = reg_wdata[2]; + + assign dio_pad_attr_27_pull_select_27_wd = reg_wdata[3]; + + assign dio_pad_attr_27_keeper_en_27_wd = reg_wdata[4]; + + assign dio_pad_attr_27_schmitt_en_27_wd = reg_wdata[5]; + + assign dio_pad_attr_27_od_en_27_wd = reg_wdata[6]; + + assign dio_pad_attr_27_input_disable_27_wd = reg_wdata[7]; + + assign dio_pad_attr_27_slew_rate_27_wd = reg_wdata[17:16]; + + assign dio_pad_attr_27_drive_strength_27_wd = reg_wdata[23:20]; + assign dio_pad_attr_28_re = addr_hit[158] & reg_re & !reg_error; + assign dio_pad_attr_28_we = addr_hit[158] & reg_we & !reg_error; + + assign dio_pad_attr_28_invert_28_wd = reg_wdata[0]; + + assign dio_pad_attr_28_virtual_od_en_28_wd = reg_wdata[1]; + + assign dio_pad_attr_28_pull_en_28_wd = reg_wdata[2]; + + assign dio_pad_attr_28_pull_select_28_wd = reg_wdata[3]; + + assign dio_pad_attr_28_keeper_en_28_wd = reg_wdata[4]; + + assign dio_pad_attr_28_schmitt_en_28_wd = reg_wdata[5]; + + assign dio_pad_attr_28_od_en_28_wd = reg_wdata[6]; + + assign dio_pad_attr_28_input_disable_28_wd = reg_wdata[7]; + + assign dio_pad_attr_28_slew_rate_28_wd = reg_wdata[17:16]; + + assign dio_pad_attr_28_drive_strength_28_wd = reg_wdata[23:20]; + assign dio_pad_attr_29_re = addr_hit[159] & reg_re & !reg_error; + assign dio_pad_attr_29_we = addr_hit[159] & reg_we & !reg_error; + + assign dio_pad_attr_29_invert_29_wd = reg_wdata[0]; + + assign dio_pad_attr_29_virtual_od_en_29_wd = reg_wdata[1]; + + assign dio_pad_attr_29_pull_en_29_wd = reg_wdata[2]; + + assign dio_pad_attr_29_pull_select_29_wd = reg_wdata[3]; + + assign dio_pad_attr_29_keeper_en_29_wd = reg_wdata[4]; + + assign dio_pad_attr_29_schmitt_en_29_wd = reg_wdata[5]; + + assign dio_pad_attr_29_od_en_29_wd = reg_wdata[6]; + + assign dio_pad_attr_29_input_disable_29_wd = reg_wdata[7]; + + assign dio_pad_attr_29_slew_rate_29_wd = reg_wdata[17:16]; + + assign dio_pad_attr_29_drive_strength_29_wd = reg_wdata[23:20]; + assign dio_pad_attr_30_re = addr_hit[160] & reg_re & !reg_error; + assign dio_pad_attr_30_we = addr_hit[160] & reg_we & !reg_error; + + assign dio_pad_attr_30_invert_30_wd = reg_wdata[0]; + + assign dio_pad_attr_30_virtual_od_en_30_wd = reg_wdata[1]; + + assign dio_pad_attr_30_pull_en_30_wd = reg_wdata[2]; + + assign dio_pad_attr_30_pull_select_30_wd = reg_wdata[3]; + + assign dio_pad_attr_30_keeper_en_30_wd = reg_wdata[4]; + + assign dio_pad_attr_30_schmitt_en_30_wd = reg_wdata[5]; + + assign dio_pad_attr_30_od_en_30_wd = reg_wdata[6]; + + assign dio_pad_attr_30_input_disable_30_wd = reg_wdata[7]; + + assign dio_pad_attr_30_slew_rate_30_wd = reg_wdata[17:16]; + + assign dio_pad_attr_30_drive_strength_30_wd = reg_wdata[23:20]; + assign dio_pad_attr_31_re = addr_hit[161] & reg_re & !reg_error; + assign dio_pad_attr_31_we = addr_hit[161] & reg_we & !reg_error; + + assign dio_pad_attr_31_invert_31_wd = reg_wdata[0]; + + assign dio_pad_attr_31_virtual_od_en_31_wd = reg_wdata[1]; + + assign dio_pad_attr_31_pull_en_31_wd = reg_wdata[2]; + + assign dio_pad_attr_31_pull_select_31_wd = reg_wdata[3]; + + assign dio_pad_attr_31_keeper_en_31_wd = reg_wdata[4]; + + assign dio_pad_attr_31_schmitt_en_31_wd = reg_wdata[5]; + + assign dio_pad_attr_31_od_en_31_wd = reg_wdata[6]; + + assign dio_pad_attr_31_input_disable_31_wd = reg_wdata[7]; + + assign dio_pad_attr_31_slew_rate_31_wd = reg_wdata[17:16]; + + assign dio_pad_attr_31_drive_strength_31_wd = reg_wdata[23:20]; + assign dio_pad_attr_32_re = addr_hit[162] & reg_re & !reg_error; + assign dio_pad_attr_32_we = addr_hit[162] & reg_we & !reg_error; + + assign dio_pad_attr_32_invert_32_wd = reg_wdata[0]; + + assign dio_pad_attr_32_virtual_od_en_32_wd = reg_wdata[1]; + + assign dio_pad_attr_32_pull_en_32_wd = reg_wdata[2]; + + assign dio_pad_attr_32_pull_select_32_wd = reg_wdata[3]; + + assign dio_pad_attr_32_keeper_en_32_wd = reg_wdata[4]; + + assign dio_pad_attr_32_schmitt_en_32_wd = reg_wdata[5]; + + assign dio_pad_attr_32_od_en_32_wd = reg_wdata[6]; + + assign dio_pad_attr_32_input_disable_32_wd = reg_wdata[7]; + + assign dio_pad_attr_32_slew_rate_32_wd = reg_wdata[17:16]; + + assign dio_pad_attr_32_drive_strength_32_wd = reg_wdata[23:20]; + assign dio_pad_attr_33_re = addr_hit[163] & reg_re & !reg_error; + assign dio_pad_attr_33_we = addr_hit[163] & reg_we & !reg_error; + + assign dio_pad_attr_33_invert_33_wd = reg_wdata[0]; + + assign dio_pad_attr_33_virtual_od_en_33_wd = reg_wdata[1]; + + assign dio_pad_attr_33_pull_en_33_wd = reg_wdata[2]; + + assign dio_pad_attr_33_pull_select_33_wd = reg_wdata[3]; + + assign dio_pad_attr_33_keeper_en_33_wd = reg_wdata[4]; + + assign dio_pad_attr_33_schmitt_en_33_wd = reg_wdata[5]; + + assign dio_pad_attr_33_od_en_33_wd = reg_wdata[6]; + + assign dio_pad_attr_33_input_disable_33_wd = reg_wdata[7]; + + assign dio_pad_attr_33_slew_rate_33_wd = reg_wdata[17:16]; + + assign dio_pad_attr_33_drive_strength_33_wd = reg_wdata[23:20]; + assign dio_pad_attr_34_re = addr_hit[164] & reg_re & !reg_error; + assign dio_pad_attr_34_we = addr_hit[164] & reg_we & !reg_error; + + assign dio_pad_attr_34_invert_34_wd = reg_wdata[0]; + + assign dio_pad_attr_34_virtual_od_en_34_wd = reg_wdata[1]; + + assign dio_pad_attr_34_pull_en_34_wd = reg_wdata[2]; + + assign dio_pad_attr_34_pull_select_34_wd = reg_wdata[3]; + + assign dio_pad_attr_34_keeper_en_34_wd = reg_wdata[4]; + + assign dio_pad_attr_34_schmitt_en_34_wd = reg_wdata[5]; + + assign dio_pad_attr_34_od_en_34_wd = reg_wdata[6]; + + assign dio_pad_attr_34_input_disable_34_wd = reg_wdata[7]; + + assign dio_pad_attr_34_slew_rate_34_wd = reg_wdata[17:16]; + + assign dio_pad_attr_34_drive_strength_34_wd = reg_wdata[23:20]; + assign dio_pad_attr_35_re = addr_hit[165] & reg_re & !reg_error; + assign dio_pad_attr_35_we = addr_hit[165] & reg_we & !reg_error; + + assign dio_pad_attr_35_invert_35_wd = reg_wdata[0]; + + assign dio_pad_attr_35_virtual_od_en_35_wd = reg_wdata[1]; + + assign dio_pad_attr_35_pull_en_35_wd = reg_wdata[2]; + + assign dio_pad_attr_35_pull_select_35_wd = reg_wdata[3]; + + assign dio_pad_attr_35_keeper_en_35_wd = reg_wdata[4]; + + assign dio_pad_attr_35_schmitt_en_35_wd = reg_wdata[5]; + + assign dio_pad_attr_35_od_en_35_wd = reg_wdata[6]; + + assign dio_pad_attr_35_input_disable_35_wd = reg_wdata[7]; + + assign dio_pad_attr_35_slew_rate_35_wd = reg_wdata[17:16]; + + assign dio_pad_attr_35_drive_strength_35_wd = reg_wdata[23:20]; + assign dio_pad_attr_36_re = addr_hit[166] & reg_re & !reg_error; + assign dio_pad_attr_36_we = addr_hit[166] & reg_we & !reg_error; + + assign dio_pad_attr_36_invert_36_wd = reg_wdata[0]; + + assign dio_pad_attr_36_virtual_od_en_36_wd = reg_wdata[1]; + + assign dio_pad_attr_36_pull_en_36_wd = reg_wdata[2]; + + assign dio_pad_attr_36_pull_select_36_wd = reg_wdata[3]; + + assign dio_pad_attr_36_keeper_en_36_wd = reg_wdata[4]; + + assign dio_pad_attr_36_schmitt_en_36_wd = reg_wdata[5]; + + assign dio_pad_attr_36_od_en_36_wd = reg_wdata[6]; + + assign dio_pad_attr_36_input_disable_36_wd = reg_wdata[7]; + + assign dio_pad_attr_36_slew_rate_36_wd = reg_wdata[17:16]; + + assign dio_pad_attr_36_drive_strength_36_wd = reg_wdata[23:20]; + assign dio_pad_attr_37_re = addr_hit[167] & reg_re & !reg_error; + assign dio_pad_attr_37_we = addr_hit[167] & reg_we & !reg_error; + + assign dio_pad_attr_37_invert_37_wd = reg_wdata[0]; + + assign dio_pad_attr_37_virtual_od_en_37_wd = reg_wdata[1]; + + assign dio_pad_attr_37_pull_en_37_wd = reg_wdata[2]; + + assign dio_pad_attr_37_pull_select_37_wd = reg_wdata[3]; + + assign dio_pad_attr_37_keeper_en_37_wd = reg_wdata[4]; + + assign dio_pad_attr_37_schmitt_en_37_wd = reg_wdata[5]; + + assign dio_pad_attr_37_od_en_37_wd = reg_wdata[6]; + + assign dio_pad_attr_37_input_disable_37_wd = reg_wdata[7]; + + assign dio_pad_attr_37_slew_rate_37_wd = reg_wdata[17:16]; + + assign dio_pad_attr_37_drive_strength_37_wd = reg_wdata[23:20]; + assign dio_pad_attr_38_re = addr_hit[168] & reg_re & !reg_error; + assign dio_pad_attr_38_we = addr_hit[168] & reg_we & !reg_error; + + assign dio_pad_attr_38_invert_38_wd = reg_wdata[0]; + + assign dio_pad_attr_38_virtual_od_en_38_wd = reg_wdata[1]; + + assign dio_pad_attr_38_pull_en_38_wd = reg_wdata[2]; + + assign dio_pad_attr_38_pull_select_38_wd = reg_wdata[3]; + + assign dio_pad_attr_38_keeper_en_38_wd = reg_wdata[4]; + + assign dio_pad_attr_38_schmitt_en_38_wd = reg_wdata[5]; + + assign dio_pad_attr_38_od_en_38_wd = reg_wdata[6]; + + assign dio_pad_attr_38_input_disable_38_wd = reg_wdata[7]; + + assign dio_pad_attr_38_slew_rate_38_wd = reg_wdata[17:16]; + + assign dio_pad_attr_38_drive_strength_38_wd = reg_wdata[23:20]; + assign dio_pad_attr_39_re = addr_hit[169] & reg_re & !reg_error; + assign dio_pad_attr_39_we = addr_hit[169] & reg_we & !reg_error; + + assign dio_pad_attr_39_invert_39_wd = reg_wdata[0]; + + assign dio_pad_attr_39_virtual_od_en_39_wd = reg_wdata[1]; + + assign dio_pad_attr_39_pull_en_39_wd = reg_wdata[2]; + + assign dio_pad_attr_39_pull_select_39_wd = reg_wdata[3]; + + assign dio_pad_attr_39_keeper_en_39_wd = reg_wdata[4]; + + assign dio_pad_attr_39_schmitt_en_39_wd = reg_wdata[5]; + + assign dio_pad_attr_39_od_en_39_wd = reg_wdata[6]; + + assign dio_pad_attr_39_input_disable_39_wd = reg_wdata[7]; + + assign dio_pad_attr_39_slew_rate_39_wd = reg_wdata[17:16]; + + assign dio_pad_attr_39_drive_strength_39_wd = reg_wdata[23:20]; + assign dio_pad_attr_40_re = addr_hit[170] & reg_re & !reg_error; + assign dio_pad_attr_40_we = addr_hit[170] & reg_we & !reg_error; + + assign dio_pad_attr_40_invert_40_wd = reg_wdata[0]; + + assign dio_pad_attr_40_virtual_od_en_40_wd = reg_wdata[1]; + + assign dio_pad_attr_40_pull_en_40_wd = reg_wdata[2]; + + assign dio_pad_attr_40_pull_select_40_wd = reg_wdata[3]; + + assign dio_pad_attr_40_keeper_en_40_wd = reg_wdata[4]; + + assign dio_pad_attr_40_schmitt_en_40_wd = reg_wdata[5]; + + assign dio_pad_attr_40_od_en_40_wd = reg_wdata[6]; + + assign dio_pad_attr_40_input_disable_40_wd = reg_wdata[7]; + + assign dio_pad_attr_40_slew_rate_40_wd = reg_wdata[17:16]; + + assign dio_pad_attr_40_drive_strength_40_wd = reg_wdata[23:20]; + assign dio_pad_attr_41_re = addr_hit[171] & reg_re & !reg_error; + assign dio_pad_attr_41_we = addr_hit[171] & reg_we & !reg_error; + + assign dio_pad_attr_41_invert_41_wd = reg_wdata[0]; + + assign dio_pad_attr_41_virtual_od_en_41_wd = reg_wdata[1]; + + assign dio_pad_attr_41_pull_en_41_wd = reg_wdata[2]; + + assign dio_pad_attr_41_pull_select_41_wd = reg_wdata[3]; + + assign dio_pad_attr_41_keeper_en_41_wd = reg_wdata[4]; + + assign dio_pad_attr_41_schmitt_en_41_wd = reg_wdata[5]; + + assign dio_pad_attr_41_od_en_41_wd = reg_wdata[6]; + + assign dio_pad_attr_41_input_disable_41_wd = reg_wdata[7]; + + assign dio_pad_attr_41_slew_rate_41_wd = reg_wdata[17:16]; + + assign dio_pad_attr_41_drive_strength_41_wd = reg_wdata[23:20]; + assign dio_pad_attr_42_re = addr_hit[172] & reg_re & !reg_error; + assign dio_pad_attr_42_we = addr_hit[172] & reg_we & !reg_error; + + assign dio_pad_attr_42_invert_42_wd = reg_wdata[0]; + + assign dio_pad_attr_42_virtual_od_en_42_wd = reg_wdata[1]; + + assign dio_pad_attr_42_pull_en_42_wd = reg_wdata[2]; + + assign dio_pad_attr_42_pull_select_42_wd = reg_wdata[3]; + + assign dio_pad_attr_42_keeper_en_42_wd = reg_wdata[4]; + + assign dio_pad_attr_42_schmitt_en_42_wd = reg_wdata[5]; + + assign dio_pad_attr_42_od_en_42_wd = reg_wdata[6]; + + assign dio_pad_attr_42_input_disable_42_wd = reg_wdata[7]; + + assign dio_pad_attr_42_slew_rate_42_wd = reg_wdata[17:16]; + + assign dio_pad_attr_42_drive_strength_42_wd = reg_wdata[23:20]; + assign dio_pad_attr_43_re = addr_hit[173] & reg_re & !reg_error; + assign dio_pad_attr_43_we = addr_hit[173] & reg_we & !reg_error; + + assign dio_pad_attr_43_invert_43_wd = reg_wdata[0]; + + assign dio_pad_attr_43_virtual_od_en_43_wd = reg_wdata[1]; + + assign dio_pad_attr_43_pull_en_43_wd = reg_wdata[2]; + + assign dio_pad_attr_43_pull_select_43_wd = reg_wdata[3]; + + assign dio_pad_attr_43_keeper_en_43_wd = reg_wdata[4]; + + assign dio_pad_attr_43_schmitt_en_43_wd = reg_wdata[5]; + + assign dio_pad_attr_43_od_en_43_wd = reg_wdata[6]; + + assign dio_pad_attr_43_input_disable_43_wd = reg_wdata[7]; + + assign dio_pad_attr_43_slew_rate_43_wd = reg_wdata[17:16]; + + assign dio_pad_attr_43_drive_strength_43_wd = reg_wdata[23:20]; + assign dio_pad_attr_44_re = addr_hit[174] & reg_re & !reg_error; + assign dio_pad_attr_44_we = addr_hit[174] & reg_we & !reg_error; + + assign dio_pad_attr_44_invert_44_wd = reg_wdata[0]; + + assign dio_pad_attr_44_virtual_od_en_44_wd = reg_wdata[1]; + + assign dio_pad_attr_44_pull_en_44_wd = reg_wdata[2]; + + assign dio_pad_attr_44_pull_select_44_wd = reg_wdata[3]; + + assign dio_pad_attr_44_keeper_en_44_wd = reg_wdata[4]; + + assign dio_pad_attr_44_schmitt_en_44_wd = reg_wdata[5]; + + assign dio_pad_attr_44_od_en_44_wd = reg_wdata[6]; + + assign dio_pad_attr_44_input_disable_44_wd = reg_wdata[7]; + + assign dio_pad_attr_44_slew_rate_44_wd = reg_wdata[17:16]; + + assign dio_pad_attr_44_drive_strength_44_wd = reg_wdata[23:20]; + assign dio_pad_attr_45_re = addr_hit[175] & reg_re & !reg_error; + assign dio_pad_attr_45_we = addr_hit[175] & reg_we & !reg_error; + + assign dio_pad_attr_45_invert_45_wd = reg_wdata[0]; + + assign dio_pad_attr_45_virtual_od_en_45_wd = reg_wdata[1]; + + assign dio_pad_attr_45_pull_en_45_wd = reg_wdata[2]; + + assign dio_pad_attr_45_pull_select_45_wd = reg_wdata[3]; + + assign dio_pad_attr_45_keeper_en_45_wd = reg_wdata[4]; + + assign dio_pad_attr_45_schmitt_en_45_wd = reg_wdata[5]; + + assign dio_pad_attr_45_od_en_45_wd = reg_wdata[6]; + + assign dio_pad_attr_45_input_disable_45_wd = reg_wdata[7]; + + assign dio_pad_attr_45_slew_rate_45_wd = reg_wdata[17:16]; + + assign dio_pad_attr_45_drive_strength_45_wd = reg_wdata[23:20]; + assign dio_pad_attr_46_re = addr_hit[176] & reg_re & !reg_error; + assign dio_pad_attr_46_we = addr_hit[176] & reg_we & !reg_error; + + assign dio_pad_attr_46_invert_46_wd = reg_wdata[0]; + + assign dio_pad_attr_46_virtual_od_en_46_wd = reg_wdata[1]; + + assign dio_pad_attr_46_pull_en_46_wd = reg_wdata[2]; + + assign dio_pad_attr_46_pull_select_46_wd = reg_wdata[3]; + + assign dio_pad_attr_46_keeper_en_46_wd = reg_wdata[4]; + + assign dio_pad_attr_46_schmitt_en_46_wd = reg_wdata[5]; + + assign dio_pad_attr_46_od_en_46_wd = reg_wdata[6]; + + assign dio_pad_attr_46_input_disable_46_wd = reg_wdata[7]; + + assign dio_pad_attr_46_slew_rate_46_wd = reg_wdata[17:16]; + + assign dio_pad_attr_46_drive_strength_46_wd = reg_wdata[23:20]; + assign dio_pad_attr_47_re = addr_hit[177] & reg_re & !reg_error; + assign dio_pad_attr_47_we = addr_hit[177] & reg_we & !reg_error; + + assign dio_pad_attr_47_invert_47_wd = reg_wdata[0]; + + assign dio_pad_attr_47_virtual_od_en_47_wd = reg_wdata[1]; + + assign dio_pad_attr_47_pull_en_47_wd = reg_wdata[2]; + + assign dio_pad_attr_47_pull_select_47_wd = reg_wdata[3]; + + assign dio_pad_attr_47_keeper_en_47_wd = reg_wdata[4]; + + assign dio_pad_attr_47_schmitt_en_47_wd = reg_wdata[5]; + + assign dio_pad_attr_47_od_en_47_wd = reg_wdata[6]; + + assign dio_pad_attr_47_input_disable_47_wd = reg_wdata[7]; + + assign dio_pad_attr_47_slew_rate_47_wd = reg_wdata[17:16]; + + assign dio_pad_attr_47_drive_strength_47_wd = reg_wdata[23:20]; + assign dio_pad_attr_48_re = addr_hit[178] & reg_re & !reg_error; + assign dio_pad_attr_48_we = addr_hit[178] & reg_we & !reg_error; + + assign dio_pad_attr_48_invert_48_wd = reg_wdata[0]; + + assign dio_pad_attr_48_virtual_od_en_48_wd = reg_wdata[1]; + + assign dio_pad_attr_48_pull_en_48_wd = reg_wdata[2]; + + assign dio_pad_attr_48_pull_select_48_wd = reg_wdata[3]; + + assign dio_pad_attr_48_keeper_en_48_wd = reg_wdata[4]; + + assign dio_pad_attr_48_schmitt_en_48_wd = reg_wdata[5]; + + assign dio_pad_attr_48_od_en_48_wd = reg_wdata[6]; + + assign dio_pad_attr_48_input_disable_48_wd = reg_wdata[7]; + + assign dio_pad_attr_48_slew_rate_48_wd = reg_wdata[17:16]; + + assign dio_pad_attr_48_drive_strength_48_wd = reg_wdata[23:20]; + assign dio_pad_attr_49_re = addr_hit[179] & reg_re & !reg_error; + assign dio_pad_attr_49_we = addr_hit[179] & reg_we & !reg_error; + + assign dio_pad_attr_49_invert_49_wd = reg_wdata[0]; + + assign dio_pad_attr_49_virtual_od_en_49_wd = reg_wdata[1]; + + assign dio_pad_attr_49_pull_en_49_wd = reg_wdata[2]; + + assign dio_pad_attr_49_pull_select_49_wd = reg_wdata[3]; + + assign dio_pad_attr_49_keeper_en_49_wd = reg_wdata[4]; + + assign dio_pad_attr_49_schmitt_en_49_wd = reg_wdata[5]; + + assign dio_pad_attr_49_od_en_49_wd = reg_wdata[6]; + + assign dio_pad_attr_49_input_disable_49_wd = reg_wdata[7]; + + assign dio_pad_attr_49_slew_rate_49_wd = reg_wdata[17:16]; + + assign dio_pad_attr_49_drive_strength_49_wd = reg_wdata[23:20]; + assign dio_pad_attr_50_re = addr_hit[180] & reg_re & !reg_error; + assign dio_pad_attr_50_we = addr_hit[180] & reg_we & !reg_error; + + assign dio_pad_attr_50_invert_50_wd = reg_wdata[0]; + + assign dio_pad_attr_50_virtual_od_en_50_wd = reg_wdata[1]; + + assign dio_pad_attr_50_pull_en_50_wd = reg_wdata[2]; + + assign dio_pad_attr_50_pull_select_50_wd = reg_wdata[3]; + + assign dio_pad_attr_50_keeper_en_50_wd = reg_wdata[4]; + + assign dio_pad_attr_50_schmitt_en_50_wd = reg_wdata[5]; + + assign dio_pad_attr_50_od_en_50_wd = reg_wdata[6]; + + assign dio_pad_attr_50_input_disable_50_wd = reg_wdata[7]; + + assign dio_pad_attr_50_slew_rate_50_wd = reg_wdata[17:16]; + + assign dio_pad_attr_50_drive_strength_50_wd = reg_wdata[23:20]; + assign dio_pad_attr_51_re = addr_hit[181] & reg_re & !reg_error; + assign dio_pad_attr_51_we = addr_hit[181] & reg_we & !reg_error; + + assign dio_pad_attr_51_invert_51_wd = reg_wdata[0]; + + assign dio_pad_attr_51_virtual_od_en_51_wd = reg_wdata[1]; + + assign dio_pad_attr_51_pull_en_51_wd = reg_wdata[2]; + + assign dio_pad_attr_51_pull_select_51_wd = reg_wdata[3]; + + assign dio_pad_attr_51_keeper_en_51_wd = reg_wdata[4]; + + assign dio_pad_attr_51_schmitt_en_51_wd = reg_wdata[5]; + + assign dio_pad_attr_51_od_en_51_wd = reg_wdata[6]; + + assign dio_pad_attr_51_input_disable_51_wd = reg_wdata[7]; + + assign dio_pad_attr_51_slew_rate_51_wd = reg_wdata[17:16]; + + assign dio_pad_attr_51_drive_strength_51_wd = reg_wdata[23:20]; + assign dio_pad_attr_52_re = addr_hit[182] & reg_re & !reg_error; + assign dio_pad_attr_52_we = addr_hit[182] & reg_we & !reg_error; + + assign dio_pad_attr_52_invert_52_wd = reg_wdata[0]; + + assign dio_pad_attr_52_virtual_od_en_52_wd = reg_wdata[1]; + + assign dio_pad_attr_52_pull_en_52_wd = reg_wdata[2]; + + assign dio_pad_attr_52_pull_select_52_wd = reg_wdata[3]; + + assign dio_pad_attr_52_keeper_en_52_wd = reg_wdata[4]; + + assign dio_pad_attr_52_schmitt_en_52_wd = reg_wdata[5]; + + assign dio_pad_attr_52_od_en_52_wd = reg_wdata[6]; + + assign dio_pad_attr_52_input_disable_52_wd = reg_wdata[7]; + + assign dio_pad_attr_52_slew_rate_52_wd = reg_wdata[17:16]; + + assign dio_pad_attr_52_drive_strength_52_wd = reg_wdata[23:20]; + assign dio_pad_attr_53_re = addr_hit[183] & reg_re & !reg_error; + assign dio_pad_attr_53_we = addr_hit[183] & reg_we & !reg_error; + + assign dio_pad_attr_53_invert_53_wd = reg_wdata[0]; + + assign dio_pad_attr_53_virtual_od_en_53_wd = reg_wdata[1]; + + assign dio_pad_attr_53_pull_en_53_wd = reg_wdata[2]; + + assign dio_pad_attr_53_pull_select_53_wd = reg_wdata[3]; + + assign dio_pad_attr_53_keeper_en_53_wd = reg_wdata[4]; + + assign dio_pad_attr_53_schmitt_en_53_wd = reg_wdata[5]; + + assign dio_pad_attr_53_od_en_53_wd = reg_wdata[6]; + + assign dio_pad_attr_53_input_disable_53_wd = reg_wdata[7]; + + assign dio_pad_attr_53_slew_rate_53_wd = reg_wdata[17:16]; + + assign dio_pad_attr_53_drive_strength_53_wd = reg_wdata[23:20]; + assign dio_pad_attr_54_re = addr_hit[184] & reg_re & !reg_error; + assign dio_pad_attr_54_we = addr_hit[184] & reg_we & !reg_error; + + assign dio_pad_attr_54_invert_54_wd = reg_wdata[0]; + + assign dio_pad_attr_54_virtual_od_en_54_wd = reg_wdata[1]; + + assign dio_pad_attr_54_pull_en_54_wd = reg_wdata[2]; + + assign dio_pad_attr_54_pull_select_54_wd = reg_wdata[3]; + + assign dio_pad_attr_54_keeper_en_54_wd = reg_wdata[4]; + + assign dio_pad_attr_54_schmitt_en_54_wd = reg_wdata[5]; + + assign dio_pad_attr_54_od_en_54_wd = reg_wdata[6]; + + assign dio_pad_attr_54_input_disable_54_wd = reg_wdata[7]; + + assign dio_pad_attr_54_slew_rate_54_wd = reg_wdata[17:16]; + + assign dio_pad_attr_54_drive_strength_54_wd = reg_wdata[23:20]; + assign dio_pad_attr_55_re = addr_hit[185] & reg_re & !reg_error; + assign dio_pad_attr_55_we = addr_hit[185] & reg_we & !reg_error; + + assign dio_pad_attr_55_invert_55_wd = reg_wdata[0]; + + assign dio_pad_attr_55_virtual_od_en_55_wd = reg_wdata[1]; + + assign dio_pad_attr_55_pull_en_55_wd = reg_wdata[2]; + + assign dio_pad_attr_55_pull_select_55_wd = reg_wdata[3]; + + assign dio_pad_attr_55_keeper_en_55_wd = reg_wdata[4]; + + assign dio_pad_attr_55_schmitt_en_55_wd = reg_wdata[5]; + + assign dio_pad_attr_55_od_en_55_wd = reg_wdata[6]; + + assign dio_pad_attr_55_input_disable_55_wd = reg_wdata[7]; + + assign dio_pad_attr_55_slew_rate_55_wd = reg_wdata[17:16]; + + assign dio_pad_attr_55_drive_strength_55_wd = reg_wdata[23:20]; + assign dio_pad_attr_56_re = addr_hit[186] & reg_re & !reg_error; + assign dio_pad_attr_56_we = addr_hit[186] & reg_we & !reg_error; + + assign dio_pad_attr_56_invert_56_wd = reg_wdata[0]; + + assign dio_pad_attr_56_virtual_od_en_56_wd = reg_wdata[1]; + + assign dio_pad_attr_56_pull_en_56_wd = reg_wdata[2]; + + assign dio_pad_attr_56_pull_select_56_wd = reg_wdata[3]; + + assign dio_pad_attr_56_keeper_en_56_wd = reg_wdata[4]; + + assign dio_pad_attr_56_schmitt_en_56_wd = reg_wdata[5]; + + assign dio_pad_attr_56_od_en_56_wd = reg_wdata[6]; + + assign dio_pad_attr_56_input_disable_56_wd = reg_wdata[7]; + + assign dio_pad_attr_56_slew_rate_56_wd = reg_wdata[17:16]; + + assign dio_pad_attr_56_drive_strength_56_wd = reg_wdata[23:20]; + assign dio_pad_attr_57_re = addr_hit[187] & reg_re & !reg_error; + assign dio_pad_attr_57_we = addr_hit[187] & reg_we & !reg_error; + + assign dio_pad_attr_57_invert_57_wd = reg_wdata[0]; + + assign dio_pad_attr_57_virtual_od_en_57_wd = reg_wdata[1]; + + assign dio_pad_attr_57_pull_en_57_wd = reg_wdata[2]; + + assign dio_pad_attr_57_pull_select_57_wd = reg_wdata[3]; + + assign dio_pad_attr_57_keeper_en_57_wd = reg_wdata[4]; + + assign dio_pad_attr_57_schmitt_en_57_wd = reg_wdata[5]; + + assign dio_pad_attr_57_od_en_57_wd = reg_wdata[6]; + + assign dio_pad_attr_57_input_disable_57_wd = reg_wdata[7]; + + assign dio_pad_attr_57_slew_rate_57_wd = reg_wdata[17:16]; + + assign dio_pad_attr_57_drive_strength_57_wd = reg_wdata[23:20]; + assign dio_pad_attr_58_re = addr_hit[188] & reg_re & !reg_error; + assign dio_pad_attr_58_we = addr_hit[188] & reg_we & !reg_error; + + assign dio_pad_attr_58_invert_58_wd = reg_wdata[0]; + + assign dio_pad_attr_58_virtual_od_en_58_wd = reg_wdata[1]; + + assign dio_pad_attr_58_pull_en_58_wd = reg_wdata[2]; + + assign dio_pad_attr_58_pull_select_58_wd = reg_wdata[3]; + + assign dio_pad_attr_58_keeper_en_58_wd = reg_wdata[4]; + + assign dio_pad_attr_58_schmitt_en_58_wd = reg_wdata[5]; + + assign dio_pad_attr_58_od_en_58_wd = reg_wdata[6]; + + assign dio_pad_attr_58_input_disable_58_wd = reg_wdata[7]; + + assign dio_pad_attr_58_slew_rate_58_wd = reg_wdata[17:16]; + + assign dio_pad_attr_58_drive_strength_58_wd = reg_wdata[23:20]; + assign dio_pad_attr_59_re = addr_hit[189] & reg_re & !reg_error; + assign dio_pad_attr_59_we = addr_hit[189] & reg_we & !reg_error; + + assign dio_pad_attr_59_invert_59_wd = reg_wdata[0]; + + assign dio_pad_attr_59_virtual_od_en_59_wd = reg_wdata[1]; + + assign dio_pad_attr_59_pull_en_59_wd = reg_wdata[2]; + + assign dio_pad_attr_59_pull_select_59_wd = reg_wdata[3]; + + assign dio_pad_attr_59_keeper_en_59_wd = reg_wdata[4]; + + assign dio_pad_attr_59_schmitt_en_59_wd = reg_wdata[5]; + + assign dio_pad_attr_59_od_en_59_wd = reg_wdata[6]; + + assign dio_pad_attr_59_input_disable_59_wd = reg_wdata[7]; + + assign dio_pad_attr_59_slew_rate_59_wd = reg_wdata[17:16]; + + assign dio_pad_attr_59_drive_strength_59_wd = reg_wdata[23:20]; + assign dio_pad_attr_60_re = addr_hit[190] & reg_re & !reg_error; + assign dio_pad_attr_60_we = addr_hit[190] & reg_we & !reg_error; + + assign dio_pad_attr_60_invert_60_wd = reg_wdata[0]; + + assign dio_pad_attr_60_virtual_od_en_60_wd = reg_wdata[1]; + + assign dio_pad_attr_60_pull_en_60_wd = reg_wdata[2]; + + assign dio_pad_attr_60_pull_select_60_wd = reg_wdata[3]; + + assign dio_pad_attr_60_keeper_en_60_wd = reg_wdata[4]; + + assign dio_pad_attr_60_schmitt_en_60_wd = reg_wdata[5]; + + assign dio_pad_attr_60_od_en_60_wd = reg_wdata[6]; + + assign dio_pad_attr_60_input_disable_60_wd = reg_wdata[7]; + + assign dio_pad_attr_60_slew_rate_60_wd = reg_wdata[17:16]; + + assign dio_pad_attr_60_drive_strength_60_wd = reg_wdata[23:20]; + assign dio_pad_attr_61_re = addr_hit[191] & reg_re & !reg_error; + assign dio_pad_attr_61_we = addr_hit[191] & reg_we & !reg_error; + + assign dio_pad_attr_61_invert_61_wd = reg_wdata[0]; + + assign dio_pad_attr_61_virtual_od_en_61_wd = reg_wdata[1]; + + assign dio_pad_attr_61_pull_en_61_wd = reg_wdata[2]; + + assign dio_pad_attr_61_pull_select_61_wd = reg_wdata[3]; + + assign dio_pad_attr_61_keeper_en_61_wd = reg_wdata[4]; + + assign dio_pad_attr_61_schmitt_en_61_wd = reg_wdata[5]; + + assign dio_pad_attr_61_od_en_61_wd = reg_wdata[6]; + + assign dio_pad_attr_61_input_disable_61_wd = reg_wdata[7]; + + assign dio_pad_attr_61_slew_rate_61_wd = reg_wdata[17:16]; + + assign dio_pad_attr_61_drive_strength_61_wd = reg_wdata[23:20]; + assign dio_pad_attr_62_re = addr_hit[192] & reg_re & !reg_error; + assign dio_pad_attr_62_we = addr_hit[192] & reg_we & !reg_error; + + assign dio_pad_attr_62_invert_62_wd = reg_wdata[0]; + + assign dio_pad_attr_62_virtual_od_en_62_wd = reg_wdata[1]; + + assign dio_pad_attr_62_pull_en_62_wd = reg_wdata[2]; + + assign dio_pad_attr_62_pull_select_62_wd = reg_wdata[3]; + + assign dio_pad_attr_62_keeper_en_62_wd = reg_wdata[4]; + + assign dio_pad_attr_62_schmitt_en_62_wd = reg_wdata[5]; + + assign dio_pad_attr_62_od_en_62_wd = reg_wdata[6]; + + assign dio_pad_attr_62_input_disable_62_wd = reg_wdata[7]; + + assign dio_pad_attr_62_slew_rate_62_wd = reg_wdata[17:16]; + + assign dio_pad_attr_62_drive_strength_62_wd = reg_wdata[23:20]; + assign dio_pad_attr_63_re = addr_hit[193] & reg_re & !reg_error; + assign dio_pad_attr_63_we = addr_hit[193] & reg_we & !reg_error; + + assign dio_pad_attr_63_invert_63_wd = reg_wdata[0]; + + assign dio_pad_attr_63_virtual_od_en_63_wd = reg_wdata[1]; + + assign dio_pad_attr_63_pull_en_63_wd = reg_wdata[2]; + + assign dio_pad_attr_63_pull_select_63_wd = reg_wdata[3]; + + assign dio_pad_attr_63_keeper_en_63_wd = reg_wdata[4]; + + assign dio_pad_attr_63_schmitt_en_63_wd = reg_wdata[5]; + + assign dio_pad_attr_63_od_en_63_wd = reg_wdata[6]; + + assign dio_pad_attr_63_input_disable_63_wd = reg_wdata[7]; + + assign dio_pad_attr_63_slew_rate_63_wd = reg_wdata[17:16]; + + assign dio_pad_attr_63_drive_strength_63_wd = reg_wdata[23:20]; + assign dio_pad_attr_64_re = addr_hit[194] & reg_re & !reg_error; + assign dio_pad_attr_64_we = addr_hit[194] & reg_we & !reg_error; + + assign dio_pad_attr_64_invert_64_wd = reg_wdata[0]; + + assign dio_pad_attr_64_virtual_od_en_64_wd = reg_wdata[1]; + + assign dio_pad_attr_64_pull_en_64_wd = reg_wdata[2]; + + assign dio_pad_attr_64_pull_select_64_wd = reg_wdata[3]; + + assign dio_pad_attr_64_keeper_en_64_wd = reg_wdata[4]; + + assign dio_pad_attr_64_schmitt_en_64_wd = reg_wdata[5]; + + assign dio_pad_attr_64_od_en_64_wd = reg_wdata[6]; + + assign dio_pad_attr_64_input_disable_64_wd = reg_wdata[7]; + + assign dio_pad_attr_64_slew_rate_64_wd = reg_wdata[17:16]; + + assign dio_pad_attr_64_drive_strength_64_wd = reg_wdata[23:20]; + assign dio_pad_attr_65_re = addr_hit[195] & reg_re & !reg_error; + assign dio_pad_attr_65_we = addr_hit[195] & reg_we & !reg_error; + + assign dio_pad_attr_65_invert_65_wd = reg_wdata[0]; + + assign dio_pad_attr_65_virtual_od_en_65_wd = reg_wdata[1]; + + assign dio_pad_attr_65_pull_en_65_wd = reg_wdata[2]; + + assign dio_pad_attr_65_pull_select_65_wd = reg_wdata[3]; + + assign dio_pad_attr_65_keeper_en_65_wd = reg_wdata[4]; + + assign dio_pad_attr_65_schmitt_en_65_wd = reg_wdata[5]; + + assign dio_pad_attr_65_od_en_65_wd = reg_wdata[6]; + + assign dio_pad_attr_65_input_disable_65_wd = reg_wdata[7]; + + assign dio_pad_attr_65_slew_rate_65_wd = reg_wdata[17:16]; + + assign dio_pad_attr_65_drive_strength_65_wd = reg_wdata[23:20]; + assign dio_pad_attr_66_re = addr_hit[196] & reg_re & !reg_error; + assign dio_pad_attr_66_we = addr_hit[196] & reg_we & !reg_error; + + assign dio_pad_attr_66_invert_66_wd = reg_wdata[0]; + + assign dio_pad_attr_66_virtual_od_en_66_wd = reg_wdata[1]; + + assign dio_pad_attr_66_pull_en_66_wd = reg_wdata[2]; + + assign dio_pad_attr_66_pull_select_66_wd = reg_wdata[3]; + + assign dio_pad_attr_66_keeper_en_66_wd = reg_wdata[4]; + + assign dio_pad_attr_66_schmitt_en_66_wd = reg_wdata[5]; + + assign dio_pad_attr_66_od_en_66_wd = reg_wdata[6]; + + assign dio_pad_attr_66_input_disable_66_wd = reg_wdata[7]; + + assign dio_pad_attr_66_slew_rate_66_wd = reg_wdata[17:16]; + + assign dio_pad_attr_66_drive_strength_66_wd = reg_wdata[23:20]; + assign dio_pad_attr_67_re = addr_hit[197] & reg_re & !reg_error; + assign dio_pad_attr_67_we = addr_hit[197] & reg_we & !reg_error; + + assign dio_pad_attr_67_invert_67_wd = reg_wdata[0]; + + assign dio_pad_attr_67_virtual_od_en_67_wd = reg_wdata[1]; + + assign dio_pad_attr_67_pull_en_67_wd = reg_wdata[2]; + + assign dio_pad_attr_67_pull_select_67_wd = reg_wdata[3]; + + assign dio_pad_attr_67_keeper_en_67_wd = reg_wdata[4]; + + assign dio_pad_attr_67_schmitt_en_67_wd = reg_wdata[5]; + + assign dio_pad_attr_67_od_en_67_wd = reg_wdata[6]; + + assign dio_pad_attr_67_input_disable_67_wd = reg_wdata[7]; + + assign dio_pad_attr_67_slew_rate_67_wd = reg_wdata[17:16]; + + assign dio_pad_attr_67_drive_strength_67_wd = reg_wdata[23:20]; + assign dio_pad_attr_68_re = addr_hit[198] & reg_re & !reg_error; + assign dio_pad_attr_68_we = addr_hit[198] & reg_we & !reg_error; + + assign dio_pad_attr_68_invert_68_wd = reg_wdata[0]; + + assign dio_pad_attr_68_virtual_od_en_68_wd = reg_wdata[1]; + + assign dio_pad_attr_68_pull_en_68_wd = reg_wdata[2]; + + assign dio_pad_attr_68_pull_select_68_wd = reg_wdata[3]; + + assign dio_pad_attr_68_keeper_en_68_wd = reg_wdata[4]; + + assign dio_pad_attr_68_schmitt_en_68_wd = reg_wdata[5]; + + assign dio_pad_attr_68_od_en_68_wd = reg_wdata[6]; + + assign dio_pad_attr_68_input_disable_68_wd = reg_wdata[7]; + + assign dio_pad_attr_68_slew_rate_68_wd = reg_wdata[17:16]; + + assign dio_pad_attr_68_drive_strength_68_wd = reg_wdata[23:20]; + assign dio_pad_attr_69_re = addr_hit[199] & reg_re & !reg_error; + assign dio_pad_attr_69_we = addr_hit[199] & reg_we & !reg_error; + + assign dio_pad_attr_69_invert_69_wd = reg_wdata[0]; + + assign dio_pad_attr_69_virtual_od_en_69_wd = reg_wdata[1]; + + assign dio_pad_attr_69_pull_en_69_wd = reg_wdata[2]; + + assign dio_pad_attr_69_pull_select_69_wd = reg_wdata[3]; + + assign dio_pad_attr_69_keeper_en_69_wd = reg_wdata[4]; + + assign dio_pad_attr_69_schmitt_en_69_wd = reg_wdata[5]; + + assign dio_pad_attr_69_od_en_69_wd = reg_wdata[6]; + + assign dio_pad_attr_69_input_disable_69_wd = reg_wdata[7]; + + assign dio_pad_attr_69_slew_rate_69_wd = reg_wdata[17:16]; + + assign dio_pad_attr_69_drive_strength_69_wd = reg_wdata[23:20]; + assign dio_pad_attr_70_re = addr_hit[200] & reg_re & !reg_error; + assign dio_pad_attr_70_we = addr_hit[200] & reg_we & !reg_error; + + assign dio_pad_attr_70_invert_70_wd = reg_wdata[0]; + + assign dio_pad_attr_70_virtual_od_en_70_wd = reg_wdata[1]; + + assign dio_pad_attr_70_pull_en_70_wd = reg_wdata[2]; + + assign dio_pad_attr_70_pull_select_70_wd = reg_wdata[3]; + + assign dio_pad_attr_70_keeper_en_70_wd = reg_wdata[4]; + + assign dio_pad_attr_70_schmitt_en_70_wd = reg_wdata[5]; + + assign dio_pad_attr_70_od_en_70_wd = reg_wdata[6]; + + assign dio_pad_attr_70_input_disable_70_wd = reg_wdata[7]; + + assign dio_pad_attr_70_slew_rate_70_wd = reg_wdata[17:16]; + + assign dio_pad_attr_70_drive_strength_70_wd = reg_wdata[23:20]; + assign dio_pad_attr_71_re = addr_hit[201] & reg_re & !reg_error; + assign dio_pad_attr_71_we = addr_hit[201] & reg_we & !reg_error; + + assign dio_pad_attr_71_invert_71_wd = reg_wdata[0]; + + assign dio_pad_attr_71_virtual_od_en_71_wd = reg_wdata[1]; + + assign dio_pad_attr_71_pull_en_71_wd = reg_wdata[2]; + + assign dio_pad_attr_71_pull_select_71_wd = reg_wdata[3]; + + assign dio_pad_attr_71_keeper_en_71_wd = reg_wdata[4]; + + assign dio_pad_attr_71_schmitt_en_71_wd = reg_wdata[5]; + + assign dio_pad_attr_71_od_en_71_wd = reg_wdata[6]; + + assign dio_pad_attr_71_input_disable_71_wd = reg_wdata[7]; + + assign dio_pad_attr_71_slew_rate_71_wd = reg_wdata[17:16]; + + assign dio_pad_attr_71_drive_strength_71_wd = reg_wdata[23:20]; + assign dio_pad_attr_72_re = addr_hit[202] & reg_re & !reg_error; + assign dio_pad_attr_72_we = addr_hit[202] & reg_we & !reg_error; + + assign dio_pad_attr_72_invert_72_wd = reg_wdata[0]; + + assign dio_pad_attr_72_virtual_od_en_72_wd = reg_wdata[1]; + + assign dio_pad_attr_72_pull_en_72_wd = reg_wdata[2]; + + assign dio_pad_attr_72_pull_select_72_wd = reg_wdata[3]; + + assign dio_pad_attr_72_keeper_en_72_wd = reg_wdata[4]; + + assign dio_pad_attr_72_schmitt_en_72_wd = reg_wdata[5]; + + assign dio_pad_attr_72_od_en_72_wd = reg_wdata[6]; + + assign dio_pad_attr_72_input_disable_72_wd = reg_wdata[7]; + + assign dio_pad_attr_72_slew_rate_72_wd = reg_wdata[17:16]; + + assign dio_pad_attr_72_drive_strength_72_wd = reg_wdata[23:20]; + assign mio_pad_sleep_status_we = addr_hit[203] & reg_we & !reg_error; + + assign mio_pad_sleep_status_en_0_wd = reg_wdata[0]; + + assign mio_pad_sleep_status_en_1_wd = reg_wdata[1]; + + assign mio_pad_sleep_status_en_2_wd = reg_wdata[2]; + + assign mio_pad_sleep_status_en_3_wd = reg_wdata[3]; + + assign mio_pad_sleep_status_en_4_wd = reg_wdata[4]; + + assign mio_pad_sleep_status_en_5_wd = reg_wdata[5]; + + assign mio_pad_sleep_status_en_6_wd = reg_wdata[6]; + + assign mio_pad_sleep_status_en_7_wd = reg_wdata[7]; + + assign mio_pad_sleep_status_en_8_wd = reg_wdata[8]; + + assign mio_pad_sleep_status_en_9_wd = reg_wdata[9]; + + assign mio_pad_sleep_status_en_10_wd = reg_wdata[10]; + + assign mio_pad_sleep_status_en_11_wd = reg_wdata[11]; + assign mio_pad_sleep_regwen_0_we = addr_hit[204] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_0_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_1_we = addr_hit[205] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_1_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_2_we = addr_hit[206] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_2_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_3_we = addr_hit[207] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_3_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_4_we = addr_hit[208] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_4_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_5_we = addr_hit[209] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_5_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_6_we = addr_hit[210] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_6_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_7_we = addr_hit[211] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_7_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_8_we = addr_hit[212] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_8_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_9_we = addr_hit[213] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_9_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_10_we = addr_hit[214] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_10_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_11_we = addr_hit[215] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_11_wd = reg_wdata[0]; + assign mio_pad_sleep_en_0_we = addr_hit[216] & reg_we & !reg_error; + + assign mio_pad_sleep_en_0_wd = reg_wdata[0]; + assign mio_pad_sleep_en_1_we = addr_hit[217] & reg_we & !reg_error; + + assign mio_pad_sleep_en_1_wd = reg_wdata[0]; + assign mio_pad_sleep_en_2_we = addr_hit[218] & reg_we & !reg_error; + + assign mio_pad_sleep_en_2_wd = reg_wdata[0]; + assign mio_pad_sleep_en_3_we = addr_hit[219] & reg_we & !reg_error; + + assign mio_pad_sleep_en_3_wd = reg_wdata[0]; + assign mio_pad_sleep_en_4_we = addr_hit[220] & reg_we & !reg_error; + + assign mio_pad_sleep_en_4_wd = reg_wdata[0]; + assign mio_pad_sleep_en_5_we = addr_hit[221] & reg_we & !reg_error; + + assign mio_pad_sleep_en_5_wd = reg_wdata[0]; + assign mio_pad_sleep_en_6_we = addr_hit[222] & reg_we & !reg_error; + + assign mio_pad_sleep_en_6_wd = reg_wdata[0]; + assign mio_pad_sleep_en_7_we = addr_hit[223] & reg_we & !reg_error; + + assign mio_pad_sleep_en_7_wd = reg_wdata[0]; + assign mio_pad_sleep_en_8_we = addr_hit[224] & reg_we & !reg_error; + + assign mio_pad_sleep_en_8_wd = reg_wdata[0]; + assign mio_pad_sleep_en_9_we = addr_hit[225] & reg_we & !reg_error; + + assign mio_pad_sleep_en_9_wd = reg_wdata[0]; + assign mio_pad_sleep_en_10_we = addr_hit[226] & reg_we & !reg_error; + + assign mio_pad_sleep_en_10_wd = reg_wdata[0]; + assign mio_pad_sleep_en_11_we = addr_hit[227] & reg_we & !reg_error; + + assign mio_pad_sleep_en_11_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_0_we = addr_hit[228] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_1_we = addr_hit[229] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_2_we = addr_hit[230] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_3_we = addr_hit[231] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_4_we = addr_hit[232] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_5_we = addr_hit[233] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_6_we = addr_hit[234] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_7_we = addr_hit[235] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_8_we = addr_hit[236] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_9_we = addr_hit[237] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_10_we = addr_hit[238] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_11_we = addr_hit[239] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_0_we = addr_hit[240] & reg_we & !reg_error; + + assign dio_pad_sleep_status_0_en_0_wd = reg_wdata[0]; + + assign dio_pad_sleep_status_0_en_1_wd = reg_wdata[1]; + + assign dio_pad_sleep_status_0_en_2_wd = reg_wdata[2]; + + assign dio_pad_sleep_status_0_en_3_wd = reg_wdata[3]; + + assign dio_pad_sleep_status_0_en_4_wd = reg_wdata[4]; + + assign dio_pad_sleep_status_0_en_5_wd = reg_wdata[5]; + + assign dio_pad_sleep_status_0_en_6_wd = reg_wdata[6]; + + assign dio_pad_sleep_status_0_en_7_wd = reg_wdata[7]; + + assign dio_pad_sleep_status_0_en_8_wd = reg_wdata[8]; + + assign dio_pad_sleep_status_0_en_9_wd = reg_wdata[9]; + + assign dio_pad_sleep_status_0_en_10_wd = reg_wdata[10]; + + assign dio_pad_sleep_status_0_en_11_wd = reg_wdata[11]; + + assign dio_pad_sleep_status_0_en_12_wd = reg_wdata[12]; + + assign dio_pad_sleep_status_0_en_13_wd = reg_wdata[13]; + + assign dio_pad_sleep_status_0_en_14_wd = reg_wdata[14]; + + assign dio_pad_sleep_status_0_en_15_wd = reg_wdata[15]; + + assign dio_pad_sleep_status_0_en_16_wd = reg_wdata[16]; + + assign dio_pad_sleep_status_0_en_17_wd = reg_wdata[17]; + + assign dio_pad_sleep_status_0_en_18_wd = reg_wdata[18]; + + assign dio_pad_sleep_status_0_en_19_wd = reg_wdata[19]; + + assign dio_pad_sleep_status_0_en_20_wd = reg_wdata[20]; + + assign dio_pad_sleep_status_0_en_21_wd = reg_wdata[21]; + + assign dio_pad_sleep_status_0_en_22_wd = reg_wdata[22]; + + assign dio_pad_sleep_status_0_en_23_wd = reg_wdata[23]; + + assign dio_pad_sleep_status_0_en_24_wd = reg_wdata[24]; + + assign dio_pad_sleep_status_0_en_25_wd = reg_wdata[25]; + + assign dio_pad_sleep_status_0_en_26_wd = reg_wdata[26]; + + assign dio_pad_sleep_status_0_en_27_wd = reg_wdata[27]; + + assign dio_pad_sleep_status_0_en_28_wd = reg_wdata[28]; + + assign dio_pad_sleep_status_0_en_29_wd = reg_wdata[29]; + + assign dio_pad_sleep_status_0_en_30_wd = reg_wdata[30]; + + assign dio_pad_sleep_status_0_en_31_wd = reg_wdata[31]; + assign dio_pad_sleep_status_1_we = addr_hit[241] & reg_we & !reg_error; + + assign dio_pad_sleep_status_1_en_32_wd = reg_wdata[0]; + + assign dio_pad_sleep_status_1_en_33_wd = reg_wdata[1]; + + assign dio_pad_sleep_status_1_en_34_wd = reg_wdata[2]; + + assign dio_pad_sleep_status_1_en_35_wd = reg_wdata[3]; + + assign dio_pad_sleep_status_1_en_36_wd = reg_wdata[4]; + + assign dio_pad_sleep_status_1_en_37_wd = reg_wdata[5]; + + assign dio_pad_sleep_status_1_en_38_wd = reg_wdata[6]; + + assign dio_pad_sleep_status_1_en_39_wd = reg_wdata[7]; + + assign dio_pad_sleep_status_1_en_40_wd = reg_wdata[8]; + + assign dio_pad_sleep_status_1_en_41_wd = reg_wdata[9]; + + assign dio_pad_sleep_status_1_en_42_wd = reg_wdata[10]; + + assign dio_pad_sleep_status_1_en_43_wd = reg_wdata[11]; + + assign dio_pad_sleep_status_1_en_44_wd = reg_wdata[12]; + + assign dio_pad_sleep_status_1_en_45_wd = reg_wdata[13]; + + assign dio_pad_sleep_status_1_en_46_wd = reg_wdata[14]; + + assign dio_pad_sleep_status_1_en_47_wd = reg_wdata[15]; + + assign dio_pad_sleep_status_1_en_48_wd = reg_wdata[16]; + + assign dio_pad_sleep_status_1_en_49_wd = reg_wdata[17]; + + assign dio_pad_sleep_status_1_en_50_wd = reg_wdata[18]; + + assign dio_pad_sleep_status_1_en_51_wd = reg_wdata[19]; + + assign dio_pad_sleep_status_1_en_52_wd = reg_wdata[20]; + + assign dio_pad_sleep_status_1_en_53_wd = reg_wdata[21]; + + assign dio_pad_sleep_status_1_en_54_wd = reg_wdata[22]; + + assign dio_pad_sleep_status_1_en_55_wd = reg_wdata[23]; + + assign dio_pad_sleep_status_1_en_56_wd = reg_wdata[24]; + + assign dio_pad_sleep_status_1_en_57_wd = reg_wdata[25]; + + assign dio_pad_sleep_status_1_en_58_wd = reg_wdata[26]; + + assign dio_pad_sleep_status_1_en_59_wd = reg_wdata[27]; + + assign dio_pad_sleep_status_1_en_60_wd = reg_wdata[28]; + + assign dio_pad_sleep_status_1_en_61_wd = reg_wdata[29]; + + assign dio_pad_sleep_status_1_en_62_wd = reg_wdata[30]; + + assign dio_pad_sleep_status_1_en_63_wd = reg_wdata[31]; + assign dio_pad_sleep_status_2_we = addr_hit[242] & reg_we & !reg_error; + + assign dio_pad_sleep_status_2_en_64_wd = reg_wdata[0]; + + assign dio_pad_sleep_status_2_en_65_wd = reg_wdata[1]; + + assign dio_pad_sleep_status_2_en_66_wd = reg_wdata[2]; + + assign dio_pad_sleep_status_2_en_67_wd = reg_wdata[3]; + + assign dio_pad_sleep_status_2_en_68_wd = reg_wdata[4]; + + assign dio_pad_sleep_status_2_en_69_wd = reg_wdata[5]; + + assign dio_pad_sleep_status_2_en_70_wd = reg_wdata[6]; + + assign dio_pad_sleep_status_2_en_71_wd = reg_wdata[7]; + + assign dio_pad_sleep_status_2_en_72_wd = reg_wdata[8]; + assign dio_pad_sleep_regwen_0_we = addr_hit[243] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_0_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_1_we = addr_hit[244] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_1_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_2_we = addr_hit[245] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_2_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_3_we = addr_hit[246] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_3_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_4_we = addr_hit[247] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_4_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_5_we = addr_hit[248] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_5_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_6_we = addr_hit[249] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_6_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_7_we = addr_hit[250] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_7_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_8_we = addr_hit[251] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_8_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_9_we = addr_hit[252] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_9_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_10_we = addr_hit[253] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_10_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_11_we = addr_hit[254] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_11_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_12_we = addr_hit[255] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_12_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_13_we = addr_hit[256] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_13_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_14_we = addr_hit[257] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_14_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_15_we = addr_hit[258] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_15_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_16_we = addr_hit[259] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_16_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_17_we = addr_hit[260] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_17_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_18_we = addr_hit[261] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_18_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_19_we = addr_hit[262] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_19_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_20_we = addr_hit[263] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_20_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_21_we = addr_hit[264] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_21_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_22_we = addr_hit[265] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_22_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_23_we = addr_hit[266] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_23_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_24_we = addr_hit[267] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_24_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_25_we = addr_hit[268] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_25_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_26_we = addr_hit[269] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_26_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_27_we = addr_hit[270] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_27_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_28_we = addr_hit[271] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_28_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_29_we = addr_hit[272] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_29_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_30_we = addr_hit[273] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_30_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_31_we = addr_hit[274] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_31_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_32_we = addr_hit[275] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_32_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_33_we = addr_hit[276] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_33_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_34_we = addr_hit[277] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_34_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_35_we = addr_hit[278] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_35_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_36_we = addr_hit[279] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_36_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_37_we = addr_hit[280] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_37_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_38_we = addr_hit[281] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_38_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_39_we = addr_hit[282] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_39_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_40_we = addr_hit[283] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_40_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_41_we = addr_hit[284] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_41_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_42_we = addr_hit[285] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_42_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_43_we = addr_hit[286] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_43_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_44_we = addr_hit[287] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_44_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_45_we = addr_hit[288] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_45_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_46_we = addr_hit[289] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_46_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_47_we = addr_hit[290] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_47_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_48_we = addr_hit[291] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_48_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_49_we = addr_hit[292] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_49_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_50_we = addr_hit[293] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_50_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_51_we = addr_hit[294] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_51_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_52_we = addr_hit[295] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_52_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_53_we = addr_hit[296] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_53_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_54_we = addr_hit[297] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_54_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_55_we = addr_hit[298] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_55_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_56_we = addr_hit[299] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_56_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_57_we = addr_hit[300] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_57_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_58_we = addr_hit[301] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_58_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_59_we = addr_hit[302] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_59_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_60_we = addr_hit[303] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_60_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_61_we = addr_hit[304] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_61_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_62_we = addr_hit[305] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_62_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_63_we = addr_hit[306] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_63_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_64_we = addr_hit[307] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_64_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_65_we = addr_hit[308] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_65_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_66_we = addr_hit[309] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_66_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_67_we = addr_hit[310] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_67_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_68_we = addr_hit[311] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_68_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_69_we = addr_hit[312] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_69_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_70_we = addr_hit[313] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_70_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_71_we = addr_hit[314] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_71_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_72_we = addr_hit[315] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_72_wd = reg_wdata[0]; + assign dio_pad_sleep_en_0_we = addr_hit[316] & reg_we & !reg_error; + + assign dio_pad_sleep_en_0_wd = reg_wdata[0]; + assign dio_pad_sleep_en_1_we = addr_hit[317] & reg_we & !reg_error; + + assign dio_pad_sleep_en_1_wd = reg_wdata[0]; + assign dio_pad_sleep_en_2_we = addr_hit[318] & reg_we & !reg_error; + + assign dio_pad_sleep_en_2_wd = reg_wdata[0]; + assign dio_pad_sleep_en_3_we = addr_hit[319] & reg_we & !reg_error; + + assign dio_pad_sleep_en_3_wd = reg_wdata[0]; + assign dio_pad_sleep_en_4_we = addr_hit[320] & reg_we & !reg_error; + + assign dio_pad_sleep_en_4_wd = reg_wdata[0]; + assign dio_pad_sleep_en_5_we = addr_hit[321] & reg_we & !reg_error; + + assign dio_pad_sleep_en_5_wd = reg_wdata[0]; + assign dio_pad_sleep_en_6_we = addr_hit[322] & reg_we & !reg_error; + + assign dio_pad_sleep_en_6_wd = reg_wdata[0]; + assign dio_pad_sleep_en_7_we = addr_hit[323] & reg_we & !reg_error; + + assign dio_pad_sleep_en_7_wd = reg_wdata[0]; + assign dio_pad_sleep_en_8_we = addr_hit[324] & reg_we & !reg_error; + + assign dio_pad_sleep_en_8_wd = reg_wdata[0]; + assign dio_pad_sleep_en_9_we = addr_hit[325] & reg_we & !reg_error; + + assign dio_pad_sleep_en_9_wd = reg_wdata[0]; + assign dio_pad_sleep_en_10_we = addr_hit[326] & reg_we & !reg_error; + + assign dio_pad_sleep_en_10_wd = reg_wdata[0]; + assign dio_pad_sleep_en_11_we = addr_hit[327] & reg_we & !reg_error; + + assign dio_pad_sleep_en_11_wd = reg_wdata[0]; + assign dio_pad_sleep_en_12_we = addr_hit[328] & reg_we & !reg_error; + + assign dio_pad_sleep_en_12_wd = reg_wdata[0]; + assign dio_pad_sleep_en_13_we = addr_hit[329] & reg_we & !reg_error; + + assign dio_pad_sleep_en_13_wd = reg_wdata[0]; + assign dio_pad_sleep_en_14_we = addr_hit[330] & reg_we & !reg_error; + + assign dio_pad_sleep_en_14_wd = reg_wdata[0]; + assign dio_pad_sleep_en_15_we = addr_hit[331] & reg_we & !reg_error; + + assign dio_pad_sleep_en_15_wd = reg_wdata[0]; + assign dio_pad_sleep_en_16_we = addr_hit[332] & reg_we & !reg_error; + + assign dio_pad_sleep_en_16_wd = reg_wdata[0]; + assign dio_pad_sleep_en_17_we = addr_hit[333] & reg_we & !reg_error; + + assign dio_pad_sleep_en_17_wd = reg_wdata[0]; + assign dio_pad_sleep_en_18_we = addr_hit[334] & reg_we & !reg_error; + + assign dio_pad_sleep_en_18_wd = reg_wdata[0]; + assign dio_pad_sleep_en_19_we = addr_hit[335] & reg_we & !reg_error; + + assign dio_pad_sleep_en_19_wd = reg_wdata[0]; + assign dio_pad_sleep_en_20_we = addr_hit[336] & reg_we & !reg_error; + + assign dio_pad_sleep_en_20_wd = reg_wdata[0]; + assign dio_pad_sleep_en_21_we = addr_hit[337] & reg_we & !reg_error; + + assign dio_pad_sleep_en_21_wd = reg_wdata[0]; + assign dio_pad_sleep_en_22_we = addr_hit[338] & reg_we & !reg_error; + + assign dio_pad_sleep_en_22_wd = reg_wdata[0]; + assign dio_pad_sleep_en_23_we = addr_hit[339] & reg_we & !reg_error; + + assign dio_pad_sleep_en_23_wd = reg_wdata[0]; + assign dio_pad_sleep_en_24_we = addr_hit[340] & reg_we & !reg_error; + + assign dio_pad_sleep_en_24_wd = reg_wdata[0]; + assign dio_pad_sleep_en_25_we = addr_hit[341] & reg_we & !reg_error; + + assign dio_pad_sleep_en_25_wd = reg_wdata[0]; + assign dio_pad_sleep_en_26_we = addr_hit[342] & reg_we & !reg_error; + + assign dio_pad_sleep_en_26_wd = reg_wdata[0]; + assign dio_pad_sleep_en_27_we = addr_hit[343] & reg_we & !reg_error; + + assign dio_pad_sleep_en_27_wd = reg_wdata[0]; + assign dio_pad_sleep_en_28_we = addr_hit[344] & reg_we & !reg_error; + + assign dio_pad_sleep_en_28_wd = reg_wdata[0]; + assign dio_pad_sleep_en_29_we = addr_hit[345] & reg_we & !reg_error; + + assign dio_pad_sleep_en_29_wd = reg_wdata[0]; + assign dio_pad_sleep_en_30_we = addr_hit[346] & reg_we & !reg_error; + + assign dio_pad_sleep_en_30_wd = reg_wdata[0]; + assign dio_pad_sleep_en_31_we = addr_hit[347] & reg_we & !reg_error; + + assign dio_pad_sleep_en_31_wd = reg_wdata[0]; + assign dio_pad_sleep_en_32_we = addr_hit[348] & reg_we & !reg_error; + + assign dio_pad_sleep_en_32_wd = reg_wdata[0]; + assign dio_pad_sleep_en_33_we = addr_hit[349] & reg_we & !reg_error; + + assign dio_pad_sleep_en_33_wd = reg_wdata[0]; + assign dio_pad_sleep_en_34_we = addr_hit[350] & reg_we & !reg_error; + + assign dio_pad_sleep_en_34_wd = reg_wdata[0]; + assign dio_pad_sleep_en_35_we = addr_hit[351] & reg_we & !reg_error; + + assign dio_pad_sleep_en_35_wd = reg_wdata[0]; + assign dio_pad_sleep_en_36_we = addr_hit[352] & reg_we & !reg_error; + + assign dio_pad_sleep_en_36_wd = reg_wdata[0]; + assign dio_pad_sleep_en_37_we = addr_hit[353] & reg_we & !reg_error; + + assign dio_pad_sleep_en_37_wd = reg_wdata[0]; + assign dio_pad_sleep_en_38_we = addr_hit[354] & reg_we & !reg_error; + + assign dio_pad_sleep_en_38_wd = reg_wdata[0]; + assign dio_pad_sleep_en_39_we = addr_hit[355] & reg_we & !reg_error; + + assign dio_pad_sleep_en_39_wd = reg_wdata[0]; + assign dio_pad_sleep_en_40_we = addr_hit[356] & reg_we & !reg_error; + + assign dio_pad_sleep_en_40_wd = reg_wdata[0]; + assign dio_pad_sleep_en_41_we = addr_hit[357] & reg_we & !reg_error; + + assign dio_pad_sleep_en_41_wd = reg_wdata[0]; + assign dio_pad_sleep_en_42_we = addr_hit[358] & reg_we & !reg_error; + + assign dio_pad_sleep_en_42_wd = reg_wdata[0]; + assign dio_pad_sleep_en_43_we = addr_hit[359] & reg_we & !reg_error; + + assign dio_pad_sleep_en_43_wd = reg_wdata[0]; + assign dio_pad_sleep_en_44_we = addr_hit[360] & reg_we & !reg_error; + + assign dio_pad_sleep_en_44_wd = reg_wdata[0]; + assign dio_pad_sleep_en_45_we = addr_hit[361] & reg_we & !reg_error; + + assign dio_pad_sleep_en_45_wd = reg_wdata[0]; + assign dio_pad_sleep_en_46_we = addr_hit[362] & reg_we & !reg_error; + + assign dio_pad_sleep_en_46_wd = reg_wdata[0]; + assign dio_pad_sleep_en_47_we = addr_hit[363] & reg_we & !reg_error; + + assign dio_pad_sleep_en_47_wd = reg_wdata[0]; + assign dio_pad_sleep_en_48_we = addr_hit[364] & reg_we & !reg_error; + + assign dio_pad_sleep_en_48_wd = reg_wdata[0]; + assign dio_pad_sleep_en_49_we = addr_hit[365] & reg_we & !reg_error; + + assign dio_pad_sleep_en_49_wd = reg_wdata[0]; + assign dio_pad_sleep_en_50_we = addr_hit[366] & reg_we & !reg_error; + + assign dio_pad_sleep_en_50_wd = reg_wdata[0]; + assign dio_pad_sleep_en_51_we = addr_hit[367] & reg_we & !reg_error; + + assign dio_pad_sleep_en_51_wd = reg_wdata[0]; + assign dio_pad_sleep_en_52_we = addr_hit[368] & reg_we & !reg_error; + + assign dio_pad_sleep_en_52_wd = reg_wdata[0]; + assign dio_pad_sleep_en_53_we = addr_hit[369] & reg_we & !reg_error; + + assign dio_pad_sleep_en_53_wd = reg_wdata[0]; + assign dio_pad_sleep_en_54_we = addr_hit[370] & reg_we & !reg_error; + + assign dio_pad_sleep_en_54_wd = reg_wdata[0]; + assign dio_pad_sleep_en_55_we = addr_hit[371] & reg_we & !reg_error; + + assign dio_pad_sleep_en_55_wd = reg_wdata[0]; + assign dio_pad_sleep_en_56_we = addr_hit[372] & reg_we & !reg_error; + + assign dio_pad_sleep_en_56_wd = reg_wdata[0]; + assign dio_pad_sleep_en_57_we = addr_hit[373] & reg_we & !reg_error; + + assign dio_pad_sleep_en_57_wd = reg_wdata[0]; + assign dio_pad_sleep_en_58_we = addr_hit[374] & reg_we & !reg_error; + + assign dio_pad_sleep_en_58_wd = reg_wdata[0]; + assign dio_pad_sleep_en_59_we = addr_hit[375] & reg_we & !reg_error; + + assign dio_pad_sleep_en_59_wd = reg_wdata[0]; + assign dio_pad_sleep_en_60_we = addr_hit[376] & reg_we & !reg_error; + + assign dio_pad_sleep_en_60_wd = reg_wdata[0]; + assign dio_pad_sleep_en_61_we = addr_hit[377] & reg_we & !reg_error; + + assign dio_pad_sleep_en_61_wd = reg_wdata[0]; + assign dio_pad_sleep_en_62_we = addr_hit[378] & reg_we & !reg_error; + + assign dio_pad_sleep_en_62_wd = reg_wdata[0]; + assign dio_pad_sleep_en_63_we = addr_hit[379] & reg_we & !reg_error; + + assign dio_pad_sleep_en_63_wd = reg_wdata[0]; + assign dio_pad_sleep_en_64_we = addr_hit[380] & reg_we & !reg_error; + + assign dio_pad_sleep_en_64_wd = reg_wdata[0]; + assign dio_pad_sleep_en_65_we = addr_hit[381] & reg_we & !reg_error; + + assign dio_pad_sleep_en_65_wd = reg_wdata[0]; + assign dio_pad_sleep_en_66_we = addr_hit[382] & reg_we & !reg_error; + + assign dio_pad_sleep_en_66_wd = reg_wdata[0]; + assign dio_pad_sleep_en_67_we = addr_hit[383] & reg_we & !reg_error; + + assign dio_pad_sleep_en_67_wd = reg_wdata[0]; + assign dio_pad_sleep_en_68_we = addr_hit[384] & reg_we & !reg_error; + + assign dio_pad_sleep_en_68_wd = reg_wdata[0]; + assign dio_pad_sleep_en_69_we = addr_hit[385] & reg_we & !reg_error; + + assign dio_pad_sleep_en_69_wd = reg_wdata[0]; + assign dio_pad_sleep_en_70_we = addr_hit[386] & reg_we & !reg_error; + + assign dio_pad_sleep_en_70_wd = reg_wdata[0]; + assign dio_pad_sleep_en_71_we = addr_hit[387] & reg_we & !reg_error; + + assign dio_pad_sleep_en_71_wd = reg_wdata[0]; + assign dio_pad_sleep_en_72_we = addr_hit[388] & reg_we & !reg_error; + + assign dio_pad_sleep_en_72_wd = reg_wdata[0]; + assign dio_pad_sleep_mode_0_we = addr_hit[389] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_1_we = addr_hit[390] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_2_we = addr_hit[391] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_3_we = addr_hit[392] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_4_we = addr_hit[393] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_5_we = addr_hit[394] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_6_we = addr_hit[395] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_7_we = addr_hit[396] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_8_we = addr_hit[397] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_9_we = addr_hit[398] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_10_we = addr_hit[399] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_11_we = addr_hit[400] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_12_we = addr_hit[401] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_13_we = addr_hit[402] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_14_we = addr_hit[403] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_15_we = addr_hit[404] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_15_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_16_we = addr_hit[405] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_16_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_17_we = addr_hit[406] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_17_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_18_we = addr_hit[407] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_18_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_19_we = addr_hit[408] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_19_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_20_we = addr_hit[409] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_20_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_21_we = addr_hit[410] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_21_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_22_we = addr_hit[411] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_22_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_23_we = addr_hit[412] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_23_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_24_we = addr_hit[413] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_24_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_25_we = addr_hit[414] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_25_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_26_we = addr_hit[415] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_26_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_27_we = addr_hit[416] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_27_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_28_we = addr_hit[417] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_28_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_29_we = addr_hit[418] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_29_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_30_we = addr_hit[419] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_30_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_31_we = addr_hit[420] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_31_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_32_we = addr_hit[421] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_32_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_33_we = addr_hit[422] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_33_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_34_we = addr_hit[423] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_34_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_35_we = addr_hit[424] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_35_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_36_we = addr_hit[425] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_36_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_37_we = addr_hit[426] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_37_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_38_we = addr_hit[427] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_38_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_39_we = addr_hit[428] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_39_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_40_we = addr_hit[429] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_40_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_41_we = addr_hit[430] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_41_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_42_we = addr_hit[431] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_42_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_43_we = addr_hit[432] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_43_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_44_we = addr_hit[433] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_44_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_45_we = addr_hit[434] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_45_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_46_we = addr_hit[435] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_46_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_47_we = addr_hit[436] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_47_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_48_we = addr_hit[437] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_48_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_49_we = addr_hit[438] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_49_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_50_we = addr_hit[439] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_50_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_51_we = addr_hit[440] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_51_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_52_we = addr_hit[441] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_52_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_53_we = addr_hit[442] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_53_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_54_we = addr_hit[443] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_54_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_55_we = addr_hit[444] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_55_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_56_we = addr_hit[445] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_56_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_57_we = addr_hit[446] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_57_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_58_we = addr_hit[447] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_58_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_59_we = addr_hit[448] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_59_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_60_we = addr_hit[449] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_60_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_61_we = addr_hit[450] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_61_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_62_we = addr_hit[451] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_62_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_63_we = addr_hit[452] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_63_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_64_we = addr_hit[453] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_64_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_65_we = addr_hit[454] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_65_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_66_we = addr_hit[455] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_66_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_67_we = addr_hit[456] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_67_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_68_we = addr_hit[457] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_68_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_69_we = addr_hit[458] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_69_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_70_we = addr_hit[459] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_70_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_71_we = addr_hit[460] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_71_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_72_we = addr_hit[461] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_72_wd = reg_wdata[1:0]; + assign wkup_detector_regwen_0_we = addr_hit[462] & reg_we & !reg_error; + + assign wkup_detector_regwen_0_wd = reg_wdata[0]; + assign wkup_detector_regwen_1_we = addr_hit[463] & reg_we & !reg_error; + + assign wkup_detector_regwen_1_wd = reg_wdata[0]; + assign wkup_detector_regwen_2_we = addr_hit[464] & reg_we & !reg_error; + + assign wkup_detector_regwen_2_wd = reg_wdata[0]; + assign wkup_detector_regwen_3_we = addr_hit[465] & reg_we & !reg_error; + + assign wkup_detector_regwen_3_wd = reg_wdata[0]; + assign wkup_detector_regwen_4_we = addr_hit[466] & reg_we & !reg_error; + + assign wkup_detector_regwen_4_wd = reg_wdata[0]; + assign wkup_detector_regwen_5_we = addr_hit[467] & reg_we & !reg_error; + + assign wkup_detector_regwen_5_wd = reg_wdata[0]; + assign wkup_detector_regwen_6_we = addr_hit[468] & reg_we & !reg_error; + + assign wkup_detector_regwen_6_wd = reg_wdata[0]; + assign wkup_detector_regwen_7_we = addr_hit[469] & reg_we & !reg_error; + + assign wkup_detector_regwen_7_wd = reg_wdata[0]; + assign wkup_detector_en_0_we = addr_hit[470] & reg_we & !reg_error; + + assign wkup_detector_en_1_we = addr_hit[471] & reg_we & !reg_error; + + assign wkup_detector_en_2_we = addr_hit[472] & reg_we & !reg_error; + + assign wkup_detector_en_3_we = addr_hit[473] & reg_we & !reg_error; + + assign wkup_detector_en_4_we = addr_hit[474] & reg_we & !reg_error; + + assign wkup_detector_en_5_we = addr_hit[475] & reg_we & !reg_error; + + assign wkup_detector_en_6_we = addr_hit[476] & reg_we & !reg_error; + + assign wkup_detector_en_7_we = addr_hit[477] & reg_we & !reg_error; + + assign wkup_detector_0_we = addr_hit[478] & reg_we & !reg_error; + + + + assign wkup_detector_1_we = addr_hit[479] & reg_we & !reg_error; + + + + assign wkup_detector_2_we = addr_hit[480] & reg_we & !reg_error; + + + + assign wkup_detector_3_we = addr_hit[481] & reg_we & !reg_error; + + + + assign wkup_detector_4_we = addr_hit[482] & reg_we & !reg_error; + + + + assign wkup_detector_5_we = addr_hit[483] & reg_we & !reg_error; + + + + assign wkup_detector_6_we = addr_hit[484] & reg_we & !reg_error; + + + + assign wkup_detector_7_we = addr_hit[485] & reg_we & !reg_error; + + + + assign wkup_detector_cnt_th_0_we = addr_hit[486] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_1_we = addr_hit[487] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_2_we = addr_hit[488] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_3_we = addr_hit[489] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_4_we = addr_hit[490] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_5_we = addr_hit[491] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_6_we = addr_hit[492] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_7_we = addr_hit[493] & reg_we & !reg_error; + + assign wkup_detector_padsel_0_we = addr_hit[494] & reg_we & !reg_error; + + assign wkup_detector_padsel_0_wd = reg_wdata[5:0]; + assign wkup_detector_padsel_1_we = addr_hit[495] & reg_we & !reg_error; + + assign wkup_detector_padsel_1_wd = reg_wdata[5:0]; + assign wkup_detector_padsel_2_we = addr_hit[496] & reg_we & !reg_error; + + assign wkup_detector_padsel_2_wd = reg_wdata[5:0]; + assign wkup_detector_padsel_3_we = addr_hit[497] & reg_we & !reg_error; + + assign wkup_detector_padsel_3_wd = reg_wdata[5:0]; + assign wkup_detector_padsel_4_we = addr_hit[498] & reg_we & !reg_error; + + assign wkup_detector_padsel_4_wd = reg_wdata[5:0]; + assign wkup_detector_padsel_5_we = addr_hit[499] & reg_we & !reg_error; + + assign wkup_detector_padsel_5_wd = reg_wdata[5:0]; + assign wkup_detector_padsel_6_we = addr_hit[500] & reg_we & !reg_error; + + assign wkup_detector_padsel_6_wd = reg_wdata[5:0]; + assign wkup_detector_padsel_7_we = addr_hit[501] & reg_we & !reg_error; + + assign wkup_detector_padsel_7_wd = reg_wdata[5:0]; + assign wkup_cause_we = addr_hit[502] & reg_we & !reg_error; + + + + + + + + + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check = '0; + reg_we_check[0] = alert_test_we; + reg_we_check[1] = mio_periph_insel_regwen_0_we; + reg_we_check[2] = mio_periph_insel_regwen_1_we; + reg_we_check[3] = mio_periph_insel_regwen_2_we; + reg_we_check[4] = mio_periph_insel_regwen_3_we; + reg_we_check[5] = mio_periph_insel_0_gated_we; + reg_we_check[6] = mio_periph_insel_1_gated_we; + reg_we_check[7] = mio_periph_insel_2_gated_we; + reg_we_check[8] = mio_periph_insel_3_gated_we; + reg_we_check[9] = mio_outsel_regwen_0_we; + reg_we_check[10] = mio_outsel_regwen_1_we; + reg_we_check[11] = mio_outsel_regwen_2_we; + reg_we_check[12] = mio_outsel_regwen_3_we; + reg_we_check[13] = mio_outsel_regwen_4_we; + reg_we_check[14] = mio_outsel_regwen_5_we; + reg_we_check[15] = mio_outsel_regwen_6_we; + reg_we_check[16] = mio_outsel_regwen_7_we; + reg_we_check[17] = mio_outsel_regwen_8_we; + reg_we_check[18] = mio_outsel_regwen_9_we; + reg_we_check[19] = mio_outsel_regwen_10_we; + reg_we_check[20] = mio_outsel_regwen_11_we; + reg_we_check[21] = mio_outsel_0_gated_we; + reg_we_check[22] = mio_outsel_1_gated_we; + reg_we_check[23] = mio_outsel_2_gated_we; + reg_we_check[24] = mio_outsel_3_gated_we; + reg_we_check[25] = mio_outsel_4_gated_we; + reg_we_check[26] = mio_outsel_5_gated_we; + reg_we_check[27] = mio_outsel_6_gated_we; + reg_we_check[28] = mio_outsel_7_gated_we; + reg_we_check[29] = mio_outsel_8_gated_we; + reg_we_check[30] = mio_outsel_9_gated_we; + reg_we_check[31] = mio_outsel_10_gated_we; + reg_we_check[32] = mio_outsel_11_gated_we; + reg_we_check[33] = mio_pad_attr_regwen_0_we; + reg_we_check[34] = mio_pad_attr_regwen_1_we; + reg_we_check[35] = mio_pad_attr_regwen_2_we; + reg_we_check[36] = mio_pad_attr_regwen_3_we; + reg_we_check[37] = mio_pad_attr_regwen_4_we; + reg_we_check[38] = mio_pad_attr_regwen_5_we; + reg_we_check[39] = mio_pad_attr_regwen_6_we; + reg_we_check[40] = mio_pad_attr_regwen_7_we; + reg_we_check[41] = mio_pad_attr_regwen_8_we; + reg_we_check[42] = mio_pad_attr_regwen_9_we; + reg_we_check[43] = mio_pad_attr_regwen_10_we; + reg_we_check[44] = mio_pad_attr_regwen_11_we; + reg_we_check[45] = mio_pad_attr_0_gated_we; + reg_we_check[46] = mio_pad_attr_1_gated_we; + reg_we_check[47] = mio_pad_attr_2_gated_we; + reg_we_check[48] = mio_pad_attr_3_gated_we; + reg_we_check[49] = mio_pad_attr_4_gated_we; + reg_we_check[50] = mio_pad_attr_5_gated_we; + reg_we_check[51] = mio_pad_attr_6_gated_we; + reg_we_check[52] = mio_pad_attr_7_gated_we; + reg_we_check[53] = mio_pad_attr_8_gated_we; + reg_we_check[54] = mio_pad_attr_9_gated_we; + reg_we_check[55] = mio_pad_attr_10_gated_we; + reg_we_check[56] = mio_pad_attr_11_gated_we; + reg_we_check[57] = dio_pad_attr_regwen_0_we; + reg_we_check[58] = dio_pad_attr_regwen_1_we; + reg_we_check[59] = dio_pad_attr_regwen_2_we; + reg_we_check[60] = dio_pad_attr_regwen_3_we; + reg_we_check[61] = dio_pad_attr_regwen_4_we; + reg_we_check[62] = dio_pad_attr_regwen_5_we; + reg_we_check[63] = dio_pad_attr_regwen_6_we; + reg_we_check[64] = dio_pad_attr_regwen_7_we; + reg_we_check[65] = dio_pad_attr_regwen_8_we; + reg_we_check[66] = dio_pad_attr_regwen_9_we; + reg_we_check[67] = dio_pad_attr_regwen_10_we; + reg_we_check[68] = dio_pad_attr_regwen_11_we; + reg_we_check[69] = dio_pad_attr_regwen_12_we; + reg_we_check[70] = dio_pad_attr_regwen_13_we; + reg_we_check[71] = dio_pad_attr_regwen_14_we; + reg_we_check[72] = dio_pad_attr_regwen_15_we; + reg_we_check[73] = dio_pad_attr_regwen_16_we; + reg_we_check[74] = dio_pad_attr_regwen_17_we; + reg_we_check[75] = dio_pad_attr_regwen_18_we; + reg_we_check[76] = dio_pad_attr_regwen_19_we; + reg_we_check[77] = dio_pad_attr_regwen_20_we; + reg_we_check[78] = dio_pad_attr_regwen_21_we; + reg_we_check[79] = dio_pad_attr_regwen_22_we; + reg_we_check[80] = dio_pad_attr_regwen_23_we; + reg_we_check[81] = dio_pad_attr_regwen_24_we; + reg_we_check[82] = dio_pad_attr_regwen_25_we; + reg_we_check[83] = dio_pad_attr_regwen_26_we; + reg_we_check[84] = dio_pad_attr_regwen_27_we; + reg_we_check[85] = dio_pad_attr_regwen_28_we; + reg_we_check[86] = dio_pad_attr_regwen_29_we; + reg_we_check[87] = dio_pad_attr_regwen_30_we; + reg_we_check[88] = dio_pad_attr_regwen_31_we; + reg_we_check[89] = dio_pad_attr_regwen_32_we; + reg_we_check[90] = dio_pad_attr_regwen_33_we; + reg_we_check[91] = dio_pad_attr_regwen_34_we; + reg_we_check[92] = dio_pad_attr_regwen_35_we; + reg_we_check[93] = dio_pad_attr_regwen_36_we; + reg_we_check[94] = dio_pad_attr_regwen_37_we; + reg_we_check[95] = dio_pad_attr_regwen_38_we; + reg_we_check[96] = dio_pad_attr_regwen_39_we; + reg_we_check[97] = dio_pad_attr_regwen_40_we; + reg_we_check[98] = dio_pad_attr_regwen_41_we; + reg_we_check[99] = dio_pad_attr_regwen_42_we; + reg_we_check[100] = dio_pad_attr_regwen_43_we; + reg_we_check[101] = dio_pad_attr_regwen_44_we; + reg_we_check[102] = dio_pad_attr_regwen_45_we; + reg_we_check[103] = dio_pad_attr_regwen_46_we; + reg_we_check[104] = dio_pad_attr_regwen_47_we; + reg_we_check[105] = dio_pad_attr_regwen_48_we; + reg_we_check[106] = dio_pad_attr_regwen_49_we; + reg_we_check[107] = dio_pad_attr_regwen_50_we; + reg_we_check[108] = dio_pad_attr_regwen_51_we; + reg_we_check[109] = dio_pad_attr_regwen_52_we; + reg_we_check[110] = dio_pad_attr_regwen_53_we; + reg_we_check[111] = dio_pad_attr_regwen_54_we; + reg_we_check[112] = dio_pad_attr_regwen_55_we; + reg_we_check[113] = dio_pad_attr_regwen_56_we; + reg_we_check[114] = dio_pad_attr_regwen_57_we; + reg_we_check[115] = dio_pad_attr_regwen_58_we; + reg_we_check[116] = dio_pad_attr_regwen_59_we; + reg_we_check[117] = dio_pad_attr_regwen_60_we; + reg_we_check[118] = dio_pad_attr_regwen_61_we; + reg_we_check[119] = dio_pad_attr_regwen_62_we; + reg_we_check[120] = dio_pad_attr_regwen_63_we; + reg_we_check[121] = dio_pad_attr_regwen_64_we; + reg_we_check[122] = dio_pad_attr_regwen_65_we; + reg_we_check[123] = dio_pad_attr_regwen_66_we; + reg_we_check[124] = dio_pad_attr_regwen_67_we; + reg_we_check[125] = dio_pad_attr_regwen_68_we; + reg_we_check[126] = dio_pad_attr_regwen_69_we; + reg_we_check[127] = dio_pad_attr_regwen_70_we; + reg_we_check[128] = dio_pad_attr_regwen_71_we; + reg_we_check[129] = dio_pad_attr_regwen_72_we; + reg_we_check[130] = dio_pad_attr_0_gated_we; + reg_we_check[131] = dio_pad_attr_1_gated_we; + reg_we_check[132] = dio_pad_attr_2_gated_we; + reg_we_check[133] = dio_pad_attr_3_gated_we; + reg_we_check[134] = dio_pad_attr_4_gated_we; + reg_we_check[135] = dio_pad_attr_5_gated_we; + reg_we_check[136] = dio_pad_attr_6_gated_we; + reg_we_check[137] = dio_pad_attr_7_gated_we; + reg_we_check[138] = dio_pad_attr_8_gated_we; + reg_we_check[139] = dio_pad_attr_9_gated_we; + reg_we_check[140] = dio_pad_attr_10_gated_we; + reg_we_check[141] = dio_pad_attr_11_gated_we; + reg_we_check[142] = dio_pad_attr_12_gated_we; + reg_we_check[143] = dio_pad_attr_13_gated_we; + reg_we_check[144] = dio_pad_attr_14_gated_we; + reg_we_check[145] = dio_pad_attr_15_gated_we; + reg_we_check[146] = dio_pad_attr_16_gated_we; + reg_we_check[147] = dio_pad_attr_17_gated_we; + reg_we_check[148] = dio_pad_attr_18_gated_we; + reg_we_check[149] = dio_pad_attr_19_gated_we; + reg_we_check[150] = dio_pad_attr_20_gated_we; + reg_we_check[151] = dio_pad_attr_21_gated_we; + reg_we_check[152] = dio_pad_attr_22_gated_we; + reg_we_check[153] = dio_pad_attr_23_gated_we; + reg_we_check[154] = dio_pad_attr_24_gated_we; + reg_we_check[155] = dio_pad_attr_25_gated_we; + reg_we_check[156] = dio_pad_attr_26_gated_we; + reg_we_check[157] = dio_pad_attr_27_gated_we; + reg_we_check[158] = dio_pad_attr_28_gated_we; + reg_we_check[159] = dio_pad_attr_29_gated_we; + reg_we_check[160] = dio_pad_attr_30_gated_we; + reg_we_check[161] = dio_pad_attr_31_gated_we; + reg_we_check[162] = dio_pad_attr_32_gated_we; + reg_we_check[163] = dio_pad_attr_33_gated_we; + reg_we_check[164] = dio_pad_attr_34_gated_we; + reg_we_check[165] = dio_pad_attr_35_gated_we; + reg_we_check[166] = dio_pad_attr_36_gated_we; + reg_we_check[167] = dio_pad_attr_37_gated_we; + reg_we_check[168] = dio_pad_attr_38_gated_we; + reg_we_check[169] = dio_pad_attr_39_gated_we; + reg_we_check[170] = dio_pad_attr_40_gated_we; + reg_we_check[171] = dio_pad_attr_41_gated_we; + reg_we_check[172] = dio_pad_attr_42_gated_we; + reg_we_check[173] = dio_pad_attr_43_gated_we; + reg_we_check[174] = dio_pad_attr_44_gated_we; + reg_we_check[175] = dio_pad_attr_45_gated_we; + reg_we_check[176] = dio_pad_attr_46_gated_we; + reg_we_check[177] = dio_pad_attr_47_gated_we; + reg_we_check[178] = dio_pad_attr_48_gated_we; + reg_we_check[179] = dio_pad_attr_49_gated_we; + reg_we_check[180] = dio_pad_attr_50_gated_we; + reg_we_check[181] = dio_pad_attr_51_gated_we; + reg_we_check[182] = dio_pad_attr_52_gated_we; + reg_we_check[183] = dio_pad_attr_53_gated_we; + reg_we_check[184] = dio_pad_attr_54_gated_we; + reg_we_check[185] = dio_pad_attr_55_gated_we; + reg_we_check[186] = dio_pad_attr_56_gated_we; + reg_we_check[187] = dio_pad_attr_57_gated_we; + reg_we_check[188] = dio_pad_attr_58_gated_we; + reg_we_check[189] = dio_pad_attr_59_gated_we; + reg_we_check[190] = dio_pad_attr_60_gated_we; + reg_we_check[191] = dio_pad_attr_61_gated_we; + reg_we_check[192] = dio_pad_attr_62_gated_we; + reg_we_check[193] = dio_pad_attr_63_gated_we; + reg_we_check[194] = dio_pad_attr_64_gated_we; + reg_we_check[195] = dio_pad_attr_65_gated_we; + reg_we_check[196] = dio_pad_attr_66_gated_we; + reg_we_check[197] = dio_pad_attr_67_gated_we; + reg_we_check[198] = dio_pad_attr_68_gated_we; + reg_we_check[199] = dio_pad_attr_69_gated_we; + reg_we_check[200] = dio_pad_attr_70_gated_we; + reg_we_check[201] = dio_pad_attr_71_gated_we; + reg_we_check[202] = dio_pad_attr_72_gated_we; + reg_we_check[203] = mio_pad_sleep_status_we; + reg_we_check[204] = mio_pad_sleep_regwen_0_we; + reg_we_check[205] = mio_pad_sleep_regwen_1_we; + reg_we_check[206] = mio_pad_sleep_regwen_2_we; + reg_we_check[207] = mio_pad_sleep_regwen_3_we; + reg_we_check[208] = mio_pad_sleep_regwen_4_we; + reg_we_check[209] = mio_pad_sleep_regwen_5_we; + reg_we_check[210] = mio_pad_sleep_regwen_6_we; + reg_we_check[211] = mio_pad_sleep_regwen_7_we; + reg_we_check[212] = mio_pad_sleep_regwen_8_we; + reg_we_check[213] = mio_pad_sleep_regwen_9_we; + reg_we_check[214] = mio_pad_sleep_regwen_10_we; + reg_we_check[215] = mio_pad_sleep_regwen_11_we; + reg_we_check[216] = mio_pad_sleep_en_0_gated_we; + reg_we_check[217] = mio_pad_sleep_en_1_gated_we; + reg_we_check[218] = mio_pad_sleep_en_2_gated_we; + reg_we_check[219] = mio_pad_sleep_en_3_gated_we; + reg_we_check[220] = mio_pad_sleep_en_4_gated_we; + reg_we_check[221] = mio_pad_sleep_en_5_gated_we; + reg_we_check[222] = mio_pad_sleep_en_6_gated_we; + reg_we_check[223] = mio_pad_sleep_en_7_gated_we; + reg_we_check[224] = mio_pad_sleep_en_8_gated_we; + reg_we_check[225] = mio_pad_sleep_en_9_gated_we; + reg_we_check[226] = mio_pad_sleep_en_10_gated_we; + reg_we_check[227] = mio_pad_sleep_en_11_gated_we; + reg_we_check[228] = mio_pad_sleep_mode_0_gated_we; + reg_we_check[229] = mio_pad_sleep_mode_1_gated_we; + reg_we_check[230] = mio_pad_sleep_mode_2_gated_we; + reg_we_check[231] = mio_pad_sleep_mode_3_gated_we; + reg_we_check[232] = mio_pad_sleep_mode_4_gated_we; + reg_we_check[233] = mio_pad_sleep_mode_5_gated_we; + reg_we_check[234] = mio_pad_sleep_mode_6_gated_we; + reg_we_check[235] = mio_pad_sleep_mode_7_gated_we; + reg_we_check[236] = mio_pad_sleep_mode_8_gated_we; + reg_we_check[237] = mio_pad_sleep_mode_9_gated_we; + reg_we_check[238] = mio_pad_sleep_mode_10_gated_we; + reg_we_check[239] = mio_pad_sleep_mode_11_gated_we; + reg_we_check[240] = dio_pad_sleep_status_0_we; + reg_we_check[241] = dio_pad_sleep_status_1_we; + reg_we_check[242] = dio_pad_sleep_status_2_we; + reg_we_check[243] = dio_pad_sleep_regwen_0_we; + reg_we_check[244] = dio_pad_sleep_regwen_1_we; + reg_we_check[245] = dio_pad_sleep_regwen_2_we; + reg_we_check[246] = dio_pad_sleep_regwen_3_we; + reg_we_check[247] = dio_pad_sleep_regwen_4_we; + reg_we_check[248] = dio_pad_sleep_regwen_5_we; + reg_we_check[249] = dio_pad_sleep_regwen_6_we; + reg_we_check[250] = dio_pad_sleep_regwen_7_we; + reg_we_check[251] = dio_pad_sleep_regwen_8_we; + reg_we_check[252] = dio_pad_sleep_regwen_9_we; + reg_we_check[253] = dio_pad_sleep_regwen_10_we; + reg_we_check[254] = dio_pad_sleep_regwen_11_we; + reg_we_check[255] = dio_pad_sleep_regwen_12_we; + reg_we_check[256] = dio_pad_sleep_regwen_13_we; + reg_we_check[257] = dio_pad_sleep_regwen_14_we; + reg_we_check[258] = dio_pad_sleep_regwen_15_we; + reg_we_check[259] = dio_pad_sleep_regwen_16_we; + reg_we_check[260] = dio_pad_sleep_regwen_17_we; + reg_we_check[261] = dio_pad_sleep_regwen_18_we; + reg_we_check[262] = dio_pad_sleep_regwen_19_we; + reg_we_check[263] = dio_pad_sleep_regwen_20_we; + reg_we_check[264] = dio_pad_sleep_regwen_21_we; + reg_we_check[265] = dio_pad_sleep_regwen_22_we; + reg_we_check[266] = dio_pad_sleep_regwen_23_we; + reg_we_check[267] = dio_pad_sleep_regwen_24_we; + reg_we_check[268] = dio_pad_sleep_regwen_25_we; + reg_we_check[269] = dio_pad_sleep_regwen_26_we; + reg_we_check[270] = dio_pad_sleep_regwen_27_we; + reg_we_check[271] = dio_pad_sleep_regwen_28_we; + reg_we_check[272] = dio_pad_sleep_regwen_29_we; + reg_we_check[273] = dio_pad_sleep_regwen_30_we; + reg_we_check[274] = dio_pad_sleep_regwen_31_we; + reg_we_check[275] = dio_pad_sleep_regwen_32_we; + reg_we_check[276] = dio_pad_sleep_regwen_33_we; + reg_we_check[277] = dio_pad_sleep_regwen_34_we; + reg_we_check[278] = dio_pad_sleep_regwen_35_we; + reg_we_check[279] = dio_pad_sleep_regwen_36_we; + reg_we_check[280] = dio_pad_sleep_regwen_37_we; + reg_we_check[281] = dio_pad_sleep_regwen_38_we; + reg_we_check[282] = dio_pad_sleep_regwen_39_we; + reg_we_check[283] = dio_pad_sleep_regwen_40_we; + reg_we_check[284] = dio_pad_sleep_regwen_41_we; + reg_we_check[285] = dio_pad_sleep_regwen_42_we; + reg_we_check[286] = dio_pad_sleep_regwen_43_we; + reg_we_check[287] = dio_pad_sleep_regwen_44_we; + reg_we_check[288] = dio_pad_sleep_regwen_45_we; + reg_we_check[289] = dio_pad_sleep_regwen_46_we; + reg_we_check[290] = dio_pad_sleep_regwen_47_we; + reg_we_check[291] = dio_pad_sleep_regwen_48_we; + reg_we_check[292] = dio_pad_sleep_regwen_49_we; + reg_we_check[293] = dio_pad_sleep_regwen_50_we; + reg_we_check[294] = dio_pad_sleep_regwen_51_we; + reg_we_check[295] = dio_pad_sleep_regwen_52_we; + reg_we_check[296] = dio_pad_sleep_regwen_53_we; + reg_we_check[297] = dio_pad_sleep_regwen_54_we; + reg_we_check[298] = dio_pad_sleep_regwen_55_we; + reg_we_check[299] = dio_pad_sleep_regwen_56_we; + reg_we_check[300] = dio_pad_sleep_regwen_57_we; + reg_we_check[301] = dio_pad_sleep_regwen_58_we; + reg_we_check[302] = dio_pad_sleep_regwen_59_we; + reg_we_check[303] = dio_pad_sleep_regwen_60_we; + reg_we_check[304] = dio_pad_sleep_regwen_61_we; + reg_we_check[305] = dio_pad_sleep_regwen_62_we; + reg_we_check[306] = dio_pad_sleep_regwen_63_we; + reg_we_check[307] = dio_pad_sleep_regwen_64_we; + reg_we_check[308] = dio_pad_sleep_regwen_65_we; + reg_we_check[309] = dio_pad_sleep_regwen_66_we; + reg_we_check[310] = dio_pad_sleep_regwen_67_we; + reg_we_check[311] = dio_pad_sleep_regwen_68_we; + reg_we_check[312] = dio_pad_sleep_regwen_69_we; + reg_we_check[313] = dio_pad_sleep_regwen_70_we; + reg_we_check[314] = dio_pad_sleep_regwen_71_we; + reg_we_check[315] = dio_pad_sleep_regwen_72_we; + reg_we_check[316] = dio_pad_sleep_en_0_gated_we; + reg_we_check[317] = dio_pad_sleep_en_1_gated_we; + reg_we_check[318] = dio_pad_sleep_en_2_gated_we; + reg_we_check[319] = dio_pad_sleep_en_3_gated_we; + reg_we_check[320] = dio_pad_sleep_en_4_gated_we; + reg_we_check[321] = dio_pad_sleep_en_5_gated_we; + reg_we_check[322] = dio_pad_sleep_en_6_gated_we; + reg_we_check[323] = dio_pad_sleep_en_7_gated_we; + reg_we_check[324] = dio_pad_sleep_en_8_gated_we; + reg_we_check[325] = dio_pad_sleep_en_9_gated_we; + reg_we_check[326] = dio_pad_sleep_en_10_gated_we; + reg_we_check[327] = dio_pad_sleep_en_11_gated_we; + reg_we_check[328] = dio_pad_sleep_en_12_gated_we; + reg_we_check[329] = dio_pad_sleep_en_13_gated_we; + reg_we_check[330] = dio_pad_sleep_en_14_gated_we; + reg_we_check[331] = dio_pad_sleep_en_15_gated_we; + reg_we_check[332] = dio_pad_sleep_en_16_gated_we; + reg_we_check[333] = dio_pad_sleep_en_17_gated_we; + reg_we_check[334] = dio_pad_sleep_en_18_gated_we; + reg_we_check[335] = dio_pad_sleep_en_19_gated_we; + reg_we_check[336] = dio_pad_sleep_en_20_gated_we; + reg_we_check[337] = dio_pad_sleep_en_21_gated_we; + reg_we_check[338] = dio_pad_sleep_en_22_gated_we; + reg_we_check[339] = dio_pad_sleep_en_23_gated_we; + reg_we_check[340] = dio_pad_sleep_en_24_gated_we; + reg_we_check[341] = dio_pad_sleep_en_25_gated_we; + reg_we_check[342] = dio_pad_sleep_en_26_gated_we; + reg_we_check[343] = dio_pad_sleep_en_27_gated_we; + reg_we_check[344] = dio_pad_sleep_en_28_gated_we; + reg_we_check[345] = dio_pad_sleep_en_29_gated_we; + reg_we_check[346] = dio_pad_sleep_en_30_gated_we; + reg_we_check[347] = dio_pad_sleep_en_31_gated_we; + reg_we_check[348] = dio_pad_sleep_en_32_gated_we; + reg_we_check[349] = dio_pad_sleep_en_33_gated_we; + reg_we_check[350] = dio_pad_sleep_en_34_gated_we; + reg_we_check[351] = dio_pad_sleep_en_35_gated_we; + reg_we_check[352] = dio_pad_sleep_en_36_gated_we; + reg_we_check[353] = dio_pad_sleep_en_37_gated_we; + reg_we_check[354] = dio_pad_sleep_en_38_gated_we; + reg_we_check[355] = dio_pad_sleep_en_39_gated_we; + reg_we_check[356] = dio_pad_sleep_en_40_gated_we; + reg_we_check[357] = dio_pad_sleep_en_41_gated_we; + reg_we_check[358] = dio_pad_sleep_en_42_gated_we; + reg_we_check[359] = dio_pad_sleep_en_43_gated_we; + reg_we_check[360] = dio_pad_sleep_en_44_gated_we; + reg_we_check[361] = dio_pad_sleep_en_45_gated_we; + reg_we_check[362] = dio_pad_sleep_en_46_gated_we; + reg_we_check[363] = dio_pad_sleep_en_47_gated_we; + reg_we_check[364] = dio_pad_sleep_en_48_gated_we; + reg_we_check[365] = dio_pad_sleep_en_49_gated_we; + reg_we_check[366] = dio_pad_sleep_en_50_gated_we; + reg_we_check[367] = dio_pad_sleep_en_51_gated_we; + reg_we_check[368] = dio_pad_sleep_en_52_gated_we; + reg_we_check[369] = dio_pad_sleep_en_53_gated_we; + reg_we_check[370] = dio_pad_sleep_en_54_gated_we; + reg_we_check[371] = dio_pad_sleep_en_55_gated_we; + reg_we_check[372] = dio_pad_sleep_en_56_gated_we; + reg_we_check[373] = dio_pad_sleep_en_57_gated_we; + reg_we_check[374] = dio_pad_sleep_en_58_gated_we; + reg_we_check[375] = dio_pad_sleep_en_59_gated_we; + reg_we_check[376] = dio_pad_sleep_en_60_gated_we; + reg_we_check[377] = dio_pad_sleep_en_61_gated_we; + reg_we_check[378] = dio_pad_sleep_en_62_gated_we; + reg_we_check[379] = dio_pad_sleep_en_63_gated_we; + reg_we_check[380] = dio_pad_sleep_en_64_gated_we; + reg_we_check[381] = dio_pad_sleep_en_65_gated_we; + reg_we_check[382] = dio_pad_sleep_en_66_gated_we; + reg_we_check[383] = dio_pad_sleep_en_67_gated_we; + reg_we_check[384] = dio_pad_sleep_en_68_gated_we; + reg_we_check[385] = dio_pad_sleep_en_69_gated_we; + reg_we_check[386] = dio_pad_sleep_en_70_gated_we; + reg_we_check[387] = dio_pad_sleep_en_71_gated_we; + reg_we_check[388] = dio_pad_sleep_en_72_gated_we; + reg_we_check[389] = dio_pad_sleep_mode_0_gated_we; + reg_we_check[390] = dio_pad_sleep_mode_1_gated_we; + reg_we_check[391] = dio_pad_sleep_mode_2_gated_we; + reg_we_check[392] = dio_pad_sleep_mode_3_gated_we; + reg_we_check[393] = dio_pad_sleep_mode_4_gated_we; + reg_we_check[394] = dio_pad_sleep_mode_5_gated_we; + reg_we_check[395] = dio_pad_sleep_mode_6_gated_we; + reg_we_check[396] = dio_pad_sleep_mode_7_gated_we; + reg_we_check[397] = dio_pad_sleep_mode_8_gated_we; + reg_we_check[398] = dio_pad_sleep_mode_9_gated_we; + reg_we_check[399] = dio_pad_sleep_mode_10_gated_we; + reg_we_check[400] = dio_pad_sleep_mode_11_gated_we; + reg_we_check[401] = dio_pad_sleep_mode_12_gated_we; + reg_we_check[402] = dio_pad_sleep_mode_13_gated_we; + reg_we_check[403] = dio_pad_sleep_mode_14_gated_we; + reg_we_check[404] = dio_pad_sleep_mode_15_gated_we; + reg_we_check[405] = dio_pad_sleep_mode_16_gated_we; + reg_we_check[406] = dio_pad_sleep_mode_17_gated_we; + reg_we_check[407] = dio_pad_sleep_mode_18_gated_we; + reg_we_check[408] = dio_pad_sleep_mode_19_gated_we; + reg_we_check[409] = dio_pad_sleep_mode_20_gated_we; + reg_we_check[410] = dio_pad_sleep_mode_21_gated_we; + reg_we_check[411] = dio_pad_sleep_mode_22_gated_we; + reg_we_check[412] = dio_pad_sleep_mode_23_gated_we; + reg_we_check[413] = dio_pad_sleep_mode_24_gated_we; + reg_we_check[414] = dio_pad_sleep_mode_25_gated_we; + reg_we_check[415] = dio_pad_sleep_mode_26_gated_we; + reg_we_check[416] = dio_pad_sleep_mode_27_gated_we; + reg_we_check[417] = dio_pad_sleep_mode_28_gated_we; + reg_we_check[418] = dio_pad_sleep_mode_29_gated_we; + reg_we_check[419] = dio_pad_sleep_mode_30_gated_we; + reg_we_check[420] = dio_pad_sleep_mode_31_gated_we; + reg_we_check[421] = dio_pad_sleep_mode_32_gated_we; + reg_we_check[422] = dio_pad_sleep_mode_33_gated_we; + reg_we_check[423] = dio_pad_sleep_mode_34_gated_we; + reg_we_check[424] = dio_pad_sleep_mode_35_gated_we; + reg_we_check[425] = dio_pad_sleep_mode_36_gated_we; + reg_we_check[426] = dio_pad_sleep_mode_37_gated_we; + reg_we_check[427] = dio_pad_sleep_mode_38_gated_we; + reg_we_check[428] = dio_pad_sleep_mode_39_gated_we; + reg_we_check[429] = dio_pad_sleep_mode_40_gated_we; + reg_we_check[430] = dio_pad_sleep_mode_41_gated_we; + reg_we_check[431] = dio_pad_sleep_mode_42_gated_we; + reg_we_check[432] = dio_pad_sleep_mode_43_gated_we; + reg_we_check[433] = dio_pad_sleep_mode_44_gated_we; + reg_we_check[434] = dio_pad_sleep_mode_45_gated_we; + reg_we_check[435] = dio_pad_sleep_mode_46_gated_we; + reg_we_check[436] = dio_pad_sleep_mode_47_gated_we; + reg_we_check[437] = dio_pad_sleep_mode_48_gated_we; + reg_we_check[438] = dio_pad_sleep_mode_49_gated_we; + reg_we_check[439] = dio_pad_sleep_mode_50_gated_we; + reg_we_check[440] = dio_pad_sleep_mode_51_gated_we; + reg_we_check[441] = dio_pad_sleep_mode_52_gated_we; + reg_we_check[442] = dio_pad_sleep_mode_53_gated_we; + reg_we_check[443] = dio_pad_sleep_mode_54_gated_we; + reg_we_check[444] = dio_pad_sleep_mode_55_gated_we; + reg_we_check[445] = dio_pad_sleep_mode_56_gated_we; + reg_we_check[446] = dio_pad_sleep_mode_57_gated_we; + reg_we_check[447] = dio_pad_sleep_mode_58_gated_we; + reg_we_check[448] = dio_pad_sleep_mode_59_gated_we; + reg_we_check[449] = dio_pad_sleep_mode_60_gated_we; + reg_we_check[450] = dio_pad_sleep_mode_61_gated_we; + reg_we_check[451] = dio_pad_sleep_mode_62_gated_we; + reg_we_check[452] = dio_pad_sleep_mode_63_gated_we; + reg_we_check[453] = dio_pad_sleep_mode_64_gated_we; + reg_we_check[454] = dio_pad_sleep_mode_65_gated_we; + reg_we_check[455] = dio_pad_sleep_mode_66_gated_we; + reg_we_check[456] = dio_pad_sleep_mode_67_gated_we; + reg_we_check[457] = dio_pad_sleep_mode_68_gated_we; + reg_we_check[458] = dio_pad_sleep_mode_69_gated_we; + reg_we_check[459] = dio_pad_sleep_mode_70_gated_we; + reg_we_check[460] = dio_pad_sleep_mode_71_gated_we; + reg_we_check[461] = dio_pad_sleep_mode_72_gated_we; + reg_we_check[462] = wkup_detector_regwen_0_we; + reg_we_check[463] = wkup_detector_regwen_1_we; + reg_we_check[464] = wkup_detector_regwen_2_we; + reg_we_check[465] = wkup_detector_regwen_3_we; + reg_we_check[466] = wkup_detector_regwen_4_we; + reg_we_check[467] = wkup_detector_regwen_5_we; + reg_we_check[468] = wkup_detector_regwen_6_we; + reg_we_check[469] = wkup_detector_regwen_7_we; + reg_we_check[470] = wkup_detector_en_0_we; + reg_we_check[471] = wkup_detector_en_1_we; + reg_we_check[472] = wkup_detector_en_2_we; + reg_we_check[473] = wkup_detector_en_3_we; + reg_we_check[474] = wkup_detector_en_4_we; + reg_we_check[475] = wkup_detector_en_5_we; + reg_we_check[476] = wkup_detector_en_6_we; + reg_we_check[477] = wkup_detector_en_7_we; + reg_we_check[478] = wkup_detector_0_we; + reg_we_check[479] = wkup_detector_1_we; + reg_we_check[480] = wkup_detector_2_we; + reg_we_check[481] = wkup_detector_3_we; + reg_we_check[482] = wkup_detector_4_we; + reg_we_check[483] = wkup_detector_5_we; + reg_we_check[484] = wkup_detector_6_we; + reg_we_check[485] = wkup_detector_7_we; + reg_we_check[486] = wkup_detector_cnt_th_0_we; + reg_we_check[487] = wkup_detector_cnt_th_1_we; + reg_we_check[488] = wkup_detector_cnt_th_2_we; + reg_we_check[489] = wkup_detector_cnt_th_3_we; + reg_we_check[490] = wkup_detector_cnt_th_4_we; + reg_we_check[491] = wkup_detector_cnt_th_5_we; + reg_we_check[492] = wkup_detector_cnt_th_6_we; + reg_we_check[493] = wkup_detector_cnt_th_7_we; + reg_we_check[494] = wkup_detector_padsel_0_gated_we; + reg_we_check[495] = wkup_detector_padsel_1_gated_we; + reg_we_check[496] = wkup_detector_padsel_2_gated_we; + reg_we_check[497] = wkup_detector_padsel_3_gated_we; + reg_we_check[498] = wkup_detector_padsel_4_gated_we; + reg_we_check[499] = wkup_detector_padsel_5_gated_we; + reg_we_check[500] = wkup_detector_padsel_6_gated_we; + reg_we_check[501] = wkup_detector_padsel_7_gated_we; + reg_we_check[502] = wkup_cause_we; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[1]: begin + reg_rdata_next[0] = mio_periph_insel_regwen_0_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = mio_periph_insel_regwen_1_qs; + end + + addr_hit[3]: begin + reg_rdata_next[0] = mio_periph_insel_regwen_2_qs; + end + + addr_hit[4]: begin + reg_rdata_next[0] = mio_periph_insel_regwen_3_qs; + end + + addr_hit[5]: begin + reg_rdata_next[3:0] = mio_periph_insel_0_qs; + end + + addr_hit[6]: begin + reg_rdata_next[3:0] = mio_periph_insel_1_qs; + end + + addr_hit[7]: begin + reg_rdata_next[3:0] = mio_periph_insel_2_qs; + end + + addr_hit[8]: begin + reg_rdata_next[3:0] = mio_periph_insel_3_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = mio_outsel_regwen_0_qs; + end + + addr_hit[10]: begin + reg_rdata_next[0] = mio_outsel_regwen_1_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = mio_outsel_regwen_2_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = mio_outsel_regwen_3_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = mio_outsel_regwen_4_qs; + end + + addr_hit[14]: begin + reg_rdata_next[0] = mio_outsel_regwen_5_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = mio_outsel_regwen_6_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = mio_outsel_regwen_7_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = mio_outsel_regwen_8_qs; + end + + addr_hit[18]: begin + reg_rdata_next[0] = mio_outsel_regwen_9_qs; + end + + addr_hit[19]: begin + reg_rdata_next[0] = mio_outsel_regwen_10_qs; + end + + addr_hit[20]: begin + reg_rdata_next[0] = mio_outsel_regwen_11_qs; + end + + addr_hit[21]: begin + reg_rdata_next[2:0] = mio_outsel_0_qs; + end + + addr_hit[22]: begin + reg_rdata_next[2:0] = mio_outsel_1_qs; + end + + addr_hit[23]: begin + reg_rdata_next[2:0] = mio_outsel_2_qs; + end + + addr_hit[24]: begin + reg_rdata_next[2:0] = mio_outsel_3_qs; + end + + addr_hit[25]: begin + reg_rdata_next[2:0] = mio_outsel_4_qs; + end + + addr_hit[26]: begin + reg_rdata_next[2:0] = mio_outsel_5_qs; + end + + addr_hit[27]: begin + reg_rdata_next[2:0] = mio_outsel_6_qs; + end + + addr_hit[28]: begin + reg_rdata_next[2:0] = mio_outsel_7_qs; + end + + addr_hit[29]: begin + reg_rdata_next[2:0] = mio_outsel_8_qs; + end + + addr_hit[30]: begin + reg_rdata_next[2:0] = mio_outsel_9_qs; + end + + addr_hit[31]: begin + reg_rdata_next[2:0] = mio_outsel_10_qs; + end + + addr_hit[32]: begin + reg_rdata_next[2:0] = mio_outsel_11_qs; + end + + addr_hit[33]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_0_qs; + end + + addr_hit[34]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_1_qs; + end + + addr_hit[35]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_2_qs; + end + + addr_hit[36]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_3_qs; + end + + addr_hit[37]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_4_qs; + end + + addr_hit[38]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_5_qs; + end + + addr_hit[39]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_6_qs; + end + + addr_hit[40]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_7_qs; + end + + addr_hit[41]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_8_qs; + end + + addr_hit[42]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_9_qs; + end + + addr_hit[43]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_10_qs; + end + + addr_hit[44]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_11_qs; + end + + addr_hit[45]: begin + reg_rdata_next[0] = mio_pad_attr_0_invert_0_qs; + reg_rdata_next[1] = mio_pad_attr_0_virtual_od_en_0_qs; + reg_rdata_next[2] = mio_pad_attr_0_pull_en_0_qs; + reg_rdata_next[3] = mio_pad_attr_0_pull_select_0_qs; + reg_rdata_next[4] = mio_pad_attr_0_keeper_en_0_qs; + reg_rdata_next[5] = mio_pad_attr_0_schmitt_en_0_qs; + reg_rdata_next[6] = mio_pad_attr_0_od_en_0_qs; + reg_rdata_next[7] = mio_pad_attr_0_input_disable_0_qs; + reg_rdata_next[17:16] = mio_pad_attr_0_slew_rate_0_qs; + reg_rdata_next[23:20] = mio_pad_attr_0_drive_strength_0_qs; + end + + addr_hit[46]: begin + reg_rdata_next[0] = mio_pad_attr_1_invert_1_qs; + reg_rdata_next[1] = mio_pad_attr_1_virtual_od_en_1_qs; + reg_rdata_next[2] = mio_pad_attr_1_pull_en_1_qs; + reg_rdata_next[3] = mio_pad_attr_1_pull_select_1_qs; + reg_rdata_next[4] = mio_pad_attr_1_keeper_en_1_qs; + reg_rdata_next[5] = mio_pad_attr_1_schmitt_en_1_qs; + reg_rdata_next[6] = mio_pad_attr_1_od_en_1_qs; + reg_rdata_next[7] = mio_pad_attr_1_input_disable_1_qs; + reg_rdata_next[17:16] = mio_pad_attr_1_slew_rate_1_qs; + reg_rdata_next[23:20] = mio_pad_attr_1_drive_strength_1_qs; + end + + addr_hit[47]: begin + reg_rdata_next[0] = mio_pad_attr_2_invert_2_qs; + reg_rdata_next[1] = mio_pad_attr_2_virtual_od_en_2_qs; + reg_rdata_next[2] = mio_pad_attr_2_pull_en_2_qs; + reg_rdata_next[3] = mio_pad_attr_2_pull_select_2_qs; + reg_rdata_next[4] = mio_pad_attr_2_keeper_en_2_qs; + reg_rdata_next[5] = mio_pad_attr_2_schmitt_en_2_qs; + reg_rdata_next[6] = mio_pad_attr_2_od_en_2_qs; + reg_rdata_next[7] = mio_pad_attr_2_input_disable_2_qs; + reg_rdata_next[17:16] = mio_pad_attr_2_slew_rate_2_qs; + reg_rdata_next[23:20] = mio_pad_attr_2_drive_strength_2_qs; + end + + addr_hit[48]: begin + reg_rdata_next[0] = mio_pad_attr_3_invert_3_qs; + reg_rdata_next[1] = mio_pad_attr_3_virtual_od_en_3_qs; + reg_rdata_next[2] = mio_pad_attr_3_pull_en_3_qs; + reg_rdata_next[3] = mio_pad_attr_3_pull_select_3_qs; + reg_rdata_next[4] = mio_pad_attr_3_keeper_en_3_qs; + reg_rdata_next[5] = mio_pad_attr_3_schmitt_en_3_qs; + reg_rdata_next[6] = mio_pad_attr_3_od_en_3_qs; + reg_rdata_next[7] = mio_pad_attr_3_input_disable_3_qs; + reg_rdata_next[17:16] = mio_pad_attr_3_slew_rate_3_qs; + reg_rdata_next[23:20] = mio_pad_attr_3_drive_strength_3_qs; + end + + addr_hit[49]: begin + reg_rdata_next[0] = mio_pad_attr_4_invert_4_qs; + reg_rdata_next[1] = mio_pad_attr_4_virtual_od_en_4_qs; + reg_rdata_next[2] = mio_pad_attr_4_pull_en_4_qs; + reg_rdata_next[3] = mio_pad_attr_4_pull_select_4_qs; + reg_rdata_next[4] = mio_pad_attr_4_keeper_en_4_qs; + reg_rdata_next[5] = mio_pad_attr_4_schmitt_en_4_qs; + reg_rdata_next[6] = mio_pad_attr_4_od_en_4_qs; + reg_rdata_next[7] = mio_pad_attr_4_input_disable_4_qs; + reg_rdata_next[17:16] = mio_pad_attr_4_slew_rate_4_qs; + reg_rdata_next[23:20] = mio_pad_attr_4_drive_strength_4_qs; + end + + addr_hit[50]: begin + reg_rdata_next[0] = mio_pad_attr_5_invert_5_qs; + reg_rdata_next[1] = mio_pad_attr_5_virtual_od_en_5_qs; + reg_rdata_next[2] = mio_pad_attr_5_pull_en_5_qs; + reg_rdata_next[3] = mio_pad_attr_5_pull_select_5_qs; + reg_rdata_next[4] = mio_pad_attr_5_keeper_en_5_qs; + reg_rdata_next[5] = mio_pad_attr_5_schmitt_en_5_qs; + reg_rdata_next[6] = mio_pad_attr_5_od_en_5_qs; + reg_rdata_next[7] = mio_pad_attr_5_input_disable_5_qs; + reg_rdata_next[17:16] = mio_pad_attr_5_slew_rate_5_qs; + reg_rdata_next[23:20] = mio_pad_attr_5_drive_strength_5_qs; + end + + addr_hit[51]: begin + reg_rdata_next[0] = mio_pad_attr_6_invert_6_qs; + reg_rdata_next[1] = mio_pad_attr_6_virtual_od_en_6_qs; + reg_rdata_next[2] = mio_pad_attr_6_pull_en_6_qs; + reg_rdata_next[3] = mio_pad_attr_6_pull_select_6_qs; + reg_rdata_next[4] = mio_pad_attr_6_keeper_en_6_qs; + reg_rdata_next[5] = mio_pad_attr_6_schmitt_en_6_qs; + reg_rdata_next[6] = mio_pad_attr_6_od_en_6_qs; + reg_rdata_next[7] = mio_pad_attr_6_input_disable_6_qs; + reg_rdata_next[17:16] = mio_pad_attr_6_slew_rate_6_qs; + reg_rdata_next[23:20] = mio_pad_attr_6_drive_strength_6_qs; + end + + addr_hit[52]: begin + reg_rdata_next[0] = mio_pad_attr_7_invert_7_qs; + reg_rdata_next[1] = mio_pad_attr_7_virtual_od_en_7_qs; + reg_rdata_next[2] = mio_pad_attr_7_pull_en_7_qs; + reg_rdata_next[3] = mio_pad_attr_7_pull_select_7_qs; + reg_rdata_next[4] = mio_pad_attr_7_keeper_en_7_qs; + reg_rdata_next[5] = mio_pad_attr_7_schmitt_en_7_qs; + reg_rdata_next[6] = mio_pad_attr_7_od_en_7_qs; + reg_rdata_next[7] = mio_pad_attr_7_input_disable_7_qs; + reg_rdata_next[17:16] = mio_pad_attr_7_slew_rate_7_qs; + reg_rdata_next[23:20] = mio_pad_attr_7_drive_strength_7_qs; + end + + addr_hit[53]: begin + reg_rdata_next[0] = mio_pad_attr_8_invert_8_qs; + reg_rdata_next[1] = mio_pad_attr_8_virtual_od_en_8_qs; + reg_rdata_next[2] = mio_pad_attr_8_pull_en_8_qs; + reg_rdata_next[3] = mio_pad_attr_8_pull_select_8_qs; + reg_rdata_next[4] = mio_pad_attr_8_keeper_en_8_qs; + reg_rdata_next[5] = mio_pad_attr_8_schmitt_en_8_qs; + reg_rdata_next[6] = mio_pad_attr_8_od_en_8_qs; + reg_rdata_next[7] = mio_pad_attr_8_input_disable_8_qs; + reg_rdata_next[17:16] = mio_pad_attr_8_slew_rate_8_qs; + reg_rdata_next[23:20] = mio_pad_attr_8_drive_strength_8_qs; + end + + addr_hit[54]: begin + reg_rdata_next[0] = mio_pad_attr_9_invert_9_qs; + reg_rdata_next[1] = mio_pad_attr_9_virtual_od_en_9_qs; + reg_rdata_next[2] = mio_pad_attr_9_pull_en_9_qs; + reg_rdata_next[3] = mio_pad_attr_9_pull_select_9_qs; + reg_rdata_next[4] = mio_pad_attr_9_keeper_en_9_qs; + reg_rdata_next[5] = mio_pad_attr_9_schmitt_en_9_qs; + reg_rdata_next[6] = mio_pad_attr_9_od_en_9_qs; + reg_rdata_next[7] = mio_pad_attr_9_input_disable_9_qs; + reg_rdata_next[17:16] = mio_pad_attr_9_slew_rate_9_qs; + reg_rdata_next[23:20] = mio_pad_attr_9_drive_strength_9_qs; + end + + addr_hit[55]: begin + reg_rdata_next[0] = mio_pad_attr_10_invert_10_qs; + reg_rdata_next[1] = mio_pad_attr_10_virtual_od_en_10_qs; + reg_rdata_next[2] = mio_pad_attr_10_pull_en_10_qs; + reg_rdata_next[3] = mio_pad_attr_10_pull_select_10_qs; + reg_rdata_next[4] = mio_pad_attr_10_keeper_en_10_qs; + reg_rdata_next[5] = mio_pad_attr_10_schmitt_en_10_qs; + reg_rdata_next[6] = mio_pad_attr_10_od_en_10_qs; + reg_rdata_next[7] = mio_pad_attr_10_input_disable_10_qs; + reg_rdata_next[17:16] = mio_pad_attr_10_slew_rate_10_qs; + reg_rdata_next[23:20] = mio_pad_attr_10_drive_strength_10_qs; + end + + addr_hit[56]: begin + reg_rdata_next[0] = mio_pad_attr_11_invert_11_qs; + reg_rdata_next[1] = mio_pad_attr_11_virtual_od_en_11_qs; + reg_rdata_next[2] = mio_pad_attr_11_pull_en_11_qs; + reg_rdata_next[3] = mio_pad_attr_11_pull_select_11_qs; + reg_rdata_next[4] = mio_pad_attr_11_keeper_en_11_qs; + reg_rdata_next[5] = mio_pad_attr_11_schmitt_en_11_qs; + reg_rdata_next[6] = mio_pad_attr_11_od_en_11_qs; + reg_rdata_next[7] = mio_pad_attr_11_input_disable_11_qs; + reg_rdata_next[17:16] = mio_pad_attr_11_slew_rate_11_qs; + reg_rdata_next[23:20] = mio_pad_attr_11_drive_strength_11_qs; + end + + addr_hit[57]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_0_qs; + end + + addr_hit[58]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_1_qs; + end + + addr_hit[59]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_2_qs; + end + + addr_hit[60]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_3_qs; + end + + addr_hit[61]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_4_qs; + end + + addr_hit[62]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_5_qs; + end + + addr_hit[63]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_6_qs; + end + + addr_hit[64]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_7_qs; + end + + addr_hit[65]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_8_qs; + end + + addr_hit[66]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_9_qs; + end + + addr_hit[67]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_10_qs; + end + + addr_hit[68]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_11_qs; + end + + addr_hit[69]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_12_qs; + end + + addr_hit[70]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_13_qs; + end + + addr_hit[71]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_14_qs; + end + + addr_hit[72]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_15_qs; + end + + addr_hit[73]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_16_qs; + end + + addr_hit[74]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_17_qs; + end + + addr_hit[75]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_18_qs; + end + + addr_hit[76]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_19_qs; + end + + addr_hit[77]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_20_qs; + end + + addr_hit[78]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_21_qs; + end + + addr_hit[79]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_22_qs; + end + + addr_hit[80]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_23_qs; + end + + addr_hit[81]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_24_qs; + end + + addr_hit[82]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_25_qs; + end + + addr_hit[83]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_26_qs; + end + + addr_hit[84]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_27_qs; + end + + addr_hit[85]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_28_qs; + end + + addr_hit[86]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_29_qs; + end + + addr_hit[87]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_30_qs; + end + + addr_hit[88]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_31_qs; + end + + addr_hit[89]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_32_qs; + end + + addr_hit[90]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_33_qs; + end + + addr_hit[91]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_34_qs; + end + + addr_hit[92]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_35_qs; + end + + addr_hit[93]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_36_qs; + end + + addr_hit[94]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_37_qs; + end + + addr_hit[95]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_38_qs; + end + + addr_hit[96]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_39_qs; + end + + addr_hit[97]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_40_qs; + end + + addr_hit[98]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_41_qs; + end + + addr_hit[99]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_42_qs; + end + + addr_hit[100]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_43_qs; + end + + addr_hit[101]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_44_qs; + end + + addr_hit[102]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_45_qs; + end + + addr_hit[103]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_46_qs; + end + + addr_hit[104]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_47_qs; + end + + addr_hit[105]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_48_qs; + end + + addr_hit[106]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_49_qs; + end + + addr_hit[107]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_50_qs; + end + + addr_hit[108]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_51_qs; + end + + addr_hit[109]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_52_qs; + end + + addr_hit[110]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_53_qs; + end + + addr_hit[111]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_54_qs; + end + + addr_hit[112]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_55_qs; + end + + addr_hit[113]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_56_qs; + end + + addr_hit[114]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_57_qs; + end + + addr_hit[115]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_58_qs; + end + + addr_hit[116]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_59_qs; + end + + addr_hit[117]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_60_qs; + end + + addr_hit[118]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_61_qs; + end + + addr_hit[119]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_62_qs; + end + + addr_hit[120]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_63_qs; + end + + addr_hit[121]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_64_qs; + end + + addr_hit[122]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_65_qs; + end + + addr_hit[123]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_66_qs; + end + + addr_hit[124]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_67_qs; + end + + addr_hit[125]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_68_qs; + end + + addr_hit[126]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_69_qs; + end + + addr_hit[127]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_70_qs; + end + + addr_hit[128]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_71_qs; + end + + addr_hit[129]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_72_qs; + end + + addr_hit[130]: begin + reg_rdata_next[0] = dio_pad_attr_0_invert_0_qs; + reg_rdata_next[1] = dio_pad_attr_0_virtual_od_en_0_qs; + reg_rdata_next[2] = dio_pad_attr_0_pull_en_0_qs; + reg_rdata_next[3] = dio_pad_attr_0_pull_select_0_qs; + reg_rdata_next[4] = dio_pad_attr_0_keeper_en_0_qs; + reg_rdata_next[5] = dio_pad_attr_0_schmitt_en_0_qs; + reg_rdata_next[6] = dio_pad_attr_0_od_en_0_qs; + reg_rdata_next[7] = dio_pad_attr_0_input_disable_0_qs; + reg_rdata_next[17:16] = dio_pad_attr_0_slew_rate_0_qs; + reg_rdata_next[23:20] = dio_pad_attr_0_drive_strength_0_qs; + end + + addr_hit[131]: begin + reg_rdata_next[0] = dio_pad_attr_1_invert_1_qs; + reg_rdata_next[1] = dio_pad_attr_1_virtual_od_en_1_qs; + reg_rdata_next[2] = dio_pad_attr_1_pull_en_1_qs; + reg_rdata_next[3] = dio_pad_attr_1_pull_select_1_qs; + reg_rdata_next[4] = dio_pad_attr_1_keeper_en_1_qs; + reg_rdata_next[5] = dio_pad_attr_1_schmitt_en_1_qs; + reg_rdata_next[6] = dio_pad_attr_1_od_en_1_qs; + reg_rdata_next[7] = dio_pad_attr_1_input_disable_1_qs; + reg_rdata_next[17:16] = dio_pad_attr_1_slew_rate_1_qs; + reg_rdata_next[23:20] = dio_pad_attr_1_drive_strength_1_qs; + end + + addr_hit[132]: begin + reg_rdata_next[0] = dio_pad_attr_2_invert_2_qs; + reg_rdata_next[1] = dio_pad_attr_2_virtual_od_en_2_qs; + reg_rdata_next[2] = dio_pad_attr_2_pull_en_2_qs; + reg_rdata_next[3] = dio_pad_attr_2_pull_select_2_qs; + reg_rdata_next[4] = dio_pad_attr_2_keeper_en_2_qs; + reg_rdata_next[5] = dio_pad_attr_2_schmitt_en_2_qs; + reg_rdata_next[6] = dio_pad_attr_2_od_en_2_qs; + reg_rdata_next[7] = dio_pad_attr_2_input_disable_2_qs; + reg_rdata_next[17:16] = dio_pad_attr_2_slew_rate_2_qs; + reg_rdata_next[23:20] = dio_pad_attr_2_drive_strength_2_qs; + end + + addr_hit[133]: begin + reg_rdata_next[0] = dio_pad_attr_3_invert_3_qs; + reg_rdata_next[1] = dio_pad_attr_3_virtual_od_en_3_qs; + reg_rdata_next[2] = dio_pad_attr_3_pull_en_3_qs; + reg_rdata_next[3] = dio_pad_attr_3_pull_select_3_qs; + reg_rdata_next[4] = dio_pad_attr_3_keeper_en_3_qs; + reg_rdata_next[5] = dio_pad_attr_3_schmitt_en_3_qs; + reg_rdata_next[6] = dio_pad_attr_3_od_en_3_qs; + reg_rdata_next[7] = dio_pad_attr_3_input_disable_3_qs; + reg_rdata_next[17:16] = dio_pad_attr_3_slew_rate_3_qs; + reg_rdata_next[23:20] = dio_pad_attr_3_drive_strength_3_qs; + end + + addr_hit[134]: begin + reg_rdata_next[0] = dio_pad_attr_4_invert_4_qs; + reg_rdata_next[1] = dio_pad_attr_4_virtual_od_en_4_qs; + reg_rdata_next[2] = dio_pad_attr_4_pull_en_4_qs; + reg_rdata_next[3] = dio_pad_attr_4_pull_select_4_qs; + reg_rdata_next[4] = dio_pad_attr_4_keeper_en_4_qs; + reg_rdata_next[5] = dio_pad_attr_4_schmitt_en_4_qs; + reg_rdata_next[6] = dio_pad_attr_4_od_en_4_qs; + reg_rdata_next[7] = dio_pad_attr_4_input_disable_4_qs; + reg_rdata_next[17:16] = dio_pad_attr_4_slew_rate_4_qs; + reg_rdata_next[23:20] = dio_pad_attr_4_drive_strength_4_qs; + end + + addr_hit[135]: begin + reg_rdata_next[0] = dio_pad_attr_5_invert_5_qs; + reg_rdata_next[1] = dio_pad_attr_5_virtual_od_en_5_qs; + reg_rdata_next[2] = dio_pad_attr_5_pull_en_5_qs; + reg_rdata_next[3] = dio_pad_attr_5_pull_select_5_qs; + reg_rdata_next[4] = dio_pad_attr_5_keeper_en_5_qs; + reg_rdata_next[5] = dio_pad_attr_5_schmitt_en_5_qs; + reg_rdata_next[6] = dio_pad_attr_5_od_en_5_qs; + reg_rdata_next[7] = dio_pad_attr_5_input_disable_5_qs; + reg_rdata_next[17:16] = dio_pad_attr_5_slew_rate_5_qs; + reg_rdata_next[23:20] = dio_pad_attr_5_drive_strength_5_qs; + end + + addr_hit[136]: begin + reg_rdata_next[0] = dio_pad_attr_6_invert_6_qs; + reg_rdata_next[1] = dio_pad_attr_6_virtual_od_en_6_qs; + reg_rdata_next[2] = dio_pad_attr_6_pull_en_6_qs; + reg_rdata_next[3] = dio_pad_attr_6_pull_select_6_qs; + reg_rdata_next[4] = dio_pad_attr_6_keeper_en_6_qs; + reg_rdata_next[5] = dio_pad_attr_6_schmitt_en_6_qs; + reg_rdata_next[6] = dio_pad_attr_6_od_en_6_qs; + reg_rdata_next[7] = dio_pad_attr_6_input_disable_6_qs; + reg_rdata_next[17:16] = dio_pad_attr_6_slew_rate_6_qs; + reg_rdata_next[23:20] = dio_pad_attr_6_drive_strength_6_qs; + end + + addr_hit[137]: begin + reg_rdata_next[0] = dio_pad_attr_7_invert_7_qs; + reg_rdata_next[1] = dio_pad_attr_7_virtual_od_en_7_qs; + reg_rdata_next[2] = dio_pad_attr_7_pull_en_7_qs; + reg_rdata_next[3] = dio_pad_attr_7_pull_select_7_qs; + reg_rdata_next[4] = dio_pad_attr_7_keeper_en_7_qs; + reg_rdata_next[5] = dio_pad_attr_7_schmitt_en_7_qs; + reg_rdata_next[6] = dio_pad_attr_7_od_en_7_qs; + reg_rdata_next[7] = dio_pad_attr_7_input_disable_7_qs; + reg_rdata_next[17:16] = dio_pad_attr_7_slew_rate_7_qs; + reg_rdata_next[23:20] = dio_pad_attr_7_drive_strength_7_qs; + end + + addr_hit[138]: begin + reg_rdata_next[0] = dio_pad_attr_8_invert_8_qs; + reg_rdata_next[1] = dio_pad_attr_8_virtual_od_en_8_qs; + reg_rdata_next[2] = dio_pad_attr_8_pull_en_8_qs; + reg_rdata_next[3] = dio_pad_attr_8_pull_select_8_qs; + reg_rdata_next[4] = dio_pad_attr_8_keeper_en_8_qs; + reg_rdata_next[5] = dio_pad_attr_8_schmitt_en_8_qs; + reg_rdata_next[6] = dio_pad_attr_8_od_en_8_qs; + reg_rdata_next[7] = dio_pad_attr_8_input_disable_8_qs; + reg_rdata_next[17:16] = dio_pad_attr_8_slew_rate_8_qs; + reg_rdata_next[23:20] = dio_pad_attr_8_drive_strength_8_qs; + end + + addr_hit[139]: begin + reg_rdata_next[0] = dio_pad_attr_9_invert_9_qs; + reg_rdata_next[1] = dio_pad_attr_9_virtual_od_en_9_qs; + reg_rdata_next[2] = dio_pad_attr_9_pull_en_9_qs; + reg_rdata_next[3] = dio_pad_attr_9_pull_select_9_qs; + reg_rdata_next[4] = dio_pad_attr_9_keeper_en_9_qs; + reg_rdata_next[5] = dio_pad_attr_9_schmitt_en_9_qs; + reg_rdata_next[6] = dio_pad_attr_9_od_en_9_qs; + reg_rdata_next[7] = dio_pad_attr_9_input_disable_9_qs; + reg_rdata_next[17:16] = dio_pad_attr_9_slew_rate_9_qs; + reg_rdata_next[23:20] = dio_pad_attr_9_drive_strength_9_qs; + end + + addr_hit[140]: begin + reg_rdata_next[0] = dio_pad_attr_10_invert_10_qs; + reg_rdata_next[1] = dio_pad_attr_10_virtual_od_en_10_qs; + reg_rdata_next[2] = dio_pad_attr_10_pull_en_10_qs; + reg_rdata_next[3] = dio_pad_attr_10_pull_select_10_qs; + reg_rdata_next[4] = dio_pad_attr_10_keeper_en_10_qs; + reg_rdata_next[5] = dio_pad_attr_10_schmitt_en_10_qs; + reg_rdata_next[6] = dio_pad_attr_10_od_en_10_qs; + reg_rdata_next[7] = dio_pad_attr_10_input_disable_10_qs; + reg_rdata_next[17:16] = dio_pad_attr_10_slew_rate_10_qs; + reg_rdata_next[23:20] = dio_pad_attr_10_drive_strength_10_qs; + end + + addr_hit[141]: begin + reg_rdata_next[0] = dio_pad_attr_11_invert_11_qs; + reg_rdata_next[1] = dio_pad_attr_11_virtual_od_en_11_qs; + reg_rdata_next[2] = dio_pad_attr_11_pull_en_11_qs; + reg_rdata_next[3] = dio_pad_attr_11_pull_select_11_qs; + reg_rdata_next[4] = dio_pad_attr_11_keeper_en_11_qs; + reg_rdata_next[5] = dio_pad_attr_11_schmitt_en_11_qs; + reg_rdata_next[6] = dio_pad_attr_11_od_en_11_qs; + reg_rdata_next[7] = dio_pad_attr_11_input_disable_11_qs; + reg_rdata_next[17:16] = dio_pad_attr_11_slew_rate_11_qs; + reg_rdata_next[23:20] = dio_pad_attr_11_drive_strength_11_qs; + end + + addr_hit[142]: begin + reg_rdata_next[0] = dio_pad_attr_12_invert_12_qs; + reg_rdata_next[1] = dio_pad_attr_12_virtual_od_en_12_qs; + reg_rdata_next[2] = dio_pad_attr_12_pull_en_12_qs; + reg_rdata_next[3] = dio_pad_attr_12_pull_select_12_qs; + reg_rdata_next[4] = dio_pad_attr_12_keeper_en_12_qs; + reg_rdata_next[5] = dio_pad_attr_12_schmitt_en_12_qs; + reg_rdata_next[6] = dio_pad_attr_12_od_en_12_qs; + reg_rdata_next[7] = dio_pad_attr_12_input_disable_12_qs; + reg_rdata_next[17:16] = dio_pad_attr_12_slew_rate_12_qs; + reg_rdata_next[23:20] = dio_pad_attr_12_drive_strength_12_qs; + end + + addr_hit[143]: begin + reg_rdata_next[0] = dio_pad_attr_13_invert_13_qs; + reg_rdata_next[1] = dio_pad_attr_13_virtual_od_en_13_qs; + reg_rdata_next[2] = dio_pad_attr_13_pull_en_13_qs; + reg_rdata_next[3] = dio_pad_attr_13_pull_select_13_qs; + reg_rdata_next[4] = dio_pad_attr_13_keeper_en_13_qs; + reg_rdata_next[5] = dio_pad_attr_13_schmitt_en_13_qs; + reg_rdata_next[6] = dio_pad_attr_13_od_en_13_qs; + reg_rdata_next[7] = dio_pad_attr_13_input_disable_13_qs; + reg_rdata_next[17:16] = dio_pad_attr_13_slew_rate_13_qs; + reg_rdata_next[23:20] = dio_pad_attr_13_drive_strength_13_qs; + end + + addr_hit[144]: begin + reg_rdata_next[0] = dio_pad_attr_14_invert_14_qs; + reg_rdata_next[1] = dio_pad_attr_14_virtual_od_en_14_qs; + reg_rdata_next[2] = dio_pad_attr_14_pull_en_14_qs; + reg_rdata_next[3] = dio_pad_attr_14_pull_select_14_qs; + reg_rdata_next[4] = dio_pad_attr_14_keeper_en_14_qs; + reg_rdata_next[5] = dio_pad_attr_14_schmitt_en_14_qs; + reg_rdata_next[6] = dio_pad_attr_14_od_en_14_qs; + reg_rdata_next[7] = dio_pad_attr_14_input_disable_14_qs; + reg_rdata_next[17:16] = dio_pad_attr_14_slew_rate_14_qs; + reg_rdata_next[23:20] = dio_pad_attr_14_drive_strength_14_qs; + end + + addr_hit[145]: begin + reg_rdata_next[0] = dio_pad_attr_15_invert_15_qs; + reg_rdata_next[1] = dio_pad_attr_15_virtual_od_en_15_qs; + reg_rdata_next[2] = dio_pad_attr_15_pull_en_15_qs; + reg_rdata_next[3] = dio_pad_attr_15_pull_select_15_qs; + reg_rdata_next[4] = dio_pad_attr_15_keeper_en_15_qs; + reg_rdata_next[5] = dio_pad_attr_15_schmitt_en_15_qs; + reg_rdata_next[6] = dio_pad_attr_15_od_en_15_qs; + reg_rdata_next[7] = dio_pad_attr_15_input_disable_15_qs; + reg_rdata_next[17:16] = dio_pad_attr_15_slew_rate_15_qs; + reg_rdata_next[23:20] = dio_pad_attr_15_drive_strength_15_qs; + end + + addr_hit[146]: begin + reg_rdata_next[0] = dio_pad_attr_16_invert_16_qs; + reg_rdata_next[1] = dio_pad_attr_16_virtual_od_en_16_qs; + reg_rdata_next[2] = dio_pad_attr_16_pull_en_16_qs; + reg_rdata_next[3] = dio_pad_attr_16_pull_select_16_qs; + reg_rdata_next[4] = dio_pad_attr_16_keeper_en_16_qs; + reg_rdata_next[5] = dio_pad_attr_16_schmitt_en_16_qs; + reg_rdata_next[6] = dio_pad_attr_16_od_en_16_qs; + reg_rdata_next[7] = dio_pad_attr_16_input_disable_16_qs; + reg_rdata_next[17:16] = dio_pad_attr_16_slew_rate_16_qs; + reg_rdata_next[23:20] = dio_pad_attr_16_drive_strength_16_qs; + end + + addr_hit[147]: begin + reg_rdata_next[0] = dio_pad_attr_17_invert_17_qs; + reg_rdata_next[1] = dio_pad_attr_17_virtual_od_en_17_qs; + reg_rdata_next[2] = dio_pad_attr_17_pull_en_17_qs; + reg_rdata_next[3] = dio_pad_attr_17_pull_select_17_qs; + reg_rdata_next[4] = dio_pad_attr_17_keeper_en_17_qs; + reg_rdata_next[5] = dio_pad_attr_17_schmitt_en_17_qs; + reg_rdata_next[6] = dio_pad_attr_17_od_en_17_qs; + reg_rdata_next[7] = dio_pad_attr_17_input_disable_17_qs; + reg_rdata_next[17:16] = dio_pad_attr_17_slew_rate_17_qs; + reg_rdata_next[23:20] = dio_pad_attr_17_drive_strength_17_qs; + end + + addr_hit[148]: begin + reg_rdata_next[0] = dio_pad_attr_18_invert_18_qs; + reg_rdata_next[1] = dio_pad_attr_18_virtual_od_en_18_qs; + reg_rdata_next[2] = dio_pad_attr_18_pull_en_18_qs; + reg_rdata_next[3] = dio_pad_attr_18_pull_select_18_qs; + reg_rdata_next[4] = dio_pad_attr_18_keeper_en_18_qs; + reg_rdata_next[5] = dio_pad_attr_18_schmitt_en_18_qs; + reg_rdata_next[6] = dio_pad_attr_18_od_en_18_qs; + reg_rdata_next[7] = dio_pad_attr_18_input_disable_18_qs; + reg_rdata_next[17:16] = dio_pad_attr_18_slew_rate_18_qs; + reg_rdata_next[23:20] = dio_pad_attr_18_drive_strength_18_qs; + end + + addr_hit[149]: begin + reg_rdata_next[0] = dio_pad_attr_19_invert_19_qs; + reg_rdata_next[1] = dio_pad_attr_19_virtual_od_en_19_qs; + reg_rdata_next[2] = dio_pad_attr_19_pull_en_19_qs; + reg_rdata_next[3] = dio_pad_attr_19_pull_select_19_qs; + reg_rdata_next[4] = dio_pad_attr_19_keeper_en_19_qs; + reg_rdata_next[5] = dio_pad_attr_19_schmitt_en_19_qs; + reg_rdata_next[6] = dio_pad_attr_19_od_en_19_qs; + reg_rdata_next[7] = dio_pad_attr_19_input_disable_19_qs; + reg_rdata_next[17:16] = dio_pad_attr_19_slew_rate_19_qs; + reg_rdata_next[23:20] = dio_pad_attr_19_drive_strength_19_qs; + end + + addr_hit[150]: begin + reg_rdata_next[0] = dio_pad_attr_20_invert_20_qs; + reg_rdata_next[1] = dio_pad_attr_20_virtual_od_en_20_qs; + reg_rdata_next[2] = dio_pad_attr_20_pull_en_20_qs; + reg_rdata_next[3] = dio_pad_attr_20_pull_select_20_qs; + reg_rdata_next[4] = dio_pad_attr_20_keeper_en_20_qs; + reg_rdata_next[5] = dio_pad_attr_20_schmitt_en_20_qs; + reg_rdata_next[6] = dio_pad_attr_20_od_en_20_qs; + reg_rdata_next[7] = dio_pad_attr_20_input_disable_20_qs; + reg_rdata_next[17:16] = dio_pad_attr_20_slew_rate_20_qs; + reg_rdata_next[23:20] = dio_pad_attr_20_drive_strength_20_qs; + end + + addr_hit[151]: begin + reg_rdata_next[0] = dio_pad_attr_21_invert_21_qs; + reg_rdata_next[1] = dio_pad_attr_21_virtual_od_en_21_qs; + reg_rdata_next[2] = dio_pad_attr_21_pull_en_21_qs; + reg_rdata_next[3] = dio_pad_attr_21_pull_select_21_qs; + reg_rdata_next[4] = dio_pad_attr_21_keeper_en_21_qs; + reg_rdata_next[5] = dio_pad_attr_21_schmitt_en_21_qs; + reg_rdata_next[6] = dio_pad_attr_21_od_en_21_qs; + reg_rdata_next[7] = dio_pad_attr_21_input_disable_21_qs; + reg_rdata_next[17:16] = dio_pad_attr_21_slew_rate_21_qs; + reg_rdata_next[23:20] = dio_pad_attr_21_drive_strength_21_qs; + end + + addr_hit[152]: begin + reg_rdata_next[0] = dio_pad_attr_22_invert_22_qs; + reg_rdata_next[1] = dio_pad_attr_22_virtual_od_en_22_qs; + reg_rdata_next[2] = dio_pad_attr_22_pull_en_22_qs; + reg_rdata_next[3] = dio_pad_attr_22_pull_select_22_qs; + reg_rdata_next[4] = dio_pad_attr_22_keeper_en_22_qs; + reg_rdata_next[5] = dio_pad_attr_22_schmitt_en_22_qs; + reg_rdata_next[6] = dio_pad_attr_22_od_en_22_qs; + reg_rdata_next[7] = dio_pad_attr_22_input_disable_22_qs; + reg_rdata_next[17:16] = dio_pad_attr_22_slew_rate_22_qs; + reg_rdata_next[23:20] = dio_pad_attr_22_drive_strength_22_qs; + end + + addr_hit[153]: begin + reg_rdata_next[0] = dio_pad_attr_23_invert_23_qs; + reg_rdata_next[1] = dio_pad_attr_23_virtual_od_en_23_qs; + reg_rdata_next[2] = dio_pad_attr_23_pull_en_23_qs; + reg_rdata_next[3] = dio_pad_attr_23_pull_select_23_qs; + reg_rdata_next[4] = dio_pad_attr_23_keeper_en_23_qs; + reg_rdata_next[5] = dio_pad_attr_23_schmitt_en_23_qs; + reg_rdata_next[6] = dio_pad_attr_23_od_en_23_qs; + reg_rdata_next[7] = dio_pad_attr_23_input_disable_23_qs; + reg_rdata_next[17:16] = dio_pad_attr_23_slew_rate_23_qs; + reg_rdata_next[23:20] = dio_pad_attr_23_drive_strength_23_qs; + end + + addr_hit[154]: begin + reg_rdata_next[0] = dio_pad_attr_24_invert_24_qs; + reg_rdata_next[1] = dio_pad_attr_24_virtual_od_en_24_qs; + reg_rdata_next[2] = dio_pad_attr_24_pull_en_24_qs; + reg_rdata_next[3] = dio_pad_attr_24_pull_select_24_qs; + reg_rdata_next[4] = dio_pad_attr_24_keeper_en_24_qs; + reg_rdata_next[5] = dio_pad_attr_24_schmitt_en_24_qs; + reg_rdata_next[6] = dio_pad_attr_24_od_en_24_qs; + reg_rdata_next[7] = dio_pad_attr_24_input_disable_24_qs; + reg_rdata_next[17:16] = dio_pad_attr_24_slew_rate_24_qs; + reg_rdata_next[23:20] = dio_pad_attr_24_drive_strength_24_qs; + end + + addr_hit[155]: begin + reg_rdata_next[0] = dio_pad_attr_25_invert_25_qs; + reg_rdata_next[1] = dio_pad_attr_25_virtual_od_en_25_qs; + reg_rdata_next[2] = dio_pad_attr_25_pull_en_25_qs; + reg_rdata_next[3] = dio_pad_attr_25_pull_select_25_qs; + reg_rdata_next[4] = dio_pad_attr_25_keeper_en_25_qs; + reg_rdata_next[5] = dio_pad_attr_25_schmitt_en_25_qs; + reg_rdata_next[6] = dio_pad_attr_25_od_en_25_qs; + reg_rdata_next[7] = dio_pad_attr_25_input_disable_25_qs; + reg_rdata_next[17:16] = dio_pad_attr_25_slew_rate_25_qs; + reg_rdata_next[23:20] = dio_pad_attr_25_drive_strength_25_qs; + end + + addr_hit[156]: begin + reg_rdata_next[0] = dio_pad_attr_26_invert_26_qs; + reg_rdata_next[1] = dio_pad_attr_26_virtual_od_en_26_qs; + reg_rdata_next[2] = dio_pad_attr_26_pull_en_26_qs; + reg_rdata_next[3] = dio_pad_attr_26_pull_select_26_qs; + reg_rdata_next[4] = dio_pad_attr_26_keeper_en_26_qs; + reg_rdata_next[5] = dio_pad_attr_26_schmitt_en_26_qs; + reg_rdata_next[6] = dio_pad_attr_26_od_en_26_qs; + reg_rdata_next[7] = dio_pad_attr_26_input_disable_26_qs; + reg_rdata_next[17:16] = dio_pad_attr_26_slew_rate_26_qs; + reg_rdata_next[23:20] = dio_pad_attr_26_drive_strength_26_qs; + end + + addr_hit[157]: begin + reg_rdata_next[0] = dio_pad_attr_27_invert_27_qs; + reg_rdata_next[1] = dio_pad_attr_27_virtual_od_en_27_qs; + reg_rdata_next[2] = dio_pad_attr_27_pull_en_27_qs; + reg_rdata_next[3] = dio_pad_attr_27_pull_select_27_qs; + reg_rdata_next[4] = dio_pad_attr_27_keeper_en_27_qs; + reg_rdata_next[5] = dio_pad_attr_27_schmitt_en_27_qs; + reg_rdata_next[6] = dio_pad_attr_27_od_en_27_qs; + reg_rdata_next[7] = dio_pad_attr_27_input_disable_27_qs; + reg_rdata_next[17:16] = dio_pad_attr_27_slew_rate_27_qs; + reg_rdata_next[23:20] = dio_pad_attr_27_drive_strength_27_qs; + end + + addr_hit[158]: begin + reg_rdata_next[0] = dio_pad_attr_28_invert_28_qs; + reg_rdata_next[1] = dio_pad_attr_28_virtual_od_en_28_qs; + reg_rdata_next[2] = dio_pad_attr_28_pull_en_28_qs; + reg_rdata_next[3] = dio_pad_attr_28_pull_select_28_qs; + reg_rdata_next[4] = dio_pad_attr_28_keeper_en_28_qs; + reg_rdata_next[5] = dio_pad_attr_28_schmitt_en_28_qs; + reg_rdata_next[6] = dio_pad_attr_28_od_en_28_qs; + reg_rdata_next[7] = dio_pad_attr_28_input_disable_28_qs; + reg_rdata_next[17:16] = dio_pad_attr_28_slew_rate_28_qs; + reg_rdata_next[23:20] = dio_pad_attr_28_drive_strength_28_qs; + end + + addr_hit[159]: begin + reg_rdata_next[0] = dio_pad_attr_29_invert_29_qs; + reg_rdata_next[1] = dio_pad_attr_29_virtual_od_en_29_qs; + reg_rdata_next[2] = dio_pad_attr_29_pull_en_29_qs; + reg_rdata_next[3] = dio_pad_attr_29_pull_select_29_qs; + reg_rdata_next[4] = dio_pad_attr_29_keeper_en_29_qs; + reg_rdata_next[5] = dio_pad_attr_29_schmitt_en_29_qs; + reg_rdata_next[6] = dio_pad_attr_29_od_en_29_qs; + reg_rdata_next[7] = dio_pad_attr_29_input_disable_29_qs; + reg_rdata_next[17:16] = dio_pad_attr_29_slew_rate_29_qs; + reg_rdata_next[23:20] = dio_pad_attr_29_drive_strength_29_qs; + end + + addr_hit[160]: begin + reg_rdata_next[0] = dio_pad_attr_30_invert_30_qs; + reg_rdata_next[1] = dio_pad_attr_30_virtual_od_en_30_qs; + reg_rdata_next[2] = dio_pad_attr_30_pull_en_30_qs; + reg_rdata_next[3] = dio_pad_attr_30_pull_select_30_qs; + reg_rdata_next[4] = dio_pad_attr_30_keeper_en_30_qs; + reg_rdata_next[5] = dio_pad_attr_30_schmitt_en_30_qs; + reg_rdata_next[6] = dio_pad_attr_30_od_en_30_qs; + reg_rdata_next[7] = dio_pad_attr_30_input_disable_30_qs; + reg_rdata_next[17:16] = dio_pad_attr_30_slew_rate_30_qs; + reg_rdata_next[23:20] = dio_pad_attr_30_drive_strength_30_qs; + end + + addr_hit[161]: begin + reg_rdata_next[0] = dio_pad_attr_31_invert_31_qs; + reg_rdata_next[1] = dio_pad_attr_31_virtual_od_en_31_qs; + reg_rdata_next[2] = dio_pad_attr_31_pull_en_31_qs; + reg_rdata_next[3] = dio_pad_attr_31_pull_select_31_qs; + reg_rdata_next[4] = dio_pad_attr_31_keeper_en_31_qs; + reg_rdata_next[5] = dio_pad_attr_31_schmitt_en_31_qs; + reg_rdata_next[6] = dio_pad_attr_31_od_en_31_qs; + reg_rdata_next[7] = dio_pad_attr_31_input_disable_31_qs; + reg_rdata_next[17:16] = dio_pad_attr_31_slew_rate_31_qs; + reg_rdata_next[23:20] = dio_pad_attr_31_drive_strength_31_qs; + end + + addr_hit[162]: begin + reg_rdata_next[0] = dio_pad_attr_32_invert_32_qs; + reg_rdata_next[1] = dio_pad_attr_32_virtual_od_en_32_qs; + reg_rdata_next[2] = dio_pad_attr_32_pull_en_32_qs; + reg_rdata_next[3] = dio_pad_attr_32_pull_select_32_qs; + reg_rdata_next[4] = dio_pad_attr_32_keeper_en_32_qs; + reg_rdata_next[5] = dio_pad_attr_32_schmitt_en_32_qs; + reg_rdata_next[6] = dio_pad_attr_32_od_en_32_qs; + reg_rdata_next[7] = dio_pad_attr_32_input_disable_32_qs; + reg_rdata_next[17:16] = dio_pad_attr_32_slew_rate_32_qs; + reg_rdata_next[23:20] = dio_pad_attr_32_drive_strength_32_qs; + end + + addr_hit[163]: begin + reg_rdata_next[0] = dio_pad_attr_33_invert_33_qs; + reg_rdata_next[1] = dio_pad_attr_33_virtual_od_en_33_qs; + reg_rdata_next[2] = dio_pad_attr_33_pull_en_33_qs; + reg_rdata_next[3] = dio_pad_attr_33_pull_select_33_qs; + reg_rdata_next[4] = dio_pad_attr_33_keeper_en_33_qs; + reg_rdata_next[5] = dio_pad_attr_33_schmitt_en_33_qs; + reg_rdata_next[6] = dio_pad_attr_33_od_en_33_qs; + reg_rdata_next[7] = dio_pad_attr_33_input_disable_33_qs; + reg_rdata_next[17:16] = dio_pad_attr_33_slew_rate_33_qs; + reg_rdata_next[23:20] = dio_pad_attr_33_drive_strength_33_qs; + end + + addr_hit[164]: begin + reg_rdata_next[0] = dio_pad_attr_34_invert_34_qs; + reg_rdata_next[1] = dio_pad_attr_34_virtual_od_en_34_qs; + reg_rdata_next[2] = dio_pad_attr_34_pull_en_34_qs; + reg_rdata_next[3] = dio_pad_attr_34_pull_select_34_qs; + reg_rdata_next[4] = dio_pad_attr_34_keeper_en_34_qs; + reg_rdata_next[5] = dio_pad_attr_34_schmitt_en_34_qs; + reg_rdata_next[6] = dio_pad_attr_34_od_en_34_qs; + reg_rdata_next[7] = dio_pad_attr_34_input_disable_34_qs; + reg_rdata_next[17:16] = dio_pad_attr_34_slew_rate_34_qs; + reg_rdata_next[23:20] = dio_pad_attr_34_drive_strength_34_qs; + end + + addr_hit[165]: begin + reg_rdata_next[0] = dio_pad_attr_35_invert_35_qs; + reg_rdata_next[1] = dio_pad_attr_35_virtual_od_en_35_qs; + reg_rdata_next[2] = dio_pad_attr_35_pull_en_35_qs; + reg_rdata_next[3] = dio_pad_attr_35_pull_select_35_qs; + reg_rdata_next[4] = dio_pad_attr_35_keeper_en_35_qs; + reg_rdata_next[5] = dio_pad_attr_35_schmitt_en_35_qs; + reg_rdata_next[6] = dio_pad_attr_35_od_en_35_qs; + reg_rdata_next[7] = dio_pad_attr_35_input_disable_35_qs; + reg_rdata_next[17:16] = dio_pad_attr_35_slew_rate_35_qs; + reg_rdata_next[23:20] = dio_pad_attr_35_drive_strength_35_qs; + end + + addr_hit[166]: begin + reg_rdata_next[0] = dio_pad_attr_36_invert_36_qs; + reg_rdata_next[1] = dio_pad_attr_36_virtual_od_en_36_qs; + reg_rdata_next[2] = dio_pad_attr_36_pull_en_36_qs; + reg_rdata_next[3] = dio_pad_attr_36_pull_select_36_qs; + reg_rdata_next[4] = dio_pad_attr_36_keeper_en_36_qs; + reg_rdata_next[5] = dio_pad_attr_36_schmitt_en_36_qs; + reg_rdata_next[6] = dio_pad_attr_36_od_en_36_qs; + reg_rdata_next[7] = dio_pad_attr_36_input_disable_36_qs; + reg_rdata_next[17:16] = dio_pad_attr_36_slew_rate_36_qs; + reg_rdata_next[23:20] = dio_pad_attr_36_drive_strength_36_qs; + end + + addr_hit[167]: begin + reg_rdata_next[0] = dio_pad_attr_37_invert_37_qs; + reg_rdata_next[1] = dio_pad_attr_37_virtual_od_en_37_qs; + reg_rdata_next[2] = dio_pad_attr_37_pull_en_37_qs; + reg_rdata_next[3] = dio_pad_attr_37_pull_select_37_qs; + reg_rdata_next[4] = dio_pad_attr_37_keeper_en_37_qs; + reg_rdata_next[5] = dio_pad_attr_37_schmitt_en_37_qs; + reg_rdata_next[6] = dio_pad_attr_37_od_en_37_qs; + reg_rdata_next[7] = dio_pad_attr_37_input_disable_37_qs; + reg_rdata_next[17:16] = dio_pad_attr_37_slew_rate_37_qs; + reg_rdata_next[23:20] = dio_pad_attr_37_drive_strength_37_qs; + end + + addr_hit[168]: begin + reg_rdata_next[0] = dio_pad_attr_38_invert_38_qs; + reg_rdata_next[1] = dio_pad_attr_38_virtual_od_en_38_qs; + reg_rdata_next[2] = dio_pad_attr_38_pull_en_38_qs; + reg_rdata_next[3] = dio_pad_attr_38_pull_select_38_qs; + reg_rdata_next[4] = dio_pad_attr_38_keeper_en_38_qs; + reg_rdata_next[5] = dio_pad_attr_38_schmitt_en_38_qs; + reg_rdata_next[6] = dio_pad_attr_38_od_en_38_qs; + reg_rdata_next[7] = dio_pad_attr_38_input_disable_38_qs; + reg_rdata_next[17:16] = dio_pad_attr_38_slew_rate_38_qs; + reg_rdata_next[23:20] = dio_pad_attr_38_drive_strength_38_qs; + end + + addr_hit[169]: begin + reg_rdata_next[0] = dio_pad_attr_39_invert_39_qs; + reg_rdata_next[1] = dio_pad_attr_39_virtual_od_en_39_qs; + reg_rdata_next[2] = dio_pad_attr_39_pull_en_39_qs; + reg_rdata_next[3] = dio_pad_attr_39_pull_select_39_qs; + reg_rdata_next[4] = dio_pad_attr_39_keeper_en_39_qs; + reg_rdata_next[5] = dio_pad_attr_39_schmitt_en_39_qs; + reg_rdata_next[6] = dio_pad_attr_39_od_en_39_qs; + reg_rdata_next[7] = dio_pad_attr_39_input_disable_39_qs; + reg_rdata_next[17:16] = dio_pad_attr_39_slew_rate_39_qs; + reg_rdata_next[23:20] = dio_pad_attr_39_drive_strength_39_qs; + end + + addr_hit[170]: begin + reg_rdata_next[0] = dio_pad_attr_40_invert_40_qs; + reg_rdata_next[1] = dio_pad_attr_40_virtual_od_en_40_qs; + reg_rdata_next[2] = dio_pad_attr_40_pull_en_40_qs; + reg_rdata_next[3] = dio_pad_attr_40_pull_select_40_qs; + reg_rdata_next[4] = dio_pad_attr_40_keeper_en_40_qs; + reg_rdata_next[5] = dio_pad_attr_40_schmitt_en_40_qs; + reg_rdata_next[6] = dio_pad_attr_40_od_en_40_qs; + reg_rdata_next[7] = dio_pad_attr_40_input_disable_40_qs; + reg_rdata_next[17:16] = dio_pad_attr_40_slew_rate_40_qs; + reg_rdata_next[23:20] = dio_pad_attr_40_drive_strength_40_qs; + end + + addr_hit[171]: begin + reg_rdata_next[0] = dio_pad_attr_41_invert_41_qs; + reg_rdata_next[1] = dio_pad_attr_41_virtual_od_en_41_qs; + reg_rdata_next[2] = dio_pad_attr_41_pull_en_41_qs; + reg_rdata_next[3] = dio_pad_attr_41_pull_select_41_qs; + reg_rdata_next[4] = dio_pad_attr_41_keeper_en_41_qs; + reg_rdata_next[5] = dio_pad_attr_41_schmitt_en_41_qs; + reg_rdata_next[6] = dio_pad_attr_41_od_en_41_qs; + reg_rdata_next[7] = dio_pad_attr_41_input_disable_41_qs; + reg_rdata_next[17:16] = dio_pad_attr_41_slew_rate_41_qs; + reg_rdata_next[23:20] = dio_pad_attr_41_drive_strength_41_qs; + end + + addr_hit[172]: begin + reg_rdata_next[0] = dio_pad_attr_42_invert_42_qs; + reg_rdata_next[1] = dio_pad_attr_42_virtual_od_en_42_qs; + reg_rdata_next[2] = dio_pad_attr_42_pull_en_42_qs; + reg_rdata_next[3] = dio_pad_attr_42_pull_select_42_qs; + reg_rdata_next[4] = dio_pad_attr_42_keeper_en_42_qs; + reg_rdata_next[5] = dio_pad_attr_42_schmitt_en_42_qs; + reg_rdata_next[6] = dio_pad_attr_42_od_en_42_qs; + reg_rdata_next[7] = dio_pad_attr_42_input_disable_42_qs; + reg_rdata_next[17:16] = dio_pad_attr_42_slew_rate_42_qs; + reg_rdata_next[23:20] = dio_pad_attr_42_drive_strength_42_qs; + end + + addr_hit[173]: begin + reg_rdata_next[0] = dio_pad_attr_43_invert_43_qs; + reg_rdata_next[1] = dio_pad_attr_43_virtual_od_en_43_qs; + reg_rdata_next[2] = dio_pad_attr_43_pull_en_43_qs; + reg_rdata_next[3] = dio_pad_attr_43_pull_select_43_qs; + reg_rdata_next[4] = dio_pad_attr_43_keeper_en_43_qs; + reg_rdata_next[5] = dio_pad_attr_43_schmitt_en_43_qs; + reg_rdata_next[6] = dio_pad_attr_43_od_en_43_qs; + reg_rdata_next[7] = dio_pad_attr_43_input_disable_43_qs; + reg_rdata_next[17:16] = dio_pad_attr_43_slew_rate_43_qs; + reg_rdata_next[23:20] = dio_pad_attr_43_drive_strength_43_qs; + end + + addr_hit[174]: begin + reg_rdata_next[0] = dio_pad_attr_44_invert_44_qs; + reg_rdata_next[1] = dio_pad_attr_44_virtual_od_en_44_qs; + reg_rdata_next[2] = dio_pad_attr_44_pull_en_44_qs; + reg_rdata_next[3] = dio_pad_attr_44_pull_select_44_qs; + reg_rdata_next[4] = dio_pad_attr_44_keeper_en_44_qs; + reg_rdata_next[5] = dio_pad_attr_44_schmitt_en_44_qs; + reg_rdata_next[6] = dio_pad_attr_44_od_en_44_qs; + reg_rdata_next[7] = dio_pad_attr_44_input_disable_44_qs; + reg_rdata_next[17:16] = dio_pad_attr_44_slew_rate_44_qs; + reg_rdata_next[23:20] = dio_pad_attr_44_drive_strength_44_qs; + end + + addr_hit[175]: begin + reg_rdata_next[0] = dio_pad_attr_45_invert_45_qs; + reg_rdata_next[1] = dio_pad_attr_45_virtual_od_en_45_qs; + reg_rdata_next[2] = dio_pad_attr_45_pull_en_45_qs; + reg_rdata_next[3] = dio_pad_attr_45_pull_select_45_qs; + reg_rdata_next[4] = dio_pad_attr_45_keeper_en_45_qs; + reg_rdata_next[5] = dio_pad_attr_45_schmitt_en_45_qs; + reg_rdata_next[6] = dio_pad_attr_45_od_en_45_qs; + reg_rdata_next[7] = dio_pad_attr_45_input_disable_45_qs; + reg_rdata_next[17:16] = dio_pad_attr_45_slew_rate_45_qs; + reg_rdata_next[23:20] = dio_pad_attr_45_drive_strength_45_qs; + end + + addr_hit[176]: begin + reg_rdata_next[0] = dio_pad_attr_46_invert_46_qs; + reg_rdata_next[1] = dio_pad_attr_46_virtual_od_en_46_qs; + reg_rdata_next[2] = dio_pad_attr_46_pull_en_46_qs; + reg_rdata_next[3] = dio_pad_attr_46_pull_select_46_qs; + reg_rdata_next[4] = dio_pad_attr_46_keeper_en_46_qs; + reg_rdata_next[5] = dio_pad_attr_46_schmitt_en_46_qs; + reg_rdata_next[6] = dio_pad_attr_46_od_en_46_qs; + reg_rdata_next[7] = dio_pad_attr_46_input_disable_46_qs; + reg_rdata_next[17:16] = dio_pad_attr_46_slew_rate_46_qs; + reg_rdata_next[23:20] = dio_pad_attr_46_drive_strength_46_qs; + end + + addr_hit[177]: begin + reg_rdata_next[0] = dio_pad_attr_47_invert_47_qs; + reg_rdata_next[1] = dio_pad_attr_47_virtual_od_en_47_qs; + reg_rdata_next[2] = dio_pad_attr_47_pull_en_47_qs; + reg_rdata_next[3] = dio_pad_attr_47_pull_select_47_qs; + reg_rdata_next[4] = dio_pad_attr_47_keeper_en_47_qs; + reg_rdata_next[5] = dio_pad_attr_47_schmitt_en_47_qs; + reg_rdata_next[6] = dio_pad_attr_47_od_en_47_qs; + reg_rdata_next[7] = dio_pad_attr_47_input_disable_47_qs; + reg_rdata_next[17:16] = dio_pad_attr_47_slew_rate_47_qs; + reg_rdata_next[23:20] = dio_pad_attr_47_drive_strength_47_qs; + end + + addr_hit[178]: begin + reg_rdata_next[0] = dio_pad_attr_48_invert_48_qs; + reg_rdata_next[1] = dio_pad_attr_48_virtual_od_en_48_qs; + reg_rdata_next[2] = dio_pad_attr_48_pull_en_48_qs; + reg_rdata_next[3] = dio_pad_attr_48_pull_select_48_qs; + reg_rdata_next[4] = dio_pad_attr_48_keeper_en_48_qs; + reg_rdata_next[5] = dio_pad_attr_48_schmitt_en_48_qs; + reg_rdata_next[6] = dio_pad_attr_48_od_en_48_qs; + reg_rdata_next[7] = dio_pad_attr_48_input_disable_48_qs; + reg_rdata_next[17:16] = dio_pad_attr_48_slew_rate_48_qs; + reg_rdata_next[23:20] = dio_pad_attr_48_drive_strength_48_qs; + end + + addr_hit[179]: begin + reg_rdata_next[0] = dio_pad_attr_49_invert_49_qs; + reg_rdata_next[1] = dio_pad_attr_49_virtual_od_en_49_qs; + reg_rdata_next[2] = dio_pad_attr_49_pull_en_49_qs; + reg_rdata_next[3] = dio_pad_attr_49_pull_select_49_qs; + reg_rdata_next[4] = dio_pad_attr_49_keeper_en_49_qs; + reg_rdata_next[5] = dio_pad_attr_49_schmitt_en_49_qs; + reg_rdata_next[6] = dio_pad_attr_49_od_en_49_qs; + reg_rdata_next[7] = dio_pad_attr_49_input_disable_49_qs; + reg_rdata_next[17:16] = dio_pad_attr_49_slew_rate_49_qs; + reg_rdata_next[23:20] = dio_pad_attr_49_drive_strength_49_qs; + end + + addr_hit[180]: begin + reg_rdata_next[0] = dio_pad_attr_50_invert_50_qs; + reg_rdata_next[1] = dio_pad_attr_50_virtual_od_en_50_qs; + reg_rdata_next[2] = dio_pad_attr_50_pull_en_50_qs; + reg_rdata_next[3] = dio_pad_attr_50_pull_select_50_qs; + reg_rdata_next[4] = dio_pad_attr_50_keeper_en_50_qs; + reg_rdata_next[5] = dio_pad_attr_50_schmitt_en_50_qs; + reg_rdata_next[6] = dio_pad_attr_50_od_en_50_qs; + reg_rdata_next[7] = dio_pad_attr_50_input_disable_50_qs; + reg_rdata_next[17:16] = dio_pad_attr_50_slew_rate_50_qs; + reg_rdata_next[23:20] = dio_pad_attr_50_drive_strength_50_qs; + end + + addr_hit[181]: begin + reg_rdata_next[0] = dio_pad_attr_51_invert_51_qs; + reg_rdata_next[1] = dio_pad_attr_51_virtual_od_en_51_qs; + reg_rdata_next[2] = dio_pad_attr_51_pull_en_51_qs; + reg_rdata_next[3] = dio_pad_attr_51_pull_select_51_qs; + reg_rdata_next[4] = dio_pad_attr_51_keeper_en_51_qs; + reg_rdata_next[5] = dio_pad_attr_51_schmitt_en_51_qs; + reg_rdata_next[6] = dio_pad_attr_51_od_en_51_qs; + reg_rdata_next[7] = dio_pad_attr_51_input_disable_51_qs; + reg_rdata_next[17:16] = dio_pad_attr_51_slew_rate_51_qs; + reg_rdata_next[23:20] = dio_pad_attr_51_drive_strength_51_qs; + end + + addr_hit[182]: begin + reg_rdata_next[0] = dio_pad_attr_52_invert_52_qs; + reg_rdata_next[1] = dio_pad_attr_52_virtual_od_en_52_qs; + reg_rdata_next[2] = dio_pad_attr_52_pull_en_52_qs; + reg_rdata_next[3] = dio_pad_attr_52_pull_select_52_qs; + reg_rdata_next[4] = dio_pad_attr_52_keeper_en_52_qs; + reg_rdata_next[5] = dio_pad_attr_52_schmitt_en_52_qs; + reg_rdata_next[6] = dio_pad_attr_52_od_en_52_qs; + reg_rdata_next[7] = dio_pad_attr_52_input_disable_52_qs; + reg_rdata_next[17:16] = dio_pad_attr_52_slew_rate_52_qs; + reg_rdata_next[23:20] = dio_pad_attr_52_drive_strength_52_qs; + end + + addr_hit[183]: begin + reg_rdata_next[0] = dio_pad_attr_53_invert_53_qs; + reg_rdata_next[1] = dio_pad_attr_53_virtual_od_en_53_qs; + reg_rdata_next[2] = dio_pad_attr_53_pull_en_53_qs; + reg_rdata_next[3] = dio_pad_attr_53_pull_select_53_qs; + reg_rdata_next[4] = dio_pad_attr_53_keeper_en_53_qs; + reg_rdata_next[5] = dio_pad_attr_53_schmitt_en_53_qs; + reg_rdata_next[6] = dio_pad_attr_53_od_en_53_qs; + reg_rdata_next[7] = dio_pad_attr_53_input_disable_53_qs; + reg_rdata_next[17:16] = dio_pad_attr_53_slew_rate_53_qs; + reg_rdata_next[23:20] = dio_pad_attr_53_drive_strength_53_qs; + end + + addr_hit[184]: begin + reg_rdata_next[0] = dio_pad_attr_54_invert_54_qs; + reg_rdata_next[1] = dio_pad_attr_54_virtual_od_en_54_qs; + reg_rdata_next[2] = dio_pad_attr_54_pull_en_54_qs; + reg_rdata_next[3] = dio_pad_attr_54_pull_select_54_qs; + reg_rdata_next[4] = dio_pad_attr_54_keeper_en_54_qs; + reg_rdata_next[5] = dio_pad_attr_54_schmitt_en_54_qs; + reg_rdata_next[6] = dio_pad_attr_54_od_en_54_qs; + reg_rdata_next[7] = dio_pad_attr_54_input_disable_54_qs; + reg_rdata_next[17:16] = dio_pad_attr_54_slew_rate_54_qs; + reg_rdata_next[23:20] = dio_pad_attr_54_drive_strength_54_qs; + end + + addr_hit[185]: begin + reg_rdata_next[0] = dio_pad_attr_55_invert_55_qs; + reg_rdata_next[1] = dio_pad_attr_55_virtual_od_en_55_qs; + reg_rdata_next[2] = dio_pad_attr_55_pull_en_55_qs; + reg_rdata_next[3] = dio_pad_attr_55_pull_select_55_qs; + reg_rdata_next[4] = dio_pad_attr_55_keeper_en_55_qs; + reg_rdata_next[5] = dio_pad_attr_55_schmitt_en_55_qs; + reg_rdata_next[6] = dio_pad_attr_55_od_en_55_qs; + reg_rdata_next[7] = dio_pad_attr_55_input_disable_55_qs; + reg_rdata_next[17:16] = dio_pad_attr_55_slew_rate_55_qs; + reg_rdata_next[23:20] = dio_pad_attr_55_drive_strength_55_qs; + end + + addr_hit[186]: begin + reg_rdata_next[0] = dio_pad_attr_56_invert_56_qs; + reg_rdata_next[1] = dio_pad_attr_56_virtual_od_en_56_qs; + reg_rdata_next[2] = dio_pad_attr_56_pull_en_56_qs; + reg_rdata_next[3] = dio_pad_attr_56_pull_select_56_qs; + reg_rdata_next[4] = dio_pad_attr_56_keeper_en_56_qs; + reg_rdata_next[5] = dio_pad_attr_56_schmitt_en_56_qs; + reg_rdata_next[6] = dio_pad_attr_56_od_en_56_qs; + reg_rdata_next[7] = dio_pad_attr_56_input_disable_56_qs; + reg_rdata_next[17:16] = dio_pad_attr_56_slew_rate_56_qs; + reg_rdata_next[23:20] = dio_pad_attr_56_drive_strength_56_qs; + end + + addr_hit[187]: begin + reg_rdata_next[0] = dio_pad_attr_57_invert_57_qs; + reg_rdata_next[1] = dio_pad_attr_57_virtual_od_en_57_qs; + reg_rdata_next[2] = dio_pad_attr_57_pull_en_57_qs; + reg_rdata_next[3] = dio_pad_attr_57_pull_select_57_qs; + reg_rdata_next[4] = dio_pad_attr_57_keeper_en_57_qs; + reg_rdata_next[5] = dio_pad_attr_57_schmitt_en_57_qs; + reg_rdata_next[6] = dio_pad_attr_57_od_en_57_qs; + reg_rdata_next[7] = dio_pad_attr_57_input_disable_57_qs; + reg_rdata_next[17:16] = dio_pad_attr_57_slew_rate_57_qs; + reg_rdata_next[23:20] = dio_pad_attr_57_drive_strength_57_qs; + end + + addr_hit[188]: begin + reg_rdata_next[0] = dio_pad_attr_58_invert_58_qs; + reg_rdata_next[1] = dio_pad_attr_58_virtual_od_en_58_qs; + reg_rdata_next[2] = dio_pad_attr_58_pull_en_58_qs; + reg_rdata_next[3] = dio_pad_attr_58_pull_select_58_qs; + reg_rdata_next[4] = dio_pad_attr_58_keeper_en_58_qs; + reg_rdata_next[5] = dio_pad_attr_58_schmitt_en_58_qs; + reg_rdata_next[6] = dio_pad_attr_58_od_en_58_qs; + reg_rdata_next[7] = dio_pad_attr_58_input_disable_58_qs; + reg_rdata_next[17:16] = dio_pad_attr_58_slew_rate_58_qs; + reg_rdata_next[23:20] = dio_pad_attr_58_drive_strength_58_qs; + end + + addr_hit[189]: begin + reg_rdata_next[0] = dio_pad_attr_59_invert_59_qs; + reg_rdata_next[1] = dio_pad_attr_59_virtual_od_en_59_qs; + reg_rdata_next[2] = dio_pad_attr_59_pull_en_59_qs; + reg_rdata_next[3] = dio_pad_attr_59_pull_select_59_qs; + reg_rdata_next[4] = dio_pad_attr_59_keeper_en_59_qs; + reg_rdata_next[5] = dio_pad_attr_59_schmitt_en_59_qs; + reg_rdata_next[6] = dio_pad_attr_59_od_en_59_qs; + reg_rdata_next[7] = dio_pad_attr_59_input_disable_59_qs; + reg_rdata_next[17:16] = dio_pad_attr_59_slew_rate_59_qs; + reg_rdata_next[23:20] = dio_pad_attr_59_drive_strength_59_qs; + end + + addr_hit[190]: begin + reg_rdata_next[0] = dio_pad_attr_60_invert_60_qs; + reg_rdata_next[1] = dio_pad_attr_60_virtual_od_en_60_qs; + reg_rdata_next[2] = dio_pad_attr_60_pull_en_60_qs; + reg_rdata_next[3] = dio_pad_attr_60_pull_select_60_qs; + reg_rdata_next[4] = dio_pad_attr_60_keeper_en_60_qs; + reg_rdata_next[5] = dio_pad_attr_60_schmitt_en_60_qs; + reg_rdata_next[6] = dio_pad_attr_60_od_en_60_qs; + reg_rdata_next[7] = dio_pad_attr_60_input_disable_60_qs; + reg_rdata_next[17:16] = dio_pad_attr_60_slew_rate_60_qs; + reg_rdata_next[23:20] = dio_pad_attr_60_drive_strength_60_qs; + end + + addr_hit[191]: begin + reg_rdata_next[0] = dio_pad_attr_61_invert_61_qs; + reg_rdata_next[1] = dio_pad_attr_61_virtual_od_en_61_qs; + reg_rdata_next[2] = dio_pad_attr_61_pull_en_61_qs; + reg_rdata_next[3] = dio_pad_attr_61_pull_select_61_qs; + reg_rdata_next[4] = dio_pad_attr_61_keeper_en_61_qs; + reg_rdata_next[5] = dio_pad_attr_61_schmitt_en_61_qs; + reg_rdata_next[6] = dio_pad_attr_61_od_en_61_qs; + reg_rdata_next[7] = dio_pad_attr_61_input_disable_61_qs; + reg_rdata_next[17:16] = dio_pad_attr_61_slew_rate_61_qs; + reg_rdata_next[23:20] = dio_pad_attr_61_drive_strength_61_qs; + end + + addr_hit[192]: begin + reg_rdata_next[0] = dio_pad_attr_62_invert_62_qs; + reg_rdata_next[1] = dio_pad_attr_62_virtual_od_en_62_qs; + reg_rdata_next[2] = dio_pad_attr_62_pull_en_62_qs; + reg_rdata_next[3] = dio_pad_attr_62_pull_select_62_qs; + reg_rdata_next[4] = dio_pad_attr_62_keeper_en_62_qs; + reg_rdata_next[5] = dio_pad_attr_62_schmitt_en_62_qs; + reg_rdata_next[6] = dio_pad_attr_62_od_en_62_qs; + reg_rdata_next[7] = dio_pad_attr_62_input_disable_62_qs; + reg_rdata_next[17:16] = dio_pad_attr_62_slew_rate_62_qs; + reg_rdata_next[23:20] = dio_pad_attr_62_drive_strength_62_qs; + end + + addr_hit[193]: begin + reg_rdata_next[0] = dio_pad_attr_63_invert_63_qs; + reg_rdata_next[1] = dio_pad_attr_63_virtual_od_en_63_qs; + reg_rdata_next[2] = dio_pad_attr_63_pull_en_63_qs; + reg_rdata_next[3] = dio_pad_attr_63_pull_select_63_qs; + reg_rdata_next[4] = dio_pad_attr_63_keeper_en_63_qs; + reg_rdata_next[5] = dio_pad_attr_63_schmitt_en_63_qs; + reg_rdata_next[6] = dio_pad_attr_63_od_en_63_qs; + reg_rdata_next[7] = dio_pad_attr_63_input_disable_63_qs; + reg_rdata_next[17:16] = dio_pad_attr_63_slew_rate_63_qs; + reg_rdata_next[23:20] = dio_pad_attr_63_drive_strength_63_qs; + end + + addr_hit[194]: begin + reg_rdata_next[0] = dio_pad_attr_64_invert_64_qs; + reg_rdata_next[1] = dio_pad_attr_64_virtual_od_en_64_qs; + reg_rdata_next[2] = dio_pad_attr_64_pull_en_64_qs; + reg_rdata_next[3] = dio_pad_attr_64_pull_select_64_qs; + reg_rdata_next[4] = dio_pad_attr_64_keeper_en_64_qs; + reg_rdata_next[5] = dio_pad_attr_64_schmitt_en_64_qs; + reg_rdata_next[6] = dio_pad_attr_64_od_en_64_qs; + reg_rdata_next[7] = dio_pad_attr_64_input_disable_64_qs; + reg_rdata_next[17:16] = dio_pad_attr_64_slew_rate_64_qs; + reg_rdata_next[23:20] = dio_pad_attr_64_drive_strength_64_qs; + end + + addr_hit[195]: begin + reg_rdata_next[0] = dio_pad_attr_65_invert_65_qs; + reg_rdata_next[1] = dio_pad_attr_65_virtual_od_en_65_qs; + reg_rdata_next[2] = dio_pad_attr_65_pull_en_65_qs; + reg_rdata_next[3] = dio_pad_attr_65_pull_select_65_qs; + reg_rdata_next[4] = dio_pad_attr_65_keeper_en_65_qs; + reg_rdata_next[5] = dio_pad_attr_65_schmitt_en_65_qs; + reg_rdata_next[6] = dio_pad_attr_65_od_en_65_qs; + reg_rdata_next[7] = dio_pad_attr_65_input_disable_65_qs; + reg_rdata_next[17:16] = dio_pad_attr_65_slew_rate_65_qs; + reg_rdata_next[23:20] = dio_pad_attr_65_drive_strength_65_qs; + end + + addr_hit[196]: begin + reg_rdata_next[0] = dio_pad_attr_66_invert_66_qs; + reg_rdata_next[1] = dio_pad_attr_66_virtual_od_en_66_qs; + reg_rdata_next[2] = dio_pad_attr_66_pull_en_66_qs; + reg_rdata_next[3] = dio_pad_attr_66_pull_select_66_qs; + reg_rdata_next[4] = dio_pad_attr_66_keeper_en_66_qs; + reg_rdata_next[5] = dio_pad_attr_66_schmitt_en_66_qs; + reg_rdata_next[6] = dio_pad_attr_66_od_en_66_qs; + reg_rdata_next[7] = dio_pad_attr_66_input_disable_66_qs; + reg_rdata_next[17:16] = dio_pad_attr_66_slew_rate_66_qs; + reg_rdata_next[23:20] = dio_pad_attr_66_drive_strength_66_qs; + end + + addr_hit[197]: begin + reg_rdata_next[0] = dio_pad_attr_67_invert_67_qs; + reg_rdata_next[1] = dio_pad_attr_67_virtual_od_en_67_qs; + reg_rdata_next[2] = dio_pad_attr_67_pull_en_67_qs; + reg_rdata_next[3] = dio_pad_attr_67_pull_select_67_qs; + reg_rdata_next[4] = dio_pad_attr_67_keeper_en_67_qs; + reg_rdata_next[5] = dio_pad_attr_67_schmitt_en_67_qs; + reg_rdata_next[6] = dio_pad_attr_67_od_en_67_qs; + reg_rdata_next[7] = dio_pad_attr_67_input_disable_67_qs; + reg_rdata_next[17:16] = dio_pad_attr_67_slew_rate_67_qs; + reg_rdata_next[23:20] = dio_pad_attr_67_drive_strength_67_qs; + end + + addr_hit[198]: begin + reg_rdata_next[0] = dio_pad_attr_68_invert_68_qs; + reg_rdata_next[1] = dio_pad_attr_68_virtual_od_en_68_qs; + reg_rdata_next[2] = dio_pad_attr_68_pull_en_68_qs; + reg_rdata_next[3] = dio_pad_attr_68_pull_select_68_qs; + reg_rdata_next[4] = dio_pad_attr_68_keeper_en_68_qs; + reg_rdata_next[5] = dio_pad_attr_68_schmitt_en_68_qs; + reg_rdata_next[6] = dio_pad_attr_68_od_en_68_qs; + reg_rdata_next[7] = dio_pad_attr_68_input_disable_68_qs; + reg_rdata_next[17:16] = dio_pad_attr_68_slew_rate_68_qs; + reg_rdata_next[23:20] = dio_pad_attr_68_drive_strength_68_qs; + end + + addr_hit[199]: begin + reg_rdata_next[0] = dio_pad_attr_69_invert_69_qs; + reg_rdata_next[1] = dio_pad_attr_69_virtual_od_en_69_qs; + reg_rdata_next[2] = dio_pad_attr_69_pull_en_69_qs; + reg_rdata_next[3] = dio_pad_attr_69_pull_select_69_qs; + reg_rdata_next[4] = dio_pad_attr_69_keeper_en_69_qs; + reg_rdata_next[5] = dio_pad_attr_69_schmitt_en_69_qs; + reg_rdata_next[6] = dio_pad_attr_69_od_en_69_qs; + reg_rdata_next[7] = dio_pad_attr_69_input_disable_69_qs; + reg_rdata_next[17:16] = dio_pad_attr_69_slew_rate_69_qs; + reg_rdata_next[23:20] = dio_pad_attr_69_drive_strength_69_qs; + end + + addr_hit[200]: begin + reg_rdata_next[0] = dio_pad_attr_70_invert_70_qs; + reg_rdata_next[1] = dio_pad_attr_70_virtual_od_en_70_qs; + reg_rdata_next[2] = dio_pad_attr_70_pull_en_70_qs; + reg_rdata_next[3] = dio_pad_attr_70_pull_select_70_qs; + reg_rdata_next[4] = dio_pad_attr_70_keeper_en_70_qs; + reg_rdata_next[5] = dio_pad_attr_70_schmitt_en_70_qs; + reg_rdata_next[6] = dio_pad_attr_70_od_en_70_qs; + reg_rdata_next[7] = dio_pad_attr_70_input_disable_70_qs; + reg_rdata_next[17:16] = dio_pad_attr_70_slew_rate_70_qs; + reg_rdata_next[23:20] = dio_pad_attr_70_drive_strength_70_qs; + end + + addr_hit[201]: begin + reg_rdata_next[0] = dio_pad_attr_71_invert_71_qs; + reg_rdata_next[1] = dio_pad_attr_71_virtual_od_en_71_qs; + reg_rdata_next[2] = dio_pad_attr_71_pull_en_71_qs; + reg_rdata_next[3] = dio_pad_attr_71_pull_select_71_qs; + reg_rdata_next[4] = dio_pad_attr_71_keeper_en_71_qs; + reg_rdata_next[5] = dio_pad_attr_71_schmitt_en_71_qs; + reg_rdata_next[6] = dio_pad_attr_71_od_en_71_qs; + reg_rdata_next[7] = dio_pad_attr_71_input_disable_71_qs; + reg_rdata_next[17:16] = dio_pad_attr_71_slew_rate_71_qs; + reg_rdata_next[23:20] = dio_pad_attr_71_drive_strength_71_qs; + end + + addr_hit[202]: begin + reg_rdata_next[0] = dio_pad_attr_72_invert_72_qs; + reg_rdata_next[1] = dio_pad_attr_72_virtual_od_en_72_qs; + reg_rdata_next[2] = dio_pad_attr_72_pull_en_72_qs; + reg_rdata_next[3] = dio_pad_attr_72_pull_select_72_qs; + reg_rdata_next[4] = dio_pad_attr_72_keeper_en_72_qs; + reg_rdata_next[5] = dio_pad_attr_72_schmitt_en_72_qs; + reg_rdata_next[6] = dio_pad_attr_72_od_en_72_qs; + reg_rdata_next[7] = dio_pad_attr_72_input_disable_72_qs; + reg_rdata_next[17:16] = dio_pad_attr_72_slew_rate_72_qs; + reg_rdata_next[23:20] = dio_pad_attr_72_drive_strength_72_qs; + end + + addr_hit[203]: begin + reg_rdata_next[0] = mio_pad_sleep_status_en_0_qs; + reg_rdata_next[1] = mio_pad_sleep_status_en_1_qs; + reg_rdata_next[2] = mio_pad_sleep_status_en_2_qs; + reg_rdata_next[3] = mio_pad_sleep_status_en_3_qs; + reg_rdata_next[4] = mio_pad_sleep_status_en_4_qs; + reg_rdata_next[5] = mio_pad_sleep_status_en_5_qs; + reg_rdata_next[6] = mio_pad_sleep_status_en_6_qs; + reg_rdata_next[7] = mio_pad_sleep_status_en_7_qs; + reg_rdata_next[8] = mio_pad_sleep_status_en_8_qs; + reg_rdata_next[9] = mio_pad_sleep_status_en_9_qs; + reg_rdata_next[10] = mio_pad_sleep_status_en_10_qs; + reg_rdata_next[11] = mio_pad_sleep_status_en_11_qs; + end + + addr_hit[204]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs; + end + + addr_hit[205]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs; + end + + addr_hit[206]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs; + end + + addr_hit[207]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs; + end + + addr_hit[208]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs; + end + + addr_hit[209]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs; + end + + addr_hit[210]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs; + end + + addr_hit[211]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs; + end + + addr_hit[212]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs; + end + + addr_hit[213]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs; + end + + addr_hit[214]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs; + end + + addr_hit[215]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs; + end + + addr_hit[216]: begin + reg_rdata_next[0] = mio_pad_sleep_en_0_qs; + end + + addr_hit[217]: begin + reg_rdata_next[0] = mio_pad_sleep_en_1_qs; + end + + addr_hit[218]: begin + reg_rdata_next[0] = mio_pad_sleep_en_2_qs; + end + + addr_hit[219]: begin + reg_rdata_next[0] = mio_pad_sleep_en_3_qs; + end + + addr_hit[220]: begin + reg_rdata_next[0] = mio_pad_sleep_en_4_qs; + end + + addr_hit[221]: begin + reg_rdata_next[0] = mio_pad_sleep_en_5_qs; + end + + addr_hit[222]: begin + reg_rdata_next[0] = mio_pad_sleep_en_6_qs; + end + + addr_hit[223]: begin + reg_rdata_next[0] = mio_pad_sleep_en_7_qs; + end + + addr_hit[224]: begin + reg_rdata_next[0] = mio_pad_sleep_en_8_qs; + end + + addr_hit[225]: begin + reg_rdata_next[0] = mio_pad_sleep_en_9_qs; + end + + addr_hit[226]: begin + reg_rdata_next[0] = mio_pad_sleep_en_10_qs; + end + + addr_hit[227]: begin + reg_rdata_next[0] = mio_pad_sleep_en_11_qs; + end + + addr_hit[228]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs; + end + + addr_hit[229]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs; + end + + addr_hit[230]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs; + end + + addr_hit[231]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs; + end + + addr_hit[232]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs; + end + + addr_hit[233]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs; + end + + addr_hit[234]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs; + end + + addr_hit[235]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs; + end + + addr_hit[236]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs; + end + + addr_hit[237]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs; + end + + addr_hit[238]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs; + end + + addr_hit[239]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs; + end + + addr_hit[240]: begin + reg_rdata_next[0] = dio_pad_sleep_status_0_en_0_qs; + reg_rdata_next[1] = dio_pad_sleep_status_0_en_1_qs; + reg_rdata_next[2] = dio_pad_sleep_status_0_en_2_qs; + reg_rdata_next[3] = dio_pad_sleep_status_0_en_3_qs; + reg_rdata_next[4] = dio_pad_sleep_status_0_en_4_qs; + reg_rdata_next[5] = dio_pad_sleep_status_0_en_5_qs; + reg_rdata_next[6] = dio_pad_sleep_status_0_en_6_qs; + reg_rdata_next[7] = dio_pad_sleep_status_0_en_7_qs; + reg_rdata_next[8] = dio_pad_sleep_status_0_en_8_qs; + reg_rdata_next[9] = dio_pad_sleep_status_0_en_9_qs; + reg_rdata_next[10] = dio_pad_sleep_status_0_en_10_qs; + reg_rdata_next[11] = dio_pad_sleep_status_0_en_11_qs; + reg_rdata_next[12] = dio_pad_sleep_status_0_en_12_qs; + reg_rdata_next[13] = dio_pad_sleep_status_0_en_13_qs; + reg_rdata_next[14] = dio_pad_sleep_status_0_en_14_qs; + reg_rdata_next[15] = dio_pad_sleep_status_0_en_15_qs; + reg_rdata_next[16] = dio_pad_sleep_status_0_en_16_qs; + reg_rdata_next[17] = dio_pad_sleep_status_0_en_17_qs; + reg_rdata_next[18] = dio_pad_sleep_status_0_en_18_qs; + reg_rdata_next[19] = dio_pad_sleep_status_0_en_19_qs; + reg_rdata_next[20] = dio_pad_sleep_status_0_en_20_qs; + reg_rdata_next[21] = dio_pad_sleep_status_0_en_21_qs; + reg_rdata_next[22] = dio_pad_sleep_status_0_en_22_qs; + reg_rdata_next[23] = dio_pad_sleep_status_0_en_23_qs; + reg_rdata_next[24] = dio_pad_sleep_status_0_en_24_qs; + reg_rdata_next[25] = dio_pad_sleep_status_0_en_25_qs; + reg_rdata_next[26] = dio_pad_sleep_status_0_en_26_qs; + reg_rdata_next[27] = dio_pad_sleep_status_0_en_27_qs; + reg_rdata_next[28] = dio_pad_sleep_status_0_en_28_qs; + reg_rdata_next[29] = dio_pad_sleep_status_0_en_29_qs; + reg_rdata_next[30] = dio_pad_sleep_status_0_en_30_qs; + reg_rdata_next[31] = dio_pad_sleep_status_0_en_31_qs; + end + + addr_hit[241]: begin + reg_rdata_next[0] = dio_pad_sleep_status_1_en_32_qs; + reg_rdata_next[1] = dio_pad_sleep_status_1_en_33_qs; + reg_rdata_next[2] = dio_pad_sleep_status_1_en_34_qs; + reg_rdata_next[3] = dio_pad_sleep_status_1_en_35_qs; + reg_rdata_next[4] = dio_pad_sleep_status_1_en_36_qs; + reg_rdata_next[5] = dio_pad_sleep_status_1_en_37_qs; + reg_rdata_next[6] = dio_pad_sleep_status_1_en_38_qs; + reg_rdata_next[7] = dio_pad_sleep_status_1_en_39_qs; + reg_rdata_next[8] = dio_pad_sleep_status_1_en_40_qs; + reg_rdata_next[9] = dio_pad_sleep_status_1_en_41_qs; + reg_rdata_next[10] = dio_pad_sleep_status_1_en_42_qs; + reg_rdata_next[11] = dio_pad_sleep_status_1_en_43_qs; + reg_rdata_next[12] = dio_pad_sleep_status_1_en_44_qs; + reg_rdata_next[13] = dio_pad_sleep_status_1_en_45_qs; + reg_rdata_next[14] = dio_pad_sleep_status_1_en_46_qs; + reg_rdata_next[15] = dio_pad_sleep_status_1_en_47_qs; + reg_rdata_next[16] = dio_pad_sleep_status_1_en_48_qs; + reg_rdata_next[17] = dio_pad_sleep_status_1_en_49_qs; + reg_rdata_next[18] = dio_pad_sleep_status_1_en_50_qs; + reg_rdata_next[19] = dio_pad_sleep_status_1_en_51_qs; + reg_rdata_next[20] = dio_pad_sleep_status_1_en_52_qs; + reg_rdata_next[21] = dio_pad_sleep_status_1_en_53_qs; + reg_rdata_next[22] = dio_pad_sleep_status_1_en_54_qs; + reg_rdata_next[23] = dio_pad_sleep_status_1_en_55_qs; + reg_rdata_next[24] = dio_pad_sleep_status_1_en_56_qs; + reg_rdata_next[25] = dio_pad_sleep_status_1_en_57_qs; + reg_rdata_next[26] = dio_pad_sleep_status_1_en_58_qs; + reg_rdata_next[27] = dio_pad_sleep_status_1_en_59_qs; + reg_rdata_next[28] = dio_pad_sleep_status_1_en_60_qs; + reg_rdata_next[29] = dio_pad_sleep_status_1_en_61_qs; + reg_rdata_next[30] = dio_pad_sleep_status_1_en_62_qs; + reg_rdata_next[31] = dio_pad_sleep_status_1_en_63_qs; + end + + addr_hit[242]: begin + reg_rdata_next[0] = dio_pad_sleep_status_2_en_64_qs; + reg_rdata_next[1] = dio_pad_sleep_status_2_en_65_qs; + reg_rdata_next[2] = dio_pad_sleep_status_2_en_66_qs; + reg_rdata_next[3] = dio_pad_sleep_status_2_en_67_qs; + reg_rdata_next[4] = dio_pad_sleep_status_2_en_68_qs; + reg_rdata_next[5] = dio_pad_sleep_status_2_en_69_qs; + reg_rdata_next[6] = dio_pad_sleep_status_2_en_70_qs; + reg_rdata_next[7] = dio_pad_sleep_status_2_en_71_qs; + reg_rdata_next[8] = dio_pad_sleep_status_2_en_72_qs; + end + + addr_hit[243]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs; + end + + addr_hit[244]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs; + end + + addr_hit[245]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs; + end + + addr_hit[246]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs; + end + + addr_hit[247]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs; + end + + addr_hit[248]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs; + end + + addr_hit[249]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs; + end + + addr_hit[250]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs; + end + + addr_hit[251]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs; + end + + addr_hit[252]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs; + end + + addr_hit[253]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs; + end + + addr_hit[254]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs; + end + + addr_hit[255]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs; + end + + addr_hit[256]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs; + end + + addr_hit[257]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs; + end + + addr_hit[258]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs; + end + + addr_hit[259]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_16_qs; + end + + addr_hit[260]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_17_qs; + end + + addr_hit[261]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_18_qs; + end + + addr_hit[262]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_19_qs; + end + + addr_hit[263]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_20_qs; + end + + addr_hit[264]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_21_qs; + end + + addr_hit[265]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_22_qs; + end + + addr_hit[266]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_23_qs; + end + + addr_hit[267]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_24_qs; + end + + addr_hit[268]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_25_qs; + end + + addr_hit[269]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_26_qs; + end + + addr_hit[270]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_27_qs; + end + + addr_hit[271]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_28_qs; + end + + addr_hit[272]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_29_qs; + end + + addr_hit[273]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_30_qs; + end + + addr_hit[274]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_31_qs; + end + + addr_hit[275]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_32_qs; + end + + addr_hit[276]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_33_qs; + end + + addr_hit[277]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_34_qs; + end + + addr_hit[278]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_35_qs; + end + + addr_hit[279]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_36_qs; + end + + addr_hit[280]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_37_qs; + end + + addr_hit[281]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_38_qs; + end + + addr_hit[282]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_39_qs; + end + + addr_hit[283]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_40_qs; + end + + addr_hit[284]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_41_qs; + end + + addr_hit[285]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_42_qs; + end + + addr_hit[286]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_43_qs; + end + + addr_hit[287]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_44_qs; + end + + addr_hit[288]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_45_qs; + end + + addr_hit[289]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_46_qs; + end + + addr_hit[290]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_47_qs; + end + + addr_hit[291]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_48_qs; + end + + addr_hit[292]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_49_qs; + end + + addr_hit[293]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_50_qs; + end + + addr_hit[294]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_51_qs; + end + + addr_hit[295]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_52_qs; + end + + addr_hit[296]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_53_qs; + end + + addr_hit[297]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_54_qs; + end + + addr_hit[298]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_55_qs; + end + + addr_hit[299]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_56_qs; + end + + addr_hit[300]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_57_qs; + end + + addr_hit[301]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_58_qs; + end + + addr_hit[302]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_59_qs; + end + + addr_hit[303]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_60_qs; + end + + addr_hit[304]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_61_qs; + end + + addr_hit[305]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_62_qs; + end + + addr_hit[306]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_63_qs; + end + + addr_hit[307]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_64_qs; + end + + addr_hit[308]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_65_qs; + end + + addr_hit[309]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_66_qs; + end + + addr_hit[310]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_67_qs; + end + + addr_hit[311]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_68_qs; + end + + addr_hit[312]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_69_qs; + end + + addr_hit[313]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_70_qs; + end + + addr_hit[314]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_71_qs; + end + + addr_hit[315]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_72_qs; + end + + addr_hit[316]: begin + reg_rdata_next[0] = dio_pad_sleep_en_0_qs; + end + + addr_hit[317]: begin + reg_rdata_next[0] = dio_pad_sleep_en_1_qs; + end + + addr_hit[318]: begin + reg_rdata_next[0] = dio_pad_sleep_en_2_qs; + end + + addr_hit[319]: begin + reg_rdata_next[0] = dio_pad_sleep_en_3_qs; + end + + addr_hit[320]: begin + reg_rdata_next[0] = dio_pad_sleep_en_4_qs; + end + + addr_hit[321]: begin + reg_rdata_next[0] = dio_pad_sleep_en_5_qs; + end + + addr_hit[322]: begin + reg_rdata_next[0] = dio_pad_sleep_en_6_qs; + end + + addr_hit[323]: begin + reg_rdata_next[0] = dio_pad_sleep_en_7_qs; + end + + addr_hit[324]: begin + reg_rdata_next[0] = dio_pad_sleep_en_8_qs; + end + + addr_hit[325]: begin + reg_rdata_next[0] = dio_pad_sleep_en_9_qs; + end + + addr_hit[326]: begin + reg_rdata_next[0] = dio_pad_sleep_en_10_qs; + end + + addr_hit[327]: begin + reg_rdata_next[0] = dio_pad_sleep_en_11_qs; + end + + addr_hit[328]: begin + reg_rdata_next[0] = dio_pad_sleep_en_12_qs; + end + + addr_hit[329]: begin + reg_rdata_next[0] = dio_pad_sleep_en_13_qs; + end + + addr_hit[330]: begin + reg_rdata_next[0] = dio_pad_sleep_en_14_qs; + end + + addr_hit[331]: begin + reg_rdata_next[0] = dio_pad_sleep_en_15_qs; + end + + addr_hit[332]: begin + reg_rdata_next[0] = dio_pad_sleep_en_16_qs; + end + + addr_hit[333]: begin + reg_rdata_next[0] = dio_pad_sleep_en_17_qs; + end + + addr_hit[334]: begin + reg_rdata_next[0] = dio_pad_sleep_en_18_qs; + end + + addr_hit[335]: begin + reg_rdata_next[0] = dio_pad_sleep_en_19_qs; + end + + addr_hit[336]: begin + reg_rdata_next[0] = dio_pad_sleep_en_20_qs; + end + + addr_hit[337]: begin + reg_rdata_next[0] = dio_pad_sleep_en_21_qs; + end + + addr_hit[338]: begin + reg_rdata_next[0] = dio_pad_sleep_en_22_qs; + end + + addr_hit[339]: begin + reg_rdata_next[0] = dio_pad_sleep_en_23_qs; + end + + addr_hit[340]: begin + reg_rdata_next[0] = dio_pad_sleep_en_24_qs; + end + + addr_hit[341]: begin + reg_rdata_next[0] = dio_pad_sleep_en_25_qs; + end + + addr_hit[342]: begin + reg_rdata_next[0] = dio_pad_sleep_en_26_qs; + end + + addr_hit[343]: begin + reg_rdata_next[0] = dio_pad_sleep_en_27_qs; + end + + addr_hit[344]: begin + reg_rdata_next[0] = dio_pad_sleep_en_28_qs; + end + + addr_hit[345]: begin + reg_rdata_next[0] = dio_pad_sleep_en_29_qs; + end + + addr_hit[346]: begin + reg_rdata_next[0] = dio_pad_sleep_en_30_qs; + end + + addr_hit[347]: begin + reg_rdata_next[0] = dio_pad_sleep_en_31_qs; + end + + addr_hit[348]: begin + reg_rdata_next[0] = dio_pad_sleep_en_32_qs; + end + + addr_hit[349]: begin + reg_rdata_next[0] = dio_pad_sleep_en_33_qs; + end + + addr_hit[350]: begin + reg_rdata_next[0] = dio_pad_sleep_en_34_qs; + end + + addr_hit[351]: begin + reg_rdata_next[0] = dio_pad_sleep_en_35_qs; + end + + addr_hit[352]: begin + reg_rdata_next[0] = dio_pad_sleep_en_36_qs; + end + + addr_hit[353]: begin + reg_rdata_next[0] = dio_pad_sleep_en_37_qs; + end + + addr_hit[354]: begin + reg_rdata_next[0] = dio_pad_sleep_en_38_qs; + end + + addr_hit[355]: begin + reg_rdata_next[0] = dio_pad_sleep_en_39_qs; + end + + addr_hit[356]: begin + reg_rdata_next[0] = dio_pad_sleep_en_40_qs; + end + + addr_hit[357]: begin + reg_rdata_next[0] = dio_pad_sleep_en_41_qs; + end + + addr_hit[358]: begin + reg_rdata_next[0] = dio_pad_sleep_en_42_qs; + end + + addr_hit[359]: begin + reg_rdata_next[0] = dio_pad_sleep_en_43_qs; + end + + addr_hit[360]: begin + reg_rdata_next[0] = dio_pad_sleep_en_44_qs; + end + + addr_hit[361]: begin + reg_rdata_next[0] = dio_pad_sleep_en_45_qs; + end + + addr_hit[362]: begin + reg_rdata_next[0] = dio_pad_sleep_en_46_qs; + end + + addr_hit[363]: begin + reg_rdata_next[0] = dio_pad_sleep_en_47_qs; + end + + addr_hit[364]: begin + reg_rdata_next[0] = dio_pad_sleep_en_48_qs; + end + + addr_hit[365]: begin + reg_rdata_next[0] = dio_pad_sleep_en_49_qs; + end + + addr_hit[366]: begin + reg_rdata_next[0] = dio_pad_sleep_en_50_qs; + end + + addr_hit[367]: begin + reg_rdata_next[0] = dio_pad_sleep_en_51_qs; + end + + addr_hit[368]: begin + reg_rdata_next[0] = dio_pad_sleep_en_52_qs; + end + + addr_hit[369]: begin + reg_rdata_next[0] = dio_pad_sleep_en_53_qs; + end + + addr_hit[370]: begin + reg_rdata_next[0] = dio_pad_sleep_en_54_qs; + end + + addr_hit[371]: begin + reg_rdata_next[0] = dio_pad_sleep_en_55_qs; + end + + addr_hit[372]: begin + reg_rdata_next[0] = dio_pad_sleep_en_56_qs; + end + + addr_hit[373]: begin + reg_rdata_next[0] = dio_pad_sleep_en_57_qs; + end + + addr_hit[374]: begin + reg_rdata_next[0] = dio_pad_sleep_en_58_qs; + end + + addr_hit[375]: begin + reg_rdata_next[0] = dio_pad_sleep_en_59_qs; + end + + addr_hit[376]: begin + reg_rdata_next[0] = dio_pad_sleep_en_60_qs; + end + + addr_hit[377]: begin + reg_rdata_next[0] = dio_pad_sleep_en_61_qs; + end + + addr_hit[378]: begin + reg_rdata_next[0] = dio_pad_sleep_en_62_qs; + end + + addr_hit[379]: begin + reg_rdata_next[0] = dio_pad_sleep_en_63_qs; + end + + addr_hit[380]: begin + reg_rdata_next[0] = dio_pad_sleep_en_64_qs; + end + + addr_hit[381]: begin + reg_rdata_next[0] = dio_pad_sleep_en_65_qs; + end + + addr_hit[382]: begin + reg_rdata_next[0] = dio_pad_sleep_en_66_qs; + end + + addr_hit[383]: begin + reg_rdata_next[0] = dio_pad_sleep_en_67_qs; + end + + addr_hit[384]: begin + reg_rdata_next[0] = dio_pad_sleep_en_68_qs; + end + + addr_hit[385]: begin + reg_rdata_next[0] = dio_pad_sleep_en_69_qs; + end + + addr_hit[386]: begin + reg_rdata_next[0] = dio_pad_sleep_en_70_qs; + end + + addr_hit[387]: begin + reg_rdata_next[0] = dio_pad_sleep_en_71_qs; + end + + addr_hit[388]: begin + reg_rdata_next[0] = dio_pad_sleep_en_72_qs; + end + + addr_hit[389]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs; + end + + addr_hit[390]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs; + end + + addr_hit[391]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs; + end + + addr_hit[392]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs; + end + + addr_hit[393]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs; + end + + addr_hit[394]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs; + end + + addr_hit[395]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs; + end + + addr_hit[396]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs; + end + + addr_hit[397]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs; + end + + addr_hit[398]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs; + end + + addr_hit[399]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs; + end + + addr_hit[400]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs; + end + + addr_hit[401]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs; + end + + addr_hit[402]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs; + end + + addr_hit[403]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs; + end + + addr_hit[404]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs; + end + + addr_hit[405]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_16_qs; + end + + addr_hit[406]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_17_qs; + end + + addr_hit[407]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_18_qs; + end + + addr_hit[408]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_19_qs; + end + + addr_hit[409]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_20_qs; + end + + addr_hit[410]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_21_qs; + end + + addr_hit[411]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_22_qs; + end + + addr_hit[412]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_23_qs; + end + + addr_hit[413]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_24_qs; + end + + addr_hit[414]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_25_qs; + end + + addr_hit[415]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_26_qs; + end + + addr_hit[416]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_27_qs; + end + + addr_hit[417]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_28_qs; + end + + addr_hit[418]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_29_qs; + end + + addr_hit[419]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_30_qs; + end + + addr_hit[420]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_31_qs; + end + + addr_hit[421]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_32_qs; + end + + addr_hit[422]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_33_qs; + end + + addr_hit[423]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_34_qs; + end + + addr_hit[424]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_35_qs; + end + + addr_hit[425]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_36_qs; + end + + addr_hit[426]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_37_qs; + end + + addr_hit[427]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_38_qs; + end + + addr_hit[428]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_39_qs; + end + + addr_hit[429]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_40_qs; + end + + addr_hit[430]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_41_qs; + end + + addr_hit[431]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_42_qs; + end + + addr_hit[432]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_43_qs; + end + + addr_hit[433]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_44_qs; + end + + addr_hit[434]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_45_qs; + end + + addr_hit[435]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_46_qs; + end + + addr_hit[436]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_47_qs; + end + + addr_hit[437]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_48_qs; + end + + addr_hit[438]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_49_qs; + end + + addr_hit[439]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_50_qs; + end + + addr_hit[440]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_51_qs; + end + + addr_hit[441]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_52_qs; + end + + addr_hit[442]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_53_qs; + end + + addr_hit[443]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_54_qs; + end + + addr_hit[444]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_55_qs; + end + + addr_hit[445]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_56_qs; + end + + addr_hit[446]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_57_qs; + end + + addr_hit[447]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_58_qs; + end + + addr_hit[448]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_59_qs; + end + + addr_hit[449]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_60_qs; + end + + addr_hit[450]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_61_qs; + end + + addr_hit[451]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_62_qs; + end + + addr_hit[452]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_63_qs; + end + + addr_hit[453]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_64_qs; + end + + addr_hit[454]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_65_qs; + end + + addr_hit[455]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_66_qs; + end + + addr_hit[456]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_67_qs; + end + + addr_hit[457]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_68_qs; + end + + addr_hit[458]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_69_qs; + end + + addr_hit[459]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_70_qs; + end + + addr_hit[460]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_71_qs; + end + + addr_hit[461]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_72_qs; + end + + addr_hit[462]: begin + reg_rdata_next[0] = wkup_detector_regwen_0_qs; + end + + addr_hit[463]: begin + reg_rdata_next[0] = wkup_detector_regwen_1_qs; + end + + addr_hit[464]: begin + reg_rdata_next[0] = wkup_detector_regwen_2_qs; + end + + addr_hit[465]: begin + reg_rdata_next[0] = wkup_detector_regwen_3_qs; + end + + addr_hit[466]: begin + reg_rdata_next[0] = wkup_detector_regwen_4_qs; + end + + addr_hit[467]: begin + reg_rdata_next[0] = wkup_detector_regwen_5_qs; + end + + addr_hit[468]: begin + reg_rdata_next[0] = wkup_detector_regwen_6_qs; + end + + addr_hit[469]: begin + reg_rdata_next[0] = wkup_detector_regwen_7_qs; + end + + addr_hit[470]: begin + reg_rdata_next = DW'(wkup_detector_en_0_qs); + end + addr_hit[471]: begin + reg_rdata_next = DW'(wkup_detector_en_1_qs); + end + addr_hit[472]: begin + reg_rdata_next = DW'(wkup_detector_en_2_qs); + end + addr_hit[473]: begin + reg_rdata_next = DW'(wkup_detector_en_3_qs); + end + addr_hit[474]: begin + reg_rdata_next = DW'(wkup_detector_en_4_qs); + end + addr_hit[475]: begin + reg_rdata_next = DW'(wkup_detector_en_5_qs); + end + addr_hit[476]: begin + reg_rdata_next = DW'(wkup_detector_en_6_qs); + end + addr_hit[477]: begin + reg_rdata_next = DW'(wkup_detector_en_7_qs); + end + addr_hit[478]: begin + reg_rdata_next = DW'(wkup_detector_0_qs); + end + addr_hit[479]: begin + reg_rdata_next = DW'(wkup_detector_1_qs); + end + addr_hit[480]: begin + reg_rdata_next = DW'(wkup_detector_2_qs); + end + addr_hit[481]: begin + reg_rdata_next = DW'(wkup_detector_3_qs); + end + addr_hit[482]: begin + reg_rdata_next = DW'(wkup_detector_4_qs); + end + addr_hit[483]: begin + reg_rdata_next = DW'(wkup_detector_5_qs); + end + addr_hit[484]: begin + reg_rdata_next = DW'(wkup_detector_6_qs); + end + addr_hit[485]: begin + reg_rdata_next = DW'(wkup_detector_7_qs); + end + addr_hit[486]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_0_qs); + end + addr_hit[487]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_1_qs); + end + addr_hit[488]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_2_qs); + end + addr_hit[489]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_3_qs); + end + addr_hit[490]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_4_qs); + end + addr_hit[491]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_5_qs); + end + addr_hit[492]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_6_qs); + end + addr_hit[493]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_7_qs); + end + addr_hit[494]: begin + reg_rdata_next[5:0] = wkup_detector_padsel_0_qs; + end + + addr_hit[495]: begin + reg_rdata_next[5:0] = wkup_detector_padsel_1_qs; + end + + addr_hit[496]: begin + reg_rdata_next[5:0] = wkup_detector_padsel_2_qs; + end + + addr_hit[497]: begin + reg_rdata_next[5:0] = wkup_detector_padsel_3_qs; + end + + addr_hit[498]: begin + reg_rdata_next[5:0] = wkup_detector_padsel_4_qs; + end + + addr_hit[499]: begin + reg_rdata_next[5:0] = wkup_detector_padsel_5_qs; + end + + addr_hit[500]: begin + reg_rdata_next[5:0] = wkup_detector_padsel_6_qs; + end + + addr_hit[501]: begin + reg_rdata_next[5:0] = wkup_detector_padsel_7_qs; + end + + addr_hit[502]: begin + reg_rdata_next = DW'(wkup_cause_qs); + end + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + logic reg_busy_sel; + assign reg_busy = reg_busy_sel | shadow_busy; + always_comb begin + reg_busy_sel = '0; + unique case (1'b1) + addr_hit[470]: begin + reg_busy_sel = wkup_detector_en_0_busy; + end + addr_hit[471]: begin + reg_busy_sel = wkup_detector_en_1_busy; + end + addr_hit[472]: begin + reg_busy_sel = wkup_detector_en_2_busy; + end + addr_hit[473]: begin + reg_busy_sel = wkup_detector_en_3_busy; + end + addr_hit[474]: begin + reg_busy_sel = wkup_detector_en_4_busy; + end + addr_hit[475]: begin + reg_busy_sel = wkup_detector_en_5_busy; + end + addr_hit[476]: begin + reg_busy_sel = wkup_detector_en_6_busy; + end + addr_hit[477]: begin + reg_busy_sel = wkup_detector_en_7_busy; + end + addr_hit[478]: begin + reg_busy_sel = wkup_detector_0_busy; + end + addr_hit[479]: begin + reg_busy_sel = wkup_detector_1_busy; + end + addr_hit[480]: begin + reg_busy_sel = wkup_detector_2_busy; + end + addr_hit[481]: begin + reg_busy_sel = wkup_detector_3_busy; + end + addr_hit[482]: begin + reg_busy_sel = wkup_detector_4_busy; + end + addr_hit[483]: begin + reg_busy_sel = wkup_detector_5_busy; + end + addr_hit[484]: begin + reg_busy_sel = wkup_detector_6_busy; + end + addr_hit[485]: begin + reg_busy_sel = wkup_detector_7_busy; + end + addr_hit[486]: begin + reg_busy_sel = wkup_detector_cnt_th_0_busy; + end + addr_hit[487]: begin + reg_busy_sel = wkup_detector_cnt_th_1_busy; + end + addr_hit[488]: begin + reg_busy_sel = wkup_detector_cnt_th_2_busy; + end + addr_hit[489]: begin + reg_busy_sel = wkup_detector_cnt_th_3_busy; + end + addr_hit[490]: begin + reg_busy_sel = wkup_detector_cnt_th_4_busy; + end + addr_hit[491]: begin + reg_busy_sel = wkup_detector_cnt_th_5_busy; + end + addr_hit[492]: begin + reg_busy_sel = wkup_detector_cnt_th_6_busy; + end + addr_hit[493]: begin + reg_busy_sel = wkup_detector_cnt_th_7_busy; + end + addr_hit[502]: begin + reg_busy_sel = wkup_cause_busy; + end + default: begin + reg_busy_sel = '0; + end + endcase + end + + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_strap_sampling.sv b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_strap_sampling.sv new file mode 100644 index 0000000000000..0320a72dc8e4e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_strap_sampling.sv @@ -0,0 +1,452 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module pinmux_strap_sampling + import pinmux_pkg::*; + import pinmux_reg_pkg::*; + import prim_pad_wrapper_pkg::*; + import lc_ctrl_pkg::*; +#( + // Taget-specific pinmux configuration passed down from the + // target-specific top-level. + parameter target_cfg_t TargetCfg = DefaultTargetCfg +) ( + input clk_i, + input rst_ni, + input prim_mubi_pkg::mubi4_t scanmode_i, + // To padring side + output pad_attr_t [NumIOs-1:0] attr_padring_o, + output logic [NumIOs-1:0] out_padring_o, + output logic [NumIOs-1:0] oe_padring_o, + input logic [NumIOs-1:0] in_padring_i, + // To core side + input pad_attr_t [NumIOs-1:0] attr_core_i, + input logic [NumIOs-1:0] out_core_i, + input logic [NumIOs-1:0] oe_core_i, + output logic [NumIOs-1:0] in_core_o, + // Used for TAP qualification + input logic strap_en_i, + input lc_tx_t lc_dft_en_i, + input lc_tx_t lc_hw_debug_en_i, + input lc_tx_t lc_check_byp_en_i, + input lc_tx_t lc_escalate_en_i, + output lc_tx_t pinmux_hw_debug_en_o, + // Sampled values for DFT straps + output dft_strap_test_req_t dft_strap_test_o, + // Hold tap strap select + input dft_hold_tap_sel_i, + // Qualified JTAG signals for TAPs + output jtag_pkg::jtag_req_t lc_jtag_o, + input jtag_pkg::jtag_rsp_t lc_jtag_i, + output jtag_pkg::jtag_req_t rv_jtag_o, + input jtag_pkg::jtag_rsp_t rv_jtag_i, + output jtag_pkg::jtag_req_t dft_jtag_o, + input jtag_pkg::jtag_rsp_t dft_jtag_i +); + + + ///////////////////////////////////// + // Life cycle signal synchronizers // + ///////////////////////////////////// + + prim_mubi_pkg::mubi4_t [0:0] scanmode; + + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) // clock/reset below is only used for SVAs. + ) u_por_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o(scanmode) + ); + + typedef enum logic [1:0] { + DftEnSample, + DftEnTapSel, + DftEnLast + } lc_dft_en_e; + + lc_tx_t [DftEnLast-1:0] lc_dft_en; + prim_lc_sync #( + .NumCopies(int'(DftEnLast)) + ) u_prim_lc_sync_lc_dft_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_dft_en_i), + .lc_en_o(lc_dft_en) + ); + lc_tx_t [0:0] lc_hw_debug_en; + prim_lc_sync #( + .NumCopies(1) + ) u_prim_lc_sync_lc_hw_debug_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_hw_debug_en_i), + .lc_en_o(lc_hw_debug_en) + ); + lc_tx_t [0:0] lc_check_byp_en; + prim_lc_sync #( + .NumCopies(1) + ) u_prim_lc_sync_lc_check_byp_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_check_byp_en_i), + .lc_en_o(lc_check_byp_en) + ); + lc_tx_t [0:0] lc_escalate_en; + prim_lc_sync #( + .NumCopies(1) + ) u_prim_lc_sync_lc_escalate_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_escalate_en_i), + .lc_en_o(lc_escalate_en) + ); + + + ///////////////////////////// + // LC_HW_DEBUG_EN Latching // + ///////////////////////////// + + // In order to keep a RV_DM JTAG debug session alive during NDM reset, we need to memorize the + // state of lc_hw_debug_en, since OTP/LC will be reset as part of NDM reset (the only parts not + // reset are in the pwr/rst/clkmgrs, RV_DM and this strap sampling module). We sample the life + // cycle signal state when the strap sampling pulse is asserted bu the PWRMGR. This pulse is + // asserted once during boot (and not after an NDM reset). + // + // Note that DFT TAP selection is not affected by this since we always consume the life value for + // lc_dft_en. We also make sure to invalidate the sampled lc_hw_debug_en whenever lc_check_byp_en + // or lc_escalate_en are not OFF. lc_escalate_en is asserted as part of an escalation, and + // lc_check_byp_en is asserted whenever a life cycle transition is initiated (it causes the OTP + // controller to skip background checks on the life cycle partition as it undergoes + // modification). This makes sure that the sampled value here does not survive a life cycle + // transition. + // + // Finally, note that there is secondary gating on the RV_DM and DFT TAPs that is always consuming + // live lc_hw_debug_en and lc_dft_en signals for added protection. + + // Convert the strap enable pulse to a mubi signal and mask lc_hw_debug_en with it. + lc_tx_t lc_strap_en, lc_hw_debug_en_masked; + assign lc_strap_en = lc_tx_bool_to_lc_tx(strap_en_i); + assign lc_hw_debug_en_masked = lc_tx_and_hi(lc_strap_en, lc_hw_debug_en[0]); + + // Output ON if + // - If the strap sampling pulse is asserted and lc_hw_debug_en is ON + // - If the pinmux_hw_debug_en_q is already set to ON (this is the latching feedback loop) + // Note: make sure we use a hardened, rectifying OR function since otherwise two non-strict + // values may produce a strict ON value. + lc_tx_t hw_debug_en_set, pinmux_hw_debug_en_q; + prim_lc_or_hardened #( + .ActVal(On) + ) u_prim_lc_or_hardened ( + .clk_i, + .rst_ni, + .lc_en_a_i(lc_hw_debug_en_masked), + .lc_en_b_i(pinmux_hw_debug_en_q), + .lc_en_o (hw_debug_en_set) + ); + + // Output ON if both lc_check_byp_en and lc_escalate_en are set to OFF. + lc_tx_t hw_debug_en_gating; + assign hw_debug_en_gating = lc_tx_inv(lc_tx_and_lo(lc_check_byp_en[0], lc_escalate_en[0])); + + // Gate the hw_debug_en_set signal and feed it into the latching flop. + lc_tx_t pinmux_hw_debug_en_d; + assign pinmux_hw_debug_en_d = lc_tx_and_hi(hw_debug_en_set, hw_debug_en_gating); + + prim_lc_sender u_prim_lc_sender_pinmux_hw_debug_en ( + .clk_i, + .rst_ni, + .lc_en_i(pinmux_hw_debug_en_d), + .lc_en_o(pinmux_hw_debug_en_q) + ); + + typedef enum logic [1:0] { + HwDebugEnSample, + HwDebugEnTapSel, + HwDebugEnRvDmOut, + HwDebugEnLast + } pinmux_hw_debug_en_e; + + lc_tx_t [HwDebugEnLast-1:0] pinmux_hw_debug_en; + prim_lc_sync #( + .NumCopies(int'(HwDebugEnLast)), + .AsyncOn(0) // no sync needed + ) u_prim_lc_sync_pinmux_hw_debug_en ( + .clk_i, + .rst_ni, + .lc_en_i(pinmux_hw_debug_en_q), + .lc_en_o(pinmux_hw_debug_en) + ); + + // We send this latched version over to the RV_DM in order to gate the JTAG signals and TAP side. + // Note that the bus side will remain gated with the live lc_hw_debug_en value inside RV_DM. + assign pinmux_hw_debug_en_o = pinmux_hw_debug_en[HwDebugEnRvDmOut]; + + // Check that we can correctly latch upon strap_en_i + `ASSERT(LcHwDebugEnSet_A, + (lc_tx_test_true_strict(lc_hw_debug_en[0]) || + lc_tx_test_true_strict(pinmux_hw_debug_en_q)) && + lc_tx_test_false_strict(lc_check_byp_en[0]) && + lc_tx_test_false_strict(lc_escalate_en[0]) && + strap_en_i + |=> + lc_tx_test_true_strict(pinmux_hw_debug_en_q)) + // Check that latching ON can only occur if lc_hw_debug_en_i is set. + `ASSERT(LcHwDebugEnSetRev0_A, + lc_tx_test_false_loose(pinmux_hw_debug_en_q) ##1 + lc_tx_test_true_strict(pinmux_hw_debug_en_q) + |-> + $past(lc_tx_test_true_strict(lc_hw_debug_en[0]))) + // Check that latching ON can only occur if strap_en_i is set. + `ASSERT(LcHwDebugEnSetRev1_A, + lc_tx_test_false_loose(pinmux_hw_debug_en_q) ##1 + lc_tx_test_true_strict(pinmux_hw_debug_en_q) + |-> + $past(strap_en_i)) + // Check that any non-OFF value on lc_check_byp_en_i and + // lc_escalate_en_i clears the latched value. + `ASSERT(LcHwDebugEnClear_A, + lc_tx_test_true_loose(lc_check_byp_en[0]) || + lc_tx_test_true_loose(lc_escalate_en[0]) + |=> + lc_tx_test_false_loose(pinmux_hw_debug_en_q)) + + ////////////////////////// + // Strap Sampling Logic // + ////////////////////////// + + logic dft_strap_valid_d, dft_strap_valid_q; + logic lc_strap_sample_en, rv_strap_sample_en, dft_strap_sample_en; + logic [NTapStraps-1:0] tap_strap_d, tap_strap_q; + logic [NDFTStraps-1:0] dft_strap_d, dft_strap_q; + + // The LC strap at index 0 has a slightly different + // enable condition than the DFT strap at index 1. + assign tap_strap_d[0] = (lc_strap_sample_en) ? in_padring_i[TargetCfg.tap_strap0_idx] : + tap_strap_q[0]; + assign tap_strap_d[1] = (rv_strap_sample_en) ? in_padring_i[TargetCfg.tap_strap1_idx] : + tap_strap_q[1]; + + // We're always using the DFT strap sample enable for the DFT straps. + assign dft_strap_d = (dft_strap_sample_en) ? {in_padring_i[TargetCfg.dft_strap1_idx], + in_padring_i[TargetCfg.dft_strap0_idx]} : + dft_strap_q; + + assign dft_strap_valid_d = dft_strap_sample_en | dft_strap_valid_q; + assign dft_strap_test_o.valid = dft_strap_valid_q; + assign dft_strap_test_o.straps = dft_strap_q; + + + // During dft enabled states, we continously sample all straps unless + // told not to do so by external dft logic + logic tap_sampling_en; + logic dft_hold_tap_sel; + // Delay the strap sampling pulse by one cycle so that the pinmux_hw_debug_en above can + // propagate through the pinmux_hw_debug_en_q flop. + logic strap_en_q; + + prim_buf #( + .Width(1) + ) u_buf_hold_tap ( + .in_i(dft_hold_tap_sel_i), + .out_o(dft_hold_tap_sel) + ); + assign tap_sampling_en = lc_tx_test_true_strict(lc_dft_en[DftEnSample]) & ~dft_hold_tap_sel; + + always_comb begin : p_strap_sampling + lc_strap_sample_en = 1'b0; + rv_strap_sample_en = 1'b0; + dft_strap_sample_en = 1'b0; + // Initial strap sampling pulse from pwrmgr, + // qualified by life cycle signals. + // The DFT-mode straps are always sampled only once. + if (strap_en_q && tap_sampling_en) begin + dft_strap_sample_en = 1'b1; + end + // In DFT-enabled life cycle states we continously + // sample the TAP straps to be able to switch back and + // forth between different TAPs. + if (strap_en_q || tap_sampling_en) begin + lc_strap_sample_en = 1'b1; + if (lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnSample])) begin + rv_strap_sample_en = 1'b1; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_strap_sample + if (!rst_ni) begin + tap_strap_q <= '0; + dft_strap_q <= '0; + dft_strap_valid_q <= 1'b0; + strap_en_q <= 1'b0; + end else begin + tap_strap_q <= tap_strap_d; + dft_strap_q <= dft_strap_d; + dft_strap_valid_q <= dft_strap_valid_d; + strap_en_q <= strap_en_i; + end + end + + /////////////////////// + // TAP Selection Mux // + /////////////////////// + + logic jtag_en; + tap_strap_t tap_strap; + jtag_pkg::jtag_req_t jtag_req, lc_jtag_req, rv_jtag_req, dft_jtag_req; + jtag_pkg::jtag_rsp_t jtag_rsp, lc_jtag_rsp, rv_jtag_rsp, dft_jtag_rsp; + + // This muxes the JTAG signals to the correct TAP, based on the + // sampled straps. Further, the individual JTAG signals are gated + // using the corresponding life cycle signal. + assign tap_strap = tap_strap_t'(tap_strap_q); + `ASSERT_KNOWN(TapStrapKnown_A, tap_strap) + + always_comb begin : p_tap_mux + jtag_rsp = '0; + // Note that this holds the JTAGs in reset + // when they are not selected. + lc_jtag_req = '0; + rv_jtag_req = '0; + dft_jtag_req = '0; + // This activates the TDO override further below. + jtag_en = 1'b0; + + unique case (tap_strap) + LcTapSel: begin + lc_jtag_req = jtag_req; + jtag_rsp = lc_jtag_rsp; + jtag_en = 1'b1; + end + RvTapSel: begin + if (lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnTapSel])) begin + rv_jtag_req = jtag_req; + jtag_rsp = rv_jtag_rsp; + jtag_en = 1'b1; + end + end + DftTapSel: begin + if (lc_tx_test_true_strict(lc_dft_en[DftEnTapSel])) begin + dft_jtag_req = jtag_req; + jtag_rsp = dft_jtag_rsp; + jtag_en = 1'b1; + end + end + default: ; + endcase // tap_strap_t'(tap_strap_q) + end + + // Insert hand instantiated buffers for + // these signals to prevent further optimization. + pinmux_jtag_buf u_pinmux_jtag_buf_lc ( + .req_i(lc_jtag_req), + .req_o(lc_jtag_o), + .rsp_i(lc_jtag_i), + .rsp_o(lc_jtag_rsp) + ); + pinmux_jtag_buf u_pinmux_jtag_buf_rv ( + .req_i(rv_jtag_req), + .req_o(rv_jtag_o), + .rsp_i(rv_jtag_i), + .rsp_o(rv_jtag_rsp) + ); + pinmux_jtag_buf u_pinmux_jtag_buf_dft ( + .req_i(dft_jtag_req), + .req_o(dft_jtag_o), + .rsp_i(dft_jtag_i), + .rsp_o(dft_jtag_rsp) + ); + + ////////////////////// + // TAP Input Muxes // + ////////////////////// + + // Inputs connections + assign jtag_req.tck = in_padring_i[TargetCfg.tck_idx]; + assign jtag_req.tms = in_padring_i[TargetCfg.tms_idx]; + assign jtag_req.tdi = in_padring_i[TargetCfg.tdi_idx]; + + // Note that this resets the selected TAP controller in + // scanmode. If the TAP controller needs to be active during + // reset, this reset bypass needs to be adapted accordingly. + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_por_aon_n_mux ( + .clk0_i(in_padring_i[TargetCfg.trst_idx]), + .clk1_i(rst_ni), + .sel_i(prim_mubi_pkg::mubi4_test_true_strict(scanmode[0])), + .clk_o(jtag_req.trst_n) + ); + + // Input tie-off muxes and output overrides + for (genvar k = 0; k < NumIOs; k++) begin : gen_input_tie_off + if (k == TargetCfg.tck_idx || + k == TargetCfg.tms_idx || + k == TargetCfg.trst_idx || + k == TargetCfg.tdi_idx || + k == TargetCfg.tdo_idx) begin : gen_jtag_signal + + // Tie off inputs. + assign in_core_o[k] = (jtag_en) ? 1'b0 : in_padring_i[k]; + + if (k == TargetCfg.tdo_idx) begin : gen_output_mux + // Override TDO output. + assign out_padring_o[k] = (jtag_en) ? jtag_rsp.tdo : out_core_i[k]; + assign oe_padring_o[k] = (jtag_en) ? jtag_rsp.tdo_oe : oe_core_i[k]; + end else begin : gen_output_tie_off + // Make sure these pads are set to high-z. + assign out_padring_o[k] = (jtag_en) ? 1'b0 : out_core_i[k]; + assign oe_padring_o[k] = (jtag_en) ? 1'b0 : oe_core_i[k]; + end + + // Also reset all corresponding pad attributes to the default ('0) when JTAG is enabled. + // This disables functional pad features that may have been set, e.g., pull-up/pull-down. + // Do enable schmitt trigger on JTAG clock and JTAG reset for better signal integrity. + if (k == TargetCfg.tck_idx || k == TargetCfg.trst_idx) begin : gen_schmitt_en + assign attr_padring_o[k] = (jtag_en) ? '{schmitt_en: 1'b1, default: '0} : attr_core_i[k]; + end else begin : gen_no_schmitt + assign attr_padring_o[k] = (jtag_en) ? '0 : attr_core_i[k]; + end + end else begin : gen_other_inputs + assign attr_padring_o[k] = attr_core_i[k]; + assign in_core_o[k] = in_padring_i[k]; + assign out_padring_o[k] = out_core_i[k]; + assign oe_padring_o[k] = oe_core_i[k]; + end + end + + //////////////// + // Assertions // + //////////////// + + `ASSERT_INIT(tck_idxRange_A, TargetCfg.tck_idx >= 0 && TargetCfg.tck_idx < NumIOs) + `ASSERT_INIT(tms_idxRange_A, TargetCfg.tms_idx >= 0 && TargetCfg.tms_idx < NumIOs) + `ASSERT_INIT(trst_idxRange_A, TargetCfg.trst_idx >= 0 && TargetCfg.trst_idx < NumIOs) + `ASSERT_INIT(tdi_idxRange_A, TargetCfg.tdi_idx >= 0 && TargetCfg.tdi_idx < NumIOs) + `ASSERT_INIT(tdo_idxRange_A, TargetCfg.tdo_idx >= 0 && TargetCfg.tdo_idx < NumIOs) + + `ASSERT_INIT(tap_strap0_idxRange_A, TargetCfg.tap_strap0_idx >= 0 && + TargetCfg.tap_strap0_idx < NumIOs) + `ASSERT_INIT(tap_strap1_idxRange_A, TargetCfg.tap_strap1_idx >= 0 && + TargetCfg.tap_strap1_idx < NumIOs) + `ASSERT_INIT(dft_strap0_idxRange_A, TargetCfg.dft_strap0_idx >= 0 && + TargetCfg.dft_strap0_idx < NumIOs) + `ASSERT_INIT(dft_strap1_idxRange_A, TargetCfg.dft_strap1_idx >= 0 && + TargetCfg.dft_strap1_idx < NumIOs) + + `ASSERT(RvTapOff0_A, lc_hw_debug_en_i == Off ##2 strap_en_i && pinmux_hw_debug_en_q == Off + |=> rv_jtag_o == '0) + `ASSERT(RvTapOff1_A, pinmux_hw_debug_en[0] == Off |-> rv_jtag_o == '0) + `ASSERT(DftTapOff0_A, lc_dft_en_i == Off |-> ##2 dft_jtag_o == '0) + + // These assumptions are only used in FPV. They will cause failures in simulations. + `ASSUME_FPV(RvTapOff2_A, lc_hw_debug_en_i == Off ##2 strap_en_i && pinmux_hw_debug_en_q == Off + |=> rv_jtag_i == '0) + `ASSUME_FPV(RvTapOff3_A, pinmux_hw_debug_en[0] == Off |-> rv_jtag_i == '0) + `ASSUME_FPV(DftTapOff1_A, lc_dft_en_i == Off |-> ##2 dft_jtag_i == '0) + +endmodule : pinmux_strap_sampling diff --git a/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_wkup.sv b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_wkup.sv new file mode 100644 index 0000000000000..b8b9a04b71e90 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux_wkup.sv @@ -0,0 +1,91 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module pinmux_wkup + import pinmux_pkg::*; + import pinmux_reg_pkg::*; +#( + parameter int Cycles = 4 +) ( + input clk_i, + input rst_ni, + input wkup_en_i, + input filter_en_i, + input wkup_mode_e wkup_mode_i, + input [WkupCntWidth-1:0] wkup_cnt_th_i, + input pin_value_i, + // Wakeup request pulse signal + output logic aon_wkup_pulse_o +); + + //////////////////////////// + // Optional Signal Filter // + //////////////////////////// + + // This uses a lower value for filtering than GPIO since the always-on clock is slower. If the + // filter is disabled, this reduces to a plain 2-stage flop synchronizer. + logic filter_out_d, filter_out_q; + prim_filter #( + .AsyncOn(1), // Instantiate 2-stage synchronizer + .Cycles(Cycles) + ) u_prim_filter ( + .clk_i, + .rst_ni, + .enable_i(filter_en_i), + .filter_i(pin_value_i), + .filter_o(filter_out_d) + ); + + ////////////////////// + // Pattern Matching // + ////////////////////// + + logic rising, falling; + assign falling = ~filter_out_d & filter_out_q; + assign rising = filter_out_d & ~filter_out_q; + + logic cnt_en, cnt_eq_th; + logic [WkupCntWidth-1:0] cnt_d, cnt_q; + assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; + + assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); + + always_comb begin : p_mode + aon_wkup_pulse_o = 1'b0; + cnt_en = 1'b0; + if (wkup_en_i) begin + unique case (wkup_mode_i) + Negedge: begin + aon_wkup_pulse_o = falling; + end + Edge: begin + aon_wkup_pulse_o = rising | falling; + end + HighTimed: begin + cnt_en = filter_out_d; + aon_wkup_pulse_o = cnt_eq_th; + end + LowTimed: begin + cnt_en = ~filter_out_d; + aon_wkup_pulse_o = cnt_eq_th; + end + // Default to rising + default: begin + aon_wkup_pulse_o = rising; + end + endcase + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern + if (!rst_ni) begin + filter_out_q <= 1'b0; + cnt_q <= '0; + end else begin + filter_out_q <= filter_out_d; + cnt_q <= cnt_d; + end + end + +endmodule : pinmux_wkup diff --git a/hw/top_darjeeling/ip_autogen/pinmux/syn/constraints.sdc b/hw/top_darjeeling/ip_autogen/pinmux/syn/constraints.sdc new file mode 100644 index 0000000000000..4ca2bfef15cab --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/syn/constraints.sdc @@ -0,0 +1,58 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Generic constraints file for simple testsynthesis flow + +# note that we do not fix hold timing in this flow +set SETUP_CLOCK_UNCERTAINTY 0.5 + +##################### +# main clock # +##################### +set MAIN_CLK_PIN clk_i +set MAIN_RST_PIN rst_ni +set AON_CLK_PIN clk_aon_i + + +# set main clock to 125 MHz +set MAIN_TCK 8.0 +set_ideal_network ${MAIN_CLK_PIN} +set_ideal_network ${MAIN_RST_PIN} +set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} ${MAIN_CLK_PIN} + +# other timing constraint in ns +set IN_DEL 1.0 +set OUT_DEL 1.0 +set DELAY ${MAIN_TCK} + +create_clock ${MAIN_CLK_PIN} -period ${MAIN_TCK} +create_clock ${AON_CLK_PIN} -period ${MAIN_TCK} + +# in to out +set_max_delay ${DELAY} -from [all_inputs] -to [all_outputs] +# in to reg / reg to out +set_input_delay ${IN_DEL} [remove_from_collection [all_inputs] [get_ports -of_objects [get_clocks]]] -clock ${MAIN_CLK_PIN} +set_output_delay ${OUT_DEL} [all_outputs] -clock ${MAIN_CLK_PIN} + +set_clock_groups -name group1 -async \ + -group [get_clocks ${MAIN_CLK_PIN} ] \ + -group [get_clocks ${AON_CLK_PIN} ] \ + +##################### +# I/O drive/load # +##################### + +# attach load and drivers to IOs to get a more realistic estimate +set_driving_cell -no_design_rule -lib_cell ${DRIVING_CELL} -pin ${DRIVING_CELL_PIN} [all_inputs] +set_load [load_of ${LOAD_CELL_LIB}/${LOAD_CELL}/${LOAD_CELL_PIN}] [all_outputs] + +# set a nonzero critical range to be able to spot the violating paths better +# in the report +set_critical_range 0.5 ${DUT} + +##################### +# Size Only Cells # +##################### + +set_size_only -all_instances [get_cells -h *u_size_only*] true diff --git a/hw/top_darjeeling/ip_autogen/pinmux/syn/pinmux_syn_cfg.hjson b/hw/top_darjeeling/ip_autogen/pinmux/syn/pinmux_syn_cfg.hjson new file mode 100644 index 0000000000000..b978a14f61fe0 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pinmux/syn/pinmux_syn_cfg.hjson @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Top level dut name (sv module). + name: pinmux + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:ip_interfaces:pinmux:0.1 + + import_cfgs: [// Project wide common synthesis config file + "{proj_root}/hw/syn/tools/dvsim/common_syn_cfg.hjson"], + + // Timing constraints for this module + sdc_file: "{proj_root}/hw/top_darjeeling/ip_autogen/pinmux/syn/constraints.sdc" + + // Technology specific timing constraints for this module + foundry_sdc_file: "{foundry_root}/top_darjeeling/syn/foundry.constraints.sdc" +} diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/BUILD b/hw/top_darjeeling/ip_autogen/pwrmgr/BUILD new file mode 100644 index 0000000000000..1206ee3d1c10b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/BUILD @@ -0,0 +1,30 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +load( + "//rules:autogen.bzl", + "autogen_hjson_c_header", + "autogen_hjson_rust_header", +) + +autogen_hjson_c_header( + name = "pwrmgr_c_regs", + srcs = [ + "data/pwrmgr.hjson", + ], +) + +autogen_hjson_rust_header( + name = "pwrmgr_rust_regs", + srcs = [ + "data/pwrmgr.hjson", + ], +) + +filegroup( + name = "all_files", + srcs = glob(["**"]), +) diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/README.md b/hw/top_darjeeling/ip_autogen/pwrmgr/README.md new file mode 100644 index 0000000000000..a7d8cbacbdc77 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/README.md @@ -0,0 +1,36 @@ +# Power Manager HWIP Technical Specification +[`pwrmgr`](https://reports.opentitan.org/hw/top_darjeeling/ip_autogen/pwrmgr/dv/latest/report.html): +![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/test.svg) +![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/passing.svg) +![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/functional.svg) +![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/code.svg) + +# Overview + +This document specifies the functionality of the OpenTitan power manager. + +## Features + +- Cold boot, low power entry / exit and reset support. +- 2 different low power modes. +- Software initiated low power entry and hardware requested low power exit. +- Peripheral reset requests +- Low power abort and low power fall-through support. +- ROM integrity check at power-up. +- Local checks for escalator and power stability. + +## Description + +The power manager sequences power, clocks, and reset resources of the design through cold boot, low power entry/exit and reset scenarios. + +Cold boot, also known as POR (power on reset) is the first reset state of the design. +The power manager sequences the design from a freshly reset state to an active state where software can be initialized. + +- Low power entry is the process in which the device enters one of two low power modes (sleep or deep sleep). +- Low power exit is the process in which the device exits low power mode and returns to active state. +- Low power entry is always initiated by software, while low power exit is always initiated by a previously setup hardware event such as pins or internal timers. +- The power manager processes the software and hardware requests to perform the appropriate actions. + +Reset scenarios refer to non-POR events that cause the device to reboot. +There are various stimuli that can cause such a reset, ranging from external user input to watchdog timeout. +The power manager processes the reset request and brings the device to an appropriate state. diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/data/pwrmgr.hjson b/hw/top_darjeeling/ip_autogen/pwrmgr/data/pwrmgr.hjson new file mode 100644 index 0000000000000..27712ff50fc05 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/data/pwrmgr.hjson @@ -0,0 +1,875 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "pwrmgr", + human_name: "Power Manager", + one_line_desc: "Sequences on-chip power, clocks, and resets through different reset and power states", + one_paragraph_desc: ''' + Power Manager sequences on-chip power, clocks, and reset signals on power-on reset (aka cold boot), low power entry and exit, and non-power-on resets. + To this end, it can turn power domains on and off, control root resets with Reset Manager, and control root clock enables with AST and Clock Manager. + During power up, Power Manager is responsible for triggering OTP sensing, initiating Life Cycle Controller, coordinating with ROM Controller for the startup ROM check, and eventually releasing software to execute. + It features several countermeasures to deter fault injection (FI) attacks. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "20", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_pwrmgr", + revisions: [ + { + version: "0.1.0", + life_stage: "L1", + design_stage: "D1", + verification_stage: "V0", // this module is not verified at the block level + dif_stage: "S0", + commit_id: "b2abc989498f072d9a5530f8aab9b58c1f92c9fb" + } + { + version: "1.0.1", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + } + ] + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {reset: "rst_main_ni"}, + {clock: "clk_slow_i", reset: "rst_slow_ni"}, + {clock: "clk_lc_i", reset: "rst_lc_ni"}, + {clock: "clk_esc_i", reset: "rst_esc_ni"} + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device" } + ], + interrupt_list: [ + { name: "wakeup", desc: "Wake from low power state. See wake info for more details" }, + ], + alert_list: [ + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. + ''' + } + ], + features: [ + { name: "PWRMGR.STARTUP.LIFE_CYCLE_INITIALIZATION", + desc: "Wait completion of Life Cycle initialization." + } + { name: "PWRMGR.CLOCK_CONTROL.IO_IN_LOW_POWER", + desc: '''Controls whether the IO clock remains active in + low power mode. + ''' + } + { name: "PWRMGR.CLOCK_CONTROL.MAIN_IN_LOW_POWER", + desc: '''Controls whether the MAIN clock remains active in + low power mode. + ''' + } + { name: "PWRMGR.CLOCK_CONTROL.USB_IN_LOW_POWER", + desc: '''Controls whether the USB clock remains active in + low power mode. + ''' + } + { name: "PWRMGR.CLOCK_CONTROL.USB_WHEN_ACTIVE", + desc: "Controls whether the USB clock is enabled in active state." + } + { name: "PWRMGR.LOW_POWER.ENTRY", + desc: '''Controls of low power entry, and cases when low power is + not entered due to interrupts or specific units getting busy. + ''' + } + { name: "PWRMGR.LOW_POWER.DISABLE_POWER" + desc: '''Controls whether power is turned off for non-AON domains when + in low power. + ''' + } + { name: "PWRMGR.LOW_POWER.PINMUX_AON_PIN_WKUP_REQ_WAKEUP_ENABLE" + desc: "Enable wakeup request pin_wkup_req from pinmux_aon." + } + { name: "PWRMGR.LOW_POWER.PINMUX_AON_PIN_WKUP_REQ_WAKEUP_REQUEST" + desc: "Wakeup request pin_wkup_req from pinmux_aon." + } + { name: "PWRMGR.LOW_POWER.PINMUX_AON_USB_WKUP_REQ_WAKEUP_ENABLE" + desc: "Enable wakeup request usb_wkup_req from pinmux_aon." + } + { name: "PWRMGR.LOW_POWER.PINMUX_AON_USB_WKUP_REQ_WAKEUP_REQUEST" + desc: "Wakeup request usb_wkup_req from pinmux_aon." + } + { name: "PWRMGR.LOW_POWER.AON_TIMER_AON_WKUP_REQ_WAKEUP_ENABLE" + desc: "Enable wakeup request wkup_req from aon_timer_aon." + } + { name: "PWRMGR.LOW_POWER.AON_TIMER_AON_WKUP_REQ_WAKEUP_REQUEST" + desc: "Wakeup request wkup_req from aon_timer_aon." + } + { name: "PWRMGR.LOW_POWER.SENSOR_CTRL_WKUP_REQ_WAKEUP_ENABLE" + desc: "Enable wakeup request wkup_req from sensor_ctrl." + } + { name: "PWRMGR.LOW_POWER.SENSOR_CTRL_WKUP_REQ_WAKEUP_REQUEST" + desc: "Wakeup request wkup_req from sensor_ctrl." + } + { name: "PWRMGR.LOW_POWER.SOC_PROXY_WKUP_INTERNAL_REQ_WAKEUP_ENABLE" + desc: "Enable wakeup request wkup_internal_req from soc_proxy." + } + { name: "PWRMGR.LOW_POWER.SOC_PROXY_WKUP_INTERNAL_REQ_WAKEUP_REQUEST" + desc: "Wakeup request wkup_internal_req from soc_proxy." + } + { name: "PWRMGR.LOW_POWER.SOC_PROXY_WKUP_EXTERNAL_REQ_WAKEUP_ENABLE" + desc: "Enable wakeup request wkup_external_req from soc_proxy." + } + { name: "PWRMGR.LOW_POWER.SOC_PROXY_WKUP_EXTERNAL_REQ_WAKEUP_REQUEST" + desc: "Wakeup request wkup_external_req from soc_proxy." + } + { name: "PWRMGR.LOW_POWER.WAKE_INFO" + desc: "Record what caused the chip to wakeup from low power." + } + { name: "PWRMGR.RESET.CHECK_ROM_INTEGRITY", + desc: "Wait for successful completion of ROM integrity checks." + } + { name: "PWRMGR.RESET.AON_TIMER_AON_AON_TIMER_RST_REQ_ENABLE", + desc: "Enable reset request from aon_timer_aon." + } + { name: "PWRMGR.RESET.AON_TIMER_AON_AON_TIMER_RST_REQ_REQUEST", + desc: "Reset request from aon_timer_aon." + } + { name: "PWRMGR.RESET.SOC_PROXY_RST_REQ_EXTERNAL_ENABLE", + desc: "Enable reset request from soc_proxy." + } + { name: "PWRMGR.RESET.SOC_PROXY_RST_REQ_EXTERNAL_REQUEST", + desc: "Reset request from soc_proxy." + } + { name: "PWRMGR.RESET.ESCALATION_REQUEST", + desc: "Trigger reset in response to incoming escalation requests." + } + { name: "PWRMGR.RESET.ESCALATION_TIMEOUT", + desc: "Trigger reset in response to non-responsive escalation network." + } + { name: "PWRMGR.RESET.SW_RST_REQUEST", + desc: "Trigger reset in response to rstmgr's sw reset request." + } + { name: "PWRMGR.RESET.MAIN_POWER_GLITCH_RESET", + desc: "Trigger reset in response to glitch in main power." + } + { name: "PWRMGR.RESET.NDM_RESET_REQUEST", + desc: "Trigger reset in response to RV_DM ndm reset." + } + { name: "PWRMGR.RESET.POR_REQUEST", + desc: "Trigger reset in response to POR_N pin." + } + ] + + inter_signal_list: [ + { struct: "pwr_boot_status", + type: "uni", + name: "boot_status", + act: "req", + package: "pwrmgr_pkg", + }, + { struct: "pwr_ast", + type: "req_rsp", + name: "pwr_ast", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_rst", + type: "req_rsp", + name: "pwr_rst", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_clk", + type: "req_rsp", + name: "pwr_clk", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_otp", + type: "req_rsp", + name: "pwr_otp", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_lc", + type: "req_rsp", + name: "pwr_lc", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_flash", + type: "uni", + name: "pwr_flash", + act: "rcv", + package: "pwrmgr_pkg", + }, + + { struct: "esc_tx", + type: "uni", + name: "esc_rst_tx", + act: "rcv", + package: "prim_esc_pkg", + }, + + { struct: "esc_rx", + type: "uni", + name: "esc_rst_rx", + act: "req", + package: "prim_esc_pkg", + }, + + { struct: "pwr_cpu", + type: "uni", + name: "pwr_cpu", + act: "rcv", + package: "pwrmgr_pkg", + }, + + { struct: "logic", + width: 6, + type: "uni", + name: "wakeups", + act: "rcv", + package: "", + }, + + { struct: "logic", + width: 2, + type: "uni", + name: "rstreqs", + act: "rcv", + package: "", + }, + + { struct: "logic", + type: "uni", + name: "ndmreset_req", + act: "rcv", + }, + + { struct: "logic", + type: "uni", + name: "strap", + act: "req", + package: "", + }, + + { struct: "logic", + type: "uni", + name: "low_power", + act: "req", + package: "", + }, + + { struct: "pwrmgr_data", + type: "uni", + name: "rom_ctrl", + act: "rcv", + package: "rom_ctrl_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "fetch_en", + act: "req", + package: "lc_ctrl_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_dft_en", + act: "rcv", + package: "lc_ctrl_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_hw_debug_en", + act: "rcv", + package: "lc_ctrl_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "sw_rst_req", + act: "rcv", + package: "prim_mubi_pkg", + }, + ], + + param_list: [ + { name: "NumWkups", + desc: "Number of wakeups", + type: "int", + default: "6", + local: "true" + }, + + { name: "PINMUX_AON_PIN_WKUP_REQ_IDX", + desc: "Vector index for pinmux_aon pin_wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO", + type: "int", + default: "0", + local: "true" + }, + + { name: "PINMUX_AON_USB_WKUP_REQ_IDX", + desc: "Vector index for pinmux_aon usb_wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO", + type: "int", + default: "1", + local: "true" + }, + + { name: "AON_TIMER_AON_WKUP_REQ_IDX", + desc: "Vector index for aon_timer_aon wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO", + type: "int", + default: "2", + local: "true" + }, + + { name: "SENSOR_CTRL_WKUP_REQ_IDX", + desc: "Vector index for sensor_ctrl wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO", + type: "int", + default: "3", + local: "true" + }, + + { name: "SOC_PROXY_WKUP_INTERNAL_REQ_IDX", + desc: "Vector index for soc_proxy wkup_internal_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO", + type: "int", + default: "4", + local: "true" + }, + + { name: "SOC_PROXY_WKUP_EXTERNAL_REQ_IDX", + desc: "Vector index for soc_proxy wkup_external_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO", + type: "int", + default: "5", + local: "true" + }, + + + { name: "NumRstReqs", + desc: "Number of peripheral reset requets", + type: "int", + default: "2", + local: "true" + }, + + { name: "NumIntRstReqs", + desc: "Number of pwrmgr internal reset requets", + type: "int", + default: "2", + local: "true" + }, + + { name: "NumDebugRstReqs", + desc: "Number of debug reset requets", + type: "int", + default: "1", + local: "true" + }, + + { name: "ResetMainPwrIdx", + desc: "Reset req idx for MainPwr", + type: "int", + default: "2", + local: "true" + }, + { name: "ResetEscIdx", + desc: "Reset req idx for Esc", + type: "int", + default: "3", + local: "true" + }, + { name: "ResetNdmIdx", + desc: "Reset req idx for Ndm", + type: "int", + default: "4", + local: "true" + }, + + ], + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "LC_CTRL.INTERSIG.MUBI", + desc: "life cycle control / debug signals are multibit." + } + { name: "ROM_CTRL.INTERSIG.MUBI", + desc: "rom control done/good signals are multibit." + } + { name: "RSTMGR.INTERSIG.MUBI", + desc: "reset manager software request is multibit." + } + { name: "ESC_RX.CLK.BKGN_CHK", + desc: "Escalation receiver has a background timeout check" + } + { name: "ESC_RX.CLK.LOCAL_ESC", + desc: "Escalation receiver clock timeout has a local reset escalation" + } + { name: "FSM.SPARSE", + desc: "Sparse encoding for slow and fast state machines." + } + { name: "FSM.TERMINAL", + desc: ''' + When FSMs reach a bad state, go into a terminate state that does not + recover without user or external host intervention. + ''' + } + { name: "CTRL_FLOW.GLOBAL_ESC", + desc: "When global escalation is received, proceed directly to reset." + } + { name: "MAIN_PD.RST.LOCAL_ESC", + desc: "When main power domain reset glitches, proceed directly to reset." + } + { name: "CTRL.CONFIG.REGWEN", + desc: "Main control protected by regwen." + } + { name: "WAKEUP.CONFIG.REGWEN", + desc: "Wakeup configuration protected by regwen." + } + { name: "RESET.CONFIG.REGWEN", + desc: "Reset configuration protected by regwen." + } + + ] + + regwidth: "32", + registers: [ + + { name: "CTRL_CFG_REGWEN", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + desc: ''' + Controls the configurability of the !!CONTROL register. + + This register ensures the contents do not change once a low power hint and + WFI has occurred. + + It unlocks whenever a low power transition has completed (transition back to the + ACTIVE state) for any reason. + ''', + + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Configuration enable. + + This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated. + When the device transitions back from low power state to active state, this bit is set + back to 1 to allow software configuration of !!CONTROL + ''', + resval: "1", + }, + ] + tags: [// This regwen is completely under HW management and thus cannot be manipulated + // by software. + "excl:CsrNonInitTests:CsrExclCheck"] + }, + + + { name: "CONTROL", + desc: "Control register", + swaccess: "rw", + hwaccess: "hro", + regwen: "CTRL_CFG_REGWEN", + tags: [// Turning off USB clock in active state impacts other CSRs + // at the chip level (in other blocks, such as clkmgr), + // so we exclude writing from this register. + "excl:CsrAllTests:CsrExclWrite"] + fields: [ + { bits: "0", + hwaccess: "hrw", + name: "LOW_POWER_HINT", + desc: ''' + The low power hint to power manager. + The hint is an indication for how the manager should treat the next WFI. + Once the power manager begins a low power transition, or if a valid reset request is registered, + this bit is automatically cleared by HW. + ''' + resval: "0" + enum: [ + { value: "0", + name: "None", + desc: ''' + No low power intent + ''' + }, + { value: "1", + name: "Low Power", + desc: ''' + Next WFI should trigger low power entry + ''' + }, + ] + tags: [// The regwen for this reg is RO. CSR seq can't support to check this reg + "excl:CsrAllTests:CsrExclAll"] + }, + + { bits: "4", + name: "CORE_CLK_EN", + desc: "core clock enable during low power state", + resval: "0" + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + Core clock disabled during low power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + Core clock enabled during low power state + ''' + }, + ] + }, + + { bits: "5", + name: "IO_CLK_EN", + desc: "IO clock enable during low power state", + resval: "0" + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + IO clock disabled during low power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + IO clock enabled during low power state + ''' + }, + ] + }, + + { bits: "6", + name: "USB_CLK_EN_LP", + desc: "USB clock enable during low power state", + resval: "0", + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + USB clock disabled during low power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + USB clock enabled during low power state. + + However, if !!CONTROL.MAIN_PD_N is 0, USB clock is disabled + during low power state. + ''' + }, + ] + }, + + { bits: "7", + name: "USB_CLK_EN_ACTIVE", + desc: "USB clock enable during active power state", + resval: "1" + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + USB clock disabled during active power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + USB clock enabled during active power state + ''' + }, + ] + }, + + { bits: "8", + name: "MAIN_PD_N", + desc: "Active low, main power domain power down", + resval: "1" + enum: [ + { value: "0", + name: "Power down", + desc: ''' + Main power domain is powered down during low power state. + ''' + }, + { value: "1", + name: "Power up", + desc: ''' + Main power domain is kept powered during low power state + ''' + }, + ] + }, + + + ], + }, + + { name: "CFG_CDC_SYNC", + swaccess: "rw", + hwaccess: "hrw", + hwqe: "true", + desc: ''' + The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the + fast clock domain but used in the slow clock domain. + + The configuration are not propagated across the clock boundary until this + register is triggered and read. See fields below for more details + ''', + + fields: [ + { bits: "0", + name: "SYNC", + desc: ''' + Configuration sync. When this bit is written to 1, a sync pulse is generated. When + the sync completes, this bit then self clears. + + Software should write this bit to 1, wait for it to clear, before assuming the slow clock + domain has accepted the programmed values. + ''', + resval: "0", + }, + ] + tags: [// This bit triggers a payload synchronization and self clears when complete. + // Do not write this bit as there will be side effects and the value will not persist + "excl:CsrNonInitTests:CsrExclWrite"] + }, + + { name: "WAKEUP_EN_REGWEN", + desc: "Configuration enable for wakeup_en register", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + resval: "1" + name: "EN", + desc: ''' + When 1, WAKEUP_EN register can be configured. + When 0, WAKEUP_EN register cannot be configured. + ''', + }, + ] + }, + + { multireg: + { name: "WAKEUP_EN", + desc: "Bit mask for enabled wakeups", + swaccess: "rw", + hwaccess: "hro", + regwen: "WAKEUP_EN_REGWEN", + resval: "0" + cname: "wakeup_en", + count: "NumWkups" + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Whenever a particular bit is set to 1, that wakeup is also enabled. + Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. + ''', + }, + ] + }, + }, + + { multireg: + { name: "WAKE_STATUS", + desc: "A read only register of all current wake requests post enable mask", + swaccess: "ro", + hwaccess: "hwo", + resval: "0" + cname: "wake_status", + count: "NumWkups", + tags: [// Cannot auto-predict current wake request status + "excl:CsrNonInitTests:CsrExclWriteCheck"], + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + Current value of wake requests + ''', + }, + ] + }, + }, + + { name: "RESET_EN_REGWEN", + desc: "Configuration enable for reset_en register", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + resval: "1" + name: "EN", + desc: ''' + When 1, RESET_EN register can be configured. + When 0, RESET_EN register cannot be configured. + ''', + }, + ] + }, + + { multireg: + { name: "RESET_EN", + desc: "Bit mask for enabled reset requests", + swaccess: "rw", + hwaccess: "hro", + regwen: "RESET_EN_REGWEN", + resval: "0" + cname: "rstreq_en", + count: "NumRstReqs" + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Whenever a particular bit is set to 1, that reset request is enabled. + Whenever a particular bit is set to 0, that reset request cannot reset the device. + ''', + }, + ] + tags: [// Self resets should never be triggered by automated tests + "excl:CsrAllTests:CsrExclWrite"] + }, + }, + + { multireg: + { name: "RESET_STATUS", + desc: "A read only register of all current reset requests post enable mask", + swaccess: "ro", + hwaccess: "hwo", + resval: "0" + cname: "reset_status", + count: "NumRstReqs", + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + Current value of reset request + ''', + }, + ] + }, + }, + + { name: "ESCALATE_RESET_STATUS", + desc: "A read only register of escalation reset request", + swaccess: "ro", + hwaccess: "hwo", + resval: "0" + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + When 1, an escalation reset has been seen. + When 0, there is no escalation reset. + ''', + }, + ] + }, + + { name: "WAKE_INFO_CAPTURE_DIS", + desc: "Indicates which functions caused the chip to wakeup", + swaccess: "rw", + hwaccess: "hro", + resval: "0" + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + When written to 1, this actively suppresses the wakeup info capture. + When written to 0, wakeup info capture timing is controlled by HW. + ''', + }, + ] + }, + + { name: "WAKE_INFO", + desc: ''' + Indicates which functions caused the chip to wakeup. + The wake info recording begins whenever the device begins a valid low power entry. + + This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS. + This means it is possible to capture multiple wakeup reasons. + ''', + swaccess: "rw1c", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + resval: "0" + fields: [ + { bits: "5:0", + name: "REASONS", + desc: "Various peripheral wake reasons" + }, + { bits: "6", + name: "FALL_THROUGH", + desc: ''' + The fall through wakeup reason indicates that despite setting a WFI and providing a low power + hint, an interrupt arrived at just the right time to break the executing core out of WFI. + + The power manager detects this condition, halts low power entry and reports as a wakeup reason + ''', + }, + { bits: "7", + name: "ABORT", + desc: ''' + The abort wakeup reason indicates that despite setting a WFI and providing a low power + hint, an active flash / lifecycle / otp transaction was ongoing when the power controller + attempted to initiate low power entry. + + The power manager detects this condition, halts low power entry and reports as a wakeup reason + ''', + }, + ] + tags: [// This regwen is completely under HW management and thus cannot be manipulated + // by software. + "excl:CsrNonInitTests:CsrExclCheck"] + }, + + { name: "FAULT_STATUS", + desc: "A read only register that shows the existing faults", + swaccess: "ro", + hwaccess: "hrw", + sync: "clk_lc_i", + resval: "0" + fields: [ + { bits: "0", + name: "REG_INTG_ERR", + desc: ''' + When 1, an integrity error has occurred. + ''', + }, + + { bits: "1", + name: "ESC_TIMEOUT", + desc: ''' + When 1, an escalation clock / reset timeout has occurred. + ''', + }, + + { bits: "2", + name: "MAIN_PD_GLITCH", + desc: ''' + When 1, unexpected power glitch was observed on main PD. + ''', + }, + ] + }, + ] +} diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/data/pwrmgr_sec_cm_testplan.hjson b/hw/top_darjeeling/ip_autogen/pwrmgr/data/pwrmgr_sec_cm_testplan.hjson new file mode 100644 index 0000000000000..d867437b7c554 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/data/pwrmgr_sec_cm_testplan.hjson @@ -0,0 +1,219 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../pwrmgr/data/pwrmgr.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../pwrmgr/data/pwrmgr_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: '''Verify the countermeasure(s) BUS.INTEGRITY. + This entry is covered by tl_access_test + (hw/dv/tools/dvsim/tests/tl_access_tests.hjson) + ''' + stage: V2S + tests: ["pwrmgr_tl_intg_err"] + } + { + name: sec_cm_lc_ctrl_intersig_mubi + desc: '''Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI. + + **Stimulus**: + - Use comprehensive stimulus - reset and wakeup - + as background traffic to ensure this counter measure + is valid for various states of fast and slow state. + - Drive lc_hw_debug_en_i and lc_dft_en_i with + mixed valid and invalid values. + + **Check**: + - Collect coverage by binding cip_mubi_cov_if to + tb.dut.lc_hw_debug_en_i and tb.dut.lc_dft_en_i + - Add assertion to check whether rom_intg_chk_dis + is set to '1' only when lc_dft_en_i or lc_hw_debug_en_i + is high. + ''' + stage: V2S + tests: ["pwrmgr_sec_cm_lc_ctrl_intersig_mubi"] + } + { + name: sec_cm_rom_ctrl_intersig_mubi + desc: '''Verify the countermeasure(s) ROM_CTRL.INTERSIG.MUBI. + + **Stimulus**: + - Use comprehensive stimulus - reset and wakeup - + as background traffic to ensure this counter measure + is valid for various states of fast and slow fsm. + - Drive rom_ctrl_i with mixed valid and invalid values. + + **Check**: + - Collect coverage by binding cip_mubi_cov_if to + tb.dut.rom_ctrl_i + ''' + stage: V2S + tests: ["pwrmgr_sec_cm_rom_ctrl_intersig_mubi"] + } + { + name: sec_cm_rstmgr_intersig_mubi + desc: '''Verify the countermeasure(s) RSTMGR.INTERSIG.MUBI. + + **Stimulus**: + - Drive tb.dut.sw_rst_req_i with mixed valid and invalid values + + **Check**: + - See sw rst only happens when dut gets valid value by + probing fast fsm state. The state has to move low power state. + - Collect coverage by binding cip_mubi_cov_if to + tb.dut.sw_rst_req_i + ''' + stage: V2S + tests: ["pwrmgr_sec_cm_rstmgr_intersig_mubi"] + } + { + name: sec_cm_esc_rx_clk_bkgn_chk + desc: '''Verify the countermeasure(s) ESC_RX.CLK.BKGN_CHK. + + **Stimulus**: + - At FastPwrStateActive state, create escalation clock + or reset failure by stopping clock or asserting reset. + + **Check**: + - Expecting fatal alert event and rstreqs[ResetEscIdx]. + - Add assertion to see if u_esc_timeout happens, then + rstreqs[ResetEscIdx] should be asserted. + - After the alert agent processese the alert + by asserting escalation reset, + see if dut is back to normal operation state. + ''' + stage: V2S + tests: ["pwrmgr_esc_clk_rst_malfunc"] + } + { + name: sec_cm_esc_rx_clk_local_esc + desc: '''Verify the countermeasure(s) ESC_RX.CLK.LOCAL_ESC. + + This is triggered by common cm primitives (SecCmPrimCount). + (https://github.com/lowRISC/opentitan/blob/master + /hw/dv/sv/cip_lib/doc/index.md#security-verification + -for-common-countermeasure-primitives) + + **Check**: + - Detect fast state transition to FastPwrStateResetPrep. + - Add assertion to check if u_sec_timeout happens, then + rstreqs[ResetEscIdx] should be asserted. + ''' + stage: V2S + tests: ["pwrmgr_sec_cm"] + } + { + name: sec_cm_fsm_sparse + desc: '''Verify the countermeasure(s) FSM.SPARSE. + This is triggered by common cm primitives (SecCmPrimSparseFsmFlop). + (https://github.com/lowRISC/opentitan/blob/master + /hw/dv/sv/cip_lib/doc/index.md#security-verification + -for-common-countermeasure-primitives) + ''' + stage: V2S + tests: ["pwrmgr_sec_cm"] + } + { + name: sec_cm_fsm_terminal + desc: '''Verify the countermeasure(s) FSM.TERMINAL. + + This is caused by any invalid (slow|fast) state. + + **Check**: + - If slow state is invalid, fast state becomes FastPwrStateInvalid, + pwr_ast_o.pwr_clamp =1 and pwr_ast_o.main_pd_n = 0. + - If fast state is invalid, pwr_rst_o.rst_lc_req is all one, + pwr_rst_o.rst_sys_req is all one and pwr_clk_o = 0. + Dut should be recovered by asserting rst_n = 0. + ''' + stage: V2S + tests: ["pwrmgr_sec_cm"] + } + { + name: sec_cm_ctrl_flow_global_esc + desc: '''Verify the countermeasure(s) CTRL_FLOW.GLOBAL_ESC. + + **Stimulus**: + - Send escalation request to esc_rst_tx_i + + **Check**: + - Check fast state transition to FastPwrStateResetPrep + - Add assertion to see if we get pwr_rst_o.rstreqs[ResetEscIdx] + set when dut receives esc_rst_tx_i + ''' + stage: V2S + tests: ["pwrmgr_global_esc"] + } + { + name: sec_cm_main_pd_rst_local_esc + desc: '''Verify the countermeasure(s) MAIN_PD.RST.LOCAL_ESC. + + **Stimulus**: + - Create power reset glitch by setting tb.dut.rst_main_ni + and tb.dut.pwr_ast_i.main_pok to 0 + + **Check**: + - Check fast state transition to FastPwrStateResetPrep + - Add assertion to see if we get pwr_rst_o.rstreqs[ResetMainPwrIdx] + ''' + stage: V2S + tests: ["pwrmgr_glitch"] + } + { + name: sec_cm_ctrl_config_regwen + desc: '''Verify the countermeasure(s) CTRL.CONFIG.REGWEN. + + **Stimulus**: + - Initiate low power transition by setting + PWRMGR.CONTROL.LOW_POWER_HINT to 1. Wait for a few cycle + to ensure the csr value propagates to slow clock domain. + Then issue csr write to PWRMGR.CONTROL + + **Check**: + - After the csr update under PWRMGR.CTRL_CFG_REGWEN = 0, + read back and check the value is not updated by + the csr update attempt. + ''' + stage: V2S + tests: ["pwrmgr_sec_cm_ctrl_config_regwen"] + } + { + name: sec_cm_wakeup_config_regwen + desc: '''Verify the countermeasure(s) WAKEUP.CONFIG.REGWEN. + + This is covered by auto csr test. + ''' + stage: V2S + tests: ["pwrmgr_csr_rw"] + } + { + name: sec_cm_reset_config_regwen + desc: '''Verify the countermeasure(s) RESET.CONFIG.REGWEN. + + This is covered by auto csr test. + ''' + stage: V2S + tests: ["pwrmgr_csr_rw"] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/data/pwrmgr_testplan.hjson b/hw/top_darjeeling/ip_autogen/pwrmgr/data/pwrmgr_testplan.hjson new file mode 100644 index 0000000000000..aad3a73fc5690 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/data/pwrmgr_testplan.hjson @@ -0,0 +1,369 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "pwrmgr" + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson", + "pwrmgr_sec_cm_testplan.hjson"] + testpoints: [ + { + name: smoke + desc: ''' + Smoke test exercising the pwrmgr state transitions. + + - Brings pwrmgr out of POR. + - Enables wakeup. + - Triggers SW initiated low power transition with reset settings + in `control` CSR. + - Triggers wakeup. + - Enables and triggers a reset. + - Waits for pwrmgr to be out of reset. + + **Stimulus**: + - CSR writes to `wakeup_en`, `reset_en`, and `low_power_hint`. + - Needs many input pins to line up correctly in order to prevent the + pwrmgr from waiting forever. Most of these are set in response + to outputs, and are checked by SVA. + + **Checks**: + - The fast fsm becomes active when `fetch_en_o` output rises. + - The wakeup and reset causes are as expected reading CSRs + `wake_status` and `reset_status`. + - The output `pwr_rst_req.reset_cause` matches a low power or + reset cause. + - The output `pwr_rst_req.rstreqs` matches the enabled resets. + ''' + stage: V1 + tests: ["pwrmgr_smoke"] + } + { + name: wakeup + desc: ''' + Test random wakeup, wakeup_en, wake_info_capture_dis, and + interrupt. + + The different wakeup inputs can be disabled via bits in the + `wakeup_en` CSR. Update of `wakeup_info` can be disabled + via the `wake_info_capture_dis` CSR. Any wakeup causes an + interrupt unless interrupts are disabled. + + **Stimulus**: + - Sets `wakeup_en` randomly but don't set it to zero, or the + test will timeout. + - Set `wake_info_capture_dis` randomly on and off. + - Bring pwrmgr to low power. + - Set `wakeups_i` inputs randomly. + - Set `intr_enable` randomly. + + **Checks**: + - The fast fsm becomes active when `fetch_en_o` output rises. + - Depending on `wakeups_i`: + - If all wakeups are disabled, wait some time checking the + state remains inactive. + - Set `wakeups_i` so at least one is enabled. + - Checks `wakeup_status` CSR during transition to active state + since the reset involved will clear the wakeups_i input. + - Checks the `wake_info` CSR. + - Checks the output `pwr_rst_req.reset_cause` is `LowPwrEntry`. + - Check that `intr_wakeup_o` is set according to `intr_enable` CSR. + - Coverage collected by `wakeup_cg` and `wakeup_intr_cg`. + ''' + stage: V2 + tests: ["pwrmgr_wakeup"] + } + { + name: control_clks + desc: ''' + Test CSR control of peripheral clocks during low power. + + The peripheral clocks can be configured to remain on or be turned + off during low power with bits in the `control` CSR register. The + usb clock can also be configured off in active mode. + + **Stimulus**: + - Sets these control bits at random. + - Cause a low power transition and wakeup. + + **Checks**: + - The clock enable outputs to the AST clocks during a low + power transition match the control bits. + - The usb clock enable is also checked during active mode against + the control register. + ''' + stage: V2 + tests: ["pwrmgr_wakeup"] + } + { + name: aborted_low_power + desc: ''' + Test aborted low power transitions. + + Low power transitions can be aborted in two cases: + - The processor gets an interrupt soon after a low power entry is + triggered. + - OTP, LC, or FLASH are not idle. + This test aborts low power transitions, and disables any wakeups, + so the test would timeout if low power was entered. + + **Stimulus**: + - Bring pwrmgr to low power. + - Either disable `pwr_cpu.core_sleeping` or keep some of `lc_idle`, + `otp_idle`, or `flash_idle` inputs off. + - Disable all wakeup enables. + - Randomly set `wakeup_info_capture_dis` CSR. + + **Checks**: + - The `ctrl_cfg_regwen` CSR reads as 1 on the first attempt. + - Checks the output `pwr_rst_req.reset_cause` doesn't change for + a bounded amount of time. + - Check that the `wakeup_info` CSR flags either `fall_through` or + `abort` events when capture is enabled. + ''' + stage: V2 + tests: ["pwrmgr_aborted_low_power", "pwrmgr_lowpower_invalid"] + } + { + name: reset + desc: ''' + Test random reset and reset_en. + + Conditional reset inputs can be disabled via bits in the `reset_en` + CSR, while escalation and main power are unconditional. Resets can + be triggered either in active or low power state. + + **Stimulus**: + - Sets `reset_en` randomly. + - Randomly choose whether to put the unit in low power mode. + - Generate resets randomly in value and time: + - Conditionals via rstreqs_i, + - Main power glitch via rst_main_ni. + - Escalation via `esc_rst_tx_i`. + - Sw reset from rstmgr via `sw_rst_req_i`. + + **Checks**: + - The fast fsm becomes active when `fetch_en_o` output rises. + - Checks the `reset_status` CSRs. + - Checks `ip_clk_en` output has a low transition. + - SVA that when `pwr_rst_req.reset_cause` is HwReq, and the output + `pwr_rst_req.rstreqs` matches the unconditional and enabled + conditional resets inputs. + ''' + stage: V2 + tests: ["pwrmgr_reset", "pwrmgr_reset_invalid"] + } + { + name: main_power_glitch_reset + desc: ''' + Test reset due to a glitch in main power. + + A power glitch causes an unconditional reset. + + **Stimulus**: + - Set the rst_main_ni input low indicating a main power glitch. + + **Checks**: + - The fast fsm becomes active when `fetch_en_o` output rises. + - Checks the `reset_status` CSRs. + - Checks `ip_clk_en` output has a low transition. + - Checks the output `pwr_rst_req.reset_cause` matches HwReq. + - Checks the output `pwr_rst_req.rstreqs` matches power glitch. + ''' + stage: V2 + tests: ["pwrmgr_reset"] + } + { + name: reset_wakeup_race + desc: ''' + Test wakeup from low power and reset request almost coinciding. + + If a wakeup from low power and a reset occur at nearly the same time + the system handles them one at a time. + + **Stimulus**: + - Trigger reset and wakeup from low power as described for other + testpoints. + - Issue reset and wakeup a random number of cycles after the slow + state machine is in LowPower state. + - This also checks them coinciding. + + **Check**: + - Similar tests as for the wakeup and reset testpoints, except + making sure they happen per the triggering order. + ''' + stage: V2 + tests: ["pwrmgr_wakeup_reset"] + } + { + name: lowpower_wakeup_race + desc: ''' + Test wakeups coming close to lowpower entry. + + If low power entry and a wakeup are closely aligned the hardware + could get confused. Notice this is very unlikely, since wakeup is + only sensed when the slow fsm is in LowPower state. + + **Stimulus**: + - Trigger low power entry as described for other testpoints. + - Have all wakeups enabled. + - Assert wakeups_i in the temporal neighborhood of low power + entry. + + **Check**: + - No timeout occurs. + - Either pwrmgr remains active or a full low power cycle occurs. + ''' + stage: V2 + tests: ["pwrmgr_lowpower_wakeup_race"] + } + { + name: disable_rom_integrity_check + desc: ''' + Test rom integrity check is disabled under life cycle test states. + + While running a series of reset event, at FastPwrStateRomCheck + state, + - Drive lc_hw_debug_en_i and lc_dft_en_i to random value + excluding {lc_ctrl_pkg::On, lc_ctrl_pkg::On} for both ports. + - Set rom_ctrl_i.good = Mubi4False. + - Wait for a while to make sure fsm state check is not FastPwrStateActive. + + Then, + - Drive lc_hw_debug_en_i and lc_dft_en_i to {lc_ctrl_pkg::On, lc_ctrl_pkg::On} + - Check test finish gracefully. + + Try these steps with different lc_ctrl inputs. + ''' + stage: V2 + tests: ["pwrmgr_disable_rom_integrity_check"] + } + { + name: escalation_timeout + desc: '''This tests the escalation timeout feature. + + If the escalation network doesn't respond to an outgoing "health" + requests within 128 cycles pwrmgr should issue an escalation reset + request. + + **Stimulus**: + - Cause the external escalation network to stop responding, either + disabling the clock or jamming the differential pairs. + + **Check**: + - After 128 cycles of inactivity an escalation reset should be + triggered. + ''' + stage: V3 + tests: ["pwrmgr_escalation_timeout"] + } + { + name: stress_all + desc: '''This runs random sequences in succession. + + Randomly chooses from the following sequences: + - pwrmgr_aborted_low_power_vseq + - pwrmgr_lowpower_wakeup_race_vseq + - pwrmgr_reset_vseq + - pwrmgr_smoke_vseq + - pwrmgr_wakeup_reset_vseq + - pwrmgr_wakeup_vseq + ''' + stage: V2 + tests: ["pwrmgr_stress_all"] + } + ] + + covergroups: [ + { + name: wakeup_ctrl_cg + desc: ''' + Collects coverage on wakeup enable and capture functionality. + + This is collected per individual wakeup bit. Covergroup contains + coverpoints for the `wakeup_en` CSR bit, `wakeup_info_capture_dis` + CSR, `wakeups_i` input bit, and `wakeup_status` CSR bit, and their + cross. + ''' + } + { + name: wakeup_intr_cg + desc: ''' + Collects coverage on interrupts for wakeup functionality. + + This is collected per individual wakeup bit. Covergroup contains + coverpoints for the `intr_en` CSR, the `wakeup_status` CSR bit, + the `intr_status` CSR, the output `intr_wakeup` port, and their + cross. + ''' + } + { + name: control_cg + desc: ''' + Collects coverage on clock and power bits from `control` CSR during + a lowpower transition and active state. + ''' + } + { + name: hw_reset_0_cg + desc: ''' + Collects coverage related to external reset `0`. + + Covergroup contains coverpoints for the `rstreqs_i[0]` external + reset input, its corresponding bit in `reset_en` CSR, and whether + this reset is asserted during low power state, and suitable crosses. + ''' + } + { + name: hw_reset_1_cg + desc: ''' + Collects coverage related to external reset `1`. + + Covergroup contains coverpoints for the `rstreqs_i[1]` external + reset input, its corresponding bit in `reset_en` CSR, and whether + this reset is asserted during low power state, and suitable crosses. + ''' + } + { + name: rstmgr_sw_reset_cg + desc: ''' + Collects coverage on the software reset from rstmgr. + + Covergroup contains a coverpoint for the input `sw_rst_req_i` from + rstmgr. + ''' + } + { + name: main_power_reset_cg + desc: ''' + Collects coverage on resets due to a main power glitch. + + Covergroup contains a coverpoint for the input `rst_main_i` that + triggers a power glitch reset, and whether this reset is asserted + during low power state. + ''' + } + { + name: esc_reset_cg + desc: ''' + Collects coverage on resets due to escalation. + + Covergroup contains a coverpoint for the input `esc_rst_tx_i` that + triggers an escalation reset, and whether this reset is asserted + during low power state. + ''' + } + { + name: reset_wakeup_distance_cg + desc: ''' + Covergroup contains a coverpoint for the difference between the + cycles when the reset and the wakeup were received in the inputs. + The difference is positive when reset happened after wakeup, and + zero when the two happened at the same clock cycle. + ''' + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/data/top_darjeeling_pwrmgr.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/pwrmgr/data/top_darjeeling_pwrmgr.ipconfig.hjson new file mode 100644 index 0000000000000..01f864540c095 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/data/top_darjeeling_pwrmgr.ipconfig.hjson @@ -0,0 +1,85 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_pwrmgr + param_values: + { + NumWkups: 6 + Wkups: + [ + { + name: pin_wkup_req + width: "1" + module: pinmux_aon + } + { + name: usb_wkup_req + width: "1" + module: pinmux_aon + } + { + name: wkup_req + width: "1" + module: aon_timer_aon + } + { + name: wkup_req + width: "1" + module: sensor_ctrl + } + { + name: wkup_internal_req + width: "1" + module: soc_proxy + } + { + name: wkup_external_req + width: "1" + module: soc_proxy + } + ] + rst_reqs: + { + peripheral: + [ + { + name: aon_timer_rst_req + width: "1" + module: aon_timer_aon + desc: watchdog reset requestt + } + { + name: rst_req_external + width: "1" + module: soc_proxy + desc: External reset request + } + ] + int: + [ + { + name: MainPwr + desc: main power glitch reset request + module: pwrmgr_aon + } + { + name: Esc + desc: escalation reset request + module: alert_handler + } + ] + debug: + [ + { + name: Ndm + desc: non-debug-module reset request + module: rv_dm + } + ] + } + NumRstReqs: 2 + wait_for_external_reset: true + topname: darjeeling + } +} diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/doc/checklist.md b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/checklist.md new file mode 100644 index 0000000000000..2cb33d32f77e0 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/checklist.md @@ -0,0 +1,266 @@ +# PWRMGR Checklist + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [PWRMGR peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done |[PWRMGR Design Spec](../README.md) +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | N/A | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Done | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. +Documentation | [MISSING_FUNC][] | Done | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | +RTL | [STYLE_X][] | Done | +RTL | [CDC_SYNCMACRO][] | N/A | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [AREA_CHECK][] | Done | +Code Quality | [TIMING_CHECK][] | Done | +Security | [SEC_CM_DOCUMENTED][] | Done | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | N/A | +Security | [SEC_CM_NON_RESET_FLOPS][] | Done | +Security | [SEC_CM_SHADOW_REGS][] | Done | +Security | [SEC_CM_RTL_REVIEWED][] | Done | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Done | + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Done | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_RTL][] | Done | +Review | [REVIEW_DELETED_FF][] | Done | +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | @matutem, @vogelpi, @adk +Review | Signoff date | Done | 2024-08-06 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [PWRMGR DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Done | [PWRMGR testplan](../dv/README.md#testplan) +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | Done | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | Done | +Tests | [SIM_SMOKE_TEST_PASSING][] | Done | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done | Block has no mem +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | Xcelium +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done | +Regression | [FPV_REGRESSION_SETUP][] | N/A | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Done | +Review | [DESIGN_SPEC_REVIEWED][] | Done | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exceptions: debug, power, performance +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Done | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | Done | +Tests | [SIM_ALL_TESTS_PASSING][] | Done | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | NA | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | NA | +Tests | [SIM_FW_SIMULATED][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Done | +Coverage | [SIM_CODE_COVERAGE_V2][] | Done | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Done | +Coverage | [FPV_CODE_COVERAGE_V2][] | NA | +Coverage | [FPV_COI_COVERAGE_V2][] | NA | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Done | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done | +Tests | [FPV_SEC_CM_VERIFIED][] | Done | +Tests | [SIM_SEC_CM_VERIFIED][] | Done | +Coverage | [SIM_COVERAGE_REVIEWED][] | Done | UNR will be added after intra structure issue is resolved. +Review | [SEC_CM_DV_REVIEWED][] | Done | + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Done | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | NA | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | NA | +Coverage | [FPV_COI_COVERAGE_AT_100][] | NA | +Code Quality | [ALL_TODOS_RESOLVED][] | Done | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/doc/interfaces.md b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/interfaces.md new file mode 100644 index 0000000000000..aa6ac33bd107e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/interfaces.md @@ -0,0 +1,68 @@ +# Hardware Interfaces + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`pwrmgr`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: **`clk_slow_i`**, **`clk_lc_i`**, **`clk_esc_i`** +- Bus Device Interfaces (TL-UL): **`tl`** +- Bus Host Interfaces (TL-UL): *none* +- Peripheral Pins for Chip IO: *none* + +## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:---------------|:----------------------------|:--------|:------|--------:|:--------------| +| boot_status | pwrmgr_pkg::pwr_boot_status | uni | req | 1 | | +| pwr_ast | pwrmgr_pkg::pwr_ast | req_rsp | req | 1 | | +| pwr_rst | pwrmgr_pkg::pwr_rst | req_rsp | req | 1 | | +| pwr_clk | pwrmgr_pkg::pwr_clk | req_rsp | req | 1 | | +| pwr_otp | pwrmgr_pkg::pwr_otp | req_rsp | req | 1 | | +| pwr_lc | pwrmgr_pkg::pwr_lc | req_rsp | req | 1 | | +| pwr_flash | pwrmgr_pkg::pwr_flash | uni | rcv | 1 | | +| esc_rst_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | | +| esc_rst_rx | prim_esc_pkg::esc_rx | uni | req | 1 | | +| pwr_cpu | pwrmgr_pkg::pwr_cpu | uni | rcv | 1 | | +| wakeups | logic | uni | rcv | 6 | | +| rstreqs | logic | uni | rcv | 2 | | +| ndmreset_req | logic | uni | rcv | 1 | | +| strap | logic | uni | req | 1 | | +| low_power | logic | uni | req | 1 | | +| rom_ctrl | rom_ctrl_pkg::pwrmgr_data | uni | rcv | 1 | | +| fetch_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | | +| lc_dft_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| sw_rst_req | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | + +## Interrupts + +| Interrupt Name | Type | Description | +|:-----------------|:-------|:----------------------------------------------------------| +| wakeup | Event | Wake from low power state. See wake info for more details | + +## Security Alerts + +| Alert Name | Description | +|:-------------|:----------------------------------------------------------------------------------| +| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. | + +## Security Countermeasures + +| Countermeasure ID | Description | +|:------------------------------|:-------------------------------------------------------------------------------------------------------------------------| +| PWRMGR.BUS.INTEGRITY | End-to-end bus integrity scheme. | +| PWRMGR.LC_CTRL.INTERSIG.MUBI | life cycle control / debug signals are multibit. | +| PWRMGR.ROM_CTRL.INTERSIG.MUBI | rom control done/good signals are multibit. | +| PWRMGR.RSTMGR.INTERSIG.MUBI | reset manager software request is multibit. | +| PWRMGR.ESC_RX.CLK.BKGN_CHK | Escalation receiver has a background timeout check | +| PWRMGR.ESC_RX.CLK.LOCAL_ESC | Escalation receiver clock timeout has a local reset escalation | +| PWRMGR.FSM.SPARSE | Sparse encoding for slow and fast state machines. | +| PWRMGR.FSM.TERMINAL | When FSMs reach a bad state, go into a terminate state that does not recover without user or external host intervention. | +| PWRMGR.CTRL_FLOW.GLOBAL_ESC | When global escalation is received, proceed directly to reset. | +| PWRMGR.MAIN_PD.RST.LOCAL_ESC | When main power domain reset glitches, proceed directly to reset. | +| PWRMGR.CTRL.CONFIG.REGWEN | Main control protected by regwen. | +| PWRMGR.WAKEUP.CONFIG.REGWEN | Wakeup configuration protected by regwen. | +| PWRMGR.RESET.CONFIG.REGWEN | Reset configuration protected by regwen. | + + + diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/doc/programmers_guide.md b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/programmers_guide.md new file mode 100644 index 0000000000000..4fb6b768d973c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/programmers_guide.md @@ -0,0 +1,81 @@ +# Programmer's Guide + +The process in which the power manager is used is highly dependent on the system's topology. +The following proposes one method for how this can be done. + +Assume first the system has the power states described [above](theory_of_operation.md#supported-low-power-modes). + +## Programmer Sequence for Entering Low Power + +1. Disable interrupt handling. +2. Mask all interrupt sources that should not prevent low power entry. + - Note that merely *disabling* interrupt handling with the `mie` global interrupt-enable bit on the processing host is insufficient. + - Interrupt sources that are not masked can cause the [fall through exit](theory_of_operation.md#fall-through-handling). +3. Enable desired wakeup and reset sources in [`WAKEUP_EN`](registers.md#wakeup_en) and [`RESET_EN`](registers.md#reset_en). +4. Perform any system-specific low power entry steps, e.g. + - Interrupt checks (if something became pending prior to disable) +5. Configure low power mode configuration in [`CONTROL`](registers.md#control). + - [`LOW_POWER_HINT`](registers.md#control--low_power_hint) must be set to trigger low power entry when the CPU sleeps. +7. Set and poll [`CFG_CDC_SYNC`](registers.md#cfg_cdc_sync) to ensure above settings propagate across clock domains. +8. Execute wait-for-interrupt instruction on the processing host. + +Note that entering low power mode requires that pwrmgr's `pwr_cpu_i.core_sleeping` input be at logic high long enough to be sampled. +A wait-for-interrupt instruction does not guarantee entry into low power, since the CPU could immediately resume execution in some cases. + +### Possible Exits + +Once low power is initiated, the system may exit due to several reasons. +1. Graceful low power exit - This exit occurs when some source in the system gracefully wakes up the power manager. +2. System reset request - This exit occurs when either software or a peripheral requests the pwrmgr to reset the system. +3. [Fall through exit](theory_of_operation.md#fall-through-handling) - This exit occurs when an interrupt manages to break the wait-for-interrupt loop. +4. [Aborted entry](theory_of_operation.md#abort-handling) - This exit occurs when low power entry is attempted with an ongoing non-volatile transaction. + +In both fall through exit and aborted entry, the power manager does not actually enter low power. +Instead the low power entry is interrupted and the system restored to active state. + +In addition, a CPU's sleeping signal that is too short for the power manager to sample will not trigger even an attempt to go to low power. +In such cases, there will be no bits set in [`WAKE_INFO`](registers.md#wake_info), and no side effects of pwrmgr entering low power mode will trigger. + +To check the exit condition, software can follow these steps: +1. Clear low power hint in [`CONTROL`](registers.md#control) and poll until it becomes cleared. + + - Until the hint clears, the values in [`WAKE_INFO`](registers.md#wake_info) may not reflect the true exit condition. +2. Check [`WAKE_INFO`](registers.md#wake_info) to get the condition. + - If no bits are set, then this was a fast fall through, where low power entry was not attempted. + +## Programmer Sequence for Exiting Low Power + +There are two separate cases for low power exit. +One is exiting from deep sleep, and the other is exiting from normal sleep. + +### Exiting from Deep Sleep + +When exiting from deep sleep, the system begins execution in ROM. + +1. Complete normal preparation steps. +2. Check reset cause in [rstmgr](../../rstmgr/README.md) +3. Re-enable modules that have powered down. +4. Disable wakeup recording through [`WAKE_INFO_CAPTURE_DIS`](registers.md#wake_info_capture_dis). +5. Check which source woke up the system through [`WAKE_INFO`](registers.md#wake_info). +6. Take appropriate steps to handle the wake and resume normal operation. +7. Once wake is handled, clear the wake indication in [`WAKE_INFO`](registers.md#wake_info). + +### Exiting from Normal Sleep + +The handling for fall-through and abort are similar to normal sleep exit. +Since in these scenarios the system was not reset, software continues executing the instruction after the wait-for-interrupt invocation. + +1. Check exit condition to determine appropriate steps. +2. Clear low power hints and configuration in [`CONTROL`](registers.md#control). +3. Set and poll [`CFG_CDC_SYNC`](registers.md#cfg_cdc_sync) to ensure setting changes have propagated across clock boundaries. +4. Disable wakeup sources and stop recording. +5. Re-enable interrupts for normal operation and wakeup handling. +6. Once wake is handled, clear the wake indication in [`WAKE_INFO`](registers.md#wake_info). + +For an in-depth discussion, please see [power management programmers model](https://docs.google.com/document/d/1w86rmvylJgZVmmQ6Q1YBcCp2VFctkQT3zJ408SJMLPE/edit?usp=sharing) for additional details. + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_pwrmgr.h) diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/doc/pwrmgr_connectivity.svg b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/pwrmgr_connectivity.svg new file mode 100644 index 0000000000000..b525330ca1408 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/pwrmgr_connectivity.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/doc/pwrmgr_fsms.svg b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/pwrmgr_fsms.svg new file mode 100644 index 0000000000000..962794cd0ab79 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/pwrmgr_fsms.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/doc/registers.md b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/registers.md new file mode 100644 index 0000000000000..18b553cf4492d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/registers.md @@ -0,0 +1,435 @@ +# Registers + + +## Summary + +| Name | Offset | Length | Description | +|:---------------------------------------------------------|:---------|---------:|:--------------------------------------------------------------------------------| +| pwrmgr.[`INTR_STATE`](#intr_state) | 0x0 | 4 | Interrupt State Register | +| pwrmgr.[`INTR_ENABLE`](#intr_enable) | 0x4 | 4 | Interrupt Enable Register | +| pwrmgr.[`INTR_TEST`](#intr_test) | 0x8 | 4 | Interrupt Test Register | +| pwrmgr.[`ALERT_TEST`](#alert_test) | 0xc | 4 | Alert Test Register | +| pwrmgr.[`CTRL_CFG_REGWEN`](#ctrl_cfg_regwen) | 0x10 | 4 | Controls the configurability of the !!CONTROL register. | +| pwrmgr.[`CONTROL`](#control) | 0x14 | 4 | Control register | +| pwrmgr.[`CFG_CDC_SYNC`](#cfg_cdc_sync) | 0x18 | 4 | The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the | +| pwrmgr.[`WAKEUP_EN_REGWEN`](#wakeup_en_regwen) | 0x1c | 4 | Configuration enable for wakeup_en register | +| pwrmgr.[`WAKEUP_EN`](#WAKEUP_EN) | 0x20 | 4 | Bit mask for enabled wakeups | +| pwrmgr.[`WAKE_STATUS`](#WAKE_STATUS) | 0x24 | 4 | A read only register of all current wake requests post enable mask | +| pwrmgr.[`RESET_EN_REGWEN`](#reset_en_regwen) | 0x28 | 4 | Configuration enable for reset_en register | +| pwrmgr.[`RESET_EN`](#RESET_EN) | 0x2c | 4 | Bit mask for enabled reset requests | +| pwrmgr.[`RESET_STATUS`](#RESET_STATUS) | 0x30 | 4 | A read only register of all current reset requests post enable mask | +| pwrmgr.[`ESCALATE_RESET_STATUS`](#escalate_reset_status) | 0x34 | 4 | A read only register of escalation reset request | +| pwrmgr.[`WAKE_INFO_CAPTURE_DIS`](#wake_info_capture_dis) | 0x38 | 4 | Indicates which functions caused the chip to wakeup | +| pwrmgr.[`WAKE_INFO`](#wake_info) | 0x3c | 4 | Indicates which functions caused the chip to wakeup. | +| pwrmgr.[`FAULT_STATUS`](#fault_status) | 0x40 | 4 | A read only register that shows the existing faults | + +## INTR_STATE +Interrupt State Register +- Offset: `0x0` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "wakeup", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw1c | 0x0 | wakeup | Wake from low power state. See wake info for more details | + +## INTR_ENABLE +Interrupt Enable Register +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "wakeup", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | wakeup | Enable interrupt when [`INTR_STATE.wakeup`](#intr_state) is set. | + +## INTR_TEST +Interrupt Test Register +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "wakeup", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | wo | 0x0 | wakeup | Write 1 to force [`INTR_STATE.wakeup`](#intr_state) to 1. | + +## ALERT_TEST +Alert Test Register +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:-------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | + +## CTRL_CFG_REGWEN +Controls the configurability of the [`CONTROL`](#control) register. + +This register ensures the contents do not change once a low power hint and +WFI has occurred. + +It unlocks whenever a low power transition has completed (transition back to the +ACTIVE state) for any reason. +- Offset: `0x10` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | ro | 0x1 | EN | Configuration enable. This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated. When the device transitions back from low power state to active state, this bit is set back to 1 to allow software configuration of [`CONTROL`](#control) | + +## CONTROL +Control register +- Offset: `0x14` +- Reset default: `0x180` +- Reset mask: `0x1f1` +- Register enable: [`CTRL_CFG_REGWEN`](#ctrl_cfg_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "LOW_POWER_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "CORE_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IO_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "USB_CLK_EN_LP", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "USB_CLK_EN_ACTIVE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MAIN_PD_N", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-------------------------------------------------| +| 31:9 | | | Reserved | +| 8 | rw | 0x1 | [MAIN_PD_N](#control--main_pd_n) | +| 7 | rw | 0x1 | [USB_CLK_EN_ACTIVE](#control--usb_clk_en_active) | +| 6 | rw | 0x0 | [USB_CLK_EN_LP](#control--usb_clk_en_lp) | +| 5 | rw | 0x0 | [IO_CLK_EN](#control--io_clk_en) | +| 4 | rw | 0x0 | [CORE_CLK_EN](#control--core_clk_en) | +| 3:1 | | | Reserved | +| 0 | rw | 0x0 | [LOW_POWER_HINT](#control--low_power_hint) | + +### CONTROL . MAIN_PD_N +Active low, main power domain power down + +| Value | Name | Description | +|:--------|:-----------|:----------------------------------------------------------| +| 0x0 | Power down | Main power domain is powered down during low power state. | +| 0x1 | Power up | Main power domain is kept powered during low power state | + + +### CONTROL . USB_CLK_EN_ACTIVE +USB clock enable during active power state + +| Value | Name | Description | +|:--------|:---------|:---------------------------------------------| +| 0x0 | Disabled | USB clock disabled during active power state | +| 0x1 | Enabled | USB clock enabled during active power state | + + +### CONTROL . USB_CLK_EN_LP +USB clock enable during low power state + +| Value | Name | Description | +|:--------|:---------|:------------------------------------------------------------------------------------------------------------------------------| +| 0x0 | Disabled | USB clock disabled during low power state | +| 0x1 | Enabled | USB clock enabled during low power state. However, if !!CONTROL.MAIN_PD_N is 0, USB clock is disabled during low power state. | + + +### CONTROL . IO_CLK_EN +IO clock enable during low power state + +| Value | Name | Description | +|:--------|:---------|:-----------------------------------------| +| 0x0 | Disabled | IO clock disabled during low power state | +| 0x1 | Enabled | IO clock enabled during low power state | + + +### CONTROL . CORE_CLK_EN +core clock enable during low power state + +| Value | Name | Description | +|:--------|:---------|:-------------------------------------------| +| 0x0 | Disabled | Core clock disabled during low power state | +| 0x1 | Enabled | Core clock enabled during low power state | + + +### CONTROL . LOW_POWER_HINT +The low power hint to power manager. +The hint is an indication for how the manager should treat the next WFI. +Once the power manager begins a low power transition, or if a valid reset request is registered, +this bit is automatically cleared by HW. + +| Value | Name | Description | +|:--------|:----------|:----------------------------------------| +| 0x0 | None | No low power intent | +| 0x1 | Low Power | Next WFI should trigger low power entry | + + +## CFG_CDC_SYNC +The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the +fast clock domain but used in the slow clock domain. + +The configuration are not propagated across the clock boundary until this +register is triggered and read. See fields below for more details +- Offset: `0x18` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "SYNC", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:----------------------------| +| 31:1 | | | Reserved | +| 0 | rw | 0x0 | [SYNC](#cfg_cdc_sync--sync) | + +### CFG_CDC_SYNC . SYNC +Configuration sync. When this bit is written to 1, a sync pulse is generated. When +the sync completes, this bit then self clears. + +Software should write this bit to 1, wait for it to clear, before assuming the slow clock +domain has accepted the programmed values. + +## WAKEUP_EN_REGWEN +Configuration enable for wakeup_en register +- Offset: `0x1c` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, WAKEUP_EN register can be configured. When 0, WAKEUP_EN register cannot be configured. | + +## WAKEUP_EN +Bit mask for enabled wakeups +- Offset: `0x20` +- Reset default: `0x0` +- Reset mask: `0x3f` +- Register enable: [`WAKEUP_EN_REGWEN`](#wakeup_en_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:6 | | | | Reserved | +| 5 | rw | 0x0 | EN_5 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | +| 4 | rw | 0x0 | EN_4 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | +| 3 | rw | 0x0 | EN_3 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | +| 2 | rw | 0x0 | EN_2 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | +| 1 | rw | 0x0 | EN_1 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | +| 0 | rw | 0x0 | EN_0 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | + +## WAKE_STATUS +A read only register of all current wake requests post enable mask +- Offset: `0x24` +- Reset default: `0x0` +- Reset mask: `0x3f` + +### Fields + +```wavejson +{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_4", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_5", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------| +| 31:6 | | | | Reserved | +| 5 | ro | 0x0 | VAL_5 | Current value of wake requests | +| 4 | ro | 0x0 | VAL_4 | Current value of wake requests | +| 3 | ro | 0x0 | VAL_3 | Current value of wake requests | +| 2 | ro | 0x0 | VAL_2 | Current value of wake requests | +| 1 | ro | 0x0 | VAL_1 | Current value of wake requests | +| 0 | ro | 0x0 | VAL_0 | Current value of wake requests | + +## RESET_EN_REGWEN +Configuration enable for reset_en register +- Offset: `0x28` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, RESET_EN register can be configured. When 0, RESET_EN register cannot be configured. | + +## RESET_EN +Bit mask for enabled reset requests +- Offset: `0x2c` +- Reset default: `0x0` +- Reset mask: `0x3` +- Register enable: [`RESET_EN_REGWEN`](#reset_en_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | rw | 0x0 | EN_1 | Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device. | +| 0 | rw | 0x0 | EN_0 | Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device. | + +## RESET_STATUS +A read only register of all current reset requests post enable mask +- Offset: `0x30` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------| +| 31:2 | | | | Reserved | +| 1 | ro | 0x0 | VAL_1 | Current value of reset request | +| 0 | ro | 0x0 | VAL_0 | Current value of reset request | + +## ESCALATE_RESET_STATUS +A read only register of escalation reset request +- Offset: `0x34` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | ro | 0x0 | VAL | When 1, an escalation reset has been seen. When 0, there is no escalation reset. | + +## WAKE_INFO_CAPTURE_DIS +Indicates which functions caused the chip to wakeup +- Offset: `0x38` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | VAL | When written to 1, this actively suppresses the wakeup info capture. When written to 0, wakeup info capture timing is controlled by HW. | + +## WAKE_INFO +Indicates which functions caused the chip to wakeup. +The wake info recording begins whenever the device begins a valid low power entry. + +This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS. +This means it is possible to capture multiple wakeup reasons. +- Offset: `0x3c` +- Reset default: `0x0` +- Reset mask: `0xff` + +### Fields + +```wavejson +{"reg": [{"name": "REASONS", "bits": 6, "attr": ["rw1c"], "rotate": 0}, {"name": "FALL_THROUGH", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ABORT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-----------------------------------------| +| 31:8 | | | Reserved | +| 7 | rw1c | 0x0 | [ABORT](#wake_info--abort) | +| 6 | rw1c | 0x0 | [FALL_THROUGH](#wake_info--fall_through) | +| 5:0 | rw1c | 0x0 | [REASONS](#wake_info--reasons) | + +### WAKE_INFO . ABORT +The abort wakeup reason indicates that despite setting a WFI and providing a low power +hint, an active flash / lifecycle / otp transaction was ongoing when the power controller +attempted to initiate low power entry. + +The power manager detects this condition, halts low power entry and reports as a wakeup reason + +### WAKE_INFO . FALL_THROUGH +The fall through wakeup reason indicates that despite setting a WFI and providing a low power +hint, an interrupt arrived at just the right time to break the executing core out of WFI. + +The power manager detects this condition, halts low power entry and reports as a wakeup reason + +### WAKE_INFO . REASONS +Various peripheral wake reasons + +## FAULT_STATUS +A read only register that shows the existing faults +- Offset: `0x40` +- Reset default: `0x0` +- Reset mask: `0x7` + +### Fields + +```wavejson +{"reg": [{"name": "REG_INTG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ESC_TIMEOUT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_PD_GLITCH", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------|:----------------------------------------------------------| +| 31:3 | | | | Reserved | +| 2 | ro | 0x0 | MAIN_PD_GLITCH | When 1, unexpected power glitch was observed on main PD. | +| 1 | ro | 0x0 | ESC_TIMEOUT | When 1, an escalation clock / reset timeout has occurred. | +| 0 | ro | 0x0 | REG_INTG_ERR | When 1, an integrity error has occurred. | + + + diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/doc/theory_of_operation.md b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/theory_of_operation.md new file mode 100644 index 0000000000000..5f197a894c9e3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/doc/theory_of_operation.md @@ -0,0 +1,304 @@ +# Theory of Operation + +The power manager performs the following functions: +- Turn on/off power domain(s). +- Control root resets with the reset manager. +- Control root clock enables with AST and clock manager. +- Sequence various power up activities such as OTP sensing, life cycle initiation and releasing software to execute. + + +## Block Diagram + +See the below high level block diagram that illustrates the connections between the power manager and various system components. +Blocks outlined with a solid magenta line are always on; while blocks outlined with a dashed magenta line are a mix of components that are and those that are not. + +![Power Manager Connectivity Diagram](../doc/pwrmgr_connectivity.svg) + +## Overall Sequencing + +The power manager contains two state machines. +One operates on the always-on slow clock (this clock is always running and usually measured in KHz) and is responsible for turning faster clocks on and off and managing the power domains. +The other operates on a normal fixed clock (usually measured in MHz) and is responsible for everything else in the power sequence. + +The following diagram breaks down the general functionality of both. +The state machines are colored based on their clock domains. +The green state machine is clocked by the normal fixed domain, while the orange state machine is clocked by the slow domain. +Specific request / acknowledge signals are also highlighted in this color scheme to show where the two state machines communicate. + +![Power Manager FSMs](../doc/pwrmgr_fsms.svg) + + +Note, most of the states are transitional states, and only the following state combinations are resting states. + + +* Slow FSM `Idle` and fast FSM `Active` +* Slow FSM `Low Power` and fast FSM `Low Power` + +The slow FSM `Low Power` and fast FSM `Active` states specifically are concepts useful when examining [reset handling](#reset-request-handling). + + +## Slow Clock Domain FSM + +The slow clock domain FSM (referred to as the slow FSM from here on) resets to the Reset state. +This state is released by `por_rst_n`, which is supplied from the reset controller. +The `por_rst_n` signal is released when the reset controller detects the root power domains (`vcaon_pok` from AST) of the system are ready. +Please see the [ast](../../../ip/ast/README.md) for more details. + +The slow FSM requests the AST to power up the main domain and high speed clocks. +Once those steps are done, it requests the [fast FSM](#fast-clock-domain-fsm) to begin operation. +The slow FSM also handles power isolation controls as part of this process. + +Once the fast FSM acknowledges the power-up completion, the slow FSM transitions to `Idle` and waits for a power down request. +When a power down request is received, the slow FSM turns off AST clocks and power as directed by software configuration. +This means the clocks and power are not always turned off, but are rather controlled by software configurations in [`CONTROL`](registers.md#control) prior to low power entry . +Once these steps are complete, the slow FSM transitions to a low power state and awaits a wake request, which can come either as an actual wakeup, or a reset event (for example always on watchdog expiration). + +#### Sparse FSM + +Since the slow FSM is sparsely encoded, it is possible for the FSM to end up in an undefined state if attacked. +When this occurs, the slow FSM sends an `invalid` indication to the fast FSM and forcibly powers off and clamps everything. + +The clocks are kept on however to allow the fast FSM to operate if it is able to receive the `invalid` indication. +The slow FSM does not recover from this state until the system is reset by POR. + +Unlike [escalation resets](#escalation-reset-request), the system does not self reset. +Instead the system goes into a terminal non-responsive state where a user or host must directly intervene by toggling the power or asserting an external reset input. + +## Fast Clock Domain FSM + +The fast clock domain FSM (referred to as fast FSM from here on) resets to `Low Power` state and waits for a power-up request from the slow FSM. + +Once received, the fast FSM releases the life cycle reset stage (see [reset controller](../../rstmgr/README.md) for more details). +This allows the [OTP](../../../../ip/otp_ctrl/README.md) to begin sensing. +Once OTP sensing completes, the life cycle controller is initialized. +The initialization of the life cycle controller puts the device into its allowed operating state (see [life cycle controller](../../../../ip/lc_ctrl/README.md) for more details). + +Once life cycle initialization is done, the fast FSM enables all second level clock gating (see [clock controller](../../clkmgr/README.md) for more details) and initiates strap sampling. +For more details on what exactly the strap samples, please see [here](https://docs.google.com/spreadsheets/d/1pH8T1MhQ7TXtP_bFNT85T9jSVIHlxHAfbMnPbsMdjc0/edit?usp=sharing). + +Once strap sampling is complete, the system is ready to begin normal operations (note `flash_ctrl` initialization is explicitly not done here, please see [sections below](#flash-handling) for more details). +The fast FSM acknowledges the slow FSM (which made the original power up request) and releases the system reset stage - this enables the processor to begin operation. +Afterwards, the fast FSM transitions to `Active` state and waits for a software low power entry request. + +A low power request is initiated by software through a combination of WFI and software low power hint in [`CONTROL`](registers.md#control). +Specifically, this means if software issues only WFI, the power manager does not treat it as a power down request. +The notion of WFI is exported from the processor. +For Ibex, this is currently in the form of `core_sleeping_o`. + +In response to the low power entry request, the fast FSM disables all second level clock gating. +Before proceeding, the fast FSM explicitly separates the handling between a normal low power entry and a [reset request](#reset-request-handling). + +For low power entry, there are two cases, [fall through handling](#fall-through-handling) and [abort handling](#abort-handling). +If none of these exception cases are matched for low power entry, the fast FSM then asserts appropriate resets as necessary and requests the slow FSM to take over. + +For reset requests, fall through and aborts are not checked and the system simply resets directly. +Note in this scenario the slow FSM is not requested to take over. + +#### Sparse FSM + +Since the fast FSM is sparsely encoded, it is possible for the FSM to end up in an undefined state if attacked. +When this occurs, the fast FSM forcibly disables all clocks and holds the system in reset. + +The fast FSM does not recover from this state until the system is reset by POR. + + +### ROM Integrity Checks + +The power manager coordinates the [start up ROM check](../../../../ip/rom_ctrl/README.md#the-startup-rom-check) with `rom_ctrl`. + +After every reset, the power manager sends an indication to the `rom_ctrl` to begin performing integrity checks. +When the `rom_ctrl` checks are finished, a `done` and `good` indication are sent back to the power manager. + +If the device is in life cycle test states (`TEST_UNLOCKED` or `RMA`), the `good` signal is ignored and the ROM contents are always allowed to execute. + +If the device is not in one of the test states, the `good` signal is used to determine ROM execution. +If `good` is true, ROM execution is allowed. +If `good` is false, ROM execution is disallowed. + +### Fall Through Handling + +A low power entry fall through occurs when some condition occurs that immediately de-assert the entry conditions right after the software requests it. + +This can happen if right after software asserts WFI, an interrupt is shown to the processor, thus breaking it out of its currently stopped state. +Whether this type of fall through happens is highly dependent on how the system handles interrupts during low power entry - some systems may choose to completely silence any interrupt not related to wakeup, others may choose to leave them all enabled. +The fall through handle is specifically catered to the latter category. + +For a normal low power entry, the fast FSM first checks that the low power entry conditions are still true. +If the entry conditions are no longer true, the fast FSM "falls through" the entry handling and returns the system to active state, thus terminating the entry process. + +### Abort Handling + +If the entry conditions are still true, the fast FSM then checks there are no ongoing non-volatile activities from `otp_ctrl`, `lc_ctrl` and `flash_ctrl`. +If any module is active, the fast FSM "aborts" entry handling and returns the system to active state, thus terminating the entry process. + +## Reset Request Handling + +There are 4 reset requests in the system +- peripheral requested reset such as watchdog. +- reset manager's software requested reset, which is functionally very similar to a peripheral requested reset. +- power manager's internal reset request. +- Non-debug module reset. + +Flash brownout is handled separately and described in [flash handling section](#flash-handling) below. + +Note that the non-debug module reset is handled similarly to a peripheral requested reset, except that the non-debug module reset won't affect the debug module state and associated TAP muxing logic inside the pinmux. + +The power controller only observes reset requests in two states - the slow FSM `Low Power` state and the fast FSM `Active` state. +When a reset request is received during slow FSM `Low Power` state, the system begins its usual power up sequence even if a wakeup has not been received. + +When a reset request is received during fast FSM `Active` state, the fast FSM asserts resets and transitions back to its `Low Power` state. +The normal power-up process described [above](#fast-clock-domain-fsm) is then followed to release the resets. +Note in this case, the slow FSM is "not activated" and remains in its `Idle` state. + +### Power Manager Internal Reset Requests + +In additional to external requests, the power manager maintains 2 internal reset requests: +* Escalation reset request +* Main power domain unstable reset request + +#### Escalation Reset Request + +Alert escalation resets in general behave similarly to peripheral requested resets. +However, peripheral resets are always handled gracefully and follow the normal FSM transition. + +Alert escalations can happen at any time and do not always obey normal rules. +As a result, upon alert escalation, the power manager makes a best case effort to transition directly into reset handling. + +This may not always be possible if the escalation happens while the FSM is in an invalid state. +In this scenario, the pwrmgr keeps everything powered off and silenced and requests escalation handling if the system ever wakes up. + +#### Escalation Clock Timeout + +Under normal behavior, the power manager can receive escalation requests from the system and handle them [appropriately](#escalation-reset-request). +However, if the escalation clock or reset are non-functional for any reason, the escalation request would not be serviced. + +To mitigate this, the power manager actively checks for escalation interface clock/reset timeout. +This is done by a continuous request / acknowledge interface between the power manager's local clock/reset and the escalate network's clock/reset. + +If the request / acknowledge interface does not respond within 128 power manager clock cycles, the escalate domain is assumed to be off. +When this happens, the power manager creates a local escalation request that behaves identically to the global escalation request. + + +#### Main Power Unstable Reset Requests +If the main power ever becomes unstable (the power okay indication is low even though it is powered on), the power manager requests an internal reset. +This reset behaves similarly to the escalation reset and transitions directly into reset handling. + +Note that under normal low power conditions, the main power may be turned off. +As a result of this, the main power unstable checks are valid only during states that power should be on and stable. +This includes any state where power manager has requested the power to be turned on. + + +### Reset Requests Received During Other States + +All other states in the slow / fast FSM are considered transitional states. +Resets are not observed in other states because the system will always be transitioning towards one of the steady states (the system is in the process of powering down or powering up). +Once a steady state is reached, reset requests are then observed and processed. + +### Reset Recording + +There are two ways in which the device is reset: +- The reset requests mentioned in [reset handling](#reset-request-handling) +- Low power entry (`sleep_req` in the state diagram) + +The power manager handles only one of these at a time (see state diagrams). +This means if reset request and low power entry collide, the power manager will handle them on a first come first served basis. +When the handling of the first is completed, the power manager handles the second pending request if it is still present. + +This is done because low power resets and peripheral requested resets lead to different behaviors. +When the power manager commits to handling a specific request, it informs the reset manager why it has reset the processor. + +For example, assume a low power entry request arrives slightly ahead of reset requests. +The power manager will: +- Transition the system into low power state. +- Inform the reset manager to record "low power exit" as the reset reason. +- Once in low state, transition the system to `Active` state by using the reset request as a wakeup indicator. +- Inform the reset manager to also record the peripheral that requested reset. +- Once in `Active` state, reset the system and begin normal power-up routines again. + +If reset requests arrive slightly ahead of a low power entry request, then power manager will: +- Reset the system and begin normal power-up routines. +- Inform the reset manager to record the peripheral that requested reset. +- Once in `Active` state, if the low power entry request is still present, transition to low power state. + - Inform the reset manager to also record "low power exit" as the reset reason. +- If the low power entry request was wiped out by reset, the system then stays in `Active` state and awaits software instructions. + +Ultimately when control is returned to software, it may see two reset reasons and must handle them accordingly. + + +## Wakeup Recording + +Similar to [reset handling](#reset-request-handling), wakeup signals are only observed during slow FSM `Low Power`; however their recording is continuous until explicitly disabled by software. + +Wakeup recording begins when the fast FSM transitions out of `Active` state and continues until explicitly disabled by software. +This ensures wakeup events are not missed until software has set up the appropriate peripherals. +Recording needs clocks to be active, and during low power they are usually not. +For this reason, it is important for wakeups to be level and remain active until software clears them. + +The software is also able to enable recording during `Active` state if it chooses to do so. The recording enables are OR’d together for hardware purposes. + + +## Flash Handling +For the section below, flash macro refers to the proprietary flash storage supplied by a vendor. +`flash_ctrl`, on the other hand, refers to the open source controller that manages access to the flash macro. + +### Power-Up Handling + +The [AST](../../../ip/ast/README.md) automatically takes the flash macro out of power down state as part of the power manager's power up request. + +Once flash macro is powered up and ready, an indication is sent to the `flash_ctrl`. + +Once the boot ROM is allowed to execute, it is expected to further initialize the `flash_ctrl` and flash macro prior to using it. +This involves the following steps: + +* Poll `flash_ctrl` register to ensure flash macro has powered up and completed internal initialization. +* Initialize `flash_ctrl` seed reading and scrambling. + +### Power-Down Handling + +Before the device enters low power, the pwrmgr first checks to ensure there are no ongoing transactions to the flash macro. +When the device enters deep sleep, the flash macro is automatically put into power down mode by the AST. +The AST places the flash macro into power down through direct signaling between AST and flash macro, the pwrmgr is not directly involved. + +When the device exits low power state, it is the responsibility of the boot ROM to poll for flash macro and `flash_ctrl` power-up complete similar to the above section. + +### Flash Brownout Handling + +When the external supply of the device dips below a certain threshold during a non-volatile flash macro operation (program or erase), the flash macro requires the operation to terminate in a pre-defined manner. +This sequence will be exclusively handled by the AST. + +The power manager is unaware of the difference between POR and flash brownout. +Because of this, the software also cannot distinguish between these two reset causes. + + +## Supported Low Power Modes + +This section details the various low power modes supported by OpenTitan. + + +### Deep Sleep or Standby + +This is the lowest power mode of the device (outside of full power down or device held in reset). +During this state: + +* All clocks other than the always-on slow clock are turned off at the source. +* All non-always-on digital domains are powered off. +* I/O power domains may or may not be off. + * The state of the IO power domain has no impact on the digital core’s power budget, e.g. the IO power being off does not cause the accompanying digital logic in pads or elsewhere to leak more. + + +### Normal Sleep + +This is a fast low power mode of the device that trades-off power consumption for resume latency. +During this state: + +* All clocks other than the KHz slow clock are turned off at the source. +* All power domains are kept on for fast resume. +* Sensor countermeasures can be opportunistically on. +* I/O power domains may or may not be off. + * The state of the IO power domain has no impact on the digital core’s power budget, e.g. the IO power being off does not cause the accompanying digital logic in pads or elsewhere to leak more. + +## Debug + +When performing TAP debug, it is important for the debugging software to prevent the system from going to low power. +If the system enters low power during live debug, the debug session will be broken. +There is currently no standardized way to do this, so it is up to the debugging agent to perform the correct steps. diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/README.md b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/README.md new file mode 100644 index 0000000000000..cbcc66c68344f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/README.md @@ -0,0 +1,255 @@ +# PWRMGR DV document + +## Goals +* **DV** + * Verify all PWRMGR IP features by running dynamic simulations with a SV/UVM based testbench. + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules. +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench. + +## Current status +* [Design & verification stage](../doc/checklist.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/top_darjeeling/ip_autogen/pwrmgr/dv/latest/report.html) + +## Design features +For detailed information on PWRMGR design features, please see the [PWRMGR HWIP technical specification](../README.md). + +## Testbench architecture +PWRMGR testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +### Block diagram +![Block diagram](./doc/tb.svg) + +### Top level testbench +Top level testbench is located at [`hw/top_darjeeling/ip_autogen/pwrmgr/dv/tb.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/pwrmgr/dv/tb.sv). +It instantiates the PWRMGR DUT module [`hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr.sv). +In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [TileLink host interface](../../../../dv/sv/tl_agent/README.md) +* PWRMGR interface [`hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv). +* Interrupts ([`pins_if`](../../../../dv/sv/common_ifs/README.md)) +* Alerts ([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md)) + +### Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +### Global types & methods +All common types and methods defined at the package level can be found in +[`pwrmgr_env_pkg`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env_pkg.sv). +Some of them in use are: +```systemverilog + typedef enum int { + WakeupSysrst, + WakeupDbgCable, + WakeupPin, + WakeupUsb, + WakeupAonTimer, + WakeupSensorCtrl + } wakeup_e; + + typedef struct packed { + logic main_pd_n; + logic usb_clk_en_active; + logic usb_clk_en_lp; + logic io_clk_en; + logic core_clk_en; + } control_enables_t; + + typedef bit [pwrmgr_reg_pkg::NumWkups-1:0] wakeups_t; + typedef bit [pwrmgr_reg_pkg::NumRstReqs-1:0] resets_t; + + // This is used to send all resets to rstmgr. + typedef bit [pwrmgr_pkg::HwResetWidth-1:0] resets_out_t; +``` +### TL_agent +PWRMGR testbench instantiates (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md) which provides the ability to drive and independently monitor random traffic via TL host interface into PWRMGR device. + +### UVM RAL Model +The PWRMGR RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md). + +### Stimulus strategy +The sequences are closely related to the testplan's testpoints. +Testpoints and coverage are described in more detail in the [testplan](#testplan). +All test sequences reside in [`hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib), and extend `pwrmgr_base_vseq`. +The `pwrmgr_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. +It provides commonly used handles, variables, functions and tasks used by the test sequences. +Some of the most commonly used tasks and functions are as follows: +* task `wait_for_fast_fsm`: + Waits for the fast fsm to be active or inactive, indicated by whether the `fetch_en_o` output become On or Off respectively. + We mostly call this expecting it to be active before the tests can start, since any CSR accesses require the CPU to be running. + Due to complexities in the UVM sequences this task is called in the virtual post_apply_reset task of dv_base_vseq. +* task `wait_for_csr_to_propagate_to_slow_domain`: + Waits for `cfg_cdc_sync` CSR to be clear, indicating the CDC to the slow clock has completed. +* task `wait_for_reset_cause`: + Waits for the `pwr_rst_req.reset_cause` output to match an expected cause. +* task `check_wait_info`: + Checks the wake_info CSR matches expectations. +* task `check_reset_status`: + Checks the reset_status CSR matches expectations. +* task `check_and_clear_interrupt`: + Checks the interrupt enable, status, and output pin. + +In addition, the base sequence provides two tasks that provide expected inputs based on the pwrmgr outputs. +In the absence of these inputs the pwrmgr will be stuck waiting forever. +Being based on outputs means the inputs are in accordance to the implicit protocol. +The tasks in question are: +* task `slow_responder`: + Handles required input changes from AST for the slow state machine. + For the various `_en` outputs it changes the `_val` as required, for `core`, `io`, `main`, and `usb` clocks. +* task `fast_responder`: + Handles input changes for the fast state machine. + * Completes the handshake with rstmgr for lc and sys resets: some random cycles after an output reset is requested the corresponding reset src input must go low. + * Completes the handshake with clkmgr: the various `_status` inputs need to match the corresponding `_ip_clk_en` output after some cycles, for `io`, `main`, and `usb` clocks. + * Completes the handshake with lc and otp: both *_done inputs must match the corresponding *_init outputs after some cycles. + +These tasks are started by the parent sequence's `pre_start` task, and terminated gracefully in the parent sequence's `post_start` task. +### Test sequences +The test sequences besides the base are as follows: +* `pwrmgr_smoke_vseq` tests the pwrmgr through POR, entry and exit from software initiated low power and reset. +* `pwrmgr_wakeup_vseq` checks the transitions to low power and the wakeup settings. + It randomizes wakeup inputs, wakeup enables, the wakeup info capture enable, and the interrupt enable. +* `pwrmgr_aborted_low_power_vseq` creates scenarios that lead to aborting a low power transition. + The abort can be due to the processor waking up very soon, or otp, lc, or flash being busy. +* `pwrmgr_reset_vseq` checks the pwrmgr response to conditional resets and reset enables, and unconditional escalation and main power glitch resets. +* `pwrmgr_wakeup_reset_vseq` aligns reset and wakeup from low power. +* `pwrmgr_lowpower_wakeup_race_vseq` aligns a wakeup event coming in proximity to low power entry. + Notice the wakeup is not expected to impact low power entry, since it is not sampled at this time. + +### Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The following covergroups have been developed to prove that the test intent has been adequately met: +* `wakeup_ctrl_cg` covers wakeup and capture control. +* `wakeup_intr_cg` covers control of the interrupt due to a wakeup. +* `control_cg` covers clock controls. +* `hw_reset_0_cg` covers external reset via `rstreqs_i[0]`. +* `hw_reset_1_cg` covers external reset via `rstreqs_i[1]`. +* `rstmgr_sw_reset_cg` covers software initiated resets via rstmgr CSR. +* `main_power_reset_cg` covers resets due to a main power glitch. +* `esc_reset_cg` covers resets due to an incoming escalation. +* `reset_wakeup_distance_cg` covers the distance in clock cycles between a wakeup and a reset request. + +More details about these sequences and covergroups can be found at [testplan](#testplan). + +### Self-checking strategy +Many of the checks are performed via SVA, and are enabled for all test sequences. +Refer to the [assertions](#assertions) section below for details. + +#### Scoreboard +The `pwrmgr_scoreboard` is primarily used for end to end checking. + +Many inputs must have specific transitions to prevent the pwrmgr fsms from wait forever. +When possible the transitions are triggered by pwrmgr output changes. +These are described according to the unit that originates or is the recipient of the ports. +See also the test plan for specific ways these are driven to trigger different testpoints. + +##### AST +- Output `slow_clk_en` is always on. +- Input `slow_clk_val` is unused. +- Outputs `core_clk_en`, `io_clk_en`, and `usb_clk_en` reset low, and go high prior to the slow fsm requesting the fast fsm to wakeup. + Notice the usb clock can be programmed to stay low on wakeup via the `control` CSR. + These clock enables are cleared on reset, and should match their corresponding enables in the `control` CSR on low power transitions. + These clock enables are checked via SVAs in [`hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv). + When slow fsm transitions to `SlowPwrStateReqPwrUp` the clock enables should be on (except usb should match `control.usb_clk_en_active`). + When slow fsm transitions to `SlowPwrStatePwrClampOn` the clock enables should match their bits in the `control` CSR. +- Inputs `core_clk_val`, `io_clk_val`, and `usb_clk_val` track the corresponding enables. + They are driven by `slow_responder`, which turn them off when their enables go off, and turn them back on a few random slow clock cycles after their enables go on. + Slow fsm waits for them to go high prior to requesting fast fsm wakeup. + Lack of a high transition when needed is detected via timeout. + Such timeout would be due to the corresponding enables being set incorrectly. + These inputs are checked via SVAs in [`hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv). +- Output `main_pd_n` should go high when slow fsm transitions to `SlowPwrStateMainPowerOn`, and should match `control.main_pd_n` CSR when slow fsm transitions to `SlowPwrStateMainPowerOff`. +- Input `main_pok` should turn on for the slow fsm to start power up sequence. + This is also driven by `slow_responder`, which turn this off in response to `main_pd_n` going low, and turn it back on after a few random slow clock cycles from `main_pd_n` going high. + Lack of a high transition causes a timeout, and would point to `main_pd_n` being set incorrectly. +- Output transitions of `pwr_clamp_env` must always precede transitions of + `pwr_clamp` output. + Output transitions of `pwr_clamp` to active must always precede transitions + of `main_pd_n` output to active. + Output transitions of `pwr_clamp` to inactive must always follow transitions + of `main_pd_n` output to inactive. + +##### RSTMGR +- Output `rst_lc_req` resets to 1, also set on reset transition, and on low power transitions that turn off main clock. + Cleared early on during the steps to fast fsm active. +- Input `rst_lc_src_n` go low in response to `rst_lc_req` high, go high when `rst_lc_req` clears (and lc is reset). + Driven by `fast_responder` in response to `rst_lc_req`, waiting a few random cycles prior to transitions. + Fast fsm waits for it to go low before deactivating, and for it to go high before activating. + Checked implicitly by lack of timeout: a timeout would be due to `rst_lc_req` being set incorrectly, and by SVA as described below. +- Output `rst_sys_req` resets to 1, also set to on reset, and on low power transitions that turn off main clock. + Cleared right before the fast fsm goes active. +- Input `rst_sys_src_n` go low in response to `rst_sys_req` high. + Transitions go high when `rst_sysd_req` clears (and lc is reset). + Fast fsm waits for it to go low before deactivating. + Also driver by `fast_responder`. + Checked implicitly by lack of timeout, and by SVA. +- Output `rstreqs` correspond to the enabled pwrmgr rstreqs inputs plus main power glitch, escalation reset, and software reset request from RSTMGR. + Checked in scoreboard and SVA. +- Output `reset_cause` indicates a reset is due to low power entry or a reset request. + Checked in scoreboard. + +##### CLKMGR +- Outputs `pwr_clk_o._ip_clk_en` reset low, are driven high by fast fsm when going active, and driven low when going inactive. + The `` correspond to `io`, `main`, and `usb`. +- Inputs `pwr_clk_i._status` are expected to track `pwr_clk_o._ip_clk_en`. + Fast fsm waits for them going high prior to going active, and going low prior to deactivating. + These are controlled by the `control` CSR. + Driven by `fast_responder`, which turns them off when `_ip_clk_en` goes low, and turns them back on a few random cycles after `_ip_clk_en` goes high. + Checked by lack of a timeout: such timeout would be due to `ip_clk_en` being set incorrectly. + Also checked by SVA. + +##### OTP +- Output `otp_init` resets low, goes high when the fast fsm is going active, and low after the `otp_done` input goes high. +- Input `otp_done` is driven by `fast_responder`. + It is initialized low, and goes high some random cycles after `otp_init` goes high. + The sequencer will timeout if `otp_init` is not driven high. +- Input `otp_idle` normally set high, but is set low by the `pwrmgr_aborted_low_power_vseq` sequence. + +##### LC +The pins connecting to LC behave pretty much the same way as those to OTP. + +##### FLASH +- Input `flash_idle` is handled much like `lc_idle` and `otp_idle`. + +##### CPU +- Input `core_sleeping` is driven by sequences. + It is driven low to enable a transition to low power. + After the transition is under way it is a don't care. + The `pwrmgr_aborted_low_power_vseq` sequence sets it carefully to abort a low power entry soon after the attempt because the processor wakes up. + +##### Wakeups and Resets +There are a number of wakeup and reset requests. +They are driven by sequences as they need to. + +#### Assertions +The [`hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv) module binds a few modules containing assertions to the IP as follows: +* TLUL assertions: the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) ensures TileLink interface protocol compliance. +* Clock enables assertions: + The `pwrmgr_clock_enables_sva_if` module contains assertions checking that the various clk_en outputs correspond to the settings in the `control` CSR. +* CLKMGR clk_en to status handshake assertions: + The `clkmgr_pwrmgr_sva_if` contains assertions checking the various `_status` inputs track the corresponding `_ip_clk_en` outputs. +* AST input/output handshake assertions: + The `pwrmgr_ast_sva_if` module contains assertions checking that the inputs from the AST respond to the pwrmgr outputs. +* RSTMGR input/output handshake assertions: + The `pwrmgr_rstmgr_sva_if` module contains assertions checking the following: + * The `rst_lc_src_n` input from RSTMGR respond to the `rst_lc_req` pwrmgr output. + * The `rst_sys_src_n` input from RSTMGR respond to the `rst_sys_req` pwrmgr output. + * The different `pwr_rst_o.rstreqs` output bits track the corresponding reset causes. + These include hardware, power glitch, escalation, and software resets. + +In addition, the RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. + +## Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson -i pwrmgr_smoke +``` + +## Testplan +[Testplan](../data/pwrmgr_testplan.hjson) diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/cov/pwrmgr_cov_bind.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/cov/pwrmgr_cov_bind.sv new file mode 100644 index 0000000000000..d3a4d08cfed6c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/cov/pwrmgr_cov_bind.sv @@ -0,0 +1,33 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: +// Power manager coverage bindings for multi bus input +module pwrmgr_cov_bind; + + bind pwrmgr cip_lc_tx_cov_if u_lc_dft_en_mubi_cov_if ( + .rst_ni (rst_ni), + .val (lc_dft_en_i) + ); + + bind pwrmgr cip_lc_tx_cov_if u_lc_hw_debug_en_mubi_cov_if ( + .rst_ni (rst_ni), + .val (lc_hw_debug_en_i) + ); + + bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_rom_ctrl_good_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (rom_ctrl_i.done) + ); + + bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_rom_ctrl_done_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (rom_ctrl_i.good) + ); + + bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_sw_rst_req_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (sw_rst_req_i) + ); +endmodule // pwrmgr_cov_bind diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el new file mode 100644 index 0000000000000..6e3e974019c86 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el @@ -0,0 +1,34 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//================================================== +// This file contains the Excluded objects +// Generated By User: jdonjdon +// Format Version: 2 +// Date: Sun Sep 25 22:09:48 2022 +// ExclMode: default +//================================================== +CHECKSUM: "2301929872 963630968" +INSTANCE: tb.dut.u_esc_rx.u_prim_count +ANNOTATION: "[UNSUPPORTED] Ports are assigned constant by RTL." +Toggle step_i "net step_i[21:0]" +Toggle set_cnt_i "net set_cnt_i[21:0]" +CHECKSUM: "3681358461" +INSTANCE: tb.dut.u_esc_timeout.u_ref_timeout +ANNOTATION: "[UNR] Input req_chk_i is tied to constant 0 and src_req_i to constant 1" +Assert SyncReqAckHoldReq "assertion" +CHECKSUM: "2699797328" +INSTANCE: tb.dut.pwrmgr_ast_sva_if +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert CoreClkGlitchToEnOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert UsbClkGlitchToValOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert UsbClkGlitchToEnOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert IoClkGlitchToValOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert IoClkGlitchToEnOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert CoreClkGlitchToValOff_A "assertion" diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/cov/pwrmgr_tgl_excl.cfg b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/cov/pwrmgr_tgl_excl.cfg new file mode 100644 index 0000000000000..9d1f7fd2c62b1 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/cov/pwrmgr_tgl_excl.cfg @@ -0,0 +1,9 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//====================================================================== +// This file contains outputs of pwrmgr tied to constants. +//====================================================================== + +-module_node pwrmgr pwr_ast_o.slow_clk_en diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/doc/tb.svg b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/doc/tb.svg new file mode 100644 index 0000000000000..285ef6948e4dc --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/doc/tb.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core new file mode 100644 index 0000000000000..731e28063b434 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core @@ -0,0 +1,55 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:pwrmgr_env:0.1" +description: "PWRMGR DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:ip_interfaces:pwrmgr_pkg + files: + - pwrmgr_env_pkg.sv + - pwrmgr_env_cfg.sv: {is_include_file: true} + - pwrmgr_env_cov.sv: {is_include_file: true} + - pwrmgr_if.sv + - pwrmgr_virtual_sequencer.sv: {is_include_file: true} + - pwrmgr_scoreboard.sv: {is_include_file: true} + - pwrmgr_env.sv: {is_include_file: true} + - seq_lib/pwrmgr_vseq_list.sv: {is_include_file: true} + - seq_lib/pwrmgr_base_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_aborted_low_power_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_common_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_reset_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_smoke_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_stress_all_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_wakeup_reset_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_wakeup_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_sw_reset_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_global_esc_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_escalation_timeout_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_glitch_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_reset_invalid_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_lowpower_invalid_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: pwrmgr + ip_hjson: ../../data/pwrmgr.hjson + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.sv new file mode 100644 index 0000000000000..96646b5f2a912 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env.sv @@ -0,0 +1,57 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_env extends cip_base_env #( + .CFG_T (pwrmgr_env_cfg), + .COV_T (pwrmgr_env_cov), + .VIRTUAL_SEQUENCER_T(pwrmgr_virtual_sequencer), + .SCOREBOARD_T (pwrmgr_scoreboard) +); + `uvm_component_utils(pwrmgr_env) + + alert_esc_agent m_esc_agent; + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "slow_clk_rst_vif", cfg.slow_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get slow_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "esc_clk_rst_vif", cfg.esc_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get esc_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "lc_clk_rst_vif", cfg.lc_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get lc_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual pwrmgr_if)::get(this, "", "pwrmgr_vif", cfg.pwrmgr_vif)) begin + `uvm_fatal(`gfn, "failed to get pwrmgr_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual pwrmgr_clock_enables_sva_if)::get( + this, "", "pwrmgr_clock_enables_sva_vif", cfg.pwrmgr_clock_enables_sva_vif + )) begin + `uvm_fatal(`gfn, "failed to get pwrmgr_clock_enables_sva_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual pwrmgr_rstmgr_sva_if)::get( + this, "", "pwrmgr_rstmgr_sva_vif", cfg.pwrmgr_rstmgr_sva_vif + )) begin + `uvm_fatal(`gfn, "failed to get pwrmgr_rstmgr_sva_vif from uvm_config_db") + end + + m_esc_agent = alert_esc_agent::type_id::create("m_esc_agent", this); + uvm_config_db#(alert_esc_agent_cfg)::set(this, "m_esc_agent", "cfg", cfg.m_esc_agent_cfg); + cfg.m_esc_agent_cfg.en_cov = cfg.en_cov; + + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cfg.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cfg.sv new file mode 100644 index 0000000000000..b94e743ad01c3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cfg.sv @@ -0,0 +1,52 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_env_cfg extends cip_base_env_cfg #( + .RAL_T(pwrmgr_reg_block) +); + + // disable fault csr read check from scoreboard + bit disable_csr_rd_chk = 0; + + // Invalid state test. Used to disable interrupt check. + bit invalid_st_test = 0; + + // ext component cfgs + alert_esc_agent_cfg m_esc_agent_cfg; + + `uvm_object_utils_begin(pwrmgr_env_cfg) + `uvm_object_utils_end + + `uvm_object_new + + // ext interfaces + virtual clk_rst_if esc_clk_rst_vif; + virtual clk_rst_if lc_clk_rst_vif; + virtual clk_rst_if slow_clk_rst_vif; + virtual pwrmgr_if pwrmgr_vif; + virtual pwrmgr_clock_enables_sva_if pwrmgr_clock_enables_sva_vif; + virtual pwrmgr_rstmgr_sva_if pwrmgr_rstmgr_sva_vif; + + // The run_phase object, to deal with objections. + uvm_phase run_phase; + + virtual function void initialize(bit [31:0] csr_base_addr = '1); + list_of_alerts = pwrmgr_env_pkg::LIST_OF_ALERTS; + super.initialize(csr_base_addr); + num_interrupts = ral.intr_state.get_n_used_bits(); + `ASSERT_I(NumInstrMatch_A, num_interrupts == NUM_INTERRUPTS) + `uvm_info(`gfn, $sformatf("num_interrupts = %0d", num_interrupts), UVM_MEDIUM) + + // pwrmgr_tl_intg_err test uses default alert name "fata_fault" + // and it requires following field to be '1' + tl_intg_alert_fields[ral.fault_status.reg_intg_err] = 1; + m_tl_agent_cfg.max_outstanding_req = 1; + m_esc_agent_cfg = alert_esc_agent_cfg::type_id::create("m_esc_agent_cfg"); + `DV_CHECK_RANDOMIZE_FATAL(m_esc_agent_cfg) + m_esc_agent_cfg.is_alert = 0; + // Disable escalation ping coverage. + m_esc_agent_cfg.en_ping_cov = 0; + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cov.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cov.sv new file mode 100644 index 0000000000000..b348b99ea00b3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cov.sv @@ -0,0 +1,193 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Covergoups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here. + * Covergroups may also be wrapped inside helper classes if needed. + */ + +`include "cip_macros.svh" + +// Wrapper class for wakeup control covergroup. +class pwrmgr_wakeup_ctrl_cg_wrap; + // This covers enable, capture, and status of wakeups. + covergroup wakeup_ctrl_cg(string name) with function sample (bit enable, bit capture, bit wakeup); + option.name = name; + option.per_instance = 1; + + enable_cp: coverpoint enable; + capture_cp: coverpoint capture; + wakeup_cp: coverpoint wakeup; + + wakeup_cross: cross enable_cp, capture_cp, wakeup_cp; + endgroup + + function new(string name); + wakeup_ctrl_cg = new(name); + endfunction + + function void sample (bit enable, bit capture, bit wakeup); + wakeup_ctrl_cg.sample(enable, capture, wakeup); + endfunction +endclass + +// Wrapper class for wakeup interrupt covergroup. +class pwrmgr_wakeup_intr_cg_wrap; + // This covers interrupts generated by wakeups. + covergroup wakeup_intr_cg( + string name + ) with function sample ( + bit wakeup, bit enable, bit status, bit interrupt + ); + option.name = name; + option.per_instance = 1; + + enable_cp: coverpoint enable; + status_cp: coverpoint status; + wakeup_cp: coverpoint wakeup; + interrupt_cp: coverpoint interrupt; + + interrupt_cross: cross enable_cp, status_cp, wakeup_cp, interrupt_cp{ + // An interrupt cannot happen unless wake_status is on. + ignore_bins no_wakeup = interrupt_cross with (!wakeup_cp && interrupt_cp); + // An interrupt cannot happen unless it is enabled. + ignore_bins disable_pin = interrupt_cross with (!enable_cp && interrupt_cp); + // An interrupt cannot happen if intr_status is off. + ignore_bins no_status_pin = interrupt_cross with (!status_cp && interrupt_cp); + // If all preconditions are satisfied there must be an interrupt. + ignore_bins missing_int = interrupt_cross with (enable_cp && status_cp && wakeup_cp && + !interrupt_cp); + } + endgroup + + function new(string name); + wakeup_intr_cg = new(name); + endfunction + + function void sample (bit enable, bit status, bit wakeup, bit interrupt); + wakeup_intr_cg.sample(wakeup, enable, status, interrupt); + endfunction +endclass + +class pwrmgr_env_cov extends cip_base_env_cov #( + .CFG_T(pwrmgr_env_cfg) +); + `uvm_component_utils(pwrmgr_env_cov) + + // the base class provides the following handles for use: + // pwrmgr_env_cfg: cfg + + // covergroups + pwrmgr_wakeup_ctrl_cg_wrap wakeup_ctrl_cg_wrap[pwrmgr_reg_pkg::NumWkups]; + pwrmgr_wakeup_intr_cg_wrap wakeup_intr_cg_wrap[pwrmgr_reg_pkg::NumWkups]; + + // This collects coverage on the clock and power control functionality. + covergroup control_cg with function sample (control_enables_t control_enables, bit sleep); + core_cp: coverpoint control_enables.core_clk_en; + io_cp: coverpoint control_enables.io_clk_en; + usb_lp_cp: coverpoint control_enables.usb_clk_en_lp; + usb_active_cp: coverpoint control_enables.usb_clk_en_active; + main_pd_n_cp: coverpoint control_enables.main_pd_n; + sleep_cp: coverpoint sleep; + + control_cross: cross core_cp, io_cp, usb_lp_cp, usb_active_cp, main_pd_n_cp, sleep_cp; + endgroup + + covergroup hw_reset_0_cg with function sample (logic reset, logic enable, bit sleep); + reset_cp: coverpoint reset; + enable_cp: coverpoint enable; + sleep_cp: coverpoint sleep; + reset_cross: cross reset_cp, enable_cp, sleep_cp { + // Reset and sleep are mutually exclusive. + illegal_bins illegal = reset_cross with (reset_cp && sleep_cp); + } + endgroup + + covergroup hw_reset_1_cg with function sample (logic reset, logic enable, bit sleep); + reset_cp: coverpoint reset; + enable_cp: coverpoint enable; + sleep_cp: coverpoint sleep; + reset_cross: cross reset_cp, enable_cp, sleep_cp { + // Reset and sleep are mutually exclusive. + illegal_bins illegal = reset_cross with (reset_cp && sleep_cp); + } + endgroup + + // This reset cannot be generated in low power state since it is triggered by software. + covergroup rstmgr_sw_reset_cg with function sample (logic sw_reset); + sw_reset_cp: coverpoint sw_reset; + endgroup + + covergroup main_power_reset_cg with function sample (logic main_power_reset, bit sleep); + main_power_reset_cp: coverpoint main_power_reset; + sleep_cp: coverpoint sleep; + reset_cross: cross main_power_reset_cp, sleep_cp { + // Any reset and sleep are mutually exclusive. + illegal_bins illegal = reset_cross with (main_power_reset_cp && sleep_cp); + } + endgroup + + covergroup esc_reset_cg with function sample (logic esc_reset, bit sleep); + esc_reset_cp: coverpoint esc_reset; + sleep_cp: coverpoint sleep; + reset_cross: cross esc_reset_cp, sleep_cp { + // Any reset and sleep are mutually exclusive. + illegal_bins illegal = reset_cross with (esc_reset_cp && sleep_cp); + } + endgroup + + // This measures the number of cycles between the reset and wakeup. + // It is positive when reset happened after wakeup, and zero when they coincided in time. + covergroup reset_wakeup_distance_cg with function sample (int cycles); + cycles_cp: coverpoint cycles { + bins close[] = {[-4 : 4]}; + bins far = default; + } + endgroup + + // This covers the rom inputs that should prevent entering the active state. + covergroup rom_active_blockers_cg with function sample ( + logic [3:0] done, logic [3:0] good, logic [3:0] dft, logic [3:0] debug + ); + done_cp: coverpoint done { + `DV_MUBI4_CP_BINS + } + good_cp: coverpoint good { + `DV_MUBI4_CP_BINS + } + dft_cp: coverpoint dft { + `DV_LC_TX_T_CP_BINS + } + debug_cp: coverpoint debug { + `DV_LC_TX_T_CP_BINS + } + blockers_cross: cross done_cp, good_cp, dft_cp, debug_cp; + endgroup + + function new(string name, uvm_component parent); + super.new(name, parent); + foreach (wakeup_ctrl_cg_wrap[i]) begin + pwrmgr_env_pkg::wakeup_e wakeup = pwrmgr_env_pkg::wakeup_e'(i); + wakeup_ctrl_cg_wrap[i] = new({wakeup.name, "_ctrl_cg"}); + wakeup_intr_cg_wrap[i] = new({wakeup.name, "_intr_cg"}); + end + control_cg = new(); + hw_reset_0_cg = new(); + hw_reset_1_cg = new(); + rstmgr_sw_reset_cg = new(); + main_power_reset_cg = new(); + esc_reset_cg = new(); + reset_wakeup_distance_cg = new(); + rom_active_blockers_cg = new(); + endfunction : new + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + // [or instantiate covergroups here] + // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky + // See cip_base_env_cov for details + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env_pkg.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env_pkg.sv new file mode 100644 index 0000000000000..abfb1c051a061 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_env_pkg.sv @@ -0,0 +1,89 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package pwrmgr_env_pkg; + // dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import dv_lib_pkg::*; + import tl_agent_pkg::*; + import cip_base_pkg::*; + import dv_base_reg_pkg::*; + import csr_utils_pkg::*; + import pwrmgr_ral_pkg::*; + import alert_esc_agent_pkg::*; + import pwrmgr_pkg::PowerDomains; + import prim_mubi_pkg::mubi4_t; + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4True; + import prim_mubi_pkg::MuBi4Width; + import sec_cm_pkg::*; + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // parameters + parameter int NUM_INTERRUPTS = 1; + + // clk enable disable delay + parameter uint MAIN_CLK_DELAY_MIN = 15; + parameter uint MAIN_CLK_DELAY_MAX = 258; + parameter uint ESC_CLK_DELAY_MIN = 1; + parameter uint ESC_CLK_DELAY_MAX = 10; + + // alerts + parameter uint NUM_ALERTS = 1; + parameter string LIST_OF_ALERTS[] = {"fatal_fault"}; + + // types + typedef enum int { + WakeupSysrst, + WakeupDbgCable, + WakeupPin, + WakeupUsb, + WakeupAonTimer, + WakeupSensorCtrl + } wakeup_e; + + typedef enum int { + PwrmgrMubiNone = 0, + PwrmgrMubiLcCtrl = 1, + PwrmgrMubiRomCtrl = 2 + } pwrmgr_mubi_e; + + typedef struct packed { + logic main_pd_n; + logic usb_clk_en_active; + logic usb_clk_en_lp; + logic io_clk_en; + logic core_clk_en; + } control_enables_t; + + typedef bit [pwrmgr_reg_pkg::NumWkups-1:0] wakeups_t; + typedef bit [pwrmgr_reg_pkg::NumRstReqs-1:0] resets_t; + + // This is used to send all resets to rstmgr. + typedef bit [pwrmgr_pkg::HwResetWidth-1:0] resets_out_t; + + // need a short name to avoid 100 line cut off + parameter int MUBI4W = prim_mubi_pkg::MuBi4Width; + + // functions + + // variables + bit [NUM_INTERRUPTS-1:0] exp_intr; + wakeups_t exp_wakeup_reasons; + control_enables_t control_enables; + logic low_power_hint; + + // package sources + `include "pwrmgr_env_cfg.sv" + `include "pwrmgr_env_cov.sv" + `include "pwrmgr_virtual_sequencer.sv" + `include "pwrmgr_scoreboard.sv" + `include "pwrmgr_env.sv" + `include "pwrmgr_vseq_list.sv" + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv new file mode 100644 index 0000000000000..2a6e7202d8e36 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv @@ -0,0 +1,219 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// pwrmgr interface. +// +// Samples some internal signals to help coverage collection: +interface pwrmgr_if ( + input logic clk, + input logic rst_n, + input logic clk_slow, + input logic rst_slow_n +); + import uvm_pkg::*; + import pwrmgr_env_pkg::*; + + // Ports to the dut side. + + logic rst_main_n; + + pwrmgr_pkg::pwr_ast_req_t pwr_ast_req; + pwrmgr_pkg::pwr_ast_rsp_t pwr_ast_rsp; + + pwrmgr_pkg::pwr_rst_req_t pwr_rst_req; + pwrmgr_pkg::pwr_rst_rsp_t pwr_rst_rsp; + + pwrmgr_pkg::pwr_clk_req_t pwr_clk_req; + pwrmgr_pkg::pwr_clk_rsp_t pwr_clk_rsp; + + pwrmgr_pkg::pwr_otp_req_t pwr_otp_req; + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_rsp; + + pwrmgr_pkg::pwr_lc_req_t pwr_lc_req; + pwrmgr_pkg::pwr_lc_rsp_t pwr_lc_rsp; + + pwrmgr_pkg::pwr_flash_t pwr_flash; + + pwrmgr_pkg::pwrmgr_cpu_t cpu_i; + pwrmgr_pkg::pwr_cpu_t pwr_cpu; + + lc_ctrl_pkg::lc_tx_t fetch_en; + lc_ctrl_pkg::lc_tx_t lc_hw_debug_en; + lc_ctrl_pkg::lc_tx_t lc_dft_en; + + logic [ pwrmgr_reg_pkg::NumWkups-1:0] wakeups_i; + logic [pwrmgr_reg_pkg::NumRstReqs-1:0] rstreqs_i; + + logic strap; + logic low_power; + rom_ctrl_pkg::pwrmgr_data_t rom_ctrl; + + prim_mubi_pkg::mubi4_t sw_rst_req_i; + + logic intr_wakeup; + + // Relevant CSR values. + logic wakeup_en_regwen; + logic [ pwrmgr_reg_pkg::NumWkups-1:0] wakeup_en; + logic [ pwrmgr_reg_pkg::NumWkups-1:0] wakeup_status; + logic wakeup_capture_en; + + logic [pwrmgr_reg_pkg::NumRstReqs-1:0] reset_en; + logic [pwrmgr_reg_pkg::NumRstReqs-1:0] reset_en_q; + logic [pwrmgr_reg_pkg::NumRstReqs-1:0] reset_status; + + logic lowpwr_cfg_wen; + pwrmgr_reg_pkg::pwrmgr_hw2reg_wake_info_reg_t wake_info; + + // Internal DUT signals. +`ifndef PATH_TO_DUT + `define PATH_TO_DUT tb.dut +`endif + + // Slow fsm state. + pwrmgr_pkg::slow_pwr_state_e slow_state; + always_comb slow_state = `PATH_TO_DUT.u_slow_fsm.state_q; + + // Fast fsm state. + pwrmgr_pkg::fast_pwr_state_e fast_state; + always_comb fast_state = `PATH_TO_DUT.u_fsm.state_q; + + // cfg regwen + always_comb lowpwr_cfg_wen = `PATH_TO_DUT.lowpwr_cfg_wen; + + // reset status + always_comb reset_status = {`PATH_TO_DUT.u_reg.reset_status_val_1_qs, + `PATH_TO_DUT.u_reg.reset_status_val_0_qs}; + always_comb reset_en_q = {`PATH_TO_DUT.u_reg.reset_en_en_1_qs, + `PATH_TO_DUT.u_reg.reset_en_en_0_qs}; + always_comb + wakeup_en = { + `PATH_TO_DUT.reg2hw.wakeup_en[5].q, + `PATH_TO_DUT.reg2hw.wakeup_en[4].q, + `PATH_TO_DUT.reg2hw.wakeup_en[3].q, + `PATH_TO_DUT.reg2hw.wakeup_en[2].q, + `PATH_TO_DUT.reg2hw.wakeup_en[1].q, + `PATH_TO_DUT.reg2hw.wakeup_en[0].q + }; + + // Wakeup_status ro CSR. + always_comb + wakeup_status = { + `PATH_TO_DUT.hw2reg.wake_status[5].d, + `PATH_TO_DUT.hw2reg.wake_status[4].d, + `PATH_TO_DUT.hw2reg.wake_status[3].d, + `PATH_TO_DUT.hw2reg.wake_status[2].d, + `PATH_TO_DUT.hw2reg.wake_status[1].d, + `PATH_TO_DUT.hw2reg.wake_status[0].d + }; + + always_comb wakeup_capture_en = !`PATH_TO_DUT.u_reg.wake_info_capture_dis_qs; + always_comb wake_info = `PATH_TO_DUT.i_wake_info.info_o; + + logic intr_enable; + always_comb intr_enable = `PATH_TO_DUT.reg2hw.intr_enable.q; + + logic intr_status; + always_comb intr_status = `PATH_TO_DUT.reg2hw.intr_state.q; + + // This is only used to determine if an interrupt will be set in case of a reset while in + // low power. tryIt is very hard to perdict if the reset or a wakeup happen first, so this + // signal is used to help instead. + pwrmgr_pkg::pwrup_cause_e pwrup_cause; + always_comb pwrup_cause = `PATH_TO_DUT.slow_pwrup_cause; + + // Used to disable assertions once with the first power glitch. + bit internal_assertion_disabled; + + function automatic void update_ast_main_pok(logic value); + pwr_ast_rsp.main_pok = value; + endfunction + + function automatic void update_otp_done(logic value); + pwr_otp_rsp.otp_done = value; + endfunction + + function automatic void update_otp_idle(logic value); + pwr_otp_rsp.otp_idle = value; + endfunction + + function automatic void update_lc_done(logic value); + pwr_lc_rsp.lc_done = value; + endfunction + + function automatic void update_lc_idle(logic value); + pwr_lc_rsp.lc_idle = value; + endfunction + + function automatic void update_flash_idle(logic value); + pwr_flash.flash_idle = value; + endfunction + + function automatic void update_cpu_sleeping(logic value); + pwr_cpu.core_sleeping = value; + endfunction + + function automatic void update_wakeups(logic [pwrmgr_reg_pkg::NumWkups-1:0] wakeups); + wakeups_i = wakeups; + endfunction + + function automatic void update_resets(logic [pwrmgr_reg_pkg::NumRstReqs-1:0] resets); + rstreqs_i = resets; + endfunction + + function automatic void update_reset_en( + logic [pwrmgr_reg_pkg::NumRstReqs-1:0] reset_en_value); + reset_en = reset_en_value; + endfunction + + function automatic void update_sw_rst_req(prim_mubi_pkg::mubi4_t value); + sw_rst_req_i = value; + endfunction + + // Sends a main power glitch and disables a design assertion that trips for power glitches. + task automatic glitch_power_reset(); + rst_main_n = 1'b0; + if (!internal_assertion_disabled) begin + internal_assertion_disabled = 1'b1; + `uvm_info("pwrmgr_if", "disabling power glitch related SVA", UVM_MEDIUM) + $assertoff(1, tb.dut.u_slow_fsm.IntRstReq_A); + end + repeat (2) @(posedge clk_slow); + rst_main_n = 1'b1; + endtask + + // FIXME Move all these initializations to sequences. + initial begin + // From AST. + pwr_ast_rsp = '{default: '0}; + pwr_rst_rsp = '{default: '0}; + pwr_clk_rsp = '{default: '0}; + pwr_otp_rsp = '{default: '0}; + pwr_lc_rsp = '{default: '0}; + pwr_flash = '{default: '0}; + pwr_cpu = pwrmgr_pkg::PWR_CPU_DEFAULT; + wakeups_i = pwrmgr_pkg::WAKEUPS_DEFAULT; + rstreqs_i = pwrmgr_pkg::RSTREQS_DEFAULT; + sw_rst_req_i = prim_mubi_pkg::MuBi4False; + rom_ctrl = rom_ctrl_pkg::PWRMGR_DATA_DEFAULT; + end + + clocking slow_cb @(posedge clk_slow); + input slow_state; + input pwr_ast_req; + output pwr_ast_rsp; + endclocking + + clocking fast_cb @(posedge clk); + input fast_state; + input pwr_rst_req; + output pwr_rst_rsp; + input pwr_clk_req; + output pwr_clk_rsp; + input pwr_lc_req; + output pwr_lc_rsp; + input pwr_otp_req; + output pwr_otp_rsp; + endclocking +endinterface diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_scoreboard.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_scoreboard.sv new file mode 100644 index 0000000000000..fc08261f2bd7c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_scoreboard.sv @@ -0,0 +1,364 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_scoreboard extends cip_base_scoreboard #( + .CFG_T(pwrmgr_env_cfg), + .RAL_T(pwrmgr_reg_block), + .COV_T(pwrmgr_env_cov) +); + `uvm_component_utils(pwrmgr_scoreboard) + + // local variables + + // TLM agent fifos + + // local queues to hold incoming packets pending comparison + + `uvm_component_new + + function void build_phase(uvm_phase phase); + string common_seq_type; + super.build_phase(phase); + + void'($value$plusargs("run_%0s", common_seq_type)); + if (common_seq_type == "stress_all_with_rand_reset") do_alert_check = 0; + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + cfg.run_phase = phase; + fork + monitor_power_glitch(); + monitor_escalation_timeout(); + reset_cip_helper(); + wakeup_ctrl_coverage_collector(); + wakeup_intr_coverage_collector(); + low_power_coverage_collector(); + reset_coverage_collector(); + rom_coverage_collector(); + join_none + endtask + + task monitor_power_glitch(); + fork + forever + @cfg.pwrmgr_vif.rst_main_n begin + if (cfg.pwrmgr_vif.rst_main_n == 1'b0 && `gmv(ral.control.main_pd_n)) begin + set_exp_alert("fatal_fault", 1, 500); + end + end + join + endtask + + // An escalation timeout is triggered in test sequences by stopping clk_esc_i when the clock is + // meant to be enabled, or by driving rst_esc_ni active when the dut is not expecting it. + task monitor_escalation_timeout(); + fork + forever + @(posedge cfg.esc_clk_rst_vif.clk_gate) begin + if (cfg.pwrmgr_vif.pwr_clk_req.io_ip_clk_en) begin + // A timeout could be triggered if the escalation clock is stopped for too many clk_i + // cycles. The precise threshold is somewhat unpredictable for reasons explained in + // the pwrmgr_escalation_timeout sequence, and the sequence is such that 121 cycles + // works as a threshold to avoid unpredictable stoppages. + `uvm_info(`gfn, "Detected unexpected clk_esc_i stop", UVM_MEDIUM) + fork + begin : isolation_fork + // This fork is so we can wait for a number of cycles with the clock inactive, + // and stop waiting if the escalation clock gate is re-opened. + fork + begin + cfg.clk_rst_vif.wait_clks(121); + if (cfg.esc_clk_rst_vif.clk_gate && cfg.pwrmgr_vif.pwr_ast_req.io_clk_en && + cfg.pwrmgr_vif.pwr_clk_req.io_ip_clk_en) begin + `uvm_info(`gfn, "clk_esc_i has been inactive enough to trigger an alert", + UVM_MEDIUM) + `uvm_info(`gfn, "set_exp_alert from monitor_escalation_timeout clock gated", + UVM_MEDIUM) + set_exp_alert("fatal_fault", 1, 500); + end + end + // This stops the wait if the gate is re-opened. + @(negedge cfg.esc_clk_rst_vif.clk_gate); + join_any + disable fork; + end + join + end + end + forever + @(negedge cfg.esc_clk_rst_vif.o_rst_n) begin + if (cfg.pwrmgr_vif.fetch_en == lc_ctrl_pkg::On) begin + `uvm_info(`gfn, "Detected unexpected rst_esc_ni active", UVM_MEDIUM) + set_exp_alert("fatal_fault", 1, 500); + end + end + join + endtask + + // We need to reset the cip scoreboard, since the alert handler responds + // to lc domain0 resets, yet the pwrmgr's clk_rst_vif is aon. So when a + // reset happens the cip scoreboard needs to be informed, both when reset + // starts and when it ends. + task reset_cip_helper(); + fork + forever + @cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req begin + if (|cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req) begin + // Start of d0 reset request. + `uvm_info(`gfn, "pwrmgr start reset in reset_cip_helper", UVM_MEDIUM) + cfg.reset_asserted(); + end + end + forever + @cfg.pwrmgr_vif.fetch_en begin + if (cfg.pwrmgr_vif.fetch_en == lc_ctrl_pkg::On) begin + // End of d0 reset request. + `uvm_info(`gfn, "pwrmgr end reset in reset_cip_helper", UVM_MEDIUM) + reset_alert_state(); + end + end + join + endtask + + task wakeup_ctrl_coverage_collector(); + forever + @(posedge (|cfg.pwrmgr_vif.wakeups_i)) begin + if (cfg.en_cov) begin + // Allow for synchronization delay. + cfg.slow_clk_rst_vif.wait_clks(2); + foreach (cov.wakeup_ctrl_cg_wrap[i]) begin + cov.wakeup_ctrl_cg_wrap[i].sample(cfg.pwrmgr_vif.wakeup_en[i], + cfg.pwrmgr_vif.wakeup_capture_en, + cfg.pwrmgr_vif.wakeups_i[i]); + end + end + end + endtask + + task wakeup_intr_coverage_collector(); + forever + @(posedge (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone)) begin + if (cfg.en_cov) begin + foreach (cov.wakeup_intr_cg_wrap[i]) begin + cov.wakeup_intr_cg_wrap[i].sample( + cfg.pwrmgr_vif.wakeup_status[i], cfg.pwrmgr_vif.intr_enable, + cfg.pwrmgr_vif.intr_status, cfg.pwrmgr_vif.intr_wakeup); + end + end + end + endtask + + task low_power_coverage_collector(); + forever + @(posedge cfg.pwrmgr_vif.pwr_rst_req.reset_cause == pwrmgr_pkg::LowPwrEntry) begin + if (cfg.en_cov) begin + // At this point pwrmgr is asleep. + cov.control_cg.sample(control_enables, 1'b1); + end + end + endtask + + local task sample_reset_coverage(bit sleep); + cov.hw_reset_0_cg.sample(cfg.pwrmgr_vif.rstreqs_i[0], cfg.pwrmgr_vif.reset_en[0], sleep); + cov.hw_reset_1_cg.sample(cfg.pwrmgr_vif.rstreqs_i[1], cfg.pwrmgr_vif.reset_en[1], sleep); + cov.rstmgr_sw_reset_cg.sample(cfg.pwrmgr_vif.sw_rst_req_i == prim_mubi_pkg::MuBi4True); + cov.main_power_reset_cg.sample( + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx], sleep); + cov.esc_reset_cg.sample(cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetEscIdx], sleep); + `uvm_info(`gfn, $sformatf( + { + "reset_cg sample with hw_resets=%b, hw_resets_en=%b, ", + "esc_rst=%b, main_pwr_rst=%b, sw_rst=%b, sleep=%b" + }, + cfg.pwrmgr_vif.rstreqs_i, + cfg.pwrmgr_vif.reset_en, + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetEscIdx], + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx], + cfg.pwrmgr_vif.sw_rst_req_i == prim_mubi_pkg::MuBi4True, + sleep + ), UVM_MEDIUM) + endtask + + task reset_coverage_collector(); + fork + forever + @(posedge cfg.pwrmgr_vif.pwr_rst_req.reset_cause == pwrmgr_pkg::HwReq) begin + if (cfg.en_cov) begin + sample_reset_coverage(.sleep(1'b0)); + end + end + forever + @(posedge cfg.pwrmgr_vif.slow_state == pwrmgr_pkg::SlowPwrStateLowPower) begin + if (cfg.en_cov) begin + sample_reset_coverage(.sleep(1'b1)); + end + end + join_none + endtask + + task rom_coverage_collector(); + forever + @(cfg.pwrmgr_vif.rom_ctrl or cfg.pwrmgr_vif.lc_hw_debug_en or cfg.pwrmgr_vif.lc_dft_en) begin + if (cfg.en_cov) begin + cov.rom_active_blockers_cg.sample(cfg.pwrmgr_vif.rom_ctrl.done, + cfg.pwrmgr_vif.rom_ctrl.good, cfg.pwrmgr_vif.lc_dft_en, + cfg.pwrmgr_vif.lc_hw_debug_en); + end + end + endtask + + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + uvm_reg csr; + bit do_read_check = ~(cfg.disable_csr_rd_chk); + bit skip_intr_chk = cfg.invalid_st_test; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = (write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = (write && channel == DataChannel); + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + // if incoming access is a write to a valid csr, then make updates right away + if (addr_phase_write) begin + `uvm_info(`gfn, $sformatf("Writing 0x%x to %s", item.a_data, csr.get_full_name()), UVM_MEDIUM) + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // process the csr req + // for write, update local variable and fifo at address phase + // for read, update predication at address phase and compare at data phase + case (csr.get_name()) + // add individual case item for each csr + "intr_state": begin + if (skip_intr_chk) return; + if (data_phase_write) begin + exp_intr &= ~item.a_data; + end else if (data_phase_read) begin + bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value(); + foreach (exp_intr[i]) begin + if (cfg.en_cov) begin + cov.intr_cg.sample(i, intr_en[i], exp_intr[i]); + cov.intr_pins_cg.sample(i, cfg.intr_vif.pins[i]); + end + `DV_CHECK_EQ(item.d_data[i], exp_intr[i], $sformatf("Interrupt bit %0d", i)); + `DV_CHECK_CASE_EQ(cfg.intr_vif.pins[i], (intr_en[i] & exp_intr[i]), $sformatf( + "Interrupt_pin bit %0d", i)); + end + end + // rw1c: write 1 clears, write 0 is no-op. + do_read_check = 1'b0; + end + "intr_enable", "alert_test": begin + // Do nothing + end + "intr_test": begin + if (data_phase_write) begin + bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value(); + exp_intr |= item.a_data; + if (cfg.en_cov) begin + foreach (exp_intr[i]) begin + cov.intr_test_cg.sample(i, item.a_data[i], intr_en[i], exp_intr[i]); + end + end + end + // Write-only, so it can't be read. + do_read_check = 1'b0; + end + "ctrl_cfg_regwen": begin + // Read-only. Hardware clears this bit when going to low power mode, + // and sets it in active mode. + do_read_check = 1'b0; + end + "control": begin + // Only some bits can be checked on reads. Bit 0 is cleared by hardware + // on low power transition or when registering a valid reset. + if (data_phase_write) begin + low_power_hint = get_field_val(ral.control.low_power_hint, item.a_data); + control_enables = '{ + core_clk_en: get_field_val(ral.control.core_clk_en, item.a_data), + io_clk_en: get_field_val(ral.control.io_clk_en, item.a_data), + usb_clk_en_lp: get_field_val(ral.control.usb_clk_en_lp, item.a_data), + usb_clk_en_active: get_field_val(ral.control.usb_clk_en_active, item.a_data), + main_pd_n: get_field_val(ral.control.main_pd_n, item.a_data) + }; + `uvm_info(`gfn, $sformatf("Writing low power hint=%b", low_power_hint), UVM_MEDIUM) + `uvm_info(`gfn, $sformatf("Writing control_enables=%p", control_enables), UVM_MEDIUM) + if (cfg.en_cov) begin + // At this point the processor is not asleep. + cov.control_cg.sample(control_enables, 1'b0); + end + end + end + "cfg_cdc_sync": begin + // rw1c: When written to 1 this bit self-clears when the slow clock domain + // syncs. + do_read_check = 1'b0; + end + "wakeup_en_regwen": begin + end + "wakeup_en": begin + end + "wake_status": begin + // Read-only. + do_read_check = 1'b0; + end + "reset_en_regwen": begin + // rw0c, so writing a 1 is a no-op. + end + "reset_en": begin + if (data_phase_write) begin + cfg.pwrmgr_vif.update_reset_en(item.a_data); + end + end + "reset_status": begin + // Read-only. + do_read_check = 1'b0; + end + "escalate_reset_status": begin + // Read-only. + do_read_check = 1'b0; + end + "wake_info_capture_dis": begin + end + "wake_info": begin + // rw1c: write 1 clears, write 0 is no-op. + do_read_check = 1'b0; + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + `uvm_info(`gfn, $sformatf("Reading 0x%x from %s", item.d_data, csr.get_full_name()), UVM_LOW) + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, $sformatf( + "reg name: %0s", csr.get_full_name())) + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end + endtask + + virtual function void reset(string kind = "HARD"); + super.reset(kind); + // reset local fifos queues and variables + endfunction + + function void check_phase(uvm_phase phase); + super.check_phase(phase); + // post test checks - ensure that all local fifos and queues are empty + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_virtual_sequencer.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_virtual_sequencer.sv new file mode 100644 index 0000000000000..ec7f602fbcb4c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/pwrmgr_virtual_sequencer.sv @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(pwrmgr_env_cfg), + .COV_T(pwrmgr_env_cov) +); + `uvm_component_utils(pwrmgr_virtual_sequencer) + + + `uvm_component_new + +endclass diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_aborted_low_power_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_aborted_low_power_vseq.sv new file mode 100644 index 0000000000000..4c8bb62548ea9 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_aborted_low_power_vseq.sv @@ -0,0 +1,126 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The aborted low power test causes low power transitions to abort for CPU interrupts and nvms not +// idle. It randomly enables wakeups, info capture, and interrupts, and sends wakeups at random +// times, and causes a test failure if they are not aborted. +class pwrmgr_aborted_low_power_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_aborted_low_power_vseq) + + `uvm_object_new + + // If set causes an abort because the CPU gets an interrupt, which shows up as + // pwr_cpu.core_sleeping being low when the fast FSM is in FastPwrStateFallThrough. + rand bit cpu_interrupt; + + constraint cpu_interrupt_c { + cpu_interrupt dist { + 1 := 2, + 0 := 6 + }; + } + + rand bit flash_idle; + rand bit lc_idle; + rand bit otp_idle; + + constraint idle_c { + solve cpu_interrupt before flash_idle, lc_idle, otp_idle; + if (!cpu_interrupt) {(flash_idle && lc_idle && otp_idle) == 1'b0;} + } + + constraint wakeups_c {wakeups != 0;} + + constraint wakeup_en_c { + solve wakeups before wakeups_en; + |(wakeups_en & wakeups) == 1'b1; + } + + // Make sure wakeup capture is enabled to check the abort happened. + constraint enable_wakeup_capture_c {disable_wakeup_capture == 1'b0;} + + task body(); + logic [TL_DW-1:0] value; + wakeups_t enabled_wakeups; + wait_for_fast_fsm(FastFsmActive); + + check_wake_status('0); + set_nvms_idle(); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + // Enable wakeups. + enabled_wakeups = wakeups_en & wakeups; + `DV_CHECK(enabled_wakeups, $sformatf( + "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en)) + `uvm_info(`gfn, $sformatf( + "Enabled wakeups=0x%x (wkups=%x wkup_en=%x)", enabled_wakeups, wakeups, wakeups_en + ), UVM_MEDIUM) + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + + `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"), + UVM_MEDIUM) + csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture)); + low_power_hint = 1'b1; + + // Put CPU to sleep even before the control registers are fully written to avoid + // unexpected failures to abort due to delicate timing. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + + fork + begin + update_control_csr(); + `uvm_info(`gfn, $sformatf("After update_control_csr exp_intr=%b", exp_intr), UVM_MEDIUM) + end + begin + // Prepare for an abort ahead of time. + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + // Wait one more cycle for update_control_csr called above to predict the interrupt + // based on the value of cpu_sleeping right after the transition out of active state. + // There is enough time for this since it takes time to disable the clocks. + cfg.clk_rst_vif.wait_clks(1); + if (cpu_interrupt) begin + `uvm_info(`gfn, "Expecting a fall through (0x40)", UVM_MEDIUM) + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + end else begin + `uvm_info(`gfn, $sformatf( + "Expecting an abort (0x80): fi=%b, li=%b, oi=%b", + flash_idle, + lc_idle, + otp_idle + ), UVM_MEDIUM) + set_nvms_idle(flash_idle, lc_idle, otp_idle); + end + end + join + wait_for_fast_fsm(FastFsmActive); + + `uvm_info(`gfn, "Back from sleep attempt", UVM_MEDIUM) + @cfg.clk_rst_vif.cb; + + // No wakeups, but check abort and fall_through. + fork + begin + fast_check_reset_status(0); + end + begin + fast_check_wake_info(.reasons('0), .fall_through(cpu_interrupt), .abort(~cpu_interrupt)); + end + join + + clear_wake_info(); + + // And check interrupt is set. + check_and_clear_interrupt(.expected(1'b1)); + + // Get ready for another round. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + set_nvms_idle(); + cfg.slow_clk_rst_vif.wait_clks(4); + end + `uvm_info(`gfn, "Test done", UVM_MEDIUM) + endtask + +endclass : pwrmgr_aborted_low_power_vseq diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_base_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_base_vseq.sv new file mode 100644 index 0000000000000..9cb21e7db507b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_base_vseq.sv @@ -0,0 +1,843 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_base_vseq extends cip_base_vseq #( + .RAL_T (pwrmgr_reg_block), + .CFG_T (pwrmgr_env_cfg), + .COV_T (pwrmgr_env_cov), + .VIRTUAL_SEQUENCER_T(pwrmgr_virtual_sequencer) +); + `uvm_object_utils(pwrmgr_base_vseq) + + `uvm_object_new + + localparam int ActiveTimeoutInNanoSeconds = 10_000; + localparam int PropagationToSlowTimeoutInNanoSeconds = 15_000; + localparam int FetchEnTimeoutNs = 40_000; + + localparam int MaxCyclesBeforeEnable = 12; + + typedef enum int { + FastFsmActive, + FastFsmInactive + } fast_fsm_activity_e; + + // Random wakeups and resets. + rand wakeups_t wakeups; + rand wakeups_t wakeups_en; + rand resets_t resets; + rand resets_t resets_en; + rand bit power_glitch_reset; + rand bit escalation_reset; + rand bit ndm_reset; + + rand bit en_intr; + + constraint resets_en_c { + solve resets, power_glitch_reset, escalation_reset, ndm_reset before resets_en; + |{resets_en & resets, power_glitch_reset, escalation_reset, ndm_reset} == 1'b1; + } + + rand bit disable_wakeup_capture; + + // Random control enables. + rand control_enables_t control_enables; + + // Random delays. + rand int cycles_before_clks_ok; + rand int cycles_between_clks_ok; + rand int cycles_before_io_status; + rand int cycles_before_main_status; + rand int cycles_before_usb_status; + rand int cycles_before_rst_lc_src; + rand int cycles_before_rst_sys_src; + rand int cycles_before_otp_done; + rand int cycles_before_lc_done; + rand int cycles_before_wakeup; + rand int cycles_before_reset; + + // Slow responder delays. + rand int cycles_before_core_clk_en; + rand int cycles_before_io_clk_en; + rand int cycles_before_usb_clk_en; + rand int cycles_before_main_pok; + + // This tracks the local objection count from these responders. We do not use UVM + // objections because uvm_objection::wait_for(UVM_ALL_DROPPED, this) seems to wait + // for all objections to be dropped, not just those raised by this. + local int fast_objection_count = 0; + local int slow_objection_count = 0; + + constraint cycles_before_clks_ok_c {cycles_before_clks_ok inside {[3 : 10]};} + constraint cycles_between_clks_ok_c {cycles_between_clks_ok inside {[3 : 10]};} + constraint cycles_before_io_status_c {cycles_before_io_status inside {[0 : 4]};} + constraint cycles_before_main_status_c {cycles_before_main_status inside {[0 : 4]};} + constraint cycles_before_usb_status_c {cycles_before_usb_status inside {[0 : 4]};} + constraint cycles_before_rst_lc_src_base_c {cycles_before_rst_lc_src inside {[0 : 4]};} + constraint cycles_before_rst_sys_src_base_c {cycles_before_rst_sys_src inside {[0 : 4]};} + constraint cycles_before_otp_done_base_c {cycles_before_otp_done inside {[0 : 4]};} + constraint cycles_before_lc_done_base_c {cycles_before_lc_done inside {[0 : 4]};} + constraint cycles_before_wakeup_c {cycles_before_wakeup inside {[2 : 6]};} + constraint cycles_before_reset_c {cycles_before_reset inside {[2 : 6]};} + constraint cycles_before_core_clk_en_c { + cycles_before_core_clk_en inside {[1 : MaxCyclesBeforeEnable]}; + } + constraint cycles_before_io_clk_en_c { + cycles_before_io_clk_en inside {[1 : MaxCyclesBeforeEnable - 2]}; + } + constraint cycles_before_usb_clk_en_c { + cycles_before_usb_clk_en inside {[1 : MaxCyclesBeforeEnable]}; + } + constraint cycles_before_main_pok_c {cycles_before_main_pok inside {[2 : MaxCyclesBeforeEnable]};} + + // This is used to trigger a software reset, as per rstmgr's `reset_req` CSR. + prim_mubi_pkg::mubi4_t sw_rst_from_rstmgr = prim_mubi_pkg::MuBi4False; + + bit do_pwrmgr_init = 1'b1; + // This static variable is incremented in each pre_start and decremented in each post_start. + // It is used to start and stop the responders when the parent sequence starts and ends. + local static int sequence_depth = 0; + pwrmgr_mubi_e mubi_mode; + + // This stops randomizing cycles counts that select from a pipeline, since + // changes can lead to missing or unexpected transitions. + task stop_randomizing_cycles(); + cycles_before_core_clk_en.rand_mode(0); + cycles_before_io_clk_en.rand_mode(0); + cycles_before_usb_clk_en.rand_mode(0); + cycles_before_main_pok.rand_mode(0); + endtask + + // Disable exclusions for CONTROL.USB_CLK_EN_ACTIVE and RESET_EN: they are meant for full-chip only. + function void disable_unnecessary_exclusions(); + csr_excl_item csr_excl = ral.get_excl_item(); + `uvm_info(`gfn, "Dealing with exclusions", UVM_MEDIUM) + csr_excl.enable_excl(.obj("pwrmgr_reg_block.control"), .enable(1'b0)); + csr_excl.enable_excl(.obj("pwrmgr_reg_block.reset_en"), .enable(1'b0)); + csr_excl.print_exclusions(UVM_MEDIUM); + endfunction + + virtual task pre_start(); + cfg.pwrmgr_vif.lc_hw_debug_en = lc_ctrl_pkg::Off; + cfg.pwrmgr_vif.lc_dft_en = lc_ctrl_pkg::Off; + mubi_mode = PwrmgrMubiNone; + `DV_GET_ENUM_PLUSARG(pwrmgr_mubi_e, mubi_mode, pwrmgr_mubi_mode) + `uvm_info(`gfn, $sformatf("pwrmgr mubi mode : %s", mubi_mode.name()), UVM_MEDIUM) + + if (do_pwrmgr_init) pwrmgr_init(); + disable_unnecessary_exclusions(); + cfg.slow_clk_rst_vif.wait_for_reset(.wait_negedge(0)); + stop_randomizing_cycles(); + fork + // Deactivate rst_main_n to make sure the slow fsm won't be confused into thinking + // a power glitch occurred, and wait some cycles so testing doesn't start until any + // side-effects are cleared. This confusion can arise if a sequence with random resets + // gets reset while sending a power glitch. + begin + cfg.pwrmgr_vif.rst_main_n = 1'b1; + cfg.slow_clk_rst_vif.wait_clks(7); + end + begin + if (sequence_depth == 0) begin + `uvm_info(`gfn, "Starting responders", UVM_MEDIUM) + slow_responder(); + fast_responder(); + end + ++sequence_depth; + super.pre_start(); + end + join + endtask : pre_start + + task post_apply_reset(string reset_kind = "HARD"); + super.post_apply_reset(reset_kind); + if (reset_kind == "HARD") begin + // Undo any pending resets. + cfg.pwrmgr_vif.rst_main_n = 1'b1; + cfg.pwrmgr_vif.update_resets(0); + end + + `uvm_info(`gfn, "waiting for fast active after applying reset", UVM_MEDIUM) + + // There is tb lock up case + // when reset come while rom_ctrl = {false, false}. + // So we need rom_ctrl driver runs in parallel with + // wait_for_fast_fsm(FastFsmActive) + fork + wait_for_fast_fsm(FastFsmActive); + init_rom_response(); + join + // And drive the cpu not sleeping. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + endtask + + task post_start(); + super.post_start(); + --sequence_depth; + if (sequence_depth == 0) begin + `uvm_info(`gfn, $sformatf( + "Waiting for all objections done with fast=%0d, slow=%0d", + fast_objection_count, + slow_objection_count + ), UVM_MEDIUM) + `DV_WAIT(fast_objection_count == 0 && slow_objection_count == 0) + `uvm_info(`gfn, "all local objections are done", UVM_LOW) + control_assertions(0); + `uvm_info(`gfn, "Stopping responders", UVM_MEDIUM) + disable slow_responder; + disable fast_responder; + end + endtask + + virtual task dut_init(string reset_kind = "HARD"); + super.dut_init(); + endtask + + virtual task dut_shutdown(); + // There are no known checks to perform here. + endtask + + virtual task apply_reset(string kind = "HARD"); + `uvm_info(`gfn, $sformatf("At apply_reset kind='%0s'", kind), UVM_MEDIUM) + fork + super.apply_reset(kind); + if (kind == "HARD") begin + // A short slow clock reset should suffice. + cfg.slow_clk_rst_vif.apply_reset(.reset_width_clks(5)); + end + cfg.esc_clk_rst_vif.apply_reset(); + cfg.lc_clk_rst_vif.apply_reset(); + // Escalation resets are cleared when reset goes active. + clear_escalation_reset(); + clear_ndm_reset(); + join + // And wait until the responders settle with all okay from the AST. + `DV_WAIT( + cfg.pwrmgr_vif.pwr_ast_rsp.main_pok && + cfg.pwrmgr_vif.pwr_ast_rsp.core_clk_val && + cfg.pwrmgr_vif.pwr_ast_rsp.io_clk_val) + `uvm_info(`gfn, $sformatf("Out of apply_reset kind='%0s'", kind), UVM_MEDIUM) + endtask + + virtual task apply_resets_concurrently(int reset_duration_ps = 0); + cfg.slow_clk_rst_vif.drive_rst_pin(0); + cfg.esc_clk_rst_vif.drive_rst_pin(0); + cfg.lc_clk_rst_vif.drive_rst_pin(0); + super.apply_resets_concurrently(cfg.slow_clk_rst_vif.clk_period_ps); + cfg.esc_clk_rst_vif.drive_rst_pin(1); + cfg.lc_clk_rst_vif.drive_rst_pin(1); + cfg.slow_clk_rst_vif.drive_rst_pin(1); + endtask + + // setup basic pwrmgr features + virtual task pwrmgr_init(); + // The fast clock frequency is set by ral. + // The real slow clock rate is 200kHz, but that slows testing down. + // Increasing its frequency improves DV efficiency without compromising quality. + cfg.slow_clk_rst_vif.set_freq_mhz(7); + `uvm_info(`gfn, $sformatf( + "slow clock freq=%fMHz, period=%0dns", + cfg.slow_clk_rst_vif.clk_freq_mhz, + cfg.slow_clk_rst_vif.clk_period_ps + ), UVM_MEDIUM) + cfg.esc_clk_rst_vif.set_freq_mhz(cfg.clk_rst_vif.clk_freq_mhz); + cfg.lc_clk_rst_vif.set_freq_mhz(cfg.clk_rst_vif.clk_freq_mhz); + set_ndmreset_req('0); + control_assertions(0); + endtask + + virtual task setup_interrupt(bit enable); + csr_wr(.ptr(ral.intr_enable.wakeup), .value(enable)); + `uvm_info(`gfn, $sformatf("Wakeup interrupt is %0sabled", enable ? "en" : "dis"), UVM_MEDIUM) + endtask + + // May check intr_state.wakeup CSR against expected, and regardless, it checks that the + // interrupt output matches intr_state && intr_enable. The first check is disabled if + // check_expected is off, which is used when a reset and an interrupt come in close + // temporal proximity. + virtual task check_and_clear_interrupt(bit expected, bit check_expected = 1'b1); + bit enable; + `uvm_info(`gfn, "Checking and clearing interrupt", UVM_MEDIUM) + if (check_expected) begin + csr_rd_check(.ptr(ral.intr_state.wakeup), .compare_value(expected), + .err_msg("interrupt mismatch")); + end else begin + csr_rd(.ptr(ral.intr_state.wakeup), .value(expected)); + end + csr_rd(.ptr(ral.intr_enable.wakeup), .value(enable)); + `DV_CHECK_EQ(cfg.pwrmgr_vif.intr_wakeup, expected && enable) + csr_wr(.ptr(ral.intr_state.wakeup), .value(1'b1)); + endtask + + local function void raise_fast_objection(string label); + ++fast_objection_count; + `uvm_info(`gfn, $sformatf("Raising fast objection to %0d for %0s", fast_objection_count, label), + UVM_HIGH) + endfunction + + local function void drop_fast_objection(string label); + --fast_objection_count; + `uvm_info(`gfn, $sformatf("Dropping fast objection to %0d for %0s", fast_objection_count, label + ), UVM_HIGH) + endfunction + + local function void raise_slow_objection(string label); + ++slow_objection_count; + `uvm_info(`gfn, $sformatf("Raising slow objection to %0d for %0s", slow_objection_count, label), + UVM_MEDIUM) + endfunction + + local function void drop_slow_objection(string label); + --slow_objection_count; + `uvm_info(`gfn, $sformatf("Dropping slow objection to %0d for %0s", slow_objection_count, label + ), UVM_MEDIUM) + endfunction + + virtual function void set_ndmreset_req(logic value); + cfg.pwrmgr_vif.cpu_i.ndmreset_req = value; + endfunction + + // Generates expected responses for the slow fsm. + // - Completes the clock handshake with the ast: when a clk_en output changes, after a few + // cycles the ast is expected to set the corresponding clk_val input to the same value. + // - It is possible changes occur in fast succession, so the side-effect is pipelined. + // Uses macros because VCS flags an error for assignments to automatic variables, + // even if the variable is a ref to an interface variable. + + `define SLOW_DETECT(rsp_name_, req_) \ + forever \ + @req_ begin \ + raise_slow_objection(rsp_name_); \ + `uvm_info(`gfn, $sformatf( \ + "slow_responder: Will drive %0s to %b", rsp_name_, req_), UVM_MEDIUM) \ + end + + `define SLOW_SHIFT_SR(req_, rsp_sr_) \ + forever \ + @cfg.slow_clk_rst_vif.cb begin \ + rsp_sr_ = {rsp_sr_[MaxCyclesBeforeEnable-1:0], req_}; \ + end + + `define SLOW_ASSIGN(rsp_name_, cycles_, rsp_sr_, rsp_) \ + forever \ + @(rsp_sr_[cycles_]) begin \ + `uvm_info(`gfn, $sformatf( \ + "slow_responder: Driving %0s to %b after %0d AON cycles.", \ + rsp_name_, \ + rsp_sr_[cycles_], \ + cycles_ \ + ), UVM_MEDIUM) \ + rsp_ <= rsp_sr_[cycles_]; \ + drop_slow_objection(rsp_name_); \ + end + + task slow_responder(); + logic [MaxCyclesBeforeEnable:0] core_clk_val_sr; + logic [MaxCyclesBeforeEnable:0] io_clk_val_sr; + logic [MaxCyclesBeforeEnable:0] usb_clk_val_sr; + logic [MaxCyclesBeforeEnable:0] main_pd_val_sr; + fork + `SLOW_DETECT("core_clk_val", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.core_clk_en) + `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.core_clk_en, core_clk_val_sr) + `SLOW_ASSIGN("core_clk_val", cycles_before_core_clk_en, core_clk_val_sr, + cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.core_clk_val) + + `SLOW_DETECT("io_clk_val", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.io_clk_en) + `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.io_clk_en, io_clk_val_sr) + // Notice this splits updates due to io_clk_en in two processes: with a single process + // and a wait inside a quick sequence of changes would cause skipping some update, per + // SV scheduling semantics. + forever + @(io_clk_val_sr[cycles_before_io_clk_en]) begin + logic new_value = io_clk_val_sr[cycles_before_io_clk_en]; + `uvm_info(`gfn, $sformatf( + "slow_responder: Driving %0s to %b after %0d AON cycles.", + "io_clk_val", + new_value, + cycles_before_io_clk_en + ), UVM_MEDIUM) + if (new_value == 1) begin + cfg.clk_rst_vif.start_clk(); + cfg.lc_clk_rst_vif.start_clk(); + cfg.esc_clk_rst_vif.start_clk(); + end else begin + cfg.clk_rst_vif.stop_clk(); + cfg.lc_clk_rst_vif.stop_clk(); + cfg.esc_clk_rst_vif.stop_clk(); + end + end + forever + @(io_clk_val_sr[cycles_before_io_clk_en+2]) begin + logic new_value = io_clk_val_sr[cycles_before_io_clk_en+2]; + cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.io_clk_val <= new_value; + drop_slow_objection("io_clk_val"); + end + + `SLOW_DETECT("usb_clk_val", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.usb_clk_en) + `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.usb_clk_en, usb_clk_val_sr) + `SLOW_ASSIGN("usb_clk_val", cycles_before_usb_clk_en, usb_clk_val_sr, + cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.usb_clk_val) + + `SLOW_DETECT("main_pok", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.main_pd_n) + `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.main_pd_n, main_pd_val_sr) + `SLOW_ASSIGN("main_pok", cycles_before_main_pok, main_pd_val_sr, + cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.main_pok) + join_none + endtask : slow_responder + `undef SLOW_DETECT + `undef SLOW_SHIFT_SR + `undef SLOW_ASSIGN + + // Generates expected responses for the fast fsm. + // - Completes the reset handshake with the rstmgr for lc and sys resets: soon after a + // reset is requested the corresponding active low reset src must go low. + // - Completes the handshake with the clkmgr for io, main, and usb clocks: + // each status input needs to track the corresponding ip_clk_en output. + // - Completes handshake with lc and otp: *_done needs to track *_init. + // Macros for the same reason as the slow responder. + + `define FAST_RESPONSE_ACTION(rsp_name, rsp, req, cycles) \ + `uvm_info(`gfn, $sformatf( \ + "fast_responder %s: Will drive %0s to %b in %0d fast clock cycles", \ + rsp_name, rsp_name, req, cycles), UVM_HIGH) \ + cfg.clk_rst_vif.wait_clks(cycles); \ + rsp <= req; \ + `uvm_info(`gfn, $sformatf("fast_responder %s: Driving %0s to %b", rsp_name, rsp_name, req), UVM_HIGH) \ + + + task fast_responder(); + fork + forever + @cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req begin + `uvm_info(`gfn, $sformatf( + "fast responder got rst_lc_req change to 0x%x", + cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req + ), UVM_HIGH) + raise_fast_objection("rst_lc_src_n"); + `FAST_RESPONSE_ACTION("rst_lc_src_n", cfg.pwrmgr_vif.fast_cb.pwr_rst_rsp.rst_lc_src_n, + ~cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req, + cycles_before_rst_lc_src) + if (cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req[1] == 1'b0) begin + // Wait for the rst_lc_src_n[1] input to go inactive. + if (cfg.pwrmgr_vif.pwr_rst_rsp.rst_lc_src_n[1] != 1'b1) + @(posedge cfg.pwrmgr_vif.pwr_rst_rsp.rst_lc_src_n[1]); + cfg.esc_clk_rst_vif.drive_rst_pin(1); + cfg.lc_clk_rst_vif.drive_rst_pin(1); + end else begin + // And clear all reset requests when rst_lc_src_n[1] goes active, because when + // peripherals are reset they should drop their reset requests. + if (cfg.pwrmgr_vif.pwr_rst_rsp.rst_lc_src_n[1] != 1'b0) + @(negedge cfg.pwrmgr_vif.pwr_rst_rsp.rst_lc_src_n[1]); + cfg.esc_clk_rst_vif.drive_rst_pin(0); + cfg.lc_clk_rst_vif.drive_rst_pin(0); + clear_escalation_reset(); + clear_ndm_reset(); + cfg.pwrmgr_vif.update_resets('0); + cfg.pwrmgr_vif.update_sw_rst_req(prim_mubi_pkg::MuBi4False); + `uvm_info(`gfn, "Clearing resets", UVM_MEDIUM) + end + drop_fast_objection("rst_lc_src_n"); + `uvm_info(`gfn, "fast responder done with rst_lc_req change", UVM_HIGH) + end + forever + @cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_sys_req begin + raise_fast_objection("rst_sys_src_n"); + `FAST_RESPONSE_ACTION("rst_sys_src_n", cfg.pwrmgr_vif.fast_cb.pwr_rst_rsp.rst_sys_src_n, + ~cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_sys_req, + cycles_before_rst_sys_src) + drop_fast_objection("rst_sys_src_n"); + end + + forever + @cfg.pwrmgr_vif.fast_cb.pwr_clk_req.io_ip_clk_en begin + logic new_value = cfg.pwrmgr_vif.fast_cb.pwr_clk_req.io_ip_clk_en; + raise_fast_objection("io_status"); + `uvm_info(`gfn, $sformatf( + "fast_responder: Will drive %0s to %b in %0d fast clock cycles", + "io_status", + new_value, + cycles_before_io_status + ), UVM_HIGH) + cfg.clk_rst_vif.wait_clks(cycles_before_io_status); + if (new_value) cfg.esc_clk_rst_vif.start_clk(); + else cfg.esc_clk_rst_vif.stop_clk(); + cfg.clk_rst_vif.wait_clks(2); + cfg.pwrmgr_vif.fast_cb.pwr_clk_rsp.io_status <= new_value; + `uvm_info(`gfn, $sformatf( + "fast_responder: Driving %0s to %b", + "io_status", + cfg.pwrmgr_vif.fast_cb.pwr_clk_req.io_ip_clk_en + ), UVM_HIGH) + drop_fast_objection("io_status"); + end + + forever + @cfg.pwrmgr_vif.fast_cb.pwr_clk_req.main_ip_clk_en begin + raise_fast_objection("main_status"); + `FAST_RESPONSE_ACTION("main_status", cfg.pwrmgr_vif.fast_cb.pwr_clk_rsp.main_status, + cfg.pwrmgr_vif.fast_cb.pwr_clk_req.main_ip_clk_en, + cycles_before_main_status) + drop_fast_objection("main_status"); + end + forever + @cfg.pwrmgr_vif.fast_cb.pwr_clk_req.usb_ip_clk_en begin + raise_fast_objection("usb_status"); + `FAST_RESPONSE_ACTION("usb_status", cfg.pwrmgr_vif.fast_cb.pwr_clk_rsp.usb_status, + cfg.pwrmgr_vif.fast_cb.pwr_clk_req.usb_ip_clk_en, + cycles_before_usb_status) + drop_fast_objection("usb_status"); + end + forever + @cfg.pwrmgr_vif.fast_cb.pwr_lc_req.lc_init begin + raise_fast_objection("lc_done"); + `FAST_RESPONSE_ACTION("lc_done", cfg.pwrmgr_vif.fast_cb.pwr_lc_rsp.lc_done, + cfg.pwrmgr_vif.fast_cb.pwr_lc_req.lc_init, cycles_before_lc_done) + drop_fast_objection("lc_done"); + end + forever + @cfg.pwrmgr_vif.fast_cb.pwr_otp_req.otp_init begin + raise_fast_objection("otp_done"); + `FAST_RESPONSE_ACTION("otp_done", cfg.pwrmgr_vif.fast_cb.pwr_otp_rsp.otp_done, + cfg.pwrmgr_vif.fast_cb.pwr_otp_req.otp_init, cycles_before_otp_done) + drop_fast_objection("otp_done"); + end + join_none + endtask : fast_responder + `undef FAST_RESPONSE_ACTION + + function void control_assertions(bit enable); + `uvm_info(`gfn, $sformatf("%0sabling assertions", enable ? "En" : "Dis"), UVM_MEDIUM) + cfg.pwrmgr_clock_enables_sva_vif.disable_sva = !enable; + cfg.pwrmgr_rstmgr_sva_vif.disable_sva = !enable; + endfunction + + local task wait_for_fall_through(); + `DV_WAIT(!cfg.pwrmgr_vif.pwr_cpu.core_sleeping) + exp_intr = 1'b1; + `uvm_info(`gfn, "wait_for_fall_through succeeds", UVM_MEDIUM) + endtask + + local task wait_for_abort(); + `DV_WAIT( + !cfg.pwrmgr_vif.pwr_flash.flash_idle || !cfg.pwrmgr_vif.pwr_otp_rsp.otp_idle || + !cfg.pwrmgr_vif.pwr_lc_rsp.lc_idle) + exp_intr = 1'b1; + `uvm_info(`gfn, "wait_for_abort succeeds", UVM_MEDIUM) + endtask + + local task wait_for_low_power_transition(); + wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry); + exp_wakeup_reasons = wakeups & wakeups_en; + exp_intr = 1'b1; + `uvm_info(`gfn, "Setting expected interrupt", UVM_MEDIUM) + endtask + + task process_low_power_hint(); + `uvm_info(`gfn, "Entering process_low_power_hint", UVM_MEDIUM) + // Timeout if the low power transition waits too long for WFI. + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + `uvm_info(`gfn, "In process_low_power_hint pre forks", UVM_MEDIUM) + // Clear expectations. + exp_wakeup_reasons = 1'b0; + fork + begin : isolation_fork + fork + wait_for_fall_through(); + wait_for_abort(); + wait_for_low_power_transition(); + join_any + disable fork; + end + join + // At this point we know the low power transition went through or was aborted. + // If it went through, determine if the transition to active state is for a reset, and + // cancel the expected interrupt. + if (exp_wakeup_reasons) begin + `DV_WAIT(cfg.pwrmgr_vif.slow_state == pwrmgr_pkg::SlowPwrStateMainPowerOn) + if (cfg.pwrmgr_vif.pwrup_cause == pwrmgr_pkg::Reset) begin + `uvm_info(`gfn, "Cancelling expected interrupt", UVM_MEDIUM) + exp_intr = 1'b0; + end + end + endtask + + // Updates control CSR. + task update_control_csr(); + fork + begin + ral.control.core_clk_en.set(control_enables.core_clk_en); + ral.control.io_clk_en.set(control_enables.io_clk_en); + ral.control.usb_clk_en_lp.set(control_enables.usb_clk_en_lp); + ral.control.usb_clk_en_active.set(control_enables.usb_clk_en_active); + ral.control.main_pd_n.set(control_enables.main_pd_n); + ral.control.low_power_hint.set(low_power_hint); + // Disable assertions when main power is down. + control_assertions(control_enables.main_pd_n); + `uvm_info(`gfn, $sformatf( + "Setting control CSR to 0x%x, enables=%p, low_power_hint=%b", + ral.control.get(), + control_enables, + low_power_hint + ), UVM_MEDIUM) + csr_update(.csr(ral.control)); + wait_for_csr_to_propagate_to_slow_domain(); + end + // Predict the effect of the potential low power transition. + if (low_power_hint) process_low_power_hint(); + join_any + endtask : update_control_csr + + // This enables the fast fsm to transition to low power when all nvms are idle after the + // transition is enabled by software and cpu WFI. When not all are idle the transition is + // aborted. + virtual task set_nvms_idle(logic flash_idle = 1'b1, logic lc_idle = 1'b1, logic otp_idle = 1'b1); + `uvm_info(`gfn, $sformatf( + "Setting nvms idle: flash=%b, lc=%b, otp=%b", flash_idle, lc_idle, otp_idle), + UVM_MEDIUM) + cfg.pwrmgr_vif.update_flash_idle(flash_idle); + cfg.pwrmgr_vif.update_lc_idle(lc_idle); + cfg.pwrmgr_vif.update_otp_idle(otp_idle); + endtask + + // Waits for the fast fsm becoming active or inactive, indicated by the + // fetch_en output going On or Off respectively. + task wait_for_fast_fsm(fast_fsm_activity_e activity = FastFsmActive); + lc_ctrl_pkg::lc_tx_t fetch_en = activity == FastFsmActive ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off; + `uvm_info(`gfn, $sformatf("starting wait for pwrmgr %s", activity.name), UVM_MEDIUM) + `DV_SPINWAIT(wait (cfg.pwrmgr_vif.fetch_en == fetch_en);, + "timeout waiting for pwrmgr fast fsm target activity", FetchEnTimeoutNs) + `uvm_info(`gfn, $sformatf("pwrmgr reached %s", activity.name), UVM_MEDIUM) + endtask + + // Waits for the lc_rst output going inactive, which would complete a device reset. + // This should not be called for shallow sleep, since there is no lc_rst request. + task wait_for_lc_rst_release(); + `uvm_info(`gfn, "starting wait for release of lc_rst for non-aon domain", UVM_MEDIUM) + `DV_WAIT(cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req[1] == 1'b1, + "timeout waiting for lc_rst[1] to be active", FetchEnTimeoutNs) + `DV_WAIT(cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req[1] == 1'b0, + "timeout waiting for lc_rst[1] to be inactive", FetchEnTimeoutNs) + `uvm_info(`gfn, "pwrmgr fast released lc_req[1]", UVM_MEDIUM) + endtask + + task wait_for_reset_cause(pwrmgr_pkg::reset_cause_e cause); + `DV_WAIT(cfg.pwrmgr_vif.pwr_rst_req.reset_cause == cause) + `uvm_info(`gfn, $sformatf("Observed reset cause_match %s (0x%x)", cause.name, cause), + UVM_MEDIUM) + endtask + + virtual task wait_for_csr_to_propagate_to_slow_domain(); + csr_wr(.ptr(ral.cfg_cdc_sync), .value(1'b1)); + csr_spinwait(.ptr(ral.cfg_cdc_sync), .exp_data(1'b0), + .timeout_ns(PropagationToSlowTimeoutInNanoSeconds)); + `uvm_info(`gfn, "CSR updates made it to the slow domain", UVM_MEDIUM) + endtask + + // Checks the reset_status CSR matches expectations. + task check_reset_status(resets_t expected_resets); + csr_rd_check(.ptr(ral.reset_status[0]), .compare_value(expected_resets), + .err_msg("reset_status")); + endtask + + task fast_check_reset_status(resets_t expected_resets); + logic [pwrmgr_reg_pkg::NumRstReqs-1:0] init_reset_status; + `uvm_info(`gfn, "init reset status", UVM_MEDIUM); + // Wait to get out of low power state, since all reset status should have settled. + if (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateLowPower) begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateLowPower);, + "fast state out of low power for reset timeout", 15_000) + end + + init_reset_status = cfg.pwrmgr_vif.reset_status; + if (expected_resets == init_reset_status) begin + // This is a success, so nothing more to do. + return; + end else begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.reset_status != init_reset_status);, $sformatf( + "reset_status wait timeout exp:%x init:%x", expected_resets, init_reset_status), + 15_000) + // The various bits of reset_status could have different sync delays, wait some more. + cfg.clk_rst_vif.wait_clks(2); + `DV_CHECK_EQ(cfg.pwrmgr_vif.reset_status, expected_resets) + end + endtask + + // Checks the wake_status CSR matches expectations. + task check_wake_status(wakeups_t expected_wakeups); + csr_rd_check(.ptr(ral.wake_status[0]), .compare_value(expected_wakeups), + .err_msg("wake_status")); + endtask + + // Checks that wake_status meets expectations. Notice different bits of wake_status can + // be updated at different times, according to their arrival order. Also, whenever reset + // goes active this comparison stops. + task fast_check_wake_status(wakeups_t expected_wakeups); + logic [pwrmgr_reg_pkg::NumWkups-1:0] init_wakeup_status; + `uvm_info(`gfn, "init wakeup", UVM_MEDIUM); + init_wakeup_status = cfg.pwrmgr_vif.wakeup_status; + + // Wait to get out of low power state, since all wake status should have settled + if (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateLowPower) begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateLowPower);, + "fast state out of low power for wakeup timeout", 15_000) + end + + if (expected_wakeups == init_wakeup_status) begin + // This is a success, so nothing more to do. + return; + end else begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.wakeup_status != init_wakeup_status);, $sformatf( + "wakeup_status wait timeout exp:%x init:%x", expected_wakeups, init_wakeup_status + ), 15_000) + // The various bits of wakeup_status could have arrived at different time because they are + // triggered outside pwrmgr, so wait a couple more cycles until there is a match or there + // is a reset. + repeat (2) begin + if (cfg.pwrmgr_vif.wakeup_status == expected_wakeups || !cfg.clk_rst_vif.rst_n) return; + cfg.clk_rst_vif.wait_clks(1); + end + `DV_CHECK_EQ(cfg.pwrmgr_vif.wakeup_status, expected_wakeups) + end + endtask + + task fast_check_wake_info(wakeups_t reasons, wakeups_t prior_reasons = '0, bit fall_through, + bit prior_fall_through = '0, bit abort, bit prior_abort = '0); + pwrmgr_reg_pkg::pwrmgr_hw2reg_wake_info_reg_t initial_value, exp_value; + initial_value = cfg.pwrmgr_vif.wake_info; + + if (disable_wakeup_capture) begin + exp_value.reasons = prior_reasons; + exp_value.fall_through = prior_fall_through; + exp_value.abort = prior_abort; + end else begin + exp_value.reasons = (reasons | prior_reasons); + exp_value.fall_through = (fall_through | prior_fall_through); + exp_value.abort = (abort | prior_abort); + end + if (exp_value != initial_value) begin + // The various bits of wake_info could have different sync delays, so wait some more. + cfg.clk_rst_vif.wait_clks(1); + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.wake_info == exp_value);, + $sformatf("wake info wait timeout exp:%p actual:%p", exp_value, + cfg.pwrmgr_vif.wake_info), + 15_000) + end + endtask : fast_check_wake_info + + // Checks the wake_info CSR matches expectations depending on capture disable. + // The per-field "prior_" arguments support cases where the wake_info register was not + // cleared and may contain residual values. + task check_wake_info(wakeups_t reasons, wakeups_t prior_reasons = '0, bit fall_through, + bit prior_fall_through = '0, bit abort, bit prior_abort = '0); + if (disable_wakeup_capture) begin + csr_rd_check(.ptr(ral.wake_info.reasons), .compare_value(prior_reasons), + .err_msg("With capture disabled")); + csr_rd_check(.ptr(ral.wake_info.fall_through), .compare_value(prior_fall_through), + .err_msg("With capture disabled")); + csr_rd_check(.ptr(ral.wake_info.abort), .compare_value(prior_abort), + .err_msg("With capture disabled")); + end else begin + csr_rd_check(.ptr(ral.wake_info.reasons), .compare_value(reasons | prior_reasons), + .err_msg("With capture enabled")); + csr_rd_check(.ptr(ral.wake_info.fall_through), + .compare_value(fall_through | prior_fall_through), + .err_msg("With capture enabled")); + csr_rd_check(.ptr(ral.wake_info.abort), .compare_value(abort | prior_abort), + .err_msg("With capture enabled")); + end + endtask : check_wake_info + + task clear_wake_info(); + // To clear wake_info, capture must be disabled. + csr_wr(.ptr(ral.wake_info_capture_dis), .value(1'b1)); + csr_wr(.ptr(ral.wake_info), .value('1)); + endtask + + function void send_escalation_reset(); + `uvm_info(`gfn, "Sending escalation reset", UVM_MEDIUM) + cfg.m_esc_agent_cfg.vif.sender_cb.esc_tx_int <= 2'b10; + endfunction + + function void clear_escalation_reset(); + `uvm_info(`gfn, "Clearing escalation reset", UVM_MEDIUM) + cfg.m_esc_agent_cfg.vif.sender_cb.esc_tx_int <= 2'b01; + endfunction + + function void send_ndm_reset(); + `uvm_info(`gfn, "Sending ndm reset", UVM_MEDIUM) + cfg.pwrmgr_vif.cpu_i.ndmreset_req = 1'b1; + endfunction + + function void clear_ndm_reset(); + `uvm_info(`gfn, "Clearing ndm reset", UVM_MEDIUM) + cfg.pwrmgr_vif.cpu_i.ndmreset_req = 1'b0; + endfunction + + task send_power_glitch(); + // Create glitch by 'glitch_power_reset'. An outgoing alert is only possible + // when main power is up. + if (control_enables.main_pd_n) expect_fatal_alerts = 1; + else expect_fatal_alerts = 0; + `uvm_info(`gfn, $sformatf( + "Sending power glitch, expecting %0s alert", expect_fatal_alerts ? "an" : "no"), + UVM_MEDIUM) + cfg.pwrmgr_vif.glitch_power_reset(); + endtask + + // bad_bits = {done, good} + task add_rom_rsp_noise(); + bit [MUBI4W*2-1:0] bad_bits; + int delay; + + repeat (10) begin + delay = $urandom_range(5, 10); + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(bad_bits, + bad_bits[MUBI4W*2-1:MUBI4W] != prim_mubi_pkg::MuBi4True; + bad_bits[MUBI4W*2-1:MUBI4W] != prim_mubi_pkg::MuBi4False; + bad_bits[MUBI4W-1:0] != prim_mubi_pkg::MuBi4False; + bad_bits[MUBI4W-1:0] != prim_mubi_pkg::MuBi4True;) + `uvm_info(`gfn, $sformatf("add_rom_rsp_noise to 0x%x", bad_bits), UVM_HIGH) + cfg.pwrmgr_vif.rom_ctrl = bad_bits; + #(delay * 10ns); + end + endtask : add_rom_rsp_noise + + // Drive rom_ctrl at post reset stage + virtual task init_rom_response(); + if (cfg.pwrmgr_vif.rom_ctrl.done != prim_mubi_pkg::MuBi4True) begin + cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val( + .t_weight(1), .f_weight(1), .other_weight(1) + ); + cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val( + .t_weight(0), .f_weight(1), .other_weight(1) + ); + `DV_WAIT(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone) + cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val( + .t_weight(1), .f_weight(1), .other_weight(1) + ); + cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val( + .t_weight(0), .f_weight(1), .other_weight(1) + ); + cfg.slow_clk_rst_vif.wait_clks(10); + cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val( + .t_weight(1), .f_weight(1), .other_weight(1) + ); + cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val( + .t_weight(0), .f_weight(1), .other_weight(1) + ); + cfg.slow_clk_rst_vif.wait_clks(5); + cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val( + .t_weight(1), .f_weight(1), .other_weight(1) + ); + cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val( + .t_weight(0), .f_weight(1), .other_weight(1) + ); + cfg.slow_clk_rst_vif.wait_clks(5); + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True; + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True; + end + `uvm_info(`gfn, "Set rom response to MuBi4True", UVM_MEDIUM) + endtask + +endclass : pwrmgr_base_vseq diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_common_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_common_vseq.sv new file mode 100644 index 0000000000000..e3e131efee28e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_common_vseq.sv @@ -0,0 +1,113 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_common_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_common_vseq) + + constraint num_trans_c {num_trans inside {[1 : 2]};} + `uvm_object_new + + parameter int STATE_TRANSITION_NS = 50000; + + virtual task pre_start(); + csr_excl_item csr_excl = ral.get_excl_item(); + super.pre_start(); + // In pwrmgr, random reset event can be regarded as power glitch in tb. + // Since glitch is marked as fatal and creates alert after PR#12072, + // exclude pwrmgr_reg_block.fault_status from the random reset tests + // to avoid spurious test failure. + if (common_seq_type inside {"csr_mem_rw_with_rand_reset", "stress_all_with_rand_reset"}) begin + csr_excl.add_excl("pwrmgr_reg_block.fault_status", CsrExclCheck); + expect_fatal_alerts = 1; + end + endtask + + virtual task body(); + run_common_vseq_wrapper(num_trans); + `uvm_info(`gfn, "Done with body", UVM_HIGH) + endtask : body + + task rand_reset_eor_clean_up(); + // clear wakeup at the beginning + cfg.pwrmgr_vif.update_wakeups('0); + cfg.clk_rst_vif.wait_clks(2); + + // clear interrupt + csr_wr(.ptr(ral.intr_state), .value(1)); + endtask : rand_reset_eor_clean_up + + // pwrmgr has three alert events + // REG_INTG_ERR, ESC_TIMEOUT and MAIN_PD_GLITCH + // all others will trigger only reset. + // So disable wait_alert by skipping super.check_sec_cm_fi_resp() + virtual task check_sec_cm_fi_resp(sec_cm_base_if_proxy if_proxy); + string slow_st_to, fast_st_to, msg; + // to avoid 100 column cut off + slow_st_to = { + "slow state local esc chk timeout:", + "fast_state %s, pwr_ast_req.pwr_clamp %0d, pwr_ast_req.main_pd_n %0d" + }; + fast_st_to = { + "fast state local esc chk timeout:", + "pwr_rst_req.rst_lc_req %0d, pwr_rst_req.rst_sys_req %0d, pwr_clk_req %0d" + }; + + `uvm_info(`gfn, $sformatf("sec_cm_type %s", if_proxy.sec_cm_type.name), UVM_MEDIUM) + + case (if_proxy.sec_cm_type) + SecCmPrimSparseFsmFlop: begin + // if slow state is unknown, + // wait for + // fast_state == FastPwrStateInvalid + // tb.dut.pwr_ast_o.pwr_clamp == 1 + // tb.dut.pwr_ast_o.main_pd_n == 0 + // + // if fast state is unknown, + // wait for + // tb.dut.pwr_rst_o.rst_lc_req == 2'b11 + // tb.dut.pwr_rst_o.rst_sys_req == 2'b11 + // tb.dut.pwr_clk_o == 3'b0 + if (!uvm_re_match("*.u_slow_fsm.*", if_proxy.path)) begin + `uvm_info(`gfn, "detect unknown slow state", UVM_MEDIUM) + msg = $sformatf( + slow_st_to, + cfg.pwrmgr_vif.fast_state.name, + cfg.pwrmgr_vif.pwr_ast_req.pwr_clamp, + cfg.pwrmgr_vif.pwr_ast_req.main_pd_n + ); + + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateInvalid && + cfg.pwrmgr_vif.pwr_ast_req.pwr_clamp == 1 && + cfg.pwrmgr_vif.pwr_ast_rsp.main_pok == 0);, msg, STATE_TRANSITION_NS) + end + if (!uvm_re_match("*.u_fsm.*", if_proxy.path)) begin + `uvm_info(`gfn, "detect unknown fast state", UVM_MEDIUM) + msg = $sformatf( + fast_st_to, + cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req, + cfg.pwrmgr_vif.pwr_rst_req.rst_sys_req, + cfg.pwrmgr_vif.pwr_clk_req + ); + + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req == 2'b11 && + cfg.pwrmgr_vif.pwr_rst_req.rst_sys_req == 2'b11 && + cfg.pwrmgr_vif.pwr_clk_req == 3'h0);, msg, 5000) + end + end + SecCmPrimCount: begin + // wait for fast state to be FastPwrStateResetPrep + // before assert reset + `uvm_info(`gfn, "check rx_clk local esc", UVM_MEDIUM) + msg = $sformatf( + "rx clk loc esc chk timeout : fast_state %s", cfg.pwrmgr_vif.fast_state.name + ); + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateResetPrep);, msg, + STATE_TRANSITION_NS) + end + default: `uvm_fatal(`gfn, $sformatf("unexpected sec_cm_type %s", if_proxy.sec_cm_type.name)) + endcase // case (if_proxy.sec_cm_type) + // This makes sure errors are not injected too close together to avoid confusion. + cfg.slow_clk_rst_vif.wait_clks(10); + endtask : check_sec_cm_fi_resp +endclass diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv new file mode 100644 index 0000000000000..0026eaf41a40b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv @@ -0,0 +1,130 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Test multiple resets with setting lc_* inputs with random value. +class pwrmgr_disable_rom_integrity_check_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_disable_rom_integrity_check_vseq) + `uvm_object_new + + rand bit release_by_good; + + constraint wakeups_c {wakeups == 0;} + constraint wakeups_en_c {wakeups_en == 0;} + + function void post_randomize(); + sw_rst_from_rstmgr = get_rand_mubi4_val(.t_weight(8), .f_weight(4), .other_weight(4)); + super.post_randomize(); + endfunction + + local task detect_block(output bit blocked); + blocked = 1; + repeat (20) begin + @cfg.slow_clk_rst_vif.cb; + if (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateActive) begin + blocked = 0; + break; + end + end + endtask + + task body(); + resets_t enabled_resets; + wait_for_fast_fsm(FastFsmActive); + check_reset_status('0); + + for (int i = 0; i < 5; ++i) begin + `uvm_info(`gfn, $sformatf("Starting new round %0d", i), UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + // set lc ctrl input to random value + cfg.pwrmgr_vif.lc_hw_debug_en = get_rand_lc_tx_val( + .t_weight(1), .f_weight(3), .other_weight(1) + ); + cfg.pwrmgr_vif.lc_dft_en = get_rand_lc_tx_val(.t_weight(1), .f_weight(3), .other_weight(1)); + cfg.pwrmgr_vif.rom_ctrl.done = get_rand_mubi4_val( + .t_weight(1), .f_weight(3), .other_weight(1)); + cfg.pwrmgr_vif.rom_ctrl.good = get_rand_mubi4_val( + .t_weight(1), .f_weight(3), .other_weight(1)); + + `uvm_info(`gfn, $sformatf( + "Set done 0x%x, good 0x%x", cfg.pwrmgr_vif.rom_ctrl.done, + cfg.pwrmgr_vif.rom_ctrl.good), UVM_MEDIUM) + + enabled_resets = resets_en & resets; + `uvm_info(`gfn, $sformatf( + "Enabled resets=0x%x, power_reset=%b, escalation=%b, sw_reset=%b, ndm_reset=%b", + enabled_resets, + power_glitch_reset, + escalation_reset, + sw_rst_from_rstmgr == prim_mubi_pkg::MuBi4True, + ndm_reset + ), UVM_MEDIUM) + + csr_wr(.ptr(ral.reset_en[0]), .value(resets_en)); + // This is necessary to propagate reset_en. + wait_for_csr_to_propagate_to_slow_domain(); + + // Trigger resets. The glitch is sent prior to the externals since if it is delayed + // it will cause a separate reset after the externals, which complicates the checks. + if (power_glitch_reset) send_power_glitch(); + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + + `uvm_info(`gfn, $sformatf("Sending resets=0x%x", resets), UVM_MEDIUM) + cfg.pwrmgr_vif.update_resets(resets); + `uvm_info(`gfn, $sformatf("Sending sw reset from rstmgr=%b", sw_rst_from_rstmgr), UVM_MEDIUM) + if (escalation_reset) send_escalation_reset(); + cfg.pwrmgr_vif.update_sw_rst_req(sw_rst_from_rstmgr); + if (ndm_reset) send_ndm_reset(); + + `uvm_info(`gfn, "Wait for Fast State NE FastPwrStateActive", UVM_MEDIUM) + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + + if (cfg.pwrmgr_vif.rom_ctrl.done != prim_mubi_pkg::MuBi4True) begin + // Check fast state is not FastPwrStateActive for a while + repeat (20) begin + @cfg.slow_clk_rst_vif.cb; + `DV_CHECK_NE(cfg.pwrmgr_vif.fast_state, pwrmgr_pkg::FastPwrStateActive) + end + + // Set done to True. + `uvm_info(`gfn, "Set rom_ctrl.done input True", UVM_MEDIUM) + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True; + cfg.slow_clk_rst_vif.wait_clks(2); + end + + if (cfg.pwrmgr_vif.rom_ctrl.good != prim_mubi_pkg::MuBi4True) begin + bit blocked = 0; + detect_block(blocked); + if (blocked) begin + if (release_by_good) begin + // Set to good. + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True; + end else begin + // Disable rom checks. + `uvm_info(`gfn, "Set lc ctrl inputs On", UVM_MEDIUM) + cfg.pwrmgr_vif.lc_hw_debug_en = lc_ctrl_pkg::On; + cfg.pwrmgr_vif.lc_dft_en = lc_ctrl_pkg::On; + end + end // if (blocked) + cfg.slow_clk_rst_vif.wait_clks(2); + end + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "Back from reset", UVM_MEDIUM) + + check_wake_info(.reasons('0), .fall_through(1'b0), .abort(1'b0)); + + cfg.slow_clk_rst_vif.wait_clks(4); + check_reset_status('0); + + // And check interrupt is not set. + check_and_clear_interrupt(.expected(1'b0)); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_disable_rom_integrity_check_vseq diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv new file mode 100644 index 0000000000000..195adc3c8b645 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv @@ -0,0 +1,42 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Description: +// This sequence creates escalation clock and reset malfunction at FastPwrStateActive state. +// This event will trigger timeout counter and assert timeout signal +// when timeout counter reaches EscTimeOutCnt value. +// Once the timeout occurs, it will create fatal alert and alert agent(tb) will set esc rst. +// The pass or failure status is determined in the cip scoreboard. +class pwrmgr_esc_clk_rst_malfunc_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_esc_clk_rst_malfunc_vseq) + + `uvm_object_new + constraint num_trans_c {num_trans inside {[1 : 3]};} + + virtual task body(); + wait_for_fast_fsm(FastFsmActive); + // Wait some time so the stimulus is sent after the fast fsm becoming active. + cfg.clk_rst_vif.wait_clks(4); + expect_fatal_alerts = 1; + trigger_escalation_timeout(); + wait_for_fast_fsm(FastFsmActive); + endtask : body + + // Trigers an escalation timeout fault, either stopping clk_esc_i or driving rst_esc_ni. + // + // Randomly set a bit to 0 or 1: if 0 stop clk_esc_i, if 1 make rst_esc_ni active. + task trigger_escalation_timeout(); + int which = $urandom_range(0, 1); + `uvm_info(`gfn, $sformatf("Triggering escalation via %0s", which ? "rst" : "clk"), UVM_MEDIUM) + if (which == 0) cfg.esc_clk_rst_vif.stop_clk(); + else cfg.esc_clk_rst_vif.drive_rst_pin(1'b0); + + // Wait for cpu fetch to be disabled, as an indication a reset is triggered. + `DV_SPINWAIT(wait (cfg.pwrmgr_vif.fetch_en != lc_ctrl_pkg::On);, + "timeout waiting for the CPU to be inactive", FetchEnTimeoutNs) + `uvm_info(`gfn, "Releasing trigger", UVM_MEDIUM) + if (which == 0) cfg.esc_clk_rst_vif.start_clk(); + else cfg.esc_clk_rst_vif.drive_rst_pin(1'b1); + endtask : trigger_escalation_timeout +endclass diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_escalation_timeout_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_escalation_timeout_vseq.sv new file mode 100644 index 0000000000000..12a8c851ef386 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_escalation_timeout_vseq.sv @@ -0,0 +1,88 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Description: +// This test checks that an escalation reset is generated when the escalation clock stops for +// enough cycles. +class pwrmgr_escalation_timeout_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_escalation_timeout_vseq) + + `uvm_object_new + + // The following two parameters are used to determine when to perform checks. + + // The number of clock cycles with a stopped escalation clock before raising escalation is 128. + // But the logic can wait for up to 7 more cycles before it starts the counter, and there is + // some additional fast clock cycles of delay in the logic that triggers the escalation to + // be signalled. This adds 12 extra cycles to be conservative. + localparam int EscTimeoutMainClkThreshold = 128 + 7 + 12; + + // In addition, there is a clock domain crossing to the slow clock, which can add a couple slow + // clocks cycles plus an extra cycle for the input to meet the next clock cycle. + localparam int EscTimeoutSlowClkThreshold = 2 + 1; + + int trans_cnt = 0; + constraint num_trans_c {num_trans inside {[1 : 5]};} + + // This stops the escalation clock for a certain number of cycles, and + // checks a reset occurs or not, depending on expect_reset. + task check_stopped_esc_clk(int stop_cycles, bit expect_reset); + fork + begin + `uvm_info(`gfn, $sformatf( + "Stopping escalation clock for %0d cycles %s expecting reset", + stop_cycles, expect_reset ? "" : "not "), + UVM_MEDIUM) + cfg.esc_clk_rst_vif.stop_clk(); + // The clock will be restarted while handling a reset, so no need to restart it here. + if (!expect_reset) begin + cfg.clk_rst_vif.wait_clks(stop_cycles); + `uvm_info(`gfn, "Restarting escalation clock", UVM_MEDIUM) + cfg.esc_clk_rst_vif.start_clk(); + cfg.esc_clk_rst_vif.wait_clks(4000); + end + end + begin + if (expect_reset) begin + // The expectation is to create an outgoing reset request, disable cpu fetching, and the + // reset cause to indicate a hardware request. + // Turn the cycle counts into a number of nanoseconds for waiting with timeout. + // The clk_rst_vifs give the period in pico seconds so divide by 1000. + int wait_ns = (EscTimeoutMainClkThreshold * cfg.clk_rst_vif.clk_period_ps + + EscTimeoutSlowClkThreshold * cfg.slow_clk_rst_vif.clk_period_ps) / 1000; + `DV_SPINWAIT( + wait(cfg.pwrmgr_vif.fetch_en != lc_ctrl_pkg::On && + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetEscIdx] == 1'b1 && + cfg.pwrmgr_vif.pwr_rst_req.reset_cause == pwrmgr_pkg::HwReq); + `uvm_info(`gfn, "escalation reset completed", UVM_LOW), + "escalation reset was not completed as expected", wait_ns) + end else begin + repeat (8000) begin + cfg.clk_rst_vif.wait_clks(1); + if (cfg.pwrmgr_vif.fetch_en != lc_ctrl_pkg::On) begin + `uvm_error(`gfn, "Unexpected cpu fetch disable, indicating a reset") + end + end + end + end + join + endtask + + virtual task body(); + wait_for_fast_fsm(FastFsmActive); + cfg.slow_clk_rst_vif.set_freq_mhz(1); + cfg.esc_clk_rst_vif.wait_clks(200); + // The timeout is not accurately predictable for two reasons: + // - The initial count for the timeout can be from 0 to 7, which means the timeout could + // happen between 121 and 128 cycles after the clock. + // - The timeout has a req-ack synchronizer which has some randomness due to the phase. + // This adds a few more cycles of uncertainty. + // Keep the clock stopped for less than 118 cycles should be safe to avoid an alert. + check_stopped_esc_clk(118, 1'b0); + check_stopped_esc_clk(2000, 1'b1); + wait_for_fast_fsm(FastFsmActive); + check_stopped_esc_clk(136, 1'b1); + endtask : body + +endclass diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv new file mode 100644 index 0000000000000..0a27b8454f11d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv @@ -0,0 +1,42 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// This test asserts glitch to power_reset and see +// dut can recover gracefully. +class pwrmgr_glitch_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_glitch_vseq) + + `uvm_object_new + + int trans_cnt = 0; + constraint num_trans_c {num_trans inside {[1 : 5]};} + + virtual task body(); + expect_fatal_alerts = 1; + for (int i = 0; i < num_trans; ++i) begin + wait_for_fast_fsm(FastFsmActive); + cfg.clk_rst_vif.wait_clks(4); + + fork + send_power_glitch(); + begin + cfg.pwrmgr_vif.update_ast_main_pok(0); + cfg.slow_clk_rst_vif.wait_clks(2); + cfg.pwrmgr_vif.update_ast_main_pok(1); + end + join + + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateResetPrep && + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[2] == 1);, $sformatf( + "checker timeout : fast_state %s, pwr_rst_req 0x%x", + cfg.pwrmgr_vif.fast_state.name, + cfg.pwrmgr_vif.pwr_rst_req.rstreqs + ), 10000) + + dut_init(); + end + endtask : body +endclass diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_global_esc_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_global_esc_vseq.sv new file mode 100644 index 0000000000000..19cfba5ff531d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_global_esc_vseq.sv @@ -0,0 +1,63 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// This test asserts global escalation reset to dut +// and check glocal escalation request is handled by +// dut properly. +class pwrmgr_global_esc_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_global_esc_vseq) + + `uvm_object_new + + int trans_cnt = 0; + constraint num_trans_c {num_trans inside {[1 : 5]};} + + virtual task body(); + fork + send_esc(); + check_rst_req(); + join + endtask : body + + task send_esc(); + int cycle; + for (int i = 0; i < num_trans; ++i) begin + wait_for_fast_fsm(FastFsmActive); + cycle = $urandom_range(50, 300); + send_escalation_reset(); + repeat (cycle) @(cfg.clk_rst_vif.cb); + clear_escalation_reset(); + end + endtask : send_esc + + task check_rst_req(); + bit dut_init_done = -1; + + while (trans_cnt < num_trans) begin + @(cfg.clk_rst_vif.cb); + wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive && + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[3] == 1'b1); + trans_cnt++; + + // Make sure previous dut_init is done + if (dut_init_done > -1) begin + wait(dut_init_done == 1); + end + // Spawning dut_init thread then go to + // wait reset state + fork + begin + dut_init_done = 0; + dut_init(); + dut_init_done = 1; + end + begin + cfg.clk_rst_vif.wait_clks(10); + end + join_any + end + wait(dut_init_done == 1); + endtask : check_rst_req + +endclass diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_invalid_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_invalid_vseq.sv new file mode 100644 index 0000000000000..c65bcbfa3cae3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_invalid_vseq.sv @@ -0,0 +1,140 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// The test to create transition to invalid state from any lowpower transitions. +class pwrmgr_lowpower_invalid_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_lowpower_invalid_vseq) + `uvm_object_new + + // Create enum to map rtl local sparse state + // to continuous dv state. + typedef enum bit [3:0] { + DVWaitDisClks = 0, + DVWaitFallThrough = 1, + DVWaitNvmIdleChk = 2, + DVWaitLowPowerPrep = 3, + DVWaitReqPwrDn = 4, + DVWaitLowPower = 5, + DVWaitEnableClocks = 6, + DVWaitReleaseLcRst = 7, + DVWaitOtpInit = 8, + DVWaitLcInit = 9, + DVWaitAckPwrUp = 10, + DVWaitRomCheck = 11, + DVWaitStrap = 12, + DVWaitActive = 13, + DVWaitInvalid = 14 + } reset_index_e; + + constraint wakeups_c {wakeups != 0;} + constraint wakeup_en_c { + solve wakeups before wakeups_en; + |(wakeups_en & wakeups) == 1'b1; + } + + task body(); + reset_index_e reset_index; + resets_t enabled_resets; + string path = "tb.dut.u_fsm.fsm_invalid_i"; + int num_of_target_states = 4; + + // Spurious interrupt check can be executed by + // residue of lowpower task. Since we cannot kill csr op + // by disable fork, we have to disable spurious interrup check. + cfg.invalid_st_test = 1; + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "At body start", UVM_MEDIUM) + check_wake_status('0); + reset_index = DVWaitFallThrough; + + for (int i = 0; i < num_of_target_states; ++i) begin + `uvm_info(`gfn, $sformatf("Starting new round%0d %s", i, reset_index.name), UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + fork + start_lowpower_transition(); + begin + int wait_time_ns = 10000; + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == dv2rtl_st(reset_index));, $sformatf( + "Timed out waiting for state %s", reset_index.name), wait_time_ns) + + @cfg.clk_rst_vif.cbn; + `DV_CHECK(uvm_hdl_force(path, 1)) + `uvm_info(`gfn, "Injected invalid slow state", UVM_MEDIUM) + @cfg.clk_rst_vif.cb; + end + join_any + @cfg.clk_rst_vif.cb; + `DV_CHECK(uvm_hdl_release(path)) + `DV_CHECK(cfg.pwrmgr_vif.fast_state, pwrmgr_pkg::FastPwrStateInvalid) + + repeat (10) @cfg.clk_rst_vif.cb; + + apply_reset(); + reset_index=reset_index.next(); + wait_for_fast_fsm(FastFsmActive); + end // for (int i = 0; i < 4; ++i) + endtask + + task start_lowpower_transition(); + wakeups_t enabled_wakeups = wakeups_en & wakeups; + `DV_CHECK(enabled_wakeups, $sformatf( + "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en)) + `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", enabled_wakeups), UVM_MEDIUM) + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + + low_power_hint = 1; + update_control_csr(); + + `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", enabled_wakeups), UVM_MEDIUM) + + // Initiate low power transition. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + set_nvms_idle(); + + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + + if (ral.control.main_pd_n.get_mirrored_value() == 1'b0) begin + wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry); + end + + // Now bring it back. + cfg.slow_clk_rst_vif.wait_clks(cycles_before_wakeup); + cfg.pwrmgr_vif.update_wakeups(wakeups); + + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + // wakeups should be registered. + cfg.pwrmgr_vif.update_wakeups('1); + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "Back from wakeup", UVM_MEDIUM) + endtask : start_lowpower_transition + + function pwrmgr_pkg::fast_pwr_state_e dv2rtl_st(reset_index_e idx); + case (idx) + DVWaitDisClks: return pwrmgr_pkg::FastPwrStateDisClks; + DVWaitFallThrough: return pwrmgr_pkg::FastPwrStateFallThrough; + DVWaitNvmIdleChk: return pwrmgr_pkg::FastPwrStateNvmIdleChk; + DVWaitLowPowerPrep: return pwrmgr_pkg::FastPwrStateLowPowerPrep; + DVWaitReqPwrDn: return pwrmgr_pkg::FastPwrStateReqPwrDn; + DVWaitLowPower: return pwrmgr_pkg::FastPwrStateLowPower; + DVWaitEnableClocks: return pwrmgr_pkg::FastPwrStateEnableClocks; + DVWaitReleaseLcRst: return pwrmgr_pkg::FastPwrStateReleaseLcRst; + DVWaitOtpInit: return pwrmgr_pkg::FastPwrStateOtpInit; + DVWaitLcInit: return pwrmgr_pkg::FastPwrStateLcInit; + DVWaitAckPwrUp: return pwrmgr_pkg::FastPwrStateAckPwrUp; + DVWaitRomCheck: return pwrmgr_pkg::FastPwrStateRomCheckDone; + DVWaitStrap: return pwrmgr_pkg::FastPwrStateStrap; + DVWaitActive: return pwrmgr_pkg::FastPwrStateActive; + DVWaitInvalid: return pwrmgr_pkg::FastPwrStateInvalid; + default: begin + `uvm_error("dv2rma_st", $sformatf("unknown index:%0d", idx)) + end + endcase + endfunction : dv2rtl_st + +endclass : pwrmgr_lowpower_invalid_vseq diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv new file mode 100644 index 0000000000000..75064051a6a74 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv @@ -0,0 +1,138 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The lowpower_wakeup race test randomly enables wakeups, info capture, and interrupts, +// and sends wakeups in the temporal vecinity of low power entry. It also sends wakeups +// after wakeup processing starts. +class pwrmgr_lowpower_wakeup_race_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_lowpower_wakeup_race_vseq) + + `uvm_object_new + + constraint wakeups_c {wakeups != 0;} + + rand bit keep_prior_wake_info; + + constraint wakeup_en_c { + solve wakeups before wakeups_en; + |(wakeups_en & wakeups) == 1'b1; + } + + rand int cycles_before_early_wakeup; + rand int cycles_before_transition; + constraint cycles_racing_c { + cycles_before_early_wakeup inside {[2 : 8]}; + cycles_before_transition inside {[2 : 8]}; + } + + task body(); + logic [TL_DW-1:0] value; + wakeups_t prior_reasons = '0; + bit prior_fall_through = '0; + bit prior_abort = '0; + wait_for_fast_fsm(FastFsmActive); + + check_wake_status('0); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", wakeups_en & wakeups), UVM_MEDIUM) + + if (keep_prior_wake_info) begin + csr_rd(.ptr(ral.wake_info.reasons), .value(prior_reasons)); + csr_rd(.ptr(ral.wake_info.fall_through), .value(prior_fall_through)); + csr_rd(.ptr(ral.wake_info.abort), .value(prior_abort)); + end else begin + clear_wake_info(); + prior_reasons = '0; + prior_fall_through = '0; + prior_abort = '0; + end + `uvm_info(`gfn, $sformatf( + "Prior wake_info: reasons=0x%x, fall_through=%b, abort=%b", + prior_reasons, + prior_fall_through, + prior_abort + ), UVM_MEDIUM) + + `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"), + UVM_MEDIUM) + csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture)); + + low_power_hint = 1'b1; + update_control_csr(); + + set_nvms_idle(); + + // This will send the wakeup and trigger low power entry so they almost coincide. + fork + begin + cfg.slow_clk_rst_vif.wait_clks(cycles_before_transition); + // Initiate low power transition. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + end + begin + cfg.slow_clk_rst_vif.wait_clks(cycles_before_early_wakeup); + // Send the wakeups. + cfg.pwrmgr_vif.update_wakeups(wakeups); + end + join + + wait_for_fast_fsm(FastFsmInactive); + + // Check wake_status prior to wakeup, or the unit requesting wakeup will have been reset. + // This read will not work in the chip, since the processor will be asleep. + // We wait until the cycle following the fast fsm lc_rst release. + if (ral.control.main_pd_n.get_mirrored_value() == 1'b0) begin + wait_for_lc_rst_release(); + check_wake_status(wakeups & wakeups_en); + `uvm_info(`gfn, $sformatf("Got wake_status=0x%x", wakeups & wakeups_en), UVM_MEDIUM) + end + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + // Send more wakeups to make sure they are reported in CSRs. With this all enabled + // wakeups should be registered. + cfg.pwrmgr_vif.update_wakeups('1); + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "Back from wakeup", UVM_MEDIUM) + + // make this check parallel. + // to avoid csr rd blocking later status read request and + // miss status update window. + @cfg.clk_rst_vif.cb; + fork + begin + fast_check_reset_status(0); + end + begin + fast_check_wake_info(.reasons(wakeups_en), .prior_reasons(prior_reasons), + .fall_through(1'b0), .abort(1'b0), + .prior_fall_through(prior_fall_through), .prior_abort(prior_abort)); + end + join + // This is the expected side-effect of the low power entry reset, since the source of the + // non-aon wakeup sources will deassert it as a consequence of their reset. + // Some aon wakeups may remain active until software clears them. If they didn't, such wakeups + // will remain active, preventing the device from going to sleep. + cfg.pwrmgr_vif.update_wakeups('0); + cfg.slow_clk_rst_vif.wait_clks(10); + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + + // wait for clock is on + cfg.clk_rst_vif.wait_clks(10); + + check_wake_status('0); + + // Wait for interrupt to be generated whether or not it is enabled. + cfg.slow_clk_rst_vif.wait_clks(10); + check_and_clear_interrupt(.expected(1'b1)); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_lowpower_wakeup_race_vseq diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv new file mode 100644 index 0000000000000..a457fc55e9bc6 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv @@ -0,0 +1,79 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// The wakeup_reset test randomly enables wakeups and resets, info capture, and interrupts, +// and sends wakeups and resets in close temporal proximity at random times. +class pwrmgr_repeat_wakeup_reset_vseq extends pwrmgr_wakeup_reset_vseq; + `uvm_object_utils(pwrmgr_repeat_wakeup_reset_vseq) + + `uvm_object_new + + bit [lc_ctrl_pkg::TxWidth-1:0] bad_lc_tx; + + int cycles_from_reset; + int micros_to_release; + + bit super_sequence_done; + + // add invalid value to rom_ctrl + virtual task twirl_rom_response(); + add_rom_rsp_noise(); + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4False; + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4False; + cfg.clk_rst_vif.wait_clks(5); + add_rom_rsp_noise(); + wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone); + add_rom_rsp_noise(); + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True; + cfg.clk_rst_vif.wait_clks(5); + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True; + endtask + + task body(); + num_trans_c.constraint_mode(0); + num_trans = 50; + super_sequence_done = 0; + + disable_assert(); + fork + begin + super.body(); + super_sequence_done = 1; + end + drv_stim(mubi_mode); + join + endtask : body + + function void disable_assert(); + $assertoff(0, "tb.dut.u_cdc.u_sync_rom_ctrl"); + endfunction : disable_assert + + task drv_stim(pwrmgr_mubi_e mubi_mode); + if (mubi_mode == PwrmgrMubiLcCtrl) drv_lc_ctrl(); + endtask : drv_stim + + task drv_lc_ctrl(); + int delay; + + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(cycles_from_reset, cycles_from_reset inside {[2 : 8]};) + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(micros_to_release, micros_to_release inside {[2 : 4]};) + + repeat (50) begin + wait(cfg.esc_clk_rst_vif.rst_n); + cfg.clk_rst_vif.wait_clks(cycles_from_reset); + if (super_sequence_done) break; + `uvm_info(`gfn, "Injection to lc_hw_debug_en", UVM_MEDIUM) + cfg.pwrmgr_vif.lc_hw_debug_en = get_rand_lc_tx_val( + .t_weight(1), .f_weight(1), .other_weight(2) + ); + #(micros_to_release * 1us); + `uvm_info(`gfn, "Injection to lc_dft_en", UVM_MEDIUM) + if (super_sequence_done) break; + cfg.pwrmgr_vif.lc_dft_en = get_rand_lc_tx_val(.t_weight(1), .f_weight(1), .other_weight(2)); + #(micros_to_release * 1us); + end // repeat (50) + `uvm_info(`gfn, "ended drv_lc_ctrl", UVM_MEDIUM) + endtask : drv_lc_ctrl + +endclass : pwrmgr_repeat_wakeup_reset_vseq diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv new file mode 100644 index 0000000000000..7b0f55f83d260 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv @@ -0,0 +1,129 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// The test to create transition to invalid state from any reset transitions. +class pwrmgr_reset_invalid_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_reset_invalid_vseq) + `uvm_object_new + + // Create enum to map rtl local sparse state + // to continuous dv state. + typedef enum bit [3:0] { + DVWaitDisClks = 0, + DVWaitNvmShutDown = 1, + DVWaitResetPrep = 2, + DVWaitLowPower = 3, + DVWaitEnableClocks = 4, + DVWaitReleaseLcRst = 5, + DVWaitOtpInit = 6, + DVWaitLcInit = 7, + DVWaitAckPwrUp = 8, + DVWaitRomCheck = 9, + DVWaitStrap = 10, + DVWaitActive = 11, + DVWaitInvalid = 12 + } reset_index_e; + + constraint wakeups_c {wakeups == 0;} + constraint wakeups_en_c {wakeups_en == 0;} + + function void post_randomize(); + sw_rst_from_rstmgr = get_rand_mubi4_val(.t_weight(8), .f_weight(4), .other_weight(4)); + super.post_randomize(); + endfunction + + task body(); + reset_index_e reset_index; + resets_t enabled_resets; + string path = "tb.dut.u_fsm.fsm_invalid_i"; + int num_of_target_states = 11; + + wait_for_fast_fsm(FastFsmActive); + check_reset_status('0); + $assertoff(0, "tb.dut.u_cdc.u_clr_reqack.SyncReqAckHoldReq"); + + for (int i = 0; i < num_of_target_states; ++i) begin + `uvm_info(`gfn, $sformatf("Starting new round %0d", i), UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + fork + create_any_reset_event(); + begin + int wait_time_ns = 20000; + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == dv2rtl_st(reset_index));, $sformatf( + "Timed out waiting for state %s", reset_index.name), wait_time_ns) + + @cfg.clk_rst_vif.cbn; + `uvm_info(`gfn, $sformatf("Will cause invalid state forcing %s = 1", path), UVM_MEDIUM) + `DV_CHECK(uvm_hdl_force(path, 1)) + @cfg.clk_rst_vif.cb; + end + join + @cfg.clk_rst_vif.cb; + `DV_CHECK(uvm_hdl_release(path)) + `DV_CHECK(cfg.pwrmgr_vif.fast_state, pwrmgr_pkg::FastPwrStateInvalid) + `uvm_info(`gfn, "All good, resetting for next round", UVM_MEDIUM) + repeat (10) @cfg.clk_rst_vif.cb; + apply_reset(); + reset_index=reset_index.next(); + wait_for_fast_fsm(FastFsmActive); + end + endtask + + task create_any_reset_event(); + resets_t enabled_resets = resets_t'(resets_en & resets); + `uvm_info(`gfn, $sformatf( + "Enabled resets=0x%x, power_reset=%b, escalation=%b, sw_reset=%b, ndm_reset=%b", + enabled_resets, + power_glitch_reset, + escalation_reset, + sw_rst_from_rstmgr == prim_mubi_pkg::MuBi4True, + ndm_reset + ), UVM_MEDIUM) + + `uvm_info(`gfn, "Trying to write to reset_en CSR", UVM_MEDIUM) + csr_wr(.ptr(ral.reset_en[0]), .value(resets_en)); + // This is necessary to propagate reset_en. + wait_for_csr_to_propagate_to_slow_domain(); + + // Trigger resets. The glitch is sent prior to the externals since if it is delayed + // it will cause a separate reset after the externals, which complicates the checks. + if (power_glitch_reset) send_power_glitch(); + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + + if (cycles_before_reset == 0) enabled_resets = 0; + + `uvm_info(`gfn, $sformatf("Sending resets=0x%x", resets), UVM_MEDIUM) + cfg.pwrmgr_vif.update_resets(resets); + `uvm_info(`gfn, $sformatf("Sending sw reset from rstmgr=%b", sw_rst_from_rstmgr), UVM_MEDIUM) + if (escalation_reset) send_escalation_reset(); + if (ndm_reset) send_ndm_reset(); + cfg.pwrmgr_vif.update_sw_rst_req(sw_rst_from_rstmgr); + + endtask : create_any_reset_event + + function pwrmgr_pkg::fast_pwr_state_e dv2rtl_st(reset_index_e idx); + case (idx) + DVWaitDisClks: return pwrmgr_pkg::FastPwrStateDisClks; + DVWaitNvmShutDown: return pwrmgr_pkg::FastPwrStateNvmShutDown; + DVWaitResetPrep: return pwrmgr_pkg::FastPwrStateResetPrep; + DVWaitLowPower: return pwrmgr_pkg::FastPwrStateLowPower; + DVWaitEnableClocks: return pwrmgr_pkg::FastPwrStateEnableClocks; + DVWaitReleaseLcRst: return pwrmgr_pkg::FastPwrStateReleaseLcRst; + DVWaitOtpInit: return pwrmgr_pkg::FastPwrStateOtpInit; + DVWaitLcInit: return pwrmgr_pkg::FastPwrStateLcInit; + DVWaitAckPwrUp: return pwrmgr_pkg::FastPwrStateAckPwrUp; + DVWaitRomCheck: return pwrmgr_pkg::FastPwrStateRomCheckDone; + DVWaitStrap: return pwrmgr_pkg::FastPwrStateStrap; + DVWaitActive: return pwrmgr_pkg::FastPwrStateActive; + DVWaitInvalid: return pwrmgr_pkg::FastPwrStateInvalid; + default: begin + `uvm_error("dv2rma_st", $sformatf("unknown index:%0d", idx)) + end + endcase + endfunction : dv2rtl_st + +endclass : pwrmgr_reset_invalid_vseq diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_vseq.sv new file mode 100644 index 0000000000000..eca20c05a4111 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_vseq.sv @@ -0,0 +1,79 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The reset test randomly introduces external resets, ndm resets, power glitches, and escalation +// resets. +class pwrmgr_reset_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_reset_vseq) + `uvm_object_new + + constraint wakeups_c {wakeups == 0;} + constraint wakeups_en_c {wakeups_en == 0;} + + function void post_randomize(); + sw_rst_from_rstmgr = get_rand_mubi4_val(.t_weight(8), .f_weight(4), .other_weight(4)); + super.post_randomize(); + endfunction + + task body(); + logic [TL_DW-1:0] value; + resets_t enabled_resets; + wait_for_fast_fsm(FastFsmActive); + + check_reset_status('0); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + enabled_resets = resets_en & resets; + `uvm_info(`gfn, $sformatf( + "Enabled resets=0x%x, power_reset=%b, escalation=%b, sw_reset=%b, ndm_reset=%b", + enabled_resets, + power_glitch_reset, + escalation_reset, + sw_rst_from_rstmgr == prim_mubi_pkg::MuBi4True, + ndm_reset + ), UVM_MEDIUM) + + csr_wr(.ptr(ral.reset_en[0]), .value(resets_en)); + // This is necessary to propagate reset_en, and it needs a couple additional slow + // clock cycles for a synchronizer to be ready to mask incoming resets. + wait_for_csr_to_propagate_to_slow_domain(); + cfg.slow_clk_rst_vif.wait_clks(2); + + // Trigger resets. The glitch is sent prior to the externals since if it is delayed + // it will cause a separate reset after the externals, which complicates the checks. + if (power_glitch_reset) send_power_glitch(); + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + + `uvm_info(`gfn, $sformatf("Sending resets=0x%x", resets), UVM_MEDIUM) + cfg.pwrmgr_vif.update_resets(resets); + `uvm_info(`gfn, $sformatf("Sending sw reset from rstmgr=%b", sw_rst_from_rstmgr), UVM_MEDIUM) + if (escalation_reset) begin + send_escalation_reset(); + // Wait for the alert to propagate to fault_status? + end + cfg.pwrmgr_vif.update_sw_rst_req(sw_rst_from_rstmgr); + if (ndm_reset) send_ndm_reset(); + + // Expect to start reset. + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + `uvm_info(`gfn, "Started to process reset", UVM_MEDIUM) + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "Back from reset", UVM_MEDIUM) + + check_wake_info(.reasons('0), .fall_through(1'b0), .abort(1'b0)); + + cfg.slow_clk_rst_vif.wait_clks(4); + check_reset_status('0); + + // And check interrupt is not set. + check_and_clear_interrupt(.expected(1'b0)); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_reset_vseq diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv new file mode 100644 index 0000000000000..b8682b1b3c62c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv @@ -0,0 +1,48 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Decription: +// Create low power transition and wakeup a few times. +// When PWRMGR.CONTROL.LOW_POWER_HINT is set and core_sleep is high, +// issue random write to PWRMGR.CONTROL and check +// PWRMGR.CONTROL value is not changed, except for LOW_POWER_HINT. +class pwrmgr_sec_cm_ctrl_config_regwen_vseq extends pwrmgr_wakeup_vseq; + `uvm_object_utils(pwrmgr_sec_cm_ctrl_config_regwen_vseq) + + `uvm_object_new + + virtual task pre_start(); + super.pre_start(); + cfg.disable_csr_rd_chk = 1; + endtask : pre_start + + task proc_illegal_ctrl_access(); + uvm_reg_data_t wdata, expdata, compare_mask; + // CONTROL.LOW_POWER_HINT is hardware-writeable, so mask it from checking. + // It gets cleared very quickly. + compare_mask = '1; + compare_mask = compare_mask - ral.control.low_power_hint.get_field_mask(); + + cfg.clk_rst_vif.wait_clks(1); + wait(cfg.pwrmgr_vif.lowpwr_cfg_wen == 0); + + repeat ($urandom_range(1, 5)) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata) + expdata = ral.control.get(); + `uvm_info(`gfn, $sformatf("csr start %x", ral.control.get()), UVM_HIGH) + csr_wr(.ptr(ral.control), .value(wdata)); + csr_rd_check(.ptr(ral.control), .compare_value(expdata), .compare_mask(compare_mask)); + `uvm_info(`gfn, "csr done", UVM_HIGH) + end + endtask : proc_illegal_ctrl_access + + virtual task initiate_low_power_transition(); + super.initiate_low_power_transition(); + // The access checks can only happen if the bus is powered and the clock + // is active. + if ((ral.control.main_pd_n.get_mirrored_value() == 1'b1) && + (ral.control.io_clk_en.get_mirrored_value() == 1'b1)) begin + proc_illegal_ctrl_access(); + end + endtask +endclass : pwrmgr_sec_cm_ctrl_config_regwen_vseq diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_smoke_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_smoke_vseq.sv new file mode 100644 index 0000000000000..b54c5cc08dd73 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_smoke_vseq.sv @@ -0,0 +1,90 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The smoke test brings the pwrmgr through a POR reset, followed by a low +// power sequence, followed by reset. + +// smoke test vseq +class pwrmgr_smoke_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_smoke_vseq) + + `uvm_object_new + constraint cycles_before_rst_lc_src_c {cycles_before_rst_lc_src inside {[1 : 2]};} + constraint cycles_before_otp_done_c {cycles_before_otp_done inside {[1 : 2]};} + constraint cycles_before_lc_done_c {cycles_before_lc_done inside {[1 : 2]};} + + constraint wakeups_c {wakeups != 0;} + constraint resets_c {resets != 0;} + + constraint control_enables_c { + control_enables.core_clk_en == ral.control.core_clk_en.get_reset(); + control_enables.io_clk_en == ral.control.io_clk_en.get_reset(); + control_enables.usb_clk_en_lp == ral.control.usb_clk_en_lp.get_reset(); + control_enables.usb_clk_en_active == ral.control.usb_clk_en_active.get_reset(); + control_enables.main_pd_n == ral.control.main_pd_n.get_reset(); + } + + task body(); + logic [TL_DW-1:0] value; + wakeups_t wakeup_en; + resets_t reset_en; + wait_for_fast_fsm(FastFsmActive); + set_nvms_idle(); + setup_interrupt(.enable(1'b1)); + + check_wake_status('0); + check_reset_status('0); + + // Enable all wakeups so any peripheral can cause a wakeup. + wakeup_en = '1; + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeup_en)); + + low_power_hint = 1'b1; + update_control_csr(); + + // Initiate low power transition. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry); + + // Now bring it back. + cfg.slow_clk_rst_vif.wait_clks(cycles_before_wakeup); + cfg.pwrmgr_vif.update_wakeups(wakeups); + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "smoke back from wakeup", UVM_MEDIUM) + + check_wake_status(wakeups & wakeup_en); + check_reset_status('0); + // And make the cpu active. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + + cfg.pwrmgr_vif.update_wakeups('0); + check_and_clear_interrupt(.expected(1'b1)); + + // Enable resets. + reset_en = '1; + csr_wr(.ptr(ral.reset_en[0]), .value(reset_en)); + wait_for_csr_to_propagate_to_slow_domain(); + + // Trigger a reset. + cfg.pwrmgr_vif.update_resets(resets); + cfg.slow_clk_rst_vif.wait_clks(2); + wait_for_reset_cause(pwrmgr_pkg::HwReq); + + // Now bring it back: the slow fsm doesn't participate on this, so we cannot + // rely on the ctrl_cfg_regwen CSR. Wait for the reset status to clear. + wait_for_fast_fsm(FastFsmActive); + + // The reset_status CSR should be clear since the unit requesting reset + // should have been reset, so the incoming reset should have cleared. + check_reset_status('0); + check_wake_status('0); + clear_wake_info(); + + // Wait for interrupt to be generated whether or not it is enabled. + cfg.slow_clk_rst_vif.wait_clks(10); + check_and_clear_interrupt(.expected(1'b0)); + endtask + +endclass : pwrmgr_smoke_vseq diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_stress_all_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_stress_all_vseq.sv new file mode 100644 index 0000000000000..a088b2975b230 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_stress_all_vseq.sv @@ -0,0 +1,42 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// combine all pwrmgr seqs (except below seqs) in one seq to run sequentially +// 1. csr seq, which requires scb to be disabled +class pwrmgr_stress_all_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_stress_all_vseq) + + `uvm_object_new + + task body(); + string seq_names[] = { + "pwrmgr_aborted_low_power_vseq", + "pwrmgr_lowpower_wakeup_race_vseq", + "pwrmgr_reset_vseq", + "pwrmgr_smoke_vseq", + "pwrmgr_wakeup_reset_vseq", + "pwrmgr_wakeup_vseq" + }; + + for (int i = 1; i <= num_trans; i++) begin + uvm_sequence seq; + pwrmgr_base_vseq pwrmgr_vseq; + uint seq_idx = $urandom_range(0, seq_names.size - 1); + + seq = create_seq_by_name(seq_names[seq_idx]); + `downcast(pwrmgr_vseq, seq) + + pwrmgr_vseq.do_apply_reset = 1; + pwrmgr_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(pwrmgr_vseq) + `uvm_info(`gfn, $sformatf("seq_idx = %0d, sequence is %0s", seq_idx, pwrmgr_vseq.get_name()), + UVM_MEDIUM) + + pwrmgr_vseq.start(p_sequencer); + `uvm_info(`gfn, $sformatf( + "End of sequence %0s with seq_idx = %0d", pwrmgr_vseq.get_name(), seq_idx), + UVM_MEDIUM) + end + endtask : body +endclass diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_sw_reset_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_sw_reset_vseq.sv new file mode 100644 index 0000000000000..5fdceafb753e7 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_sw_reset_vseq.sv @@ -0,0 +1,54 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// The reset test randomly introduces external resets. +class pwrmgr_sw_reset_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_sw_reset_vseq) + `uvm_object_new + + constraint wakeups_c {wakeups == 0;} + constraint wakeups_en_c {wakeups_en == 0;} + + task body(); + int exp_rst; + wait_for_fast_fsm(FastFsmActive); + + check_reset_status('0); + num_trans_c.constraint_mode(0); + num_trans = 30; + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + cfg.pwrmgr_vif.sw_rst_req_i = prim_mubi_pkg::mubi4_t'($urandom_range(0, 15)); + exp_rst = (cfg.pwrmgr_vif.sw_rst_req_i == prim_mubi_pkg::MuBi4True); + cfg.slow_clk_rst_vif.wait_clks(4); + + // sw reset causes fast state machine transition to lowpower state + if (exp_rst == 1) begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive);, + "timeout waiting for non fast-active state", 1000) + end + + // This read is not always possible since the CPU may be off. + + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "Back from reset", UVM_MEDIUM) + + check_wake_info(.reasons('0), .fall_through(1'b0), .abort(1'b0)); + + cfg.slow_clk_rst_vif.wait_clks(4); + check_reset_status('0); + + // And check interrupt is not set. + check_and_clear_interrupt(.expected(1'b0)); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_sw_reset_vseq diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_vseq_list.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_vseq_list.sv new file mode 100644 index 0000000000000..bc09a19a0370d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_vseq_list.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "pwrmgr_base_vseq.sv" +`include "pwrmgr_aborted_low_power_vseq.sv" +`include "pwrmgr_lowpower_wakeup_race_vseq.sv" +`include "pwrmgr_reset_vseq.sv" +`include "pwrmgr_smoke_vseq.sv" +`include "pwrmgr_stress_all_vseq.sv" +`include "pwrmgr_wakeup_reset_vseq.sv" +`include "pwrmgr_wakeup_vseq.sv" +`include "pwrmgr_common_vseq.sv" +`include "pwrmgr_repeat_wakeup_reset_vseq.sv" +`include "pwrmgr_sw_reset_vseq.sv" +`include "pwrmgr_esc_clk_rst_malfunc_vseq.sv" +`include "pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv" +`include "pwrmgr_global_esc_vseq.sv" +`include "pwrmgr_escalation_timeout_vseq.sv" +`include "pwrmgr_glitch_vseq.sv" +`include "pwrmgr_disable_rom_integrity_check_vseq.sv" +`include "pwrmgr_reset_invalid_vseq.sv" +`include "pwrmgr_lowpower_invalid_vseq.sv" diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv new file mode 100644 index 0000000000000..430be24fa9d88 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv @@ -0,0 +1,168 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The wakeup_reset test randomly enables wakeups and resets, info capture, and interrupts, +// and sends wakeups and resets in close temporal proximity at random times. +// Notice it makes no sense to send escalation reset requests while in low +// power, when the clocks are stopped, or while the system is already in reset +// since escalation should not be triggered with reset active. +class pwrmgr_wakeup_reset_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_wakeup_reset_vseq) + + `uvm_object_new + + constraint wakeups_c {wakeups != 0;} + + constraint wakeup_en_c { + solve wakeups before wakeups_en; + (wakeups_en & wakeups) != 0; + } + constraint disable_wakeup_capture_c {disable_wakeup_capture == 1'b0;} + + // Disabling escalation resets per comment above. + constraint escalation_reset_c {escalation_reset == 0;} + + // Cause some delays for the rom_ctrl done and good inputs. Simple, enough to hold the + // transition to active state. + // ICEBOX(lowrisc/opentitan#18236) Consider adding checks to monitor fast state transitions are + // compliant with "ROM Integrity Checks" at + // https://opentitan.org/book/hw/top_darjeeling/ip_autogen/pwrmgr/doc/theory_of_operation.html#rom-integrity-checks + virtual task twirl_rom_response(); + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4False; + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4False; + @(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateAckPwrUp); + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True; + @(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone); + cfg.clk_rst_vif.wait_clks(10); + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4False; + cfg.clk_rst_vif.wait_clks(5); + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True; + cfg.clk_rst_vif.wait_clks(5); + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True; + endtask + + task body(); + logic [TL_DW-1:0] value; + resets_t enabled_resets; + wakeups_t enabled_wakeups; + + wait_for_fast_fsm(FastFsmActive); + + check_reset_status('0); + check_wake_status('0); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + // Enable resets. + enabled_resets = resets_en & resets; + `uvm_info(`gfn, $sformatf( + "Enabled resets=0x%x, power_reset=%b, sw_reset=%b", + enabled_resets, + power_glitch_reset, + sw_rst_from_rstmgr + ), UVM_MEDIUM) + csr_wr(.ptr(ral.reset_en[0]), .value(resets_en)); + + // Enable wakeups. + enabled_wakeups = wakeups_en & wakeups; + `DV_CHECK(enabled_wakeups, $sformatf( + "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en)) + `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", enabled_wakeups), UVM_MEDIUM) + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + + clear_wake_info(); + + `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"), + UVM_MEDIUM) + csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture)); + + low_power_hint = 1'b1; + update_control_csr(); + + // Initiate low power transition. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + set_nvms_idle(); + // Wait for the slow state machine to be in low power. + wait(cfg.pwrmgr_vif.slow_state == pwrmgr_pkg::SlowPwrStateLowPower); + // This will send the wakeup and reset so they almost coincide. + // at low power state, do not use clk_rst_vif, cause it is off. + fork + begin + cfg.slow_clk_rst_vif.wait_clks(cycles_before_reset); + cfg.pwrmgr_vif.update_resets(resets); + + if (power_glitch_reset) begin + send_power_glitch(); + enabled_resets = 0; + end + `uvm_info(`gfn, $sformatf("Sending reset=%b, power_glitch=%b", resets, power_glitch_reset + ), UVM_MEDIUM) + end + + begin + cfg.slow_clk_rst_vif.wait_clks(cycles_before_wakeup); + cfg.pwrmgr_vif.update_wakeups(wakeups); + `uvm_info(`gfn, $sformatf("Sending wakeup=%b", wakeups), UVM_MEDIUM) + end + join + + if (cfg.en_cov) begin + cov.reset_wakeup_distance_cg.sample(cycles_before_reset - cycles_before_wakeup); + end + // twirl_rom_response has some waits, and so does the code to check wake_status, + // so we fork them to avoid conflicts. + fork + begin + // At lowpower state, wait for clock comes back before check any csr + @cfg.clk_rst_vif.cb; + // Check wake_status prior to wakeup, or the unit requesting wakeup will have been reset. + // This read will not work in the chip, since the processor will be asleep. + // Reset status cannot be reliably checked here since it is cleared when reset goes active. + fast_check_wake_status(enabled_wakeups); + `uvm_info(`gfn, $sformatf("Got wake_status=0x%x", enabled_wakeups), UVM_MEDIUM) + end + twirl_rom_response(); + join + + wait_for_fast_fsm(FastFsmActive); + + check_reset_status('0); + + check_wake_info(.reasons(enabled_wakeups), .prior_reasons(1'b0), .fall_through(1'b0), + .prior_fall_through(1'b0), .abort(1'b0), .prior_abort(1'b0)); + + if (mubi_mode == PwrmgrMubiRomCtrl) begin + add_rom_rsp_noise(); + cfg.pwrmgr_vif.rom_ctrl.good = prim_mubi_pkg::MuBi4True; + cfg.clk_rst_vif.wait_clks(5); + cfg.pwrmgr_vif.rom_ctrl.done = prim_mubi_pkg::MuBi4True; + end + + // This is the expected side-effect of the low power entry reset, since the source of the + // non-aon wakeup sources will deassert it as a consequence of their reset. + // Some aon wakeups may remain active until software clears them. If they didn't, such wakeups + // will remain active, preventing the device from going to sleep. + cfg.pwrmgr_vif.update_wakeups('0); + cfg.slow_clk_rst_vif.wait_clks(10); + check_reset_status('0); + check_wake_status('0); + + cfg.slow_clk_rst_vif.wait_clks(10); + // An interrupt will be generated depending on the exact timing of the slow fsm getting + // the reset and wakeup. We choose not to predict it here (it is checked on other tests). + // Instead, we just check if the interrupt status is asserted and it is enabled the + // output interrupt is active. + check_and_clear_interrupt(.expected(1'b1), .check_expected('0)); + // Clear hardware resets: if they are enabled they are cleared when rst_lc_req[1] goes active, + // but this makes sure they are cleared even if none is enabled for the next round. + cfg.pwrmgr_vif.update_resets('0); + // And make the cpu active. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_wakeup_reset_vseq diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_vseq.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_vseq.sv new file mode 100644 index 0000000000000..7c6176d144084 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_vseq.sv @@ -0,0 +1,130 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The wakeup test randomly enables wakeups, info capture, and interrupts, +// and sends wakeups at random times. +class pwrmgr_wakeup_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_wakeup_vseq) + + `uvm_object_new + + constraint wakeups_c {wakeups != 0;} + + rand bit keep_prior_wake_info; + + constraint wakeup_en_c { + solve wakeups before wakeups_en; + |(wakeups_en & wakeups) == 1'b1; + } + + task body(); + logic [TL_DW-1:0] value; + wakeups_t enabled_wakeups; + wakeups_t prior_reasons = '0; + bit prior_fall_through = '0; + bit prior_abort = '0; + + wait_for_fast_fsm(FastFsmActive); + check_wake_status('0); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + + // Instrument interrupts. + setup_interrupt(en_intr); + + // Enable wakeups. + enabled_wakeups = wakeups_en & wakeups; + `DV_CHECK(enabled_wakeups, $sformatf( + "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en)) + `uvm_info(`gfn, $sformatf( + "Enabled wakeups=0x%x, wakeups=0x%x, enables=0x%x", + enabled_wakeups, wakeups, wakeups_en), + UVM_MEDIUM) + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + + if (keep_prior_wake_info) begin + csr_rd(.ptr(ral.wake_info.reasons), .value(prior_reasons)); + csr_rd(.ptr(ral.wake_info.fall_through), .value(prior_fall_through)); + csr_rd(.ptr(ral.wake_info.abort), .value(prior_abort)); + end else begin + clear_wake_info(); + prior_reasons = '0; + prior_fall_through = '0; + prior_abort = '0; + end + `uvm_info(`gfn, $sformatf( + "Prior wake_info: reasons=0x%x, fall_through=%b, abort=%b", + prior_reasons, + prior_fall_through, + prior_abort + ), UVM_MEDIUM) + + `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"), + UVM_MEDIUM) + csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture)); + + low_power_hint = 1'b1; + update_control_csr(); + + // Initiate low power transition. + initiate_low_power_transition(); + + if (ral.control.main_pd_n.get_mirrored_value() == 1'b0) begin + wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry); + end + + // Now bring it back. + cfg.slow_clk_rst_vif.wait_clks(cycles_before_wakeup); + cfg.pwrmgr_vif.update_wakeups(wakeups); + // Check wake_status prior to wakeup, or the unit requesting wakeup will have been reset. + // This read will not work in the chip, since the processor will be asleep. + cfg.slow_clk_rst_vif.wait_clks(4); + // wait for clock is on + cfg.clk_rst_vif.wait_clks(10); + + check_wake_status(enabled_wakeups); + `uvm_info(`gfn, $sformatf("Got wake_status=0x%x", enabled_wakeups), UVM_MEDIUM) + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "Back from wakeup", UVM_MEDIUM) + + @cfg.clk_rst_vif.cb; + fork + begin + fast_check_reset_status(0); + end + begin + fast_check_wake_info(.reasons(enabled_wakeups), .prior_reasons(prior_reasons), + .fall_through(1'b0), .abort(1'b0), + .prior_fall_through(prior_fall_through), .prior_abort(prior_abort)); + end + join + // This is the expected side-effect of the low power entry reset, since the source of the + // non-aon wakeup sources will deassert it as a consequence of their reset. + // Some aon wakeups may remain active until software clears them. If they didn't, such wakeups + // will remain active, preventing the device from going to sleep. + cfg.pwrmgr_vif.update_wakeups('0); + cfg.slow_clk_rst_vif.wait_clks(10); + + // if clock is off, we need to wait until it is resumed. + cfg.clk_rst_vif.wait_clks(5); + check_wake_status('0); + + // And make the cpu active. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + + // Wait for interrupt to be generated whether or not it is enabled. + cfg.slow_clk_rst_vif.wait_clks(10); + check_and_clear_interrupt(.expected(1'b1)); + end + clear_wake_info(); + endtask + + virtual task initiate_low_power_transition(); + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + set_nvms_idle(); + endtask +endclass : pwrmgr_wakeup_vseq diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core new file mode 100644 index 0000000000000..5ece9db65645d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:pwrmgr_sim:0.1" +description: "PWRMGR DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip_interfaces:pwrmgr + files_dv: + depend: + - lowrisc:dv:pwrmgr_test + - lowrisc:dv:pwrmgr_sva + - lowrisc:dv:pwrmgr_unit_only_sva + files: + - tb.sv + - cov/pwrmgr_cov_bind.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson new file mode 100644 index 0000000000000..9cf18c834892a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson @@ -0,0 +1,161 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: pwrmgr + + // Top level dut name (sv module). + dut: pwrmgr + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:dv:pwrmgr_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/pwrmgr_testplan.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"] + + // Exclusion files + vcs_cov_excl_files: ["{self_dir}/cov/pwrmgr_cov_manual_excl.el"] + + // Overrides + overrides: [ + { + name: design_level + value: "top" + } + // Handle generated coverage exclusion. + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {dv_root}/tools/vcs/cover.cfg+{dv_root}/tools/vcs/common_cov_excl.cfg+{self_dir}/cov/pwrmgr_tgl_excl.cfg" + } + ] + + // Add additional tops for simulation. + sim_tops: ["pwrmgr_bind", + "pwrmgr_cov_bind", + "pwrmgr_unit_only_bind", + "sec_cm_prim_count_bind", + "sec_cm_prim_sparse_fsm_flop_bind", + "sec_cm_prim_onehot_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Default UVM test and seq class name. + uvm_test: pwrmgr_base_test + uvm_test_seq: pwrmgr_base_vseq + + // Enable cdc instrumentation. + run_opts: ["+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: pwrmgr_smoke + uvm_test_seq: pwrmgr_smoke_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_reset + uvm_test_seq: pwrmgr_reset_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_lowpower_wakeup_race + uvm_test_seq: pwrmgr_lowpower_wakeup_race_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_wakeup + uvm_test_seq: pwrmgr_wakeup_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_wakeup_reset + uvm_test_seq: pwrmgr_wakeup_reset_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_aborted_low_power + uvm_test_seq: pwrmgr_aborted_low_power_vseq + } + { + name: pwrmgr_sec_cm_lc_ctrl_intersig_mubi + uvm_test_seq: pwrmgr_repeat_wakeup_reset_vseq + run_opts: ["+test_timeout_ns=3000000", "+pwrmgr_mubi_mode=PwrmgrMubiLcCtrl"] + } + { + name: pwrmgr_sec_cm_rom_ctrl_intersig_mubi + uvm_test_seq: pwrmgr_repeat_wakeup_reset_vseq + run_opts: ["+test_timeout_ns=4000000", "+pwrmgr_mubi_mode=PwrmgrMubiRomCtrl"] + } + { + name: pwrmgr_sec_cm_rstmgr_intersig_mubi + uvm_test_seq: pwrmgr_sw_reset_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_esc_clk_rst_malfunc + uvm_test_seq: pwrmgr_esc_clk_rst_malfunc_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_sec_cm_ctrl_config_regwen + uvm_test_seq: pwrmgr_sec_cm_ctrl_config_regwen_vseq + run_opts: ["+test_timeout_ns=50000000"] + } + { + name: pwrmgr_global_esc + uvm_test_seq: pwrmgr_global_esc_vseq + run_opts: ["+test_timeout_ns=1000000000"] + } + { + name: pwrmgr_escalation_timeout + uvm_test_seq: pwrmgr_escalation_timeout_vseq + } + { + name: pwrmgr_glitch + uvm_test_seq: pwrmgr_glitch_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_disable_rom_integrity_check + uvm_test_seq: pwrmgr_disable_rom_integrity_check_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_reset_invalid + uvm_test_seq: pwrmgr_reset_invalid_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_lowpower_invalid + uvm_test_seq: pwrmgr_lowpower_invalid_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["pwrmgr_smoke"] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv new file mode 100644 index 0000000000000..7dcc0b676a44c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv @@ -0,0 +1,145 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has some assertions that check the inputs from ast react according to +// the pwrmgr outputs. The ast inputs are generated by the base sequences, but +// these assertions will also be useful at full chip level. +interface pwrmgr_ast_sva_if #( + parameter bit CheckClocks = 1'b0 +) ( + input logic clk_slow_i, + input logic rst_slow_ni, + input logic clk_main_i, + input logic clk_io_i, + input logic clk_usb_i, + input logic por_d0_ni, + // The pwrmgr outputs. + input pwrmgr_pkg::pwr_ast_req_t pwr_ast_o, + // The pwrmgr inputs. + input pwrmgr_pkg::pwr_ast_rsp_t pwr_ast_i +); + + // These numbers of cycles are meant to match both the randomization in + // pwrmgr_base_vseq, and the actual cycle counts from full chip. + // Notice the expectation for full chip is that deassertion of *clk_val + // takes 0 cycles, and assertion takes a 2 cycle synchronizer delay on + // the slow clock; deassertion of main_pok takes one cycle, and assertion + // not more than 2 cycles. + localparam int MinClkWaitCycles = 0; + localparam int MinPdnWaitCycles = 0; + localparam int MaxClkWaitCycles = 60; + localparam int MaxPdnWaitCycles = 110; + + bit disable_sva; + bit reset_or_disable; + + always_comb reset_or_disable = !rst_slow_ni || disable_sva; + + `define CLK_WAIT_BOUNDS ##[MinClkWaitCycles:MaxClkWaitCycles] + `define PDN_WAIT_BOUNDS ##[MinPdnWaitCycles:MaxPdnWaitCycles] + + // Clock enable-valid. + + // Changes triggered by por_d0_ni only affect clk_val. + `ASSERT(CoreClkGlitchToValOff_A, $fell(por_d0_ni) |-> ##[0:1] !pwr_ast_i.core_clk_val, clk_slow_i, + reset_or_disable) + `ASSERT(CoreClkGlitchToValOn_A, + $rose(por_d0_ni) && pwr_ast_o.core_clk_en |-> ##[0:2] pwr_ast_i.core_clk_val, clk_slow_i, + reset_or_disable) + `ASSERT(IoClkGlitchToValOff_A, $fell(por_d0_ni) |-> ##[0:1] !pwr_ast_i.io_clk_val, clk_slow_i, + reset_or_disable) + `ASSERT(IoClkGlitchToValOn_A, + $rose(por_d0_ni) && pwr_ast_o.io_clk_en |-> ##[0:2] pwr_ast_i.io_clk_val, clk_slow_i, + reset_or_disable) + `ASSERT(UsbClkGlitchToValOff_A, $fell(por_d0_ni) |-> ##[0:5] !pwr_ast_i.usb_clk_val, clk_slow_i, + reset_or_disable) + `ASSERT(UsbClkGlitchToValOn_A, + $rose(por_d0_ni) && pwr_ast_o.usb_clk_en |-> ##[0:5] pwr_ast_i.usb_clk_val, clk_slow_i, + reset_or_disable) + + // Changes not triggered by por_d0_ni + `ASSERT(CoreClkHandshakeOn_A, + $rose(pwr_ast_o.core_clk_en) && por_d0_ni |-> `CLK_WAIT_BOUNDS + pwr_ast_i.core_clk_val || !por_d0_ni, clk_slow_i, reset_or_disable) + `ASSERT(CoreClkHandshakeOff_A, + $fell(pwr_ast_o.core_clk_en) |-> `CLK_WAIT_BOUNDS !pwr_ast_i.core_clk_val, clk_slow_i, + reset_or_disable) + + `ASSERT(IoClkHandshakeOn_A, + $rose(pwr_ast_o.io_clk_en) && por_d0_ni |-> `CLK_WAIT_BOUNDS + pwr_ast_i.io_clk_val || !por_d0_ni, clk_slow_i, reset_or_disable) + `ASSERT(IoClkHandshakeOff_A, + $fell(pwr_ast_o.io_clk_en) |-> `CLK_WAIT_BOUNDS !pwr_ast_i.io_clk_val, clk_slow_i, + reset_or_disable) + + // Usb is a bit different: apparently usb_clk_val can stay low after a power glitch, so it may + // already be low when usb_clk_en drops. + `ASSERT(UsbClkHandshakeOn_A, + $rose(pwr_ast_o.usb_clk_en) && por_d0_ni && $past(por_d0_ni, 1) |-> `CLK_WAIT_BOUNDS + pwr_ast_i.usb_clk_val || !por_d0_ni, clk_slow_i, reset_or_disable) + `ASSERT(UsbClkHandshakeOff_A, + $fell(pwr_ast_o.usb_clk_en) |-> `CLK_WAIT_BOUNDS !pwr_ast_i.usb_clk_val, clk_slow_i, + reset_or_disable) + + if (CheckClocks) begin : gen_check_clock + int main_clk_cycles, io_clk_cycles, usb_clk_cycles; + always_ff @(posedge clk_main_i) main_clk_cycles++; + always_ff @(posedge clk_io_i) io_clk_cycles++; + always_ff @(posedge clk_usb_i) usb_clk_cycles++; + + `ASSERT(MainClkStopped_A, + $fell( + pwr_ast_i.core_clk_val + ) |=> ($stable( + main_clk_cycles + ) || pwr_ast_i.core_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + `ASSERT(MainClkRun_A, + $rose( + pwr_ast_i.core_clk_val + ) |=> (!$stable( + main_clk_cycles + ) || !pwr_ast_i.core_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + + `ASSERT(IOClkStopped_A, + $fell( + pwr_ast_i.io_clk_val + ) |=> ($stable( + io_clk_cycles + ) || pwr_ast_i.io_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + `ASSERT(IOClkRun_A, + $rose( + pwr_ast_i.io_clk_val + ) |=> (!$stable( + io_clk_cycles + ) || !pwr_ast_i.io_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + + `ASSERT(USBClkStopped_A, + $fell( + pwr_ast_i.usb_clk_val + ) |=> ($stable( + usb_clk_cycles + ) || pwr_ast_i.usb_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + `ASSERT(USBClkRun_A, + $rose( + pwr_ast_i.usb_clk_val + ) |=> (!$stable( + usb_clk_cycles + ) || !pwr_ast_i.usb_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + end + + // Main pd-pok + `ASSERT(MainPdHandshakeOn_A, pwr_ast_o.main_pd_n |-> `PDN_WAIT_BOUNDS pwr_ast_i.main_pok, + clk_slow_i, reset_or_disable) + `ASSERT(MainPdHandshakeOff_A, !pwr_ast_o.main_pd_n |-> `PDN_WAIT_BOUNDS !pwr_ast_i.main_pok, + clk_slow_i, reset_or_disable) + + `undef CLK_WAIT_BOUNDS + `undef PDN_WAIT_BOUNDS +endinterface diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv new file mode 100644 index 0000000000000..1e37f68d4185b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv @@ -0,0 +1,86 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module pwrmgr_bind; +`ifndef GATE_LEVEL + bind pwrmgr tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); + + // In top-level testbench, do not bind the csr_assert_fpv to reduce simulation time. +`ifndef TOP_LEVEL_DV + bind pwrmgr pwrmgr_csr_assert_fpv pwrmgr_csr_assert (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); +`endif + + // Clock control assertions. + bind pwrmgr pwrmgr_clock_enables_sva_if pwrmgr_clock_enables_sva_if ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .fast_state(u_fsm.state_q), + .slow_state(u_slow_fsm.state_q), + // The synchronized control CSR bits. + .main_pd_ni(slow_main_pd_n), + .core_clk_en_i(slow_core_clk_en), + .io_clk_en_i(slow_io_clk_en), + .usb_clk_en_lp_i(slow_usb_clk_en_lp), + .usb_clk_en_active_i(slow_usb_clk_en_active), + .usb_ip_clk_status_i(usb_ip_clk_status), + // The main power control. + .main_pd_n(pwr_ast_o.main_pd_n), + // The output enables. + .core_clk_en(pwr_ast_o.core_clk_en), + .io_clk_en(pwr_ast_o.io_clk_en), + .usb_clk_en(pwr_ast_o.usb_clk_en) + ); + + bind pwrmgr clkmgr_pwrmgr_sva_if #(.IS_USB(0)) clkmgr_pwrmgr_io_sva_if ( + .clk_i, + .rst_ni, + .clk_en(pwr_clk_o.io_ip_clk_en), + .status(pwr_clk_i.io_status) + ); + + bind pwrmgr clkmgr_pwrmgr_sva_if #(.IS_USB(0)) clkmgr_pwrmgr_main_sva_if ( + .clk_i, + .rst_ni, + .clk_en(pwr_clk_o.main_ip_clk_en), + .status(pwr_clk_i.main_status) + ); + + bind pwrmgr clkmgr_pwrmgr_sva_if #(.IS_USB(1)) clkmgr_pwrmgr_usb_sva_if ( + .clk_i, + .rst_ni, + .clk_en(pwr_clk_o.usb_ip_clk_en), + .status(pwr_clk_i.usb_status) + ); + + bind pwrmgr pwrmgr_sec_cm_checker_assert pwrmgr_sec_cm_checker_assert ( + .clk_i, + .rst_ni, + .clk_lc_i, + .rst_lc_ni, + .clk_esc_i, + .rst_esc_ni, + .clk_slow_i, + .rst_slow_ni, + .rst_main_ni, + .io_clk_en(pwr_clk_o.io_ip_clk_en), + .pwr_rst_o, + .esc_timeout(esc_timeout_lc_q), + .slow_esc_rst_req(slow_peri_reqs.rstreqs[3]), + .slow_mp_rst_req(slow_peri_reqs.rstreqs[2]), + .slow_fsm_invalid, + .fast_fsm_invalid(u_fsm.u_state_regs.unused_err_o), + .rom_intg_chk_dis(u_fsm.rom_intg_chk_dis), + .rom_intg_chk_done(u_fsm.rom_intg_chk_done), + .rom_intg_chk_good(u_fsm.rom_intg_chk_good), + .fast_state(u_fsm.state_q), + .lc_dft_en_i(u_fsm.lc_dft_en_i), + .lc_hw_debug_en_i(u_fsm.lc_hw_debug_en_i), + .main_pd_ni(u_slow_fsm.main_pd_ni), + .rom_ctrl_done_i(u_fsm.rom_ctrl_done_i), + .rom_ctrl_good_i(u_fsm.rom_ctrl_good_i) + ); +`endif +endmodule diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv new file mode 100644 index 0000000000000..355b52cef9492 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv @@ -0,0 +1,59 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has some assertions that check that the output clock enables correspond +// to the control CSR when transitioning into or out of the active state. In +// addition, the usb clock can change anytime when in the active state. +interface pwrmgr_clock_enables_sva_if ( + input logic clk_i, + input logic rst_ni, + input pwrmgr_pkg::fast_pwr_state_e fast_state, + input pwrmgr_pkg::slow_pwr_state_e slow_state, + // The synchronized control CSR bits. + input logic main_pd_ni, + input logic io_clk_en_i, + input logic core_clk_en_i, + input logic usb_clk_en_lp_i, + input logic usb_clk_en_active_i, + input logic usb_ip_clk_status_i, + // The output enables. + input logic main_pd_n, + input logic io_clk_en, + input logic core_clk_en, + input logic usb_clk_en +); + + bit disable_sva; + bit reset_or_disable; + + always_comb reset_or_disable = !rst_ni || disable_sva; + + sequence transitionUp_S; slow_state == pwrmgr_pkg::SlowPwrStateReqPwrUp; endsequence + + sequence transitionDown_S; slow_state == pwrmgr_pkg::SlowPwrStatePwrClampOn; endsequence + + bit fast_is_active; + always_comb fast_is_active = fast_state == pwrmgr_pkg::FastPwrStateActive; + + // This allows the usb enable to be slower since it also depends on usb clk_status. + sequence usbActiveTransition_S; + ##[0:7] !fast_is_active || usb_clk_en == (usb_clk_en_active_i | usb_ip_clk_status_i); + endsequence + + `ASSERT(CoreClkPwrUp_A, transitionUp_S |=> core_clk_en == 1'b1, clk_i, reset_or_disable) + `ASSERT(IoClkPwrUp_A, transitionUp_S |=> io_clk_en == 1'b1, clk_i, reset_or_disable) + `ASSERT(UsbClkPwrUp_A, transitionUp_S |=> usb_clk_en == usb_clk_en_active_i, clk_i, + reset_or_disable) + + // This deals with transitions while the fast fsm is active. + `ASSERT(UsbClkActive_A, fast_is_active && $changed(usb_clk_en_active_i) |=> usbActiveTransition_S, + clk_i, reset_or_disable) + + `ASSERT(CoreClkPwrDown_A, transitionDown_S |=> core_clk_en == (core_clk_en_i && main_pd_ni), + clk_i, reset_or_disable) + `ASSERT(IoClkPwrDown_A, transitionDown_S |=> io_clk_en == (io_clk_en_i && main_pd_ni), clk_i, + reset_or_disable) + `ASSERT(UsbClkPwrDown_A, transitionDown_S |=> usb_clk_en == (usb_clk_en_lp_i && main_pd_ni), + clk_i, reset_or_disable) +endinterface diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core new file mode 100644 index 0000000000000..9083269e2af6e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:pwrmgr_rstmgr_sva_if:0.1" +description: "PWRMGR to RSTMGR assertion interface." +filesets: + files_dv: + depend: + - lowrisc:ip_interfaces:pwrmgr_pkg + - lowrisc:prim:assert + files: + - pwrmgr_rstmgr_sva_if.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv new file mode 100644 index 0000000000000..d7a9eb153f0f8 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has some assertions that check the inputs from rstmgr react according to +// the pwrmgr outputs. The rstmgr inputs are generated by the base sequences, but +// these assertions will also be useful at full chip level. +interface pwrmgr_rstmgr_sva_if + import pwrmgr_pkg::*, pwrmgr_reg_pkg::*; +( + input logic clk_i, + input logic rst_ni, + input logic clk_slow_i, + input logic rst_slow_ni, + + // The inputs from pwrmgr. + input logic [PowerDomains-1:0] rst_lc_req, + input logic [PowerDomains-1:0] rst_sys_req, + + // The inputs from rstmgr. + input logic [PowerDomains-1:0] rst_lc_src_n, + input logic [PowerDomains-1:0] rst_sys_src_n +); + + // Number of cycles for the LC/SYS reset handshake. + localparam int MinLcSysCycles = 0; + localparam int MaxLcSysCycles = 150; + `define LC_SYS_CYCLES ##[MinLcSysCycles:MaxLcSysCycles] + + bit disable_sva; + bit reset_or_disable; + + always_comb reset_or_disable = !rst_slow_ni || disable_sva; + + // Lc and Sys handshake: pwrmgr rst_*_req causes rstmgr rst_*_src_n + for (genvar pd = 0; pd < PowerDomains; ++pd) begin : gen_assertions_per_power_domains + `ASSERT(LcHandshakeOn_A, rst_lc_req[pd] |-> `LC_SYS_CYCLES !rst_lc_req[pd] || !rst_lc_src_n[pd], + clk_i, reset_or_disable) + `ASSERT(LcHandshakeOff_A, $fell(rst_lc_req[pd]) + |-> `LC_SYS_CYCLES rst_lc_req[pd] || rst_lc_src_n[pd], clk_i, reset_or_disable) + `ASSERT(SysHandshakeOn_A, + rst_sys_req[pd] |-> `LC_SYS_CYCLES !rst_sys_req[pd] || !rst_sys_src_n[pd], clk_i, + reset_or_disable) + `ASSERT(SysHandshakeOff_A, + !rst_sys_req[pd] |-> `LC_SYS_CYCLES rst_sys_req[pd] || rst_sys_src_n[pd], clk_i, + reset_or_disable) + end : gen_assertions_per_power_domains + `undef LC_SYS_CYCLES +endinterface diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstreqs_sva_if.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstreqs_sva_if.sv new file mode 100644 index 0000000000000..47d32756ee5cf --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstreqs_sva_if.sv @@ -0,0 +1,102 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has some assertions that check the pwrmgr rstreqs and reset_cause output is set per the +// reset requests the pwrmgr receives or generates. +interface pwrmgr_rstreqs_sva_if + import pwrmgr_pkg::*, pwrmgr_reg_pkg::*; +( + input logic clk_i, + input logic rst_ni, + input logic clk_slow_i, + input logic rst_slow_ni, + + // Input causes resets. + input logic [ NumRstReqs-1:0] rstreqs_i, + input logic [ NumRstReqs-1:0] reset_en, + input logic sw_rst_req_i, + input logic main_rst_req_i, + input logic esc_rst_req_i, + input logic ndm_rst_req_i, + // outputs + input logic main_pd_n, + input reset_cause_e reset_cause, + input logic [HwResetWidth-1:0] rstreqs +); + + // output reset cycle with a clk enable disable + localparam int MinMainRstCycles = 0; + localparam int MaxMainRstCycles = 400; + `define MAIN_RST_CYCLES ##[MinMainRstCycles:MaxMainRstCycles] + + // The timing of the escalation reset is determined by the slow clock, but will not propagate if + // the non-slow clock is off. We use the regular clock and multiply the clock cycles times the + // clock ratio. + localparam int FastToSlowFreqRatio = 120; + + localparam int MinEscRstCycles = 0; + localparam int MaxEscRstCycles = 4 * FastToSlowFreqRatio; + `define ESC_RST_CYCLES ##[MinEscRstCycles:MaxEscRstCycles] + + bit disable_sva; + bit reset_or_disable; + + always_comb reset_or_disable = !rst_ni || !rst_slow_ni || disable_sva; + + // Reset ins to outs. + for (genvar rst = 0; rst < NumRstReqs; ++rst) begin : gen_hw_resets + `ASSERT(HwResetOn_A, + $rose( + rstreqs_i[rst] && reset_en[rst] + ) |-> `MAIN_RST_CYCLES rstreqs[rst] && reset_cause == HwReq, clk_slow_i, + reset_or_disable) + `ASSERT(HwResetOff_A, + $fell( + rstreqs_i[rst] && reset_en[rst] + ) |-> `MAIN_RST_CYCLES !rstreqs[rst] && reset_cause != HwReq, clk_slow_i, + reset_or_disable) + end + + // This is used to ignore main_rst_req_i (wired to rst_main_n) if it happens during low power, + // since as part of deep sleep rst_main_n will trigger and not because of a power glitch. + logic rst_main_n_ignored_for_main_pwr_rst; + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + rst_main_n_ignored_for_main_pwr_rst <= 0; + end else if (!main_pd_n && reset_cause == LowPwrEntry) begin + rst_main_n_ignored_for_main_pwr_rst <= 1; + end else if (reset_cause != LowPwrEntry) begin + rst_main_n_ignored_for_main_pwr_rst <= 0; + end + end + + `ASSERT(MainPwrRstOn_A, + $rose( + main_rst_req_i && !rst_main_n_ignored_for_main_pwr_rst + ) |-> `MAIN_RST_CYCLES rstreqs[ResetMainPwrIdx], clk_slow_i, + reset_or_disable) + `ASSERT(MainPwrRstOff_A, + $fell( + main_rst_req_i + ) |-> `MAIN_RST_CYCLES !rstreqs[ResetMainPwrIdx], clk_slow_i, + reset_or_disable) + + // Signals in EscRstOn_A and EscRstOff_A are sampled with slow and fast clock. + // Since fast clock can be gated, use fast clock to evaluate cycle delay + // to avoid spurious failure. + `ASSERT(EscRstOn_A, + $rose( + esc_rst_req_i + ) |-> `ESC_RST_CYCLES rstreqs[ResetEscIdx], clk_i, reset_or_disable) + `ASSERT(EscRstOff_A, + $fell( + esc_rst_req_i + ) |-> `ESC_RST_CYCLES !rstreqs[ResetEscIdx], clk_i, reset_or_disable) + + // Software initiated resets do not affect rstreqs since rstmgr generates them. + `ASSERT(SwResetSetCause_A, + $rose(sw_rst_req_i) |-> MAIN_RST_CYCLES (reset_cause == HwReq), clk_i, + reset_or_disable) + +endinterface diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_sec_cm_checker_assert.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_sec_cm_checker_assert.sv new file mode 100644 index 0000000000000..69e868ec7f15d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_sec_cm_checker_assert.sv @@ -0,0 +1,165 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has a number of assertions to check security countermeasures. They are +// individually described in their comments. +module pwrmgr_sec_cm_checker_assert + import pwrmgr_reg_pkg::*; +( + input clk_i, + input rst_ni, + input clk_lc_i, + input rst_lc_ni, + input clk_esc_i, + input rst_esc_ni, + input rst_main_ni, + input clk_slow_i, + input rst_slow_ni, + input logic io_clk_en, + input pwrmgr_pkg::pwr_rst_req_t pwr_rst_o, + input slow_fsm_invalid, + input fast_fsm_invalid, + input prim_mubi_pkg::mubi4_t rom_intg_chk_dis, + input prim_mubi_pkg::mubi4_t rom_intg_chk_done, + input prim_mubi_pkg::mubi4_t rom_intg_chk_good, + input pwrmgr_pkg::fast_pwr_state_e fast_state, + input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + input esc_timeout, + input slow_esc_rst_req, + input slow_mp_rst_req, + input main_pd_ni, + input prim_mubi_pkg::mubi4_t rom_ctrl_done_i, + input prim_mubi_pkg::mubi4_t rom_ctrl_good_i +); + + bit disable_sva; + bit reset_or_disable; + bit esc_reset_or_disable; + bit slow_reset_or_disable; + + always_comb reset_or_disable = !rst_ni || disable_sva; + always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva; + always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva; + + // rom_intg_chk_dis only allows two states. + // Note that lc_dft_en_i and lc_hw_debug_en_i are already synchronized to clk_i at this + // hierarchy level. + // Check that rom integrity checks are disabled when lc_dft_en_i and lc_hw_debug_en_i are active. + `ASSERT(RomIntgChkDisTrue_A, + rom_intg_chk_dis == prim_mubi_pkg::MuBi4True |-> + (lc_dft_en_i == lc_ctrl_pkg::On && + lc_hw_debug_en_i == lc_ctrl_pkg::On), + clk_i, + reset_or_disable) + + // Check that rom integrity checks are enabled when either lc_dft_en_i or lc_hw_debug_en_i are + // inactive. + `ASSERT(RomIntgChkDisFalse_A, + rom_intg_chk_dis == prim_mubi_pkg::MuBi4False |-> + (lc_dft_en_i !== lc_ctrl_pkg::On || + lc_hw_debug_en_i !== lc_ctrl_pkg::On), + clk_i, + reset_or_disable) + + // For any assertions involving state transitions, also allow cases where the fsm + // transitions to an invalid state, since we inject invalid encodings at random. + + // Check that unless rom_intg_chk_done is mubi true the fast state machine will + // stay in FastPwrStateRomCheckDone or transition to Invalid. + `ASSERT(RomBlockCheckGoodState_A, + rom_intg_chk_done != prim_mubi_pkg::MuBi4True && + fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone |=> + fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone || + fast_state == pwrmgr_pkg::FastPwrStateInvalid, + clk_i, + reset_or_disable) + + // Check that when rom_intg_chk_done is mubi true the fast state machine will transition + // from FastPwrStateRomCheckDone to either FastPwrStateRomCheckGood or Invalid. + `ASSERT(RomAllowCheckGoodState_A, + rom_intg_chk_done == prim_mubi_pkg::MuBi4True && + fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone |=> + fast_state == pwrmgr_pkg::FastPwrStateRomCheckGood || + fast_state == pwrmgr_pkg::FastPwrStateInvalid, + clk_i, + reset_or_disable) + + // Check that unless rom_intg_chk_good is mubi true or rom_intg_chk_dis is mubi true + // the fast state machine will stay in FastPwrStateRomCheckGood. + `ASSERT(RomBlockActiveState_A, + rom_intg_chk_good != prim_mubi_pkg::MuBi4True && + rom_intg_chk_dis != prim_mubi_pkg::MuBi4True && + fast_state == pwrmgr_pkg::FastPwrStateRomCheckGood |=> + fast_state == pwrmgr_pkg::FastPwrStateRomCheckGood || + fast_state == pwrmgr_pkg::FastPwrStateInvalid, + clk_i, + reset_or_disable) + + // Check that when one of rom_intg_chk_good or rom_intg_chk_dis is mubi true the fast + // state machine will transition from FastPwrStateRomCheckGood to FastPwrStateActive + // or Invalid. + `ASSERT(RomAllowActiveState_A, + (rom_intg_chk_good == prim_mubi_pkg::MuBi4True || + rom_intg_chk_dis == prim_mubi_pkg::MuBi4True) && + fast_state == pwrmgr_pkg::FastPwrStateRomCheckGood |=> + fast_state == pwrmgr_pkg::FastPwrStateActive || + fast_state == pwrmgr_pkg::FastPwrStateInvalid, + clk_i, + reset_or_disable) + + // For testpoints sec_cm_esc_rx_clk_bkgn_chk, sec_cm_esc_rx_clk_local_esc. + // If the escalation clock (clk_esc_i) stops for too many cycles and is not + // disabled, an escalation timeout should be requested until rst_lc_ni goes + // active. + // The bound of cycles is 128 cycles for the counter, 8 cycles maximum for the + // counter to engage, and 2 cycles for a synchronizer. Use negedge of clk_i + // to sample clk_esc_i as 1 when active, and 0 when inactive. + `ASSERT(EscClkStopEscTimeout_A, !clk_esc_i && io_clk_en [* (128 + 8 + 2)] |=> + esc_timeout || !rst_lc_ni, !clk_i, reset_or_disable) + + // For testpoints sec_cm_esc_rx_clk_bkgn_chk, sec_cm_esc_rx_clk_local_esc. + // Escalation timeout should not be requested when rst_nc_ni is active. + `ASSERT(EscTimeoutStoppedByClReset_A, + !rst_lc_ni |-> !esc_timeout, clk_i, reset_or_disable) + + // For testpoints sec_cm_esc_rx_clk_bkgn_chk, sec_cm_esc_rx_clk_local_esc. + // If escalation timeout is detected a reset request will be generated. + `ASSERT(EscTimeoutTriggersReset_A, esc_timeout |=> ##[1:3] slow_esc_rst_req, + clk_slow_i, !rst_slow_ni || disable_sva) + + // pwr_rst_o.rstreqs checker + // For testpoints sec_cm_esc_rx_clk_bkgn_chk, sec_cm_esc_rx_clk_local_esc. + // If a slow clock domain escalation reset is requested, rstreqs[ResetEscIdx] + // should be asserted after some cycles unless rst_lc_n becomes active. + `ASSERT(RstreqChkEsctimeout_A, + $rose( + slow_esc_rst_req + ) ##1 slow_esc_rst_req |-> ##[0:10] pwr_rst_o.rstreqs[ResetEscIdx] || !rst_lc_ni, + clk_i, reset_or_disable) + + // For testpoint sec_cm_fsm_terminal. + // If slow_fsm or fast_fsm is invalid, both pwr_rst_o.rst_lc_req and + // pwr_rst_o.rst_sys_req should be set. + `ASSERT(RstreqChkFsmterm_A, + $rose(slow_fsm_invalid) || $rose(fast_fsm_invalid) + |-> ##[0:10] $rose(pwr_rst_o.rst_lc_req & pwr_rst_o.rst_sys_req), + clk_i, reset_or_disable) + + // For testpoint sec_cm_ctrl_flow_global_esc. + // If a slow clock domain escalation reset request is set, the output escalation + // reset pwr_rst_o.rstreqs[ResetEscIdx] should be asserted after some cycles. + `ASSERT(RstreqChkGlbesc_A, + $rose(slow_esc_rst_req) ##1 slow_esc_rst_req |-> + ##[0:10] (pwr_rst_o.rstreqs[ResetEscIdx] | !rst_esc_ni), + clk_i, reset_or_disable) + + // For testpoint sec_cm_main_pd_rst_local_esc. + // If power is up and rst_main_ni goes low, pwr_rst_o.rstreqs[ResetMainPwrIdx] + // should be asserted. + `ASSERT(RstreqChkMainpd_A, + slow_mp_rst_req |-> ##[0:5] pwr_rst_o.rstreqs[ResetMainPwrIdx], clk_i, + reset_or_disable) + +endmodule : pwrmgr_sec_cm_checker_assert diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core new file mode 100644 index 0000000000000..b5fbadc0ce5d4 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core @@ -0,0 +1,43 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:pwrmgr_sva:0.1" +description: "PWRMGR assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + - lowrisc:ip_interfaces:pwrmgr_pkg + - lowrisc:dv:clkmgr_pwrmgr_sva_if + - lowrisc:dv:pwrmgr_rstmgr_sva_if + files: + - pwrmgr_bind.sv + - pwrmgr_clock_enables_sva_if.sv + - pwrmgr_rstreqs_sva_if.sv + - pwrmgr_sec_cm_checker_assert.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:ip_interfaces:pwrmgr + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/pwrmgr.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: pwrmgr diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_bind.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_bind.sv new file mode 100644 index 0000000000000..e33bda19f5bd0 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_bind.sv @@ -0,0 +1,21 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This binds assertions that should not be bound at chip level. +module pwrmgr_unit_only_bind; + + bind pwrmgr pwrmgr_rstmgr_sva_if pwrmgr_rstmgr_sva_if ( + .clk_i, + .rst_ni, + .clk_slow_i, + .rst_slow_ni, + // The outputs from pwrmgr. + .rst_lc_req(pwr_rst_o.rst_lc_req), + .rst_sys_req(pwr_rst_o.rst_sys_req), + // The inputs from rstmgr. + .rst_lc_src_n(pwr_rst_i.rst_lc_src_n), + .rst_sys_src_n(pwr_rst_i.rst_sys_src_n) + ); + +endmodule : pwrmgr_unit_only_bind diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_sva.core b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_sva.core new file mode 100644 index 0000000000000..9a36b699f3ea1 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_sva.core @@ -0,0 +1,39 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:pwrmgr_unit_only_sva:0.1" +description: "PWRMGR assertion interfaces not suitable for chip level bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + - lowrisc:dv:pwrmgr_rstmgr_sva_if + + files: + - pwrmgr_unit_only_bind.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:ip_interfaces:pwrmgr + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/pwrmgr.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: pwrmgr diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/tb.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/tb.sv new file mode 100644 index 0000000000000..02f5b91526858 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/tb.sv @@ -0,0 +1,143 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import pwrmgr_env_pkg::*; + import pwrmgr_test_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk, rst_n; + wire clk_esc, rst_esc_n; + wire clk_lc, rst_lc_n; + wire clk_slow, rst_slow_n; + wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + wire int_reset_req; + + // interfaces + clk_rst_if clk_rst_if ( + .clk (clk), + .rst_n(rst_n) + ); + clk_rst_if lc_clk_rst_if ( + .clk (clk_lc), + .rst_n(rst_lc_n) + ); + clk_rst_if esc_clk_rst_if ( + .clk (clk_esc), + .rst_n(rst_esc_n) + ); + clk_rst_if slow_clk_rst_if ( + .clk (clk_slow), + .rst_n(rst_slow_n) + ); + pins_if #(NUM_MAX_INTERRUPTS) intr_if (interrupts); + alert_esc_if esc_if ( + .clk (clk), + .rst_n(rst_n) + ); + tl_if tl_if ( + .clk (clk), + .rst_n(rst_n) + ); + + assign interrupts[0] = pwrmgr_if.intr_wakeup; + assign int_reset_req = tb.dut.internal_reset_req; + + pwrmgr_if pwrmgr_if ( + .clk, + .rst_n, + .clk_slow, + .rst_slow_n + ); + + `DV_ALERT_IF_CONNECT(clk_lc, rst_lc_n) + + // dut + pwrmgr dut ( + .clk_i (clk), + .rst_ni (rst_n), + .clk_slow_i (clk_slow), + .rst_slow_ni(rst_slow_n), + .rst_main_ni(pwrmgr_if.rst_main_n), + .clk_lc_i (clk_lc), + .rst_lc_ni (rst_lc_n), + .clk_esc_i (clk_esc), + .rst_esc_ni (rst_esc_n), + + .tl_i(tl_if.h2d), + .tl_o(tl_if.d2h), + + .alert_rx_i(alert_rx), + .alert_tx_o(alert_tx), + + .pwr_ast_i(pwrmgr_if.pwr_ast_rsp), + .pwr_ast_o(pwrmgr_if.pwr_ast_req), + + .pwr_rst_i(pwrmgr_if.pwr_rst_rsp), + .pwr_rst_o(pwrmgr_if.pwr_rst_req), + + .pwr_clk_i(pwrmgr_if.pwr_clk_rsp), + .pwr_clk_o(pwrmgr_if.pwr_clk_req), + + .pwr_otp_i(pwrmgr_if.pwr_otp_rsp), + .pwr_otp_o(pwrmgr_if.pwr_otp_req), + + .pwr_lc_i(pwrmgr_if.pwr_lc_rsp), + .pwr_lc_o(pwrmgr_if.pwr_lc_req), + + .pwr_flash_i(pwrmgr_if.pwr_flash), + .pwr_cpu_i (pwrmgr_if.pwr_cpu), + + .fetch_en_o(pwrmgr_if.fetch_en), + .wakeups_i (pwrmgr_if.wakeups_i), + // TOOD(#22710): properly cooperate with `pwrmgr_if.rstreqs_i[1]` + .rstreqs_i ({int_reset_req, pwrmgr_if.rstreqs_i[0]}), + .ndmreset_req_i(pwrmgr_if.cpu_i.ndmreset_req), + + .lc_dft_en_i (pwrmgr_if.lc_dft_en), + .lc_hw_debug_en_i(pwrmgr_if.lc_hw_debug_en), + + .strap_o (pwrmgr_if.strap), + .low_power_o(pwrmgr_if.low_power), + + .rom_ctrl_i(pwrmgr_if.rom_ctrl), + + .sw_rst_req_i(pwrmgr_if.sw_rst_req_i), + + .esc_rst_tx_i(esc_if.esc_tx), + .esc_rst_rx_o(esc_if.esc_rx), + + .intr_wakeup_o(pwrmgr_if.intr_wakeup) + ); + + initial begin + // drive clk and rst_n from clk_if + clk_rst_if.set_active(); + esc_clk_rst_if.set_active(); + lc_clk_rst_if.set_active(); + slow_clk_rst_if.set_active(); + + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "esc_clk_rst_vif", esc_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "lc_clk_rst_vif", lc_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "slow_clk_rst_vif", slow_clk_rst_if); + uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + uvm_config_db#(virtual alert_esc_if)::set(null, "*.env.m_esc_agent*", "vif", esc_if); + uvm_config_db#(virtual pwrmgr_if)::set(null, "*.env", "pwrmgr_vif", pwrmgr_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); + uvm_config_db#(virtual pwrmgr_clock_enables_sva_if)::set( + null, "*.env", "pwrmgr_clock_enables_sva_vif", dut.pwrmgr_clock_enables_sva_if); + uvm_config_db#(virtual pwrmgr_rstmgr_sva_if)::set(null, "*.env", "pwrmgr_rstmgr_sva_vif", + dut.pwrmgr_rstmgr_sva_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end // initial begin + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/tests/pwrmgr_base_test.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/tests/pwrmgr_base_test.sv new file mode 100644 index 0000000000000..0432cfc12b3e7 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/tests/pwrmgr_base_test.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_base_test extends cip_base_test #( + .CFG_T(pwrmgr_env_cfg), + .ENV_T(pwrmgr_env) +); + + `uvm_component_utils(pwrmgr_base_test) + `uvm_component_new + + // the base class dv_base_test creates the following instances: + // pwrmgr_env_cfg: cfg + // pwrmgr_env: env + + // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in + // the run_phase; as such, nothing more needs to be done + +endclass : pwrmgr_base_test diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/tests/pwrmgr_test.core b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/tests/pwrmgr_test.core new file mode 100644 index 0000000000000..bf79e44e66ced --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/tests/pwrmgr_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:pwrmgr_test:0.1" +description: "PWRMGR DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:dv:pwrmgr_env + files: + - pwrmgr_test_pkg.sv + - pwrmgr_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/dv/tests/pwrmgr_test_pkg.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/tests/pwrmgr_test_pkg.sv new file mode 100644 index 0000000000000..afbd194155618 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/dv/tests/pwrmgr_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package pwrmgr_test_pkg; + // dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import pwrmgr_env_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // local types + + // functions + + // package sources + `include "pwrmgr_base_test.sv" + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/lint/pwrmgr.vlt b/hw/top_darjeeling/ip_autogen/pwrmgr/lint/pwrmgr.vlt new file mode 100644 index 0000000000000..a38de163cf134 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/lint/pwrmgr.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for Power Manager diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/lint/pwrmgr.waiver b/hw/top_darjeeling/ip_autogen/pwrmgr/lint/pwrmgr.waiver new file mode 100644 index 0000000000000..75aee6c3c1161 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/lint/pwrmgr.waiver @@ -0,0 +1,5 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for Power Manager diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/lint/pwrmgr_pkg.vlt b/hw/top_darjeeling/ip_autogen/pwrmgr/lint/pwrmgr_pkg.vlt new file mode 100644 index 0000000000000..a5949a211be74 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/lint/pwrmgr_pkg.vlt @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for the pwrmgr_pkg + +`verilator_config + +// Waive the SYMRSVDWORD warning in pwrmgr_reg_pkg: we have a field in +// the WAKE_INFO register called "abort", which means pwrmgr_reg_pkg +// defines a struct with that name, clashing with a C++ reserved word. +lint_off -rule SYMRSVDWORD -file "*/pwrmgr_reg_pkg.sv" -match "*common word: 'abort'" diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core new file mode 100644 index 0000000000000..4534fd5287a52 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core @@ -0,0 +1,66 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_pwrmgr:0.1 +description: "Power manager RTL" +virtual: + - lowrisc:ip_interfaces:pwrmgr + +filesets: + files_rtl: + depend: + - lowrisc:opentitan:top_darjeeling_pwrmgr_pkg:0.1 + - lowrisc:opentitan:top_darjeeling_pwrmgr_reg:0.1 + - lowrisc:ip:pwrmgr_component + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: pwrmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_components.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_components.core new file mode 100644 index 0000000000000..bf144fe1c9b5d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_components.core @@ -0,0 +1,80 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:ip:pwrmgr_component:0.1" +description: "Power manager RTL" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:esc + - lowrisc:prim:lc_sync + - lowrisc:prim:lc_sender + - lowrisc:prim:all + - lowrisc:ip:rom_ctrl_pkg + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:prim:sparse_fsm + - lowrisc:prim:mubi + - lowrisc:prim:clock_buf + - lowrisc:prim:measure + - lowrisc:ip_interfaces:alert_handler_reg + - lowrisc:ip_interfaces:pwrmgr_pkg + files: + - rtl/pwrmgr_cdc.sv + - rtl/pwrmgr_slow_fsm.sv + - rtl/pwrmgr_fsm.sv + - rtl/pwrmgr_wake_info.sv + - rtl/pwrmgr.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: pwrmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_pkg.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_pkg.core new file mode 100644 index 0000000000000..997acbf90f737 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_pkg.core @@ -0,0 +1,32 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_pwrmgr_pkg:0.1 +description: "Power manager package" +virtual: + - lowrisc:ip_interfaces:pwrmgr_pkg + +filesets: + files_rtl: + depend: + - lowrisc:opentitan:top_darjeeling_pwrmgr_reg + - lowrisc:ip:rom_ctrl_pkg + files: + - rtl/pwrmgr_pkg.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr_pkg.vlt + file_type: vlt + +targets: + default: + filesets: + - tool_verilator ? (files_verilator_waiver) + - files_rtl diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_reg.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_reg.core new file mode 100644 index 0000000000000..4734a823dc51e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_reg.core @@ -0,0 +1,24 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_pwrmgr_reg:0.1 +description: "Power manager registers" +virtual: + - lowrisc:ip_interfaces:pwrmgr_reg + +filesets: + files_rtl: + depend: + - lowrisc:tlul:headers + - lowrisc:ip:tlul + - lowrisc:prim:subreg + files: + - rtl/pwrmgr_reg_pkg.sv + - rtl/pwrmgr_reg_top.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr.sv new file mode 100644 index 0000000000000..6c0fc377a6e6f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr.sv @@ -0,0 +1,771 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager +// + +`include "prim_assert.sv" + +module pwrmgr + import pwrmgr_pkg::*; + import pwrmgr_reg_pkg::*; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}} +) ( + // Clocks and resets + input clk_slow_i, + input clk_i, + input rst_slow_ni, + input rst_ni, + input rst_main_ni, + input clk_lc_i, + input rst_lc_ni, + input clk_esc_i, + input rst_esc_ni, + + // Bus Interface + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + // AST interface + input pwr_ast_rsp_t pwr_ast_i, + output pwr_ast_req_t pwr_ast_o, + + // rstmgr interface + input pwr_rst_rsp_t pwr_rst_i, + output pwr_rst_req_t pwr_rst_o, + + // clkmgr interface + output pwr_clk_req_t pwr_clk_o, + input pwr_clk_rsp_t pwr_clk_i, + + // otp interface + input pwr_otp_rsp_t pwr_otp_i, + output pwr_otp_req_t pwr_otp_o, + + // life cycle interface + input pwr_lc_rsp_t pwr_lc_i, + output pwr_lc_req_t pwr_lc_o, + + // flash interface + input pwr_flash_t pwr_flash_i, + + // processor interface + input pwr_cpu_t pwr_cpu_i, + // SEC_CM: LC_CTRL.INTERSIG.MUBI + output lc_ctrl_pkg::lc_tx_t fetch_en_o, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, + output pwr_boot_status_t boot_status_o, + // peripherals wakeup and reset requests + input [NumWkups-1:0] wakeups_i, + input [NumRstReqs-1:0] rstreqs_i, + + // cpu related inputs + input ndmreset_req_i, + + // pinmux and other peripherals + output logic strap_o, + output logic low_power_o, + + // rom_ctrl interface + // SEC_CM: ROM_CTRL.INTERSIG.MUBI + input rom_ctrl_pkg::pwrmgr_data_t rom_ctrl_i, + + // software issued reset request + // SEC_CM: RSTMGR.INTERSIG.MUBI + input prim_mubi_pkg::mubi4_t sw_rst_req_i, + + // escalation interface + input prim_esc_pkg::esc_tx_t esc_rst_tx_i, + output prim_esc_pkg::esc_rx_t esc_rst_rx_o, + + output intr_wakeup_o + +); + //////////////////////////////////////////////////// + // Input handling // + //////////////////////////////////////////////////// + + logic ndmreset_req_q; + logic ndm_req_valid; + + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_ndm_sync ( + .clk_i, + .rst_ni, + .d_i(ndmreset_req_i), + .q_o(ndmreset_req_q) + ); + + assign ndm_req_valid = ndmreset_req_q; + + //////////////////////////// + /// escalation detections + //////////////////////////// + + logic clk_lc; + logic rst_lc_n; + assign clk_lc = clk_lc_i; + assign rst_lc_n = rst_lc_ni; + + logic clk_esc; + logic rst_esc_n; + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_esc_clk_buf ( + .clk_i(clk_esc_i), + .clk_o(clk_esc) + ); + + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_esc_rst_buf ( + .clk_i(rst_esc_ni), + .clk_o(rst_esc_n) + ); + + logic esc_rst_req_d, esc_rst_req_q; + prim_esc_receiver #( + .N_ESC_SEV (alert_handler_reg_pkg::N_ESC_SEV), + .PING_CNT_DW (alert_handler_reg_pkg::PING_CNT_DW) + ) u_esc_rx ( + .clk_i(clk_esc), + .rst_ni(rst_esc_n), + .esc_req_o(esc_rst_req_d), + .esc_rx_o(esc_rst_rx_o), + .esc_tx_i(esc_rst_tx_i) + ); + + // These assertions use formal or simulation to prove that once esc_rst_req is latched, we expect + // to see the lc reset requests in pwr_rst_o. The one exception is when escalation requests are + // cancelled while the CPU fetch is disabled, meaning the fast fsm is inactive. +`ifdef SIMULATION + // In simulation mode, the prim_cdc_rand_delay module inserts a random one cycle delay to the + // two flop synchronizers. There are two CDCs in the path from escalation reset to the fast fsm + // receiving it, one to the slow clock, and one back to the fast one. And there are additional + // cycles in the fast fsm to generate outputs. However, esc_rst_req_q can be dropped due to + // rst_lc_n, which will cause slow_peri_reqs_masked.rstreqs[ResetEscIdx] to drop. + `ASSERT(PwrmgrSecCmEscToSlowResetReq_A, + esc_rst_req_q |-> ##[1:5] !esc_rst_req_q || slow_peri_reqs_masked.rstreqs[ResetEscIdx], + clk_slow_i, !rst_slow_ni) + `ASSERT(PwrmgrSecCmFsmEscToResetReq_A, + slow_peri_reqs_masked.rstreqs[ResetEscIdx] |-> + ##[1:4] !slow_peri_reqs_masked.rstreqs[ResetEscIdx] || u_fsm.reset_reqs_i[ResetEscIdx], + clk_i, !rst_ni) +`else + `ASSERT(PwrmgrSecCmEscToSlowResetReq_A, + esc_rst_req_d |-> ##[2:3] ( + (!esc_rst_req_d && lc_ctrl_pkg::lc_tx_test_false_loose(fetch_en_o)) || + slow_peri_reqs_masked.rstreqs[ResetEscIdx] + ), clk_slow_i, !rst_slow_ni) + `ASSERT(PwrmgrSlowResetReqToFsmResetReq_A, + slow_peri_reqs_masked.rstreqs[ResetEscIdx] |-> ##1 u_fsm.reset_reqs_i[ResetEscIdx], + clk_i, !rst_ni) +`endif + + `ASSERT(PwrmgrSecCmEscToLCReset_A, u_fsm.reset_reqs_i[ResetEscIdx] && + u_fsm.state_q == FastPwrStateActive |-> ##4 pwr_rst_o.rst_lc_req == 2'b11, + clk_i, !rst_ni) + + always_ff @(posedge clk_lc or negedge rst_lc_n) begin + if (!rst_lc_n) begin + esc_rst_req_q <= '0; + end else if (esc_rst_req_d) begin + // once latched, do not clear until reset + esc_rst_req_q <= 1'b1; + end + end + + localparam int EscTimeOutCnt = 128; + logic esc_timeout, esc_timeout_lc_d, esc_timeout_lc_q; + // SEC_CM: ESC_RX.CLK.BKGN_CHK, ESC_RX.CLK.LOCAL_ESC + prim_clock_timeout #( + .TimeOutCnt(EscTimeOutCnt) + ) u_esc_timeout ( + .clk_chk_i(clk_esc), + .rst_chk_ni(rst_esc_n), + .clk_i, + .rst_ni, + // if any ip clock enable is turned on, then the escalation + // clocks are also enabled. + .en_i(|pwr_clk_o), + .timeout_o(esc_timeout) + ); + + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_esc_timeout_sync ( + .clk_i(clk_lc), + .rst_ni(rst_lc_n), + .d_i(esc_timeout), + .q_o(esc_timeout_lc_d) + ); + + always_ff @(posedge clk_lc or negedge rst_lc_n) begin + if (!rst_lc_n) begin + esc_timeout_lc_q <= '0; + end else if (esc_timeout_lc_d) begin + // once latched, do not clear until reset + esc_timeout_lc_q <= 1'b1; + end + end + + + //////////////////////////// + /// async declarations + //////////////////////////// + pwr_peri_t peri_reqs_raw; + logic slow_rst_req; + + assign peri_reqs_raw.wakeups = wakeups_i; + assign peri_reqs_raw.rstreqs[NumRstReqs-1:0] = rstreqs_i; + assign peri_reqs_raw.rstreqs[ResetMainPwrIdx] = slow_rst_req; + // SEC_CM: ESC_RX.CLK.LOCAL_ESC, CTRL_FLOW.GLOBAL_ESC + assign peri_reqs_raw.rstreqs[ResetEscIdx] = esc_rst_req_q | esc_timeout_lc_q; + assign peri_reqs_raw.rstreqs[ResetNdmIdx] = ndm_req_valid; + + //////////////////////////// + /// Software reset request + //////////////////////////// + logic sw_rst_req; + prim_buf #( + .Width(1) + ) u_sw_req_buf ( + .in_i(prim_mubi_pkg::mubi4_test_true_strict(sw_rst_req_i)), + .out_o(sw_rst_req) + ); + + assign peri_reqs_raw.rstreqs[ResetSwReqIdx] = sw_rst_req; + + //////////////////////////// + /// clk_i domain declarations + //////////////////////////// + + pwrmgr_reg2hw_t reg2hw; + pwrmgr_hw2reg_t hw2reg; + pwr_peri_t peri_reqs_masked; + + logic req_pwrup; + logic ack_pwrup; + logic req_pwrdn; + logic ack_pwrdn; + logic fsm_invalid; + logic clr_slow_req; + logic usb_ip_clk_en; + logic usb_ip_clk_status; + pwrup_cause_e pwrup_cause; + + logic low_power_fall_through; + logic low_power_abort; + + pwr_flash_t flash_rsp; + pwr_otp_rsp_t otp_rsp; + + prim_mubi_pkg::mubi4_t rom_ctrl_done; + prim_mubi_pkg::mubi4_t rom_ctrl_good; + + logic core_sleeping; + logic low_power_entry; + + //////////////////////////// + /// clk_slow_i domain declarations + //////////////////////////// + + // Captured signals + // These signals, though on clk_i domain, are safe for clk_slow_i to use + logic [NumWkups-1:0] slow_wakeup_en; + logic [NumRstReqs-1:0] slow_reset_en; + + pwr_ast_rsp_t slow_ast; + pwr_peri_t slow_peri_reqs, slow_peri_reqs_masked; + + pwrup_cause_e slow_pwrup_cause; + logic slow_pwrup_cause_toggle; + logic slow_req_pwrup; + logic slow_ack_pwrup; + logic slow_req_pwrdn; + logic slow_ack_pwrdn; + logic slow_fsm_invalid; + logic slow_main_pd_n; + logic slow_io_clk_en; + logic slow_core_clk_en; + logic slow_usb_clk_en_lp; + logic slow_usb_clk_en_active; + logic slow_clr_req; + logic slow_usb_ip_clk_en; + logic slow_usb_ip_clk_status; + + + + //////////////////////////// + /// Register module + //////////////////////////// + logic [NumAlerts-1:0] alert_test, alerts; + logic low_power_hint; + logic lowpwr_cfg_wen; + logic clr_hint; + logic wkup; + logic clr_cfg_lock; + logic reg_intg_err; + + // SEC_CM: BUS.INTEGRITY + // SEC_CM: CTRL.CONFIG.REGWEN, WAKEUP.CONFIG.REGWEN, RESET.CONFIG.REGWEN + pwrmgr_reg_top u_reg ( + .clk_i, + .rst_ni, + .clk_lc_i (clk_lc ), + .rst_lc_ni (rst_lc_n), + .tl_i, + .tl_o, + .reg2hw, + .hw2reg, + .intg_err_o (reg_intg_err) + ); + + // whenever low power entry begins, wipe the hint + assign hw2reg.control.low_power_hint.d = 1'b0; + assign hw2reg.control.low_power_hint.de = clr_hint; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + lowpwr_cfg_wen <= 1'b1; + end else if (!lowpwr_cfg_wen && (clr_cfg_lock || wkup)) begin + lowpwr_cfg_wen <= 1'b1; + end else if (low_power_entry) begin + lowpwr_cfg_wen <= 1'b0; + end + end + + assign hw2reg.ctrl_cfg_regwen.d = lowpwr_cfg_wen; + + assign hw2reg.fault_status.reg_intg_err.de = reg_intg_err; + assign hw2reg.fault_status.reg_intg_err.d = 1'b1; + assign hw2reg.fault_status.esc_timeout.de = esc_timeout_lc_q; + assign hw2reg.fault_status.esc_timeout.d = 1'b1; + + // The main power domain glitch automatically causes a reset, so regsitering + // an alert is functionally pointless. However, if an attacker somehow manages/ + // to silence the reset, this gives us one potential back-up path through alert_handler. + // Allow capture of main_pd fault status whenever the system is live. + assign hw2reg.fault_status.main_pd_glitch.de = pwr_clk_o.main_ip_clk_en; + assign hw2reg.fault_status.main_pd_glitch.d = peri_reqs_masked.rstreqs[ResetMainPwrIdx] | + reg2hw.fault_status.main_pd_glitch.q; + + `ASSERT(GlitchStatusPersist_A, $rose(reg2hw.fault_status.main_pd_glitch.q) |-> + reg2hw.fault_status.main_pd_glitch.q until !rst_lc_ni) + + //////////////////////////// + /// alerts + //////////////////////////// + + // the logic below assumes there is only one alert, so make an + // explicit assertion check for it. + `ASSERT_INIT(AlertNumCheck_A, NumAlerts == 1) + + assign alert_test = { + reg2hw.alert_test.q & + reg2hw.alert_test.qe + }; + + assign alerts[0] = reg2hw.fault_status.reg_intg_err.q | + reg2hw.fault_status.esc_timeout.q | + reg2hw.fault_status.main_pd_glitch.q; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .IsFatal(1'b1) + ) u_prim_alert_sender ( + .clk_i ( clk_lc ), + .rst_ni ( rst_lc_n ), + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[i] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + //////////////////////////// + /// cdc handling + //////////////////////////// + + pwrmgr_cdc u_cdc ( + .clk_i, + .rst_ni, + .clk_slow_i, + .rst_slow_ni, + + // slow domain signals + .slow_req_pwrup_i(slow_req_pwrup), + .slow_ack_pwrdn_i(slow_ack_pwrdn), + .slow_fsm_invalid_i(slow_fsm_invalid), + .slow_pwrup_cause_toggle_i(slow_pwrup_cause_toggle), + .slow_pwrup_cause_i(slow_pwrup_cause), + .slow_wakeup_en_o(slow_wakeup_en), + .slow_reset_en_o(slow_reset_en), + .slow_main_pd_no(slow_main_pd_n), + .slow_io_clk_en_o(slow_io_clk_en), + .slow_core_clk_en_o(slow_core_clk_en), + .slow_usb_clk_en_lp_o(slow_usb_clk_en_lp), + .slow_usb_clk_en_active_o(slow_usb_clk_en_active), + .slow_req_pwrdn_o(slow_req_pwrdn), + .slow_ack_pwrup_o(slow_ack_pwrup), + .slow_ast_o(slow_ast), + .slow_peri_reqs_o(slow_peri_reqs), + .slow_peri_reqs_masked_i(slow_peri_reqs_masked), + .slow_clr_req_o(slow_clr_req), + .slow_usb_ip_clk_en_i(slow_usb_ip_clk_en), + .slow_usb_ip_clk_status_o(slow_usb_ip_clk_status), + + // fast domain signals + .req_pwrdn_i(req_pwrdn), + .ack_pwrup_i(ack_pwrup), + .cfg_cdc_sync_i(reg2hw.cfg_cdc_sync.qe & reg2hw.cfg_cdc_sync.q), + .cdc_sync_done_o(hw2reg.cfg_cdc_sync.de), + .wakeup_en_i(reg2hw.wakeup_en), + .reset_en_i(reg2hw.reset_en), + .main_pd_ni(reg2hw.control.main_pd_n.q), + .io_clk_en_i(reg2hw.control.io_clk_en.q), + .core_clk_en_i(reg2hw.control.core_clk_en.q), + .usb_clk_en_lp_i(reg2hw.control.usb_clk_en_lp.q), + .usb_clk_en_active_i(reg2hw.control.usb_clk_en_active.q), + .ack_pwrdn_o(ack_pwrdn), + .fsm_invalid_o(fsm_invalid), + .req_pwrup_o(req_pwrup), + .pwrup_cause_o(pwrup_cause), + .peri_reqs_o(peri_reqs_masked), + .clr_slow_req_i(clr_slow_req), + .usb_ip_clk_en_o(usb_ip_clk_en), + .usb_ip_clk_status_i(usb_ip_clk_status), + + // AST signals + .ast_i(pwr_ast_i), + + // peripheral signals + .peri_i(peri_reqs_raw), + + // flash handshake + .flash_i(pwr_flash_i), + .flash_o(flash_rsp), + + // OTP signals + .otp_i(pwr_otp_i), + .otp_o(otp_rsp), + + // rom_ctrl signals + .rom_ctrl_done_i(rom_ctrl_i.done), + .rom_ctrl_done_o(rom_ctrl_done), + + // core sleeping + .core_sleeping_i(pwr_cpu_i.core_sleeping), + .core_sleeping_o(core_sleeping) + + ); + // rom_ctrl_i.good is not synchronized as it acts as a "payload" signal + // to "done". Good is only observed if "done" is high. + assign rom_ctrl_good = rom_ctrl_i.good; + assign hw2reg.cfg_cdc_sync.d = 1'b0; + + //////////////////////////// + /// Wakup and reset capture + //////////////////////////// + + // reset and wakeup requests are captured into the slow clock domain and then + // fanned out to other domains as necessary. This ensures there is not a huge + // time gap between when the slow clk domain sees the signal vs when the fast + // clock domains see it. This creates redundant syncing but keeps the time + // scale approximately the same across all domains. + // + // This also implies that these signals must be at least 1 clk_slow pulse long + // + // Since resets are not latched inside pwrmgr, there exists a corner case where + // non-always-on reset requests may get wiped out by a graceful low power entry + // It's not clear if this is really an issue at the moment, but something to keep + // in mind if future changes are needed. + // + // Latching the reset requests is not difficult, but the bigger question is who + // should clear it and when that should happen. If the clearing does not work + // correctly, it is possible for the device to end up in a permanent reset loop, + // and that would be very undesirable. + + assign slow_peri_reqs_masked.wakeups = slow_peri_reqs.wakeups & slow_wakeup_en; + // msb is software request + // the internal requests include escalation and internal requests + // the lsbs are the software enabled peripheral requests. + assign slow_peri_reqs_masked.rstreqs = slow_peri_reqs.rstreqs & + {{NumSwRstReq{1'b1}}, + {NumDebugRstReqs{1'b1}}, + {NumIntRstReqs{1'b1}}, + slow_reset_en}; + // TODO(#22711): Make this work also when `rstreqs` is structured differently. + logic strap_sampled; + logic internal_reset_req; + logic ext_reset_req; + + assign internal_reset_req =|( + slow_peri_reqs.rstreqs & + {{NumSwRstReq{1'b1}}, // SW driven reset + {NumDebugRstReqs{1'b1}}, // debugger reset + {NumIntRstReqs{1'b1}}, // {ESC reset, slow_fsm} + // exclude the external async reset + {1'b0, slow_reset_en[0]} + } + ); + + // The MSB of `slow_peri_reqs.rstreqs` is the external reset request. We want it to always + // propagate, in order to continue from the Reset Wait state in the fast FSM. + assign ext_reset_req = slow_peri_reqs.rstreqs[NumRstReqs-1]; + + for (genvar i = 0; i < NumWkups; i++) begin : gen_wakeup_status + assign hw2reg.wake_status[i].de = 1'b1; + assign hw2reg.wake_status[i].d = peri_reqs_masked.wakeups[i]; + end + + for (genvar i = 0; i < NumRstReqs; i++) begin : gen_reset_status + assign hw2reg.reset_status[i].de = 1'b1; + assign hw2reg.reset_status[i].d = peri_reqs_masked.rstreqs[i]; + end + + assign hw2reg.escalate_reset_status.de = 1'b1; + assign hw2reg.escalate_reset_status.d = peri_reqs_masked.rstreqs[NumRstReqs]; + + + //////////////////////////// + /// clk_slow FSM + //////////////////////////// + + pwrmgr_slow_fsm u_slow_fsm ( + .clk_i (clk_slow_i), + .rst_ni (rst_slow_ni), + .rst_main_ni (rst_main_ni), + .wakeup_i (|slow_peri_reqs_masked.wakeups), + .reset_req_i (|slow_peri_reqs_masked.rstreqs), + .ast_i (slow_ast), + .req_pwrup_o (slow_req_pwrup), + .pwrup_cause_o (slow_pwrup_cause), + .pwrup_cause_toggle_o (slow_pwrup_cause_toggle), + .ack_pwrup_i (slow_ack_pwrup), + .req_pwrdn_i (slow_req_pwrdn), + .ack_pwrdn_o (slow_ack_pwrdn), + .rst_req_o (slow_rst_req), + .fsm_invalid_o (slow_fsm_invalid), + .clr_req_i (slow_clr_req), + .usb_ip_clk_en_o (slow_usb_ip_clk_en), + .usb_ip_clk_status_i (slow_usb_ip_clk_status), + + .main_pd_ni (slow_main_pd_n), + .io_clk_en_i (slow_io_clk_en), + .core_clk_en_i (slow_core_clk_en), + .usb_clk_en_lp_i (slow_usb_clk_en_lp), + .usb_clk_en_active_i (slow_usb_clk_en_active), + + // outputs to AST - These are on the slow clock domain + // TBD - need to check this with partners + .ast_o (pwr_ast_o) + ); + + lc_ctrl_pkg::lc_tx_t lc_dft_en; + prim_lc_sync u_prim_lc_sync_dft_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_dft_en_i), + .lc_en_o({lc_dft_en}) + ); + + lc_ctrl_pkg::lc_tx_t lc_hw_debug_en; + prim_lc_sync u_prim_lc_sync_hw_debug_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_hw_debug_en_i), + .lc_en_o({lc_hw_debug_en}) + ); + + //////////////////////////// + /// clk FSM + //////////////////////////// + + assign low_power_hint = reg2hw.control.low_power_hint.q == LowPower; + assign low_power_entry = core_sleeping & low_power_hint; + + pwrmgr_fsm u_fsm ( + .clk_i, + .rst_ni, + .clk_slow_i, + .rst_slow_ni, + + // interface with slow_fsm + .req_pwrup_i (req_pwrup), + .pwrup_cause_i (pwrup_cause), // por, wake or reset request + .ack_pwrup_o (ack_pwrup), + .req_pwrdn_o (req_pwrdn), + .ack_pwrdn_i (ack_pwrdn), + .low_power_entry_i (low_power_entry), + .reset_reqs_i (peri_reqs_masked.rstreqs), + .fsm_invalid_i (fsm_invalid), + .clr_slow_req_o (clr_slow_req), + .usb_ip_clk_en_i (usb_ip_clk_en), + .usb_ip_clk_status_o (usb_ip_clk_status), + + // cfg + .main_pd_ni (reg2hw.control.main_pd_n.q), + + // consumed in pwrmgr + .wkup_o (wkup), + .clr_cfg_lock_o (clr_cfg_lock), + .fall_through_o (low_power_fall_through), + .abort_o (low_power_abort), + .clr_hint_o (clr_hint), + .int_reset_req_i (internal_reset_req), + .ext_reset_req_i (ext_reset_req), + + // rstmgr + .pwr_rst_o (pwr_rst_o), + .pwr_rst_i (pwr_rst_i), + + // clkmgr + .ips_clk_en_o (pwr_clk_o), + .clk_en_status_i (pwr_clk_i), + + // otp + .otp_init_o (pwr_otp_o.otp_init), + .otp_done_i (otp_rsp.otp_done), + .otp_idle_i (otp_rsp.otp_idle), + + // lc + .lc_init_o (pwr_lc_o.lc_init), + .lc_done_i (pwr_lc_i.lc_done), + .lc_idle_i (pwr_lc_i.lc_idle), + .lc_dft_en_i (lc_dft_en), + .lc_hw_debug_en_i (lc_hw_debug_en), + + // flash + .flash_idle_i (flash_rsp.flash_idle), + + // rom_ctrl + .rom_ctrl_done_i (rom_ctrl_done), + .rom_ctrl_good_i (rom_ctrl_good), + + // processing element + .fetch_en_o, + + // pinmux and other peripherals + .strap_o, + .strap_sampled_o (strap_sampled), // to debug monitoring logic + .low_power_o + ); + + //////////////////////////// + /// Wakeup Info Capture + //////////////////////////// + + logic wake_info_wen; + logic [TotalWakeWidth-1:0] wake_info_data; + + assign wake_info_wen = reg2hw.wake_info.abort.qe | + reg2hw.wake_info.fall_through.qe | + reg2hw.wake_info.reasons.qe; + + assign wake_info_data = {reg2hw.wake_info.abort.q, + reg2hw.wake_info.fall_through.q, + reg2hw.wake_info.reasons.q}; + + pwrmgr_wake_info i_wake_info ( + .clk_i, + .rst_ni, + .wr_i (wake_info_wen), + .data_i (wake_info_data), + .start_capture_i (low_power_o), + .record_dis_i (reg2hw.wake_info_capture_dis.q), + .wakeups_i (peri_reqs_masked.wakeups), + .fall_through_i (low_power_fall_through), + .abort_i (low_power_abort), + .info_o (hw2reg.wake_info) + ); + + //////////////////////////// + /// Interrupts + //////////////////////////// + + // This interrupt is asserted whenever the fast FSM transitions + // into active state. However, it does not assert during POR + prim_intr_hw #(.Width(1)) intr_wakeup ( + .clk_i, + .rst_ni, + .event_intr_i (wkup), + .reg2hw_intr_enable_q_i (reg2hw.intr_enable.q), + .reg2hw_intr_test_q_i (reg2hw.intr_test.q), + .reg2hw_intr_test_qe_i (reg2hw.intr_test.qe), + .reg2hw_intr_state_q_i (reg2hw.intr_state.q), + .hw2reg_intr_state_de_o (hw2reg.intr_state.de), + .hw2reg_intr_state_d_o (hw2reg.intr_state.d), + .intr_o (intr_wakeup_o) + ); + + //////////////////////////////////////////////////// + // Routing status signal outputs for monitoring + //////////////////////////////////////////////////// + assign boot_status_o.cpu_fetch_en = fetch_en_o; + assign boot_status_o.rom_ctrl_status = rom_ctrl_i; + assign boot_status_o.lc_done = pwr_lc_i.lc_done; + assign boot_status_o.otp_done = otp_rsp.otp_done; + assign boot_status_o.clk_status = pwr_clk_i; + assign boot_status_o.light_reset_req = internal_reset_req; + assign boot_status_o.strap_sampled = strap_sampled; + + //////////////////////////// + /// Assertions + //////////////////////////// + + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid ) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready ) + `ASSERT_KNOWN(AlertsKnownO_A, alert_tx_o ) + `ASSERT_KNOWN(AstKnownO_A, pwr_ast_o ) + `ASSERT_KNOWN(RstKnownO_A, pwr_rst_o ) + `ASSERT_KNOWN(ClkKnownO_A, pwr_clk_o ) + `ASSERT_KNOWN(OtpKnownO_A, pwr_otp_o ) + `ASSERT_KNOWN(LcKnownO_A, pwr_lc_o ) + `ASSERT_KNOWN(IntrKnownO_A, intr_wakeup_o ) + + // EscTimeOutCnt also sets the required clock ratios between escalator and local clock + // Ie, clk_lc cannot be so slow that the timeout count is reached + `ifdef INC_ASSERT + //VCS coverage off + // pragma coverage off + logic effective_rst_n; + assign effective_rst_n = clk_lc_i && rst_ni; + + logic [31:0] cnt; + always_ff @(posedge clk_i or negedge effective_rst_n) begin + if (!effective_rst_n) begin + cnt <= '0; + end else begin + cnt <= cnt + 1'b1; + end + end + //VCS coverage on + // pragma coverage on + + `ASSERT(ClkRatio_A, cnt < EscTimeOutCnt) + + `endif + + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(FsmCheck_A, u_fsm.u_state_regs, + pwr_rst_o.rst_lc_req && pwr_rst_o.rst_sys_req) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(SlowFsmCheck_A, u_slow_fsm.u_state_regs, + pwr_ast_o.pwr_clamp && !pwr_ast_o.main_pd_n, 0, 2, + clk_slow_i, !rst_slow_ni) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0]) +endmodule // pwrmgr diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_cdc.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_cdc.sv new file mode 100644 index 0000000000000..90e7b6916c1a9 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_cdc.sv @@ -0,0 +1,333 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager CDC handling +// + +`include "prim_assert.sv" + +module pwrmgr_cdc import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*; +( + // Clocks and resets + input clk_slow_i, + input clk_i, + input rst_slow_ni, + input rst_ni, + + // slow domain signals, + input slow_req_pwrup_i, + input slow_ack_pwrdn_i, + input slow_fsm_invalid_i, + input slow_pwrup_cause_toggle_i, + input pwrup_cause_e slow_pwrup_cause_i, + output logic [NumWkups-1:0] slow_wakeup_en_o, + output logic [NumRstReqs-1:0] slow_reset_en_o, + output logic slow_main_pd_no, + output logic slow_io_clk_en_o, + output logic slow_core_clk_en_o, + output logic slow_usb_clk_en_lp_o, + output logic slow_usb_clk_en_active_o, + output logic slow_req_pwrdn_o, + output logic slow_ack_pwrup_o, + output pwr_ast_rsp_t slow_ast_o, + output pwr_peri_t slow_peri_reqs_o, + input pwr_peri_t slow_peri_reqs_masked_i, + output logic slow_clr_req_o, + input slow_usb_ip_clk_en_i, + output slow_usb_ip_clk_status_o, + + // fast domain signals + input req_pwrdn_i, + input ack_pwrup_i, + input cfg_cdc_sync_i, + input [NumWkups-1:0] wakeup_en_i, + input logic [NumRstReqs-1:0] reset_en_i, + input main_pd_ni, + input io_clk_en_i, + input core_clk_en_i, + input usb_clk_en_lp_i, + input usb_clk_en_active_i, + output logic ack_pwrdn_o, + output logic fsm_invalid_o, + output logic req_pwrup_o, + output pwrup_cause_e pwrup_cause_o, + output pwr_peri_t peri_reqs_o, + output logic cdc_sync_done_o, + input clr_slow_req_i, + output logic usb_ip_clk_en_o, + input usb_ip_clk_status_i, + + // peripheral inputs, mixed domains + input pwr_peri_t peri_i, + input pwr_flash_t flash_i, + output pwr_flash_t flash_o, + + // otp interface + input pwr_otp_rsp_t otp_i, + output pwr_otp_rsp_t otp_o, + + // AST inputs, unknown domain + input pwr_ast_rsp_t ast_i, + + // rom_ctrl signals + input prim_mubi_pkg::mubi4_t rom_ctrl_done_i, + output prim_mubi_pkg::mubi4_t rom_ctrl_done_o, + + // core sleeping + input core_sleeping_i, + output logic core_sleeping_o + +); + + //////////////////////////////// + // Sync from clk_i to clk_slow_i + //////////////////////////////// + + logic slow_cdc_sync; + pwr_ast_rsp_t slow_ast_q, slow_ast_q2; + + prim_flop_2sync # ( + .Width(1) + ) u_req_pwrdn_sync ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .d_i(req_pwrdn_i), + .q_o(slow_req_pwrdn_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_ack_pwrup_sync ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .d_i(ack_pwrup_i), + .q_o(slow_ack_pwrup_o) + ); + + prim_pulse_sync u_slow_cdc_sync ( + .clk_src_i(clk_i), + .rst_src_ni(rst_ni), + .src_pulse_i(cfg_cdc_sync_i), + .clk_dst_i(clk_slow_i), + .rst_dst_ni(rst_slow_ni), + .dst_pulse_o(slow_cdc_sync) + ); + + // Even though this is multi-bit, the bits are individual request lines. + // So there is no general concern about recombining as there is + // no intent to use them in a related manner. + prim_flop_2sync # ( + .Width($bits(pwr_peri_t)) + ) u_slow_ext_req_sync ( + .clk_i (clk_slow_i), + .rst_ni (rst_slow_ni), + .d_i (peri_i), + .q_o (slow_peri_reqs_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_ip_clk_status_sync ( + .clk_i (clk_slow_i), + .rst_ni (rst_slow_ni), + .d_i (usb_ip_clk_status_i), + .q_o (slow_usb_ip_clk_status_o) + ); + + // Some of the AST signals are multi-bits themselves (such as clk_val) + // thus they need to be delayed one more stage to check for stability + prim_flop_2sync # ( + .Width($bits(pwr_ast_rsp_t)), + .ResetValue(PWR_AST_RSP_SYNC_DEFAULT) + ) u_ast_sync ( + .clk_i (clk_slow_i), + .rst_ni (rst_slow_ni), + .d_i (ast_i), + .q_o (slow_ast_q) + ); + + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_ast_q2 <= PWR_AST_RSP_SYNC_DEFAULT; + end else begin + slow_ast_q2 <= slow_ast_q; + end + end + + // if possible, we should simulate below with random delays through + // flop_2sync + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_ast_o <= PWR_AST_RSP_SYNC_DEFAULT; + end else if (slow_ast_q2 == slow_ast_q) begin + // Output only updates whenever sync and delayed outputs both agree. + // If there are delays in sync, this will result in a 1 cycle difference + // and the output will hold the previous value + slow_ast_o <= slow_ast_q2; + end + end + + // only register configurations can be sync'd using slow_cdc_sync + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_wakeup_en_o <= '0; + slow_reset_en_o <= '0; + slow_main_pd_no <= '1; + slow_io_clk_en_o <= '0; + slow_core_clk_en_o <= '0; + slow_usb_clk_en_lp_o <= '0; + slow_usb_clk_en_active_o <= 1'b1; + end else if (slow_cdc_sync) begin + slow_wakeup_en_o <= wakeup_en_i; + slow_reset_en_o <= reset_en_i; + slow_main_pd_no <= main_pd_ni; + slow_io_clk_en_o <= io_clk_en_i; + slow_core_clk_en_o <= core_clk_en_i; + slow_usb_clk_en_lp_o <= usb_clk_en_lp_i; + slow_usb_clk_en_active_o <= usb_clk_en_active_i; + end + end + + //////////////////////////////// + // Sync from clk_slow_i to clk_i + //////////////////////////////// + + logic pwrup_cause_toggle_q, pwrup_cause_toggle_q2; + logic pwrup_cause_chg; + + prim_flop_2sync # ( + .Width(1) + ) u_req_pwrup_sync ( + .clk_i, + .rst_ni, + .d_i(slow_req_pwrup_i), + .q_o(req_pwrup_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_ack_pwrdn_sync ( + .clk_i, + .rst_ni, + .d_i(slow_ack_pwrdn_i), + .q_o(ack_pwrdn_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_int_fsm_invalid_sync ( + .clk_i, + .rst_ni, + .d_i(slow_fsm_invalid_i), + .q_o(fsm_invalid_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_pwrup_chg_sync ( + .clk_i, + .rst_ni, + .d_i(slow_pwrup_cause_toggle_i), + .q_o(pwrup_cause_toggle_q) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_ip_clk_en_sync ( + .clk_i, + .rst_ni, + .d_i(slow_usb_ip_clk_en_i), + .q_o(usb_ip_clk_en_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_sleeping_sync ( + .clk_i, + .rst_ni, + .d_i(core_sleeping_i), + .q_o(core_sleeping_o) + ); + + prim_pulse_sync u_scdc_sync ( + .clk_src_i(clk_slow_i), + .rst_src_ni(rst_slow_ni), + .src_pulse_i(slow_cdc_sync), + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .dst_pulse_o(cdc_sync_done_o) + ); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + pwrup_cause_toggle_q2 <= 1'b0; + end else begin + pwrup_cause_toggle_q2 <= pwrup_cause_toggle_q; + end + end + + assign pwrup_cause_chg = pwrup_cause_toggle_q2 ^ pwrup_cause_toggle_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + pwrup_cause_o <= Por; + end else if (pwrup_cause_chg) begin + pwrup_cause_o <= slow_pwrup_cause_i; + end + end + + prim_flop_2sync #( + .Width($bits(pwr_peri_t)) + ) u_ext_req_sync ( + .clk_i, + .rst_ni, + .d_i(slow_peri_reqs_masked_i), + .q_o(peri_reqs_o) + ); + + prim_flop_2sync #( + .Width(1), + .ResetValue(1'b1) + ) u_sync_flash_idle ( + .clk_i, + .rst_ni, + .d_i(flash_i.flash_idle), + .q_o(flash_o.flash_idle) + ); + + prim_flop_2sync #( + .Width($bits(pwr_otp_rsp_t)), + .ResetValue('0) + ) u_sync_otp ( + .clk_i, + .rst_ni, + .d_i(otp_i), + .q_o(otp_o) + ); + + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(1), + .StabilityCheck(1) + ) u_sync_rom_ctrl ( + .clk_i, + .rst_ni, + .mubi_i(rom_ctrl_done_i), + .mubi_o({rom_ctrl_done_o}) + ); + + //////////////////////////////// + // Handshake + //////////////////////////////// + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_clr_req_sync ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .d_i(clr_slow_req_i), + .q_o(slow_clr_req_o) + ); + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_cdc_pulse.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_cdc_pulse.sv new file mode 100644 index 0000000000000..ad7c501439ef3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_cdc_pulse.sv @@ -0,0 +1,91 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager module to find slow clock edges +// The clock is not used directly to avoid STA issues, instead a toggle +// pulse is used. + +`include "prim_assert.sv" + +module pwrmgr_cdc_pulse ( + input clk_slow_i, + input clk_i, + input rst_ni, + input rst_slow_ni, + input start_i, + input stop_i, + output logic pulse_o +); + + logic slow_toggle_pq, slow_toggle_nq; + logic clk_slow_pq, clk_slow_nq; + logic clk_slow_pq2, clk_slow_nq2; + logic toggle; + logic valid; + + // toggle pulse generated on positive edge + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_toggle_pq <= 1'b0; + end else begin + slow_toggle_pq <= ~slow_toggle_pq; + end + end + + // toggle pulse generated on negative edge + always_ff @(negedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_toggle_nq <= 1'b0; + end else begin + slow_toggle_nq <= ~slow_toggle_nq; + end + end + + + prim_flop_2sync # ( + .Width(1) + ) i_pos_sync ( + .clk_i, + .rst_ni, + .d_i(slow_toggle_pq), + .q_o(clk_slow_pq) + ); + + prim_flop_2sync # ( + .Width(1) + ) i_neg_sync ( + .clk_i, + .rst_ni, + .d_i(slow_toggle_nq), + .q_o(clk_slow_nq) + ); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + clk_slow_pq2 <= 1'b0; + clk_slow_nq2 <= 1'b0; + end else begin + clk_slow_pq2 <= clk_slow_pq; + clk_slow_nq2 <= clk_slow_nq; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + valid <= 1'b0; + end else if (valid && stop_i) begin + valid <= 1'b0; + end else if (!valid && toggle && start_i) begin + valid <= 1'b1; + end + end + + // toggle is found on either positive and negative edges of clk_slow_i + assign toggle = clk_slow_pq2 ^ clk_slow_pq | clk_slow_nq2 ^ clk_slow_nq; + assign pulse_o = valid & toggle; + + + + +endmodule // pwrmgr diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_fsm.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_fsm.sv new file mode 100644 index 0000000000000..e053283b910e6 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_fsm.sv @@ -0,0 +1,575 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager Fast FSM +// + +`include "prim_assert.sv" + +module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( + input clk_i, + input rst_ni, + input clk_slow_i, + input rst_slow_ni, + + // interface with slow_fsm + input req_pwrup_i, + input pwrup_cause_e pwrup_cause_i, + output logic ack_pwrup_o, + output logic req_pwrdn_o, + input ack_pwrdn_i, + input low_power_entry_i, + input main_pd_ni, + input [TotalResetWidth-1:0] reset_reqs_i, + input fsm_invalid_i, + output logic clr_slow_req_o, + input usb_ip_clk_en_i, + output logic usb_ip_clk_status_o, + + // consumed in pwrmgr + output logic wkup_o, // generate wake interrupt + output logic fall_through_o, + output logic abort_o, + output logic clr_hint_o, + output logic clr_cfg_lock_o, + input logic int_reset_req_i, // internally generated reset request. + // Send to platform to assert reset + input logic ext_reset_req_i, // Internal Req held until ext reset deasserts + + // rstmgr + output pwr_rst_req_t pwr_rst_o, + input pwr_rst_rsp_t pwr_rst_i, + + // clkmgr + output pwr_clk_req_t ips_clk_en_o, + input pwr_clk_rsp_t clk_en_status_i, + + // otp + output logic otp_init_o, + input otp_done_i, + input otp_idle_i, + + // lc + output logic lc_init_o, + input lc_done_i, + input lc_idle_i, + input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + + // flash + input flash_idle_i, + + // rom_ctrl + input prim_mubi_pkg::mubi4_t rom_ctrl_done_i, + input prim_mubi_pkg::mubi4_t rom_ctrl_good_i, + + // pinmux + output logic strap_o, + output logic strap_sampled_o, + output logic low_power_o, + + // processing elements + output lc_ctrl_pkg::lc_tx_t fetch_en_o +); + + import prim_mubi_pkg::mubi4_t; + import prim_mubi_pkg::mubi4_test_true_strict; + import prim_mubi_pkg::mubi4_or_hi; + import prim_mubi_pkg::mubi4_and_hi; + import lc_ctrl_pkg::lc_tx_and_hi; + import lc_ctrl_pkg::lc_tx_test_true_strict; + + // The code below always assumes the always on domain is index 0 + `ASSERT_INIT(AlwaysOnIndex_A, ALWAYS_ON_DOMAIN == 0) + + // when there are multiple on domains, the latter 1 should become another parameter + localparam int OffDomainSelStart = ALWAYS_ON_DOMAIN + 1; + + // all powered down domains have resets asserted + logic pd_n_rsts_asserted; + + // all domains have resets asserted + logic all_rsts_asserted; + + // resets are valid + logic reset_valid; + + // reset hint to rstmgr + reset_cause_e reset_cause_q, reset_cause_d; + + // reset request + logic reset_req; + logic direct_rst_req; + logic ndmreset_req; + logic hw_rst_req; + logic sw_rst_req; + + // strap sample should only happen on cold boot or when the + // the system goes through a reset cycle + + // disable processing element fetching + lc_ctrl_pkg::lc_tx_t fetch_en_q, fetch_en_d; + + fast_pwr_state_e state_d, state_q; + logic reset_ongoing_q, reset_ongoing_d; + logic req_pwrdn_q, req_pwrdn_d; + logic ack_pwrup_q, ack_pwrup_d; + logic ip_clk_en_q, ip_clk_en_d; + logic [PowerDomains-1:0] rst_lc_req_q, rst_sys_req_q; + logic [PowerDomains-1:0] rst_lc_req_d, rst_sys_req_d; + logic otp_init; + logic lc_init; + logic low_power_q, low_power_d; + + assign pd_n_rsts_asserted = pwr_rst_i.rst_lc_src_n[PowerDomains-1:OffDomainSelStart] == '0 & + pwr_rst_i.rst_sys_src_n[PowerDomains-1:OffDomainSelStart] == '0; + + logic lc_rsts_valid; + assign lc_rsts_valid = ((rst_lc_req_q & ~pwr_rst_i.rst_lc_src_n) | + (~rst_lc_req_q & pwr_rst_i.rst_lc_src_n)) == {PowerDomains{1'b1}}; + logic sys_rsts_valid; + assign sys_rsts_valid = ((rst_sys_req_q & ~pwr_rst_i.rst_sys_src_n) | + (~rst_sys_req_q & pwr_rst_i.rst_sys_src_n)) == {PowerDomains{1'b1}}; + + assign all_rsts_asserted = lc_rsts_valid & sys_rsts_valid; + + // Any reset request was asserted. + assign reset_req = |reset_reqs_i; + + // Any peripheral triggererd hardware reset request. + assign hw_rst_req = |reset_reqs_i[NumRstReqs-1:0]; + + // Direct reset request that bypass checks. + assign direct_rst_req = reset_reqs_i[ResetEscIdx] | + reset_reqs_i[ResetMainPwrIdx]; + + // Ndm reset request. + assign ndmreset_req = reset_reqs_i[ResetNdmIdx]; + + // Software triggered reset request. + assign sw_rst_req = reset_reqs_i[ResetSwReqIdx]; + + // when in low power path, resets are controlled by domain power down + // when in reset path, all resets must be asserted + // when the reset cause is something else, it is invalid + assign reset_valid = reset_cause_q == LowPwrEntry ? main_pd_ni | pd_n_rsts_asserted : + reset_cause_q == HwReq ? all_rsts_asserted : 1'b0; + + // Provide the ability to control the reset to OpenTitan RoT from an external source. The logic + // below makes sure that when an internal reset request is generated, it is held high until the + // external SoC reset logic asserts and then deasserts deasserts the external reset signal. The + // pwrmgr fast FSM is held in FastPwrStateResetWait state until the external reset deasserts. + // This ensure that the OT reset exit is synchronized with the rest of the SoC & platform. + logic ext_rst_req_d, ext_rst_req_q; + logic ext_rst_pending_d, ext_rst_pending_q; + + always_comb begin + ext_rst_req_d = ext_reset_req_i; + ext_rst_pending_d = ext_rst_pending_q; + + if (ext_rst_pending_q && !ext_rst_req_d && ext_rst_req_q) begin + ext_rst_pending_d = 1'b0; + end else if (int_reset_req_i) begin + ext_rst_pending_d = 1'b1; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + ext_rst_req_q <= 1'b0; + ext_rst_pending_q <= 1'b0; + end else begin + ext_rst_req_q <= ext_rst_req_d; + ext_rst_pending_q <= ext_rst_pending_d; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + ack_pwrup_q <= 1'b0; + req_pwrdn_q <= 1'b0; + reset_ongoing_q <= 1'b0; + ip_clk_en_q <= 1'b0; + rst_lc_req_q <= {PowerDomains{1'b1}}; + rst_sys_req_q <= {PowerDomains{1'b1}}; + reset_cause_q <= ResetUndefined; + low_power_q <= 1'b1; + end else begin + ack_pwrup_q <= ack_pwrup_d; + req_pwrdn_q <= req_pwrdn_d; + reset_ongoing_q <= reset_ongoing_d; + ip_clk_en_q <= ip_clk_en_d; + rst_lc_req_q <= rst_lc_req_d; + rst_sys_req_q <= rst_sys_req_d; + reset_cause_q <= reset_cause_d; + low_power_q <= low_power_d; + end + end + + // SEC_CM: FSM.SPARSE + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, fast_pwr_state_e, FastPwrStateLowPower) + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + strap_sampled_o <= 1'b0; + end else if (&rst_sys_req_q) begin + strap_sampled_o <= 1'b0; + end else if (strap_o) begin + strap_sampled_o <= 1'b1; + end + end + + prim_lc_sender u_fetch_en ( + .clk_i, + .rst_ni, + .lc_en_i(fetch_en_d), + .lc_en_o(fetch_en_q) + ); + assign fetch_en_o = fetch_en_q; + + // Life cycle broadcast may take time to propagate through the system. + // The sync below simulates that behavior using the slowest clock in the + // system. + logic slow_lc_done; + logic lc_done; + + prim_flop_2sync #( + .Width(1) + ) u_slow_sync_lc_done ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .d_i(lc_done_i), + .q_o(slow_lc_done) + ); + + prim_flop_2sync #( + .Width(1) + ) u_sync_lc_done ( + .clk_i, + .rst_ni, + .d_i(slow_lc_done), + .q_o(lc_done) + ); + + + logic clks_enabled; + logic clks_disabled; + + // clocks all enabled computed as follows: + // if enable is high, meaning clock is requested to turn on, the status must + // also be 1. + // if enable is low, meaning clock is not requested to turn on, the status is + // don't care. + // the bit-wise OR of both conditions must be all true. + assign clks_enabled = ip_clk_en_q && + &((ips_clk_en_o & clk_en_status_i) | ~ips_clk_en_o); + + // clocks all disabled is the opposite: + // if enable is low the status must also be low. + // if enable is high, the status is don't care. + // the bit-wise OR of both conditions must be all true. + assign clks_disabled = ~ip_clk_en_q && + &((~ips_clk_en_o & ~clk_en_status_i) | ips_clk_en_o); + + + // rom integrity checks are disabled during TEST / RMA states + // During TEST / RMA states, both dft_en and hw_debug_en are On. + // During DEV / PROD states, either both signals are Off, or only + // hw_debug_en is On + + mubi4_t rom_intg_chk_dis; + assign rom_intg_chk_dis = lc_tx_test_true_strict(lc_tx_and_hi(lc_dft_en_i, lc_hw_debug_en_i)) ? + prim_mubi_pkg::MuBi4True : + prim_mubi_pkg::MuBi4False; + + mubi4_t rom_intg_chk_done; + mubi4_t rom_intg_chk_good; + assign rom_intg_chk_done = mubi4_or_hi(mubi4_and_hi(rom_intg_chk_dis, rom_ctrl_done_i), + rom_ctrl_done_i); + assign rom_intg_chk_good = mubi4_or_hi(rom_intg_chk_dis, rom_ctrl_good_i); + + always_comb begin + otp_init = 1'b0; + lc_init = 1'b0; + wkup_o = 1'b0; + fall_through_o = 1'b0; + abort_o = 1'b0; + clr_hint_o = 1'b0; + clr_cfg_lock_o = 1'b0; + strap_o = 1'b0; + clr_slow_req_o = 1'b0; + + state_d = state_q; + ack_pwrup_d = ack_pwrup_q; + req_pwrdn_d = req_pwrdn_q; + reset_ongoing_d = reset_ongoing_q; + ip_clk_en_d = ip_clk_en_q; + rst_lc_req_d = rst_lc_req_q; + rst_sys_req_d = rst_sys_req_q; + reset_cause_d = reset_cause_q; + low_power_d = low_power_q; + fetch_en_d = fetch_en_q; + + unique case(state_q) + + FastPwrStateLowPower: begin + if (req_pwrup_i || reset_ongoing_q) begin + state_d = FastPwrStateEnableClocks; + end + end + + FastPwrStateEnableClocks: begin + ip_clk_en_d = 1'b1; + if (clks_enabled) begin + state_d = FastPwrStateReleaseLcRst; + end + end + + FastPwrStateReleaseLcRst: begin + rst_lc_req_d = '0; // release rst_lc_n for all power domains + rst_sys_req_d = '0; // release rst_sys_n for all power domains + // once all resets are released continue to otp initialization + if (&pwr_rst_i.rst_lc_src_n) begin + state_d = FastPwrStateOtpInit; + end + end + + FastPwrStateOtpInit: begin + otp_init = 1'b1; + + if (otp_done_i) begin + state_d = FastPwrStateLcInit; + end + end + + FastPwrStateLcInit: begin + lc_init = 1'b1; + + if (lc_done) begin + state_d = FastPwrStateAckPwrUp; + + end + end + + FastPwrStateAckPwrUp: begin + // only ack the slow_fsm if we actually transitioned through it + ack_pwrup_d = !reset_ongoing_q; + + // wait for request power up to drop relative to ack + if (!req_pwrup_i || reset_ongoing_q) begin + ack_pwrup_d = 1'b0; + clr_cfg_lock_o = 1'b1; + // generate a wakeup interrupt if we intended to go to low power + // and we were woken from low power with a wakeup and not reset + wkup_o = (pwrup_cause_i == Wake) & (reset_cause_q == LowPwrEntry); + // This constitutes the end of a reset cycle + reset_ongoing_d = 1'b0; + state_d = FastPwrStateStrap; + end + end + + FastPwrStateStrap: begin + strap_o = ~strap_sampled_o; + state_d = FastPwrStateRomCheckDone; + end + + FastPwrStateRomCheckDone: begin + // zero outgoing low power indication + low_power_d = '0; + reset_cause_d = ResetNone; + + // When done is observed, advance to good check + if (mubi4_test_true_strict(rom_intg_chk_done)) begin + state_d = FastPwrStateRomCheckGood; + end + end + + FastPwrStateRomCheckGood: begin + if (mubi4_test_true_strict(rom_intg_chk_good)) begin + state_d = FastPwrStateActive; + end + end + + FastPwrStateActive: begin + // only in active state, allow processor to execute + fetch_en_d = lc_ctrl_pkg::On; + + // when handling reset request or low power entry of any + // kind, stop processor from fetching + if (reset_req || low_power_entry_i) begin + fetch_en_d = lc_ctrl_pkg::Off; + reset_cause_d = ResetUndefined; + state_d = FastPwrStateDisClks; + end + end + + FastPwrStateDisClks: begin + ip_clk_en_d = 1'b0; + + if (clks_disabled) begin + state_d = reset_req ? FastPwrStateNvmShutDown : FastPwrStateFallThrough; + low_power_d = ~reset_req; + end else begin + // escalation was received, skip all handshaking and directly reset + state_d = direct_rst_req ? FastPwrStateNvmShutDown : state_q; + low_power_d = ~reset_req; + end + end + + // Low Power Path + FastPwrStateFallThrough: begin + clr_hint_o = 1'b1; + + // The processor was interrupted after it asserted WFI and is executing again + if (!low_power_entry_i) begin + ip_clk_en_d = 1'b1; + wkup_o = 1'b1; + fall_through_o = 1'b1; + state_d = FastPwrStateRomCheckDone; + end else begin + state_d = FastPwrStateNvmIdleChk; + end + end + + FastPwrStateNvmIdleChk: begin + + if (otp_idle_i && lc_idle_i && flash_idle_i) begin + state_d = FastPwrStateLowPowerPrep; + end else begin + ip_clk_en_d = 1'b1; + wkup_o = 1'b1; + abort_o = 1'b1; + state_d = FastPwrStateRomCheckDone; + end + end + + FastPwrStateLowPowerPrep: begin + // reset cause is set only if main power domain will be turned off + reset_cause_d = LowPwrEntry; + + // reset non-always-on domains if requested + // this includes the clock manager, which implies pwr/rst managers must + // be fed directly from the source + for (int i = OffDomainSelStart; i < PowerDomains; i++) begin + rst_lc_req_d[i] = ~main_pd_ni; + rst_sys_req_d[i] = ~main_pd_ni; + end + + if (reset_valid) begin + state_d = FastPwrStateReqPwrDn; + end + end + + FastPwrStateReqPwrDn: begin + req_pwrdn_d = 1'b1; + + if (ack_pwrdn_i) begin + req_pwrdn_d = 1'b0; + state_d = FastPwrStateLowPower; + end + end + + // Reset Path + FastPwrStateNvmShutDown: begin + clr_hint_o = 1'b1; + reset_ongoing_d = 1'b1; + state_d = FastPwrStateResetPrep; + end + + FastPwrStateResetPrep: begin + reset_cause_d = HwReq; + rst_lc_req_d = {PowerDomains{1'b1}}; + rst_sys_req_d = {PowerDomains{(hw_rst_req | + direct_rst_req | + sw_rst_req) | + (ndmreset_req & + lc_ctrl_pkg::lc_tx_test_false_loose(lc_hw_debug_en_i))}}; + + + state_d = FastPwrStateResetWait; + end + + FastPwrStateResetWait: begin + rst_lc_req_d = {PowerDomains{1'b1}}; + clr_slow_req_o = reset_reqs_i[ResetMainPwrIdx]; + // The main power reset request is checked here specifically because it is + // the only reset request in the system that operates on the POR domain. + // This has to be the case since it would otherwise not be able to monitor + // the non-always-on domains. + // + // As a result of this, the normal reset process does not automatically + // wipe out the reset request, so we specifically clear it and wait for it to be + // cleared before proceeding. This also implies if the system is under a persistent + // glitch, or if someone just turned off the power before pwrmgr turns it off itself, + // we will stay stuck here and perpetually hold the system in reset. + // Need to hold in reset until external reset deasserts (i.e. ext_rst_pending_q goes low) + if (reset_valid && !reset_reqs_i[ResetMainPwrIdx] && !ext_rst_pending_q) begin + state_d = FastPwrStateLowPower; + end + end + + + // Terminal state, kill everything + // SEC_CM: FSM.TERMINAL + default: begin + rst_lc_req_d = {PowerDomains{1'b1}}; + rst_sys_req_d = {PowerDomains{1'b1}}; + ip_clk_en_d = 1'b0; + end + endcase // unique case (state_q) + + if (fsm_invalid_i) begin + // the slow fsm is completely out of sync, transition to terminal state + state_d = FastPwrStateInvalid; + end + + + end // always_comb + + assign ack_pwrup_o = ack_pwrup_q; + assign req_pwrdn_o = req_pwrdn_q; + assign low_power_o = low_power_q; + + assign pwr_rst_o.rst_lc_req = rst_lc_req_q; + assign pwr_rst_o.rst_sys_req = rst_sys_req_q; + assign pwr_rst_o.reset_cause = reset_cause_q; + assign pwr_rst_o.rstreqs = reset_reqs_i[HwResetWidth-1:0]; + + // main and io clocks are only turned on/off as part of normal + // power sequence + assign ips_clk_en_o.main_ip_clk_en = ip_clk_en_q; + assign ips_clk_en_o.io_ip_clk_en = ip_clk_en_q; + prim_flop #( + .Width(1), + .ResetValue(1'b0) + ) u_usb_ip_clk_en ( + .clk_i, + .rst_ni, + .d_i(ip_clk_en_d & usb_ip_clk_en_i), + .q_o(ips_clk_en_o.usb_ip_clk_en) + ); + assign usb_ip_clk_status_o = clk_en_status_i.usb_status; + + prim_flop #( + .Width(1), + .ResetValue(1'b0) + ) u_reg_otp_init ( + .clk_i, + .rst_ni, + .d_i(otp_init), + .q_o(otp_init_o) + ); + + prim_flop #( + .Width(1), + .ResetValue(1'b0) + ) u_reg_lc_init ( + .clk_i, + .rst_ni, + .d_i(lc_init), + .q_o(lc_init_o) + ); + + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv new file mode 100644 index 0000000000000..d3b3d6ac115d6 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv @@ -0,0 +1,292 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager Package +// + +package pwrmgr_pkg; + + // global constant + parameter int ALWAYS_ON_DOMAIN = 0; + + // variables referenced by other modules / packages + parameter int PowerDomains = 2; // this needs to be a topgen populated number, or from topcfg? + + // variables referenced only by pwrmgr + localparam int TotalWakeWidth = pwrmgr_reg_pkg::NumWkups + 2; // Abort and fall through are added + + parameter int NumSwRstReq = 1; + + // position of escalation request + parameter int HwResetWidth = pwrmgr_reg_pkg::NumRstReqs + + pwrmgr_reg_pkg::NumIntRstReqs + + pwrmgr_reg_pkg::NumDebugRstReqs; + parameter int TotalResetWidth = HwResetWidth + NumSwRstReq; + parameter int ResetSwReqIdx = TotalResetWidth - 1; + + // pwrmgr to ast + typedef struct packed { + logic main_pd_n; + logic pwr_clamp_env; + logic pwr_clamp; + logic slow_clk_en; + logic core_clk_en; + logic io_clk_en; + logic usb_clk_en; + } pwr_ast_req_t; + + typedef struct packed { + logic slow_clk_val; + logic core_clk_val; + logic io_clk_val; + logic usb_clk_val; + logic main_pok; + } pwr_ast_rsp_t; + + // default value of pwr_ast_rsp (for dangling ports) + parameter pwr_ast_rsp_t PWR_AST_RSP_DEFAULT = '{ + slow_clk_val: 1'b1, + core_clk_val: 1'b1, + io_clk_val: 1'b1, + usb_clk_val: 1'b1, + main_pok: 1'b1 + }; + + parameter pwr_ast_rsp_t PWR_AST_RSP_SYNC_DEFAULT = '{ + slow_clk_val: 1'b0, + core_clk_val: 1'b0, + io_clk_val: 1'b0, + usb_clk_val: 1'b0, + main_pok: 1'b0 + }; + + // reasons for pwrmgr reset + typedef enum logic [1:0] { + ResetNone = 0, // there is no reset + LowPwrEntry = 1, // reset is caused by low power entry + HwReq = 2, // reset is caused by peripheral reset requests + ResetUndefined = 3 // this should never happen outside of POR + } reset_cause_e; + + // pwrmgr to rstmgr + typedef struct packed { + logic [PowerDomains-1:0] rst_lc_req; + logic [PowerDomains-1:0] rst_sys_req; + logic [HwResetWidth-1:0] rstreqs; + reset_cause_e reset_cause; + } pwr_rst_req_t; + + // rstmgr to pwrmgr + typedef struct packed { + logic [PowerDomains-1:0] rst_lc_src_n; + logic [PowerDomains-1:0] rst_sys_src_n; + } pwr_rst_rsp_t; + + // default value (for dangling ports) + parameter pwr_rst_rsp_t PWR_RST_RSP_DEFAULT = '{ + rst_lc_src_n: {PowerDomains{1'b1}}, + rst_sys_src_n: {PowerDomains{1'b1}} + }; + + // pwrmgr to clkmgr + typedef struct packed { + logic main_ip_clk_en; + logic io_ip_clk_en; + logic usb_ip_clk_en; + } pwr_clk_req_t; + + // clkmgr to pwrmgr + typedef struct packed { + logic main_status; + logic io_status; + logic usb_status; + } pwr_clk_rsp_t; + + // pwrmgr to otp + typedef struct packed { + logic otp_init; + } pwr_otp_req_t; + + // otp to pwrmgr + typedef struct packed { + logic otp_done; + logic otp_idle; + } pwr_otp_rsp_t; + + // default value (for dangling ports) + parameter pwr_otp_rsp_t PWR_OTP_RSP_DEFAULT = '{ + otp_done: 1'b1, + otp_idle: 1'b1 + }; + + // pwrmgr to lifecycle + typedef struct packed { + logic lc_init; + } pwr_lc_req_t; + + // lifecycle to pwrmgr + typedef struct packed { + logic lc_done; + logic lc_idle; + } pwr_lc_rsp_t; + + // default value (for dangling ports) + parameter pwr_lc_rsp_t PWR_LC_RSP_DEFAULT = '{ + lc_done: 1'b1, + lc_idle: 1'b1 + }; + + typedef struct packed { + logic flash_idle; + } pwr_flash_t; + + parameter pwr_flash_t PWR_FLASH_DEFAULT = '{ + flash_idle: 1'b1 + }; + + // processor to pwrmgr + typedef struct packed { + logic core_sleeping; + } pwr_cpu_t; + + // cpu reset requests and status + typedef struct packed { + logic ndmreset_req; + } pwrmgr_cpu_t; + + typedef struct packed { + lc_ctrl_pkg::lc_tx_t cpu_fetch_en; + rom_ctrl_pkg::pwrmgr_data_t [pwrmgr_reg_pkg::NumRomInputs-1:0] rom_ctrl_status; + logic lc_done; + logic otp_done; + logic strap_sampled; + logic light_reset_req; + pwr_clk_rsp_t clk_status; + } pwr_boot_status_t; + + // exported resets + + // default value for pwrmgr_ast_rsp_t (for dangling ports) + parameter pwrmgr_cpu_t PWRMGR_CPU_DEFAULT = '{ + ndmreset_req: '0 + }; + + // default value (for dangling ports) + parameter pwr_cpu_t PWR_CPU_DEFAULT = '{ + core_sleeping: 1'b0 + }; + + // default value (for dangling ports) + parameter int WAKEUPS_DEFAULT = '0; + parameter int RSTREQS_DEFAULT = '0; + + // peripherals to pwrmgr + typedef struct packed { + logic [pwrmgr_reg_pkg::NumWkups-1:0] wakeups; + // reset requests include external requests + escalation reset + logic [TotalResetWidth-1:0] rstreqs; + } pwr_peri_t; + + // power-up causes + typedef enum logic [1:0] { + Por = 2'h0, + Wake = 2'h1, + Reset = 2'h2 + } pwrup_cause_e; + + // low power hints + typedef enum logic { + None = 1'b0, + LowPower = 1'b1 + } low_power_hint_e; + + // fast fsm state enum + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 19 -n 12 \ + // -s 3096160381 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: ||||||||||||||||| (30.99%) + // 6: |||||||||||||||||||| (35.09%) + // 7: ||||||||| (15.79%) + // 8: |||||| (10.53%) + // 9: ||| (5.85%) + // 10: | (1.75%) + // 11: -- + // 12: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 10 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 10 + // + localparam int FastPwrStateWidth = 12; + typedef enum logic [FastPwrStateWidth-1:0] { + FastPwrStateLowPower = 12'b000000110111, + FastPwrStateEnableClocks = 12'b101011001110, + FastPwrStateReleaseLcRst = 12'b100111000000, + FastPwrStateOtpInit = 12'b111110100010, + FastPwrStateLcInit = 12'b101001010011, + FastPwrStateStrap = 12'b110000111010, + FastPwrStateAckPwrUp = 12'b000010101000, + FastPwrStateRomCheckDone = 12'b010111110011, + FastPwrStateRomCheckGood = 12'b010000000100, + FastPwrStateActive = 12'b001101100100, + FastPwrStateDisClks = 12'b001110010101, + FastPwrStateFallThrough = 12'b011011010000, + FastPwrStateNvmIdleChk = 12'b100101111001, + FastPwrStateLowPowerPrep = 12'b010110001111, + FastPwrStateNvmShutDown = 12'b001100001010, + FastPwrStateResetPrep = 12'b011001101111, + FastPwrStateResetWait = 12'b111111111100, + FastPwrStateReqPwrDn = 12'b111010001001, + FastPwrStateInvalid = 12'b110101010110 + } fast_pwr_state_e; + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 12 -n 10 \ + // -s 1726685338 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (54.55%) + // 6: |||||||||||||||| (45.45%) + // 7: -- + // 8: -- + // 9: -- + // 10: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 8 + // + localparam int SlowPwrStateWidth = 10; + typedef enum logic [SlowPwrStateWidth-1:0] { + SlowPwrStateReset = 10'b0000100010, + SlowPwrStateLowPower = 10'b1011000111, + SlowPwrStateMainPowerOn = 10'b0110101111, + SlowPwrStatePwrClampOff = 10'b0110010001, + SlowPwrStateClocksOn = 10'b1010111100, + SlowPwrStateReqPwrUp = 10'b0011011010, + SlowPwrStateIdle = 10'b1111100000, + SlowPwrStateAckPwrDn = 10'b0001110101, + SlowPwrStateClocksOff = 10'b1101111011, + SlowPwrStatePwrClampOn = 10'b0101001100, + SlowPwrStateMainPowerOff = 10'b1000001001, + SlowPwrStateInvalid = 10'b1100010110 + } slow_pwr_state_e; + +endpackage // pwrmgr_pkg diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_reg_pkg.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_reg_pkg.sv new file mode 100644 index 0000000000000..7efdcfdebc2c3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_reg_pkg.sv @@ -0,0 +1,279 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package pwrmgr_reg_pkg; + + // Param list + parameter int NumWkups = 6; + parameter int PINMUX_AON_PIN_WKUP_REQ_IDX = 0; + parameter int PINMUX_AON_USB_WKUP_REQ_IDX = 1; + parameter int AON_TIMER_AON_WKUP_REQ_IDX = 2; + parameter int SENSOR_CTRL_WKUP_REQ_IDX = 3; + parameter int SOC_PROXY_WKUP_INTERNAL_REQ_IDX = 4; + parameter int SOC_PROXY_WKUP_EXTERNAL_REQ_IDX = 5; + parameter int NumRstReqs = 2; + parameter int NumIntRstReqs = 2; + parameter int NumDebugRstReqs = 1; + parameter int ResetMainPwrIdx = 2; + parameter int ResetEscIdx = 3; + parameter int ResetNdmIdx = 4; + parameter int NumAlerts = 1; + + // Address widths within the block + parameter int BlockAw = 7; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_intr_state_reg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_intr_enable_reg_t; + + typedef struct packed { + logic q; + logic qe; + } pwrmgr_reg2hw_intr_test_reg_t; + + typedef struct packed { + logic q; + logic qe; + } pwrmgr_reg2hw_alert_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + } main_pd_n; + struct packed { + logic q; + } usb_clk_en_active; + struct packed { + logic q; + } usb_clk_en_lp; + struct packed { + logic q; + } io_clk_en; + struct packed { + logic q; + } core_clk_en; + struct packed { + logic q; + } low_power_hint; + } pwrmgr_reg2hw_control_reg_t; + + typedef struct packed { + logic q; + logic qe; + } pwrmgr_reg2hw_cfg_cdc_sync_reg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_wakeup_en_mreg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_reset_en_mreg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_wake_info_capture_dis_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } abort; + struct packed { + logic q; + logic qe; + } fall_through; + struct packed { + logic [5:0] q; + logic qe; + } reasons; + } pwrmgr_reg2hw_wake_info_reg_t; + + typedef struct packed { + struct packed { + logic q; + } main_pd_glitch; + struct packed { + logic q; + } esc_timeout; + struct packed { + logic q; + } reg_intg_err; + } pwrmgr_reg2hw_fault_status_reg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_intr_state_reg_t; + + typedef struct packed { + logic d; + } pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } low_power_hint; + } pwrmgr_hw2reg_control_reg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_cfg_cdc_sync_reg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_wake_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_reset_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_escalate_reset_status_reg_t; + + typedef struct packed { + struct packed { + logic [5:0] d; + } reasons; + struct packed { + logic d; + } fall_through; + struct packed { + logic d; + } abort; + } pwrmgr_hw2reg_wake_info_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } reg_intg_err; + struct packed { + logic d; + logic de; + } esc_timeout; + struct packed { + logic d; + logic de; + } main_pd_glitch; + } pwrmgr_hw2reg_fault_status_reg_t; + + // Register -> HW type + typedef struct packed { + pwrmgr_reg2hw_intr_state_reg_t intr_state; // [36:36] + pwrmgr_reg2hw_intr_enable_reg_t intr_enable; // [35:35] + pwrmgr_reg2hw_intr_test_reg_t intr_test; // [34:33] + pwrmgr_reg2hw_alert_test_reg_t alert_test; // [32:31] + pwrmgr_reg2hw_control_reg_t control; // [30:25] + pwrmgr_reg2hw_cfg_cdc_sync_reg_t cfg_cdc_sync; // [24:23] + pwrmgr_reg2hw_wakeup_en_mreg_t [5:0] wakeup_en; // [22:17] + pwrmgr_reg2hw_reset_en_mreg_t [1:0] reset_en; // [16:15] + pwrmgr_reg2hw_wake_info_capture_dis_reg_t wake_info_capture_dis; // [14:14] + pwrmgr_reg2hw_wake_info_reg_t wake_info; // [13:3] + pwrmgr_reg2hw_fault_status_reg_t fault_status; // [2:0] + } pwrmgr_reg2hw_t; + + // HW -> register type + typedef struct packed { + pwrmgr_hw2reg_intr_state_reg_t intr_state; // [38:37] + pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t ctrl_cfg_regwen; // [36:36] + pwrmgr_hw2reg_control_reg_t control; // [35:34] + pwrmgr_hw2reg_cfg_cdc_sync_reg_t cfg_cdc_sync; // [33:32] + pwrmgr_hw2reg_wake_status_mreg_t [5:0] wake_status; // [31:20] + pwrmgr_hw2reg_reset_status_mreg_t [1:0] reset_status; // [19:16] + pwrmgr_hw2reg_escalate_reset_status_reg_t escalate_reset_status; // [15:14] + pwrmgr_hw2reg_wake_info_reg_t wake_info; // [13:6] + pwrmgr_hw2reg_fault_status_reg_t fault_status; // [5:0] + } pwrmgr_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] PWRMGR_INTR_STATE_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] PWRMGR_INTR_ENABLE_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] PWRMGR_INTR_TEST_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] PWRMGR_ALERT_TEST_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] PWRMGR_CTRL_CFG_REGWEN_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] PWRMGR_CONTROL_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] PWRMGR_CFG_CDC_SYNC_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_REGWEN_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] PWRMGR_WAKE_STATUS_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_REGWEN_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] PWRMGR_RESET_STATUS_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] PWRMGR_ESCALATE_RESET_STATUS_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] PWRMGR_FAULT_STATUS_OFFSET = 7'h 40; + + // Reset values for hwext registers and their fields + parameter logic [0:0] PWRMGR_INTR_TEST_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_INTR_TEST_WAKEUP_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_ALERT_TEST_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_RESVAL = 1'h 1; + parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_EN_RESVAL = 1'h 1; + parameter logic [7:0] PWRMGR_WAKE_INFO_RESVAL = 8'h 0; + parameter logic [5:0] PWRMGR_WAKE_INFO_REASONS_RESVAL = 6'h 0; + parameter logic [0:0] PWRMGR_WAKE_INFO_FALL_THROUGH_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_WAKE_INFO_ABORT_RESVAL = 1'h 0; + + // Register index + typedef enum int { + PWRMGR_INTR_STATE, + PWRMGR_INTR_ENABLE, + PWRMGR_INTR_TEST, + PWRMGR_ALERT_TEST, + PWRMGR_CTRL_CFG_REGWEN, + PWRMGR_CONTROL, + PWRMGR_CFG_CDC_SYNC, + PWRMGR_WAKEUP_EN_REGWEN, + PWRMGR_WAKEUP_EN, + PWRMGR_WAKE_STATUS, + PWRMGR_RESET_EN_REGWEN, + PWRMGR_RESET_EN, + PWRMGR_RESET_STATUS, + PWRMGR_ESCALATE_RESET_STATUS, + PWRMGR_WAKE_INFO_CAPTURE_DIS, + PWRMGR_WAKE_INFO, + PWRMGR_FAULT_STATUS + } pwrmgr_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] PWRMGR_PERMIT [17] = '{ + 4'b 0001, // index[ 0] PWRMGR_INTR_STATE + 4'b 0001, // index[ 1] PWRMGR_INTR_ENABLE + 4'b 0001, // index[ 2] PWRMGR_INTR_TEST + 4'b 0001, // index[ 3] PWRMGR_ALERT_TEST + 4'b 0001, // index[ 4] PWRMGR_CTRL_CFG_REGWEN + 4'b 0011, // index[ 5] PWRMGR_CONTROL + 4'b 0001, // index[ 6] PWRMGR_CFG_CDC_SYNC + 4'b 0001, // index[ 7] PWRMGR_WAKEUP_EN_REGWEN + 4'b 0001, // index[ 8] PWRMGR_WAKEUP_EN + 4'b 0001, // index[ 9] PWRMGR_WAKE_STATUS + 4'b 0001, // index[10] PWRMGR_RESET_EN_REGWEN + 4'b 0001, // index[11] PWRMGR_RESET_EN + 4'b 0001, // index[12] PWRMGR_RESET_STATUS + 4'b 0001, // index[13] PWRMGR_ESCALATE_RESET_STATUS + 4'b 0001, // index[14] PWRMGR_WAKE_INFO_CAPTURE_DIS + 4'b 0001, // index[15] PWRMGR_WAKE_INFO + 4'b 0001 // index[16] PWRMGR_FAULT_STATUS + }; + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_reg_top.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_reg_top.sv new file mode 100644 index 0000000000000..ba7e6c9689234 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_reg_top.sv @@ -0,0 +1,1487 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module pwrmgr_reg_top ( + input clk_i, + input rst_ni, + input clk_lc_i, + input rst_lc_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output pwrmgr_reg_pkg::pwrmgr_reg2hw_t reg2hw, // Write + input pwrmgr_reg_pkg::pwrmgr_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import pwrmgr_reg_pkg::* ; + + localparam int AW = 7; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [16:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(17) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_lc_i or negedge rst_lc_ni) begin + if (!rst_lc_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic intr_state_we; + logic intr_state_qs; + logic intr_state_wd; + logic intr_enable_we; + logic intr_enable_qs; + logic intr_enable_wd; + logic intr_test_we; + logic intr_test_wd; + logic alert_test_we; + logic alert_test_wd; + logic ctrl_cfg_regwen_re; + logic ctrl_cfg_regwen_qs; + logic control_we; + logic control_low_power_hint_qs; + logic control_low_power_hint_wd; + logic control_core_clk_en_qs; + logic control_core_clk_en_wd; + logic control_io_clk_en_qs; + logic control_io_clk_en_wd; + logic control_usb_clk_en_lp_qs; + logic control_usb_clk_en_lp_wd; + logic control_usb_clk_en_active_qs; + logic control_usb_clk_en_active_wd; + logic control_main_pd_n_qs; + logic control_main_pd_n_wd; + logic cfg_cdc_sync_we; + logic cfg_cdc_sync_qs; + logic cfg_cdc_sync_wd; + logic wakeup_en_regwen_we; + logic wakeup_en_regwen_qs; + logic wakeup_en_regwen_wd; + logic wakeup_en_we; + logic wakeup_en_en_0_qs; + logic wakeup_en_en_0_wd; + logic wakeup_en_en_1_qs; + logic wakeup_en_en_1_wd; + logic wakeup_en_en_2_qs; + logic wakeup_en_en_2_wd; + logic wakeup_en_en_3_qs; + logic wakeup_en_en_3_wd; + logic wakeup_en_en_4_qs; + logic wakeup_en_en_4_wd; + logic wakeup_en_en_5_qs; + logic wakeup_en_en_5_wd; + logic wake_status_val_0_qs; + logic wake_status_val_1_qs; + logic wake_status_val_2_qs; + logic wake_status_val_3_qs; + logic wake_status_val_4_qs; + logic wake_status_val_5_qs; + logic reset_en_regwen_we; + logic reset_en_regwen_qs; + logic reset_en_regwen_wd; + logic reset_en_we; + logic reset_en_en_0_qs; + logic reset_en_en_0_wd; + logic reset_en_en_1_qs; + logic reset_en_en_1_wd; + logic reset_status_val_0_qs; + logic reset_status_val_1_qs; + logic escalate_reset_status_qs; + logic wake_info_capture_dis_we; + logic wake_info_capture_dis_qs; + logic wake_info_capture_dis_wd; + logic wake_info_re; + logic wake_info_we; + logic [5:0] wake_info_reasons_qs; + logic [5:0] wake_info_reasons_wd; + logic wake_info_fall_through_qs; + logic wake_info_fall_through_wd; + logic wake_info_abort_qs; + logic wake_info_abort_wd; + logic fault_status_reg_intg_err_qs; + logic fault_status_esc_timeout_qs; + logic fault_status_main_pd_glitch_qs; + // Define register CDC handling. + // CDC handling is done on a per-reg instead of per-field boundary. + + // Register instances + // R[intr_state]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_wd), + + // from internal hardware + .de (hw2reg.intr_state.de), + .d (hw2reg.intr_state.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.q), + .ds (), + + // to register interface (read) + .qs (intr_state_qs) + ); + + + // R[intr_enable]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_qs) + ); + + + // R[intr_test]: V(True) + logic intr_test_qe; + logic [0:0] intr_test_flds_we; + assign intr_test_qe = &intr_test_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_intr_test ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[0]), + .q (reg2hw.intr_test.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.qe = intr_test_qe; + + + // R[alert_test]: V(True) + logic alert_test_qe; + logic [0:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_alert_test ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.qe = alert_test_qe; + + + // R[ctrl_cfg_regwen]: V(True) + prim_subreg_ext #( + .DW (1) + ) u_ctrl_cfg_regwen ( + .re (ctrl_cfg_regwen_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.ctrl_cfg_regwen.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (ctrl_cfg_regwen_qs) + ); + + + // R[control]: V(False) + // Create REGWEN-gated WE signal + logic control_gated_we; + assign control_gated_we = control_we & ctrl_cfg_regwen_qs; + // F[low_power_hint]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_control_low_power_hint ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (control_gated_we), + .wd (control_low_power_hint_wd), + + // from internal hardware + .de (hw2reg.control.low_power_hint.de), + .d (hw2reg.control.low_power_hint.d), + + // to internal hardware + .qe (), + .q (reg2hw.control.low_power_hint.q), + .ds (), + + // to register interface (read) + .qs (control_low_power_hint_qs) + ); + + // F[core_clk_en]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_control_core_clk_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (control_gated_we), + .wd (control_core_clk_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.control.core_clk_en.q), + .ds (), + + // to register interface (read) + .qs (control_core_clk_en_qs) + ); + + // F[io_clk_en]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_control_io_clk_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (control_gated_we), + .wd (control_io_clk_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.control.io_clk_en.q), + .ds (), + + // to register interface (read) + .qs (control_io_clk_en_qs) + ); + + // F[usb_clk_en_lp]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_control_usb_clk_en_lp ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (control_gated_we), + .wd (control_usb_clk_en_lp_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.control.usb_clk_en_lp.q), + .ds (), + + // to register interface (read) + .qs (control_usb_clk_en_lp_qs) + ); + + // F[usb_clk_en_active]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_control_usb_clk_en_active ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (control_gated_we), + .wd (control_usb_clk_en_active_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.control.usb_clk_en_active.q), + .ds (), + + // to register interface (read) + .qs (control_usb_clk_en_active_qs) + ); + + // F[main_pd_n]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_control_main_pd_n ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (control_gated_we), + .wd (control_main_pd_n_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.control.main_pd_n.q), + .ds (), + + // to register interface (read) + .qs (control_main_pd_n_qs) + ); + + + // R[cfg_cdc_sync]: V(False) + logic cfg_cdc_sync_qe; + logic [0:0] cfg_cdc_sync_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_cfg_cdc_sync0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&cfg_cdc_sync_flds_we), + .q_o(cfg_cdc_sync_qe) + ); + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cfg_cdc_sync ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cfg_cdc_sync_we), + .wd (cfg_cdc_sync_wd), + + // from internal hardware + .de (hw2reg.cfg_cdc_sync.de), + .d (hw2reg.cfg_cdc_sync.d), + + // to internal hardware + .qe (cfg_cdc_sync_flds_we[0]), + .q (reg2hw.cfg_cdc_sync.q), + .ds (), + + // to register interface (read) + .qs (cfg_cdc_sync_qs) + ); + assign reg2hw.cfg_cdc_sync.qe = cfg_cdc_sync_qe; + + + // R[wakeup_en_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wakeup_en_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wakeup_en_regwen_we), + .wd (wakeup_en_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wakeup_en_regwen_qs) + ); + + + // Subregister 0 of Multireg wakeup_en + // R[wakeup_en]: V(False) + // Create REGWEN-gated WE signal + logic wakeup_en_gated_we; + assign wakeup_en_gated_we = wakeup_en_we & wakeup_en_regwen_qs; + // F[en_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wakeup_en_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wakeup_en_gated_we), + .wd (wakeup_en_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wakeup_en[0].q), + .ds (), + + // to register interface (read) + .qs (wakeup_en_en_0_qs) + ); + + // F[en_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wakeup_en_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wakeup_en_gated_we), + .wd (wakeup_en_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wakeup_en[1].q), + .ds (), + + // to register interface (read) + .qs (wakeup_en_en_1_qs) + ); + + // F[en_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wakeup_en_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wakeup_en_gated_we), + .wd (wakeup_en_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wakeup_en[2].q), + .ds (), + + // to register interface (read) + .qs (wakeup_en_en_2_qs) + ); + + // F[en_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wakeup_en_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wakeup_en_gated_we), + .wd (wakeup_en_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wakeup_en[3].q), + .ds (), + + // to register interface (read) + .qs (wakeup_en_en_3_qs) + ); + + // F[en_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wakeup_en_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wakeup_en_gated_we), + .wd (wakeup_en_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wakeup_en[4].q), + .ds (), + + // to register interface (read) + .qs (wakeup_en_en_4_qs) + ); + + // F[en_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wakeup_en_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wakeup_en_gated_we), + .wd (wakeup_en_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wakeup_en[5].q), + .ds (), + + // to register interface (read) + .qs (wakeup_en_en_5_qs) + ); + + + // Subregister 0 of Multireg wake_status + // R[wake_status]: V(False) + // F[val_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wake_status_val_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.wake_status[0].de), + .d (hw2reg.wake_status[0].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wake_status_val_0_qs) + ); + + // F[val_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wake_status_val_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.wake_status[1].de), + .d (hw2reg.wake_status[1].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wake_status_val_1_qs) + ); + + // F[val_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wake_status_val_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.wake_status[2].de), + .d (hw2reg.wake_status[2].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wake_status_val_2_qs) + ); + + // F[val_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wake_status_val_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.wake_status[3].de), + .d (hw2reg.wake_status[3].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wake_status_val_3_qs) + ); + + // F[val_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wake_status_val_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.wake_status[4].de), + .d (hw2reg.wake_status[4].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wake_status_val_4_qs) + ); + + // F[val_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wake_status_val_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.wake_status[5].de), + .d (hw2reg.wake_status[5].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wake_status_val_5_qs) + ); + + + // R[reset_en_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_reset_en_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (reset_en_regwen_we), + .wd (reset_en_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (reset_en_regwen_qs) + ); + + + // Subregister 0 of Multireg reset_en + // R[reset_en]: V(False) + // Create REGWEN-gated WE signal + logic reset_en_gated_we; + assign reset_en_gated_we = reset_en_we & reset_en_regwen_qs; + // F[en_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_reset_en_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (reset_en_gated_we), + .wd (reset_en_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.reset_en[0].q), + .ds (), + + // to register interface (read) + .qs (reset_en_en_0_qs) + ); + + // F[en_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_reset_en_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (reset_en_gated_we), + .wd (reset_en_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.reset_en[1].q), + .ds (), + + // to register interface (read) + .qs (reset_en_en_1_qs) + ); + + + // Subregister 0 of Multireg reset_status + // R[reset_status]: V(False) + // F[val_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_reset_status_val_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.reset_status[0].de), + .d (hw2reg.reset_status[0].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (reset_status_val_0_qs) + ); + + // F[val_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_reset_status_val_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.reset_status[1].de), + .d (hw2reg.reset_status[1].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (reset_status_val_1_qs) + ); + + + // R[escalate_reset_status]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_escalate_reset_status ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.escalate_reset_status.de), + .d (hw2reg.escalate_reset_status.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (escalate_reset_status_qs) + ); + + + // R[wake_info_capture_dis]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wake_info_capture_dis ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wake_info_capture_dis_we), + .wd (wake_info_capture_dis_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wake_info_capture_dis.q), + .ds (), + + // to register interface (read) + .qs (wake_info_capture_dis_qs) + ); + + + // R[wake_info]: V(True) + logic wake_info_qe; + logic [2:0] wake_info_flds_we; + assign wake_info_qe = &wake_info_flds_we; + // F[reasons]: 5:0 + prim_subreg_ext #( + .DW (6) + ) u_wake_info_reasons ( + .re (wake_info_re), + .we (wake_info_we), + .wd (wake_info_reasons_wd), + .d (hw2reg.wake_info.reasons.d), + .qre (), + .qe (wake_info_flds_we[0]), + .q (reg2hw.wake_info.reasons.q), + .ds (), + .qs (wake_info_reasons_qs) + ); + assign reg2hw.wake_info.reasons.qe = wake_info_qe; + + // F[fall_through]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_wake_info_fall_through ( + .re (wake_info_re), + .we (wake_info_we), + .wd (wake_info_fall_through_wd), + .d (hw2reg.wake_info.fall_through.d), + .qre (), + .qe (wake_info_flds_we[1]), + .q (reg2hw.wake_info.fall_through.q), + .ds (), + .qs (wake_info_fall_through_qs) + ); + assign reg2hw.wake_info.fall_through.qe = wake_info_qe; + + // F[abort]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_wake_info_abort ( + .re (wake_info_re), + .we (wake_info_we), + .wd (wake_info_abort_wd), + .d (hw2reg.wake_info.abort.d), + .qre (), + .qe (wake_info_flds_we[2]), + .q (reg2hw.wake_info.abort.q), + .ds (), + .qs (wake_info_abort_qs) + ); + assign reg2hw.wake_info.abort.qe = wake_info_qe; + + + // R[fault_status]: V(False) + // F[reg_intg_err]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_fault_status_reg_intg_err ( + // sync clock and reset required for this register + .clk_i (clk_lc_i), + .rst_ni (rst_lc_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.fault_status.reg_intg_err.de), + .d (hw2reg.fault_status.reg_intg_err.d), + + // to internal hardware + .qe (), + .q (reg2hw.fault_status.reg_intg_err.q), + .ds (), + + // to register interface (read) + .qs (fault_status_reg_intg_err_qs) + ); + + // F[esc_timeout]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_fault_status_esc_timeout ( + // sync clock and reset required for this register + .clk_i (clk_lc_i), + .rst_ni (rst_lc_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.fault_status.esc_timeout.de), + .d (hw2reg.fault_status.esc_timeout.d), + + // to internal hardware + .qe (), + .q (reg2hw.fault_status.esc_timeout.q), + .ds (), + + // to register interface (read) + .qs (fault_status_esc_timeout_qs) + ); + + // F[main_pd_glitch]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_fault_status_main_pd_glitch ( + // sync clock and reset required for this register + .clk_i (clk_lc_i), + .rst_ni (rst_lc_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.fault_status.main_pd_glitch.de), + .d (hw2reg.fault_status.main_pd_glitch.d), + + // to internal hardware + .qe (), + .q (reg2hw.fault_status.main_pd_glitch.q), + .ds (), + + // to register interface (read) + .qs (fault_status_main_pd_glitch_qs) + ); + + + + logic [16:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == PWRMGR_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == PWRMGR_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == PWRMGR_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == PWRMGR_ALERT_TEST_OFFSET); + addr_hit[ 4] = (reg_addr == PWRMGR_CTRL_CFG_REGWEN_OFFSET); + addr_hit[ 5] = (reg_addr == PWRMGR_CONTROL_OFFSET); + addr_hit[ 6] = (reg_addr == PWRMGR_CFG_CDC_SYNC_OFFSET); + addr_hit[ 7] = (reg_addr == PWRMGR_WAKEUP_EN_REGWEN_OFFSET); + addr_hit[ 8] = (reg_addr == PWRMGR_WAKEUP_EN_OFFSET); + addr_hit[ 9] = (reg_addr == PWRMGR_WAKE_STATUS_OFFSET); + addr_hit[10] = (reg_addr == PWRMGR_RESET_EN_REGWEN_OFFSET); + addr_hit[11] = (reg_addr == PWRMGR_RESET_EN_OFFSET); + addr_hit[12] = (reg_addr == PWRMGR_RESET_STATUS_OFFSET); + addr_hit[13] = (reg_addr == PWRMGR_ESCALATE_RESET_STATUS_OFFSET); + addr_hit[14] = (reg_addr == PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET); + addr_hit[15] = (reg_addr == PWRMGR_WAKE_INFO_OFFSET); + addr_hit[16] = (reg_addr == PWRMGR_FAULT_STATUS_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(PWRMGR_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(PWRMGR_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(PWRMGR_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(PWRMGR_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(PWRMGR_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(PWRMGR_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(PWRMGR_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(PWRMGR_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(PWRMGR_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(PWRMGR_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(PWRMGR_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(PWRMGR_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(PWRMGR_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(PWRMGR_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(PWRMGR_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(PWRMGR_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(PWRMGR_PERMIT[16] & ~reg_be))))); + end + + // Generate write-enables + assign intr_state_we = addr_hit[0] & reg_we & !reg_error; + + assign intr_state_wd = reg_wdata[0]; + assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; + + assign intr_enable_wd = reg_wdata[0]; + assign intr_test_we = addr_hit[2] & reg_we & !reg_error; + + assign intr_test_wd = reg_wdata[0]; + assign alert_test_we = addr_hit[3] & reg_we & !reg_error; + + assign alert_test_wd = reg_wdata[0]; + assign ctrl_cfg_regwen_re = addr_hit[4] & reg_re & !reg_error; + assign control_we = addr_hit[5] & reg_we & !reg_error; + + assign control_low_power_hint_wd = reg_wdata[0]; + + assign control_core_clk_en_wd = reg_wdata[4]; + + assign control_io_clk_en_wd = reg_wdata[5]; + + assign control_usb_clk_en_lp_wd = reg_wdata[6]; + + assign control_usb_clk_en_active_wd = reg_wdata[7]; + + assign control_main_pd_n_wd = reg_wdata[8]; + assign cfg_cdc_sync_we = addr_hit[6] & reg_we & !reg_error; + + assign cfg_cdc_sync_wd = reg_wdata[0]; + assign wakeup_en_regwen_we = addr_hit[7] & reg_we & !reg_error; + + assign wakeup_en_regwen_wd = reg_wdata[0]; + assign wakeup_en_we = addr_hit[8] & reg_we & !reg_error; + + assign wakeup_en_en_0_wd = reg_wdata[0]; + + assign wakeup_en_en_1_wd = reg_wdata[1]; + + assign wakeup_en_en_2_wd = reg_wdata[2]; + + assign wakeup_en_en_3_wd = reg_wdata[3]; + + assign wakeup_en_en_4_wd = reg_wdata[4]; + + assign wakeup_en_en_5_wd = reg_wdata[5]; + assign reset_en_regwen_we = addr_hit[10] & reg_we & !reg_error; + + assign reset_en_regwen_wd = reg_wdata[0]; + assign reset_en_we = addr_hit[11] & reg_we & !reg_error; + + assign reset_en_en_0_wd = reg_wdata[0]; + + assign reset_en_en_1_wd = reg_wdata[1]; + assign wake_info_capture_dis_we = addr_hit[14] & reg_we & !reg_error; + + assign wake_info_capture_dis_wd = reg_wdata[0]; + assign wake_info_re = addr_hit[15] & reg_re & !reg_error; + assign wake_info_we = addr_hit[15] & reg_we & !reg_error; + + assign wake_info_reasons_wd = reg_wdata[5:0]; + + assign wake_info_fall_through_wd = reg_wdata[6]; + + assign wake_info_abort_wd = reg_wdata[7]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check = '0; + reg_we_check[0] = intr_state_we; + reg_we_check[1] = intr_enable_we; + reg_we_check[2] = intr_test_we; + reg_we_check[3] = alert_test_we; + reg_we_check[4] = 1'b0; + reg_we_check[5] = control_gated_we; + reg_we_check[6] = cfg_cdc_sync_we; + reg_we_check[7] = wakeup_en_regwen_we; + reg_we_check[8] = wakeup_en_gated_we; + reg_we_check[9] = 1'b0; + reg_we_check[10] = reset_en_regwen_we; + reg_we_check[11] = reset_en_gated_we; + reg_we_check[12] = 1'b0; + reg_we_check[13] = 1'b0; + reg_we_check[14] = wake_info_capture_dis_we; + reg_we_check[15] = wake_info_we; + reg_we_check[16] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = intr_state_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = intr_enable_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[4]: begin + reg_rdata_next[0] = ctrl_cfg_regwen_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = control_low_power_hint_qs; + reg_rdata_next[4] = control_core_clk_en_qs; + reg_rdata_next[5] = control_io_clk_en_qs; + reg_rdata_next[6] = control_usb_clk_en_lp_qs; + reg_rdata_next[7] = control_usb_clk_en_active_qs; + reg_rdata_next[8] = control_main_pd_n_qs; + end + + addr_hit[6]: begin + reg_rdata_next[0] = cfg_cdc_sync_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = wakeup_en_regwen_qs; + end + + addr_hit[8]: begin + reg_rdata_next[0] = wakeup_en_en_0_qs; + reg_rdata_next[1] = wakeup_en_en_1_qs; + reg_rdata_next[2] = wakeup_en_en_2_qs; + reg_rdata_next[3] = wakeup_en_en_3_qs; + reg_rdata_next[4] = wakeup_en_en_4_qs; + reg_rdata_next[5] = wakeup_en_en_5_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = wake_status_val_0_qs; + reg_rdata_next[1] = wake_status_val_1_qs; + reg_rdata_next[2] = wake_status_val_2_qs; + reg_rdata_next[3] = wake_status_val_3_qs; + reg_rdata_next[4] = wake_status_val_4_qs; + reg_rdata_next[5] = wake_status_val_5_qs; + end + + addr_hit[10]: begin + reg_rdata_next[0] = reset_en_regwen_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = reset_en_en_0_qs; + reg_rdata_next[1] = reset_en_en_1_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = reset_status_val_0_qs; + reg_rdata_next[1] = reset_status_val_1_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = escalate_reset_status_qs; + end + + addr_hit[14]: begin + reg_rdata_next[0] = wake_info_capture_dis_qs; + end + + addr_hit[15]: begin + reg_rdata_next[5:0] = wake_info_reasons_qs; + reg_rdata_next[6] = wake_info_fall_through_qs; + reg_rdata_next[7] = wake_info_abort_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = fault_status_reg_intg_err_qs; + reg_rdata_next[1] = fault_status_esc_timeout_qs; + reg_rdata_next[2] = fault_status_main_pd_glitch_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_slow_fsm.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_slow_fsm.sv new file mode 100644 index 0000000000000..f78105a85874d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_slow_fsm.sv @@ -0,0 +1,358 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager Slow FSM +// + +`include "prim_assert.sv" + +module pwrmgr_slow_fsm import pwrmgr_pkg::*; ( + input clk_i, + input rst_ni, + input rst_main_ni, + + // sync'ed requests from peripherals + input wakeup_i, + input reset_req_i, + + // interface with fast fsm + output logic req_pwrup_o, + output logic pwrup_cause_toggle_o, + output pwrup_cause_e pwrup_cause_o, + input ack_pwrup_i, + input req_pwrdn_i, + output logic ack_pwrdn_o, + output logic rst_req_o, + output logic fsm_invalid_o, + input clr_req_i, + output logic usb_ip_clk_en_o, + input usb_ip_clk_status_i, + + // low power entry configuration + input main_pd_ni, + input io_clk_en_i, + input core_clk_en_i, + input usb_clk_en_lp_i, + input usb_clk_en_active_i, + + // AST interface + input pwr_ast_rsp_t ast_i, + output pwr_ast_req_t ast_o +); + + slow_pwr_state_e state_q, state_d; + + // All signals crossing over to other domain must be flopped + pwrup_cause_e cause_q, cause_d; + logic cause_toggle_q, cause_toggle_d; + logic req_pwrup_q, req_pwrup_d; + logic ack_pwrdn_q, ack_pwrdn_d; + + logic clk_active; + + // All power signals and signals going to analog logic are flopped to avoid transitional glitches + logic pd_nq, pd_nd; + logic pwr_clamp_q, pwr_clamp_d; + logic pwr_clamp_env_q, pwr_clamp_env_d; + logic core_clk_en_q, core_clk_en_d; + logic io_clk_en_q, io_clk_en_d; + logic usb_clk_en_q, usb_clk_en_d; + logic fsm_invalid_q, fsm_invalid_d; + + logic all_clks_valid; + logic all_clks_invalid; + + // when to monitor pok for instability + // These are monitored only in active and low power states + logic mon_main_pok; + logic set_main_pok; + logic async_main_pok_st; + logic main_pok_st; + + // all clocks sources are valid + // if clocks (usb) not configured to be active, then just bypass check + assign all_clks_valid = ast_i.core_clk_val & + ast_i.io_clk_val & + (~usb_clk_en_active_i | ast_i.usb_clk_val); + + // usb clock state during low power is not completely controlled by + // input. + // if main_pd_ni is 0, (ie power will be turned off), then the low power + // state of usb is also off. If main_pd_ni is 1 (power will be kept on), + // then the low power state of usb is directly controlled. + logic usb_clk_en_lp; + assign usb_clk_en_lp = main_pd_ni & usb_clk_en_lp_i; + + // all other clocks are also diasbled when power is turned off. + logic core_clk_en; + logic io_clk_en; + assign core_clk_en = main_pd_ni & core_clk_en_i; + assign io_clk_en = main_pd_ni & io_clk_en_i; + + // if clocks were configured to turn off, make sure val is invalid + // if clocks were not configured to turn off, just bypass the check + assign all_clks_invalid = (core_clk_en | ~ast_i.core_clk_val) & + (io_clk_en | ~ast_i.io_clk_val) & + (usb_clk_en_lp | ~ast_i.usb_clk_val); + + // ensure that clock controls are constantly re-evaluated and not just + // in one specific state + // When fsm is invalid, force the clocks to be on such that the fast fsm + // can forcibly reset the system. + // In the event the clocks cannot be turned on even when forced, the fsm + // invalid signal forces power to turn off. + assign core_clk_en_d = fsm_invalid_q | (clk_active | core_clk_en); + assign io_clk_en_d = fsm_invalid_q | (clk_active | io_clk_en); + assign usb_clk_en_d = fsm_invalid_q | (clk_active ? usb_clk_en_active_i : usb_clk_en_lp); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + cause_q <= Por; + cause_toggle_q <= 1'b0; + pd_nq <= 1'b1; + pwr_clamp_q <= 1'b1; + pwr_clamp_env_q <= 1'b1; + core_clk_en_q <= 1'b0; + io_clk_en_q <= 1'b0; + usb_clk_en_q <= 1'b0; + req_pwrup_q <= 1'b0; + ack_pwrdn_q <= 1'b0; + fsm_invalid_q <= 1'b0; + end else begin + cause_q <= cause_d; + cause_toggle_q <= cause_toggle_d; + pd_nq <= pd_nd; + pwr_clamp_q <= pwr_clamp_d; + pwr_clamp_env_q <= pwr_clamp_env_d; + core_clk_en_q <= core_clk_en_d; + io_clk_en_q <= io_clk_en_d; + usb_clk_en_q <= usb_clk_en_d; + req_pwrup_q <= req_pwrup_d; + ack_pwrdn_q <= ack_pwrdn_d; + fsm_invalid_q <= fsm_invalid_d; + end + end + + // SEC_CM: FSM.SPARSE + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, slow_pwr_state_e, SlowPwrStateReset) + + always_comb begin + state_d = state_q; + cause_d = cause_q; + pd_nd = pd_nq; + cause_toggle_d = cause_toggle_q; + pwr_clamp_d = pwr_clamp_q; + pwr_clamp_env_d = pwr_clamp_env_q; + + req_pwrup_d = req_pwrup_q; + ack_pwrdn_d = ack_pwrdn_q; + fsm_invalid_d = fsm_invalid_q; + + set_main_pok = '0; + + clk_active = '0; + + unique case(state_q) + + SlowPwrStateReset: begin + state_d = SlowPwrStateMainPowerOn; + cause_d = Por; + end + + SlowPwrStateLowPower: begin + // reset request behaves identically to a wakeup, other than the power-up cause being + // different + if (wakeup_i || reset_req_i) begin + state_d = SlowPwrStateMainPowerOn; + cause_toggle_d = ~cause_toggle_q; + cause_d = reset_req_i ? Reset : Wake; + end + end + + SlowPwrStateMainPowerOn: begin + pd_nd = 1'b1; + + if (main_pok_st) begin + set_main_pok = 1'b1; + pwr_clamp_env_d = 1'b0; + state_d = SlowPwrStatePwrClampOff; + end + end + + SlowPwrStatePwrClampOff: begin + pwr_clamp_d = 1'b0; + state_d = SlowPwrStateClocksOn; + end + + SlowPwrStateClocksOn: begin + clk_active = 1'b1; + + if (all_clks_valid) begin + state_d = SlowPwrStateReqPwrUp; + end + end + + SlowPwrStateReqPwrUp: begin + clk_active = 1'b1; + req_pwrup_d = 1'b1; + + // req_pwrdn_i should be 0 here to indicate + // the request from the previous round has definitely completed + if (ack_pwrup_i && !req_pwrdn_i) begin + req_pwrup_d = 1'b0; + state_d = SlowPwrStateIdle; + end + end + + SlowPwrStateIdle: begin + // ack_pwrup_i should be 0 here to indicate + // the ack from the previous round has definitively completed + clk_active = 1'b1; + + if (req_pwrdn_i && !ack_pwrup_i) begin + state_d = SlowPwrStateAckPwrDn; + end + end + + SlowPwrStateAckPwrDn: begin + clk_active = 1'b1; + ack_pwrdn_d = 1'b1; + + if (!req_pwrdn_i) begin + ack_pwrdn_d = 1'b0; + state_d = SlowPwrStateClocksOff; + end + end + + SlowPwrStateClocksOff: begin + if (all_clks_invalid) begin + // if main power is turned off, assert early clamp ahead + pwr_clamp_env_d = ~main_pd_ni; + state_d = SlowPwrStatePwrClampOn; + end + end + + SlowPwrStatePwrClampOn: begin + // if main power is turned off, assert clamp ahead + pwr_clamp_d = pwr_clamp_env_q; + state_d = SlowPwrStateMainPowerOff; + end + + SlowPwrStateMainPowerOff: begin + pd_nd = main_pd_ni; + + // Proceed if power is already off, or if there was no intent to + // turn off the power. + if (!main_pok_st | main_pd_ni) begin + state_d = SlowPwrStateLowPower; + end + end + + // Very terminal state, kill everything + // Signal the fast FSM if it somehow is still running. + // Both FSMs are now permanently out of sync and the device + // must be rebooted. + // SEC_CM: FSM.TERMINAL + default: begin + fsm_invalid_d = 1'b1; + pd_nd = 1'b0; + pwr_clamp_d = 1'b1; + end + endcase // unique case (state_q) + end // always_comb + + // If the main_pok ever drops, capture that glitch + // and hold onto it for reset escalation + always_ff @(posedge clk_i or negedge rst_main_ni) begin + if (!rst_main_ni) begin + async_main_pok_st <= '0; + end else begin + async_main_pok_st <= ast_i.main_pok; + end + end + + // We need to synchronize the above because the reset + // may cause the signal to change at any time. + prim_flop_2sync # ( + .Width(1) + ) u_main_pok_sync ( + .clk_i, + .rst_ni, + .d_i(async_main_pok_st), + .q_o(main_pok_st) + ); + + // Determine when pok should be monitored + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mon_main_pok <= '0; + end else if (!pd_nd && mon_main_pok) begin + mon_main_pok <= 1'b0; + end else if (set_main_pok) begin + mon_main_pok <= 1'b1; + end + end + + // power stability reset request + // If the main power becomes unstable for whatever reason, + // request reset + // SEC_CM: MAIN_PD.RST.LOCAL_ESC + logic pwr_rst_req; + assign pwr_rst_req = mon_main_pok & ~main_pok_st; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rst_req_o <= '0; + end else if (clr_req_i) begin + rst_req_o <= '0; + end else begin + rst_req_o <= rst_req_o | pwr_rst_req; + end + end + + assign pwrup_cause_o = cause_q; + assign pwrup_cause_toggle_o = cause_toggle_q; + assign req_pwrup_o = req_pwrup_q; + assign ack_pwrdn_o = ack_pwrdn_q; + assign fsm_invalid_o = fsm_invalid_q; + + assign ast_o.core_clk_en = core_clk_en_q; + assign ast_o.io_clk_en = io_clk_en_q; + // usb's enable is handshake with pwr_fsm, as it can be turned on/off + // outside of the normal low power sequence + prim_flop #( + .Width(1), + .ResetValue('0) + ) u_usb_clk_en ( + .clk_i, + .rst_ni, + // immediate enable + // graceful disable when status is 0 + .d_i(usb_clk_en_q | usb_ip_clk_status_i), + .q_o(ast_o.usb_clk_en) + ); + assign usb_ip_clk_en_o = usb_clk_en_q; + + assign ast_o.main_pd_n = pd_nq; + assign ast_o.pwr_clamp_env = pwr_clamp_env_q; + assign ast_o.pwr_clamp = pwr_clamp_q; + // This is hardwired to 1 all the time + assign ast_o.slow_clk_en = 1'b1; + + + //////////////////////////// + /// Unused + //////////////////////////// + + logic unused_slow_clk_val; + assign unused_slow_clk_val = ast_i.slow_clk_val; + + //////////////////////////// + /// Assertion + //////////////////////////// + // Under normal circumstances, this should NEVER fire + // May need to add a signal to disable this check for simulation + `ASSERT(IntRstReq_A, pwr_rst_req == '0) + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_wake_info.sv b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_wake_info.sv new file mode 100644 index 0000000000000..ada62ea1d1a95 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/rtl/pwrmgr_wake_info.sv @@ -0,0 +1,74 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager Wake Information +// + +`include "prim_assert.sv" + +module pwrmgr_wake_info import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*; +( + input clk_i, + input rst_ni, + input wr_i, + input [TotalWakeWidth-1:0] data_i, + input start_capture_i, + input record_dis_i, + input [NumWkups-1:0] wakeups_i, + input fall_through_i, + input abort_i, + output pwrmgr_hw2reg_wake_info_reg_t info_o +); + + logic record_en; + + // detect rising edge of start_capture_i + logic start_capture_q1, start_capture; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + start_capture_q1 <= 1'b1; + end else begin + start_capture_q1 <= start_capture_i; + end + end + + assign start_capture = start_capture_i & ~start_capture_q1; + + // generate the record enbale signal + // HW enables the recording + // Software can suppress the recording or disable it + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + record_en <= 1'b0; + end else if (start_capture && !record_dis_i) begin + // if not disabled by software + // a recording enable puls by HW starts recording + record_en <= 1'b1; + end else if (record_dis_i && record_en) begin + // if recording is already ongoing + // a disable command by software shuts things down + record_en <= 1'b0; + end + end + + logic [TotalWakeWidth-1:0] info; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + info <= '0; + end else if (wr_i) begin + info <= info & ~data_i; // W1C + end else if (record_en) begin // If set once, hold until clear + info[0 +: NumWkups] <= info[0 +: NumWkups] | wakeups_i; + info[NumWkups +: 2] <= info[NumWkups +: 2] | {abort_i, fall_through_i}; + end + end + + // assign outputs + assign info_o.abort.d = info[NumWkups + 1]; + assign info_o.fall_through.d = info[NumWkups]; + assign info_o.reasons = info[NumWkups-1:0]; + + + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/util/reg_pwrmgr.py b/hw/top_darjeeling/ip_autogen/pwrmgr/util/reg_pwrmgr.py new file mode 100755 index 0000000000000..736fbb81f8998 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/util/reg_pwrmgr.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python3 +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +r"""Convert mako template to Hjson register description +""" +import argparse +import sys +from io import StringIO + +from mako.template import Template + + +def main(): + parser = argparse.ArgumentParser(prog="reg_pwrmgr") + parser.add_argument('input', + nargs='?', + metavar='file', + type=argparse.FileType('r'), + default=sys.stdin, + help='input template file') + parser.add_argument('--n_wkups', + type=int, + default=16, + help='Number of Wakeup sources') + + args = parser.parse_args() + + # Determine output: if stdin then stdout if not then ?? + out = StringIO() + + reg_tpl = Template(args.input.read()) + out.write( + reg_tpl.render(NumWkups=args.n_wkups)) + + print(out.getvalue()) + + out.close() + + +if __name__ == "__main__": + main() diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/BUILD b/hw/top_darjeeling/ip_autogen/rstmgr/BUILD new file mode 100644 index 0000000000000..417731a72f481 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/BUILD @@ -0,0 +1,30 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +load( + "//rules:autogen.bzl", + "autogen_hjson_c_header", + "autogen_hjson_rust_header", +) + +autogen_hjson_c_header( + name = "rstmgr_c_regs", + srcs = [ + "data/rstmgr.hjson", + ], +) + +autogen_hjson_rust_header( + name = "rstmgr_rust_regs", + srcs = [ + "data/rstmgr.hjson", + ], +) + +filegroup( + name = "all_files", + srcs = glob(["**"]), +) diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/README.md b/hw/top_darjeeling/ip_autogen/rstmgr/README.md new file mode 100644 index 0000000000000..75d81417e4c29 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/README.md @@ -0,0 +1,29 @@ +# Reset Manager HWIP Technical Specification + +[`rstmgr`](https://reports.opentitan.org/hw/top_darjeeling/ip_autogen/rstmgr/dv/latest/report.html): +![](https://dashboards.lowrisc.org/badges/dv/rstmgr/test.svg) +![](https://dashboards.lowrisc.org/badges/dv/rstmgr/passing.svg) +![](https://dashboards.lowrisc.org/badges/dv/rstmgr/functional.svg) +![](https://dashboards.lowrisc.org/badges/dv/rstmgr/code.svg) + +[`rstmgr_cnsty_chk`](https://reports.opentitan.org/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/latest/report.html): +![](https://dashboards.lowrisc.org/badges/dv/rstmgr_cnsty_chk/test.svg) +![](https://dashboards.lowrisc.org/badges/dv/rstmgr_cnsty_chk/passing.svg) +![](https://dashboards.lowrisc.org/badges/dv/rstmgr_cnsty_chk/functional.svg) +![](https://dashboards.lowrisc.org/badges/dv/rstmgr_cnsty_chk/code.svg) + +# Overview + +This document describes the functionality of the reset controller and its interaction with the rest of the OpenTitan system. + +## Features + +* Stretch incoming POR. +* Cascaded system resets. +* Peripheral system reset requests. +* RISC-V non-debug-module reset support. +* Limited and selective software controlled module reset. +* Always-on reset information register. +* Always-on alert crash dump register. +* Always-on CPU crash dump register. +* Reset consistency checks. diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr.cfg.example.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr.cfg.example.hjson new file mode 100644 index 0000000000000..028899301a0c1 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr.cfg.example.hjson @@ -0,0 +1,48 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Example configuration +{ + // Reset attributes + // name: name of reset. + // + // gen: whether the reset is generated + // 1: it is a generated reset inside rstmgr + // 0: it is a hardwired design reset inside rstmgr (roots and por) + // + // type: the reset type [ext, top] + // ext: the reset is coming in from the ports, external to earlgrey + // int: the reset is only used inside rstmgr + // top: the reset is output from rstmgr to top level struct + // + // root: The parent reset + // If type is "ext", there is no root, since it is external + // + // domain: The power domain + // If no domain, it means there is no choice, just inherits from root. + // Otherwise, selects the domain to which it is related + // 0 is defaulted for always on. + // TBD: This should eventually be changed to a name->index project wide lookup + // + // clk: related clock domain for synchronous release + // If type is "por", there is not related clock, since it is + // likely external or generated from a voltage comparator + // + resets: [ + { name: "rst_ni", gen: 0, type: "ext" } + { name: "por_aon", gen: 0, type: "top", root: "rst_ni", clk: "aon" } + { name: "lc_src", gen: 0, type: "int", root: "por", clk: "io_div2" } + { name: "sys_src", gen: 0, type: "int", root: "por", clk: "io_div2" } + { name: "por", gen: 1, type: "top", root: "por_aon", clk: "main" } + { name: "por_io", gen: 1, type: "top", root: "por_aon", clk: "io" } + { name: "por_io_div2", gen: 1, type: "top", root: "por_aon", clk: "io_div2" } + { name: "por_usb", gen: 1, type: "top", root: "por_aon", clk: "usb" } + { name: "lc", gen: 1, type: "top", domain: "0", root: "lc_src", clk: "io_div2" } + { name: "sys", gen: 1, type: "top", domain: "0", root: "sys_src", clk: "main" } + { name: "sys_io", gen: 1, type: "top", domain: "0", root: "sys_src", clk: "io_div2" } + { name: "sys_aon", gen: 1, type: "top", domain: "0", root: "sys_src", clk: "aon" } + { name: "spi_device", gen: 1, type: "top", domain: "0", root: "sys_src", clk: "io_div2", sw: 1 } + { name: "usb", gen: 1, type: "top", domain: "0", root: "sys_src", clk: "usb", sw: 1 } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr.hjson new file mode 100644 index 0000000000000..4d65f056c2046 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr.hjson @@ -0,0 +1,606 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + + + +# RSTMGR register template +# +{ + name: "rstmgr", + human_name: "Reset Manager", + one_line_desc: "Controls the on-chip reset signals, records reset cause and CPU crash dump for software", + one_paragraph_desc: ''' + Reset Manager controls the on-chip reset. + It receives one root power-on reset signal for each power domain from AST and feeds one reset signal for each on-chip reset domain to the OpenTitan hardware blocks. + Resets can be requested by Power Manager, which internally arbitrates peripheral resets, e.g., from AON Timer and Alert Handler, RISC-V Debug Module, and to a limited extent by software. + Through always-on registers, software can get information on the reset cause, as well as alert and CPU status prior to a triggered reset (crash dump). + To deter fault injection (FI) attacks, several countermeasures are implemented, including consistency checks of leaf resets and support for shadow resets. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "22", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_rstmgr", + revisions: [ + { + version: "1.0.0", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + } + ] + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {clock: "clk_aon_i"}, + {clock: "clk_io_div4_i"}, + {clock: "clk_main_i"}, + {clock: "clk_io_i"}, + {clock: "clk_io_div2_i"}, + {clock: "clk_usb_i"}, + {clock: "clk_por_i", reset: "rst_por_ni"}, + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device" } + ], + alert_list: [ + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal structural fault is detected. + Structural faults include errors such as sparse fsm errors and tlul integrity errors. + ''' + } + { name: "fatal_cnsty_fault", + desc: ''' + This fatal alert is triggered when a reset consistency fault is detected. + It is separated from the category above for clearer error collection and debug. + ''' + } + ], + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "SCAN.INTERSIG.MUBI", + desc: "scan control signals are multibit" + } + { name: "LEAF.RST.BKGN_CHK", + desc: "Background consistency checks for each leaf reset." + } + { name: "LEAF.RST.SHADOW", + desc: "Leaf resets to blocks containing shadow registers are shadowed" + } + { name: "LEAF.FSM.SPARSE", + desc: "Sparsely encoded fsm for each leaf rst check. The Hamming delta is only 3 as there are a significant number of leaf resets" + } + { name: "SW_RST.CONFIG.REGWEN", + desc: "Software reset controls are protected by regwen" + } + { name: "DUMP_CTRL.CONFIG.REGWEN", + desc: "Crash dump controls are protected by regwen" + } + ] + regwidth: "32", + scan: "true", + scan_reset: "true", + param_list: [ + { name: "RdWidth", + desc: "Read width for crash info", + type: "int", + default: "32", + local: "true" + }, + + { name: "IdxWidth", + desc: "Index width for crash info", + type: "int", + default: "4", + local: "true" + }, + + { name: "NumHwResets", + desc: "Number of hardware reset requests, inclusive of debug resets and pwrmgr's internal resets ", + type: "int", + default: "5", + local: "true" + }, + + { name: "NumSwResets", + desc: "Number of software resets", + type: "int", + default: "3", + local: "true" + }, + + { name: "NumTotalResets", + desc: "Number of total reset requests, inclusive of hw/sw, por and low power exit", + type: "int", + default: "8", + local: "true" + }, + + { name: "SecCheck", + type: "bit", + default: "1'b1", + desc: ''' + When 1, enable rstmgr reset consistency checks. + When 0, there are no consistency checks. + ''' + local: "false", + expose: "true" + }, + + { name: "SecMaxSyncDelay", + type: "int", + default: "2", + desc: ''' + The maximum synchronization delay for parent / child reset checks. + ''' + local: "false", + expose: "true" + }, + ], + features: [ + { name: "RSTMGR.SW_RST.CHIP_RESET", + desc: "Cause a reset of all but some AON and system debug blocks via CSR." + } + { name: "RSTMGR.SW_RST.SPI_DEVICE_REQUEST", + desc: "Trigger reset of SPI_DEVICE peripheral via CSR." + } + { name: "RSTMGR.SW_RST.SPI_DEVICE_ENABLE", + desc: "Enable reset of SPI_DEVICE peripheral via CSR." + } + { name: "RSTMGR.SW_RST.SPI_HOST0_REQUEST", + desc: "Trigger reset of SPI_HOST0 peripheral via CSR." + } + { name: "RSTMGR.SW_RST.SPI_HOST0_ENABLE", + desc: "Enable reset of SPI_HOST0 peripheral via CSR." + } + { name: "RSTMGR.SW_RST.I2C0_REQUEST", + desc: "Trigger reset of I2C0 peripheral via CSR." + } + { name: "RSTMGR.SW_RST.I2C0_ENABLE", + desc: "Enable reset of I2C0 peripheral via CSR." + } + { name: "RSTMGR.RESET_INFO.CAPTURE", + desc: "Capture information about the causes of a reset." + } + { name: "RSTMGR.RESET_INFO.CLEAR", + desc: "Clear information about the causes of a reset." + } + { name: "RSTMGR.ALERT_INFO.CAPTURE", + desc: "Capture alert crash dump information upon reset." + } + { name: "RSTMGR.ALERT_INFO.ENABLE", + desc: "Enable capture of alert crash dump information." + } + { name: "RSTMGR.CPU_INFO.CAPTURE", + desc: "Capture cpu crash dump information upon reset." + } + { name: "RSTMGR.CPU_INFO.ENABLE", + desc: "Enable capture of cpu crash dump information." + } + { name: "RSTMGR.ALERT_HANDLER.RESET_STATUS", + desc: "Inform alert handler about reset enable status for each reset." + } + ] + // Define rstmgr struct package + inter_signal_list: [ + { struct: "logic", + type: "uni", + name: "por_n", + act: "rcv", + width: "2" + desc: ''' + Root power on reset signals from ast. + There is one root reset signal for each core power domain. + ''' + }, + + { struct: "pwr_rst", // pwr_rst_req_t, pwr_rst_rsp_t + type: "req_rsp", + name: "pwr", // resets_o (req), resets_i (rsp) + act: "rsp", + desc: ''' + Reset request signals from power manager. + Power manager can request for specific domains of the lc/sys reset tree to assert. + ''' + }, + + { struct: "rstmgr_out", + type: "uni", + name: "resets", + act: "req", + package: "rstmgr_pkg", // Origin package (only needs for the req) + desc: ''' + Leaf resets fed to the system. + ''' + }, + + { struct: "rstmgr_rst_en", + type: "uni", + name: "rst_en", + act: "req", + package: "rstmgr_pkg", // Origin package (only needs for the req) + desc: ''' + Low-power-group outputs used by alert handler. + ''' + }, + + { struct: "alert_crashdump", + type: "uni", + name: "alert_dump", + act: "rcv", + package: "alert_pkg", + desc: ''' + Alert handler crash dump information. + ''' + }, + + { struct: "cpu_crash_dump", + type: "uni", + name: "cpu_dump", + act: "rcv", + package: "rv_core_ibex_pkg", + desc: ''' + Main processing element crash dump information. + ''' + }, + + { struct: "mubi4", + type: "uni", + name: "sw_rst_req", + act: "req", + package: "prim_mubi_pkg", + desc: ''' + Software requested system reset to pwrmgr. + ''' + }, + + // Exported resets + ], + + registers: [ + + { name: "RESET_REQ", + desc: ''' + Software requested system reset. + ''', + swaccess: "rw", + hwaccess: "hrw", + fields: [ + { bits: "3:0", + mubi: true + name: "VAL", + desc: ''' + When set to kMultiBitBool4True, a reset to power manager is requested. + Upon completion of reset, this bit is automatically cleared by hardware. + ''' + resval: false + }, + ], + tags: [// This register will cause a system reset, directed test only + "excl:CsrAllTests:CsrExclWrite"] + }, + + { name: "RESET_INFO", + desc: ''' + Device reset reason. + ''', + swaccess: "rw1c", + hwaccess: "hwo", + sync: "clk_por_i", + fields: [ + { bits: "0", + hwaccess: "none", + name: "POR", + desc: ''' + Indicates when a device has reset due to power up. + ''' + resval: "1" + }, + + { bits: "1", + name: "LOW_POWER_EXIT", + desc: ''' + Indicates when a device has reset due low power exit. + ''' + resval: "0" + }, + + { bits: "2", + hwaccess: "hrw", + name: "SW_RESET", + desc: ''' + Indicates when a device has reset due to !!RESET_REQ. + ''' + resval: "0" + }, + + // reset requests include escalation reset, main power glitch, + // ndm reset request + other peripheral requests + { bits: "7:3", + hwaccess: "hrw", + name: "HW_REQ", + desc: ''' + Indicates when a device has reset due to a hardware requested reset. + The bit mapping is as follows: + b3: aon_timer_aon: watchdog reset requestt + b4: soc_proxy: External reset request + b5: pwrmgr_aon: main power glitch reset request + b6: alert_handler: escalation reset request + b7: rv_dm: non-debug-module reset request + ''' + resval: "0" + }, + ] + }, + + { name: "ALERT_REGWEN", + desc: "Alert write enable", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + name: "EN", + resval: "1" + desc: ''' + When 1, !!ALERT_INFO_CTRL can be modified. + ''' + }, + ] + } + + { name: "ALERT_INFO_CTRL", + desc: ''' + Alert info dump controls. + ''', + swaccess: "rw", + hwaccess: "hro", + sync: "clk_por_i", + regwen: "ALERT_REGWEN", + fields: [ + { bits: "0", + name: "EN", + hwaccess: "hrw", + desc: ''' + Enable alert dump to capture new information. + This field is automatically set to 0 upon system reset (even if rstmgr is not reset). + ''' + resval: "0" + }, + + { bits: "4+IdxWidth-1:4", + name: "INDEX", + desc: ''' + Controls which 32-bit value to read. + ''' + resval: "0" + }, + ] + }, + + { name: "ALERT_INFO_ATTR", + desc: ''' + Alert info dump attributes. + ''', + swaccess: "ro", + hwaccess: "hwo", + sync: "clk_por_i", + hwext: "true", + fields: [ + { bits: "IdxWidth-1:0", + name: "CNT_AVAIL", + swaccess: "ro", + hwaccess: "hwo", + desc: ''' + The number of 32-bit values contained in the alert info dump. + ''' + resval: "0", + tags: [// This field is tied to a design constant, thus the + // default value is never 0. Since there is not a way + // to express this behavior at the moment, exclude from automated checks. + "excl:CsrAllTests:CsrExclCheck"] + }, + ] + }, + + { name: "ALERT_INFO", + desc: ''' + Alert dump information prior to last reset. + Which value read is controlled by the !!ALERT_INFO_CTRL register. + ''', + swaccess: "ro", + hwaccess: "hwo", + sync: "clk_por_i", + hwext: "true", + fields: [ + { bits: "31:0", + name: "VALUE", + desc: ''' + The current 32-bit value of crash dump. + ''' + resval: "0", + }, + ] + }, + { name: "CPU_REGWEN", + desc: "Cpu write enable", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + name: "EN", + resval: "1" + desc: ''' + When 1, !!CPU_INFO_CTRL can be modified. + ''' + }, + ] + } + + { name: "CPU_INFO_CTRL", + desc: ''' + Cpu info dump controls. + ''', + swaccess: "rw", + hwaccess: "hro", + sync: "clk_por_i", + regwen: "CPU_REGWEN", + fields: [ + { bits: "0", + name: "EN", + hwaccess: "hrw", + desc: ''' + Enable cpu dump to capture new information. + This field is automatically set to 0 upon system reset (even if rstmgr is not reset). + ''' + resval: "0" + }, + + { bits: "4+IdxWidth-1:4", + name: "INDEX", + desc: ''' + Controls which 32-bit value to read. + ''' + resval: "0" + }, + ] + }, + + { name: "CPU_INFO_ATTR", + desc: ''' + Cpu info dump attributes. + ''', + swaccess: "ro", + hwaccess: "hwo", + sync: "clk_por_i", + hwext: "true", + fields: [ + { bits: "IdxWidth-1:0", + name: "CNT_AVAIL", + swaccess: "ro", + hwaccess: "hwo", + desc: ''' + The number of 32-bit values contained in the cpu info dump. + ''' + resval: "0", + tags: [// This field is tied to a design constant, thus the + // default value is never 0. Since there is not a way + // to express this behavior at the moment, exclude from automated checks. + "excl:CsrAllTests:CsrExclCheck"] + }, + ] + }, + + { name: "CPU_INFO", + desc: ''' + Cpu dump information prior to last reset. + Which value read is controlled by the !!CPU_INFO_CTRL register. + ''', + swaccess: "ro", + hwaccess: "hwo", + sync: "clk_por_i", + hwext: "true", + fields: [ + { bits: "31:0", + name: "VALUE", + desc: ''' + The current 32-bit value of crash dump. + ''' + resval: "0", + }, + ] + }, + + + # Templated registers for software control + + { multireg: { + cname: "RSTMGR_SW_RST", + name: "SW_RST_REGWEN", + desc: ''' + Register write enable for software controllable resets. + When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. + When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed. + ''', + count: "NumSwResets", + swaccess: "rw0c", + hwaccess: "none", + compact: false, + fields: [ + { + bits: "0", + name: "EN", + desc: "Register write enable for software controllable resets", + resval: "1", + }, + ], + } + } + + { multireg: { + cname: "RSTMGR_SW_RST", + name: "SW_RST_CTRL_N", + desc: ''' + Software controllable resets. + When a particular bit value is 0, the corresponding module is held in reset. + When a particular bit value is 1, the corresponding module is not held in reset. + ''', + count: "NumSwResets", + swaccess: "rw", + hwaccess: "hro", + regwen: "SW_RST_REGWEN", + regwen_multi: true, + fields: [ + { + bits: "0", + name: "VAL", + desc: "Software reset value", + resval: "1", + }, + ], + tags: [// Don't reset other IPs as it will affect CSR access on these IPs. + // In addition, rapid flips of these bits can occasionally cause the reset + // consistency checkers to trigger alerts, which also update err_code bits. + "excl:CsrAllTests:CsrExclWrite"] + } + } + + { name: "ERR_CODE", + desc: ''' + A bit vector of all the errors that have occurred in reset manager + ''', + swaccess: "ro", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "REG_INTG_ERR", + desc: ''' + The register file has experienced an integrity error. + ''' + resval: "0" + }, + + { bits: "1", + name: "RESET_CONSISTENCY_ERR", + desc: ''' + A inconsistent parent / child reset was observed. + ''' + resval: "0" + }, + + { bits: "2", + name: "FSM_ERR", + desc: ''' + Sparsely encoded fsm error. + ''' + resval: "0" + }, + + ] + }, + ] +} diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr_sec_cm_testplan.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr_sec_cm_testplan.hjson new file mode 100644 index 0000000000000..096bd7f57771e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr_sec_cm_testplan.hjson @@ -0,0 +1,108 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../rstmgr/data/rstmgr.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../rstmgr/data/rstmgr_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: '''Verify the countermeasure(s) BUS.INTEGRITY. + This entry is covered by tl_access_test. + ''' + stage: V2S + tests: ["rstmgr_tl_intg_err"] + } + { + name: sec_cm_scan_intersig_mubi + desc: '''Verify the countermeasure(s) SCAN.INTERSIG.MUBI. + + **Stimulus**: + Same as smoke test but drive scanmode_i with a constant invalid + value during the test. + + **Check**: + If dut accepts any of invalid values, test will fail by turning dut to scanmode. + ''' + stage: V2S + tests: ["rstmgr_sec_cm_scan_intersig_mubi"] + } + { + name: sec_cm_leaf_rst_bkgn_chk + desc: '''Verify the countermeasure(s) LEAF.RST.BKGN_CHK. + + ** Stimulus**: + Execute a series of reset event - lowpower, hwreq, and + sw reset -. And at the beginning of these events, create + reset consistency error to one of 25 leaf modules. + (exclude u_daon_por_io_div4 and u_daon_por_io_div4_shadowed, + see #11858, #12729 for details) + Do the same test for all 25 modules. + + **Check**: + Upon asserting each reset consistency error, + check alert_fatal_cnsty_fault is asserted. + ''' + stage: V2S + tests: ["rstmgr_leaf_rst_cnsty"] + } + { + name: sec_cm_leaf_rst_shadow + desc: '''Verify the countermeasure(s) LEAF.RST.SHADOW. + After power up, create glitch to a shadow leaf reset module. + Check if normal leaf reset module is not triggerred. + Do over all {shadow, normal} leaf reset module pairs + ''' + stage: V2S + tests: ["rstmgr_leaf_rst_shadow_attack"] + } + { + name: sec_cm_leaf_fsm_sparse + desc: '''Verify the countermeasure(s) LEAF.FSM.SPARSE. + + Force leaf rst check state to illegal value. + This is triggered by common cm primitives + ''' + stage: V2S + tests: ["rstmgr_sec_cm"] + } + { + name: sec_cm_sw_rst_config_regwen + desc: '''Verify the countermeasure(s) SW_RST.CONFIG.REGWEN. + + RSTMGR.SW_RST_CTRL_N. + This is covered by auto csr test. + ''' + stage: V2S + tests: ["rstmgr_csr_rw"] + } + { + name: sec_cm_dump_ctrl_config_regwen + desc: '''Verify the countermeasure(s) DUMP_CTRL.CONFIG.REGWEN. + + RSTMGR.ALERT_INFO_CTRL and RSTMGR.CPU_INFO_CTRL + This is covered by auto csr test. + ''' + stage: V2S + tests: ["rstmgr_csr_rw"] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr_testplan.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr_testplan.hjson new file mode 100644 index 0000000000000..be44e83d038f4 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr_testplan.hjson @@ -0,0 +1,247 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "rstmgr" + import_testplans: ["hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson", + "rstmgr_sec_cm_testplan.hjson"] + + testpoints: [ + { + name: smoke + desc: ''' + Smoke test accessing a major datapath within the rstmgr. + + Checks the behavior of rstmgr when receiving various reset requests. + + **Stimulus**: + - Send a scan reset. + - Send a low power entry reset. + - Send a peripheral reset request. + - Send a debug reset. + - Configure a software request for peripheral reset. + - Set alert and cpu dump inputs to random values. + + **Checks**: + - Checks the reset_info matches expected values. + - Checks the `alert_info` CSR correctly captures the input info. + - Checks the `cpu_info` CSR correctly captures the input info. + - Checks the output reset pins corresponding to sw resettable + units match `sw_rst_ctrl_n` CSR. + ''' + stage: V1 + tests: ["rstmgr_smoke"] + } + { + name: reset_stretcher + desc: '''Test the POR reset signal must be stable for multiple cycles. + + The POR reset signal must remain active for at least 32 consecutive + cycles before going inactive for the rest of the reset tree to go + inactive. + + **Stimulus**: + - Activate POR, and de-activate it at a random width less than 32 + cycles between de-activations for N de-activations. + + **Checks**: + - With SVA check the output reset is only set if the input reset + has had at least 32 cycles of steady input reset active. + ''' + stage: V2 + tests: ["rstmgr_por_stretcher"] + } + { + name: sw_rst + desc: '''Test the sw_rst functionality. + + The `sw_rst_regwen` and `sw_rst_ctrl_n` CSRs control the specific + reset outputs to peripherals in the following sequence: + - Test all `sw_rst_ctrl_n` bits when `sw_rst_regwen` is all 1's. + - Clear each `sw_rst_regwen` bit to verify the corresponding resets + are masked. + + **Stimulus**: + - Write `sw_rst_ctrl_n` CSR with random values when regwen is all 1's. + - Clear each `sw_rst_regwen` bit and write `sw_rst_ctrl_n` CSR with + all 0's. + - After each regwen bit check set `sw_rst_ctrl_n` to all 1's. + + **Checks**: + - Check that the zero bits in `sw_rst_ctrl_n` enabled by + `sw_rst_regwen` cause the respective resets to become active. + - Check that the zero bits in `sw_rst_ctrl_n` disabled by + `sw_rst_regwen` have no effect on resets. + - Check the `reset_info`, `cpu_info`, and `alert_info` CSRs are not modified. + ''' + stage: V2 + tests: ["rstmgr_sw_rst"] + } + { + name: sw_rst_reset_race + desc: '''Test sw_rst and reset close in time. + + Sends sw_rst and regular resets in close temporal proximity. + + **Stimulus**: + - Write `sw_rst_ctrl_n` CSR with random values when regwen is all 1's. + - Send a hardware reset. + - Release resets. + + **Checks**: + - Check the `reset_info` CSR. + - Reset behavior is checked by SVA. + ''' + stage: V2 + tests: ["rstmgr_sw_rst_reset_race"] + } + { + name: reset_info + desc: '''Test the reporting of reset reason. + + **Stimulus**: + - Generate the different resets recorded in `reset_info` CSR. + - Randomly clear `reset_info` (it is rw1c). + + **Checks**: + - The resulting setting of `reset_info` is as expected. + - Each bit was set at least once. + - Each bit was cleared at least once. + ''' + stage: V2 + tests: ["rstmgr_reset"] + } + { + name: cpu_info + desc: '''Test the cpu_info recording. + + The `cpu_info` CSR register(s) can capture the contents of the + `cpu_dump_i` input when resets happen and it is enabled. + + **Stimulus**: + - Regularly modify the `cpu_dump_i` input. + - With `cpu_regwen` on, randomly set `cpu_info_ctrl.en` to control + whether the dump should be captured. + - Generate reset(s) as in `smoke` testpoint. + + **Checks**: + - Verify the `cpu_info` is only captured when enabled. + - Verify the `cpu_info` contents at each `cpu_info_ctrl.index` + matches the expected value. + ''' + stage: V2 + tests: ["rstmgr_reset"] + } + { + name: alert_info + desc: '''Test the alert_info recording. + + The `alert_info` CSR register(s) can capture the contents of the + `alert_dump_i` input when resets happen and it is enabled. + + **Stimulus**: + - Regularly modify the `alert_dump_i` input. + - With `alert_regwen` on, randomly set `alert_info_ctrl.en` to + control whether the dump should be captured. + - Generate reset(s) as in `smoke` testpoint. + + **Checks**: + - Verify the `alert_info` is only captured when enabled. + - Verify the `alert_info` contents at each `alert_info_ctrl.index` + matches the expected value. + ''' + stage: V2 + tests: ["rstmgr_reset"] + } + { + name: reset_info_capture + desc: '''Test the capture blocking effect of rst_cpu_n input. + + After an AON reset reset capture is blocked until the input + rst_cpu_n goes inactive. + + **Stimulus**: + - Wait for a random number of resets before setting rst_cpu_n + inactive. + + **Checks**: + - Non-AON resets prior to this event don't capture. + ''' + stage: V2 + tests: ["rstmgr_reset"] + } + { + name: stress_all + desc: '''This runs random tests sequentially. + + Stress with the following sequences: + - rstmgr_reset_vseq + - rstmgr_smoke_vseq + - rstmgr_sw_rst_vseq + ''' + stage: V2 + tests: ["rstmgr_stress_all"] + } + ] + + covergroups: [ + { + name: reset_stretcher_cg + desc: '''Collects coverage on the reset_stretcher functionality. + + The stretcher counter is reset when por_n_i is not stable. + Collect both the count at the point of instability, and the + number of times the counter was reset. + ''' + } + { + name: alert_info_capture_cg + desc: '''Collects coverage on reset type and enable when reset occurs. + + Uses `reset_cp` that records the reset encoded as in `reset_info` + CSR, and `ctrl_en_cp` capturing `alert_info_ctrl.en` CSR, and + creates the per-reset_cp bit cross. + ''' + } + { + name: alert_info_access_cg + desc: '''Collects coverage on the reads of alert_info. + + This captures `alert_info_ctrl.index` CSR to verify all fields + of alert_info have been read. + ''' + } + { + name: cpu_info_capture_cg + desc: '''Collects coverage on the reset and enable when reset occurs. + + Uses `reset_cp` that records the reset encoded as in `reset_info` + CSR, and `ctrl_en_cp` capturing `cpu_info_ctrl.en` CSR, and creates + the per-reset_cp bit cross. + ''' + } + { + name: cpu_info_access_cg + desc: '''Collects coverage on the reads of cpu_info. + + This captures `cpu_info_ctrl.index` CSR to verify all fields + of cpu_info have been read. + ''' + } + { + name: sw_rst_cg + desc: '''Collects coverage on the software reset functionality. + + Each bit of the pair `sw_rst_regwen` and `sw_rst_ctrl_n` CSRs + independently control if the corresponding output reset is + activated. + This collects one coverpoint for each, and their cross. + ''' + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson new file mode 100644 index 0000000000000..ebf8a8bb11340 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson @@ -0,0 +1,548 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_rstmgr + param_values: + { + clks: + [ + aon + io_div4 + main + io + io_div2 + usb + ] + reqs: + { + peripheral: + [ + { + name: aon_timer_rst_req + width: "1" + module: aon_timer_aon + desc: watchdog reset requestt + } + { + name: rst_req_external + width: "1" + module: soc_proxy + desc: External reset request + } + ] + int: + [ + { + name: MainPwr + desc: main power glitch reset request + module: pwrmgr_aon + } + { + name: Esc + desc: escalation reset request + module: alert_handler + } + ] + debug: + [ + { + name: Ndm + desc: non-debug-module reset request + module: rv_dm + } + ] + } + power_domains: + [ + Aon + "0" + ] + num_rstreqs: 2 + sw_rsts: + [ + spi_device + spi_host0 + i2c0 + ] + output_rsts: + [ + { + name: por_aon + gen: false + type: top + domains: + [ + "0" + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_aon_n + clock: aon + } + { + name: por + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_n + parent: por_aon + clock: main + } + { + name: por_io + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_n + parent: por_aon + clock: io + } + { + name: por_io_div2 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_div2_n + parent: por_aon + clock: io_div2 + } + { + name: por_io_div4 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_div4_n + parent: por_aon + clock: io_div4 + } + { + name: por_usb + gen: true + type: top + domains: + [ + Aon + "0" + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_usb_n + parent: por_aon + clock: usb + } + { + name: lc + gen: true + type: top + domains: + [ + "0" + Aon + ] + shadowed: true + sw: false + path: rstmgr_aon_resets.rst_lc_n + parent: lc_src + clock: main + } + { + name: lc_aon + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_aon_n + parent: lc_src + clock: aon + } + { + name: lc_io + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_io_n + parent: lc_src + clock: io + } + { + name: lc_io_div2 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_io_div2_n + parent: lc_src + clock: io_div2 + } + { + name: lc_io_div4 + gen: true + type: top + domains: + [ + "0" + Aon + ] + shadowed: true + sw: false + path: rstmgr_aon_resets.rst_lc_io_div4_n + parent: lc_src + clock: io_div4 + } + { + name: lc_usb + gen: true + type: top + domains: + [ + Aon + "0" + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_usb_n + parent: lc_src + clock: usb + } + { + name: sys + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_sys_n + parent: sys_src + clock: main + } + { + name: sys_io_div4 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_sys_io_div4_n + parent: sys_src + clock: io_div4 + } + { + name: spi_device + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_spi_device_n + parent: lc_src + clock: io_div4 + } + { + name: spi_host0 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_spi_host0_n + parent: lc_src + clock: io_div4 + } + { + name: i2c0 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_i2c0_n + parent: lc_src + clock: io_div4 + } + ] + leaf_rsts: + [ + { + name: por + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_n + parent: por_aon + clock: main + } + { + name: por_io + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_n + parent: por_aon + clock: io + } + { + name: por_io_div2 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_div2_n + parent: por_aon + clock: io_div2 + } + { + name: por_io_div4 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_div4_n + parent: por_aon + clock: io_div4 + } + { + name: por_usb + gen: true + type: top + domains: + [ + Aon + "0" + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_usb_n + parent: por_aon + clock: usb + } + { + name: lc + gen: true + type: top + domains: + [ + "0" + Aon + ] + shadowed: true + sw: false + path: rstmgr_aon_resets.rst_lc_n + parent: lc_src + clock: main + } + { + name: lc_aon + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_aon_n + parent: lc_src + clock: aon + } + { + name: lc_io + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_io_n + parent: lc_src + clock: io + } + { + name: lc_io_div2 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_io_div2_n + parent: lc_src + clock: io_div2 + } + { + name: lc_io_div4 + gen: true + type: top + domains: + [ + "0" + Aon + ] + shadowed: true + sw: false + path: rstmgr_aon_resets.rst_lc_io_div4_n + parent: lc_src + clock: io_div4 + } + { + name: lc_usb + gen: true + type: top + domains: + [ + Aon + "0" + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_usb_n + parent: lc_src + clock: usb + } + { + name: sys + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_sys_n + parent: sys_src + clock: main + } + { + name: sys_io_div4 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_sys_io_div4_n + parent: sys_src + clock: io_div4 + } + { + name: spi_device + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_spi_device_n + parent: lc_src + clock: io_div4 + } + { + name: spi_host0 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_spi_host0_n + parent: lc_src + clock: io_div4 + } + { + name: i2c0 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_i2c0_n + parent: lc_src + clock: io_div4 + } + ] + rst_ni: lc_io_div4 + export_rsts: {} + topname: darjeeling + } +} diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/doc/checklist.md b/hw/top_darjeeling/ip_autogen/rstmgr/doc/checklist.md new file mode 100644 index 0000000000000..1e01155675d9d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/doc/checklist.md @@ -0,0 +1,266 @@ +# RSTMGR Checklist + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [RSTMGR peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done | [RSTMGR Design Spec](../README.md) +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | NA | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Done | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. +Documentation | [MISSING_FUNC][] | Done | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | +RTL | [STYLE_X][] | Done | +RTL | [CDC_SYNCMACRO][] | Done | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [AREA_CHECK][] | Done | +Code Quality | [TIMING_CHECK][] | Done | +Security | [SEC_CM_DOCUMENTED][] | Done | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | N/A | +Security | [SEC_CM_NON_RESET_FLOPS][] | Done | +Security | [SEC_CM_SHADOW_REGS][] | Done | +Security | [SEC_CM_RTL_REVIEWED][] | Done | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Done | + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Done | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | With waivers approved by TC on 2024-08-08 +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_RTL][] | Done | +Review | [REVIEW_DELETED_FF][] | Done | +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | matutem@, vogelpi@, adk@ +Review | Signoff date | Done | 2024-08-08 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [RSTMGR DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Done | [RSTMGR Testplan](../dv/README.md#testplan) +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | Done | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | Done | +Tests | [SIM_SMOKE_TEST_PASSING][] | Done | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done | Block has no mem +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | Xcelium +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done | +Regression | [FPV_REGRESSION_SETUP][] | N/A | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Done | +Review | [DESIGN_SPEC_REVIEWED][] | Done | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exception: power, performance +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Done | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | Done | +Tests | [SIM_ALL_TESTS_PASSING][] | Done | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | N/A | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | N/A | +Tests | [SIM_FW_SIMULATED][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Done | +Coverage | [SIM_CODE_COVERAGE_V2][] | Done | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Done | +Coverage | [FPV_CODE_COVERAGE_V2][] | N/A | +Coverage | [FPV_COI_COVERAGE_V2][] | N/A | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Done | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done | +Tests | [FPV_SEC_CM_VERIFIED][] | Done | +Tests | [SIM_SEC_CM_VERIFIED][] | Done | +Coverage | [SIM_COVERAGE_REVIEWED][] | Done | +Review | [SEC_CM_DV_REVIEWED][] | Done | + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/doc/interfaces.md b/hw/top_darjeeling/ip_autogen/rstmgr/doc/interfaces.md new file mode 100644 index 0000000000000..330b536aef16a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/doc/interfaces.md @@ -0,0 +1,55 @@ +# Hardware Interfaces + + +The following table lists the instantiation parameters of `rstmgr`. + +Parameter | Default | Description +----------------------------|---------------|--------------- +`SecCheck` | 1 | Enables reset consistency checks on the leaf reset. Each check contains a small FSM. +`SecMaxSyncDelay` | 2 | The default synchronization delay assumptions used in reset consistency checks. If a design uses a sync cell with more stages of delay, that value should be supplied. + + + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`rstmgr`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: **`clk_aon_i`**, **`clk_io_div4_i`**, **`clk_main_i`**, **`clk_io_i`**, **`clk_io_div2_i`**, **`clk_usb_i`**, **`clk_por_i`** +- Bus Device Interfaces (TL-UL): **`tl`** +- Bus Host Interfaces (TL-UL): *none* +- Peripheral Pins for Chip IO: *none* +- Interrupts: *none* + +## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:------------|:---------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------| +| por_n | logic | uni | rcv | 2 | Root power on reset signals from ast. There is one root reset signal for each core power domain. | +| pwr | pwr_rst | req_rsp | rsp | 1 | Reset request signals from power manager. Power manager can request for specific domains of the lc/sys reset tree to assert. | +| resets | rstmgr_pkg::rstmgr_out | uni | req | 1 | Leaf resets fed to the system. | +| rst_en | rstmgr_pkg::rstmgr_rst_en | uni | req | 1 | Low-power-group outputs used by alert handler. | +| alert_dump | alert_pkg::alert_crashdump | uni | rcv | 1 | Alert handler crash dump information. | +| cpu_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | rcv | 1 | Main processing element crash dump information. | +| sw_rst_req | prim_mubi_pkg::mubi4 | uni | req | 1 | Software requested system reset to pwrmgr. | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | + +## Security Alerts + +| Alert Name | Description | +|:------------------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------| +| fatal_fault | This fatal alert is triggered when a fatal structural fault is detected. Structural faults include errors such as sparse fsm errors and tlul integrity errors. | +| fatal_cnsty_fault | This fatal alert is triggered when a reset consistency fault is detected. It is separated from the category above for clearer error collection and debug. | + +## Security Countermeasures + +| Countermeasure ID | Description | +|:-------------------------------|:---------------------------------------------------------------------------------------------------------------------------| +| RSTMGR.BUS.INTEGRITY | End-to-end bus integrity scheme. | +| RSTMGR.SCAN.INTERSIG.MUBI | scan control signals are multibit | +| RSTMGR.LEAF.RST.BKGN_CHK | Background consistency checks for each leaf reset. | +| RSTMGR.LEAF.RST.SHADOW | Leaf resets to blocks containing shadow registers are shadowed | +| RSTMGR.LEAF.FSM.SPARSE | Sparsely encoded fsm for each leaf rst check. The Hamming delta is only 3 as there are a significant number of leaf resets | +| RSTMGR.SW_RST.CONFIG.REGWEN | Software reset controls are protected by regwen | +| RSTMGR.DUMP_CTRL.CONFIG.REGWEN | Crash dump controls are protected by regwen | + + + diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/doc/programmers_guide.md b/hw/top_darjeeling/ip_autogen/rstmgr/doc/programmers_guide.md new file mode 100644 index 0000000000000..8f46814c81ca8 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/doc/programmers_guide.md @@ -0,0 +1,5 @@ +# Programmer's Guide + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_rstmgr.h) diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/doc/registers.md b/hw/top_darjeeling/ip_autogen/rstmgr/doc/registers.md new file mode 100644 index 0000000000000..cd958b0d9755d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/doc/registers.md @@ -0,0 +1,316 @@ +# Registers + + +## Summary + +| Name | Offset | Length | Description | +|:---------------------------------------------|:---------|---------:|:-------------------------------------------------------------------| +| rstmgr.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | +| rstmgr.[`RESET_REQ`](#reset_req) | 0x4 | 4 | Software requested system reset. | +| rstmgr.[`RESET_INFO`](#reset_info) | 0x8 | 4 | Device reset reason. | +| rstmgr.[`ALERT_REGWEN`](#alert_regwen) | 0xc | 4 | Alert write enable | +| rstmgr.[`ALERT_INFO_CTRL`](#alert_info_ctrl) | 0x10 | 4 | Alert info dump controls. | +| rstmgr.[`ALERT_INFO_ATTR`](#alert_info_attr) | 0x14 | 4 | Alert info dump attributes. | +| rstmgr.[`ALERT_INFO`](#alert_info) | 0x18 | 4 | Alert dump information prior to last reset. | +| rstmgr.[`CPU_REGWEN`](#cpu_regwen) | 0x1c | 4 | Cpu write enable | +| rstmgr.[`CPU_INFO_CTRL`](#cpu_info_ctrl) | 0x20 | 4 | Cpu info dump controls. | +| rstmgr.[`CPU_INFO_ATTR`](#cpu_info_attr) | 0x24 | 4 | Cpu info dump attributes. | +| rstmgr.[`CPU_INFO`](#cpu_info) | 0x28 | 4 | Cpu dump information prior to last reset. | +| rstmgr.[`SW_RST_REGWEN_0`](#sw_rst_regwen) | 0x2c | 4 | Register write enable for software controllable resets. | +| rstmgr.[`SW_RST_REGWEN_1`](#sw_rst_regwen) | 0x30 | 4 | Register write enable for software controllable resets. | +| rstmgr.[`SW_RST_REGWEN_2`](#sw_rst_regwen) | 0x34 | 4 | Register write enable for software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_0`](#sw_rst_ctrl_n) | 0x38 | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_1`](#sw_rst_ctrl_n) | 0x3c | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_2`](#sw_rst_ctrl_n) | 0x40 | 4 | Software controllable resets. | +| rstmgr.[`ERR_CODE`](#err_code) | 0x44 | 4 | A bit vector of all the errors that have occurred in reset manager | + +## ALERT_TEST +Alert Test Register +- Offset: `0x0` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_cnsty_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------------|:-------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | wo | 0x0 | fatal_cnsty_fault | Write 1 to trigger one alert event of this kind. | +| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | + +## RESET_REQ +Software requested system reset. +- Offset: `0x4` +- Reset default: `0x9` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3:0 | rw | 0x9 | VAL | When set to kMultiBitBool4True, a reset to power manager is requested. Upon completion of reset, this bit is automatically cleared by hardware. | + +## RESET_INFO +Device reset reason. +- Offset: `0x8` +- Reset default: `0x1` +- Reset mask: `0xff` + +### Fields + +```wavejson +{"reg": [{"name": "POR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "LOW_POWER_EXIT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "SW_RESET", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "HW_REQ", "bits": 5, "attr": ["rw1c"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:----------------------------------------------| +| 31:8 | | | Reserved | +| 7:3 | rw1c | 0x0 | [HW_REQ](#reset_info--hw_req) | +| 2 | rw1c | 0x0 | [SW_RESET](#reset_info--sw_reset) | +| 1 | rw1c | 0x0 | [LOW_POWER_EXIT](#reset_info--low_power_exit) | +| 0 | rw1c | 0x1 | [POR](#reset_info--por) | + +### RESET_INFO . HW_REQ +Indicates when a device has reset due to a hardware requested reset. +The bit mapping is as follows: +b3: aon_timer_aon: watchdog reset requestt +b4: soc_proxy: External reset request +b5: pwrmgr_aon: main power glitch reset request +b6: alert_handler: escalation reset request +b7: rv_dm: non-debug-module reset request + +### RESET_INFO . SW_RESET +Indicates when a device has reset due to [`RESET_REQ.`](#reset_req) + +### RESET_INFO . LOW_POWER_EXIT +Indicates when a device has reset due low power exit. + +### RESET_INFO . POR +Indicates when a device has reset due to power up. + +## ALERT_REGWEN +Alert write enable +- Offset: `0xc` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, [`ALERT_INFO_CTRL`](#alert_info_ctrl) can be modified. | + +## ALERT_INFO_CTRL +Alert info dump controls. +- Offset: `0x10` +- Reset default: `0x0` +- Reset mask: `0xf1` +- Register enable: [`ALERT_REGWEN`](#alert_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "INDEX", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------| +| 31:8 | | | | Reserved | +| 7:4 | rw | 0x0 | INDEX | Controls which 32-bit value to read. | +| 3:1 | | | | Reserved | +| 0 | rw | 0x0 | EN | Enable alert dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset). | + +## ALERT_INFO_ATTR +Alert info dump attributes. +- Offset: `0x14` +- Reset default: `0x0` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "CNT_AVAIL", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3:0 | ro | 0x0 | CNT_AVAIL | The number of 32-bit values contained in the alert info dump. | + +## ALERT_INFO + Alert dump information prior to last reset. + Which value read is controlled by the [`ALERT_INFO_CTRL`](#alert_info_ctrl) register. +- Offset: `0x18` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "VALUE", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------| +| 31:0 | ro | 0x0 | VALUE | The current 32-bit value of crash dump. | + +## CPU_REGWEN +Cpu write enable +- Offset: `0x1c` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, [`CPU_INFO_CTRL`](#cpu_info_ctrl) can be modified. | + +## CPU_INFO_CTRL +Cpu info dump controls. +- Offset: `0x20` +- Reset default: `0x0` +- Reset mask: `0xf1` +- Register enable: [`CPU_REGWEN`](#cpu_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "INDEX", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------| +| 31:8 | | | | Reserved | +| 7:4 | rw | 0x0 | INDEX | Controls which 32-bit value to read. | +| 3:1 | | | | Reserved | +| 0 | rw | 0x0 | EN | Enable cpu dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset). | + +## CPU_INFO_ATTR +Cpu info dump attributes. +- Offset: `0x24` +- Reset default: `0x0` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "CNT_AVAIL", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3:0 | ro | 0x0 | CNT_AVAIL | The number of 32-bit values contained in the cpu info dump. | + +## CPU_INFO + Cpu dump information prior to last reset. + Which value read is controlled by the [`CPU_INFO_CTRL`](#cpu_info_ctrl) register. +- Offset: `0x28` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "VALUE", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------| +| 31:0 | ro | 0x0 | VALUE | The current 32-bit value of crash dump. | + +## SW_RST_REGWEN +Register write enable for software controllable resets. +When a particular bit value is 0, the corresponding value in [`SW_RST_CTRL_N`](#sw_rst_ctrl_n) can no longer be changed. +When a particular bit value is 1, the corresponding value in [`SW_RST_CTRL_N`](#sw_rst_ctrl_n) can be changed. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:----------------|:---------| +| SW_RST_REGWEN_0 | 0x2c | +| SW_RST_REGWEN_1 | 0x30 | +| SW_RST_REGWEN_2 | 0x34 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable for software controllable resets | + +## SW_RST_CTRL_N +Software controllable resets. +When a particular bit value is 0, the corresponding module is held in reset. +When a particular bit value is 1, the corresponding module is not held in reset. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:----------------|:---------| +| SW_RST_CTRL_N_0 | 0x38 | +| SW_RST_CTRL_N_1 | 0x3c | +| SW_RST_CTRL_N_2 | 0x40 | + + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x1 | VAL | Software reset value | + +## ERR_CODE +A bit vector of all the errors that have occurred in reset manager +- Offset: `0x44` +- Reset default: `0x0` +- Reset mask: `0x7` + +### Fields + +```wavejson +{"reg": [{"name": "REG_INTG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RESET_CONSISTENCY_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FSM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------------|:------------------------------------------------------| +| 31:3 | | | | Reserved | +| 2 | ro | 0x0 | FSM_ERR | Sparsely encoded fsm error. | +| 1 | ro | 0x0 | RESET_CONSISTENCY_ERR | A inconsistent parent / child reset was observed. | +| 0 | ro | 0x0 | REG_INTG_ERR | The register file has experienced an integrity error. | + + + diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/doc/reset_topology.svg b/hw/top_darjeeling/ip_autogen/rstmgr/doc/reset_topology.svg new file mode 100644 index 0000000000000..81510a296435e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/doc/reset_topology.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/doc/theory_of_operation.md b/hw/top_darjeeling/ip_autogen/rstmgr/doc/theory_of_operation.md new file mode 100644 index 0000000000000..39efddb0cf423 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/doc/theory_of_operation.md @@ -0,0 +1,310 @@ +# Theory of Operation + +The OpenTitan reset topology and reset controller block diagram are shown in the diagram below. +The reset controller is closely related to the [power controller](../../pwrmgr/README.md), please refer to that spec for details on how reset controller inputs are controlled. + +![Reset Topology](../doc/reset_topology.svg) + +## Reset Topology + +The topology can be summarized as follows: + +* There are two reset domains + * Test Domain - Driven by `TRSTn` + * Core Domain - Driven by internal [POR circuitry](../../../ip/ast/README.md). +* Test domain is comprised of the following components + * SOC TAP and related DFT circuits + * RISC-V TAP (part of the `rv_dm` module) + +The test domain does not have sub reset trees. +`TRSTn` is used directly by all components in the domain. + +The Core domain consists of all remaining logic and contains 4 sub reset trees, see table below. + + + + + + + + + + + + + + + + + + + + + + +
+Reset Tree + Description +
rst_por_n + POR reset tree. +

+This reset is driven by ast, stretched inside the reset manager and resets all core domain logic in the design. +

rst_lc_n + Life Cycle reset tree. +

+This reset is derived from rst_por_n and resets all logic in the design except:

    + +
  • rv_dm +
  • A small portion of pinmux
+
rst_sys_n + Debug reset tree. +

+This reset is derived from rst_por_n and resets debug domain logic excluded in the life cycle reset tree

    +
rst_{module}_n + Module specific reset. +

+This reset is derived from rst_lc_n and sets only the targeted module and nothing else. +

+For OpenTitan, the only current targets are spi_device, all instances of spi_host, all instances of i2c and usbdev +

+ +The reset trees are cascaded upon one another in this order: +- `rst_por_n` -> `rst_lc_n` -> `rst_module_n` +- `rst_por_n` -> `rst_sys_n` -> `rst_module_n` +This means when a particular reset asserts, all downstream resets also assert. + +The primary difference between `rst_lc_n` and `rst_sys_n` is that the former controls the reset state of most logic in the system, while the latter controls the reset state only of the debug domain. +This separation is required because the debug domain may request the system to reset while retaining debug info and control. +This is particularly useful if one wanted to debug something early during the boot flow, and thus needed to set a break point after requesting a debug reset. + +The reset topology also contains additional properties: +* Selective processor HART resets, such as `hartreset` in `dmcontrol`, are not implemented, as it causes a security policy inconsistency with the remaining system. + * Specifically, these selective resets can cause the cascaded property shown above to not be obeyed. +* Modules do not implement local resets that wipe configuration registers, especially if there are configuration locks. + * Modules are allowed to implement local soft resets that clear datapaths; but these are examined on a case by case basis for possible security side channels. +* In a production system, the Test Reset Input (`TRSTn`) should be explicitly asserted through system integration. + * In a production system, `TRSTn` only needs to be released for RMA transitions and nothing else. +. + +## Reset Manager + +The reset manager handles the reset of the core domain, and also holds relevant reset information in CSR registers, such as: + +* [`RESET_INFO`](registers.md#reset_info) indicates why the system was reset. +* [`ALERT_INFO`](registers.md#alert_info) contains the recorded alert status prior to system reset. + * This is useful in case the reset was triggered by an alert escalation. +* [`CPU_INFO`](registers.md#cpu_info) contains recorded CPU state prior to system reset. + * This is useful in case the reset was triggered by a watchdog where the host hung on a particular bus transaction. + +Additionally, the reset manager, along with the power manager, accepts requests from the system and asserts resets for the appropriate clock trees. +These requests primarily come from the following sources: +* Peripherals capable of reset requests: such as [sysrst_ctrl](../../../../ip/sysrst_ctrl/README.md) and [always on timers ](../../../../ip/aon_timer/README.md). +* Debug modules such as `rv_dm`. +* Power manager request for low power entry and exit. +* Escalation reset requests such as those from `alert_handler` or `pwrmgr` itself. +* Direct software request for reset. + +### Shadow Resets + +OpenTitan supports the shadow configuration registers. +These are registers stored in two constantly checking copies to ensure the values are not maliciously or accidentally disturbed. +For these components, the reset manager outputs a shadow reset dedicated to resetting only the shadow storage. +This reset separation ensures that a targetted attack on the reset line cannot easily defeat shadow registers. + +### Reset Consistency Checks + +The reset manager implements reset consistency checks to ensure that triggered resets are supposed to happen and not due to some fault in the system. +Every leaf reset in the system has an associated consistency checker. + +The consistency check ensures that when a leaf reset asserts, either its parent reset must have asserted, or the software request, if available, has asserted. +While this sounds simple in principle, the check itself crosses up to 3 clock domains and must be carefully managed. + +First, the parent and leaf resets are used to asynchronously assert a flag indication. +This flag indication is then synchronized into the reset manager's local clock domain. + +The reset manager then checks as follows: +- If a leaf reset has asserted, check to see either its parent or software request (synchronous to the local domain) has asserted. + +- If the condition is not true, it is possible the parent reset indication is still being synchronized, thus we wait for the parent indication. + +- It is also possible the parent indication was seen first, but the leaf condition was not, in this case, we wait for the leaf indication. + +- A timeout period corresponding to the maximum synchronization delay is used to cover both waits. + - If the appropriate pairing is not seen in the given amount of time, signal an error, as the leaf reset asserted without cause. + +- If all reset conditions are satisfied, wait for the reset release to gracefully complete the cycle. + +### Reset Indications for Alert Handler + +The alert handler needs to know the status of the various reset domains in the system to avoid false alert indications due to the ping mechanism. +To that end, the reset manager outputs a 4bit MuBi signal for each reset domain that indicates whether its reset is active. +For more information on this mechanism, see [alert handler documentation](../../alert_handler/doc/theory_of_operation.md#low-power-management-of-alert-channels). + +## Design Details + +The reset manager generates the resets required by the system by synchronizing reset tree components to appropriate output clocks. +As a result, a particular reset tree (for example `rst_lc_n`) may have multiple outputs depending on the clock domains of its consumers. + +Each reset tree is discussed in detail below. + +## POR Reset Tree + +The POR reset tree, `rst_por_n`, is the root reset of the entire device. +If this reset ever asserts, everything in the design is reset. + +The `ast` input `aon_pok` is used as the root reset indication. +It is filtered and stretched to cover any slow voltage ramp scenarios. +The stretch parameters are design time configurations. + +* The filter acts as a synchronizer and is by default 3 stages. +* The count by default is 32. + * The counter increments only when all stages of the filter are 1. + * If any stage at any point becomes '0', the reset counter returns to 0 and downstream logic is driven to reset again. +* Both functions are expected to operate on slow, always available KHz clocks. + + +## Life Cycle Reset Tree + +Life cycle reset, `rst_lc_n` asserts under the following conditions: +* Whenever `rst_por_n` asserts. +* Whenever a peripheral reset request (always on timer watchdog, rbox reset request, alert handler escalation, direct software request) is received. + +The `rst_lc_n` tree contains both always-on and non-always-on versions. +How many non-always-on versions is dependent on how many power domains are supported by the system. + +## System Reset Tree + +System reset, `rst_sys_n` , assertion depends on life cycle state. + +When in PROD and PROD_END states, `rst_sys_n` is identical to `rst_lc_n`. + +When in TEST, RMA and DEV states, `rst_sys_n` is identical to `rst_lc_n` unless the reset request is `ndmreset_req`. +`ndmreset_req` is issued by the debug module of the system, it requests for all logic, except those needed to maintain debug state to reset. + +Since `ndmreset_req` is valid only during TEST, RMA and DEV states, it is the only place where the reset is differentiated. +During these states, when `ndmreset_req` is issued, all logic except the debug module and associated glue logic are reset. + +The `rst_sys_n` tree contains both always-on and non-always-on versions. +How many non-always-on versions is dependent on how many power domains are supported by the system. + +## Output Leaf Resets + +The reset trees discussed above are not directly output to the system for consumption. +Instead, the output leaf resets are synchronized versions of the various root resets. +How many leaf resets there are and to which clock is decided by the system and templated through the reset manager module. + +Assuming a leaf output has N power domains and M clock domains, it potentially means one reset tree may output NxM outputs to satisfy all the reset scenario combinations. + +## Power Domains and Reset Trees + +It is alluded above that reset trees may contain both always-on and non-always-on versions. +This distinction is required to support power manager's various low power states. +When a power domain goes offline, all of its components must reset, regardless of the reset tree to which it belongs. + +For example, assume a system with two power domains - `Domain A` is always-on, and `Domain B` is non-always-on. +When `Domain B` is powered off, all of `Domain B`'s resets, from `rst_lc_n`, `rst_sys_n` to `rst_module_n` are asserted. +However, the corresponding resets for `Domain A` are left untouched because it has not been powered off. + +## Software Controlled Resets + +Certain leaf resets can be directly controlled by software. +Due to security considerations, most leaf resets cannot be controlled, only a few blocks are given exceptions. +The only blocks currently allowed to software reset are `spi_device`, `usbdev`, `spi_host` and `i2c`. + +The criteria for selecting which block is software reset controllable is meant to be overly restrictive. +Unless there is a clear need, the default option is to not provide reset control. + +In general, the following rules apply: +* If a module has configuration register lockdown, it cannot be software resettable. +* If a module operates on secret data (keys), it cannot be software resettable. + * Or a software reset should render the secret data unusable until some initialization routine is run to reduce the Hamming leakage of secret data. +* If a module can alter the software's perception of time or general control flow (timer or interrupt aggregator), it cannot be software resettable. +* If a module contains sensor functions for security, it cannot be software resettable. +* If a module controls life cycle or related function, it cannot be software resettable. + +## Summary + +The following table summarizes the different reset requests and which part of each reset tree, along with what power domain is affected. + +Reset Request Type | Example | POR Reset Tree | LC Reset Tree | SYS Reset Tree | Module Specific Reset +----------------------------------| --------------------------------------------------------------| ---------------| ------------- | --------------- | ---------------------- +POR | VCC toggle, POR_N pad toggle | all domains | all domains | all domains | all domains +HW reset Request | `aon_timer` reset request, `alert_handler` escalation request | | all domains | all domains | all domains +Directed SW system reset request | `rstmgr` SW_RESET | | all domains | all domains | all domains +Ndm reset request (PROD/PROD_END) | `rv_dm` non-debug-module reset request in PROD | | all domains | all domains | all domains +Ndm reset request (Other states) | `rv_dm` non-debug-module reset request in DEV | | all domains | | all domains +SW low power entry | wait-for-interrupt deep sleep entry | | non-aon domains | non-aon domains | non-aon domains +SW controlled reset request | `rstmgr` SW_RST_CTRL_N | | | | all domains + + +## Reset Information + +The reset information register is a reflection of the reset state from the perspective of the system. +In OpenTitan, since there is only 1 host, it is thus from the perspective of the processor. +This also suggests that if the design had multiple processors, there would need to be multiple such registers. + +If a reset does not cause the processor to reset, there is no reason for the reset information to change (this is also why there is a strong security link between the reset of the processor and the rest of the system). +The following are the currently defined reset reasons and their meaning: + +Reset Cause | Description +------------------------|--------------- +`POR` | Cold boot, the system was reset through POR circuitry. +`LOW_POWER_EXIT` | Warm boot, the system was reset through low power exit. +`NDM RESET` | Warm boot, the system was reset through `rv_dm` non-debug-module request. +`SW_REQ` | Warm boot, the system was reset through [`RESET_REQ`](registers.md#reset_req). +`HW_REQ` | Warm boot, the system was reset through peripheral requests. There may be multiple such requests. + + +The reset info register is write 1 clear. +It is software responsibility to clear old reset reasons; the reset manager simply records based on the rules below. + +Excluding power on reset, which is always recorded when the device POR circuitry is triggered, the other resets are recorded when authorized by the reset manager. +Reset manager authorization is based on reset categories as indicated by the power manager. +The power manager has three reset categories that are mutually exclusive: +* No reset has been triggered by pwrmgr. +* Low power entry reset has been triggered by pwrmgr. +* Software or peripheral reset request has been triggered by pwrmgr. + +The reset categories are sent to the reset manager so that it can decide which reason to record when the processor reset is observed. +Non-debug-module resets are allowed only when no resets have been triggered by pwrmgr. + +Since a reset could be motivated by multiple reasons (a security escalation during low power transition for example), the reset information registers constantly record all reset causes in which it is allowed. +The only case where this is not done is `POR`, where active recording is silenced until the first processor reset release. + +Even though four reset causes are labeled as warm boot, their effects on the system are not identical. + +* When the reset cause is `LOW_POWER_EXIT`, it means only the non-always-on domains have been reset. + * Always-on domains retain their pre-low power values. +* When the reset cause is `NDM_RESET`, it means only the `rst_sys_n` tree has asserted for all power domains. +* When the reset cause is `HW_REQ` or `SW_REQ`, it means everything other than power / clock / reset managers have reset. + +This behavioral difference may be important to software, as it implies the configuration of the system may need to be different. + +## Crash Dump Information + +The reset manager manages crash dump information for software debugging across unexpected resets and watchdogs. +When enabled, the latest alert information and latest CPU information are captured in always-on registers. + +When the software resumes after the reset, it is then able to examine the last CPU state or the last set of alert information to understand why the system has reset. + +The enable for such debug capture can be locked such that it never captures. + +### Alert Information + +The alert information register contains the value of the alert crash dump prior to a triggered reset. +Since this information differs in length between system implementation, the alert information register only displays 32-bits at a time. +The [`ALERT_INFO_ATTR`](registers.md#alert_info_attr) register indicates how many 32-bit data segments must be read. + +To enable alert crash dump capture, set [`ALERT_INFO_CTRL.EN`](registers.md#alert_info_ctrl) to 1. +Once the system has reset, check [`ALERT_INFO_ATTR.CNT_AVAIL`](registers.md#alert_info_attr) for how many reads need to be done. +Set [`ALERT_INFO_CTRL.INDEX`](registers.md#alert_info_ctrl) to the desired segment, and then read the output from [`ALERT_INFO`](registers.md#alert_info). + +### CPU Information + +The CPU information register contains the value of the CPU state prior to a triggered reset. +Since this information differs in length between system implementation, the information register only displays 32-bits at a time. + +For more details on the CPU dump details, please see [crash dump](../../../../ip/rv_core_ibex/README.md#crash-dump-collection). + +The [`CPU_INFO_ATTR`](registers.md#cpu_info_attr) register indicates how many 32-bit data segments must be read. +Software then simply needs to write in [`CPU_INFO_CTRL.INDEX`](registers.md#cpu_info_ctrl) which segment it wishes and then read out the [`CPU_INFO`](registers.md#cpu_info) register. diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/README.md b/hw/top_darjeeling/ip_autogen/rstmgr/dv/README.md new file mode 100644 index 0000000000000..6de3ff7d057f6 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/README.md @@ -0,0 +1,121 @@ +# RSTMGR DV document + +* **DV** + * Verify all RSTMGR IP features by running dynamic simulations with a SV/UVM based testbench + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench + +* [Design & verification stage](../../../../README.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/top_darjeeling/ip_autogen/rstmgr/dv/latest/report.html) + +For detailed information on RSTMGR design features, please see the [RSTMGR HWIP technical specification](../README.md). + +RSTMGR testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +![Block diagram](./doc/tb.svg) + +The top level testbench is located at [`hw/top_darjeeling/ip_autogen/rstmgr/dv/tb.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/rstmgr/dv/tb.sv). +It instantiates the RSTMGR DUT module [`hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr.sv). +In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [TileLink host interface](../../../../dv/sv/tl_agent/README.md) +* RSTMGR interface [`hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_if.sv) +* Alerts ([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md)) + +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +All common types and methods defined at the package level can be found in +`rstmgr_env_pkg`. Some of them in use are: +```systemverilog + typedef logic [NumSwResets-1:0] sw_rst_t; + typedef logic [$bits(alert_pkg::alert_crashdump_t)-1:0] linearized_alert_dump_t; + typedef virtual pwrmgr_rstmgr_sva_if #(.CHECK_RSTREQS(0)) parameterized_pwrmgr_rstmgr_sva_vif; +``` +The RSTMGR testbench instantiates (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md). +This provides the ability to drive and independently monitor random traffic via the TL host interface into the RSTMGR device. + +RSTMGR testbench instantiates (already handled in CIP base env) [alert_agents](../../../../dv/sv/alert_esc_agent/README.md): +[list alert names]. +The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in RSTMGR device. + +The RSTMGR RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md). + +The following test sequences and covergroups are described in more detail in the testplan at `hw/top_darjeeling/ip_autogen/pwrmgr/data/rstmgr_testplan.hjson`, and also included [below](#testplan). + +This IP is only reset via the `por_n_i` input, and by `scan_rst_ni` qualified by `scanmode_i` being active. +The regular `rst_ni` input is connected to its own `resets_o.rst_por_io_div4_n[0]` output, so the reset output from `clk_rst_if` is not connected. +Similarly, all reset outputs from other `clk_rst_if` instances are ignored, and only their clock output is used. +This is consistent with this IP being in charge of all derived resets in the chip. + +Besides the POR resets above, the test sequences mostly assert various reset requests from pwrmgr and trigger resets vir RESET_REQ CSR. +Alert and CPU dump info is randomized and checked on resets. + +The test sequences reside in [`hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib). +All test sequences are extended from `rstmgr_base_vseq`, which is extended from `cip_base_vseq` and serves as a starting point. +It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. +Some of the most commonly used tasks / functions are as follows: +* task `wait_for_cpu_out_of_reset`: + Waits for the `resets_o.rst_sys_n[1]` output to go high, indicating the CPU is out of reset and CSRs can be accessed. +* task `check_cpu_dump_info`: + Reads and compares each field in the `cpu_info` CSR against the given cpu dump. +* task `check_software_reset_csr_and_pins`: + Reads and compares the `sw_rst_ctrl_n` CSR and the output reset ports against the given value. + +Other sequences follow: +* `rstmgr_smoke_vseq` tests the rstmgr through software initiated low power, peripheral reset, ndm reset, and software initiated resets. +* `rstmgr_reset_stretcher_vseq` tests the `resets_o.rst_por_aon_n[0]` output is asserted after 32 stable cycles of `ast_i.aon_pok`. +* `rstmgr_sw_rst_vseq` tests the functionality provided by the `sw_rst_regwen` and `sw_rst_ctrl_n`. +* `rstmgr_reset_info_vseq` tests the `reset_info` CSR contents correspond to the different resets. +* `rstmgr_cpu_info_vseq` tests the `cpu_info` CSR contents capture to the `cpu_dump_i` present at the time of a reset. +* `rstmgr_alert_info_vseq` tests the `alert_info` CSR contents capture to the `alert_dump_i` present at the time of a reset. + +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The following covergroups have been developed to prove that the test intent has been adequately met: +* `reset_stretcher_cg` +* `alert_info_cg` +* `cpu_info_cg` +* `alert_info_capture_cg` +* `cpu_info_capture_cg` +* `sw_rst_cg` + +Most self checking is done using SVA, and via explicit CSR reads. +The latter are described in the testplan. + +* TLUL assertions: The `tb/rstmgr_bind.sv` file binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. +* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. +* Response to pwrmgr's `rst_lc_req` and `rst_sys_req` inputs: these trigger transitions in `rst_lc_src_n` and `rst_sys_rst_n` outputs. + Checked via SVAs in [`hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv). +* Response to `cpu_i.ndmreset_req` input: after it is asserted, rstmgr's `rst_sys_src_n` should go active. + Checked via SVA in [`hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv). +* Resets cascade hierarchically per [Reset Topology](../doc/theory_of_operation.md#reset-topology). + Checked via SVA in [`hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv). +* POR must be active for at least 32 consecutive cycles before going inactive before output resets go inactive. + Checked via SVA in [`hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv). +* The scan reset `scan_rst_ni` qualified by `scanmode_i` triggers all cascaded resets that `por_n_i` does. + Checked via SVA in [`hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv). +* Software resets to peripherals also cascade hierarchically. + Checked via SVA in [`hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv). +* The output `rst_en_o` for alert_handler tracks their corresponding resets. + Checked via SVA in both [`hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv) and [`hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv). +* The `alert` and `cpu_info_attr` indicate the number of 32-bit words needed to capture their inputs. + Checked via SVA in `hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv`. + +The rstmgr_cnsty_chk module is a D2S component. +It depends on very specific timing, and requires tampering stimulus to verify its functionality. +It has its own separate dv environment and tests at `hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk`. +It is excluded from coverage for the rstmgr dv tests. + +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson -i rstmgr_smoke +``` + +[Testplan](../data/rstmgr_testplan.hjson) diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/cov/rstmgr_cov_bind.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/cov/rstmgr_cov_bind.sv new file mode 100644 index 0000000000000..03781409cc624 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/cov/rstmgr_cov_bind.sv @@ -0,0 +1,13 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: +// Reset manager coverage bindings for multi bus input +module rstmgr_cov_bind; + // sec cm coverage bind + bind rstmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_scanmode_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (scanmode_i) + ); +endmodule diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/cov/rstmgr_cover.cfg b/hw/top_darjeeling/ip_autogen/rstmgr/dv/cov/rstmgr_cover.cfg new file mode 100644 index 0000000000000..7dc7cd2f1dc4f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/cov/rstmgr_cover.cfg @@ -0,0 +1,9 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Remove rstmgr_cnsty_chk module tree since it is a pre-verified sub-module. +-moduletree rstmgr_cnsty_chk +begin tgl + +module rstmgr_cnsty_chk +end diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/cov/rstmgr_tgl_excl.cfg b/hw/top_darjeeling/ip_autogen/rstmgr/dv/cov/rstmgr_tgl_excl.cfg new file mode 100644 index 0000000000000..5a9c86e0bc32e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/cov/rstmgr_tgl_excl.cfg @@ -0,0 +1,32 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//====================================================================== +// This file contains outputs of rstmgr tied to constants. +//====================================================================== + +-module_node rstmgr resets_o.rst_por_n[Domain0Sel] +-module_node rstmgr rst_en_o.por[Domain0Sel] +-module_node rstmgr resets_o.rst_por_io_n[Domain0Sel] +-module_node rstmgr rst_en_o.por_io[Domain0Sel] +-module_node rstmgr resets_o.rst_por_io_div2_n[Domain0Sel] +-module_node rstmgr rst_en_o.por_io_div2[Domain0Sel] +-module_node rstmgr resets_o.rst_por_io_div4_n[Domain0Sel] +-module_node rstmgr rst_en_o.por_io_div4[Domain0Sel] +-module_node rstmgr resets_o.rst_lc_aon_n[Domain0Sel] +-module_node rstmgr rst_en_o.lc_aon[Domain0Sel] +-module_node rstmgr resets_o.rst_lc_io_n[Domain0Sel] +-module_node rstmgr rst_en_o.lc_io[Domain0Sel] +-module_node rstmgr resets_o.rst_lc_io_div2_n[Domain0Sel] +-module_node rstmgr rst_en_o.lc_io_div2[Domain0Sel] +-module_node rstmgr resets_o.rst_sys_n[DomainAonSel] +-module_node rstmgr rst_en_o.sys[DomainAonSel] +-module_node rstmgr resets_o.rst_sys_io_div4_n[Domain0Sel] +-module_node rstmgr rst_en_o.sys_io_div4[Domain0Sel] +-module_node rstmgr resets_o.rst_spi_device_n[DomainAonSel] +-module_node rstmgr rst_en_o.spi_device[DomainAonSel] +-module_node rstmgr resets_o.rst_spi_host0_n[DomainAonSel] +-module_node rstmgr rst_en_o.spi_host0[DomainAonSel] +-module_node rstmgr resets_o.rst_i2c0_n[DomainAonSel] +-module_node rstmgr rst_en_o.i2c0[DomainAonSel] diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/cov/rstmgr_unr_excl.el b/hw/top_darjeeling/ip_autogen/rstmgr/dv/cov/rstmgr_unr_excl.el new file mode 100644 index 0000000000000..2426c55284a4e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/cov/rstmgr_unr_excl.el @@ -0,0 +1,88 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Generated UNR file from Synopsys UNR tool with D2S rstmgr_cnsty_chk module +// excluded. +// +//================================================== +// This file contains the Excluded objects +// Generated By User: maturana +// Format Version: 2 +// Date: Tue Jan 17 12:16:09 2023 +// ExclMode: default +//================================================== +CHECKSUM: "258095983 1288805244" +INSTANCE: tb.dut +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_i2c1_n [0] "logic resets_o.rst_i2c1_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_i2c1_n [0] "logic resets_o.rst_i2c1_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_i2c0_n [0] "logic resets_o.rst_i2c0_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_i2c0_n [0] "logic resets_o.rst_i2c0_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_usb_aon_n [0] "logic resets_o.rst_usb_aon_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_usb_aon_n [0] "logic resets_o.rst_usb_aon_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_usb_n [0] "logic resets_o.rst_usb_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_usb_n [0] "logic resets_o.rst_usb_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_spi_host1_n [0] "logic resets_o.rst_spi_host1_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_spi_host1_n [0] "logic resets_o.rst_spi_host1_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_spi_host0_n [0] "logic resets_o.rst_spi_host0_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_spi_host0_n [0] "logic resets_o.rst_spi_host0_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_spi_device_n [0] "logic resets_o.rst_spi_device_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_spi_device_n [0] "logic resets_o.rst_spi_device_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_sys_io_div4_n [1] "logic resets_o.rst_sys_io_div4_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_sys_io_div4_n [1] "logic resets_o.rst_sys_io_div4_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_sys_n [0] "logic resets_o.rst_sys_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_sys_n [0] "logic resets_o.rst_sys_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_lc_aon_n [1] "logic resets_o.rst_lc_aon_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_lc_aon_n [1] "logic resets_o.rst_lc_aon_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_por_usb_n [1] "logic resets_o.rst_por_usb_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_por_usb_n [1] "logic resets_o.rst_por_usb_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_por_io_div4_n [1] "logic resets_o.rst_por_io_div4_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_por_io_div4_n [1] "logic resets_o.rst_por_io_div4_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_por_io_div2_n [1] "logic resets_o.rst_por_io_div2_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_por_io_div2_n [1] "logic resets_o.rst_por_io_div2_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_por_io_n [1] "logic resets_o.rst_por_io_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_por_io_n [1] "logic resets_o.rst_por_io_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_por_n [1] "logic resets_o.rst_por_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_por_n [1] "logic resets_o.rst_por_n[1:0]" +CHECKSUM: "7550215 3610141655" +INSTANCE: tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o "logic err_o" +CHECKSUM: "74367784 3785313510" +INSTANCE: tb.dut.u_reg.u_reg_if +ANNOTATION: "VC_COV_UNR" +Condition 18 "3340270436" "(addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error) 1 -1" (5 "01000") diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/doc/tb.svg b/hw/top_darjeeling/ip_autogen/rstmgr/dv/doc/tb.svg new file mode 100644 index 0000000000000..8a1940ac4dcd7 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/doc/tb.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env.core b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env.core new file mode 100644 index 0000000000000..a8d54568b804e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env.core @@ -0,0 +1,53 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:rstmgr_env:0.1" +description: "RSTMGR DV UVM environment" +filesets: + files_rtl: + depend: + - lowrisc:ip_interfaces:rstmgr + + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:ip_interfaces:rstmgr_pkg + + files: + - rstmgr_env_pkg.sv + - rstmgr_env_cfg.sv: {is_include_file: true} + - rstmgr_env_cov.sv: {is_include_file: true} + - rstmgr_virtual_sequencer.sv: {is_include_file: true} + - rstmgr_scoreboard.sv: {is_include_file: true} + - rstmgr_env.sv: {is_include_file: true} + - seq_lib/rstmgr_vseq_list.sv: {is_include_file: true} + - seq_lib/rstmgr_base_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_common_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_por_stretcher_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_reset_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_smoke_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_stress_all_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_sw_rst_reset_race_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_sw_rst_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_sec_cm_scan_intersig_mubi_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_leaf_rst_cnsty_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_leaf_rst_shadow_attack_vseq.sv: {is_include_file: true} + - rstmgr_if.sv + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: rstmgr + ip_hjson: ../../data/rstmgr.hjson + +targets: + default: + filesets: + - files_dv + - files_rtl + generate: + - ral diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env.sv new file mode 100644 index 0000000000000..482611aa412e5 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env.sv @@ -0,0 +1,67 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_env extends cip_base_env #( + .CFG_T (rstmgr_env_cfg), + .COV_T (rstmgr_env_cov), + .VIRTUAL_SEQUENCER_T(rstmgr_virtual_sequencer), + .SCOREBOARD_T (rstmgr_scoreboard) +); + `uvm_component_utils(rstmgr_env) + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "aon_clk_rst_vif", cfg.aon_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get aon_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "io_clk_rst_vif", cfg.io_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get io_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "io_div2_clk_rst_vif", cfg.io_div2_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get io_div2_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "io_div4_clk_rst_vif", cfg.io_div4_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get io_div4_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "main_clk_rst_vif", cfg.main_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get main_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "usb_clk_rst_vif", cfg.usb_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get usb_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual pwrmgr_rstmgr_sva_if)::get( + this, "", "pwrmgr_rstmgr_sva_vif", cfg.pwrmgr_rstmgr_sva_vif + )) begin + `uvm_fatal(`gfn, "failed to get pwrmgr_rstmgr_sva_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual rstmgr_cascading_sva_if)::get( + this, "", "rstmgr_cascading_sva_vif", cfg.rstmgr_cascading_sva_vif + )) begin + `uvm_fatal(`gfn, "failed to get rstmgr_cascading_sva_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual rstmgr_if)::get(this, "", "rstmgr_vif", cfg.rstmgr_vif)) begin + `uvm_fatal(`gfn, "failed to get rstmgr_vif from uvm_config_db") + end + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env_cfg.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env_cfg.sv new file mode 100644 index 0000000000000..b5c1f3fc3284f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env_cfg.sv @@ -0,0 +1,37 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_env_cfg extends cip_base_env_cfg #( + .RAL_T(rstmgr_reg_block) +); + + // This scoreboard handle is used to flag expected errors. + rstmgr_scoreboard scoreboard; + + // ext component cfgs + + `uvm_object_utils_begin(rstmgr_env_cfg) + `uvm_object_utils_end + + `uvm_object_new + + virtual clk_rst_if aon_clk_rst_vif; + virtual clk_rst_if io_clk_rst_vif; + virtual clk_rst_if io_div2_clk_rst_vif; + virtual clk_rst_if io_div4_clk_rst_vif; + virtual clk_rst_if main_clk_rst_vif; + virtual clk_rst_if usb_clk_rst_vif; + virtual pwrmgr_rstmgr_sva_if pwrmgr_rstmgr_sva_vif; + virtual rstmgr_cascading_sva_if rstmgr_cascading_sva_vif; + virtual rstmgr_if rstmgr_vif; + + virtual function void initialize(bit [31:0] csr_base_addr = '1); + list_of_alerts = rstmgr_env_pkg::LIST_OF_ALERTS; + super.initialize(csr_base_addr); + + tl_intg_alert_fields[ral.err_code.reg_intg_err] = 1; + m_tl_agent_cfg.max_outstanding_req = 1; + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env_cov.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env_cov.sv new file mode 100644 index 0000000000000..3872317a8a752 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env_cov.sv @@ -0,0 +1,104 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Covergoups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here + * Covergroups may also be wrapped inside helper classes if needed. + */ + +class rstmgr_sw_rst_cg_wrap; + covergroup sw_rst_cg(string name) with function sample (bit enable, bit rst_n); + option.name = name; + option.per_instance = 1; + + enable_cp: coverpoint enable; + rst_n_cp: coverpoint rst_n; + + sw_rst_cross: cross enable, rst_n; + endgroup + + function new(string name); + sw_rst_cg = new(name); + endfunction + + function void sample (bit enable, bit rst_n); + sw_rst_cg.sample(enable, rst_n); + endfunction +endclass + +class rstmgr_env_cov extends cip_base_env_cov #( + .CFG_T(rstmgr_env_cfg) +); + `uvm_component_utils(rstmgr_env_cov) + + // the base class provides the following handles for use: + // rstmgr_env_cfg: cfg + + rstmgr_sw_rst_cg_wrap sw_rst_cg_wrap[NumSwResets]; + + covergroup alert_info_capture_cg with function sample (logic [7:0] reset_info, logic enable); + reset_info_cp: coverpoint reset_info { + bins reset_info_cp[] = {1, 2, 4, 8, 16, 32, 64, 128}; + bins others = default; + } + enable_cp: coverpoint enable; + capture_cross: cross reset_info_cp, enable_cp; + endgroup + + covergroup alert_info_access_cg with function sample (logic [3:0] index); + index_cp: coverpoint index { + bins valid[] = {[0 : ($bits(alert_crashdump_t) + 31) / 32 - 1]}; + bins others = default; + } + endgroup + + covergroup cpu_info_capture_cg with function sample (logic [7:0] reset_info, logic enable); + reset_info_cp: coverpoint reset_info { + bins reset_info_cp[] = {1, 2, 4, 8, 16, 32, 64, 128}; + bins others = default; + } + enable_cp: coverpoint enable; + capture_cross: cross reset_info_cp, enable_cp; + endgroup + + covergroup cpu_info_access_cg with function sample (logic [3:0] index); + index_cp: coverpoint index { + bins valid[] = {[0 : ($bits(rv_core_ibex_pkg::cpu_crash_dump_t) + 31) / 32 - 1]}; + bins others = default; + } + endgroup + + covergroup reset_stretcher_cg with function sample (byte length, byte count); + length_cp: coverpoint length { + bins lb[8] = {[1 : 40]}; + bins others = default; + } + count_cp: coverpoint count { + bins cb[4] = {[0 : 15]}; + bins others = default; + } + endgroup + + function new(string name, uvm_component parent); + super.new(name, parent); + foreach (sw_rst_cg_wrap[i]) begin + string cg_name = $sformatf("sw_rst_ctrl_n[%0d]", i); + sw_rst_cg_wrap[i] = new(cg_name); + end + alert_info_capture_cg = new(); + alert_info_access_cg = new(); + cpu_info_capture_cg = new(); + cpu_info_access_cg = new(); + reset_stretcher_cg = new(); + endfunction : new + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + // [or instantiate covergroups here] + // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky + // See cip_base_env_cov for details + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env_pkg.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env_pkg.sv new file mode 100644 index 0000000000000..f00cf85cec113 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_env_pkg.sv @@ -0,0 +1,110 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package rstmgr_env_pkg; + // dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import dv_lib_pkg::*; + import tl_agent_pkg::*; + import cip_base_pkg::*; + import dv_base_reg_pkg::*; + import csr_utils_pkg::*; + import rstmgr_ral_pkg::*; + + import prim_mubi_pkg::mubi4_t; + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4True; + + import rstmgr_reg_pkg::NumHwResets; + import rstmgr_reg_pkg::NumSwResets; + + import alert_pkg::alert_crashdump_t; + import rv_core_ibex_pkg::cpu_crash_dump_t; + + import sec_cm_pkg::*; + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // parameters + parameter string LIST_OF_ALERTS[] = {"fatal_fault", "fatal_cnsty_fault"}; + parameter uint NUM_ALERTS = 2; + + // Sorted instances of rstmgr_leaf_rst modules in top_earlgrey's rstmgr. + // This can be generated from the source using + // grep -A 5 rstmgr_leaf_rst | \ + // egrep '^[ ]+\) u_' | sed 's/[ )(]//g' | sort | \ + // sed 's/\(.*\)/ \"\1\",/' + parameter string LIST_OF_LEAFS[] = { + "u_d0_i2c0", + "u_d0_i2c1", + "u_d0_i2c2", + "u_d0_lc", + "u_d0_lc_io", + "u_d0_lc_io_div2", + // There are 4 rstmgr_leaf_rst instances with security checks disabled. + // "u_d0_lc_io_div4", + // "u_d0_lc_io_div4_shadowed", + "u_d0_lc_shadowed", + "u_d0_lc_usb", + "u_d0_spi_device", + "u_d0_spi_host0", + "u_d0_spi_host1", + "u_d0_sys", + "u_d0_usb", + "u_d0_usb_aon", + "u_daon_lc", + "u_daon_lc_aon", + "u_daon_lc_io", + "u_daon_lc_io_div2", + // Same as comment above. + // "u_daon_lc_io_div4", + // "u_daon_lc_io_div4_shadowed", + "u_daon_lc_shadowed", + "u_daon_lc_usb", + "u_daon_por", + "u_daon_por_io", + "u_daon_por_io_div2", + "u_daon_por_io_div4", + "u_daon_por_usb", + "u_daon_sys_io_div4" + }; + + // Instances of rstmgr_leaf_rst modules which have a shadow pair. + parameter string LIST_OF_SHADOW_LEAFS[] = { + "u_d0_lc", + "u_d0_lc_io_div4", + "u_daon_lc", + "u_daon_lc_io_div4" + }; + + // types + typedef logic [NumSwResets-1:0] sw_rst_t; + typedef class rstmgr_scoreboard; + + typedef logic [$bits(alert_crashdump_t)-1:0] linearized_alert_dump_t; + + // This is used to capture the values of CSR fields are reset by POR only, so these CSR + // values can be restored to their pre-reset value right after a reset is done and undo + // the dv_base reset clearing them. + typedef struct packed { + logic alert_info_ctrl_en; + logic [3:0] alert_info_ctrl_index; + logic cpu_info_ctrl_en; + logic [3:0] cpu_info_ctrl_index; + } rstmgr_values_of_por_csr_fields_t; + + // functions + + // package sources + `include "rstmgr_env_cfg.sv" + `include "rstmgr_env_cov.sv" + `include "rstmgr_virtual_sequencer.sv" + `include "rstmgr_scoreboard.sv" + `include "rstmgr_env.sv" + `include "rstmgr_vseq_list.sv" + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_if.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_if.sv new file mode 100644 index 0000000000000..fdab940f2bb65 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_if.sv @@ -0,0 +1,69 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// clkmgr interface. + +interface rstmgr_if ( + input logic clk_aon, + input logic clk, + input logic rst_n +); + + import rstmgr_env_pkg::*; + import rstmgr_pkg::PowerDomains; + + logic [PowerDomains-1:0] por_n; + + pwrmgr_pkg::pwr_rst_req_t pwr_i; + pwrmgr_pkg::pwr_rst_rsp_t pwr_o; + + prim_mubi_pkg::mubi4_t sw_rst_req_o; + + // cpu related inputs + rstmgr_pkg::rstmgr_cpu_t cpu_i; + + // Interface to alert handler + alert_pkg::alert_crashdump_t alert_dump_i; + + // Interface to cpu crash dump + rv_core_ibex_pkg::cpu_crash_dump_t cpu_dump_i; + + // dft bypass + logic scan_rst_ni; + prim_mubi_pkg::mubi4_t scanmode_i; + + // Reset status for alert handler. + rstmgr_pkg::rstmgr_rst_en_t rst_en_o; + + // reset outputs + rstmgr_pkg::rstmgr_out_t resets_o; + + // Supporting code. + int aon_cycles; + always @(posedge clk_aon) aon_cycles += 1; + + // Internal DUT signals. +`ifndef PATH_TO_DUT + `define PATH_TO_DUT tb.dut +`endif + + logic [7:0] reset_info; + always_comb begin + reset_info = { + `PATH_TO_DUT.u_reg.reset_info_hw_req_qs, + `PATH_TO_DUT.u_reg.reset_info_sw_reset_qs, + `PATH_TO_DUT.u_reg.reset_info_low_power_exit_qs, + `PATH_TO_DUT.u_reg.reset_info_por_qs + }; + end + + logic alert_info_en; + always_comb alert_info_en = `PATH_TO_DUT.reg2hw.alert_info_ctrl.en.q; + + logic cpu_info_en; + always_comb cpu_info_en = `PATH_TO_DUT.reg2hw.cpu_info_ctrl.en.q; + + bit rst_ni_inactive; + always_comb rst_ni_inactive = resets_o.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]; +endinterface diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_scoreboard.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_scoreboard.sv new file mode 100644 index 0000000000000..2a095fda859ae --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_scoreboard.sv @@ -0,0 +1,312 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_scoreboard extends cip_base_scoreboard #( + .CFG_T(rstmgr_env_cfg), + .RAL_T(rstmgr_reg_block), + .COV_T(rstmgr_env_cov) +); + `uvm_component_utils(rstmgr_scoreboard) + + // local variables + static const string sw_rst_ctrl_n_preffix = "sw_rst_ctrl_n_"; + + // This is used to capture and restore upon a regular reset the CSR values that are reset + // by POR only, since the CIP and lower layers will reset all CSRs. + rstmgr_values_of_por_csr_fields_t por_fields; + + // TLM agent fifos + + // local queues to hold incoming packets pending comparison + + `uvm_component_new + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + cfg.scoreboard = this; + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + // Initial capture to be able to restore after POR. + capture_por_csr_fields(); + fork + monitor_por(); + monitor_capture(); + monitor_tlul_rst(); + join_none + endtask + + // Start coverage collection after the very first POR negedge, since that transition is not + // useful for coverage. + local task monitor_por(); + int stretch_start; + int reset_count; + if (!cfg.en_cov) return; + @(negedge cfg.rstmgr_vif.por_n); + forever + @cfg.rstmgr_vif.por_n begin + if (cfg.rstmgr_vif.por_n == 1'b1) stretch_start = cfg.rstmgr_vif.aon_cycles; + else begin + int stretch_cycles = cfg.rstmgr_vif.aon_cycles - stretch_start; + ++reset_count; + `DV_CHECK_GT(stretch_cycles, 0) + cov.reset_stretcher_cg.sample(stretch_cycles, reset_count); + end + end + endtask + + local task monitor_capture(); + if (!cfg.en_cov) return; + forever + @cfg.rstmgr_vif.reset_info begin + if (cfg.rstmgr_vif.reset_info != '0) begin + cov.alert_info_capture_cg.sample(cfg.rstmgr_vif.reset_info, cfg.rstmgr_vif.alert_info_en); + cov.cpu_info_capture_cg.sample(cfg.rstmgr_vif.reset_info, cfg.rstmgr_vif.cpu_info_en); + end + end + endtask + + // Monitor tlul reset to update csr_utils_pkg::under_reset variable. This is needed + // because the tlul reset in rstmgr is generated internally, unlike any other modules + // where it is controlled by clk_rst_vif. + local task monitor_tlul_rst(); + forever + @cfg.m_tl_agent_cfg.vif.rst_n begin + if (!cfg.m_tl_agent_cfg.vif.rst_n) begin + `uvm_info(`gfn, "tl got reset", UVM_MEDIUM) + under_reset = 1; + end else begin + `uvm_info(`gfn, "tl got out of reset", UVM_MEDIUM) + under_reset = 0; + clear_outstanding_access(); + cfg.clk_rst_vif.wait_clks(1); + restore_por_csr_fields(); + end + end + endtask + + // This converts the trailing digits in a name to a number. + // It is fatal if there are no trailing digits. + local function int get_index_from_multibit_name(string name); + string suffix; + int last_char_index = name.len() - 1; + int i; + for (i = 0; i <= last_char_index; ++i) begin + byte character = name[last_char_index - i]; + if (character < "0" || character > "9") break; + end + `DV_CHECK(i > 0) + suffix = name.substr(last_char_index - i, last_char_index); + return suffix.atoi(); + endfunction + + local function bit blocked_by_regwen(string ral_name); + bit blocked = 0; + + if (ral_name == "alert_info_ctrl") + blocked = `gmv(ral.alert_regwen) == 0; + if (ral_name == "cpu_info_ctrl") + blocked = `gmv(ral.cpu_regwen) == 0; + // And only the various "sw_rst_ctrl_n may be blocked, so ignore all others. + if (uvm_re_match({sw_rst_ctrl_n_preffix, "*"}, ral_name)) + return 0; + case (ral_name[sw_rst_ctrl_n_preffix.len()]) + "0": blocked = `gmv(ral.sw_rst_regwen[0]) == 0; + "1": blocked = `gmv(ral.sw_rst_regwen[1]) == 0; + "2": blocked = `gmv(ral.sw_rst_regwen[2]) == 0; + "3": blocked = `gmv(ral.sw_rst_regwen[3]) == 0; + "4": blocked = `gmv(ral.sw_rst_regwen[4]) == 0; + "5": blocked = `gmv(ral.sw_rst_regwen[5]) == 0; + "6": blocked = `gmv(ral.sw_rst_regwen[6]) == 0; + "7": blocked = `gmv(ral.sw_rst_regwen[7]) == 0; + default: + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", ral_name)) + endcase + `uvm_info(`gfn, $sformatf( + "blocked_by_regwen: csr = %0s is %0sblocked", ral_name, blocked ? "" : "not "), + UVM_MEDIUM) + return blocked; + endfunction + + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + uvm_reg csr; + bit do_read_check = 1'b1; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = (write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = (write && channel == DataChannel); + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + // If incoming access is a write to a valid csr and is not blocked by a regwen, make + // updates right away. + if (addr_phase_write) begin + if (!blocked_by_regwen(csr.get_name())) + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // process the csr req: + // for write, update local variable and fifo at address phase, + // for read, update predication at address phase and compare at data phase. + case (csr.get_name()) + // add individual case item for each csr + "alert_test": begin + // Write only. + do_read_check = 1'b0; + end + "reset_req": begin + end + "reset_info": begin + // RW1C. + do_read_check = 1'b0; + end + "alert_regwen": begin + // RW0C. + end + "alert_info_ctrl": begin + // The en bit is cleared by any hardware reset, but other bits are only cleared by POR. + end + "alert_info_attr": begin + // Read only. + do_read_check = 1'b0; + end + "alert_info": begin + // Read only. + do_read_check = 1'b0; + if (cfg.en_cov) begin + cov.alert_info_access_cg.sample(ral.alert_info_ctrl.index.get()); + end + end + "cpu_regwen": begin + // RW0C. + end + "cpu_info_ctrl": begin + // The en bit is cleared by any hardware reset, but other bits are only cleared by POR. + end + "cpu_info_attr": begin + // Read only. + do_read_check = 1'b0; + end + "cpu_info": begin + // Read only. + do_read_check = 1'b0; + if (cfg.en_cov) begin + cov.cpu_info_access_cg.sample(ral.cpu_info_ctrl.index.get()); + end + end + "err_code": begin + // Set by hardware. + do_read_check = 1'b0; + end + default: begin + if (!uvm_re_match({sw_rst_ctrl_n_preffix, "*"}, csr.get_name())) begin + `uvm_info(`gfn, $sformatf("write to %0s with 0x%x", csr.get_name(), item.a_data), + UVM_MEDIUM) + if (cfg.en_cov && addr_phase_write) begin + int i = get_index_from_multibit_name(csr.get_name()); + logic enable = ral.sw_rst_regwen[i].get(); + cov.sw_rst_cg_wrap[i].sample(enable, item.a_data); + end + end else if (!uvm_re_match("sw_rst_regwen_*", csr.get_name())) begin + // RW0C, so check. + end else begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + if (do_read_check) begin + uvm_reg_data_t mirrored_value = csr.get_mirrored_value(); + case (csr.get_name()) + "alert_info_ctrl", + "cpu_info_ctrl": begin + // Override bit 0 since it can be cleared by hardware. + `DV_CHECK_EQ((mirrored_value | 1), (item.d_data | 1), $sformatf( + "reg name: %0s, before masking: mirrored value 0x%x, data read 0x%x", + csr.get_full_name(), mirrored_value, item.d_data)) + end + default: + `DV_CHECK_EQ(mirrored_value, item.d_data, $sformatf( + "reg name: %0s", csr.get_full_name())) + endcase + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end + endtask + + local function void capture_por_csr_fields(); + por_fields.alert_info_ctrl_en = `gmv(ral.alert_info_ctrl.en); + `uvm_info(`gfn, $sformatf("captured alert_info_ctrl.en 0x%x", por_fields.alert_info_ctrl_en), + UVM_MEDIUM) + por_fields.alert_info_ctrl_index = `gmv(ral.alert_info_ctrl.index); + `uvm_info(`gfn, $sformatf( + "captured alert_info_ctrl.index 0x%x", por_fields.alert_info_ctrl_index), UVM_MEDIUM) + por_fields.cpu_info_ctrl_en = `gmv(ral.cpu_info_ctrl.en); + `uvm_info(`gfn, $sformatf( + "captured cpu_info_ctrl.en 0x%x", por_fields.cpu_info_ctrl_en), UVM_MEDIUM) + por_fields.cpu_info_ctrl_index = `gmv(ral.cpu_info_ctrl.index); + `uvm_info(`gfn, $sformatf( + "captured cpu_info_ctrl.index 0x%x", por_fields.cpu_info_ctrl_index), UVM_MEDIUM) + endfunction + + // Restore the alert and cpu_info_ctrl index values, and the enable bits only on low power reset + // since all other resets clear them. + local task restore_por_csr_fields(); + if (cfg.rstmgr_vif.reset_info[ral.reset_info.low_power_exit.get_lsb_pos()]) begin + `uvm_info(`gfn, $sformatf( + "Restoring alert_info_ctrl.en to 0x%x", por_fields.alert_info_ctrl_en), UVM_MEDIUM) + csr_wr(.ptr(ral.alert_info_ctrl.en), .value(por_fields.alert_info_ctrl_en), .backdoor(1), + .predict(1)); + `uvm_info(`gfn, $sformatf("Restoring cpu_info_ctrl.en to 0x%x", por_fields.cpu_info_ctrl_en), + UVM_MEDIUM) + csr_wr(.ptr(ral.cpu_info_ctrl.en), .value(por_fields.cpu_info_ctrl_en), .backdoor(1), + .predict(1)); + end + `uvm_info(`gfn, $sformatf( + "Restoring alert_info_ctrl.index to 0x%x", por_fields.alert_info_ctrl_index), + UVM_MEDIUM) + csr_wr(.ptr(ral.alert_info_ctrl.index), .value(por_fields.alert_info_ctrl_index), .backdoor(1), + .predict(1)); + `uvm_info(`gfn, $sformatf( + "After restoring alert_info_ctrl mirrored value 0x%x", `gmv(ral.alert_info_ctrl)), + UVM_MEDIUM) + `uvm_info(`gfn, $sformatf( + "Restoring cpu_info_ctrl.index to 0x%x", por_fields.cpu_info_ctrl_index), UVM_MEDIUM) + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(por_fields.cpu_info_ctrl_index), .backdoor(1), + .predict(1)); + `uvm_info(`gfn, $sformatf( + "After restoring cpu_info_ctrl mirrored value 0x%x", `gmv(ral.cpu_info_ctrl)), + UVM_MEDIUM) + endtask + + // There are a handful of registers that are reset on POR only, but the dv_base classes + // will clear all mirrored values on reset. Rather than changing all that code to handle + // resets more accurately here we just capture the mirrored values of all such CSRs + // before reset, and apply them back once reset is handled. It would be really clean if + // they could be restored here right after reset, but restore is a task so it cannot be + // called within a function. + virtual function void reset(string kind = "HARD"); + capture_por_csr_fields(); + super.reset(kind); + // reset local fifos queues and variables + endfunction + + function void check_phase(uvm_phase phase); + super.check_phase(phase); + // post test checks - ensure that all local fifos and queues are empty + endfunction + +endclass diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_virtual_sequencer.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_virtual_sequencer.sv new file mode 100644 index 0000000000000..f81afdab42b27 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/rstmgr_virtual_sequencer.sv @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(rstmgr_env_cfg), + .COV_T(rstmgr_env_cov) +); + `uvm_component_utils(rstmgr_virtual_sequencer) + + + `uvm_component_new + +endclass diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv new file mode 100644 index 0000000000000..bb2485acf7a1b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv @@ -0,0 +1,556 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_base_vseq extends cip_base_vseq #( + .RAL_T (rstmgr_reg_block), + .CFG_T (rstmgr_env_cfg), + .COV_T (rstmgr_env_cov), + .VIRTUAL_SEQUENCER_T(rstmgr_virtual_sequencer) +); + + `uvm_object_utils(rstmgr_base_vseq) + + `uvm_object_new + + // Set clock frequencies per spec, except the aon is 200kHZ, which is + // too slow and could slow testing down for no good reason. + localparam int AON_FREQ_MHZ = 3; + localparam int IO_FREQ_MHZ = 96; + localparam int IO_DIV2_FREQ_MHZ = 48; + localparam int IO_DIV4_FREQ_MHZ = 24; + localparam int MAIN_FREQ_MHZ = 100; + localparam int USB_FREQ_MHZ = 48; + + // POR needs to be stable not less than 32 clock cycles, plus some extra, before it + // propagates to the rest of the logic. + localparam int POR_CLK_CYCLES = 40; + + // This is only used for the various clocks to start ticking, so can be any small number. + localparam int BOGUS_RESET_CLK_CYCLES = 2; + + // Some extra cycles from reset going inactive before the CPU's reset goes inactive. + localparam int CPU_RESET_CLK_CYCLES = 10; + + // The different types of reset. + typedef enum int { + ResetPOR, + ResetScan, + ResetLowPower, + ResetSw, + ResetHw, + ResetLast + } reset_e; + + // The reset_info adds POR and low power to TotalResetWidth. + typedef logic [pwrmgr_pkg::TotalResetWidth+2-1:0] reset_info_t; + typedef logic [pwrmgr_pkg::HwResetWidth-1:0] rstreqs_t; + + rand sw_rst_t sw_rst_regwen; + rand sw_rst_t sw_rst_ctrl_n; + + bit reset_once; + + rand cpu_crash_dump_t cpu_dump; + rand alert_crashdump_t alert_dump; + + rand rstreqs_t rstreqs; + + rand logic scan_rst_ni; + constraint scan_rst_ni_c {scan_rst_ni == 1;} + + // Various cycles for delaying stimulus. + rand int rst_to_req_cycles; + constraint rst_to_req_cycles_c {rst_to_req_cycles inside {[1 : 6]};} + + rand int release_lc_to_release_sys_cycles; + constraint release_lc_to_release_sys_cycles_c { + release_lc_to_release_sys_cycles inside {[1 : 10]}; + } + + rand int scan_rst_cycles; + constraint scan_rst_cycles_c {scan_rst_cycles inside {[0 : 4]};} + + rand int scanmode_cycles; + constraint scanmode_cycles_c {scanmode_cycles inside {[0 : 4]};} + + rand int lowpower_rst_cycles; + constraint lowpower_rst_cycles_c {lowpower_rst_cycles inside {[0 : 20]};} + + rand int sw_rst_cycles; + constraint sw_rst_cycles_c {sw_rst_cycles inside {[0 : 20]};} + + rand int hw_rst_cycles; + constraint hw_rst_cycles_c {hw_rst_cycles inside {[0 : 20]};} + + rand int reset_us; + constraint reset_us_c {reset_us inside {[1 : 4]};} + + bit do_rstmgr_init = 1'b1; + + mubi4_t scanmode; + int scanmode_on_weight = 8; + + // This is used to randomize the delays for the clocks to start and stop. + typedef struct { + bit [5:0] io_delay; + bit [5:0] io_div2_delay; + bit [5:0] io_div4_delay; + bit [5:0] main_delay; + bit [5:0] usb_delay; + } clock_delays_in_ns_t; + + // What to expect when testing resets. + string reset_name[reset_e] = '{ + ResetPOR: "POR", + ResetScan: "scan", + ResetLowPower: "low power", + ResetSw: "software", + ResetHw: "hardware" + }; + + function int get_reset_code(reset_e reset, rstreqs_t rstreqs); + case (reset) + ResetPOR, ResetScan: return 1 << ral.reset_info.por.get_lsb_pos(); + ResetLowPower: return 1 << ral.reset_info.low_power_exit.get_lsb_pos(); + ResetSw: return 1 << ral.reset_info.sw_reset.get_lsb_pos(); + ResetHw: return rstreqs << ral.reset_info.hw_req.get_lsb_pos(); + default: `uvm_error(`gfn, $sformatf("Unexpected reset code %0d", reset)) + endcase + endfunction + + function void post_randomize(); + scanmode = get_rand_mubi4_val(scanmode_on_weight, 4, 4); + endfunction + + local function void update_scanmode(prim_mubi_pkg::mubi4_t value); + cfg.rstmgr_vif.scanmode_i = value; + endfunction + + local function void update_scan_rst_n(logic value); + cfg.rstmgr_vif.scan_rst_ni = value; + endfunction + + local function void set_pwrmgr_rst_reqs(logic rst_lc_req, logic rst_sys_req); + `uvm_info(`gfn, $sformatf("Setting pwr_i lc_req=%x sys_req=%x", rst_lc_req, rst_sys_req), + UVM_MEDIUM) + cfg.rstmgr_vif.pwr_i.rst_lc_req = {rstmgr_pkg::PowerDomains{rst_lc_req}}; + cfg.rstmgr_vif.pwr_i.rst_sys_req = {rstmgr_pkg::PowerDomains{rst_sys_req}}; + endfunction + + local function void set_rstreqs(rstreqs_t rstreqs); + cfg.rstmgr_vif.pwr_i.rstreqs = rstreqs; + endfunction + + local function void add_rstreqs(rstreqs_t rstreqs); + cfg.rstmgr_vif.pwr_i.rstreqs |= rstreqs; + `uvm_info(`gfn, $sformatf("Updating rstreqs to 0x%x", cfg.rstmgr_vif.pwr_i.rstreqs), UVM_MEDIUM) + endfunction + + local function void set_reset_cause(pwrmgr_pkg::reset_cause_e reset_cause); + cfg.rstmgr_vif.pwr_i.reset_cause = reset_cause; + endfunction + + static function logic is_running_sequence(string seq_name); + string actual_sequence = "none"; + // Okay to ignore return value since the default won't match. + void'($value$plusargs("UVM_TEST_SEQ=%0s", actual_sequence)); + return actual_sequence.compare(seq_name) == 0; + endfunction + + virtual protected task check_reset_info(logic [TL_DW-1:0] expected_value, + string msg = "reset_info mismatch"); + csr_rd_check(.ptr(ral.reset_info), .compare_value(expected_value), .err_msg(msg)); + endtask + + local function void set_cpu_dump_info(cpu_crash_dump_t cpu_dump); + `uvm_info(`gfn, $sformatf("Setting cpu_dump_i to %p", cpu_dump), UVM_MEDIUM) + cfg.rstmgr_vif.cpu_dump_i = cpu_dump; + endfunction + + local task check_cpu_dump_info(cpu_crash_dump_t cpu_dump); + `uvm_info(`gfn, "Checking cpu_info", UVM_MEDIUM) + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(7)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.prev_valid), + .err_msg("checking previous_valid")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(6)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.prev_exception_pc), + .err_msg("checking previous exception_pc")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(5)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.prev_exception_addr), + .err_msg("checking previous exception_addr")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(4)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.current.current_pc), + .err_msg("checking current current_pc")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(3)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.current.next_pc), + .err_msg("checking current next_pc")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(2)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.current.last_data_addr), + .err_msg("checking current last_data_addr")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(1)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.current.exception_pc), + .err_msg("checking current exception_pc")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(0)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.current.exception_addr), + .err_msg("checking current exception_addr")); + + endtask + + local function void set_alert_dump_info(alert_crashdump_t alert_dump); + `uvm_info(`gfn, $sformatf( + "Setting alert_dump_i to 0x%x", linearized_alert_dump_t'({>>{alert_dump}})), + UVM_MEDIUM) + cfg.rstmgr_vif.alert_dump_i = alert_dump; + endfunction + + local task check_alert_dump_info(alert_crashdump_t alert_dump); + localparam int DumpWidth = $bits(alert_dump); + localparam int WordWidth = 32; + logic [DumpWidth-1:0] linear_dump = {>>{alert_dump}}; + int i; + `uvm_info(`gfn, "Checking alert_info", UVM_MEDIUM) + for (i = 0; i + WordWidth <= DumpWidth; i += WordWidth) begin + csr_wr(.ptr(ral.alert_info_ctrl.index), .value(i / WordWidth)); + csr_rd_check(.ptr(ral.alert_info), .compare_value(linear_dump[i+:WordWidth]), + .err_msg($sformatf("checking alert_info bits %0d:%0d", i + 31, i))); + end + if (i < DumpWidth) begin + logic [(DumpWidth % 32) - 1:0] word = linear_dump >> i; + csr_wr(.ptr(ral.alert_info_ctrl.index), .value(i / WordWidth)); + csr_rd_check(.ptr(ral.alert_info), .compare_value(word), + .err_msg($sformatf("checking alert_info bits %0d:%0d", DumpWidth - 1, i))); + end + endtask + + virtual protected task set_alert_info_for_capture(alert_crashdump_t alert_dump, logic enable); + set_alert_dump_info(alert_dump); + `uvm_info(`gfn, $sformatf("%0sabling alert_info capture", (enable ? "En" : "Dis")), UVM_MEDIUM) + csr_wr(.ptr(ral.alert_info_ctrl.en), .value(enable)); + endtask + + virtual protected task set_cpu_info_for_capture(cpu_crash_dump_t cpu_dump, logic enable); + set_cpu_dump_info(cpu_dump); + `uvm_info(`gfn, $sformatf("%0sabling cpu_info capture", (enable ? "En" : "Dis")), UVM_MEDIUM) + csr_wr(.ptr(ral.cpu_info_ctrl.en), .value(enable)); + endtask + + virtual protected task set_alert_and_cpu_info_for_capture(alert_crashdump_t alert_dump, + cpu_crash_dump_t cpu_dump); + set_alert_info_for_capture(alert_dump, 1'b1); + set_cpu_info_for_capture(cpu_dump, 1'b1); + endtask + + virtual protected task check_alert_info_after_reset(alert_crashdump_t alert_dump, logic enable); + csr_rd_check(.ptr(ral.alert_info_ctrl.en), .compare_value(enable), + .err_msg($sformatf("Expected alert info capture enable %b", enable))); + csr_wr(.ptr(ral.alert_info_ctrl.en), .value(enable)); + check_alert_dump_info(alert_dump); + endtask + + virtual protected task check_cpu_info_after_reset(cpu_crash_dump_t cpu_dump, logic enable); + csr_rd_check(.ptr(ral.cpu_info_ctrl.en), .compare_value(enable), + .err_msg($sformatf("Expected cpu info capture enable %b", enable))); + csr_wr(.ptr(ral.cpu_info_ctrl.en), .value(enable)); + check_cpu_dump_info(cpu_dump); + endtask + + // Checks both alert and cpu_info_ctrl.en, and their _info contents. + // This is tricky: both ctrl.en fields don't necessarily match the mirrored value since the + // hardware may update them on most resets. This can cause the subsequent writes to the .index + // field to overwrite the .en field. To make things simpler, after checking .en's expected + // value we write it to update the mirrored value. + virtual protected task check_alert_and_cpu_info_after_reset( + alert_crashdump_t alert_dump, cpu_crash_dump_t cpu_dump, logic enable); + check_alert_info_after_reset(alert_dump, enable); + check_cpu_info_after_reset(cpu_dump, enable); + endtask + + virtual protected task clear_alert_and_cpu_info(); + set_alert_and_cpu_info_for_capture('0, '0); + send_sw_reset(); + cfg.io_div4_clk_rst_vif.wait_clks(20); // # of lc reset cycles measured from waveform + check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(0)); + endtask + + virtual protected task clear_sw_rst_ctrl_n(); + const sw_rst_t sw_rst_all_ones = '1; + rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_ctrl_n), .value(sw_rst_all_ones)); + rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_ctrl_n), .compare_value(sw_rst_all_ones), + .err_msg("Expected sw_rst_ctrl_n to be set")); + endtask + + virtual protected task clear_sw_rst_ctrl_n_per_entry(int entry); + csr_wr(.ptr(ral.sw_rst_ctrl_n[entry]), .value(1'b1)); + csr_rd_check(.ptr(ral.sw_rst_ctrl_n[entry]), .compare_value(1'b1), + .err_msg($sformatf("Expected sw_rst_ctrl_n[%0d] to be set", entry))); + endtask + + virtual protected task check_sw_rst_regwen(sw_rst_t expected_regwen); + rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_regwen), .compare_value(expected_regwen), + .err_msg("Mismatching sw_rst_regwen")); + endtask + + // Stimulate and check sw_rst_ctrl_n with a given sw_rst_regwen setting. + // Exit when a reset is detected or the sequence would be invalid and may get stuck. + virtual protected task check_sw_rst_ctrl_n(sw_rst_t sw_rst_ctrl_n, sw_rst_t sw_rst_regwen, + bit erase_ctrl_n); + sw_rst_t exp_ctrl_n = ~sw_rst_regwen | sw_rst_ctrl_n; + + `uvm_info(`gfn, $sformatf( + "Setting sw_rst_ctrl_n to 0x%0x with regwen 0x%x, expect 0x%x", + sw_rst_ctrl_n, + sw_rst_regwen, + exp_ctrl_n + ), UVM_MEDIUM) + foreach (ral.sw_rst_ctrl_n[i]) begin + if (under_reset) return; + csr_wr(.ptr(ral.sw_rst_ctrl_n[i]), .value(sw_rst_ctrl_n[i])); + if (under_reset) return; + csr_rd_check(.ptr(ral.sw_rst_ctrl_n[i]), .compare_value(exp_ctrl_n[i]), + .err_msg($sformatf("Mismatch for bit %0d", i))); + end + if (erase_ctrl_n && !under_reset) clear_sw_rst_ctrl_n(); + endtask + + virtual protected task check_sw_rst_ctrl_n_per_entry( + sw_rst_t sw_rst_ctrl_n, sw_rst_t sw_rst_regwen, bit erase_ctrl_n, int entry); + sw_rst_t exp_ctrl_n; + + `uvm_info(`gfn, $sformatf("Set sw_rst_ctrl_n[%0d] to 0x%0x", entry, sw_rst_ctrl_n), UVM_MEDIUM) + csr_wr(.ptr(ral.sw_rst_ctrl_n[entry]), .value(sw_rst_ctrl_n[entry])); + // And check that the reset outputs match the actual ctrl_n settings. + // Allow for domain crossing delay. + cfg.io_div2_clk_rst_vif.wait_clks(3); + exp_ctrl_n = ~sw_rst_regwen | sw_rst_ctrl_n; + `uvm_info(`gfn, $sformatf( + "regwen=%b, ctrl_n=%b, expected=%b", sw_rst_regwen, sw_rst_ctrl_n, exp_ctrl_n), + UVM_MEDIUM) + csr_rd_check(.ptr(ral.sw_rst_ctrl_n[entry]), .compare_value(exp_ctrl_n[entry]), + .err_msg($sformatf("Expected enabled updates in sw_rst_ctrl_n[%0d]", entry))); + if (erase_ctrl_n) clear_sw_rst_ctrl_n_per_entry(entry); + endtask + + local task control_all_clocks(bit enable); + // Randomize the delays for each clock turning on or off. + clock_delays_in_ns_t delays; + `DV_CHECK_STD_RANDOMIZE_FATAL(delays) + if (enable) fork + #(delays.io_delay * 1ns) cfg.io_clk_rst_vif.start_clk(); + #(delays.io_div2_delay * 1ns) cfg.io_div2_clk_rst_vif.start_clk(); + #(delays.io_div4_delay * 1ns) cfg.io_div4_clk_rst_vif.start_clk(); + #(delays.main_delay * 1ns) cfg.main_clk_rst_vif.start_clk(); + #(delays.usb_delay * 1ns) cfg.usb_clk_rst_vif.start_clk(); + join else fork + #(delays.io_delay * 1ns) cfg.io_clk_rst_vif.stop_clk(); + #(delays.io_div2_delay * 1ns) cfg.io_div2_clk_rst_vif.stop_clk(); + #(delays.io_div4_delay * 1ns) cfg.io_div4_clk_rst_vif.stop_clk(); + #(delays.main_delay * 1ns) cfg.main_clk_rst_vif.stop_clk(); + #(delays.usb_delay * 1ns) cfg.usb_clk_rst_vif.stop_clk(); + join + endtask + + // Happens with hardware resets. + local task reset_start(pwrmgr_pkg::reset_cause_e reset_cause); + `uvm_info(`gfn, $sformatf("Starting pwrmgr inputs for %0s request", reset_cause.name()), + UVM_MEDIUM) + set_reset_cause(reset_cause); + // These lag the reset requests since they are set after the pwrmgr fast fsm has made some + // state transitions. + cfg.io_div4_clk_rst_vif.wait_clks(rst_to_req_cycles); + set_pwrmgr_rst_reqs(.rst_lc_req('1), .rst_sys_req('1)); + cfg.clk_rst_vif.stop_clk(); + if (reset_cause == pwrmgr_pkg::LowPwrEntry) begin + control_all_clocks(.enable(0)); + end + endtask + + protected task wait_till_active(); + // And wait for the main reset to be done. + `DV_WAIT(cfg.rstmgr_vif.rst_ni_inactive, "Time-out waiting for rst_ni becoming inactive"); + // And wait a few cycles for settling before allowing the sequences to start. + cfg.io_div4_clk_rst_vif.wait_clks(8); + endtask + + protected task reset_done(); + `uvm_info(`gfn, "Releasing reset", UVM_LOW) + update_scanmode(prim_mubi_pkg::MuBi4False); + update_scan_rst_n(1'b1); + if (cfg.rstmgr_vif.pwr_i.reset_cause == pwrmgr_pkg::LowPwrEntry) begin + control_all_clocks(.enable(1)); + end + cfg.clk_rst_vif.start_clk(); + cfg.io_div4_clk_rst_vif.wait_clks(10); + set_reset_cause(pwrmgr_pkg::ResetNone); + set_pwrmgr_rst_reqs(.rst_lc_req('0), .rst_sys_req('1)); + cfg.io_div4_clk_rst_vif.wait_clks(release_lc_to_release_sys_cycles); + set_pwrmgr_rst_reqs(.rst_lc_req('0), .rst_sys_req('0)); + set_rstreqs(0); + wait_till_active(); + `uvm_info(`gfn, "Reset done", UVM_MEDIUM) + endtask + + // Sends either an external hardware reset request, setting the possibly different + // rstreqs bits at different times. It optionally completes the reset. + virtual protected task send_hw_reset(rstreqs_t rstreqs, logic complete_it = 1); + `uvm_info(`gfn, $sformatf("Sending hw reset with 0b%0b", rstreqs), UVM_LOW) + reset_start(pwrmgr_pkg::HwReq); + fork + begin : isolation_fork + foreach (rstreqs[i]) begin : loop + if (rstreqs[i]) begin + fork + automatic int index = i; + automatic bit [2:0] cycles; + `DV_CHECK_STD_RANDOMIZE_FATAL(cycles) + cfg.io_div4_clk_rst_vif.wait_clks(cycles); + add_rstreqs(rstreqs & (1 << index)); + join_none + end + end : loop + wait fork; + end : isolation_fork + join + if (complete_it) reset_done(); + endtask + + virtual protected task send_lowpower_reset(bit complete_it = 1); + `uvm_info(`gfn, "Sending low power reset", UVM_LOW) + reset_start(pwrmgr_pkg::LowPwrEntry); + if (complete_it) reset_done(); + endtask + + + // Lead with scan_rst active to avoid some derived sequence changing scanmode_i in such + // a way it defeats this reset. + virtual protected task send_scan_reset(bit complete_it = 1); + `uvm_info(`gfn, "Sending scan reset", UVM_MEDIUM) + fork + begin + cfg.io_div4_clk_rst_vif.wait_clks(scan_rst_cycles); + update_scan_rst_n(1'b0); + end + begin + cfg.io_div4_clk_rst_vif.wait_clks(scanmode_cycles); + update_scanmode(prim_mubi_pkg::MuBi4True); + end + join + reset_start(pwrmgr_pkg::HwReq); + + // The clocks are turned off, so wait in time units. + #(reset_us * 1us); + if (complete_it) reset_done(); + endtask + + // Requests a sw reset. It is cleared by hardware once the reset is taken. + virtual protected task send_sw_reset(bit complete_it = 1); + `uvm_info(`gfn, "Sending sw reset", UVM_LOW) + reset_start(pwrmgr_pkg::HwReq); + #(reset_us * 1us); + if (complete_it) reset_done(); + endtask + + virtual task dut_init(string reset_kind = "HARD"); + if (do_rstmgr_init) rstmgr_init(); + super.dut_init(); + endtask + + virtual task dut_shutdown(); + // No checks seem needed. + endtask + + local task start_clocks(); + control_all_clocks(.enable(1)); + fork + cfg.aon_clk_rst_vif.apply_reset(.reset_width_clks(BOGUS_RESET_CLK_CYCLES)); + cfg.io_clk_rst_vif.apply_reset(.reset_width_clks(BOGUS_RESET_CLK_CYCLES)); + cfg.io_div2_clk_rst_vif.apply_reset(.reset_width_clks(BOGUS_RESET_CLK_CYCLES)); + cfg.io_div4_clk_rst_vif.apply_reset(.reset_width_clks(BOGUS_RESET_CLK_CYCLES)); + cfg.main_clk_rst_vif.apply_reset(.reset_width_clks(BOGUS_RESET_CLK_CYCLES)); + cfg.usb_clk_rst_vif.apply_reset(.reset_width_clks(BOGUS_RESET_CLK_CYCLES)); + join + endtask + + protected task por_reset_done(bit complete_it); + cfg.rstmgr_vif.por_n = '1; + reset_start(pwrmgr_pkg::ResetUndefined); + #(reset_us * 1us); + if (complete_it) reset_done(); + endtask + + virtual protected task por_reset(bit complete_it = 1); + `uvm_info(`gfn, "Starting POR", UVM_MEDIUM) + cfg.rstmgr_vif.por_n = '0; + control_all_clocks(.enable(0)); + #(100 * 1ns); + start_clocks(); + cfg.aon_clk_rst_vif.wait_clks(POR_CLK_CYCLES); + por_reset_done(complete_it); + endtask + + virtual task apply_reset(string kind = "HARD"); + fork + por_reset(); + super.apply_reset(kind); + join + endtask + + virtual task apply_resets_concurrently(int reset_duration_ps = 0); + fork + por_reset(); + start_clocks(); + super.apply_resets_concurrently(reset_duration_ps); + join + `uvm_info(`gfn, "Done with apply_resets_concurrently", UVM_MEDIUM) + endtask + + // Disable exclusions for RESET_REQ since they cause trouble for full-chip only. + function void disable_unnecessary_exclusions(); + csr_excl_item csr_excl = ral.get_excl_item(); + `uvm_info(`gfn, "Dealing with exclusions", UVM_MEDIUM) + csr_excl.enable_excl(.obj("rstmgr_reg_block.reset_req"), .enable(1'b0)); + csr_excl.print_exclusions(UVM_MEDIUM); + endfunction + + task pre_start(); + if (do_rstmgr_init) rstmgr_init(); + disable_unnecessary_exclusions(); + super.pre_start(); + endtask + + // setup basic rstmgr features + virtual task rstmgr_init(); + // Must set clk_rst_vif frequency to IO_DIV4_FREQ_MHZ since they are gated + // versions of each other and have no clock domain crossings. + // Notice they may still end up out of phase due to the way they get started. + cfg.clk_rst_vif.set_freq_mhz(IO_DIV4_FREQ_MHZ); + cfg.aon_clk_rst_vif.set_freq_mhz(AON_FREQ_MHZ); + cfg.io_clk_rst_vif.set_freq_mhz(IO_FREQ_MHZ); + cfg.io_div2_clk_rst_vif.set_freq_mhz(IO_DIV2_FREQ_MHZ); + cfg.io_div4_clk_rst_vif.set_freq_mhz(IO_DIV4_FREQ_MHZ); + cfg.main_clk_rst_vif.set_freq_mhz(MAIN_FREQ_MHZ); + cfg.usb_clk_rst_vif.set_freq_mhz(USB_FREQ_MHZ); + // Initial values for some input pins. + cfg.rstmgr_vif.scanmode_i = prim_mubi_pkg::MuBi4False; + cfg.rstmgr_vif.scan_rst_ni = scan_rst_ni; + set_pwrmgr_rst_reqs(1'b0, 1'b0); + set_rstreqs('0); + set_reset_cause(pwrmgr_pkg::ResetNone); + endtask + + // csr method wrapper for unpacked array registers + virtual task rstmgr_csr_rd_check_unpack( + input uvm_object ptr[], input uvm_reg_data_t compare_value = 0, input string err_msg = ""); + foreach (ptr[i]) begin + if (cfg.under_reset) return; + csr_rd_check(.ptr(ptr[i]), .compare_value(compare_value[i]), .err_msg(err_msg)); + end + endtask : rstmgr_csr_rd_check_unpack + + virtual task rstmgr_csr_wr_unpack(input uvm_object ptr[], input uvm_reg_data_t value); + foreach (ptr[i]) begin + if (cfg.under_reset) return; + csr_wr(.ptr(ptr[i]), .value(value[i])); + end + endtask +endclass : rstmgr_base_vseq diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_common_vseq.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_common_vseq.sv new file mode 100644 index 0000000000000..3f87231dfd307 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_common_vseq.sv @@ -0,0 +1,15 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_common_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_common_vseq) + + constraint num_trans_c {num_trans inside {[1 : 2]};} + `uvm_object_new + + virtual task body(); + run_common_vseq_wrapper(num_trans); + endtask : body + +endclass diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_cnsty_vseq.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_cnsty_vseq.sv new file mode 100644 index 0000000000000..fdc180ea41f9f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_cnsty_vseq.sv @@ -0,0 +1,228 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This tests each leaf reset consistency checkers. +// +// For resets out of +// 1 - low power entry reset +// 2 - hw req reset +// 3 - sw reset +// Create reset consistency errors in the current leaf, and check that a +// fatal_cnsty_fault alert is generated. +class rstmgr_leaf_rst_cnsty_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_leaf_rst_cnsty_vseq) + + `uvm_object_new + + int cycles_to_check = 7; + int error_pos; + int my_pos; + rand int cycles_reset_width; + rand int cycles_child_reset_width; + rand int cycles_in_apply_resets; + rand int cycles_to_child_reset; + rand int cycles_to_child_release; + rand int cycles_to_parent_reset; + rand int cycles_to_parent_release; + rand int cycles_to_sw_reset; + rand int cycles_to_sw_release; + + constraint rstreqs_non_zero_c {rstreqs != '0;} + constraint sw_rst_regwen_non_trivial_c {sw_rst_regwen != '0 && sw_rst_regwen != '1;} + constraint sw_rst_some_reset_n_c {sw_rst_regwen & ~sw_rst_ctrl_n != '0;} + + constraint cycles_reset_width_c {cycles_reset_width inside {[2 : 10]};} + constraint cycles_child_reset_width_c {cycles_child_reset_width inside {[2 : 10]};} + constraint cycles_in_apply_resets_c {cycles_in_apply_resets inside {[5 : 25]};} + constraint cycles_to_child_reset_c {cycles_to_child_reset inside {[3 : 8]};} + constraint cycles_to_child_release_c {cycles_to_child_release inside {[3 : 6]};} + constraint cycles_to_parent_reset_c {cycles_to_parent_reset inside {[2 : 8]};} + constraint cycles_to_parent_release_c {cycles_to_parent_release inside {[3 : 6]};} + constraint cycles_to_sw_reset_c {cycles_to_sw_reset inside {[2 : 8]};} + constraint cycles_to_sw_release_c {cycles_to_sw_release inside {[3 : 6]};} + + // There is an extra POR reset when the consistency failure is triggered due to apply_reset. + int maybe_por_reset; + + task body(); + for (int i = 0; i < LIST_OF_LEAFS.size(); ++i) begin + string leaf_path = {"tb.dut.", LIST_OF_LEAFS[i], ".gen_rst_chk.u_rst_chk"}; + error_pos = $urandom_range(1, 3); + my_pos = 0; + `uvm_info(`gfn, $sformatf("Round %0d %s pos:%0d", i, leaf_path, error_pos), UVM_MEDIUM) + // Get a clean slate for reset_info. + csr_wr(.ptr(ral.reset_info), .value('1)); + + fork + unexpected_child_activity(leaf_path); + begin + int expected; + set_pos_and_wait(); + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + // Send low power entry reset. + send_lowpower_reset(); + expected = 1 << ral.reset_info.low_power_exit.get_lsb_pos(); + + check_reset_info(maybe_por_reset | expected, "expected reset_info to indicate low power"); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 1'b1); + + csr_wr(.ptr(ral.reset_info), .value('1)); + cfg.io_div4_clk_rst_vif.wait_clks(10); + + // Send HwReq. + // Enable alert_info and cpu_info capture. + set_pos_and_wait(); + `DV_CHECK_RANDOMIZE_FATAL(this) + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + expected = rstreqs << ral.reset_info.hw_req.get_lsb_pos(); + send_hw_reset(rstreqs); + check_reset_info(maybe_por_reset | expected, $sformatf( + "expected reset_info to match hw_req 0x%x", expected)); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 1'b0); + + csr_wr(.ptr(ral.reset_info), .value('1)); + + set_pos_and_wait(); + `DV_CHECK_RANDOMIZE_FATAL(this) + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + + // Send sw reset. + csr_wr(.ptr(ral.reset_req), .value(MuBi4True)); + send_sw_reset(); + expected = 1 << ral.reset_info.sw_reset.get_lsb_pos(); + check_reset_info(maybe_por_reset | expected, "Expected reset_info to indicate sw reset"); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 0); + csr_wr(.ptr(ral.reset_info), .value('1)); + end + join + end + endtask : body + + task post_start(); + expect_fatal_alerts = 1; + super.post_start(); + endtask + + task send_unexpected_child_reset(string path); + `uvm_info(`gfn, "unexpected child reset start", UVM_MEDIUM) + // clear all + set_leaf_reset(.path({path, ".parent_rst_ni"}), .value(1), .cycles(0)); + set_leaf_reset(.path({path, ".sw_rst_req_i"}), .value(0), .cycles(0)); + set_leaf_reset(.path({path, ".child_rst_ni"}), .value(1), .cycles(0)); + + cfg.scoreboard.set_exp_alert("fatal_cnsty_fault", 1, 20); + + // assert child reset + set_leaf_reset(.path({path, ".child_rst_ni"}), .value(0), .cycles(cycles_to_child_reset)); + endtask : send_unexpected_child_reset + + task send_unexpected_child_release(string path); + `uvm_info(`gfn, "unexpected child release start", UVM_MEDIUM) + fork + set_leaf_reset(.path({path, ".parent_rst_ni"}), .value(0), .cycles(cycles_to_parent_reset)); + set_leaf_reset(.path({path, ".sw_rst_req_i"}), .value(1), .cycles(cycles_to_sw_reset)); + set_leaf_reset(.path({path, ".child_rst_ni"}), .value(0), .cycles(cycles_to_child_reset)); + join + + cfg.scoreboard.set_exp_alert("fatal_cnsty_fault", 1, 20); + + set_leaf_reset(.path({path, ".child_rst_ni"}), .value(1), .cycles(cycles_to_child_release)); + endtask : send_unexpected_child_release + + local task set_leaf_reset(string path, logic value, int cycles); + cfg.clk_rst_vif.wait_clks(cycles); + `uvm_info(`gfn, $sformatf("Force %s = %b", path, value), UVM_MEDIUM) + `DV_CHECK(uvm_hdl_force(path, value)) + endtask : set_leaf_reset + + // Create some unexpected child activity when my_pos is error_pos. The unexpected activity + // should trigger alerts, so this fails if no alert is generated. + task unexpected_child_activity(string path); + int err_value; + string lpath; + `DV_SPINWAIT(while (my_pos < error_pos) @cfg.clk_rst_vif.cb;, + "Timeout waiting for my_pos < error_pos", 1000_000) + + `DV_SPINWAIT(wait_for_cnsty_idle(path);, "Timeout waiting for cnsty_idle", 1000_000) + + `DV_SPINWAIT(wait_for_alert_sender_ready();, "Timeout waiting for alert_sender ready", 1000_000) + `DV_CHECK_RANDOMIZE_FATAL(this); + `uvm_info(`gfn, "Triggering inconsistency", UVM_MEDIUM) + randcase + 1: send_unexpected_child_reset(path); + 1: send_unexpected_child_release(path); + endcase + + cfg.clk_rst_vif.wait_clks(cycles_to_check); + `DV_SPINWAIT(wait(cfg.m_alert_agent_cfgs["fatal_cnsty_fault"].vif.alert_tx_final.alert_p);, + "Timeout waiting for alert fatal_cnsty_fault", 10_000) + + lpath = {path, ".child_rst_ni"}; + `DV_CHECK(uvm_hdl_release(lpath)) + lpath = {path, ".parent_rst_ni"}; + `DV_CHECK(uvm_hdl_release(lpath)) + lpath = {path, ".sw_rst_req_i"}; + `DV_CHECK(uvm_hdl_release(lpath)) + // And expect POR bit to be set. + maybe_por_reset = 1; + apply_reset(); + + // set error_pos to large value + // after error injection. + error_pos = 100; + endtask : unexpected_child_activity + + // wait for parent and child reset deassert. + // to make sure rstmgr_cnsty_chk state is not Reset state. + task wait_for_cnsty_idle(string path); + int value = 1; + string lpath; + + while (value == 1) begin + @cfg.clk_rst_vif.cb; + lpath = {path, ".sync_parent_rst"}; + `DV_CHECK(uvm_hdl_read(lpath, value)) + end + value = 1; + while (value == 1) begin + @cfg.clk_rst_vif.cb; + lpath = {path, ".sync_child_rst"}; + `DV_CHECK(uvm_hdl_read(lpath, value)) + end + endtask : wait_for_cnsty_idle + + // This waits until the alert_rx differential pairs are complementary, indicating the + // end of their initialization phase. This is necessary so the fault injection doesn't + // happen during initialization, which would end up delaying the outgoing alert. + task wait_for_alert_sender_ready(); + `uvm_info(`gfn, "Waiting for alert sender ready", UVM_MEDIUM) + forever @cfg.m_alert_agent_cfgs["fatal_cnsty_fault"].vif.sender_cb begin + if (cfg.m_alert_agent_cfgs["fatal_cnsty_fault"].vif.sender_cb.alert_rx.ping_p != + cfg.m_alert_agent_cfgs["fatal_cnsty_fault"].vif.sender_cb.alert_rx.ping_n && + cfg.m_alert_agent_cfgs["fatal_cnsty_fault"].vif.sender_cb.alert_rx.ack_p != + cfg.m_alert_agent_cfgs["fatal_cnsty_fault"].vif.sender_cb.alert_rx.ack_n) begin + `uvm_info(`gfn, "Alert sender is ready", UVM_MEDIUM) + return; + end + end + endtask : wait_for_alert_sender_ready + + task check_alert_and_cpu_info_after_reset(alert_crashdump_t alert_dump, cpu_crash_dump_t cpu_dump, + logic enable); + + if (error_pos != my_pos) begin + super.check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, enable); + end + endtask : check_alert_and_cpu_info_after_reset + + // Increments my_pos and if it equals error_pos this just waits to give time for the consistency + // error to be injected and side-effects to be created. Clear the expectation of a por reset + // since this is a new reset. + task set_pos_and_wait(); + maybe_por_reset = 0; + my_pos++; + `DV_SPINWAIT(while (my_pos == error_pos) @cfg.clk_rst_vif.cb;, $sformatf( + "Timeout waiting for my_pos == error_pos ends my_pos:%0d", my_pos), 1000_000) + endtask : set_pos_and_wait +endclass : rstmgr_leaf_rst_cnsty_vseq diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_shadow_attack_vseq.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_shadow_attack_vseq.sv new file mode 100644 index 0000000000000..4b88e03748fb6 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_shadow_attack_vseq.sv @@ -0,0 +1,84 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// Test assert glitch to shadow leaf reset module and +// check if nomal reset module got affected or vice versa +class rstmgr_leaf_rst_shadow_attack_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_leaf_rst_shadow_attack_vseq) + + `uvm_object_new + + string leaf_path; + + task body(); + for (int i = 0; i < LIST_OF_SHADOW_LEAFS.size(); ++i) begin + leaf_path = {"tb.dut.", LIST_OF_SHADOW_LEAFS[i]}; + `uvm_info(`gfn, $sformatf("Round %0d %s ", i, leaf_path), UVM_MEDIUM) + + leaf_rst_attack(leaf_path, {leaf_path, "_shadowed"}); + leaf_rst_attack({leaf_path, "_shadowed"}, leaf_path); + end + endtask : body + + task leaf_rst_attack(string npath, string gpath); + // Wait for any bit in rst_sys_io_div4_n to become inactive. + wait(|cfg.rstmgr_vif.resets_o.rst_sys_io_div4_n); + // Disable cascading reset assertions, since forcing related signals causes failures. + cfg.rstmgr_cascading_sva_vif.disable_sva = 1'b1; + `uvm_info(`gfn, $sformatf("Starting leaf attack between %s and %s", npath, gpath), UVM_MEDIUM) + cfg.scoreboard.set_exp_alert("fatal_cnsty_fault", 1, 20); + add_glitch(gpath); + wait_and_check(npath); + remove_glitch(gpath); + cfg.rstmgr_cascading_sva_vif.disable_sva = 1'b0; + `uvm_info(`gfn, "Ending leaf attack", UVM_MEDIUM) + + cfg.clk_rst_vif.wait_clks(10); + apply_reset(); + endtask : leaf_rst_attack + + + function void add_glitch(string path); + string epath = {path, ".rst_en_o"}; + string opath = {path, ".leaf_rst_o"}; + + `DV_CHECK(uvm_hdl_force(epath, prim_mubi_pkg::MuBi4True), $sformatf( + "Path %0s has problem", epath)) + `DV_CHECK(uvm_hdl_force(opath, 0), $sformatf("Path %0s has problem", opath)) + endfunction + + task wait_and_check(string path); + logic [3:0] rst_en; + logic leaf_rst; + string epath = {path, ".rst_en_o"}; + string opath = {path, ".leaf_rst_o"}; + + // Wait enough cycles to allow the uvm_hdl_force to take effect, since it is not instantaneous, + // and for side-effects to propagate. + cfg.io_div4_clk_rst_vif.wait_clks(10); + + `uvm_info(`gfn, $sformatf("Checking rst and en for %s", path), UVM_MEDIUM) + `DV_CHECK(uvm_hdl_read(epath, rst_en), $sformatf("Path %0s has problem", epath)) + `DV_CHECK(uvm_hdl_read(opath, leaf_rst), $sformatf("Path %0s has problem", opath)) + + `DV_CHECK_EQ(prim_mubi_pkg::mubi4_t'(rst_en), prim_mubi_pkg::MuBi4False, + $sformatf("%s value mismatch", epath)) + `DV_CHECK_EQ(leaf_rst, 1, $sformatf("%s value mismatch", opath)) + endtask : wait_and_check + + function void remove_glitch(string path); + string epath = {path, ".rst_en_o"}; + string opath = {path, ".leaf_rst_o"}; + `DV_CHECK(uvm_hdl_release(epath), $sformatf("Path %0s has problem", epath)) + `DV_CHECK(uvm_hdl_release(opath), $sformatf("Path %0s has problem", opath)) + endfunction + + // clean up glitch will create reset consistency error + // in shadow leaf reset module + task post_start(); + expect_fatal_alerts = 1; + super.post_start(); + endtask + +endclass : rstmgr_leaf_rst_shadow_attack_vseq diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_por_stretcher_vseq.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_por_stretcher_vseq.sv new file mode 100644 index 0000000000000..5a68b71345311 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_por_stretcher_vseq.sv @@ -0,0 +1,43 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Tests the POR stretching functionality: it directly controls the por_n_i input at the start of +// the test, and randomly glitches it for a few cycles at intervals less than the stretch cycle +// count, which is at least 32 cycles, to make sure the internal and output resets won't be +// released until the input is held steady for a sufficient number of cycles. +class rstmgr_por_stretcher_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_por_stretcher_vseq) + + `uvm_object_new + + // Wait a few cycles for resets to propagate before we start flipping por_n_i, to avoid + // spurious SVA failures dut to missing rise transitions of leaf resets. + localparam int AON_CYCLES_BEFORE_START = 4; + + // Wait this many cycles before checking for side effects of a complete reset. + localparam int AON_CYCLES_BEFORE_RESET_CHECK = 45; + + rand int glitch_separation_cycles; + rand int glitch_duration_cycles; + + // The separation between glitches that will cause a reset to fail to propagate. + constraint glitch_separation_cycles_c {glitch_separation_cycles inside {[1 : 35]};} + // The duration cycle is not very interesting. + constraint glitch_duration_cycles_c {glitch_duration_cycles inside {[1 : 8]};} + + task body(); + cfg.aon_clk_rst_vif.wait_clks(AON_CYCLES_BEFORE_START); + for (int i = 0; i < num_trans; ++i) begin + `DV_CHECK_RANDOMIZE_FATAL(this) + cfg.rstmgr_vif.por_n = 1'b1; + cfg.aon_clk_rst_vif.wait_clks(glitch_separation_cycles); + cfg.rstmgr_vif.por_n = 1'b0; + cfg.aon_clk_rst_vif.wait_clks(glitch_duration_cycles); + `DV_CHECK_EQ(cfg.rstmgr_vif.resets_o.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel], 1'b0) + end + por_reset_done(.complete_it(1)); + csr_rd_check(.ptr(ral.reset_info.por), .compare_value(1'b1), + .err_msg("Unexpected reset_info.por low")); + endtask +endclass diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv new file mode 100644 index 0000000000000..1a5071c521c2f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv @@ -0,0 +1,189 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Tests the reset_info CSR settings, and alert and cpu dump capture for random +// resets. +// +// Notice that for rstmgr both POR and scan reset have identical side-effects. +class rstmgr_reset_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_reset_vseq) + + `uvm_object_new + + typedef bit [ResetLast-1:0] which_resets_t; + + rand bit por_rst; + rand bit scan_rst; + rand bit low_power_rst; + rand bit sw_rst; + rand bit hw_rst; + + constraint which_resets_c { + $onehot( + {por_rst, scan_rst, low_power_rst, sw_rst || hw_rst} + ); + } + + constraint num_trans_c {num_trans inside {[40 : 60]};} + + // VCS seems to have non-uniform distributions for this variable. + rand logic alert_enable; + + rand logic cpu_enable; + + rand reset_e start_reset; + constraint start_reset_c {start_reset inside {ResetPOR, ResetScan};} + + which_resets_t which_resets; + mubi4_t sw_reset_csr; + + function which_resets_t create_which_resets(); + which_resets_t which_resets; + if (por_rst) which_resets[ResetPOR] = 1; + if (scan_rst) which_resets[ResetScan] = 1; + if (low_power_rst) which_resets[ResetLowPower] = 1; + if (sw_rst) which_resets[ResetSw] = 1; + if (hw_rst) which_resets[ResetHw] = 1; + return which_resets; + endfunction + + function bit has_aon_reset(which_resets_t which_resets); + return which_resets[ResetPOR] || which_resets[ResetScan]; + endfunction + + function bit clear_capture_enable(which_resets_t which_resets); + return (which_resets & ~(1 << ResetLowPower)) ? 1 : 0; + endfunction + + function void post_randomize(); + sw_reset_csr = get_rand_mubi4_val(0, 2, 4); + endfunction + + function string resets_description(which_resets_t which_resets, rstreqs_t rstreqs); + string msg = "Resets to be sent:"; + bit some; + for (reset_e r = r.first(); r != r.last(); r = r.next()) begin + if (which_resets[r]) begin + if (some) msg = {msg, ", "}; + msg = {msg, " ", reset_name[r]}; + if (r == ResetHw) msg = {msg, $sformatf(" with 0x%x", rstreqs)}; + some = 1; + end + end + return msg; + endfunction + + function reset_info_t get_expected_reset_info(which_resets_t which_resets, rstreqs_t rstreqs); + reset_info_t reset_info; + for (reset_e r = r.first(); r != r.last(); r = r.next()) begin + if (which_resets[r]) reset_info |= get_reset_code(r, rstreqs); + end + return reset_info; + endfunction + + task body(); + reset_info_t expected_reset_info_code; + logic expected_alert_enable; + logic expected_cpu_enable; + alert_crashdump_t expected_alert_dump = '0; + cpu_crash_dump_t expected_cpu_dump = '0; + alert_crashdump_t prev_alert_dump = '0; + cpu_crash_dump_t prev_cpu_dump = '0; + + // Expect reset info to be POR when running the sequence standalone. + if (is_running_sequence("rstmgr_reset_vseq")) begin + check_reset_info(1, "expected reset_info to be POR"); + check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(1'b0)); + end + + `DV_CHECK_RANDOMIZE_FATAL(this) + + // Clear reset_info register, and enable cpu and alert info capture. + set_alert_info_for_capture(alert_dump, alert_enable); + set_cpu_info_for_capture(cpu_dump, cpu_enable); + csr_wr(.ptr(ral.reset_info), .value('1)); + + // We need to start with an AON reset to process non-capturing resets. + if (start_reset == ResetPOR) por_reset(); + else if (start_reset == ResetScan) send_scan_reset(); + + // On either of these resets we expect captures to be all zero and enables to be off. + expected_alert_dump = '0; + expected_cpu_dump = '0; + expected_alert_enable = 0; + expected_cpu_enable = 0; + + cfg.clk_rst_vif.wait_clks(8); + // Wait till rst_lc_n is inactive for non-aon. + `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_lc_n[1]) + + check_reset_info(get_reset_code(start_reset, 0), {reset_name[start_reset], " reset"}); + check_alert_info_after_reset(expected_alert_dump, expected_alert_enable); + check_cpu_info_after_reset(expected_cpu_dump, expected_cpu_enable); + prev_alert_dump = expected_alert_dump; + prev_cpu_dump = expected_cpu_dump; + + for (int i = 0; i < num_trans; ++i) begin : trans_loop + logic clear_enables; + logic has_aon; + + `uvm_info(`gfn, $sformatf("Starting new round %0d", i), UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + which_resets = create_which_resets(); + set_alert_info_for_capture(alert_dump, alert_enable); + set_cpu_info_for_capture(cpu_dump, cpu_enable); + csr_wr(.ptr(ral.reset_info), .value('1)); + if (which_resets[ResetSw]) begin + sw_reset_csr = MuBi4True; + csr_wr(.ptr(ral.reset_req), .value(sw_reset_csr)); + end + has_aon = has_aon_reset(which_resets); + clear_enables = clear_capture_enable(which_resets); + + `uvm_info(`gfn, $sformatf("Expected to %0s capture enables", clear_enables ? "clear" : "hold" + ), UVM_MEDIUM) + expected_reset_info_code = get_expected_reset_info(which_resets, rstreqs); + expected_alert_enable = alert_enable && !clear_enables; + expected_cpu_enable = cpu_enable && !clear_enables; + expected_alert_dump = has_aon ? '0 : (alert_enable ? alert_dump : prev_alert_dump); + expected_cpu_dump = has_aon ? '0 : (cpu_enable ? cpu_dump : prev_cpu_dump); + `uvm_info(`gfn, resets_description(which_resets, rstreqs), UVM_MEDIUM) + `uvm_info(`gfn, $sformatf("resets with alert_en %b, cpu_en %b", alert_enable, cpu_enable), + UVM_MEDIUM) + + fork + if (which_resets[ResetPOR]) por_reset(.complete_it(0)); + if (which_resets[ResetScan]) send_scan_reset(.complete_it(0)); + if (which_resets[ResetLowPower]) begin + cfg.io_div4_clk_rst_vif.wait_clks(lowpower_rst_cycles); + send_lowpower_reset(.complete_it(0)); + end + if (which_resets[ResetSw]) begin + cfg.io_div4_clk_rst_vif.wait_clks(sw_rst_cycles); + send_sw_reset(.complete_it(0)); + end + if (which_resets[ResetHw]) begin + cfg.io_div4_clk_rst_vif.wait_clks(hw_rst_cycles); + send_hw_reset(rstreqs, .complete_it(0)); + end + join + #(reset_us * 1us); + reset_done(); + + cfg.io_div4_clk_rst_vif.wait_clks(8); + wait(cfg.rstmgr_vif.resets_o.rst_lc_n[1]); + check_reset_info(expected_reset_info_code); + check_alert_info_after_reset(.alert_dump(expected_alert_dump), + .enable(expected_alert_enable)); + check_cpu_info_after_reset(.cpu_dump(expected_cpu_dump), .enable(expected_cpu_enable)); + if (has_aon) read_and_check_all_csrs_after_reset(); + prev_alert_dump = expected_alert_dump; + prev_cpu_dump = expected_cpu_dump; + end : trans_loop + csr_wr(.ptr(ral.reset_info), .value('1)); + // This clears the info registers to cancel side-effects into other sequences with stress tests. + clear_alert_and_cpu_info(); + endtask : body + +endclass : rstmgr_reset_vseq diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sec_cm_scan_intersig_mubi_vseq.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sec_cm_scan_intersig_mubi_vseq.sv new file mode 100644 index 0000000000000..cb4369acbb47b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sec_cm_scan_intersig_mubi_vseq.sv @@ -0,0 +1,52 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: +// While running smoke test, assert illegal scanmode input +class rstmgr_sec_cm_scan_intersig_mubi_vseq extends rstmgr_smoke_vseq; + + `uvm_object_utils(rstmgr_sec_cm_scan_intersig_mubi_vseq) + + `uvm_object_new + + task body(); + fork + begin : isolation_fork + fork + super.body(); + add_noise(); + join_any + disable fork; + end + join + endtask : body + + task add_noise(); + int delay; + + forever begin + // If scan_rst_ni is active we assume super is doing a scan reset, so keep scanmode_i True. + if (cfg.rstmgr_vif.scan_rst_ni == 1'b1) begin + cfg.rstmgr_vif.scanmode_i = get_rand_mubi4_val(0, 1, 4); + end else begin + cfg.rstmgr_vif.scanmode_i = prim_mubi_pkg::MuBi4True; + end + delay = $urandom_range(5, 30); + fork + // This waits for a certain number of cycles or for a change in scan_rst_ni, + // whichever is sooner, or it could end up skipping a full scan reset. + begin : isolation_fork + fork + // @(edge) is not supported by xcelium, workaround with posedge+negedge + @(posedge cfg.rstmgr_vif.scan_rst_ni or negedge cfg.rstmgr_vif.scan_rst_ni); + cfg.clk_rst_vif.wait_clks(delay); + join_any + disable fork; + end + join + // Somehow without this VCS will scan_rst_ni transitions to 0. + #0; + end + endtask : add_noise +endclass : rstmgr_sec_cm_scan_intersig_mubi_vseq diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv new file mode 100644 index 0000000000000..9d8a05495c66b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv @@ -0,0 +1,116 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Tests the different kinds of reset: POR, low power wakeup, hardware reset, debug_mode reset, +// and software initiated peripheral resets. +class rstmgr_smoke_vseq extends rstmgr_base_vseq; + + `uvm_object_utils(rstmgr_smoke_vseq) + + `uvm_object_new + + constraint rstreqs_non_zero_c {rstreqs != '0;} + constraint sw_rst_regwen_non_trivial_c {sw_rst_regwen != '0 && sw_rst_regwen != '1;} + constraint sw_rst_some_reset_c {sw_rst_regwen & ~sw_rst_ctrl_n != '0;} + + local task wait_between_resets(); + cfg.io_div4_clk_rst_vif.wait_clks(10); + endtask + + task body(); + uvm_reg_data_t exp_reg; + bit is_standalone = is_running_sequence("rstmgr_smoke_vseq"); + // Expect reset info to be POR when running the sequence standalone. + if (is_standalone) begin + check_reset_info(1, "expected reset_info to be POR"); + check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(1'b0)); + end + csr_wr(.ptr(ral.reset_info), .value('1)); + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + + send_scan_reset(); + // Scan reset triggers an AON reset (and all others). + wait(&cfg.rstmgr_vif.resets_o.rst_por_aon_n); + + check_reset_info(1, "expected reset_info to be POR for scan reset"); + // Alert and cpu info settings were reset. Check and re-enable them. + check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(1'b0)); + wait_between_resets(); + + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + + csr_wr(.ptr(ral.reset_info), .value('1)); + + // Send low power entry reset. + send_lowpower_reset(); + exp_reg = csr_utils_pkg::get_csr_val_with_updated_field(ral.reset_info.low_power_exit, '0, 1); + check_reset_info(exp_reg, "expected reset_info to indicate low power"); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 1'b1); + wait_between_resets(); + + csr_wr(.ptr(ral.reset_info), .value('1)); + + // Send HwReq. + // Enable alert_info and cpu_info capture. + `DV_CHECK_RANDOMIZE_FATAL(this) + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + + send_hw_reset(rstreqs); + exp_reg = csr_utils_pkg::get_csr_val_with_updated_field(ral.reset_info.hw_req, '0, rstreqs); + check_reset_info(exp_reg, $sformatf("expected reset_info to match 0x%x", exp_reg)); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 1'b0); + wait_between_resets(); + + csr_wr(.ptr(ral.reset_info), .value('1)); + + `DV_CHECK_RANDOMIZE_FATAL(this) + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + + `DV_CHECK_RANDOMIZE_FATAL(this) + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + + // Send sw reset. + csr_wr(.ptr(ral.reset_req), .value(MuBi4True)); + send_sw_reset(); + exp_reg = csr_utils_pkg::get_csr_val_with_updated_field(ral.reset_info.sw_reset, '0, 1); + check_reset_info(exp_reg, "Expected reset_info to indicate sw reset"); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 0); + wait_between_resets(); + + csr_wr(.ptr(ral.reset_info), .value('1)); + + // Testing software resets: only run this when the sequence is run standalone, since + // setting sw_rst_regwen is irreversible. + if (is_standalone) begin : sw_rst + logic [NumSwResets-1:0] exp_ctrl_n; + const logic [NumSwResets-1:0] sw_rst_all_ones = '1; + alert_crashdump_t bogus_alert_dump = '1; + cpu_crash_dump_t bogus_cpu_dump = '1; + + set_alert_and_cpu_info_for_capture(bogus_alert_dump, bogus_cpu_dump); + rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_ctrl_n), .compare_value(sw_rst_all_ones), + .err_msg("expected no reset on")); + rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_regwen), .value(sw_rst_regwen)); + `uvm_info(`gfn, $sformatf("sw_rst_regwen set to 0x%0h", sw_rst_regwen), UVM_LOW) + rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_regwen), .compare_value(sw_rst_regwen)); + + // This is probably also tested by common CSR tests. + // Check sw_rst_regwen can not be set to all ones again because it is rw0c. + rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_regwen), .value({NumSwResets{1'b1}})); + rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_regwen), .compare_value(sw_rst_regwen), + .err_msg("Expected sw_rst_regwen block raising individual bits because rw0c")); + + // Check that the regwen disabled bits block corresponding updated to ctrl_n. + rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_ctrl_n), .value(sw_rst_regwen)); + rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_ctrl_n), .compare_value(sw_rst_all_ones), + .err_msg("Expected sw_rst_ctrl_n not to change")); + + check_sw_rst_ctrl_n(sw_rst_ctrl_n, sw_rst_regwen, 1); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 1'b1); + end : sw_rst + // This clears the info registers to cancel side-effects into other sequences with stress tests. + clear_alert_and_cpu_info(); + endtask : body + +endclass : rstmgr_smoke_vseq diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_stress_all_vseq.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_stress_all_vseq.sv new file mode 100644 index 0000000000000..0ab994ac1c83e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_stress_all_vseq.sv @@ -0,0 +1,37 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// combine all rstmgr seqs (except below seqs) in one seq to run sequentially +// 1. csr seq, which requires scb to be disabled +class rstmgr_stress_all_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_stress_all_vseq) + + `uvm_object_new + + task body(); + string seq_names[] = {"rstmgr_reset_vseq", "rstmgr_smoke_vseq", "rstmgr_sw_rst_vseq"}; + for (int i = 1; i <= num_trans; i++) begin + uvm_sequence seq; + rstmgr_base_vseq rstmgr_vseq; + uint seq_idx = $urandom_range(0, seq_names.size - 1); + + seq = create_seq_by_name(seq_names[seq_idx]); + `downcast(rstmgr_vseq, seq) + + // if upper seq disables do_apply_reset for this seq, then can't issue reset + // as upper seq may drive reset + if (do_apply_reset) rstmgr_vseq.do_apply_reset = $urandom_range(0, 1); + else rstmgr_vseq.do_apply_reset = 0; + rstmgr_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(rstmgr_vseq) + `uvm_info(`gfn, $sformatf("seq_idx = %0d, sequence is %0s", seq_idx, rstmgr_vseq.get_name()), + UVM_MEDIUM) + + rstmgr_vseq.start(p_sequencer); + `uvm_info(`gfn, $sformatf( + "End of sequence %0s with seq_idx = %0d", rstmgr_vseq.get_name(), seq_idx), + UVM_MEDIUM) + end + endtask : body +endclass diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_reset_race_vseq.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_reset_race_vseq.sv new file mode 100644 index 0000000000000..1e38ad100cadd --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_reset_race_vseq.sv @@ -0,0 +1,59 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Tests the software reset functionality: using `sw_rst_regen` and `sw_rst_ctrl_n` CSRs it causes +// resets for each of the bits randomly. It also triggers lc or sys resets to verify the reset +// transitions that cause rising upper resets but non-rising leafs. +// +// Then it clears specific `sw_rst_regwen` bits and attempts to cause resets to determine +// the bits with `sw_rst_regwen` cleared cannot cause a reset. +class rstmgr_sw_rst_reset_race_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_sw_rst_reset_race_vseq) + + `uvm_object_new + rand int cycles_before_sw_rst; + rand int cycles_before_reset; + + // When reset is issued the clocks will be stopped, so the sw_rst_ctrl_n writes must + // start before reset to be safe, or this could wait forever since the clock will stop. + constraint cycles_racing_c { + solve cycles_before_reset before cycles_before_sw_rst; + cycles_before_reset inside {[2 : 8]}; + cycles_before_sw_rst inside {[1 : cycles_before_reset - 1]}; + } + + constraint rstreqs_non_zero_c {rstreqs != '0;} + + task body(); + bit [NumSwResets-1:0] exp_ctrl_n; + bit [NumSwResets-1:0] sw_rst_regwen = '1; + int expected; + alert_pkg::alert_crashdump_t bogus_alert_dump = '1; + rv_core_ibex_pkg::cpu_crash_dump_t bogus_cpu_dump = '1; + set_alert_and_cpu_info_for_capture(bogus_alert_dump, bogus_cpu_dump); + + for (int i = 0; i < num_trans; ++i) begin + csr_wr(.ptr(ral.reset_info), .value('1)); + + `DV_CHECK_RANDOMIZE_FATAL(this) + fork + begin + cfg.clk_rst_vif.wait_clks(cycles_before_sw_rst); + check_sw_rst_ctrl_n(sw_rst_ctrl_n, sw_rst_regwen, 0); + `uvm_info(`gfn, "Done with sw_rst", UVM_MEDIUM) + end + begin + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + send_hw_reset(rstreqs, .complete_it(0)); + `uvm_info(`gfn, "Done with send_reset", UVM_MEDIUM) + end + join + #(reset_us * 1us); + reset_done(); + clear_sw_rst_ctrl_n(); + expected = rstreqs << ral.reset_info.hw_req.get_lsb_pos(); + check_reset_info(expected, $sformatf("expected reset_info to match 0x%x", expected)); + end + endtask +endclass diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_vseq.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_vseq.sv new file mode 100644 index 0000000000000..edb0ba7d24d21 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_vseq.sv @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Tests the software reset functionality: using `sw_rst_regen` and `sw_rst_ctrl_n` CSRs it causes +// resets for each of the bits randomly. It also triggers lc or sys resets to verify the reset +// transitions that cause rising upper resets but non-rising leafs. +// +// Then it clears each `sw_rst_regwen` bits and attempts to cause resets to determine +// the bits with `sw_rst_regwen` cleared cannot cause a reset. +class rstmgr_sw_rst_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_sw_rst_vseq) + + `uvm_object_new + + task body(); + bit [NumSwResets-1:0] exp_ctrl_n; + bit [NumSwResets-1:0] sw_rst_regwen = '1; + alert_crashdump_t bogus_alert_dump = '1; + cpu_crash_dump_t bogus_cpu_dump = '1; + set_alert_and_cpu_info_for_capture(bogus_alert_dump, bogus_cpu_dump); + + for (int i = 0; i < num_trans; ++i) begin + `DV_CHECK_RANDOMIZE_FATAL(this) + check_sw_rst_ctrl_n(sw_rst_ctrl_n, sw_rst_regwen, i % 2); + end + // Only run this part of the test if running standalone. Doing this in a stress test + // messes things up since setting the sw_rst_regwen CSR is irreversible. + if (is_running_sequence("rstmgr_sw_rst_vseq")) begin + // In preparation for the per-bit enable test, set sw_rst_ctrl_n to all 1. + rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_ctrl_n), .value({NumSwResets{1'b1}})); + for (int i = 0; i < NumSwResets; ++i) begin + // Clear the regwen. + bit [NumSwResets-1:0] val_regwen = ~(1 << i); + bit [NumSwResets-1:0] exp_regwen = (~0) << (i + 1); + `uvm_info(`gfn, $sformatf("clearing sw_rst_regwen[%0d]", i), UVM_LOW) + csr_wr(.ptr(ral.sw_rst_regwen[i]), .value(val_regwen[i])); + check_sw_rst_regwen(exp_regwen); + check_sw_rst_ctrl_n(.sw_rst_ctrl_n('0), .sw_rst_regwen(exp_regwen), .erase_ctrl_n(1'b1)); + check_sw_rst_ctrl_n(.sw_rst_ctrl_n('1), .sw_rst_regwen(exp_regwen), .erase_ctrl_n(1'b1)); + // Check we cannot set it back. + csr_wr(.ptr(ral.sw_rst_regwen[i]), .value(1)); + csr_rd_check(.ptr(ral.sw_rst_regwen[i]), .compare_value(0), + .err_msg($sformatf("sw_rst_regwen[%0d] cannot be set back to 1", i))); + end + check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(1'b1)); + end + endtask +endclass diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_vseq_list.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_vseq_list.sv new file mode 100644 index 0000000000000..10d98cad9bf90 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_vseq_list.sv @@ -0,0 +1,15 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "rstmgr_base_vseq.sv" +`include "rstmgr_por_stretcher_vseq.sv" +`include "rstmgr_reset_vseq.sv" +`include "rstmgr_smoke_vseq.sv" +`include "rstmgr_stress_all_vseq.sv" +`include "rstmgr_sw_rst_reset_race_vseq.sv" +`include "rstmgr_sw_rst_vseq.sv" +`include "rstmgr_common_vseq.sv" +`include "rstmgr_sec_cm_scan_intersig_mubi_vseq.sv" +`include "rstmgr_leaf_rst_cnsty_vseq.sv" +`include "rstmgr_leaf_rst_shadow_attack_vseq.sv" diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/cov_manual_excl.el b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/cov_manual_excl.el new file mode 100644 index 0000000000000..f152dfdd346ef --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/cov_manual_excl.el @@ -0,0 +1,15 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +//================================================== +// This file contains the Excluded objects +// Generated By User: maturana +// Format Version: 2 +// Date: Wed Nov 16 12:45:49 2022 +// ExclMode: default +//================================================== +CHECKSUM: "3681358461" +INSTANCE: tb.dut.u_child_handshake +ANNOTATION: "[UNR] src_req_i and req_chk_i are tied to constants" +Assert SyncReqAckHoldReq "assertion" diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/cov_unr_excl.el b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/cov_unr_excl.el new file mode 100644 index 0000000000000..75fe8118bd0af --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/cov_unr_excl.el @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +//================================================== +// This file contains the Excluded objects +// Generated By User: maturana +// Format Version: 2 +// Date: Wed Nov 16 20:32:58 2022 +// ExclMode: default +//================================================== +CHECKSUM: "1154881809 722956608" +INSTANCE: tb.dut +ANNOTATION: "VC_COV_UNR" +Condition 4 "1172916134" "(sync_child_rst && ((!sync_parent_rst))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 5 "1866172979" "(sync_parent_rst && ((!sync_child_rst))) 1 -1" (2 "10") diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/data/rstmgr_cnsty_chk_testplan.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/data/rstmgr_cnsty_chk_testplan.hjson new file mode 100644 index 0000000000000..8c1d365bb0a89 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/data/rstmgr_cnsty_chk_testplan.hjson @@ -0,0 +1,43 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "rstmgr_cnsty_chk" + testpoints: [ + { + name: unexpected_child_reset_activity + desc: '''Verify unexpected child_reset activity flags an error. + ''' + stage: V2S + tests: ["rstmgr_cnsty_chk_smoke"] + } + { + name: child_reset_asserts_late + desc: '''Verify error triggered if child reset asserts late. + ''' + stage: V2S + tests: [] + } + { + name: child_reset_releases_late + desc: '''Verify error triggered if child reset releases late. + ''' + stage: V2S + tests: [] + } + { + name: parent_reset_asserts_late + desc: '''Verify error triggered if parent reset asserts late. + ''' + stage: V2S + tests: [] + } + { + name: parent_reset_releases_late + desc: '''Verify error triggered if parent reset releases late. + ''' + stage: V2S + tests: [] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core new file mode 100644 index 0000000000000..11c3cfc7e74fe --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core @@ -0,0 +1,32 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:rstmgr_cnsty_chk_sim:0.1" +description: "Rstmgr_cnsty_chk DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip:rstmgr_cnsty_chk + - lowrisc:dv:sec_cm + file_type: systemVerilogSource + + files_dv: + depend: + - lowrisc:dv:dv_utils + - lowrisc:dv:dv_test_status + - lowrisc:dv:common_ifs + files: + - tb.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson new file mode 100644 index 0000000000000..6be0a77e0858a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson @@ -0,0 +1,57 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: rstmgr_cnsty_chk + + // Top level dut name (sv module). + dut: rstmgr_cnsty_chk + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:dv:rstmgr_cnsty_chk_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/data/rstmgr_cnsty_chk_testplan.hjson" + + // Import additional common sim cfg files. + import_cfgs: ["{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson"] + + + // Specific exclusion files. + vcs_cov_excl_files: ["{self_dir}/cov_manual_excl.el", + "{self_dir}/cov_unr_excl.el"] + + // Default iterations for all tests - each test entry can override this. + reseed: 10 + + // Enable cdc instrumentation. + run_opts: ["+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: rstmgr_cnsty_chk_test + } + ] + // List of regressions. + regressions: [ + { + name: smoke + tests: ["rstmgr_cnsty_chk_test"] + } + ] + overrides: [ + // This override is in order to pick the autogen rstmgr packages. + { + name: design_level + value: "top" + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/tb.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/tb.sv new file mode 100644 index 0000000000000..560e7c57ae4a7 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/tb.sv @@ -0,0 +1,471 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Testbench module for rstmgr_cnsty_chk. +// +// The test runs pairs of events separated by a variable number of cycles in order to determine +// when errors are triggered. +// +// Consider events E1 and E2: it can send E1 from N cycles before E2 up to M cycles after it and +// any number of cycles in between. +// +// The event pairs considered are: +// - Parent reset active, child reset active +// - Sw reset active, child reset active +// - Parent reset inactive, child reset inactive +// - Sw reset inactive, child reset inactive +// +// There are two clocks involved, and it tests either one running faster then the other. +// +// In order to improve coverage it also injects sparse fsm errors. + +// Interface driving the dut. +interface rstmgr_cnsty_chk_if; + logic child_rst_ni; + logic parent_rst_ni; + logic sw_rst_req_i; + logic sw_rst_req_clr_o; + logic err_o; + logic fsm_err_o; +endinterface + +// Class generating stimulus. +class reset_class; + parameter time ClkPeriod = 10_000; + parameter time ChildFastClkPeriod = 6_543; + parameter time ChildSlowClkPeriod = 25_678; + + parameter int ScanSweepBeforeCycles = 50; + parameter int ScanSweepAfterCycles = 10; + parameter int ScanSweepCycles = ScanSweepBeforeCycles + ScanSweepAfterCycles; + + parameter int IterationsPerDelta = 16; + + import uvm_pkg::*; + + typedef enum int { + OrderChildLags, + OrderChildLeads + } order_e; + + typedef enum int { + TimingOkay, + TimingSlow + } timing_e; + + typedef enum int { + ChildClkFaster, + ChildClkSlower + } child_clk_e; + + typedef struct packed { + order_e order; + timing_e timing; + } reset_op_t; + + virtual clk_rst_if clk_rst_vif; + virtual clk_rst_if child_clk_rst_vif; + virtual rstmgr_cnsty_chk_if reset_vif; + + logic error = 0; + int cycles_to_check = 8; + + bit parent_rst_n; + bit sw_reset; + + int cycles_to_child_reset; + int cycles_to_child_release; + int cycles_to_parent_reset; + int cycles_to_parent_release; + int cycles_to_sw_reset; + int cycles_to_sw_release; + + rand int cycles_reset_width; + rand int cycles_child_reset_width; + rand int cycles_in_apply_resets; + + constraint cycles_reset_width_c {cycles_reset_width inside {[2 : 10]};} + constraint cycles_child_reset_width_c {cycles_child_reset_width inside {[2 : 10]};} + constraint cycles_in_apply_resets_c {cycles_in_apply_resets inside {[5 : 25]};} + + function new(virtual clk_rst_if clk_vif, virtual clk_rst_if child_clk_vif, + virtual rstmgr_cnsty_chk_if rst_vif); + clk_rst_vif = clk_vif; + child_clk_rst_vif = child_clk_vif; + reset_vif = rst_vif; + endfunction + + function string get_full_name(); + return "reset_class"; + endfunction + + task set_child_period(child_clk_e child_clk); + if (child_clk == ChildClkFaster) begin + `uvm_info(`gfn, $sformatf( + "Setting child clk (%0d ps) faster than reference (%0d ps)", + ChildFastClkPeriod, + ClkPeriod + ), UVM_LOW) + child_clk_rst_vif.set_period_ps(ChildFastClkPeriod); + end else begin + `uvm_info(`gfn, $sformatf( + "Setting child clk (%0d ps) slower than reference (%0d ps)", + ChildSlowClkPeriod, + ClkPeriod + ), UVM_LOW) + child_clk_rst_vif.set_period_ps(ChildSlowClkPeriod); + end + endtask + + task apply_resets(); + `uvm_info(`gfn, "Start apply_resets", UVM_MEDIUM) + fork + clk_rst_vif.apply_reset(.reset_width_clks(cycles_reset_width)); + child_clk_rst_vif.apply_reset(.reset_width_clks(cycles_child_reset_width)); + begin + reset_vif.parent_rst_ni = 1'b0; + clk_rst_vif.wait_clks(cycles_in_apply_resets); + reset_vif.parent_rst_ni = 1'b1; + end + begin + reset_vif.child_rst_ni = 1'b0; + child_clk_rst_vif.wait_clks(cycles_in_apply_resets); + reset_vif.child_rst_ni = 1'b1; + end + join + clk_rst_vif.wait_clks(20); + `uvm_info(`gfn, "End apply_resets", UVM_MEDIUM) + endtask + + task set_quiescent(); + `uvm_info(`gfn, "Setting quiescent inputs", UVM_MEDIUM) + reset_vif.parent_rst_ni = 1'b1; + reset_vif.sw_rst_req_i = 1'b0; + reset_vif.child_rst_ni = 1'b1; + endtask + + task set_parent_reset(logic value, int cycles); + if (reset_vif.parent_rst_ni == value) return; + `uvm_info(`gfn, $sformatf("Setting parent_rst_ni=%b after %0d cycles", value, cycles), UVM_HIGH) + clk_rst_vif.wait_clks(cycles); + reset_vif.parent_rst_ni = value; + endtask + + task set_sw_reset(logic value, int cycles); + if (reset_vif.sw_rst_req_i == value) return; + `uvm_info(`gfn, $sformatf("Setting sw_rst_req_i=%b after %0d cycles", value, cycles), UVM_HIGH) + clk_rst_vif.wait_clks(cycles); + reset_vif.sw_rst_req_i = value; + endtask + + task set_child_reset(logic value, int cycles); + if (reset_vif.child_rst_ni == value) return; + `uvm_info(`gfn, $sformatf("Setting child_rst_ni=%b after %0d cycles", value, cycles), UVM_HIGH) + clk_rst_vif.wait_clks(cycles); + reset_vif.child_rst_ni = value; + endtask + + task reset_start(); + fork + set_parent_reset(.value(parent_rst_n), .cycles(cycles_to_parent_reset)); + set_sw_reset(.value(sw_reset), .cycles(cycles_to_sw_reset)); + set_child_reset(.value(0), .cycles(cycles_to_child_reset)); + join + endtask + + task reset_end(); + fork + set_parent_reset(.value(1), .cycles(cycles_to_parent_release)); + set_sw_reset(.value(0), .cycles(cycles_to_sw_release)); + set_child_reset(.value(1), .cycles(cycles_to_child_release)); + join + endtask + + // Run a number of reset scenarios with some given cycle delays to allow CDC cycle fluctuations. + task run_iterations(input string description, input int delta_cycles, output int error_count); + error_count = 0; + for (int i = 0; i < IterationsPerDelta; ++i) begin + set_quiescent(); + reset_start(); + clk_rst_vif.wait_clks(20); + reset_end(); + clk_rst_vif.wait_clks(cycles_to_check); + if (reset_vif.err_o) begin + ++error_count; + end + `uvm_info(`gfn, $sformatf( + "Scan %0s with cycles delta %0d error %b", + description, + delta_cycles, + reset_vif.err_o + ), UVM_HIGH) + // May get error, so reset. + set_quiescent(); + apply_resets(); + end + endtask + + // Run a parent reset to child reset. + task scan_parent_rst(); + `uvm_info(`gfn, "scanning parent resets", UVM_LOW) + sw_reset = 0; + parent_rst_n = 0; + cycles_to_parent_release = 4; + cycles_to_child_release = 5; + cycles_to_child_reset = ScanSweepBeforeCycles; + for ( + cycles_to_parent_reset = 0; + cycles_to_parent_reset < ScanSweepCycles; + ++cycles_to_parent_reset + ) begin + int error_count = 0; + int delta_cycles = cycles_to_parent_reset - cycles_to_child_reset; + `uvm_info(`gfn, $sformatf("Sending parent reset %0d cycles from child", delta_cycles), + UVM_MEDIUM) + run_iterations("parent reset", delta_cycles, error_count); + `uvm_info(`gfn, $sformatf( + "Scan parent reset with cycles delta %0d total errors %0d / %0d", + delta_cycles, + error_count, + IterationsPerDelta + ), UVM_LOW) + `DV_CHECK(((delta_cycles <= -4) || (delta_cycles >= 4)) || (error_count == 0)) + `DV_CHECK(((delta_cycles >= -5) && (delta_cycles <= 5)) || + (error_count == IterationsPerDelta)) + end + endtask + + task scan_parent_release(); + `uvm_info(`gfn, "scanning parent release", UVM_LOW) + sw_reset = 0; + parent_rst_n = 0; + cycles_to_parent_reset = 5; + cycles_to_child_reset = 5; + cycles_to_child_release = ScanSweepBeforeCycles; + for ( + cycles_to_parent_release = 0; + cycles_to_parent_release < ScanSweepCycles; + ++cycles_to_parent_release + ) begin + int error_count = 0; + int delta_cycles = cycles_to_parent_release - cycles_to_child_release; + `uvm_info(`gfn, $sformatf("Sending parent release %0d cycles from child", delta_cycles), + UVM_MEDIUM) + run_iterations("parent release", delta_cycles, error_count); + `uvm_info(`gfn, $sformatf( + "Scan parent release with cycles delta %0d total errors %0d / %0d", + delta_cycles, + error_count, + IterationsPerDelta + ), UVM_LOW) + `DV_CHECK((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0)) + `DV_CHECK(((delta_cycles > -42) && (delta_cycles < 2)) || (error_count == IterationsPerDelta)) + end + endtask + + task scan_sw_rst(); + `uvm_info(`gfn, "scanning sw resets", UVM_LOW) + sw_reset = 1; + parent_rst_n = 1; + cycles_to_sw_release = 4; + cycles_to_child_release = 5; + cycles_to_child_reset = ScanSweepBeforeCycles; + for (cycles_to_sw_reset = 0; cycles_to_sw_reset < ScanSweepCycles; ++cycles_to_sw_reset) begin + int error_count = 0; + int delta_cycles = cycles_to_sw_reset - cycles_to_child_reset; + `uvm_info(`gfn, $sformatf("Sending sw reset %0d cycles from child", delta_cycles), UVM_HIGH) + run_iterations("sw reset", delta_cycles, error_count); + `uvm_info(`gfn, $sformatf( + "Scan sw reset with cycles delta %0d total errors %0d / %0d", + delta_cycles, + error_count, + IterationsPerDelta + ), UVM_LOW) + `DV_CHECK((delta_cycles >= 3) || (error_count == 0)) + `DV_CHECK((delta_cycles <= 3) || (error_count == IterationsPerDelta)) + end + endtask + + task scan_sw_release(); + `uvm_info(`gfn, "scanning sw releases", UVM_LOW) + sw_reset = 1; + parent_rst_n = 1; + cycles_to_sw_reset = 4; + cycles_to_child_reset = 5; + cycles_to_child_release = ScanSweepBeforeCycles; + for ( + cycles_to_sw_release = 0; cycles_to_sw_release < ScanSweepCycles; ++cycles_to_sw_release + ) begin + int error_count = 0; + int delta_cycles = cycles_to_sw_release - cycles_to_child_release; + `uvm_info(`gfn, $sformatf("Sending sw release %0d cycles from child", delta_cycles), UVM_HIGH) + run_iterations("sw release", delta_cycles, error_count); + `uvm_info(`gfn, $sformatf( + "Scan sw release with cycles delta %0d total errors %0d / %0d", + delta_cycles, + error_count, + IterationsPerDelta + ), UVM_LOW) + `DV_CHECK((delta_cycles < -8) || (delta_cycles > 3) || (error_count == 0)) + `DV_CHECK(((delta_cycles > -38) && (delta_cycles < 5)) || (error_count == IterationsPerDelta)) + end + endtask + + task inject_fsm_errors(); + sec_cm_pkg::sec_cm_base_if_proxy if_proxy = sec_cm_pkg::find_sec_cm_if_proxy( + "tb.dut.u_state_regs", 0 + ); + `DV_CHECK(!reset_vif.fsm_err_o) + repeat (10) begin + clk_rst_vif.wait_clks(5); + if_proxy.inject_fault(); + clk_rst_vif.wait_clks(5); + if_proxy.restore_fault(); + `DV_CHECK(reset_vif.fsm_err_o) + apply_resets(); + `DV_CHECK(!reset_vif.fsm_err_o) + end + clk_rst_vif.wait_clks(5); + endtask + + task body(); + foreach (sec_cm_pkg::sec_cm_if_proxy_q[i]) begin + `uvm_info(`gfn, $sformatf("Path of proxy: %0s", sec_cm_pkg::sec_cm_if_proxy_q[i].path), + UVM_MEDIUM) + end + clk_rst_vif.set_period_ps(ClkPeriod); + clk_rst_vif.set_active(); + child_clk_rst_vif.set_period_ps(ChildFastClkPeriod); + child_clk_rst_vif.set_active(); + `DV_CHECK_RANDOMIZE_FATAL(this); + + `uvm_info(`gfn, "Past set active", UVM_MEDIUM) + set_quiescent(); + apply_resets(); + + // Run with child clock faster than reference. + set_child_period(ChildClkFaster); + clk_rst_vif.wait_clks(20); + + set_quiescent(); + apply_resets(); + scan_parent_rst(); + + set_quiescent(); + apply_resets(); + scan_parent_release(); + + set_quiescent(); + apply_resets(); + scan_sw_rst(); + + set_quiescent(); + apply_resets(); + scan_sw_release(); + + set_quiescent(); + apply_resets(); + + // Run with child clock slower than reference. + set_child_period(ChildClkSlower); + clk_rst_vif.wait_clks(20); + + set_quiescent(); + apply_resets(); + scan_parent_rst(); + + set_quiescent(); + apply_resets(); + scan_parent_release(); + + set_quiescent(); + apply_resets(); + scan_sw_rst(); + + set_quiescent(); + apply_resets(); + scan_sw_release(); + + // And inject sparse fsm errors. + set_quiescent(); + apply_resets(); + inject_fsm_errors(); + endtask +endclass + +module tb; + + import uvm_pkg::*; + + reset_class reset_cl; + + wire clk_i; + wire rst_ni; + wire child_clk_i; + wire unused_child_rst_ni; + + bind prim_sparse_fsm_flop prim_sparse_fsm_flop_if #( + .Width(Width), + .CustomForceName(CustomForceName) + ) prim_sparse_fsm_flop_if (.*); + + clk_rst_if clk_rst_if ( + .clk (clk_i), + .rst_n(rst_ni) + ); + clk_rst_if child_clk_rst_if ( + .clk (child_clk_i), + .rst_n(child_rst_ni) + ); + rstmgr_cnsty_chk_if rstmgr_cnsty_chk_if (); + + logic sw_rst_req_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + sw_rst_req_q <= '0; + end else if (sw_rst_req_q && rstmgr_cnsty_chk_if.sw_rst_req_clr_o) begin + sw_rst_req_q <= '0; + end else if (!sw_rst_req_q && rstmgr_cnsty_chk_if.sw_rst_req_i && + !rstmgr_cnsty_chk_if.sw_rst_req_clr_o) begin + sw_rst_req_q <= 1'b1; + end + end + + logic leaf_chk_rst_n; + prim_rst_sync u_prim_rst_sync ( + .clk_i (child_clk_i), + .d_i (rst_ni), + .q_o (leaf_chk_rst_n), + .scan_rst_ni(1'b1), + .scanmode_i(prim_mubi_pkg::MuBi4False) + ); + + rstmgr_cnsty_chk dut ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .child_clk_i(child_clk_i), + .child_rst_ni(rstmgr_cnsty_chk_if.child_rst_ni), + .child_chk_rst_ni(leaf_chk_rst_n), + .parent_rst_ni(rstmgr_cnsty_chk_if.parent_rst_ni), + .sw_rst_req_i(rstmgr_cnsty_chk_if.sw_rst_req_i | sw_rst_req_q), + .sw_rst_req_clr_o(rstmgr_cnsty_chk_if.sw_rst_req_clr_o), + .err_o(rstmgr_cnsty_chk_if.err_o), + .fsm_err_o(rstmgr_cnsty_chk_if.fsm_err_o) + ); + + // set this to one to avoid a SVA error + // This SVA is to ensure we have a fatal alert check attached to the FSM error, but this is unit + // level testbench, no alert will occur. + assign dut.u_state_regs.unused_assert_connected = 1; + initial begin + automatic dv_utils_pkg::dv_report_server dv_report_server = new(); + $timeformat(-12, 0, " ps", 12); + uvm_report_server::set_server(dv_report_server); + reset_cl = new(clk_rst_if, child_clk_rst_if, rstmgr_cnsty_chk_if); + reset_cl.body(); + dv_report_server.report_summarize(); + $finish(); + end + +endmodule : tb diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core new file mode 100644 index 0000000000000..c9d6ae318a74f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:rstmgr_sim:0.1" +description: "RSTMGR DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip_interfaces:rstmgr + + files_dv: + depend: + - lowrisc:dv:rstmgr_test + - lowrisc:dv:rstmgr_sva + files: + - tb.sv + - cov/rstmgr_cov_bind.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson new file mode 100644 index 0000000000000..58d13fb308a0b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson @@ -0,0 +1,113 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: rstmgr + + // Top level dut name (sv module). + dut: rstmgr + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:dv:rstmgr_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/rstmgr_testplan.hjson" + + // RAL spec - used to generate the RAL model. + ral_spec: "{self_dir}/../data/rstmgr.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + // Just run the stress_all sequence, and don't inject random + // resets since we may get overlapping resets due to sequences + // that inject them. + "{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson" + ] + + // Specific exclusion files. + vcs_cov_excl_files: ["{self_dir}/cov/rstmgr_unr_excl.el"] + + // Overrides + overrides: [ + { + name: design_level + value: "top" + } + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover.cfg+{proj_root}/hw/dv/tools/vcs/common_cov_excl.cfg+{self_dir}/cov/rstmgr_cover.cfg+{self_dir}/cov/rstmgr_tgl_excl.cfg" + } + ] + + // Add additional tops for simulation. + sim_tops: ["rstmgr_bind", "rstmgr_cov_bind", + "sec_cm_prim_sparse_fsm_flop_bind", + "sec_cm_prim_onehot_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Default UVM test and seq class name. + uvm_test: rstmgr_base_test + uvm_test_seq: rstmgr_base_vseq + + // Enable cdc instrumentation. + run_opts: ["+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: rstmgr_smoke + uvm_test_seq: rstmgr_smoke_vseq + } + { + name: rstmgr_por_stretcher + uvm_test_seq: rstmgr_por_stretcher_vseq + } + { + name: rstmgr_reset + uvm_test_seq: rstmgr_reset_vseq + } + { + name: rstmgr_sw_rst_reset_race + uvm_test_seq: rstmgr_sw_rst_reset_race_vseq + } + { + name: rstmgr_sw_rst + uvm_test_seq: rstmgr_sw_rst_vseq + } + { + name: rstmgr_sec_cm_scan_intersig_mubi + uvm_test_seq: rstmgr_sec_cm_scan_intersig_mubi_vseq + } + { + name: rstmgr_leaf_rst_cnsty + uvm_test_seq: rstmgr_leaf_rst_cnsty_vseq + } + { + name: rstmgr_leaf_rst_shadow_attack + uvm_test_seq: rstmgr_leaf_rst_shadow_attack_vseq + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["rstmgr_smoke"] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv new file mode 100644 index 0000000000000..e3467c7d72867 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has assertions that check the read-only value of the alert and cpu_info_attr. +interface rstmgr_attrs_sva_if ( + input logic rst_ni, + input int actual_alert_info_attr, + input int actual_cpu_info_attr, + input int expected_alert_info_attr, + input int expected_cpu_info_attr +); + + initial + @(posedge rst_ni) begin + `ASSERT_I(AlertInfoAttr_A, actual_alert_info_attr == expected_alert_info_attr) + `ASSERT_I(CpuInfoAttr_A, actual_cpu_info_attr == expected_cpu_info_attr) + end +endinterface diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_bind.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_bind.sv new file mode 100644 index 0000000000000..108ba5e290576 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_bind.sv @@ -0,0 +1,104 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module rstmgr_bind; +`ifndef GATE_LEVEL + bind rstmgr tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); + + // In top-level testbench, do not bind the csr_assert_fpv to reduce simulation time. +`ifndef TOP_LEVEL_DV + bind rstmgr rstmgr_csr_assert_fpv rstmgr_csr_assert (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); +`endif + + bind rstmgr rstmgr_cascading_sva_if rstmgr_cascading_sva_if ( + .clk_i, + .clk_aon_i, + .clk_io_div4_i, + .clk_io_div2_i, + .clk_io_i, + .clk_main_i, + .clk_usb_i, + .por_n_i, + .scan_rst_ni, + .scanmode_i, + .resets_o, + .rst_lc_req(pwr_i.rst_lc_req), + .rst_sys_req(pwr_i.rst_sys_req), + .rst_lc_src_n(pwr_o.rst_lc_src_n), + .rst_sys_src_n(pwr_o.rst_sys_src_n) + ); + + bind rstmgr rstmgr_attrs_sva_if rstmgr_attrs_sva_if ( + .rst_ni, + .actual_alert_info_attr(int'(hw2reg.alert_info_attr)), + .actual_cpu_info_attr(int'(hw2reg.cpu_info_attr)), + .expected_alert_info_attr(($bits(alert_dump_i) + 31) / 32), + .expected_cpu_info_attr(($bits(cpu_dump_i) + 31) / 32) + ); + + bind rstmgr pwrmgr_rstmgr_sva_if pwrmgr_rstmgr_sva_if ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clk_slow_i(clk_aon_i), + .rst_slow_ni(&rst_por_aon_n), + // These are actually used for checks. + .rst_lc_req(pwr_i.rst_lc_req), + .rst_sys_req(pwr_i.rst_sys_req), + // The inputs from rstmgr. + .rst_lc_src_n(pwr_o.rst_lc_src_n), + .rst_sys_src_n(pwr_o.rst_sys_src_n) + ); + + bind rstmgr rstmgr_sw_rst_sva_if rstmgr_sw_rst_sva_if ( + .clk_i({ + clk_io_div4_i, + clk_io_div4_i, + clk_io_div4_i, + clk_aon_i, + clk_usb_i, + clk_io_div2_i, + clk_io_i, + clk_io_div4_i + }), + .rst_ni, + .parent_rst_n(rst_sys_src_n[1]), + .ctrl_ns(reg2hw.sw_rst_ctrl_n), + .rst_ens({ + rst_en_o.i2c2[1] == prim_mubi_pkg::MuBi4True, + rst_en_o.i2c1[1] == prim_mubi_pkg::MuBi4True, + rst_en_o.i2c0[1] == prim_mubi_pkg::MuBi4True, + rst_en_o.usb_aon[1] == prim_mubi_pkg::MuBi4True, + rst_en_o.usb[1] == prim_mubi_pkg::MuBi4True, + rst_en_o.spi_host1[1] == prim_mubi_pkg::MuBi4True, + rst_en_o.spi_host0[1] == prim_mubi_pkg::MuBi4True, + rst_en_o.spi_device[1] == prim_mubi_pkg::MuBi4True + }), + .rst_ns({ + resets_o.rst_i2c2_n[1], + resets_o.rst_i2c1_n[1], + resets_o.rst_i2c0_n[1], + resets_o.rst_usb_aon_n[1], + resets_o.rst_usb_n[1], + resets_o.rst_spi_host1_n[1], + resets_o.rst_spi_host0_n[1], + resets_o.rst_spi_device_n[1] + }) + ); + + bind rstmgr rstmgr_rst_en_track_sva_if rstmgr_rst_en_track_sva_if ( + .resets_i(resets_o), + .reset_en_i(rst_en_o), + .clk_aon_i(clk_aon_i), + .clk_io_div4_i(clk_io_div4_i), + .clk_main_i(clk_main_i), + .clk_io_i(clk_io_i), + .clk_io_div2_i(clk_io_div2_i), + .clk_usb_i(clk_usb_i), + .rst_por_ni(rst_por_ni) + ); + +`endif +endmodule diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv new file mode 100644 index 0000000000000..9c138af8a396a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv @@ -0,0 +1,188 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has assertions that check the reset outputs of rstmgr cascade properly. +// This means higher level resets always cause the lower level ones to assert. +// The hierarchy is +// por > lc > sys > specific peripherals +// In addition, a scan reset is at the same level as por. +// +// Local terminology: A cascading relationship is between an "above" and a "below" reset. +// +// Some individual reset outputs will always be off. Allowing for this in general would +// weaken the property that some resets MUST rise following other rise. +// +// Peripheral resets cascade from sys, and are checked in rstmgr_sw_rst_sva_if since they +// require additional inputs. +interface rstmgr_cascading_sva_if ( + input logic clk_i, + input logic clk_aon_i, + input logic clk_io_div2_i, + input logic clk_io_div4_i, + input logic clk_io_i, + input logic clk_main_i, + input logic clk_usb_i, + input [rstmgr_pkg::PowerDomains-1:0] por_n_i, + input rstmgr_pkg::rstmgr_out_t resets_o, + input [rstmgr_pkg::PowerDomains-1:0] rst_lc_req, + input [rstmgr_pkg::PowerDomains-1:0] rst_sys_req, + input [rstmgr_pkg::PowerDomains-1:0] rst_lc_src_n, + input [rstmgr_pkg::PowerDomains-1:0] rst_sys_src_n, + input logic scan_rst_ni, + input prim_mubi_pkg::mubi4_t scanmode_i +); + + // The min and max bounds on the number of cycles for an edge to occur. + typedef struct { + int min; + int max; + } bounds_t; + + // The bounds for a fall and rise edge to occur. + typedef struct { + bounds_t fall; + bounds_t rise; + } edge_bounds_t; + + // This is used to check por_n_i active high leads to a rising edge of rst_por_aon_n[0]. + // The number of cycles with por_n_i stable is 32 plus synchronizers and some filter stages. + localparam edge_bounds_t PorCycles = '{fall: '{min: 0, max: 4}, rise: '{min: 35, max: 40}}; + + // This is used to check for regular synchronizing delay. Reset falls asynchronously so the + // fall min cycles is zero. + localparam edge_bounds_t SyncCycles = '{fall: '{min: 0, max: 3}, rise: '{min: 1, max: 3}}; + + // Cycles are counted from the output rst_por_aon_n or scan reset edges. The rise times can be + // higher since in the chip the aon reset goes through the pwrmgr slow fsm where it causes an + // lc rise request and there may be multiple synchronizers in the path. + localparam edge_bounds_t LcCycles = '{fall: '{min: 0, max: 4}, rise: '{min: 1, max: 4}}; + + // In the real system the rise of rst_lc_src_n is triggered by the pwr_i.rst_lc_req input, + // which can take a few cycles since it comes from the pwrmgr after it gets reset, + // is generated with the aon clock, and gets synchronized before it triggers + // a rise in rst_lc_src_n. There is an SVA for the rise in pwrmgr_rstmgr_sva_if. + + // The cycles are counted from Lc edges. + localparam edge_bounds_t SysCycles = '{fall: '{min: 0, max: 3}, rise: '{min: 1, max: 5}}; + + // The different peripheral edges are synchronized to their respective clocks, + // so these counts assume synchronization and are triggered on the correct clock. + localparam edge_bounds_t PeriCycles = '{fall: '{min: 0, max: 4}, rise: '{min: 2, max: 8}}; + + bit disable_sva; + + // Macros to avoid excessive boiler-plate code below. + `define FALL_ASSERT(_name, _from, _to, _cycles, _clk) \ + `ASSERT(_name``AboveFall_A, \ + $fell(_from) |-> ##[_cycles.fall.min:_cycles.fall.max] _from || !_to, _clk, \ + disable_sva) + + `define RISE_ASSERTS(_name, _from, _to, _cycles, _clk) \ + `ASSERT(_name``AboveRise_A, \ + $rose(_from) ##1 _from [* _cycles.rise.min] |=> ##[0:_cycles.rise.max-_cycles.rise.min] (!_from || _to), _clk, \ + disable_sva) \ + + `define CASCADED_ASSERTS(_name, _from, _to, _cycles, _clk) \ + `FALL_ASSERT(_name, _from, _to, _cycles, _clk) \ + `RISE_ASSERTS(_name, _from, _to, _cycles, _clk) + + // A fall in por_n_i leads to a fall in rst_por_aon_n[0]. + `FALL_ASSERT(CascadePorToAon, por_n_i[rstmgr_pkg::DomainAonSel], + resets_o.rst_por_aon_n[rstmgr_pkg::DomainAonSel], PorCycles, clk_aon_i) + + // A number of consecutive cycles with por_n_i inactive (high) should cause the aon resets to + // become inactive. This checks POR stretching. + + // The antecedent: por_n_i rising and being active for enough cycles. + + logic scanmode; + always_comb scanmode = prim_mubi_pkg::mubi4_test_true_strict(scanmode_i); + + logic scan_reset_n; + always_comb scan_reset_n = !scanmode || scan_rst_ni; + + // In scanmode only scan_rst_ni controls reset, so por_n_i is ignored. + logic aon_por_n_i; + always_comb aon_por_n_i = por_n_i[rstmgr_pkg::DomainAonSel] && !scanmode; + + sequence PorStable_S; + $rose( + aon_por_n_i + ) ##1 aon_por_n_i [* PorCycles.rise.min]; + endsequence + + // The reset stretching assertion. + `ASSERT(StablePorToAonRise_A, + PorStable_S |-> ##[0:(PorCycles.rise.max-PorCycles.rise.min)] + !aon_por_n_i || resets_o.rst_por_aon_n[0], + clk_aon_i, disable_sva) + + // The scan reset to Por. + `ASSERT(ScanRstToAonRise_A, scan_reset_n && scanmode |-> resets_o.rst_por_aon_n[0], clk_aon_i, + disable_sva) + + logic [rstmgr_pkg::PowerDomains-1:0] effective_aon_rst_n; + always_comb + effective_aon_rst_n = resets_o.rst_por_aon_n & {rstmgr_pkg::PowerDomains{scan_reset_n}}; + + // The AON reset triggers the various POR reset for the different clock domains through + // synchronizers. + // The current system doesn't have any consumers of domain 1 por_io_div4, and thus only domain 0 + // cascading is checked here. + `CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv4, effective_aon_rst_n[0], + resets_o.rst_por_io_div4_n[0], SyncCycles, clk_io_div4_i) + + // The internal reset is triggered by one of synchronized por. + logic [rstmgr_pkg::PowerDomains-1:0] por_rst_n; + always_comb por_rst_n = resets_o.rst_por_aon_n; + + logic [rstmgr_pkg::PowerDomains-1:0] local_rst_or_lc_req_n; + always_comb local_rst_or_lc_req_n = por_rst_n & ~rst_lc_req; + + logic [rstmgr_pkg::PowerDomains-1:0] lc_rst_or_sys_req_n; + always_comb lc_rst_or_sys_req_n = por_rst_n & ~rst_sys_req; + + for (genvar pd = 0; pd < rstmgr_pkg::PowerDomains; ++pd) begin : g_power_domains + // The root lc reset is triggered either by the internal reset, or by the pwr_i.rst_lc_req + // input. The latter is checked independently in pwrmgr_rstmgr_sva_if. + `CASCADED_ASSERTS(CascadeLocalRstToLc, local_rst_or_lc_req_n[pd], rst_lc_src_n[pd], LcCycles, + clk_i) + + // The root sys reset is triggered by the lc reset, or independently by external requests. + // The latter is checked independently in pwrmgr_rstmgr_sva_if. + `CASCADED_ASSERTS(CascadeLcToSys, lc_rst_or_sys_req_n[pd], rst_sys_src_n[pd], SysCycles, clk_i) + + // Controlled by rst_sys_src_n. + if (pd == rstmgr_pkg::DomainAonSel) begin : gen_sys_io_div4_chk + `CASCADED_ASSERTS(CascadeSysToSysIoDiv4, rst_sys_src_n[pd], resets_o.rst_sys_io_div4_n[pd], + SysCycles, clk_io_div4_i) + end + end + + // Aon to POR + `CASCADED_ASSERTS(CascadeEffAonToRstPor, effective_aon_rst_n[rstmgr_pkg::DomainAonSel], + resets_o.rst_por_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_main_i) + `CASCADED_ASSERTS(CascadeEffAonToRstPorIo, effective_aon_rst_n[rstmgr_pkg::DomainAonSel], + resets_o.rst_por_io_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_io_i) + `CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv2, effective_aon_rst_n[rstmgr_pkg::DomainAonSel], + resets_o.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_io_div2_i) + `CASCADED_ASSERTS(CascadeEffAonToRstPorUcb, effective_aon_rst_n[rstmgr_pkg::DomainAonSel], + resets_o.rst_por_usb_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_usb_i) + + // Controlled by rst_lc_src_n. + `CASCADED_ASSERTS(CascadeLcToLcAon, rst_lc_src_n[rstmgr_pkg::DomainAonSel], + resets_o.rst_lc_aon_n[rstmgr_pkg::DomainAonSel], SysCycles, clk_aon_i) + `CASCADED_ASSERTS(CascadeLcToLc, rst_lc_src_n[rstmgr_pkg::Domain0Sel], + resets_o.rst_lc_n[rstmgr_pkg::Domain0Sel], SysCycles, clk_main_i) + + // Controlled by rst_sys_src_n. + `CASCADED_ASSERTS(CascadeSysToSys, rst_sys_src_n[rstmgr_pkg::Domain0Sel], + resets_o.rst_sys_n[rstmgr_pkg::Domain0Sel], PeriCycles, clk_main_i) + `CASCADED_ASSERTS(CascadeLcToLcShadowed, rst_lc_src_n[rstmgr_pkg::Domain0Sel], + resets_o.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel], SysCycles, clk_main_i) + + `undef FALL_ASSERT + `undef RISE_ASSERTS + `undef CASCADED_ASSERTS +endinterface diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_rst_en_track_sva_if.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_rst_en_track_sva_if.sv new file mode 100644 index 0000000000000..487fbe7bbdd72 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_rst_en_track_sva_if.sv @@ -0,0 +1,308 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This checks that the outgoing resets and the corresponding reset enable going to alert handler +// are shifted by a single clock cycle. +interface rstmgr_rst_en_track_sva_if ( + input rstmgr_pkg::rstmgr_out_t resets_i, + input rstmgr_pkg::rstmgr_rst_en_t reset_en_i, + input logic clk_aon_i, + input logic clk_io_div4_i, + input logic clk_main_i, + input logic clk_io_i, + input logic clk_io_div2_i, + input logic clk_usb_i, + input logic rst_por_ni +); + import rstmgr_pkg::DomainAonSel; + import rstmgr_pkg::Domain0Sel; + localparam int DELAY = 1; + + `ASSERT(D0RstPorAonEnTracksRstPorAonActive_A, + $fell(resets_i.rst_por_aon_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.por_aon[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_aon_i, + !rst_por_ni) + + `ASSERT(D0RstPorAonEnTracksRstPorAonInactive_A, + $rose(resets_i.rst_por_aon_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_por_aon_n[Domain0Sel] || + reset_en_i.por_aon[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_aon_i, + !rst_por_ni) + + `ASSERT(DAonRstPorAonEnTracksRstPorAonActive_A, + $fell(resets_i.rst_por_aon_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.por_aon[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_aon_i, + !rst_por_ni) + + `ASSERT(DAonRstPorAonEnTracksRstPorAonInactive_A, + $rose(resets_i.rst_por_aon_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_por_aon_n[DomainAonSel] || + reset_en_i.por_aon[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_aon_i, + !rst_por_ni) + + `ASSERT(DAonRstPorEnTracksRstPorActive_A, + $fell(resets_i.rst_por_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.por[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_main_i, + !rst_por_ni) + + `ASSERT(DAonRstPorEnTracksRstPorInactive_A, + $rose(resets_i.rst_por_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_por_n[DomainAonSel] || + reset_en_i.por[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_main_i, + !rst_por_ni) + + `ASSERT(DAonRstPorIoEnTracksRstPorIoActive_A, + $fell(resets_i.rst_por_io_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.por_io[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_i, + !rst_por_ni) + + `ASSERT(DAonRstPorIoEnTracksRstPorIoInactive_A, + $rose(resets_i.rst_por_io_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_por_io_n[DomainAonSel] || + reset_en_i.por_io[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_i, + !rst_por_ni) + + `ASSERT(DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A, + $fell(resets_i.rst_por_io_div2_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.por_io_div2[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_div2_i, + !rst_por_ni) + + `ASSERT(DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A, + $rose(resets_i.rst_por_io_div2_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_por_io_div2_n[DomainAonSel] || + reset_en_i.por_io_div2[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_div2_i, + !rst_por_ni) + + `ASSERT(DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A, + $fell(resets_i.rst_por_io_div4_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.por_io_div4[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A, + $rose(resets_i.rst_por_io_div4_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_por_io_div4_n[DomainAonSel] || + reset_en_i.por_io_div4[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(DAonRstPorUsbEnTracksRstPorUsbActive_A, + $fell(resets_i.rst_por_usb_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.por_usb[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_usb_i, + !rst_por_ni) + + `ASSERT(DAonRstPorUsbEnTracksRstPorUsbInactive_A, + $rose(resets_i.rst_por_usb_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_por_usb_n[DomainAonSel] || + reset_en_i.por_usb[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_usb_i, + !rst_por_ni) + + `ASSERT(D0RstPorUsbEnTracksRstPorUsbActive_A, + $fell(resets_i.rst_por_usb_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.por_usb[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_usb_i, + !rst_por_ni) + + `ASSERT(D0RstPorUsbEnTracksRstPorUsbInactive_A, + $rose(resets_i.rst_por_usb_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_por_usb_n[Domain0Sel] || + reset_en_i.por_usb[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_usb_i, + !rst_por_ni) + + `ASSERT(D0RstLcShadowedEnTracksRstLcShadowedActive_A, + $fell(resets_i.rst_lc_shadowed_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.lc_shadowed[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_main_i, + !rst_por_ni) + + `ASSERT(D0RstLcShadowedEnTracksRstLcShadowedInactive_A, + $rose(resets_i.rst_lc_shadowed_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_lc_shadowed_n[Domain0Sel] || + reset_en_i.lc_shadowed[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_main_i, + !rst_por_ni) + + `ASSERT(DAonRstLcShadowedEnTracksRstLcShadowedActive_A, + $fell(resets_i.rst_lc_shadowed_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.lc_shadowed[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_main_i, + !rst_por_ni) + + `ASSERT(DAonRstLcShadowedEnTracksRstLcShadowedInactive_A, + $rose(resets_i.rst_lc_shadowed_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_lc_shadowed_n[DomainAonSel] || + reset_en_i.lc_shadowed[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_main_i, + !rst_por_ni) + + `ASSERT(DAonRstLcAonEnTracksRstLcAonActive_A, + $fell(resets_i.rst_lc_aon_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.lc_aon[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_aon_i, + !rst_por_ni) + + `ASSERT(DAonRstLcAonEnTracksRstLcAonInactive_A, + $rose(resets_i.rst_lc_aon_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_lc_aon_n[DomainAonSel] || + reset_en_i.lc_aon[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_aon_i, + !rst_por_ni) + + `ASSERT(DAonRstLcIoEnTracksRstLcIoActive_A, + $fell(resets_i.rst_lc_io_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.lc_io[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_i, + !rst_por_ni) + + `ASSERT(DAonRstLcIoEnTracksRstLcIoInactive_A, + $rose(resets_i.rst_lc_io_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_lc_io_n[DomainAonSel] || + reset_en_i.lc_io[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_i, + !rst_por_ni) + + `ASSERT(DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A, + $fell(resets_i.rst_lc_io_div2_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.lc_io_div2[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_div2_i, + !rst_por_ni) + + `ASSERT(DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A, + $rose(resets_i.rst_lc_io_div2_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_lc_io_div2_n[DomainAonSel] || + reset_en_i.lc_io_div2[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_div2_i, + !rst_por_ni) + + `ASSERT(D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A, + $fell(resets_i.rst_lc_io_div4_shadowed_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.lc_io_div4_shadowed[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A, + $rose(resets_i.rst_lc_io_div4_shadowed_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_lc_io_div4_shadowed_n[Domain0Sel] || + reset_en_i.lc_io_div4_shadowed[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A, + $fell(resets_i.rst_lc_io_div4_shadowed_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.lc_io_div4_shadowed[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A, + $rose(resets_i.rst_lc_io_div4_shadowed_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_lc_io_div4_shadowed_n[DomainAonSel] || + reset_en_i.lc_io_div4_shadowed[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(DAonRstLcUsbEnTracksRstLcUsbActive_A, + $fell(resets_i.rst_lc_usb_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.lc_usb[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_usb_i, + !rst_por_ni) + + `ASSERT(DAonRstLcUsbEnTracksRstLcUsbInactive_A, + $rose(resets_i.rst_lc_usb_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_lc_usb_n[DomainAonSel] || + reset_en_i.lc_usb[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_usb_i, + !rst_por_ni) + + `ASSERT(D0RstLcUsbEnTracksRstLcUsbActive_A, + $fell(resets_i.rst_lc_usb_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.lc_usb[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_usb_i, + !rst_por_ni) + + `ASSERT(D0RstLcUsbEnTracksRstLcUsbInactive_A, + $rose(resets_i.rst_lc_usb_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_lc_usb_n[Domain0Sel] || + reset_en_i.lc_usb[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_usb_i, + !rst_por_ni) + + `ASSERT(D0RstSysEnTracksRstSysActive_A, + $fell(resets_i.rst_sys_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.sys[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_main_i, + !rst_por_ni) + + `ASSERT(D0RstSysEnTracksRstSysInactive_A, + $rose(resets_i.rst_sys_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_sys_n[Domain0Sel] || + reset_en_i.sys[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_main_i, + !rst_por_ni) + + `ASSERT(DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A, + $fell(resets_i.rst_sys_io_div4_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.sys_io_div4[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A, + $rose(resets_i.rst_sys_io_div4_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_sys_io_div4_n[DomainAonSel] || + reset_en_i.sys_io_div4[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstSpiDeviceEnTracksRstSpiDeviceActive_A, + $fell(resets_i.rst_spi_device_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.spi_device[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A, + $rose(resets_i.rst_spi_device_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_spi_device_n[Domain0Sel] || + reset_en_i.spi_device[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstSpiHost0EnTracksRstSpiHost0Active_A, + $fell(resets_i.rst_spi_host0_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.spi_host0[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstSpiHost0EnTracksRstSpiHost0Inactive_A, + $rose(resets_i.rst_spi_host0_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_spi_host0_n[Domain0Sel] || + reset_en_i.spi_host0[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstI2c0EnTracksRstI2c0Active_A, + $fell(resets_i.rst_i2c0_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.i2c0[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstI2c0EnTracksRstI2c0Inactive_A, + $rose(resets_i.rst_i2c0_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_i2c0_n[Domain0Sel] || + reset_en_i.i2c0[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + +endinterface diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_sva.core b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_sva.core new file mode 100644 index 0000000000000..440c3f479543f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_sva.core @@ -0,0 +1,35 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:rstmgr_sva:0.1" +description: "RSTMGR assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:prim:mubi + - lowrisc:ip_interfaces:rstmgr_pkg + - lowrisc:fpv:csr_assert_gen + - lowrisc:dv:rstmgr_sva_ifs + + files: + - rstmgr_bind.sv + file_type: systemVerilogSource + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/rstmgr.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + formal: + <<: *default_target + filesets: + - files_dv + toplevel: rstmgr diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_sva_ifs.core b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_sva_ifs.core new file mode 100644 index 0000000000000..e1e04e136731d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_sva_ifs.core @@ -0,0 +1,25 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:rstmgr_sva_ifs:0.1" +description: "RSTMGR cascading resets assertion interface." +filesets: + files_dv: + depend: + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:ip_interfaces:pwrmgr_pkg + - lowrisc:ip_interfaces:rstmgr + - lowrisc:dv:pwrmgr_rstmgr_sva_if + + files: + - rstmgr_attrs_sva_if.sv + - rstmgr_cascading_sva_if.sv + - rstmgr_rst_en_track_sva_if.sv + - rstmgr_sw_rst_sva_if.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv new file mode 100644 index 0000000000000..7be1e05940778 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv @@ -0,0 +1,44 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has assertions that check the output resets read-only value of the alert and cpu_info_attr. +interface rstmgr_sw_rst_sva_if ( + input logic [rstmgr_reg_pkg::NumSwResets-1:0] clk_i, + input logic rst_ni, + input logic parent_rst_n, + input logic [rstmgr_reg_pkg::NumSwResets-1:0] ctrl_ns, + input logic [rstmgr_reg_pkg::NumSwResets-1:0] rst_ens, + input logic [rstmgr_reg_pkg::NumSwResets-1:0] rst_ns +); + parameter int RiseMin = 2; + parameter int RiseMax = 12; + + bit disable_sva; + + for (genvar i = 0; i < rstmgr_reg_pkg::NumSwResets; ++i) begin : gen_assertions + logic rst_cause; + always_comb rst_cause = !parent_rst_n || !ctrl_ns[i]; + + sequence CauseReadyOn_S; + $rose( + rst_cause + ) ##1 rst_cause [* RiseMin]; + endsequence + + sequence CauseReadyOff_S; + $fell( + rst_cause + ) ##1 !rst_cause [* RiseMin]; + endsequence + + `ASSERT(RstNOn_A, CauseReadyOn_S |=> ##[0:RiseMax-RiseMin] !rst_cause || !rst_ns[i], clk_i[i], + !rst_ni || disable_sva) + `ASSERT(RstNOff_A, CauseReadyOff_S |=> ##[0:RiseMax-RiseMin] rst_cause || rst_ns[i], clk_i[i], + !rst_ni || disable_sva) + `ASSERT(RstEnOn_A, CauseReadyOn_S |=> ##[0:RiseMax-RiseMin] !rst_cause || rst_ens[i], clk_i[i], + !rst_ni || disable_sva) + `ASSERT(RstEnOff_A, CauseReadyOff_S |=> ##[0:RiseMax-RiseMin] rst_cause || !rst_ens[i], + clk_i[i], !rst_ni || disable_sva) + end +endinterface diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/tb.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/tb.sv new file mode 100644 index 0000000000000..7dd5cdbab44e4 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/tb.sv @@ -0,0 +1,145 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import rstmgr_env_pkg::*; + import rstmgr_test_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk, rst_n; + wire clk_aon; + wire clk_io_div4_i; + wire clk_main_i; + wire clk_io_i; + wire clk_io_div2_i; + wire clk_usb_i; + + // interfaces + clk_rst_if clk_rst_if ( + .clk, + .rst_n + ); + clk_rst_if aon_clk_rst_if ( + .clk (clk_aon), + .rst_n() + ); + clk_rst_if io_clk_rst_if ( + .clk (clk_io), + .rst_n() + ); + clk_rst_if io_div2_clk_rst_if ( + .clk (clk_io_div2), + .rst_n() + ); + clk_rst_if io_div4_clk_rst_if ( + .clk (clk_io_div4), + .rst_n() + ); + clk_rst_if main_clk_rst_if ( + .clk (clk_main), + .rst_n() + ); + clk_rst_if usb_clk_rst_if ( + .clk (clk_usb), + .rst_n() + ); + + tl_if tl_if ( + .clk, + .rst_n(rstmgr_if.resets_o.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + + rstmgr_if rstmgr_if ( + .clk_aon, + .clk, + .rst_n + ); + + initial begin + clk_rst_if.set_active(); + aon_clk_rst_if.set_active(); + io_clk_rst_if.set_active(); + io_div2_clk_rst_if.set_active(); + io_div4_clk_rst_if.set_active(); + main_clk_rst_if.set_active(); + usb_clk_rst_if.set_active(); + end + + `DV_ALERT_IF_CONNECT() + + // dut + // IMPORTANT: Notice the rst_ni input is connected to one of dut's outputs. + // This is consistent with rstmgr being the only source of resets. + rstmgr dut ( + .clk_i (clk), + .rst_ni (rstmgr_if.resets_o.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .clk_aon_i (clk_aon), + .clk_io_div4_i(clk_io_div4), + .clk_main_i (clk_main), + .clk_io_i (clk_io), + .clk_io_div2_i(clk_io_div2), + .clk_usb_i (clk_usb), + .clk_por_i (clk_io_div4), + .rst_por_ni (rstmgr_if.resets_o.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]), + + .tl_i (tl_if.h2d), + .tl_o (tl_if.d2h), + .alert_rx_i(alert_rx), + .alert_tx_o(alert_tx), + + .por_n_i(rstmgr_if.por_n), + + .pwr_i(rstmgr_if.pwr_i), + .pwr_o(rstmgr_if.pwr_o), + + .sw_rst_req_o (rstmgr_if.sw_rst_req_o), + + .alert_dump_i(rstmgr_if.alert_dump_i), + .cpu_dump_i (rstmgr_if.cpu_dump_i), + + .scan_rst_ni(rstmgr_if.scan_rst_ni), + .scanmode_i (rstmgr_if.scanmode_i), + + .rst_en_o(rstmgr_if.rst_en_o), + .resets_o(rstmgr_if.resets_o) + ); + + initial begin + // drive clk and rst_n from clk_rst_if + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "aon_clk_rst_vif", aon_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "io_clk_rst_vif", io_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "io_div2_clk_rst_vif", + io_div2_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "io_div4_clk_rst_vif", + io_div4_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "main_clk_rst_vif", main_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "usb_clk_rst_vif", usb_clk_rst_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); + + uvm_config_db#(virtual pwrmgr_rstmgr_sva_if)::set(null, "*.env", "pwrmgr_rstmgr_sva_vif", + dut.pwrmgr_rstmgr_sva_if); + uvm_config_db#(virtual rstmgr_cascading_sva_if)::set(null, "*.env", "rstmgr_cascading_sva_vif", + dut.rstmgr_cascading_sva_if); + uvm_config_db#(virtual rstmgr_if)::set(null, "*.env", "rstmgr_vif", rstmgr_if); + + $timeformat(-12, 0, " ps", 12); + run_test(); + end + + initial begin + // This may help any code that depends on clk_rst_vif.rst_n in the infrastructure: they won't + // be able to change but at least the reset value will be true to the environment. + clk_rst_if.drive_rst_n = 1'b0; + force clk_rst_if.rst_n = rstmgr_if.resets_o.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]; + end + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/tests/rstmgr_base_test.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/tests/rstmgr_base_test.sv new file mode 100644 index 0000000000000..a3eaf46e04f0a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/tests/rstmgr_base_test.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_base_test extends cip_base_test #( + .CFG_T(rstmgr_env_cfg), + .ENV_T(rstmgr_env) +); + + `uvm_component_utils(rstmgr_base_test) + `uvm_component_new + + // the base class dv_base_test creates the following instances: + // rstmgr_env_cfg: cfg + // rstmgr_env: env + + // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in + // the run_phase; as such, nothing more needs to be done + +endclass : rstmgr_base_test diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/tests/rstmgr_test.core b/hw/top_darjeeling/ip_autogen/rstmgr/dv/tests/rstmgr_test.core new file mode 100644 index 0000000000000..8b162abee16ac --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/tests/rstmgr_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:rstmgr_test:0.1" +description: "RSTMGR DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:dv:rstmgr_env + files: + - rstmgr_test_pkg.sv + - rstmgr_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/dv/tests/rstmgr_test_pkg.sv b/hw/top_darjeeling/ip_autogen/rstmgr/dv/tests/rstmgr_test_pkg.sv new file mode 100644 index 0000000000000..6bc66f09e85d6 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/dv/tests/rstmgr_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package rstmgr_test_pkg; + // dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import rstmgr_env_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // local types + + // functions + + // package sources + `include "rstmgr_base_test.sv" + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/lint/rstmgr.vlt b/hw/top_darjeeling/ip_autogen/rstmgr/lint/rstmgr.vlt new file mode 100644 index 0000000000000..a345f0dcdf9fe --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/lint/rstmgr.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for rstmgr diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/lint/rstmgr.waiver b/hw/top_darjeeling/ip_autogen/rstmgr/lint/rstmgr.waiver new file mode 100644 index 0000000000000..4958290fba509 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/lint/rstmgr.waiver @@ -0,0 +1,37 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for rstmgr + +# dedicated reset drivers / muxes +set_reset_drivers prim_clock_mux2 prim_flop_2sync prim_flop +set_clock_drivers prim_clock_buf + +waive -rules TERMINAL_STATE -location {rstmgr_cnsty_chk.sv} -regexp {Terminal state 'Error' is detected} \ + -comment "Intentional terminal state" + +# All leaf resets have a reset multiplexer for scan reset +waive -rules RESET_MUX -location {rstmgr.sv rstmgr_por.sv rstmgr_ctrl.sv} -regexp {Asynchronous reset '(resets_o\.)?rst_[A-Za-z_0-9]+_n(\[[0-9:]+\])?' is driven by a multiplexer} \ + -comment "This is dedicated reset infrastructure, and hence permissible" + +waive -rules RESET_MUX -location {rstmgr_leaf_rst.sv} -regexp {Asynchronous reset 'leaf_rst_o' is driven by a multiplexer} \ + -comment "This is dedicated reset infrastructure, and hence permissible" + +waive -rules RESET_MUX -location {rstmgr_leaf_rst.sv} -regexp {Asynchronous reset 'gen_rst_chk.leaf_chk_rst_n' is driven by a multiplexer here, used as a reset 'rst_dst_ni' at} \ + -comment "This is dedicated reset infrastructure, and hence permissible" + +waive -rules RESET_USE -location {rstmgr.sv} -regexp {'rst_(por_aon_)?n\[1\]' is connected to 'rstmgr_ctrl' port 'rst_.*ni*} \ + -comment "Parent Non always on resets are combined with the always on reset first before being used as resets" + +waive -rules RESET_USE -location {rstmgr.sv} -regexp {rst_lc_src_n.* is connected to 'rstmgr_ctrl' port 'rst_parent_ni.*} \ + -comment "Parent resets are used synchronously instead of directly as async resets" + +waive -rules CONST_FF -location {rstmgr_crash_info.sv} -regexp {Flip-flop \'slots_q\[.*\]\[.*\]\' is driven by constant zeros in module \'rstmgr_crash_info\'} \ + -comment "Some bits int the last slot are tied off to zero." + +waive -rules CONST_FF -location {rstmgr_cnsty_chk.sv} -regexp {Flip-flop '(parent|child)_rst_asserted' is driven by constant zero} \ + -comment "These flipflop inputs are driven by zero." + +waive -rules CONST_FF -location {rstmgr_por.sv} -msg {Flip-flop 'rst_filter_n[0]' is driven by constant one} \ + -comment "This flipflops is a reset filter, and the first index is driven by a constant one." diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core new file mode 100644 index 0000000000000..3ae8bb48fa0e1 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr.core @@ -0,0 +1,71 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_rstmgr:0.1 +description: "Reset manager RTL" +virtual: + - lowrisc:ip_interfaces:rstmgr + +filesets: + files_rtl: + depend: + - lowrisc:ip:alert_handler_component + - lowrisc:ip:rv_core_ibex_pkg + - lowrisc:ip:tlul + - lowrisc:prim:clock_mux2 + - lowrisc:prim:esc + - lowrisc:prim:lc_sync + - lowrisc:prim:mubi + - lowrisc:prim:clock_buf + - lowrisc:prim:sparse_fsm + - lowrisc:opentitan:top_darjeeling_rstmgr_pkg:0.1 + - lowrisc:opentitan:top_darjeeling_rstmgr_reg:0.1 + - lowrisc:ip:rstmgr_cnsty_chk + files: + - rtl/rstmgr_ctrl.sv + - rtl/rstmgr_por.sv + - rtl/rstmgr_crash_info.sv + - rtl/rstmgr_leaf_rst.sv + - rtl/rstmgr.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/rstmgr.waiver + file_type: waiver + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - files_rtl + toplevel: rstmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_cnsty_chk.core b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_cnsty_chk.core new file mode 100644 index 0000000000000..1ad8579b55594 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_cnsty_chk.core @@ -0,0 +1,40 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: "lowrisc:ip:rstmgr_cnsty_chk" +description: "Rstmgr consistency checker" +filesets: + files_rtl: + depend: + - lowrisc:prim:all + - lowrisc:prim:sparse_fsm + - lowrisc:ip:rv_core_ibex_pkg + - lowrisc:ip_interfaces:rstmgr_pkg + files: + - rtl/rstmgr_cnsty_chk.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +targets: + default: + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_pkg.core b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_pkg.core new file mode 100644 index 0000000000000..2bb40151a3d3e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_pkg.core @@ -0,0 +1,23 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_rstmgr_pkg:0.1 +description: "Reset manager package" +virtual: + - lowrisc:ip_interfaces:rstmgr_pkg + +filesets: + files_rtl: + depend: + - lowrisc:ip_interfaces:alert_handler_reg + - lowrisc:ip_interfaces:pwrmgr_pkg + - lowrisc:opentitan:top_darjeeling_rstmgr_reg + files: + - rtl/rstmgr_pkg.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_reg.core b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_reg.core new file mode 100644 index 0000000000000..2aa72a7e17024 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rstmgr_reg.core @@ -0,0 +1,22 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_rstmgr_reg:0.1 +description: "Reset manager registers" +virtual: + - lowrisc:ip_interfaces:rstmgr_reg + +filesets: + files_rtl: + depend: + - lowrisc:tlul:headers + files: + - rtl/rstmgr_reg_pkg.sv + - rtl/rstmgr_reg_top.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr.sv b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr.sv new file mode 100644 index 0000000000000..ee11b11306428 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr.sv @@ -0,0 +1,1093 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module is the overall reset manager wrapper + +`include "prim_assert.sv" + + +// This top level controller is fairly hardcoded right now, but will be switched to a template +module rstmgr + import rstmgr_pkg::*; + import rstmgr_reg_pkg::*; + import prim_mubi_pkg::mubi4_t; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter bit SecCheck = 1, + parameter int SecMaxSyncDelay = 2 +) ( + // Primary module clocks + input clk_i, + input rst_ni, + input clk_aon_i, + input clk_io_div4_i, + input clk_main_i, + input clk_io_i, + input clk_io_div2_i, + input clk_usb_i, + input clk_por_i, + input rst_por_ni, + + // POR input + input [PowerDomains-1:0] por_n_i, + + // Bus Interface + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + // pwrmgr interface + input pwrmgr_pkg::pwr_rst_req_t pwr_i, + output pwrmgr_pkg::pwr_rst_rsp_t pwr_o, + + // software initiated reset request + output mubi4_t sw_rst_req_o, + + // Interface to alert handler + input alert_pkg::alert_crashdump_t alert_dump_i, + + // Interface to cpu crash dump + input rv_core_ibex_pkg::cpu_crash_dump_t cpu_dump_i, + + // dft bypass + input scan_rst_ni, + // SEC_CM: SCAN.INTERSIG.MUBI + input prim_mubi_pkg::mubi4_t scanmode_i, + + // Reset asserted indications going to alert handler + output rstmgr_rst_en_t rst_en_o, + + // reset outputs + output rstmgr_out_t resets_o + +); + + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4True; + + // receive POR and stretch + // The por is at first stretched and synced on clk_aon + // The rst_ni and pok_i input will be changed once AST is integrated + logic [PowerDomains-1:0] rst_por_aon_n; + + for (genvar i = 0; i < PowerDomains; i++) begin : gen_rst_por_aon + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] por_scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_por_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o(por_scanmode) + ); + + if (i == DomainAonSel) begin : gen_rst_por_aon_normal + rstmgr_por u_rst_por_aon ( + .clk_i(clk_aon_i), + .rst_ni(por_n_i[i]), + .scan_rst_ni, + .scanmode_i(prim_mubi_pkg::mubi4_test_true_strict(por_scanmode[0])), + .rst_no(rst_por_aon_n[i]) + ); + + // reset asserted indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender ( + .clk_i(clk_aon_i), + .rst_ni(rst_por_aon_n[i]), + .mubi_i(MuBi4False), + .mubi_o(rst_en_o.por_aon[i]) + ); + end else begin : gen_rst_por_domain + logic rst_por_aon_premux; + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_por_domain_sync ( + .clk_i(clk_aon_i), + // do not release from reset if aon has not + .rst_ni(rst_por_aon_n[DomainAonSel] & por_n_i[i]), + .d_i(1'b1), + .q_o(rst_por_aon_premux) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_por_domain_mux ( + .clk0_i(rst_por_aon_premux), + .clk1_i(scan_rst_ni), + .sel_i(prim_mubi_pkg::mubi4_test_true_strict(por_scanmode[0])), + .clk_o(rst_por_aon_n[i]) + ); + + // reset asserted indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender ( + .clk_i(clk_aon_i), + .rst_ni(rst_por_aon_n[i]), + .mubi_i(MuBi4False), + .mubi_o(rst_en_o.por_aon[i]) + ); + end + end + assign resets_o.rst_por_aon_n = rst_por_aon_n; + + logic clk_por; + logic rst_por_n; + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_por_clk_buf ( + .clk_i(clk_por_i), + .clk_o(clk_por) + ); + + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_por_rst_buf ( + .clk_i(rst_por_ni), + .clk_o(rst_por_n) + ); + + //////////////////////////////////////////////////// + // Register Interface // + //////////////////////////////////////////////////// + + rstmgr_reg_pkg::rstmgr_reg2hw_t reg2hw; + rstmgr_reg_pkg::rstmgr_hw2reg_t hw2reg; + + logic reg_intg_err; + // SEC_CM: BUS.INTEGRITY + // SEC_CM: SW_RST.CONFIG.REGWEN, DUMP_CTRL.CONFIG.REGWEN + rstmgr_reg_top u_reg ( + .clk_i, + .rst_ni, + .clk_por_i (clk_por), + .rst_por_ni (rst_por_n), + .tl_i, + .tl_o, + .reg2hw, + .hw2reg, + .intg_err_o(reg_intg_err) + ); + + + //////////////////////////////////////////////////// + // Errors // + //////////////////////////////////////////////////// + + // consistency check errors + logic [15:0][PowerDomains-1:0] cnsty_chk_errs; + logic [15:0][PowerDomains-1:0] shadow_cnsty_chk_errs; + + // consistency sparse fsm errors + logic [15:0][PowerDomains-1:0] fsm_errs; + logic [15:0][PowerDomains-1:0] shadow_fsm_errs; + + assign hw2reg.err_code.reg_intg_err.d = 1'b1; + assign hw2reg.err_code.reg_intg_err.de = reg_intg_err; + assign hw2reg.err_code.reset_consistency_err.d = 1'b1; + assign hw2reg.err_code.reset_consistency_err.de = |cnsty_chk_errs || + |shadow_cnsty_chk_errs; + assign hw2reg.err_code.fsm_err.d = 1'b1; + assign hw2reg.err_code.fsm_err.de = |fsm_errs || |shadow_fsm_errs; + //////////////////////////////////////////////////// + // Alerts // + //////////////////////////////////////////////////// + logic [NumAlerts-1:0] alert_test, alerts; + + // All of these are fatal alerts + assign alerts[0] = reg2hw.err_code.reg_intg_err.q | + (|reg2hw.err_code.fsm_err.q); + + assign alerts[1] = reg2hw.err_code.reset_consistency_err.q; + + assign alert_test = { + reg2hw.alert_test.fatal_cnsty_fault.q & reg2hw.alert_test.fatal_cnsty_fault.qe, + reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe + }; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .IsFatal(1'b1) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[i] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + //////////////////////////////////////////////////// + // Source resets in the system // + // These are hardcoded and not directly used. // + // Instead they act as async reset roots. // + //////////////////////////////////////////////////// + + // The two source reset modules are chained together. The output of one is fed into the + // the second. This ensures that if upstream resets for any reason, the associated downstream + // reset will also reset. + + logic [PowerDomains-1:0] rst_lc_src_n; + logic [PowerDomains-1:0] rst_sys_src_n; + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] rst_ctrl_scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_ctrl_scanmode_sync ( + .clk_i (clk_por), + .rst_ni (rst_por_n), + .mubi_i(scanmode_i), + .mubi_o(rst_ctrl_scanmode) + ); + + // lc reset sources + rstmgr_ctrl u_lc_src ( + .clk_i (clk_por), + .scanmode_i(prim_mubi_pkg::mubi4_test_true_strict(rst_ctrl_scanmode[0])), + .scan_rst_ni, + .rst_req_i(pwr_i.rst_lc_req), + .rst_parent_ni(rst_por_aon_n), + .rst_no(rst_lc_src_n) + ); + + // sys reset sources + rstmgr_ctrl u_sys_src ( + .clk_i (clk_por), + .scanmode_i(prim_mubi_pkg::mubi4_test_true_strict(rst_ctrl_scanmode[0])), + .scan_rst_ni, + .rst_req_i(pwr_i.rst_sys_req), + .rst_parent_ni(rst_por_aon_n), + .rst_no(rst_sys_src_n) + ); + + assign pwr_o.rst_lc_src_n = rst_lc_src_n; + assign pwr_o.rst_sys_src_n = rst_sys_src_n; + + + //////////////////////////////////////////////////// + // leaf reset in the system // + // These should all be generated // + //////////////////////////////////////////////////// + // To simplify generation, each reset generates all associated power domain outputs. + // If a reset does not support a particular power domain, that reset is always hard-wired to 0. + + // Generating resets for por + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_por ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_main_i), + .parent_rst_ni(rst_por_aon_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.por[DomainAonSel]), + .leaf_rst_o(resets_o.rst_por_n[DomainAonSel]), + .err_o(cnsty_chk_errs[0][DomainAonSel]), + .fsm_err_o(fsm_errs[0][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_por_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonPorFsmCheck_A, + u_daon_por.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_por_n[Domain0Sel] = '0; + assign cnsty_chk_errs[0][Domain0Sel] = '0; + assign fsm_errs[0][Domain0Sel] = '0; + assign rst_en_o.por[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[0] = '0; + assign shadow_fsm_errs[0] = '0; + + // Generating resets for por_io + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_por_io ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_i), + .parent_rst_ni(rst_por_aon_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.por_io[DomainAonSel]), + .leaf_rst_o(resets_o.rst_por_io_n[DomainAonSel]), + .err_o(cnsty_chk_errs[1][DomainAonSel]), + .fsm_err_o(fsm_errs[1][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_por_io_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonPorIoFsmCheck_A, + u_daon_por_io.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_por_io_n[Domain0Sel] = '0; + assign cnsty_chk_errs[1][Domain0Sel] = '0; + assign fsm_errs[1][Domain0Sel] = '0; + assign rst_en_o.por_io[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[1] = '0; + assign shadow_fsm_errs[1] = '0; + + // Generating resets for por_io_div2 + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_por_io_div2 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div2_i), + .parent_rst_ni(rst_por_aon_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.por_io_div2[DomainAonSel]), + .leaf_rst_o(resets_o.rst_por_io_div2_n[DomainAonSel]), + .err_o(cnsty_chk_errs[2][DomainAonSel]), + .fsm_err_o(fsm_errs[2][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_por_io_div2_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonPorIoDiv2FsmCheck_A, + u_daon_por_io_div2.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_por_io_div2_n[Domain0Sel] = '0; + assign cnsty_chk_errs[2][Domain0Sel] = '0; + assign fsm_errs[2][Domain0Sel] = '0; + assign rst_en_o.por_io_div2[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[2] = '0; + assign shadow_fsm_errs[2] = '0; + + // Generating resets for por_io_div4 + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_por_io_div4 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_por_aon_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.por_io_div4[DomainAonSel]), + .leaf_rst_o(resets_o.rst_por_io_div4_n[DomainAonSel]), + .err_o(cnsty_chk_errs[3][DomainAonSel]), + .fsm_err_o(fsm_errs[3][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_por_io_div4_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonPorIoDiv4FsmCheck_A, + u_daon_por_io_div4.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_por_io_div4_n[Domain0Sel] = '0; + assign cnsty_chk_errs[3][Domain0Sel] = '0; + assign fsm_errs[3][Domain0Sel] = '0; + assign rst_en_o.por_io_div4[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[3] = '0; + assign shadow_fsm_errs[3] = '0; + + // Generating resets for por_usb + // Power Domains: ['Aon', '0'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_por_usb ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_usb_i), + .parent_rst_ni(rst_por_aon_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.por_usb[DomainAonSel]), + .leaf_rst_o(resets_o.rst_por_usb_n[DomainAonSel]), + .err_o(cnsty_chk_errs[4][DomainAonSel]), + .fsm_err_o(fsm_errs[4][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_por_usb_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonPorUsbFsmCheck_A, + u_daon_por_usb.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_d0_por_usb ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_usb_i), + .parent_rst_ni(rst_por_aon_n[Domain0Sel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.por_usb[Domain0Sel]), + .leaf_rst_o(resets_o.rst_por_usb_n[Domain0Sel]), + .err_o(cnsty_chk_errs[4][Domain0Sel]), + .fsm_err_o(fsm_errs[4][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_por_usb_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0PorUsbFsmCheck_A, + u_d0_por_usb.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign shadow_cnsty_chk_errs[4] = '0; + assign shadow_fsm_errs[4] = '0; + + // Generating resets for lc + // Power Domains: ['0', 'Aon'] + // Shadowed: True + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_main_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_n[DomainAonSel]), + .err_o(cnsty_chk_errs[5][DomainAonSel]), + .fsm_err_o(fsm_errs[5][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_lc_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonLcFsmCheck_A, + u_daon_lc.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_d0_lc ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_main_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc[Domain0Sel]), + .leaf_rst_o(resets_o.rst_lc_n[Domain0Sel]), + .err_o(cnsty_chk_errs[5][Domain0Sel]), + .fsm_err_o(fsm_errs[5][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_lc_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0LcFsmCheck_A, + u_d0_lc.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc_shadowed ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_main_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_shadowed[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_shadowed_n[DomainAonSel]), + .err_o(shadow_cnsty_chk_errs[5][DomainAonSel]), + .fsm_err_o(shadow_fsm_errs[5][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_lc_shadowed_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonLcShadowedFsmCheck_A, + u_daon_lc_shadowed.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_d0_lc_shadowed ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_main_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_shadowed[Domain0Sel]), + .leaf_rst_o(resets_o.rst_lc_shadowed_n[Domain0Sel]), + .err_o(shadow_cnsty_chk_errs[5][Domain0Sel]), + .fsm_err_o(shadow_fsm_errs[5][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_lc_shadowed_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0LcShadowedFsmCheck_A, + u_d0_lc_shadowed.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + + // Generating resets for lc_aon + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc_aon ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_aon_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_aon[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_aon_n[DomainAonSel]), + .err_o(cnsty_chk_errs[6][DomainAonSel]), + .fsm_err_o(fsm_errs[6][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_lc_aon_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonLcAonFsmCheck_A, + u_daon_lc_aon.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_lc_aon_n[Domain0Sel] = '0; + assign cnsty_chk_errs[6][Domain0Sel] = '0; + assign fsm_errs[6][Domain0Sel] = '0; + assign rst_en_o.lc_aon[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[6] = '0; + assign shadow_fsm_errs[6] = '0; + + // Generating resets for lc_io + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc_io ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_io[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_io_n[DomainAonSel]), + .err_o(cnsty_chk_errs[7][DomainAonSel]), + .fsm_err_o(fsm_errs[7][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_lc_io_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonLcIoFsmCheck_A, + u_daon_lc_io.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_lc_io_n[Domain0Sel] = '0; + assign cnsty_chk_errs[7][Domain0Sel] = '0; + assign fsm_errs[7][Domain0Sel] = '0; + assign rst_en_o.lc_io[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[7] = '0; + assign shadow_fsm_errs[7] = '0; + + // Generating resets for lc_io_div2 + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc_io_div2 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div2_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_io_div2[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_io_div2_n[DomainAonSel]), + .err_o(cnsty_chk_errs[8][DomainAonSel]), + .fsm_err_o(fsm_errs[8][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_lc_io_div2_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonLcIoDiv2FsmCheck_A, + u_daon_lc_io_div2.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_lc_io_div2_n[Domain0Sel] = '0; + assign cnsty_chk_errs[8][Domain0Sel] = '0; + assign fsm_errs[8][Domain0Sel] = '0; + assign rst_en_o.lc_io_div2[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[8] = '0; + assign shadow_fsm_errs[8] = '0; + + // Generating resets for lc_io_div4 + // Power Domains: ['0', 'Aon'] + // Shadowed: True + rstmgr_leaf_rst #( + .SecCheck(0), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc_io_div4 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_io_div4[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_io_div4_n[DomainAonSel]), + .err_o(cnsty_chk_errs[9][DomainAonSel]), + .fsm_err_o(fsm_errs[9][DomainAonSel]) + ); + + rstmgr_leaf_rst #( + .SecCheck(0), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_d0_lc_io_div4 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_io_div4[Domain0Sel]), + .leaf_rst_o(resets_o.rst_lc_io_div4_n[Domain0Sel]), + .err_o(cnsty_chk_errs[9][Domain0Sel]), + .fsm_err_o(fsm_errs[9][Domain0Sel]) + ); + + rstmgr_leaf_rst #( + .SecCheck(0), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc_io_div4_shadowed ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_io_div4_shadowed[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_io_div4_shadowed_n[DomainAonSel]), + .err_o(shadow_cnsty_chk_errs[9][DomainAonSel]), + .fsm_err_o(shadow_fsm_errs[9][DomainAonSel]) + ); + + rstmgr_leaf_rst #( + .SecCheck(0), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_d0_lc_io_div4_shadowed ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_io_div4_shadowed[Domain0Sel]), + .leaf_rst_o(resets_o.rst_lc_io_div4_shadowed_n[Domain0Sel]), + .err_o(shadow_cnsty_chk_errs[9][Domain0Sel]), + .fsm_err_o(shadow_fsm_errs[9][Domain0Sel]) + ); + + + // Generating resets for lc_usb + // Power Domains: ['Aon', '0'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc_usb ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_usb_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_usb[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_usb_n[DomainAonSel]), + .err_o(cnsty_chk_errs[10][DomainAonSel]), + .fsm_err_o(fsm_errs[10][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_lc_usb_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonLcUsbFsmCheck_A, + u_daon_lc_usb.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_d0_lc_usb ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_usb_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_usb[Domain0Sel]), + .leaf_rst_o(resets_o.rst_lc_usb_n[Domain0Sel]), + .err_o(cnsty_chk_errs[10][Domain0Sel]), + .fsm_err_o(fsm_errs[10][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_lc_usb_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0LcUsbFsmCheck_A, + u_d0_lc_usb.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign shadow_cnsty_chk_errs[10] = '0; + assign shadow_fsm_errs[10] = '0; + + // Generating resets for sys + // Power Domains: ['0'] + // Shadowed: False + assign resets_o.rst_sys_n[DomainAonSel] = '0; + assign cnsty_chk_errs[11][DomainAonSel] = '0; + assign fsm_errs[11][DomainAonSel] = '0; + assign rst_en_o.sys[DomainAonSel] = MuBi4True; + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_d0_sys ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_main_i), + .parent_rst_ni(rst_sys_src_n[Domain0Sel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.sys[Domain0Sel]), + .leaf_rst_o(resets_o.rst_sys_n[Domain0Sel]), + .err_o(cnsty_chk_errs[11][Domain0Sel]), + .fsm_err_o(fsm_errs[11][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_sys_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0SysFsmCheck_A, + u_d0_sys.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign shadow_cnsty_chk_errs[11] = '0; + assign shadow_fsm_errs[11] = '0; + + // Generating resets for sys_io_div4 + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_sys_io_div4 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_sys_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.sys_io_div4[DomainAonSel]), + .leaf_rst_o(resets_o.rst_sys_io_div4_n[DomainAonSel]), + .err_o(cnsty_chk_errs[12][DomainAonSel]), + .fsm_err_o(fsm_errs[12][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_sys_io_div4_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonSysIoDiv4FsmCheck_A, + u_daon_sys_io_div4.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_sys_io_div4_n[Domain0Sel] = '0; + assign cnsty_chk_errs[12][Domain0Sel] = '0; + assign fsm_errs[12][Domain0Sel] = '0; + assign rst_en_o.sys_io_div4[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[12] = '0; + assign shadow_fsm_errs[12] = '0; + + // Generating resets for spi_device + // Power Domains: ['0'] + // Shadowed: False + assign resets_o.rst_spi_device_n[DomainAonSel] = '0; + assign cnsty_chk_errs[13][DomainAonSel] = '0; + assign fsm_errs[13][DomainAonSel] = '0; + assign rst_en_o.spi_device[DomainAonSel] = MuBi4True; + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b1) + ) u_d0_spi_device ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[SPI_DEVICE].q), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.spi_device[Domain0Sel]), + .leaf_rst_o(resets_o.rst_spi_device_n[Domain0Sel]), + .err_o(cnsty_chk_errs[13][Domain0Sel]), + .fsm_err_o(fsm_errs[13][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_spi_device_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0SpiDeviceFsmCheck_A, + u_d0_spi_device.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign shadow_cnsty_chk_errs[13] = '0; + assign shadow_fsm_errs[13] = '0; + + // Generating resets for spi_host0 + // Power Domains: ['0'] + // Shadowed: False + assign resets_o.rst_spi_host0_n[DomainAonSel] = '0; + assign cnsty_chk_errs[14][DomainAonSel] = '0; + assign fsm_errs[14][DomainAonSel] = '0; + assign rst_en_o.spi_host0[DomainAonSel] = MuBi4True; + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b1) + ) u_d0_spi_host0 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[SPI_HOST0].q), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.spi_host0[Domain0Sel]), + .leaf_rst_o(resets_o.rst_spi_host0_n[Domain0Sel]), + .err_o(cnsty_chk_errs[14][Domain0Sel]), + .fsm_err_o(fsm_errs[14][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_spi_host0_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0SpiHost0FsmCheck_A, + u_d0_spi_host0.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign shadow_cnsty_chk_errs[14] = '0; + assign shadow_fsm_errs[14] = '0; + + // Generating resets for i2c0 + // Power Domains: ['0'] + // Shadowed: False + assign resets_o.rst_i2c0_n[DomainAonSel] = '0; + assign cnsty_chk_errs[15][DomainAonSel] = '0; + assign fsm_errs[15][DomainAonSel] = '0; + assign rst_en_o.i2c0[DomainAonSel] = MuBi4True; + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b1) + ) u_d0_i2c0 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[I2C0].q), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.i2c0[Domain0Sel]), + .leaf_rst_o(resets_o.rst_i2c0_n[Domain0Sel]), + .err_o(cnsty_chk_errs[15][Domain0Sel]), + .fsm_err_o(fsm_errs[15][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_i2c0_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0I2c0FsmCheck_A, + u_d0_i2c0.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign shadow_cnsty_chk_errs[15] = '0; + assign shadow_fsm_errs[15] = '0; + + + //////////////////////////////////////////////////// + // Reset info construction // + //////////////////////////////////////////////////// + + logic rst_hw_req; + logic rst_low_power; + logic pwrmgr_rst_req; + + // there is a valid reset request from pwrmgr + assign pwrmgr_rst_req = |pwr_i.rst_lc_req || |pwr_i.rst_sys_req; + + // a reset reason is only valid if the related processing element is also reset. + // In the future, if ever there are multiple processing elements, this code here + // must be updated to account for each individual core. + assign rst_hw_req = pwrmgr_rst_req & + (pwr_i.reset_cause == pwrmgr_pkg::HwReq); + assign rst_low_power = pwrmgr_rst_req & + (pwr_i.reset_cause == pwrmgr_pkg::LowPwrEntry); + + // software initiated reset request + assign sw_rst_req_o = prim_mubi_pkg::mubi4_t'(reg2hw.reset_req.q); + + // when pwrmgr reset request is received (reset is imminent), clear software + // request so we are not in an infinite reset loop. + assign hw2reg.reset_req.de = pwrmgr_rst_req; + assign hw2reg.reset_req.d = prim_mubi_pkg::MuBi4False; + + // Only sw is allowed to clear a reset reason, hw is only allowed to set it. + assign hw2reg.reset_info.low_power_exit.d = 1'b1; + assign hw2reg.reset_info.low_power_exit.de = rst_low_power; + + // software issued request triggers the same response as hardware, although it is + // accounted for differently. + assign hw2reg.reset_info.sw_reset.d = prim_mubi_pkg::mubi4_test_true_strict(sw_rst_req_o) | + reg2hw.reset_info.sw_reset.q; + assign hw2reg.reset_info.sw_reset.de = rst_hw_req; + + // HW reset requests most likely will be multi-bit, so OR in whatever reasons + // that are already set. + assign hw2reg.reset_info.hw_req.d = pwr_i.rstreqs | + reg2hw.reset_info.hw_req.q; + assign hw2reg.reset_info.hw_req.de = rst_hw_req; + + //////////////////////////////////////////////////// + // Crash info capture // + //////////////////////////////////////////////////// + + logic dump_capture; + assign dump_capture = rst_hw_req | rst_low_power; + + // halt dump capture once we hit particular conditions + logic dump_capture_halt; + assign dump_capture_halt = rst_hw_req; + + rstmgr_crash_info #( + .CrashDumpWidth($bits(alert_pkg::alert_crashdump_t)) + ) u_alert_info ( + .clk_i(clk_por_i), + .rst_ni(rst_por_ni), + .dump_i(alert_dump_i), + .dump_capture_i(dump_capture & reg2hw.alert_info_ctrl.en.q), + .slot_sel_i(reg2hw.alert_info_ctrl.index.q), + .slots_cnt_o(hw2reg.alert_info_attr.d), + .slot_o(hw2reg.alert_info.d) + ); + + rstmgr_crash_info #( + .CrashDumpWidth($bits(rv_core_ibex_pkg::cpu_crash_dump_t)) + ) u_cpu_info ( + .clk_i(clk_por_i), + .rst_ni(rst_por_ni), + .dump_i(cpu_dump_i), + .dump_capture_i(dump_capture & reg2hw.cpu_info_ctrl.en.q), + .slot_sel_i(reg2hw.cpu_info_ctrl.index.q), + .slots_cnt_o(hw2reg.cpu_info_attr.d), + .slot_o(hw2reg.cpu_info.d) + ); + + // once dump is captured, no more information is captured until + // re-enabled by software. + assign hw2reg.alert_info_ctrl.en.d = 1'b0; + assign hw2reg.alert_info_ctrl.en.de = dump_capture_halt; + assign hw2reg.cpu_info_ctrl.en.d = 1'b0; + assign hw2reg.cpu_info_ctrl.en.de = dump_capture_halt; + + //////////////////////////////////////////////////// + // Exported resets // + //////////////////////////////////////////////////// + + + + + //////////////////////////////////////////////////// + // Assertions // + //////////////////////////////////////////////////// + + `ASSERT_INIT(ParameterMatch_A, NumHwResets == pwrmgr_pkg::HwResetWidth) + + // when upstream resets, downstream must also reset + + // output known asserts + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid ) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready ) + `ASSERT_KNOWN(AlertsKnownO_A, alert_tx_o ) + `ASSERT_KNOWN(PwrKnownO_A, pwr_o ) + `ASSERT_KNOWN(ResetsKnownO_A, resets_o ) + `ASSERT_KNOWN(RstEnKnownO_A, rst_en_o ) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0]) +endmodule // rstmgr diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_cnsty_chk.sv b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_cnsty_chk.sv new file mode 100644 index 0000000000000..d70ab3be41c0b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_cnsty_chk.sv @@ -0,0 +1,273 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module implements reset consistency checks +// The main goal is to check whether conditions allow for a reset to be asserted +// For example, if a child reset asserts, it must be the case that its parent +// reset or software controls (if available) have asserted. +// If a child reset asserts and neither of the above case is true, it is considered +// a fatal error. + +`include "prim_assert.sv" + +module rstmgr_cnsty_chk + import rstmgr_pkg::*; + import rstmgr_reg_pkg::*; +#( + parameter int SecMaxSyncDelay = 2, + parameter bit SwRstReq = 1 +) ( + input clk_i, + input rst_ni, + input child_clk_i, + input child_rst_ni, + input child_chk_rst_ni, // rst_ni synchronized to child_clk_i domain. + input parent_rst_ni, + input sw_rst_req_i, + output logic sw_rst_req_clr_o, + output logic err_o, + output logic fsm_err_o +); + + // The "+ 2" here is because the cnt counter that uses this width needs to be able to count up to + // SecMaxSyncDelay + 1. + localparam int CntWidth = $clog2(SecMaxSyncDelay + 2); + + // These two flops below are completely async. + // The value from these flops are always fed through synchronizers before use. + logic parent_rst_asserted; + always_ff @(posedge clk_i or negedge parent_rst_ni) begin + if (!parent_rst_ni) begin + parent_rst_asserted <= 1'b1; + end else begin + parent_rst_asserted <= '0; + end + end + + logic child_rst_asserted; + always_ff @(posedge clk_i or negedge child_rst_ni) begin + if (!child_rst_ni) begin + child_rst_asserted <= 1'b1; + end else begin + child_rst_asserted <= '0; + end + end + + logic sync_parent_rst; + prim_flop_2sync #( + .Width(1), + .ResetValue(1) + ) u_parent_sync ( + .clk_i, + .rst_ni, + .d_i(parent_rst_asserted), + .q_o(sync_parent_rst) + ); + + logic sync_child_rst; + prim_flop_2sync #( + .Width(1), + .ResetValue(1) + ) u_child_sync ( + .clk_i, + .rst_ni, + .d_i(child_rst_asserted), + .q_o(sync_child_rst) + ); + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 7 -n 6 \ + // -s 90402488 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||||||||| (57.14%) + // 4: ||||||||||||||| (42.86%) + // 5: -- + // 6: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 4 + // Minimum Hamming weight: 1 + // Maximum Hamming weight: 5 + // + localparam int StateWidth = 6; + typedef enum logic [StateWidth-1:0] { + Reset = 6'b010001, + Idle = 6'b100011, + WaitForParent = 6'b111101, + WaitForChild = 6'b001111, + WaitForSrcRelease = 6'b100100, + WaitForChildRelease = 6'b111010, + Error = 6'b010110, + FsmError = 6'b001000 + } state_e; + + state_e state_q, state_d; + + // SEC_CM: LEAF.FSM.SPARSE + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Reset, clk_i, rst_ni) + + logic timeout; + logic cnt_inc; + logic cnt_clr; + logic [CntWidth-1:0] cnt; + + // the timeout count is on clk_i because the synchronizers are + // also operating on clk_i. We are mainly trying to wait out the reset assertion delays. + // parent resets are asynchronous assertion so there is at most a one cycle separation. + // if needed we can make this timeout bigger. + assign timeout = int'(cnt) > SecMaxSyncDelay; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + cnt <= '0; + end else if (cnt_clr) begin + cnt <= '0; + end else if (cnt_inc && !timeout) begin + cnt <= cnt + 1'b1; + end + end + + logic src_valid; + // The following code makes it easier for tools such as UNR, + // it is not functionally required. + if (SwRstReq) begin : gen_sw_rst_req + assign src_valid = sync_parent_rst || sw_rst_req_i; + end else begin : gen_no_sw_rst_req + assign src_valid = sync_parent_rst; + + logic unused_sw_rst_req; + assign unused_sw_rst_req = sw_rst_req_i; + end + + logic sync_child_ack; + + always_comb begin + state_d = state_q; + err_o = '0; + fsm_err_o = '0; + cnt_inc = '0; + cnt_clr = '0; + sw_rst_req_clr_o = '0; + + unique case (state_q) + Reset: begin + // when the checker itself comes out of reset, conditions + // may be ambiguous, wait for things to stabilize + if (!sync_child_rst && !sync_parent_rst) begin + state_d = Idle; + end + end + + Idle: begin + // If a child reset asserts, one of the conditions must be true. + // It is possible for the child to assert but parent to remain de-asserted + // due to CDC latency (or vice versa), wait for the other corresponding reset + // when this occurs. + if (sync_child_rst && src_valid) begin + state_d = WaitForSrcRelease; + end else if (sync_child_rst && !sync_parent_rst) begin + state_d = WaitForParent; + end else if (sync_parent_rst && !sync_child_rst) begin + state_d = WaitForChild; + end + end + + // parent reset must show up within timeout region + WaitForParent: begin + cnt_inc = 1'b1; + + if (timeout && !sync_parent_rst) begin + state_d = Error; + end else if (sync_parent_rst) begin + state_d = WaitForSrcRelease; + cnt_clr = 1'b1; + end + end + + // child reset must show up within timeout region + WaitForChild: begin + cnt_inc = 1'b1; + + if (timeout && !sync_child_rst) begin + state_d = Error; + end else if (sync_child_rst) begin + state_d = WaitForSrcRelease; + cnt_clr = 1'b1; + end + end + + // waiting for parent reset to release + WaitForSrcRelease: begin + // if arrived here due to software requested reset, it is now + // okay to clear the original request. + sw_rst_req_clr_o = 1'b1; + + // it is not possible for the child reset to release + // ahead of the parent reset + if (!sync_child_rst && src_valid) begin + state_d = Error; + end else if (!src_valid) begin + cnt_clr = 1'b1; + state_d = WaitForChildRelease; + end + end + + // waiting for child reset to release + WaitForChildRelease: begin + // operate only on child ack to keep things in sync + // This is needed because the reset releases are synchronous to the child clock. + // So if we have a situation where the child clock is way slower than the local + // clock used to increment the count, we may timeout incorrectly. + // By using sync_child_ack, we ensure that the count is advanced only when a + // child clock edge is seen. This usage is conservative, because by the time + // sync_child_ack is seen, there may have been more than one child clock, yet the + // count is only incremented by 1. + cnt_inc = sync_child_ack; + if (sync_child_rst && src_valid) begin + // This condition covers the case if for whatever reason the parent reset re-asserts + // in a valid way. + state_d = WaitForSrcRelease; + cnt_clr = 1'b1; + end else if (sync_child_rst && timeout) begin + state_d = Error; + end else if (!sync_child_rst) begin + state_d = Idle; + cnt_clr = 1'b1; + end + end + + Error: begin + err_o = 1'b1; + end + + FsmError: begin + fsm_err_o = 1'b1; + end + + default: begin + state_d = FsmError; + fsm_err_o = 1'b1; + end + endcase // unique case (state_q) + end // always_comb + + logic child_ack; + prim_sync_reqack u_child_handshake ( + .clk_src_i(clk_i), + .rst_src_ni(rst_ni), + .clk_dst_i(child_clk_i), + .rst_dst_ni(child_chk_rst_ni), + .req_chk_i('0), + .src_req_i(1'b1), + .src_ack_o(sync_child_ack), + .dst_req_o(child_ack), + .dst_ack_i(child_ack) + ); + +endmodule // rstmgr_cnsty_chk diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_crash_info.sv b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_crash_info.sv new file mode 100644 index 0000000000000..e252c43fd6d63 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_crash_info.sv @@ -0,0 +1,60 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// This module implements the crash dump functionality + +`include "prim_assert.sv" + +module rstmgr_crash_info + import rstmgr_pkg::*; + import rstmgr_reg_pkg::IdxWidth; + import rstmgr_reg_pkg::RdWidth; +#( + parameter int CrashDumpWidth = 32, + localparam int CrashRemainder = CrashDumpWidth % RdWidth > 0 ? 1 : 0, + localparam int unsigned CrashStoreSlot = CrashDumpWidth / RdWidth + CrashRemainder, + localparam int SlotCntWidth = $clog2(CrashStoreSlot) +) ( + input clk_i, + input rst_ni, + input [CrashDumpWidth-1:0] dump_i, + input dump_capture_i, + input [IdxWidth-1:0] slot_sel_i, + output logic [IdxWidth-1:0] slots_cnt_o, + output logic [RdWidth-1:0] slot_o +); + + localparam int TotalWidth = CrashStoreSlot * RdWidth; + logic [2**SlotCntWidth-1:0][RdWidth-1:0] slots; + logic [ CrashStoreSlot-1:0][RdWidth-1:0] slots_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + slots_q <= '0; + end else if (dump_capture_i) begin + slots_q <= TotalWidth'(dump_i); + end + end + + always_comb begin + slots = '0; + slots[CrashStoreSlot-1:0] = slots_q; + end + + assign slots_cnt_o = CrashStoreSlot[IdxWidth-1:0]; + assign slot_o = slots[slot_sel_i[SlotCntWidth-1:0]]; + + if (SlotCntWidth < IdxWidth) begin : gen_tieoffs + //VCS coverage off + // pragma coverage off + logic [IdxWidth-SlotCntWidth-1:0] unused_idx; + assign unused_idx = slot_sel_i[IdxWidth-1:SlotCntWidth]; + //VCS coverage on + // pragma coverage on + end + + // Make sure the crash dump isn't excessively large + `ASSERT_INIT(CntStoreSlot_A, CrashStoreSlot < (1 << IdxWidth)) + `ASSERT_INIT(CntWidth_A, SlotCntWidth <= IdxWidth) + +endmodule // rstmgr_crash_info diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_ctrl.sv b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_ctrl.sv new file mode 100644 index 0000000000000..a762ec8281b9e --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_ctrl.sv @@ -0,0 +1,77 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module implements generic reset controls +// + +`include "prim_assert.sv" + +module rstmgr_ctrl + import rstmgr_pkg::*; + import rstmgr_reg_pkg::*; +( + input clk_i, + input [PowerDomains-1:0] rst_req_i, + input [PowerDomains-1:0] rst_parent_ni, // parent reset + output logic [PowerDomains-1:0] rst_no, + input scanmode_i, + input scan_rst_ni +); + + // the always on root reset + logic rst_aon_n_premux, rst_aon_n; + + // the remaining resets + logic [OffDomains-1:0] rst_pd_nd, rst_pd_nq; + + // always on handling + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_aon_rst ( + .clk_i, + .rst_ni(rst_parent_ni[DomainAonSel]), + .d_i(~rst_req_i[DomainAonSel]), + .q_o(rst_aon_n_premux) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_aon_mux ( + .clk0_i(rst_aon_n_premux), + .clk1_i(scan_rst_ni), + .sel_i(scanmode_i), + .clk_o(rst_aon_n) + ); + assign rst_no[DomainAonSel] = rst_aon_n; + + // the non-always-on domains + // These reset whenever the always on domain reset, to ensure power definition consistency. + // By extension, they also reset whenever the root (rst_ni) resets + assign rst_pd_nd = ~rst_req_i[Domain0Sel +: OffDomains]; + + localparam int DomainPdStartIdx = DomainAonSel + 1; + for(genvar i = 0; i < OffDomains; i++) begin : gen_rst_pd_n + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_pd_rst ( + .clk_i, + // when the always on portion resets, always reset the non-always-on portion as well. + .rst_ni(rst_aon_n & rst_parent_ni[DomainPdStartIdx + i]), + .d_i(rst_pd_nd[i]), + .q_o(rst_pd_nq[i]) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_pd_mux ( + .clk0_i(rst_pd_nq[i]), + .clk1_i(scan_rst_ni), + .sel_i(scanmode_i), + .clk_o(rst_no[DomainPdStartIdx + i]) + ); + end + +endmodule // rstmgr_ctrl diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_leaf_rst.sv b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_leaf_rst.sv new file mode 100644 index 0000000000000..ca1ab02a1c7e3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_leaf_rst.sv @@ -0,0 +1,134 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module generates the leaf resets and instantiates the associated reset +// checks. + +`include "prim_assert.sv" + +module rstmgr_leaf_rst + import rstmgr_pkg::*; + import rstmgr_reg_pkg::*; + import prim_mubi_pkg::mubi4_t; #( + parameter bit SecCheck = 1, + parameter int SecMaxSyncDelay = 2, + parameter bit SwRstReq = 1 +) ( + input clk_i, + input rst_ni, + input leaf_clk_i, + input parent_rst_ni, + input sw_rst_req_ni, + input prim_mubi_pkg::mubi4_t scanmode_i, + input scan_rst_ni, + output mubi4_t rst_en_o, + output logic leaf_rst_o, + output logic err_o, + output logic fsm_err_o +); + + prim_mubi_pkg::mubi4_t scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o({scanmode}) + ); + + logic leaf_rst_sync; + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_rst_sync ( + .clk_i(leaf_clk_i), + .rst_ni(parent_rst_ni), + .d_i(sw_rst_req_ni), + .q_o(leaf_rst_sync) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_mux ( + .clk0_i(leaf_rst_sync), + .clk1_i(scan_rst_ni), + .sel_i(prim_mubi_pkg::mubi4_test_true_strict(scanmode)), + .clk_o(leaf_rst_o) + ); + + logic sw_rst_req_q; + logic clr_sw_rst_req; + if (SwRstReq && SecCheck) begin : gen_sw_rst_req + // once software requests a reset, hold on to the request until the consistency + // checker passes the assertion check point + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + sw_rst_req_q <= '0; + end else if (sw_rst_req_q && clr_sw_rst_req) begin + sw_rst_req_q <= '0; + end else if (!sw_rst_req_q && !sw_rst_req_ni && !clr_sw_rst_req) begin + sw_rst_req_q <= 1'b1; + end + end + end else begin : gen_no_sw_rst_req + //VCS coverage off + // pragma coverage off + logic unused_sig; + assign unused_sig = clr_sw_rst_req; + //VCS coverage on + // pragma coverage on + assign sw_rst_req_q = '0; + end + + if (SecCheck) begin : gen_rst_chk + + // We have to create a separately synced reset for the child handshakes below, since keeping the + // child side of the prim_sync_reqack synchronizer under reset would defeat the reset checker's + // purpose, as it would never count any clock ticks in the WaitForChildRelease state above. + logic leaf_chk_rst_n; + prim_rst_sync u_prim_rst_sync ( + .clk_i (leaf_clk_i), + .d_i (rst_ni), + .q_o (leaf_chk_rst_n), + .scan_rst_ni, + .scanmode_i + ); + + // SEC_CM: LEAF.RST.BKGN_CHK + rstmgr_cnsty_chk #( + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(SwRstReq) + ) u_rst_chk ( + .clk_i, + .rst_ni, + .child_clk_i(leaf_clk_i), + .child_rst_ni(leaf_rst_o), + .child_chk_rst_ni(leaf_chk_rst_n), + .parent_rst_ni, + .sw_rst_req_i(sw_rst_req_q | ~sw_rst_req_ni), + .sw_rst_req_clr_o(clr_sw_rst_req), + .err_o, + .fsm_err_o + ); + end else begin : gen_no_rst_chk + logic unused_sig; + assign unused_sig = sw_rst_req_q; + assign clr_sw_rst_req = '0; + assign err_o = '0; + assign fsm_err_o = '0; + end + + // reset asserted indication for alert handler + prim_mubi4_sender #( + .ResetValue(prim_mubi_pkg::MuBi4True) + ) u_prim_mubi4_sender ( + .clk_i(leaf_clk_i), + .rst_ni(leaf_rst_o), + .mubi_i(prim_mubi_pkg::MuBi4False), + .mubi_o(rst_en_o) + ); + +endmodule // rstmgr_leaf_rst diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_pkg.sv b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_pkg.sv new file mode 100644 index 0000000000000..0a2f80411cab8 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_pkg.sv @@ -0,0 +1,103 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +package rstmgr_pkg; + + // Power domain parameters + parameter int PowerDomains = 2; + parameter int DomainAonSel = 0; + parameter int Domain0Sel = 1; + + // Number of non-always-on domains + parameter int OffDomains = PowerDomains-1; + + // positions of software controllable reset bits + parameter int SPI_DEVICE = 0; + parameter int SPI_HOST0 = 1; + parameter int I2C0 = 2; + + // resets generated and broadcast + // SEC_CM: LEAF.RST.SHADOW + typedef struct packed { + logic [PowerDomains-1:0] rst_por_aon_n; + logic [PowerDomains-1:0] rst_por_n; + logic [PowerDomains-1:0] rst_por_io_n; + logic [PowerDomains-1:0] rst_por_io_div2_n; + logic [PowerDomains-1:0] rst_por_io_div4_n; + logic [PowerDomains-1:0] rst_por_usb_n; + logic [PowerDomains-1:0] rst_lc_shadowed_n; + logic [PowerDomains-1:0] rst_lc_n; + logic [PowerDomains-1:0] rst_lc_aon_n; + logic [PowerDomains-1:0] rst_lc_io_n; + logic [PowerDomains-1:0] rst_lc_io_div2_n; + logic [PowerDomains-1:0] rst_lc_io_div4_shadowed_n; + logic [PowerDomains-1:0] rst_lc_io_div4_n; + logic [PowerDomains-1:0] rst_lc_usb_n; + logic [PowerDomains-1:0] rst_sys_n; + logic [PowerDomains-1:0] rst_sys_io_div4_n; + logic [PowerDomains-1:0] rst_spi_device_n; + logic [PowerDomains-1:0] rst_spi_host0_n; + logic [PowerDomains-1:0] rst_i2c0_n; + } rstmgr_out_t; + + // reset indication for alert handler + typedef struct packed { + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_aon; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_io; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_io_div2; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_io_div4; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_usb; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_shadowed; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_aon; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_io; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_io_div2; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_io_div4_shadowed; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_io_div4; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_usb; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] sys; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] sys_io_div4; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] spi_device; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] spi_host0; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] i2c0; + } rstmgr_rst_en_t; + + parameter int NumOutputRst = 19 * PowerDomains; + + // cpu reset requests and status + typedef struct packed { + logic ndmreset_req; + } rstmgr_cpu_t; + + // exported resets + + // default value for rstmgr_ast_rsp_t (for dangling ports) + parameter rstmgr_cpu_t RSTMGR_CPU_DEFAULT = '{ + ndmreset_req: '0 + }; + + // Enumeration for pwrmgr hw reset inputs + localparam int ResetWidths = $clog2(rstmgr_reg_pkg::NumTotalResets); + typedef enum logic [ResetWidths-1:0] { + ReqPeriResetIdx[0:1], + ReqMainPwrResetIdx, + ReqEscResetIdx, + ReqNdmResetIdx + } reset_req_idx_e; + + // Enumeration for reset info bit idx + typedef enum logic [ResetWidths-1:0] { + InfoPorIdx, + InfoLowPowerExitIdx, + InfoSwResetIdx, + InfoPeriResetIdx[0:1], + InfoMainPwrResetIdx, + InfoEscResetIdx, + InfoNdmResetIdx + } reset_info_idx_e; + + +endpackage // rstmgr_pkg diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_por.sv b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_por.sv new file mode 100644 index 0000000000000..0ac7e14becb72 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_por.sv @@ -0,0 +1,106 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module stretches the POR +// + +module rstmgr_por #( + parameter int FilterStages = 3, + parameter int unsigned StretchCount = 32 +) ( + input clk_i, + input rst_ni, + input scan_rst_ni, + input scanmode_i, + output logic rst_no +); + localparam int CtrWidth = $clog2(StretchCount+1); + + logic rst_root_n_pre_mux, rst_root_n; + logic [FilterStages-1:0] rst_filter_n; + logic rst_stable; + logic rst_clean_n; + logic [CtrWidth-1:0] cnt; + logic cnt_en; + + // sync the POR + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_rst_sync ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(1'b1), + .q_o(rst_root_n_pre_mux) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_root_mux ( + .clk0_i(rst_root_n_pre_mux), + .clk1_i(scan_rst_ni), + .sel_i(scanmode_i), + .clk_o(rst_root_n) + ); + + // filter the POR + always_ff @(posedge clk_i or negedge rst_root_n) begin + if (!rst_root_n) begin + rst_filter_n <= '0; + end else begin + rst_filter_n <= {rst_filter_n[0 +: FilterStages-1], 1'b1}; + end + end + + // The stable is a vote of all filter stages. + // Only when all the stages agree is the reset considered stable and count allowed. + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_clean_mux ( + .clk0_i(rst_filter_n[FilterStages-1]), + .clk1_i(scan_rst_ni), + .sel_i(scanmode_i), + .clk_o(rst_clean_n) + ); + + assign rst_stable = &rst_filter_n; + assign cnt_en = rst_stable & !rst_no; + + // stretch the POR + logic rst_nd, rst_nq; + + assign rst_nd = ~rst_stable ? 1'b0 : + cnt_en & (cnt == StretchCount[CtrWidth-1:0]) ? 1'b1 : rst_nq; + + always_ff @(posedge clk_i or negedge rst_clean_n) begin + if (!rst_clean_n) begin + cnt <= '0; + end else if (!rst_stable) begin + cnt <= '0; + end else if (cnt_en) begin + cnt <= cnt + 1'b1; + end + end + + prim_flop #( + .Width(1), + .ResetValue('0) + ) u_rst_flop ( + .clk_i, + .rst_ni(rst_clean_n), + .d_i(rst_nd), + .q_o(rst_nq) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_out_mux ( + .clk0_i(rst_nq), + .clk1_i(scan_rst_ni), + .sel_i(scanmode_i), + .clk_o(rst_no) + ); + +endmodule // rstmgr_por diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv new file mode 100644 index 0000000000000..a171a21c1cd70 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv @@ -0,0 +1,248 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package rstmgr_reg_pkg; + + // Param list + parameter int RdWidth = 32; + parameter int IdxWidth = 4; + parameter int NumHwResets = 5; + parameter int NumSwResets = 3; + parameter int NumTotalResets = 8; + parameter int NumAlerts = 2; + + // Address widths within the block + parameter int BlockAw = 7; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic q; + logic qe; + } fatal_cnsty_fault; + struct packed { + logic q; + logic qe; + } fatal_fault; + } rstmgr_reg2hw_alert_test_reg_t; + + typedef struct packed { + logic [3:0] q; + } rstmgr_reg2hw_reset_req_reg_t; + + typedef struct packed { + struct packed { + logic [4:0] q; + } hw_req; + struct packed { + logic q; + } sw_reset; + } rstmgr_reg2hw_reset_info_reg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + } index; + struct packed { + logic q; + } en; + } rstmgr_reg2hw_alert_info_ctrl_reg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + } index; + struct packed { + logic q; + } en; + } rstmgr_reg2hw_cpu_info_ctrl_reg_t; + + typedef struct packed { + logic q; + } rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t; + + typedef struct packed { + struct packed { + logic q; + } fsm_err; + struct packed { + logic q; + } reset_consistency_err; + struct packed { + logic q; + } reg_intg_err; + } rstmgr_reg2hw_err_code_reg_t; + + typedef struct packed { + logic [3:0] d; + logic de; + } rstmgr_hw2reg_reset_req_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } low_power_exit; + struct packed { + logic d; + logic de; + } sw_reset; + struct packed { + logic [4:0] d; + logic de; + } hw_req; + } rstmgr_hw2reg_reset_info_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } en; + } rstmgr_hw2reg_alert_info_ctrl_reg_t; + + typedef struct packed { + logic [3:0] d; + } rstmgr_hw2reg_alert_info_attr_reg_t; + + typedef struct packed { + logic [31:0] d; + } rstmgr_hw2reg_alert_info_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } en; + } rstmgr_hw2reg_cpu_info_ctrl_reg_t; + + typedef struct packed { + logic [3:0] d; + } rstmgr_hw2reg_cpu_info_attr_reg_t; + + typedef struct packed { + logic [31:0] d; + } rstmgr_hw2reg_cpu_info_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } reg_intg_err; + struct packed { + logic d; + logic de; + } reset_consistency_err; + struct packed { + logic d; + logic de; + } fsm_err; + } rstmgr_hw2reg_err_code_reg_t; + + // Register -> HW type + typedef struct packed { + rstmgr_reg2hw_alert_test_reg_t alert_test; // [29:26] + rstmgr_reg2hw_reset_req_reg_t reset_req; // [25:22] + rstmgr_reg2hw_reset_info_reg_t reset_info; // [21:16] + rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [15:11] + rstmgr_reg2hw_cpu_info_ctrl_reg_t cpu_info_ctrl; // [10:6] + rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t [2:0] sw_rst_ctrl_n; // [5:3] + rstmgr_reg2hw_err_code_reg_t err_code; // [2:0] + } rstmgr_reg2hw_t; + + // HW -> register type + typedef struct packed { + rstmgr_hw2reg_reset_req_reg_t reset_req; // [96:92] + rstmgr_hw2reg_reset_info_reg_t reset_info; // [91:82] + rstmgr_hw2reg_alert_info_ctrl_reg_t alert_info_ctrl; // [81:80] + rstmgr_hw2reg_alert_info_attr_reg_t alert_info_attr; // [79:76] + rstmgr_hw2reg_alert_info_reg_t alert_info; // [75:44] + rstmgr_hw2reg_cpu_info_ctrl_reg_t cpu_info_ctrl; // [43:42] + rstmgr_hw2reg_cpu_info_attr_reg_t cpu_info_attr; // [41:38] + rstmgr_hw2reg_cpu_info_reg_t cpu_info; // [37:6] + rstmgr_hw2reg_err_code_reg_t err_code; // [5:0] + } rstmgr_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] RSTMGR_ALERT_TEST_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] RSTMGR_RESET_REQ_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] RSTMGR_RESET_INFO_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] RSTMGR_ALERT_REGWEN_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_CTRL_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_ATTR_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] RSTMGR_CPU_REGWEN_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_CTRL_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_ATTR_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_0_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_1_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_2_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_0_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_1_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_2_OFFSET = 7'h 40; + parameter logic [BlockAw-1:0] RSTMGR_ERR_CODE_OFFSET = 7'h 44; + + // Reset values for hwext registers and their fields + parameter logic [1:0] RSTMGR_ALERT_TEST_RESVAL = 2'h 0; + parameter logic [0:0] RSTMGR_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [0:0] RSTMGR_ALERT_TEST_FATAL_CNSTY_FAULT_RESVAL = 1'h 0; + parameter logic [3:0] RSTMGR_ALERT_INFO_ATTR_RESVAL = 4'h 0; + parameter logic [3:0] RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_RESVAL = 4'h 0; + parameter logic [31:0] RSTMGR_ALERT_INFO_RESVAL = 32'h 0; + parameter logic [31:0] RSTMGR_ALERT_INFO_VALUE_RESVAL = 32'h 0; + parameter logic [3:0] RSTMGR_CPU_INFO_ATTR_RESVAL = 4'h 0; + parameter logic [3:0] RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_RESVAL = 4'h 0; + parameter logic [31:0] RSTMGR_CPU_INFO_RESVAL = 32'h 0; + parameter logic [31:0] RSTMGR_CPU_INFO_VALUE_RESVAL = 32'h 0; + + // Register index + typedef enum int { + RSTMGR_ALERT_TEST, + RSTMGR_RESET_REQ, + RSTMGR_RESET_INFO, + RSTMGR_ALERT_REGWEN, + RSTMGR_ALERT_INFO_CTRL, + RSTMGR_ALERT_INFO_ATTR, + RSTMGR_ALERT_INFO, + RSTMGR_CPU_REGWEN, + RSTMGR_CPU_INFO_CTRL, + RSTMGR_CPU_INFO_ATTR, + RSTMGR_CPU_INFO, + RSTMGR_SW_RST_REGWEN_0, + RSTMGR_SW_RST_REGWEN_1, + RSTMGR_SW_RST_REGWEN_2, + RSTMGR_SW_RST_CTRL_N_0, + RSTMGR_SW_RST_CTRL_N_1, + RSTMGR_SW_RST_CTRL_N_2, + RSTMGR_ERR_CODE + } rstmgr_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] RSTMGR_PERMIT [18] = '{ + 4'b 0001, // index[ 0] RSTMGR_ALERT_TEST + 4'b 0001, // index[ 1] RSTMGR_RESET_REQ + 4'b 0001, // index[ 2] RSTMGR_RESET_INFO + 4'b 0001, // index[ 3] RSTMGR_ALERT_REGWEN + 4'b 0001, // index[ 4] RSTMGR_ALERT_INFO_CTRL + 4'b 0001, // index[ 5] RSTMGR_ALERT_INFO_ATTR + 4'b 1111, // index[ 6] RSTMGR_ALERT_INFO + 4'b 0001, // index[ 7] RSTMGR_CPU_REGWEN + 4'b 0001, // index[ 8] RSTMGR_CPU_INFO_CTRL + 4'b 0001, // index[ 9] RSTMGR_CPU_INFO_ATTR + 4'b 1111, // index[10] RSTMGR_CPU_INFO + 4'b 0001, // index[11] RSTMGR_SW_RST_REGWEN_0 + 4'b 0001, // index[12] RSTMGR_SW_RST_REGWEN_1 + 4'b 0001, // index[13] RSTMGR_SW_RST_REGWEN_2 + 4'b 0001, // index[14] RSTMGR_SW_RST_CTRL_N_0 + 4'b 0001, // index[15] RSTMGR_SW_RST_CTRL_N_1 + 4'b 0001, // index[16] RSTMGR_SW_RST_CTRL_N_2 + 4'b 0001 // index[17] RSTMGR_ERR_CODE + }; + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv new file mode 100644 index 0000000000000..6c6eedb634cec --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv @@ -0,0 +1,1124 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module rstmgr_reg_top ( + input clk_i, + input rst_ni, + input clk_por_i, + input rst_por_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output rstmgr_reg_pkg::rstmgr_reg2hw_t reg2hw, // Write + input rstmgr_reg_pkg::rstmgr_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import rstmgr_reg_pkg::* ; + + localparam int AW = 7; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [17:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(18) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic alert_test_we; + logic alert_test_fatal_fault_wd; + logic alert_test_fatal_cnsty_fault_wd; + logic reset_req_we; + logic [3:0] reset_req_qs; + logic [3:0] reset_req_wd; + logic reset_info_we; + logic reset_info_por_qs; + logic reset_info_por_wd; + logic reset_info_low_power_exit_qs; + logic reset_info_low_power_exit_wd; + logic reset_info_sw_reset_qs; + logic reset_info_sw_reset_wd; + logic [4:0] reset_info_hw_req_qs; + logic [4:0] reset_info_hw_req_wd; + logic alert_regwen_we; + logic alert_regwen_qs; + logic alert_regwen_wd; + logic alert_info_ctrl_we; + logic alert_info_ctrl_en_qs; + logic alert_info_ctrl_en_wd; + logic [3:0] alert_info_ctrl_index_qs; + logic [3:0] alert_info_ctrl_index_wd; + logic alert_info_attr_re; + logic [3:0] alert_info_attr_qs; + logic alert_info_re; + logic [31:0] alert_info_qs; + logic cpu_regwen_we; + logic cpu_regwen_qs; + logic cpu_regwen_wd; + logic cpu_info_ctrl_we; + logic cpu_info_ctrl_en_qs; + logic cpu_info_ctrl_en_wd; + logic [3:0] cpu_info_ctrl_index_qs; + logic [3:0] cpu_info_ctrl_index_wd; + logic cpu_info_attr_re; + logic [3:0] cpu_info_attr_qs; + logic cpu_info_re; + logic [31:0] cpu_info_qs; + logic sw_rst_regwen_0_we; + logic sw_rst_regwen_0_qs; + logic sw_rst_regwen_0_wd; + logic sw_rst_regwen_1_we; + logic sw_rst_regwen_1_qs; + logic sw_rst_regwen_1_wd; + logic sw_rst_regwen_2_we; + logic sw_rst_regwen_2_qs; + logic sw_rst_regwen_2_wd; + logic sw_rst_ctrl_n_0_we; + logic sw_rst_ctrl_n_0_qs; + logic sw_rst_ctrl_n_0_wd; + logic sw_rst_ctrl_n_1_we; + logic sw_rst_ctrl_n_1_qs; + logic sw_rst_ctrl_n_1_wd; + logic sw_rst_ctrl_n_2_we; + logic sw_rst_ctrl_n_2_qs; + logic sw_rst_ctrl_n_2_wd; + logic err_code_reg_intg_err_qs; + logic err_code_reset_consistency_err_qs; + logic err_code_fsm_err_qs; + // Define register CDC handling. + // CDC handling is done on a per-reg instead of per-field boundary. + + // Register instances + // R[alert_test]: V(True) + logic alert_test_qe; + logic [1:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + // F[fatal_fault]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_fault ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_fault_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.fatal_fault.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe; + + // F[fatal_cnsty_fault]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_cnsty_fault ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_cnsty_fault_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[1]), + .q (reg2hw.alert_test.fatal_cnsty_fault.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_cnsty_fault.qe = alert_test_qe; + + + // R[reset_req]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_reset_req ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (reset_req_we), + .wd (reset_req_wd), + + // from internal hardware + .de (hw2reg.reset_req.de), + .d (hw2reg.reset_req.d), + + // to internal hardware + .qe (), + .q (reg2hw.reset_req.q), + .ds (), + + // to register interface (read) + .qs (reset_req_qs) + ); + + + // R[reset_info]: V(False) + // F[por]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_reset_info_por ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (reset_info_we), + .wd (reset_info_por_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (reset_info_por_qs) + ); + + // F[low_power_exit]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_reset_info_low_power_exit ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (reset_info_we), + .wd (reset_info_low_power_exit_wd), + + // from internal hardware + .de (hw2reg.reset_info.low_power_exit.de), + .d (hw2reg.reset_info.low_power_exit.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (reset_info_low_power_exit_qs) + ); + + // F[sw_reset]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_reset_info_sw_reset ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (reset_info_we), + .wd (reset_info_sw_reset_wd), + + // from internal hardware + .de (hw2reg.reset_info.sw_reset.de), + .d (hw2reg.reset_info.sw_reset.d), + + // to internal hardware + .qe (), + .q (reg2hw.reset_info.sw_reset.q), + .ds (), + + // to register interface (read) + .qs (reset_info_sw_reset_qs) + ); + + // F[hw_req]: 7:3 + prim_subreg #( + .DW (5), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (5'h0), + .Mubi (1'b0) + ) u_reset_info_hw_req ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (reset_info_we), + .wd (reset_info_hw_req_wd), + + // from internal hardware + .de (hw2reg.reset_info.hw_req.de), + .d (hw2reg.reset_info.hw_req.d), + + // to internal hardware + .qe (), + .q (reg2hw.reset_info.hw_req.q), + .ds (), + + // to register interface (read) + .qs (reset_info_hw_req_qs) + ); + + + // R[alert_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_we), + .wd (alert_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (alert_regwen_qs) + ); + + + // R[alert_info_ctrl]: V(False) + // Create REGWEN-gated WE signal + logic alert_info_ctrl_gated_we; + assign alert_info_ctrl_gated_we = alert_info_ctrl_we & alert_regwen_qs; + // F[en]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_info_ctrl_en ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (alert_info_ctrl_gated_we), + .wd (alert_info_ctrl_en_wd), + + // from internal hardware + .de (hw2reg.alert_info_ctrl.en.de), + .d (hw2reg.alert_info_ctrl.en.d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_info_ctrl.en.q), + .ds (), + + // to register interface (read) + .qs (alert_info_ctrl_en_qs) + ); + + // F[index]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_alert_info_ctrl_index ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (alert_info_ctrl_gated_we), + .wd (alert_info_ctrl_index_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_info_ctrl.index.q), + .ds (), + + // to register interface (read) + .qs (alert_info_ctrl_index_qs) + ); + + + // R[alert_info_attr]: V(True) + prim_subreg_ext #( + .DW (4) + ) u_alert_info_attr ( + .re (alert_info_attr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.alert_info_attr.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (alert_info_attr_qs) + ); + + + // R[alert_info]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_alert_info ( + .re (alert_info_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.alert_info.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (alert_info_qs) + ); + + + // R[cpu_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_cpu_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cpu_regwen_we), + .wd (cpu_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (cpu_regwen_qs) + ); + + + // R[cpu_info_ctrl]: V(False) + // Create REGWEN-gated WE signal + logic cpu_info_ctrl_gated_we; + assign cpu_info_ctrl_gated_we = cpu_info_ctrl_we & cpu_regwen_qs; + // F[en]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cpu_info_ctrl_en ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (cpu_info_ctrl_gated_we), + .wd (cpu_info_ctrl_en_wd), + + // from internal hardware + .de (hw2reg.cpu_info_ctrl.en.de), + .d (hw2reg.cpu_info_ctrl.en.d), + + // to internal hardware + .qe (), + .q (reg2hw.cpu_info_ctrl.en.q), + .ds (), + + // to register interface (read) + .qs (cpu_info_ctrl_en_qs) + ); + + // F[index]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cpu_info_ctrl_index ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (cpu_info_ctrl_gated_we), + .wd (cpu_info_ctrl_index_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cpu_info_ctrl.index.q), + .ds (), + + // to register interface (read) + .qs (cpu_info_ctrl_index_qs) + ); + + + // R[cpu_info_attr]: V(True) + prim_subreg_ext #( + .DW (4) + ) u_cpu_info_attr ( + .re (cpu_info_attr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.cpu_info_attr.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (cpu_info_attr_qs) + ); + + + // R[cpu_info]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_cpu_info ( + .re (cpu_info_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.cpu_info.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (cpu_info_qs) + ); + + + // Subregister 0 of Multireg sw_rst_regwen + // R[sw_rst_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_regwen_0_we), + .wd (sw_rst_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (sw_rst_regwen_0_qs) + ); + + + // Subregister 1 of Multireg sw_rst_regwen + // R[sw_rst_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_regwen_1_we), + .wd (sw_rst_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (sw_rst_regwen_1_qs) + ); + + + // Subregister 2 of Multireg sw_rst_regwen + // R[sw_rst_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_regwen_2_we), + .wd (sw_rst_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (sw_rst_regwen_2_qs) + ); + + + // Subregister 0 of Multireg sw_rst_ctrl_n + // R[sw_rst_ctrl_n_0]: V(False) + // Create REGWEN-gated WE signal + logic sw_rst_ctrl_n_0_gated_we; + assign sw_rst_ctrl_n_0_gated_we = sw_rst_ctrl_n_0_we & sw_rst_regwen_0_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_ctrl_n_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_ctrl_n_0_gated_we), + .wd (sw_rst_ctrl_n_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.sw_rst_ctrl_n[0].q), + .ds (), + + // to register interface (read) + .qs (sw_rst_ctrl_n_0_qs) + ); + + + // Subregister 1 of Multireg sw_rst_ctrl_n + // R[sw_rst_ctrl_n_1]: V(False) + // Create REGWEN-gated WE signal + logic sw_rst_ctrl_n_1_gated_we; + assign sw_rst_ctrl_n_1_gated_we = sw_rst_ctrl_n_1_we & sw_rst_regwen_1_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_ctrl_n_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_ctrl_n_1_gated_we), + .wd (sw_rst_ctrl_n_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.sw_rst_ctrl_n[1].q), + .ds (), + + // to register interface (read) + .qs (sw_rst_ctrl_n_1_qs) + ); + + + // Subregister 2 of Multireg sw_rst_ctrl_n + // R[sw_rst_ctrl_n_2]: V(False) + // Create REGWEN-gated WE signal + logic sw_rst_ctrl_n_2_gated_we; + assign sw_rst_ctrl_n_2_gated_we = sw_rst_ctrl_n_2_we & sw_rst_regwen_2_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_ctrl_n_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_ctrl_n_2_gated_we), + .wd (sw_rst_ctrl_n_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.sw_rst_ctrl_n[2].q), + .ds (), + + // to register interface (read) + .qs (sw_rst_ctrl_n_2_qs) + ); + + + // R[err_code]: V(False) + // F[reg_intg_err]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_err_code_reg_intg_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.err_code.reg_intg_err.de), + .d (hw2reg.err_code.reg_intg_err.d), + + // to internal hardware + .qe (), + .q (reg2hw.err_code.reg_intg_err.q), + .ds (), + + // to register interface (read) + .qs (err_code_reg_intg_err_qs) + ); + + // F[reset_consistency_err]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_err_code_reset_consistency_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.err_code.reset_consistency_err.de), + .d (hw2reg.err_code.reset_consistency_err.d), + + // to internal hardware + .qe (), + .q (reg2hw.err_code.reset_consistency_err.q), + .ds (), + + // to register interface (read) + .qs (err_code_reset_consistency_err_qs) + ); + + // F[fsm_err]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_err_code_fsm_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.err_code.fsm_err.de), + .d (hw2reg.err_code.fsm_err.d), + + // to internal hardware + .qe (), + .q (reg2hw.err_code.fsm_err.q), + .ds (), + + // to register interface (read) + .qs (err_code_fsm_err_qs) + ); + + + + logic [17:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == RSTMGR_ALERT_TEST_OFFSET); + addr_hit[ 1] = (reg_addr == RSTMGR_RESET_REQ_OFFSET); + addr_hit[ 2] = (reg_addr == RSTMGR_RESET_INFO_OFFSET); + addr_hit[ 3] = (reg_addr == RSTMGR_ALERT_REGWEN_OFFSET); + addr_hit[ 4] = (reg_addr == RSTMGR_ALERT_INFO_CTRL_OFFSET); + addr_hit[ 5] = (reg_addr == RSTMGR_ALERT_INFO_ATTR_OFFSET); + addr_hit[ 6] = (reg_addr == RSTMGR_ALERT_INFO_OFFSET); + addr_hit[ 7] = (reg_addr == RSTMGR_CPU_REGWEN_OFFSET); + addr_hit[ 8] = (reg_addr == RSTMGR_CPU_INFO_CTRL_OFFSET); + addr_hit[ 9] = (reg_addr == RSTMGR_CPU_INFO_ATTR_OFFSET); + addr_hit[10] = (reg_addr == RSTMGR_CPU_INFO_OFFSET); + addr_hit[11] = (reg_addr == RSTMGR_SW_RST_REGWEN_0_OFFSET); + addr_hit[12] = (reg_addr == RSTMGR_SW_RST_REGWEN_1_OFFSET); + addr_hit[13] = (reg_addr == RSTMGR_SW_RST_REGWEN_2_OFFSET); + addr_hit[14] = (reg_addr == RSTMGR_SW_RST_CTRL_N_0_OFFSET); + addr_hit[15] = (reg_addr == RSTMGR_SW_RST_CTRL_N_1_OFFSET); + addr_hit[16] = (reg_addr == RSTMGR_SW_RST_CTRL_N_2_OFFSET); + addr_hit[17] = (reg_addr == RSTMGR_ERR_CODE_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(RSTMGR_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(RSTMGR_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(RSTMGR_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(RSTMGR_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(RSTMGR_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(RSTMGR_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(RSTMGR_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(RSTMGR_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(RSTMGR_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(RSTMGR_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(RSTMGR_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(RSTMGR_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(RSTMGR_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(RSTMGR_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(RSTMGR_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(RSTMGR_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(RSTMGR_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(RSTMGR_PERMIT[17] & ~reg_be))))); + end + + // Generate write-enables + assign alert_test_we = addr_hit[0] & reg_we & !reg_error; + + assign alert_test_fatal_fault_wd = reg_wdata[0]; + + assign alert_test_fatal_cnsty_fault_wd = reg_wdata[1]; + assign reset_req_we = addr_hit[1] & reg_we & !reg_error; + + assign reset_req_wd = reg_wdata[3:0]; + assign reset_info_we = addr_hit[2] & reg_we & !reg_error; + + assign reset_info_por_wd = reg_wdata[0]; + + assign reset_info_low_power_exit_wd = reg_wdata[1]; + + assign reset_info_sw_reset_wd = reg_wdata[2]; + + assign reset_info_hw_req_wd = reg_wdata[7:3]; + assign alert_regwen_we = addr_hit[3] & reg_we & !reg_error; + + assign alert_regwen_wd = reg_wdata[0]; + assign alert_info_ctrl_we = addr_hit[4] & reg_we & !reg_error; + + assign alert_info_ctrl_en_wd = reg_wdata[0]; + + assign alert_info_ctrl_index_wd = reg_wdata[7:4]; + assign alert_info_attr_re = addr_hit[5] & reg_re & !reg_error; + assign alert_info_re = addr_hit[6] & reg_re & !reg_error; + assign cpu_regwen_we = addr_hit[7] & reg_we & !reg_error; + + assign cpu_regwen_wd = reg_wdata[0]; + assign cpu_info_ctrl_we = addr_hit[8] & reg_we & !reg_error; + + assign cpu_info_ctrl_en_wd = reg_wdata[0]; + + assign cpu_info_ctrl_index_wd = reg_wdata[7:4]; + assign cpu_info_attr_re = addr_hit[9] & reg_re & !reg_error; + assign cpu_info_re = addr_hit[10] & reg_re & !reg_error; + assign sw_rst_regwen_0_we = addr_hit[11] & reg_we & !reg_error; + + assign sw_rst_regwen_0_wd = reg_wdata[0]; + assign sw_rst_regwen_1_we = addr_hit[12] & reg_we & !reg_error; + + assign sw_rst_regwen_1_wd = reg_wdata[0]; + assign sw_rst_regwen_2_we = addr_hit[13] & reg_we & !reg_error; + + assign sw_rst_regwen_2_wd = reg_wdata[0]; + assign sw_rst_ctrl_n_0_we = addr_hit[14] & reg_we & !reg_error; + + assign sw_rst_ctrl_n_0_wd = reg_wdata[0]; + assign sw_rst_ctrl_n_1_we = addr_hit[15] & reg_we & !reg_error; + + assign sw_rst_ctrl_n_1_wd = reg_wdata[0]; + assign sw_rst_ctrl_n_2_we = addr_hit[16] & reg_we & !reg_error; + + assign sw_rst_ctrl_n_2_wd = reg_wdata[0]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check = '0; + reg_we_check[0] = alert_test_we; + reg_we_check[1] = reset_req_we; + reg_we_check[2] = reset_info_we; + reg_we_check[3] = alert_regwen_we; + reg_we_check[4] = alert_info_ctrl_gated_we; + reg_we_check[5] = 1'b0; + reg_we_check[6] = 1'b0; + reg_we_check[7] = cpu_regwen_we; + reg_we_check[8] = cpu_info_ctrl_gated_we; + reg_we_check[9] = 1'b0; + reg_we_check[10] = 1'b0; + reg_we_check[11] = sw_rst_regwen_0_we; + reg_we_check[12] = sw_rst_regwen_1_we; + reg_we_check[13] = sw_rst_regwen_2_we; + reg_we_check[14] = sw_rst_ctrl_n_0_gated_we; + reg_we_check[15] = sw_rst_ctrl_n_1_gated_we; + reg_we_check[16] = sw_rst_ctrl_n_2_gated_we; + reg_we_check[17] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + addr_hit[1]: begin + reg_rdata_next[3:0] = reset_req_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = reset_info_por_qs; + reg_rdata_next[1] = reset_info_low_power_exit_qs; + reg_rdata_next[2] = reset_info_sw_reset_qs; + reg_rdata_next[7:3] = reset_info_hw_req_qs; + end + + addr_hit[3]: begin + reg_rdata_next[0] = alert_regwen_qs; + end + + addr_hit[4]: begin + reg_rdata_next[0] = alert_info_ctrl_en_qs; + reg_rdata_next[7:4] = alert_info_ctrl_index_qs; + end + + addr_hit[5]: begin + reg_rdata_next[3:0] = alert_info_attr_qs; + end + + addr_hit[6]: begin + reg_rdata_next[31:0] = alert_info_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = cpu_regwen_qs; + end + + addr_hit[8]: begin + reg_rdata_next[0] = cpu_info_ctrl_en_qs; + reg_rdata_next[7:4] = cpu_info_ctrl_index_qs; + end + + addr_hit[9]: begin + reg_rdata_next[3:0] = cpu_info_attr_qs; + end + + addr_hit[10]: begin + reg_rdata_next[31:0] = cpu_info_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = sw_rst_regwen_0_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = sw_rst_regwen_1_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = sw_rst_regwen_2_qs; + end + + addr_hit[14]: begin + reg_rdata_next[0] = sw_rst_ctrl_n_0_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = sw_rst_ctrl_n_1_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = sw_rst_ctrl_n_2_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = err_code_reg_intg_err_qs; + reg_rdata_next[1] = err_code_reset_consistency_err_qs; + reg_rdata_next[2] = err_code_fsm_err_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/README.md b/hw/top_darjeeling/ip_autogen/rv_plic/README.md new file mode 100644 index 0000000000000..1436784f7a380 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/README.md @@ -0,0 +1,26 @@ +# Interrupt Controller Technical Specification + +# Overview + +This document specifies the Interrupt Controller (RV_PLIC) functionality. This +module conforms to the +[Comportable guideline for peripheral functionality](../../../../doc/contributing/hw/comportability/README.md). +See that document for integration overview within the broader top level system. + + +## Features + +- RISC-V Platform-Level Interrupt Controller (PLIC) compliant interrupt controller +- Support arbitrary number of interrupt vectors (up to 255) and targets +- Support interrupt enable, interrupt status registers +- Memory-mapped MSIP register per HART for software interrupt control. + +## Description + +The RV_PLIC module is designed to manage various interrupt sources from the +peripherals. It receives interrupt events as either edge or level of the +incoming interrupt signals (``intr_src_i``) and can notify multiple targets. + +## Compatibility + +The RV_PLIC is compatible with any RISC-V core implementing the RISC-V privilege specification. diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic.hjson b/hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic.hjson new file mode 100644 index 0000000000000..e7dc31a48a206 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic.hjson @@ -0,0 +1,1477 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +# RV_PLIC register template +# +# Parameter (given by Python tool) +# - src: Number of Interrupt Sources +# - target: Number of Targets that handle interrupt requests +# - prio: Max value of interrupt priorities +# - module_instance_name: Module instance name. +{ + name: "rv_plic", + human_name: "RISC-V platform level interrupt controller", + one_line_desc: "Interrupt controller, adhering to RISC-V PLIC specification", + one_paragraph_desc: ''' + rv_plic is an interrupt controller which handles multiple interrupt sources. Each interrupt + source can be enabled or disabled, and can be given a priority. rv_plic generates an output + that identifies the source with the highest priority amongst those that are currently asserted. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "33", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_rv_plic", + revisions: [ + { + version: "2.0.0", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2", + dif_stage: "S2", + commit_id: "", + notes: "Use FPV to perform block level verification.", + } + ], + clocking: [{clock: "clk_i", reset: "rst_ni"}], + bus_interfaces: [ + { protocol: "tlul", direction: "device" } + ], + + param_list: [ + { name: "NumSrc", + desc: "Number of interrupt sources", + type: "int", + default: "160", + local: "true" + }, + { name: "NumTarget", + desc: "Number of Targets (Harts)", + type: "int", + default: "1", + local: "true", + }, + { name: "PrioWidth", + desc: "Width of priority signals", + type: "int", + default: "2", + local: "true", + }, + ], + + // In order to not disturb the PLIC address map, we place the alert test + // register manually at a safe offset after the main CSRs. + no_auto_alert_regs: "True", + alert_list: [ + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. + ''' + } + ], + + inter_signal_list: [ + { struct: "logic", + type: "uni", + name: "irq", + act: "req", + package: "", + width: "1" + }, + + { struct: "logic", + type: "uni", + name: "irq_id", + act: "req", + package: "", + }, + + { struct: "logic", + type: "uni", + name: "msip", + act: "req", + package: "", + width: "1" + }, + ] + + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + ] + + features: [ + { name: "RV_PLIC.PRIORITY", + desc: '''Each interrupt source can be given a configurable priority.''' + } + { name: "RV_PLIC.ENABLE", + desc: '''Each target has an associated set of interrupt enable bits. Configuring these + controls whether a target will be notified when the interrupt is triggered. + ''' + } + ] + + regwidth: "32", + registers: [ + { name: "PRIO0", + desc: "Interrupt Source 0 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO1", + desc: "Interrupt Source 1 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO2", + desc: "Interrupt Source 2 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO3", + desc: "Interrupt Source 3 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO4", + desc: "Interrupt Source 4 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO5", + desc: "Interrupt Source 5 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO6", + desc: "Interrupt Source 6 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO7", + desc: "Interrupt Source 7 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO8", + desc: "Interrupt Source 8 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO9", + desc: "Interrupt Source 9 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO10", + desc: "Interrupt Source 10 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO11", + desc: "Interrupt Source 11 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO12", + desc: "Interrupt Source 12 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO13", + desc: "Interrupt Source 13 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO14", + desc: "Interrupt Source 14 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO15", + desc: "Interrupt Source 15 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO16", + desc: "Interrupt Source 16 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO17", + desc: "Interrupt Source 17 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO18", + desc: "Interrupt Source 18 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO19", + desc: "Interrupt Source 19 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO20", + desc: "Interrupt Source 20 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO21", + desc: "Interrupt Source 21 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO22", + desc: "Interrupt Source 22 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO23", + desc: "Interrupt Source 23 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO24", + desc: "Interrupt Source 24 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO25", + desc: "Interrupt Source 25 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO26", + desc: "Interrupt Source 26 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO27", + desc: "Interrupt Source 27 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO28", + desc: "Interrupt Source 28 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO29", + desc: "Interrupt Source 29 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO30", + desc: "Interrupt Source 30 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO31", + desc: "Interrupt Source 31 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO32", + desc: "Interrupt Source 32 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO33", + desc: "Interrupt Source 33 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO34", + desc: "Interrupt Source 34 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO35", + desc: "Interrupt Source 35 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO36", + desc: "Interrupt Source 36 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO37", + desc: "Interrupt Source 37 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO38", + desc: "Interrupt Source 38 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO39", + desc: "Interrupt Source 39 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO40", + desc: "Interrupt Source 40 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO41", + desc: "Interrupt Source 41 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO42", + desc: "Interrupt Source 42 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO43", + desc: "Interrupt Source 43 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO44", + desc: "Interrupt Source 44 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO45", + desc: "Interrupt Source 45 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO46", + desc: "Interrupt Source 46 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO47", + desc: "Interrupt Source 47 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO48", + desc: "Interrupt Source 48 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO49", + desc: "Interrupt Source 49 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO50", + desc: "Interrupt Source 50 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO51", + desc: "Interrupt Source 51 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO52", + desc: "Interrupt Source 52 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO53", + desc: "Interrupt Source 53 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO54", + desc: "Interrupt Source 54 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO55", + desc: "Interrupt Source 55 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO56", + desc: "Interrupt Source 56 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO57", + desc: "Interrupt Source 57 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO58", + desc: "Interrupt Source 58 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO59", + desc: "Interrupt Source 59 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO60", + desc: "Interrupt Source 60 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO61", + desc: "Interrupt Source 61 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO62", + desc: "Interrupt Source 62 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO63", + desc: "Interrupt Source 63 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO64", + desc: "Interrupt Source 64 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO65", + desc: "Interrupt Source 65 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO66", + desc: "Interrupt Source 66 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO67", + desc: "Interrupt Source 67 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO68", + desc: "Interrupt Source 68 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO69", + desc: "Interrupt Source 69 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO70", + desc: "Interrupt Source 70 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO71", + desc: "Interrupt Source 71 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO72", + desc: "Interrupt Source 72 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO73", + desc: "Interrupt Source 73 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO74", + desc: "Interrupt Source 74 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO75", + desc: "Interrupt Source 75 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO76", + desc: "Interrupt Source 76 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO77", + desc: "Interrupt Source 77 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO78", + desc: "Interrupt Source 78 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO79", + desc: "Interrupt Source 79 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO80", + desc: "Interrupt Source 80 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO81", + desc: "Interrupt Source 81 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO82", + desc: "Interrupt Source 82 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO83", + desc: "Interrupt Source 83 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO84", + desc: "Interrupt Source 84 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO85", + desc: "Interrupt Source 85 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO86", + desc: "Interrupt Source 86 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO87", + desc: "Interrupt Source 87 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO88", + desc: "Interrupt Source 88 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO89", + desc: "Interrupt Source 89 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO90", + desc: "Interrupt Source 90 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO91", + desc: "Interrupt Source 91 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO92", + desc: "Interrupt Source 92 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO93", + desc: "Interrupt Source 93 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO94", + desc: "Interrupt Source 94 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO95", + desc: "Interrupt Source 95 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO96", + desc: "Interrupt Source 96 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO97", + desc: "Interrupt Source 97 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO98", + desc: "Interrupt Source 98 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO99", + desc: "Interrupt Source 99 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO100", + desc: "Interrupt Source 100 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO101", + desc: "Interrupt Source 101 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO102", + desc: "Interrupt Source 102 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO103", + desc: "Interrupt Source 103 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO104", + desc: "Interrupt Source 104 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO105", + desc: "Interrupt Source 105 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO106", + desc: "Interrupt Source 106 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO107", + desc: "Interrupt Source 107 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO108", + desc: "Interrupt Source 108 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO109", + desc: "Interrupt Source 109 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO110", + desc: "Interrupt Source 110 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO111", + desc: "Interrupt Source 111 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO112", + desc: "Interrupt Source 112 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO113", + desc: "Interrupt Source 113 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO114", + desc: "Interrupt Source 114 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO115", + desc: "Interrupt Source 115 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO116", + desc: "Interrupt Source 116 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO117", + desc: "Interrupt Source 117 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO118", + desc: "Interrupt Source 118 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO119", + desc: "Interrupt Source 119 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO120", + desc: "Interrupt Source 120 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO121", + desc: "Interrupt Source 121 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO122", + desc: "Interrupt Source 122 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO123", + desc: "Interrupt Source 123 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO124", + desc: "Interrupt Source 124 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO125", + desc: "Interrupt Source 125 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO126", + desc: "Interrupt Source 126 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO127", + desc: "Interrupt Source 127 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO128", + desc: "Interrupt Source 128 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO129", + desc: "Interrupt Source 129 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO130", + desc: "Interrupt Source 130 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO131", + desc: "Interrupt Source 131 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO132", + desc: "Interrupt Source 132 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO133", + desc: "Interrupt Source 133 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO134", + desc: "Interrupt Source 134 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO135", + desc: "Interrupt Source 135 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO136", + desc: "Interrupt Source 136 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO137", + desc: "Interrupt Source 137 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO138", + desc: "Interrupt Source 138 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO139", + desc: "Interrupt Source 139 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO140", + desc: "Interrupt Source 140 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO141", + desc: "Interrupt Source 141 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO142", + desc: "Interrupt Source 142 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO143", + desc: "Interrupt Source 143 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO144", + desc: "Interrupt Source 144 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO145", + desc: "Interrupt Source 145 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO146", + desc: "Interrupt Source 146 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO147", + desc: "Interrupt Source 147 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO148", + desc: "Interrupt Source 148 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO149", + desc: "Interrupt Source 149 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO150", + desc: "Interrupt Source 150 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO151", + desc: "Interrupt Source 151 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO152", + desc: "Interrupt Source 152 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO153", + desc: "Interrupt Source 153 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO154", + desc: "Interrupt Source 154 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO155", + desc: "Interrupt Source 155 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO156", + desc: "Interrupt Source 156 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO157", + desc: "Interrupt Source 157 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO158", + desc: "Interrupt Source 158 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "PRIO159", + desc: "Interrupt Source 159 Priority", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { skipto: "0x00001000" } + { multireg: { + name: "IP", + desc: "Interrupt Pending", + count: "NumSrc", + cname: "RV_PLIC", + swaccess: "ro", + hwaccess: "hwo", + fields: [ + { bits: "0", name: "P", desc: "Interrupt Pending of Source" } + ], + tags: [// IP is driven by intr_src, cannot auto-predict + "excl:CsrNonInitTests:CsrExclCheck"], + } + }, + { skipto: "0x2000" } + { multireg: { + name: "IE0", + desc: "Interrupt Enable for Target 0", + count: "NumSrc", + cname: "RV_PLIC", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "0", name: "E", desc: "Interrupt Enable of Source" } + ], + } + } + { skipto: "0x200000" } + { name: "THRESHOLD0", + desc: "Threshold of priority for Target 0", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "CC0", + desc: '''Claim interrupt by read, complete interrupt by write for Target 0. + Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.''', + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + hwre: "true", + fields: [ + { bits: "7:0" } + ], + tags: [// CC register value is related to IP + "excl:CsrNonInitTests:CsrExclCheck"], + } + { skipto: "0x4000000" } + { name: "MSIP0", + desc: '''msip for Hart 0. + Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear.''', + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "0", + desc: "Software Interrupt Pending register", + } + ], + } + { skipto: "0x4004000" } + { name: "ALERT_TEST", + desc: '''Alert Test Register.''', + swaccess: "wo", + hwaccess: "hro", + hwqe: "True", + hwext: "True", + fields: [ + { bits: "0", + name: "fatal_fault", + desc: "'Write 1 to trigger one alert event of this kind.'", + } + ], + } + ], +} diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic_fpv_testplan.hjson b/hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic_fpv_testplan.hjson new file mode 100644 index 0000000000000..ea0956eff732b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic_fpv_testplan.hjson @@ -0,0 +1,73 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "rv_plic" + import_testplans: ["hw/dv/tools/dvsim/testplans/fpv_csr_testplan.hjson"] + testpoints: [ + { + name: LevelTriggeredIp_A + desc: '''If interrupt pending (`ip`) is triggered, and the level indicator is set to + level triggered (`le=0`), then in the prvious clock cycle, the interrupt source + (`intr_src_i) should be set to 1.''' + stage: V2 + tests: ["rv_plic_assert"] + } + { + name: LevelTriggeredIpWithClaim_A + desc: '''If `intr_src_i` is set to 1, level indicator is set to level triggered, and claim + signal is not set, then at the next clock cycle `ip` will be triggered.''' + stage: V2 + tests: ["rv_plic_assert"] + } + { + name: IpStableAfterTriggered_A + desc: "Once `ip` is set, it stays stable until is being claimed." + stage: V2 + tests: ["rv_plic_assert"] + } + { + name: IpClearAfterClaim_A + desc: "Once `ip` is set and being claimed, its value is cleared to 0." + stage: V2 + tests: ["rv_plic_assert"] + } + { + name: IpStableAfterClaimed_A + desc: '''Once `ip` is cleared to 0, it stays stable until completed and being triggered + again.''' + stage: V2 + tests: ["rv_plic_assert"] + } + { + name: TriggerIrqForwardCheck_A + desc: '''If interrupt is enabled (`ie=1`), interrupt pending is set (`ip=1`), interrupt + input has the highest priority among the rest of the inputs, and its priority is + above the threshold. Then in the next clock clcye, the `irq_o` should be triggered, + and the `irq_id_o` will reflect the input ID.''' + stage: V2 + tests: ["rv_plic_assert"] + } + { + name: TriggerIrqBackwardCheck_A + desc: '''If `irq_o` is set to 1, then in the previous clock cycle, the corresponding + `ip` should be set, `ie` should be enabled, and the interrupt source should above the + threshold and have the highest priority.''' + stage: V2 + tests: ["rv_plic_assert"] + + } + { + name: IdChangeWithIrq_A + desc: '''If `irq_id_o` signal is changed and the signal does not change to 0 (value 0 does + not represent any interrupt source ID). Then either of the two condition should have + happened: + - `irq_o` is triggered + - No interrupt triggered, `ip` is set and `ie` is enabled, interrupt source priority is the + largest among the rest of the interrupt, but the interrupt source + priority is smaller than the threshold''' + stage: V2 + tests: ["rv_plic_assert"] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic_sec_cm_testplan.hjson b/hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic_sec_cm_testplan.hjson new file mode 100644 index 0000000000000..d7aac02a08d24 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic_sec_cm_testplan.hjson @@ -0,0 +1,33 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../rv_plic/data/rv_plic.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../rv_plic/data/rv_plic_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: "Verify the countermeasure(s) BUS.INTEGRITY." + stage: V2S + tests: [] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/data/top_darjeeling_rv_plic.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/rv_plic/data/top_darjeeling_rv_plic.ipconfig.hjson new file mode 100644 index 0000000000000..2caf7c0edc6d1 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/data/top_darjeeling_rv_plic.ipconfig.hjson @@ -0,0 +1,13 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_rv_plic + param_values: + { + src: 160 + target: 1 + prio: 3 + topname: darjeeling + } +} diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/doc/block_diagram.svg b/hw/top_darjeeling/ip_autogen/rv_plic/doc/block_diagram.svg new file mode 100644 index 0000000000000..ac02b678fa6d7 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/doc/block_diagram.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/doc/checklist.md b/hw/top_darjeeling/ip_autogen/rv_plic/doc/checklist.md new file mode 100644 index 0000000000000..9177f98cdeefa --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/doc/checklist.md @@ -0,0 +1,264 @@ +# RV_PLIC Checklist + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [RV_PLIC peripheral](../README.md). +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done | [RV_PLIC Spec][] +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | Done | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | + +[RV_PLIC Spec]: ../README.md + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | N/A | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [MISSING_FUNC][] | N/A | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [AREA_CHECK][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | One TODO about Vivado Issue +RTL | [STYLE_X][] | Done | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | N/A | +Code Quality | [TIMING_CHECK][] | Done | Fmax @ 50MHz on NexysVideo +Code Quality | [CDC_SYNCMACRO][] | N/A | +Security | [SEC_CM_DOCUMENTED][] | N/A | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | N/A | +Security | [SEC_CM_NON_RESET_FLOPS][] | N/A | +Security | [SEC_CM_SHADOW_REGS][] | N/A | +Security | [SEC_CM_RTL_REVIEWED][] | N/A | +Security | [SEC_CM_COUNCIL_REVIEWED][] | N/A | This block only contains the bus-integrity CM. + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Done | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_RTL][] | Done | +Review | [REVIEW_DELETED_FF][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | eunchan@ gac@ chencindy@ ttrippel@ +Review | Signoff date | Done | 2022-07-25 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [rv_plic_fpv_plan](./dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Done | +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | N/A | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | N/A | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | N/A | +Tests | [SIM_SMOKE_TEST_PASSING][] | N/A | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | N/A | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Done | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | N/A | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | N/A | +Regression | [FPV_REGRESSION_SETUP][] | Done | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | N/A | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A | +Review | [DESIGN_SPEC_REVIEWED][] | Done | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | N/A | +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | N/A | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | N/A | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | N/A | +Tests | [SIM_ALL_TESTS_PASSING][] | N/A | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Done | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Done | +Tests | [SIM_FW_SIMULATED][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | N/A | +Coverage | [SIM_CODE_COVERAGE_V2][] | N/A | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | N/A | +Coverage | [FPV_CODE_COVERAGE_V2][] | Done | +Coverage | [FPV_COI_COVERAGE_V2][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | N/A | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Not Started | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]: ../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Waived | Waived since only 1 standard sec_cm - bus integrity. +Tests | [FPV_SEC_CM_PROVEN][] | Done | The bus integrity cm has been proven formally. +Tests | [SIM_SEC_CM_VERIFIED][] | N/A | This module only has an FPV testbench. +Coverage | [SIM_COVERAGE_REVIEWED][] | N/A | This module only has an FPV testbench. +Review | [SEC_CM_DV_REVIEWED][] | Waived | Waived since only 1 standard sec_cm - bus integrity. + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_proven +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/doc/dv/README.md b/hw/top_darjeeling/ip_autogen/rv_plic/doc/dv/README.md new file mode 100644 index 0000000000000..18130a9ce6c30 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/doc/dv/README.md @@ -0,0 +1,48 @@ +# RV_PLIC DV document + +## Goals +* DV: + * RV_PLIC is decided to verify in FPV only + +* FPV: + * Verify all the RV_PLIC outputs by writing assumptions and assertions with a + FPV based testbench + * Verify TileLink device protocol compliance with a FPV based testbench + +## Current status +* [Design & verification stage](../../../../README.md) + * [HW development stages](../../../../../../doc/project_governance/development_stages.md) +* FPV dashboard (link TBD) + +## Design features +For detailed information on RV_PLIC design features, please see the +[RV_PLIC design specification](../../README.md). + +## Testbench architecture +RV_PLIC FPV testbench has been constructed based on the [formal +architecture](../../../../../formal/README.md). + +### Block diagram +![Block diagram](fpv.svg) + +#### TLUL assertions +* The file `rv_plic_bind.sv` binds the `tlul_assert` [assertions](../../../../../ip/tlul/doc/TlulProtocolChecker.md) + to rv_plic to ensure TileLink interface protocol compliance. +* The `hw/rv_plic/fpv/tb/rv_plic_bind.sv` also binds the `rv_plic_csr_assert_fpv` + under `fpv/vip/` to check if TileLink writes and reads correct + CSRs. + +#### RV_PLIC assertions +The file `rv_plic_bind.sv` binds the `rv_plic_assert` under `rv_plic_assert.sv`. +The assertion file ensures RV_PLIC's outputs (`irq_o` and `irq_id_o`) and important signals (`ip`) are being asserted. + +##### Symbolic variables +Due to there are large number of input interrupt sources, the symbolic variable +is used to reduce the number of repeated assertions code. In RV_PLIC, we +declared two symbolic variables `src_sel` and `tgt_sel` to represent the index for +interrupt source and interrupt target. +Detailed explanation is listed in the +[Symbolic Variables](../../../../../formal/README.md#symbolic-variables) section. + +## Testplan +[Testplan](../../data/rv_plic_fpv_testplan.hjson) diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/doc/dv/fpv.svg b/hw/top_darjeeling/ip_autogen/rv_plic/doc/dv/fpv.svg new file mode 100644 index 0000000000000..2f4cfe0798530 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/doc/dv/fpv.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/doc/programmers_guide.md b/hw/top_darjeeling/ip_autogen/rv_plic/doc/programmers_guide.md new file mode 100644 index 0000000000000..cdbd8f2c62a3a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/doc/programmers_guide.md @@ -0,0 +1,100 @@ +# Programmer's Guide + +## Initialization + +After reset, RV_PLIC doesn't generate any interrupts to any targets even if +interrupt sources are set, as all priorities and thresholds are 0 by default and +all ``IE`` values are 0. Software should configure the above three registers. + +[`PRIO0`](../data/rv_plic.hjson#prio0) .. [`PRIO31`](../data/rv_plic.hjson#prio1) registers are unique. So, only one of the targets +shall configure them. + +```c +// Pseudo-code below +void plic_init() { + // Configure priority + // Note that PRIO0 register doesn't affect as intr_src_i[0] is tied to 0. + for (int i = 0; i < N_SOURCE; ++i) { + *(PRIO + i) = value(i); + } +} + +void plic_threshold(tid, threshold) { + *(THRESHOLD + tid) = threshold; +} + +void plic_enable(tid, iid) { + // iid: 0-based ID + int offset = ceil(N_SOURCE / 32) * tid + (iid >> 5); + + *(IE + offset) = *(IE + offset) | (1 << (iid % 32)); +} +``` + +## Handling Interrupt Request Events + +If software receives an interrupt request, it is recommended to follow the steps +shown below (assuming target 0 which uses [`CC0`](../data/rv_plic.hjson#cc0) for claim/complete). + +1. Claim the interrupts right after entering to the interrupt service routine + by reading the [`CC0`](../data/rv_plic.hjson#cc0) register. +2. Determine which interrupt should be serviced based on the values read from + the [`CC0`](../data/rv_plic.hjson#cc0) register. +3. Execute ISR, clearing the originating peripheral interrupt. +4. Write Interrupt ID to [`CC0`](../data/rv_plic.hjson#cc0) +5. Repeat as necessary for other pending interrupts. + +It is possible to have multiple interrupt events claimed. If software claims one +interrupt request, then the process module advertises any pending interrupts +with lower priority unless new higher priority interrupt events occur. If a +higher interrupt event occurs after previous interrupt is claimed, the RV_PLIC +IP advertises the higher priority interrupt. Software may utilize an event +manager inside a loop so that interrupt claiming and completion can be +separated. + +~~~~c +void interrupt_service() { + uint32_t tid = /* ... */; + uint32_t iid = *(CC + tid); + if (iid == 0) { + // Interrupt is claimed by one of other targets. + return; + } + + do { + // Process interrupts... + // ... + + // Finish. + *(CC + tid) = iid; + iid = *(CC + tid); + } while (iid != 0); +} +~~~~ + +As a reference, default interrupt service routines are auto-generated for each +IP, and are documented [here](/sw/apis/isr__testutils_8h.html). + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_rv_plic.h) + +## Registers + +The RV_PLIC in the top level is generated by topgen tool so that the number of +interrupt sources may be different. + +- IE: CEILING(N_SOURCE / DW) X N_TARGET + Each bit enables corresponding interrupt source. Each target has IE set. +- PRIO: N_SOURCE + Universal set across all targets. Lower n bits are valid. n is determined by + MAX_PRIO parameter +- THRESHOLD: N_TARGET + Priority threshold per target. Only priority of the interrupt greater than + threshold can raise interrupt notification to the target. +- IP: CEILING(N_SOURCE / DW) + Pending bits right after the gateways. Read-only +- CC: N_TARGET + Claim by read, complete by write + +* [Register Table](../data/rv_plic.hjson#interfaces) diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/doc/theory_of_operation.md b/hw/top_darjeeling/ip_autogen/rv_plic/doc/theory_of_operation.md new file mode 100644 index 0000000000000..161a7979787cd --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/doc/theory_of_operation.md @@ -0,0 +1,118 @@ +# Theory of Operation + +## Block Diagram + +![RV_PLIC Block Diagram](block_diagram.svg) + +## Hardware Interfaces + +* [Interface Tables](../data/rv_plic.hjson#interfaces) + +## Design Details + +### Identifier + +Each interrupt source has a unique ID assigned based upon its bit position +within the input `intr_src_i`. ID ranges from 0 to N, the number of interrupt +sources. ID 0 is reserved and represents no interrupt. The bit 0 of +`intr_src_i` shall be tied to 0 from the outside of RV_PLIC. The +`intr_src_i[i]` bit has an ID of `i`. This ID is used when targets "claim" the +interrupt and to "complete" the interrupt event. + +### Priority and Threshold + +Interrupt sources have configurable priority values. The maximum value of the +priority is configurable through the localparam `MAX_PRIO` in the rv_plic +top-level module. For each target there is a threshold value ([`THRESHOLD0`](../data/rv_plic.hjson#threshold0) for +target 0). RV_PLIC notifies a target of an interrupt only if it's priority is +strictly greater than the target's threshold. Note this means an interrupt with +a priority is 0 is effectively prevented from causing an interrupt at any target +and a target can suppress all interrupts by setting it's threshold to the max +priority value. + +`MAX_PRIO` parameter is most area contributing option in RV_PLIC. If `MAX_PRIO` +is big, then finding the highest priority in Process module may consume a lot of +logic gates. + +### Interrupt Gateways + +The Gateway observes incoming interrupt sources and converts them to a common +interrupt format used internally by RV_PLIC. It can be parameterized to detect +interrupts events on an edge (when the signal changes from **0** to **1**) or +level basis (where the signal remains at **1**). +The choice is a system-integration decision and can be configured via the design parameter `LevelEdgeTrig` for each interrupt request. + +When the gateway detects an interrupt event it raises the interrupt pending bit +([`IP`](../data/rv_plic.hjson#ip)) for that interrupt source. When an interrupt is claimed by a target the +relevant bit of [`IP`](../data/rv_plic.hjson#ip) is cleared. A bit in [`IP`](../data/rv_plic.hjson#ip) will not be reasserted until the +target signals completion of the interrupt. Any new interrupt event between a +bit in [`IP`](../data/rv_plic.hjson#ip) asserting and completing that interrupt is ignored. In particular +this means that for edge triggered interrupts if a new edge is seen after the +source's [`IP`](../data/rv_plic.hjson#ip) bit is asserted but before completion, that edge will be ignored +(counting missed edges as discussed in the RISC-V PLIC specification is not +supported). + +Note that there is no ability for a level triggered interrupt to be cancelled. +If the interrupt drops after the gateway has set a bit in [`IP`](../data/rv_plic.hjson#ip), the bit will +remain set until the interrupt is completed. The SW handler should be conscious +of this and check the interrupt still requires handling in the handler if this +behaviour is possible. + +### Interrupt Enables + +Each target has a set of Interrupt Enable ([`IE0`](../data/rv_plic.hjson#ie0) for target 0) registers. Each +bit in the [`IE0`](../data/rv_plic.hjson#ie0) registers controls the corresponding interrupt source. If an +interrupt source is disabled for a target, then interrupt events from that +source won't trigger an interrupt at the target. RV_PLIC doesn't have a global +interrupt disable feature. + +### Interrupt Claims + +"Claiming" an interrupt is done by a target reading the associated +Claim/Completion register for the target ([`CC0`](../data/rv_plic.hjson#cc0) for target 0). The return value +of the [`CC0`](../data/rv_plic.hjson#cc0) read represents the ID of the pending interrupt that has the +highest priority. If two or more pending interrupts have the same priority, +RV_PLIC chooses the one with lowest ID. Only interrupts that are enabled +for the target can be claimed. The target priority threshold doesn't matter +(this only factors into whether an interrupt is signalled to the target) so +lower priority interrupt IDs can be returned on a read from [`CC0`](../data/rv_plic.hjson#cc0). If no +interrupt is pending (or all pending interrupts are disabled for the target) a +read of [`CC0`](../data/rv_plic.hjson#cc0) returns an ID of 0. + +### Interrupt Completion + +After an interrupt is claimed, the relevant bit of interrupt pending ([`IP`](../data/rv_plic.hjson#ip)) is +cleared, regardless of the status of the `intr_src_i` input value. Until a +target "completes" the interrupt, it won't be re-asserted if a new event for the +interrupt occurs. A target completes the interrupt by writing the ID of the +interrupt to the Claim/Complete register ([`CC0`](../data/rv_plic.hjson#cc0) for target 0). The write event +is forwarded to the Gateway logic, which resets the interrupt status to accept a +new interrupt event. The assumption is that the processor has cleaned up the +originating interrupt event during the time between claim and complete such that +`intr_src_i[ID]` will have de-asserted (unless a new interrupt has occurred). + +```wavejson +{ signal: [ + { name: 'clk', wave: 'p...........' }, + { name: 'intr_src_i[i]', wave: '01....0.1...', node:'.a....e.f...'}, + { name: 'irq_o', wave: '0.1.0......1', node:'..b.d......h'}, + { name: 'irq_id_o', wave: '=.=.=......=', + data: ["0","i","0","i"] }, + { name: 'claim', wave: '0..10.......', node:'...c........'}, + { name: 'complete', wave: '0.........10', node:'..........g.'}, + ], + head:{ + text: 'Interrupt Flow', + tick: 0, + }, +} +``` + +In the example above an interrupt for source ID `i` is configured as a level +interrupt and is raised at a, this results in the target being notified of the +interrupt at b. The target claims the interrupt at c (reading `i` from it's +Claim/Complete register) so `irq_o` deasserts though `intr_src_i[i]` remains +raised. The SW handles the interrupt and it drops at e. However a new interrupt +quickly occurs at f. As complete hasn't been signaled yet `irq_o` isn't +asserted. At g the interrupt is completed (by writing `i` to it's +Claim/Complete register) so at h `irq_o` is asserted due to the new interrupt. diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/fpv/rv_plic_expected_failure.hjson b/hw/top_darjeeling/ip_autogen/rv_plic/fpv/rv_plic_expected_failure.hjson new file mode 100644 index 0000000000000..e77d6989e7b07 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/fpv/rv_plic_expected_failure.hjson @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +{ + unreachable: + [ + rv_plic_tb.dut.FpvSecCmRegWeOnehotCheck_A:precondition1 + rv_plic_tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.Onehot0Check_A:precondition1 + rv_plic_tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.gen_enable_check.gen_not_strict.EnableCheck_A:precondition1 + ] +} diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/fpv/rv_plic_fpv.core b/hw/top_darjeeling/ip_autogen/rv_plic/fpv/rv_plic_fpv.core new file mode 100644 index 0000000000000..7d7642b5d1ea5 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/fpv/rv_plic_fpv.core @@ -0,0 +1,44 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_rv_plic_fpv:0.1 +description: "FPV for RISC-V PLIC" + +filesets: + files_formal: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:all + - lowrisc:opentitan:top_darjeeling_rv_plic + - lowrisc:fpv:csr_assert_gen + files: + - tb/rv_plic_bind_fpv.sv + - tb/rv_plic_tb.sv + - vip/rv_plic_assert_fpv.sv + file_type: systemVerilogSource + + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../data/rv_plic.hjson + depend: lowrisc:opentitan:top_darjeeling_rv_plic + +targets: + default: &default_target + # note, this setting is just used + # to generate a file list for jg + default_tool: icarus + filesets: + - files_formal + generate: + - csr_assert_gen + toplevel: rv_plic_tb + + formal: + <<: *default_target + + lint: + <<: *default_target diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/fpv/tb/rv_plic_bind_fpv.sv b/hw/top_darjeeling/ip_autogen/rv_plic/fpv/tb/rv_plic_bind_fpv.sv new file mode 100644 index 0000000000000..cfe6c847bda16 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/fpv/tb/rv_plic_bind_fpv.sv @@ -0,0 +1,47 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module rv_plic_bind_fpv; + + import rv_plic_reg_pkg::*; + + bind rv_plic rv_plic_assert_fpv #( + .NumSrc(rv_plic_reg_pkg::NumSrc), + .NumTarget(rv_plic_reg_pkg::NumTarget), + .NumAlerts(rv_plic_reg_pkg::NumAlerts), + .PRIOW(rv_plic_reg_pkg::PrioWidth) + ) rv_plic_assert_fpv( + .clk_i, + .rst_ni, + .intr_src_i, + .alert_rx_i, + .alert_tx_o, + .irq_o, + .irq_id_o, + .msip_o, + .ip, + .ie, + .claim, + .complete, + .prio, + .threshold + ); + + bind rv_plic tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + + bind rv_plic rv_plic_csr_assert_fpv rv_plic_csr_assert_fpv ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + +endmodule : rv_plic_bind_fpv diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv b/hw/top_darjeeling/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv new file mode 100644 index 0000000000000..8a64257766d71 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv @@ -0,0 +1,40 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Testbench module for rv_plic. Intended to use with a formal tool. + +module rv_plic_tb import rv_plic_reg_pkg::*; #( + // test all implementations + localparam int unsigned NumInstances = 1 +) ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t [NumInstances-1:0] tl_i, + output tlul_pkg::tl_d2h_t [NumInstances-1:0] tl_o, + input [NumInstances-1:0][NumSrc-1:0] intr_src_i, + input prim_alert_pkg::alert_rx_t [NumInstances-1:0][NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumInstances-1:0][NumAlerts-1:0] alert_tx_o, + output [NumInstances-1:0][NumTarget-1:0] irq_o, + output [$clog2(NumSrc)-1:0] irq_id_o [NumInstances][NumTarget], + output logic [NumInstances-1:0][NumTarget-1:0] msip_o +); + + // TODO: once the PLIC is fully parameterizable in RTL, generate + // several instances with different NumSrc and NumTarget configs here + // (in a similar way as this has been done in prim_lfsr_fpv) + // for (genvar k = 0; k < NumInstances; k++) begin : geNumInstances + rv_plic dut ( + .clk_i , + .rst_ni , + .tl_i (tl_i[0]), + .tl_o (tl_o[0]), + .intr_src_i (intr_src_i[0]), + .alert_rx_i (alert_rx_i[0]), + .alert_tx_o (alert_tx_o[0]), + .irq_o (irq_o[0]), + .irq_id_o (irq_id_o[0]), + .msip_o (msip_o[0]) + ); + +endmodule : rv_plic_tb diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/fpv/vip/rv_plic_assert_fpv.sv b/hw/top_darjeeling/ip_autogen/rv_plic/fpv/vip/rv_plic_assert_fpv.sv new file mode 100644 index 0000000000000..fb09709fe0bcf --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/fpv/vip/rv_plic_assert_fpv.sv @@ -0,0 +1,107 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Testbench module for rv_plic. Intended to use with a formal tool. + +`include "prim_assert.sv" + +module rv_plic_assert_fpv #(parameter int NumSrc = 1, + parameter int NumTarget = 1, + parameter int NumAlerts = 1, + parameter int PRIOW = $clog2(7+1) +) ( + input clk_i, + input rst_ni, + input [NumSrc-1:0] intr_src_i, + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + input prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + input [NumTarget-1:0] irq_o, + input [$clog2(NumSrc)-1:0] irq_id_o [NumTarget], + input [NumTarget-1:0] msip_o, + // probe design signals + input [NumSrc-1:0] ip, + input [NumSrc-1:0] ie [NumTarget], + input [NumSrc-1:0] claim, + input [NumSrc-1:0] complete, + input [NumSrc-1:0][PRIOW-1:0] prio, + input [PRIOW-1:0] threshold [NumTarget] +); + + localparam int SrcIdxWidth = NumSrc > 1 ? $clog2(NumSrc - 1) : 1; + localparam int TgtIdxWidth = NumTarget > 1 ? $clog2(NumTarget - 1) : 1; + + logic claim_reg, claimed; + logic max_priority; + logic irq; + logic [$clog2(NumSrc)-1:0] i_high_prio; + + // symbolic variables + bit [SrcIdxWidth-1:0] src_sel; + bit [TgtIdxWidth-1:0] tgt_sel; + + `ASSUME_FPV(IsrcRange_M, src_sel > 0 && src_sel < NumSrc, clk_i, !rst_ni) + `ASSUME_FPV(ItgtRange_M, tgt_sel >= 0 && tgt_sel < NumTarget, clk_i, !rst_ni) + `ASSUME_FPV(IsrcStable_M, ##1 $stable(src_sel), clk_i, !rst_ni) + `ASSUME_FPV(ItgtStable_M, ##1 $stable(tgt_sel), clk_i, !rst_ni) + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + claim_reg <= 1'b0; + end else if (claim[src_sel]) begin + claim_reg <= 1'b1; + end else if (complete[src_sel]) begin + claim_reg <= 1'b0; + end + end + + assign claimed = claim_reg || claim[src_sel]; + + always_comb begin + max_priority = 1'b1; + for (int i = 0; i < NumSrc; i++) begin + // conditions that if src_sel has the highest priority with the lowest ID + if (i != src_sel && ip[i] && ie[tgt_sel][i] && + (prio[i] > prio[src_sel] || (prio[i] == prio[src_sel] && i < src_sel))) begin + max_priority = 1'b0; + break; + end + end + end + + always_comb begin + automatic logic [31:0] max_prio = 0; + for (int i = NumSrc-1; i >= 0; i--) begin + if (ip[i] && ie[tgt_sel][i] && prio[i] >= max_prio) begin + max_prio = prio[i]; + i_high_prio = i; // i is the smallest id if have IPs with the same priority + end + end + if (max_prio > threshold[tgt_sel]) irq = 1'b1; + else irq = 1'b0; + end + + // when IP is set, previous cycle should follow edge or level triggered criteria + `ASSERT(LevelTriggeredIp_A, ##3 $rose(ip[src_sel]) |-> $past(intr_src_i[src_sel], 3)) + + // when interrupt is trigger, and nothing claimed yet, then next cycle should assert IP. + `ASSERT(LevelTriggeredIpWithClaim_A, ##2 $past(intr_src_i[src_sel], 2) && + !claimed |=> ip[src_sel]) + + // ip stays stable until claimed, reset to 0 after claimed, and stays 0 until complete + `ASSERT(IpStableAfterTriggered_A, ip[src_sel] && !claimed |=> ip[src_sel]) + `ASSERT(IpClearAfterClaim_A, ip[src_sel] && claim[src_sel] |=> !ip[src_sel]) + `ASSERT(IpStableAfterClaimed_A, claimed |=> !ip[src_sel]) + + // when ip is set and priority is the largest and above threshold, and interrupt enable is set, + // assertion irq_o at next cycle + `ASSERT(TriggerIrqForwardCheck_A, ip[src_sel] && prio[src_sel] > threshold[tgt_sel] && + max_priority && ie[tgt_sel][src_sel] |=> irq_o[tgt_sel]) + + `ASSERT(TriggerIrqBackwardCheck_A, $rose(irq_o[tgt_sel]) |-> + $past(irq) && (irq_id_o[tgt_sel] == $past(i_high_prio))) + + // when irq ID changed, but not to ID=0, irq_o should be high, or irq represents the largest prio + // but smaller than the threshold + `ASSERT(IdChangeWithIrq_A, !$stable(irq_id_o[tgt_sel]) && irq_id_o[tgt_sel] != 0 |-> + irq_o[tgt_sel] || ((irq_id_o[tgt_sel]) == $past(i_high_prio) && !$past(irq))) +endmodule : rv_plic_assert_fpv diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/lint/rv_plic.vlt b/hw/top_darjeeling/ip_autogen/rv_plic/lint/rv_plic.vlt new file mode 100644 index 0000000000000..f9318e609c6c4 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/lint/rv_plic.vlt @@ -0,0 +1,7 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for rv_plic + +`verilator_config diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/lint/rv_plic.waiver b/hw/top_darjeeling/ip_autogen/rv_plic/lint/rv_plic.waiver new file mode 100644 index 0000000000000..9e84bd9021205 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/lint/rv_plic.waiver @@ -0,0 +1,22 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for Platform-Level Interrupt Controller + +waive -rules ONE_BIT_MEM_WIDTH -location {rv_plic.sv} -regexp {Memory '(claim_re|complete_we)' has} \ + -comment "N_TARGET can be 1." + +waive -rules VAR_INDEX_RANGE -location {rv_plic.sv} -regexp {(claim_id|complete_id).* (maximum|minimum) value} \ + -comment "Claim ID is guarded inside target module, complete ID has undeterministic behavior if FW writes OOR value" + +waive -rules HIER_NET_NOT_READ -location {rv_plic.sv} -regexp {[Nn]et 'tl_[io]\.[ad]_(address|param|user)} \ + -comment "Register interface doesn't use upper address and param, user filed" + +waive -rules EXPLICIT_BITLEN -location {rv_plic_target.sv} -regexp {Bit length .* '1'} \ + -comment "i + 1 is assumed as constant and guarded by SRCW" +waive -rules INTEGER -location {rv_plic_target.sv} -regexp {'i' of type int used as} \ + -comment "int i is static and only assigned to irq_id_next when it hits condition" + +waive -rules TWOS_COMP -location {rv_plic_target.sv} -regexp {Explicit two's complement with terms} \ + -comment "This is permissible in this context" diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic.sv b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic.sv new file mode 100644 index 0000000000000..26cde5cdf5594 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic.sv @@ -0,0 +1,434 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// RISC-V Platform-Level Interrupt Controller compliant INTC +// +// Current version doesn't support MSI interrupt but it is easy to add +// the feature. Create one external register and connect qe signal to the +// gateway module (as edge-triggered) +// +// Consider to set MAX_PRIO as small number as possible. It is main factor +// of area increase if edge-triggered counter isn't implemented. +// +// Verilog parameter +// MAX_PRIO: Maximum value of interrupt priority + +`include "prim_assert.sv" + +module rv_plic import rv_plic_reg_pkg::*; #( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + // OpenTitan IP standardizes on level triggered interrupts, + // hence LevelEdgeTrig is set to all-zeroes by default. + // Note that in case of edge-triggered interrupts, CDC handling is not + // fully implemented yet (this would require instantiating pulse syncs + // and routing the source clocks / resets to the PLIC). + parameter logic [NumSrc-1:0] LevelEdgeTrig = '0, // 0: level, 1: edge + // derived parameter + localparam int SRCW = $clog2(NumSrc) +) ( + input clk_i, + input rst_ni, + + // Bus Interface (device) + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Interrupt Sources + input [NumSrc-1:0] intr_src_i, + + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + // Interrupt notification to targets + output [NumTarget-1:0] irq_o, + output [SRCW-1:0] irq_id_o [NumTarget], + + output logic [NumTarget-1:0] msip_o +); + + rv_plic_reg2hw_t reg2hw; + rv_plic_hw2reg_t hw2reg; + + localparam int MAX_PRIO = 3; + localparam int PRIOW = $clog2(MAX_PRIO+1); + + logic [NumSrc-1:0] ip; + + logic [NumSrc-1:0] ie [NumTarget]; + + logic [NumTarget-1:0] claim_re; // Target read indicator + logic [SRCW-1:0] claim_id [NumTarget]; + logic [NumSrc-1:0] claim; // Converted from claim_re/claim_id + + logic [NumTarget-1:0] complete_we; // Target write indicator + logic [SRCW-1:0] complete_id [NumTarget]; + logic [NumSrc-1:0] complete; // Converted from complete_re/complete_id + + logic [SRCW-1:0] cc_id [NumTarget]; // Write ID + + logic [NumSrc-1:0][PRIOW-1:0] prio; + + logic [PRIOW-1:0] threshold [NumTarget]; + + // Glue logic between rv_plic_reg_top and others + assign cc_id = irq_id_o; + + always_comb begin + claim = '0; + for (int i = 0 ; i < NumTarget ; i++) begin + if (claim_re[i]) claim[claim_id[i]] = 1'b1; + end + end + always_comb begin + complete = '0; + for (int i = 0 ; i < NumTarget ; i++) begin + if (complete_we[i]) complete[complete_id[i]] = 1'b1; + end + end + + //`ASSERT_PULSE(claimPulse, claim_re[i]) + //`ASSERT_PULSE(completePulse, complete_we[i]) + + `ASSERT(onehot0Claim, $onehot0(claim_re)) + + `ASSERT(onehot0Complete, $onehot0(complete_we)) + + ////////////// + // Priority // + ////////////// + assign prio[0] = reg2hw.prio0.q; + assign prio[1] = reg2hw.prio1.q; + assign prio[2] = reg2hw.prio2.q; + assign prio[3] = reg2hw.prio3.q; + assign prio[4] = reg2hw.prio4.q; + assign prio[5] = reg2hw.prio5.q; + assign prio[6] = reg2hw.prio6.q; + assign prio[7] = reg2hw.prio7.q; + assign prio[8] = reg2hw.prio8.q; + assign prio[9] = reg2hw.prio9.q; + assign prio[10] = reg2hw.prio10.q; + assign prio[11] = reg2hw.prio11.q; + assign prio[12] = reg2hw.prio12.q; + assign prio[13] = reg2hw.prio13.q; + assign prio[14] = reg2hw.prio14.q; + assign prio[15] = reg2hw.prio15.q; + assign prio[16] = reg2hw.prio16.q; + assign prio[17] = reg2hw.prio17.q; + assign prio[18] = reg2hw.prio18.q; + assign prio[19] = reg2hw.prio19.q; + assign prio[20] = reg2hw.prio20.q; + assign prio[21] = reg2hw.prio21.q; + assign prio[22] = reg2hw.prio22.q; + assign prio[23] = reg2hw.prio23.q; + assign prio[24] = reg2hw.prio24.q; + assign prio[25] = reg2hw.prio25.q; + assign prio[26] = reg2hw.prio26.q; + assign prio[27] = reg2hw.prio27.q; + assign prio[28] = reg2hw.prio28.q; + assign prio[29] = reg2hw.prio29.q; + assign prio[30] = reg2hw.prio30.q; + assign prio[31] = reg2hw.prio31.q; + assign prio[32] = reg2hw.prio32.q; + assign prio[33] = reg2hw.prio33.q; + assign prio[34] = reg2hw.prio34.q; + assign prio[35] = reg2hw.prio35.q; + assign prio[36] = reg2hw.prio36.q; + assign prio[37] = reg2hw.prio37.q; + assign prio[38] = reg2hw.prio38.q; + assign prio[39] = reg2hw.prio39.q; + assign prio[40] = reg2hw.prio40.q; + assign prio[41] = reg2hw.prio41.q; + assign prio[42] = reg2hw.prio42.q; + assign prio[43] = reg2hw.prio43.q; + assign prio[44] = reg2hw.prio44.q; + assign prio[45] = reg2hw.prio45.q; + assign prio[46] = reg2hw.prio46.q; + assign prio[47] = reg2hw.prio47.q; + assign prio[48] = reg2hw.prio48.q; + assign prio[49] = reg2hw.prio49.q; + assign prio[50] = reg2hw.prio50.q; + assign prio[51] = reg2hw.prio51.q; + assign prio[52] = reg2hw.prio52.q; + assign prio[53] = reg2hw.prio53.q; + assign prio[54] = reg2hw.prio54.q; + assign prio[55] = reg2hw.prio55.q; + assign prio[56] = reg2hw.prio56.q; + assign prio[57] = reg2hw.prio57.q; + assign prio[58] = reg2hw.prio58.q; + assign prio[59] = reg2hw.prio59.q; + assign prio[60] = reg2hw.prio60.q; + assign prio[61] = reg2hw.prio61.q; + assign prio[62] = reg2hw.prio62.q; + assign prio[63] = reg2hw.prio63.q; + assign prio[64] = reg2hw.prio64.q; + assign prio[65] = reg2hw.prio65.q; + assign prio[66] = reg2hw.prio66.q; + assign prio[67] = reg2hw.prio67.q; + assign prio[68] = reg2hw.prio68.q; + assign prio[69] = reg2hw.prio69.q; + assign prio[70] = reg2hw.prio70.q; + assign prio[71] = reg2hw.prio71.q; + assign prio[72] = reg2hw.prio72.q; + assign prio[73] = reg2hw.prio73.q; + assign prio[74] = reg2hw.prio74.q; + assign prio[75] = reg2hw.prio75.q; + assign prio[76] = reg2hw.prio76.q; + assign prio[77] = reg2hw.prio77.q; + assign prio[78] = reg2hw.prio78.q; + assign prio[79] = reg2hw.prio79.q; + assign prio[80] = reg2hw.prio80.q; + assign prio[81] = reg2hw.prio81.q; + assign prio[82] = reg2hw.prio82.q; + assign prio[83] = reg2hw.prio83.q; + assign prio[84] = reg2hw.prio84.q; + assign prio[85] = reg2hw.prio85.q; + assign prio[86] = reg2hw.prio86.q; + assign prio[87] = reg2hw.prio87.q; + assign prio[88] = reg2hw.prio88.q; + assign prio[89] = reg2hw.prio89.q; + assign prio[90] = reg2hw.prio90.q; + assign prio[91] = reg2hw.prio91.q; + assign prio[92] = reg2hw.prio92.q; + assign prio[93] = reg2hw.prio93.q; + assign prio[94] = reg2hw.prio94.q; + assign prio[95] = reg2hw.prio95.q; + assign prio[96] = reg2hw.prio96.q; + assign prio[97] = reg2hw.prio97.q; + assign prio[98] = reg2hw.prio98.q; + assign prio[99] = reg2hw.prio99.q; + assign prio[100] = reg2hw.prio100.q; + assign prio[101] = reg2hw.prio101.q; + assign prio[102] = reg2hw.prio102.q; + assign prio[103] = reg2hw.prio103.q; + assign prio[104] = reg2hw.prio104.q; + assign prio[105] = reg2hw.prio105.q; + assign prio[106] = reg2hw.prio106.q; + assign prio[107] = reg2hw.prio107.q; + assign prio[108] = reg2hw.prio108.q; + assign prio[109] = reg2hw.prio109.q; + assign prio[110] = reg2hw.prio110.q; + assign prio[111] = reg2hw.prio111.q; + assign prio[112] = reg2hw.prio112.q; + assign prio[113] = reg2hw.prio113.q; + assign prio[114] = reg2hw.prio114.q; + assign prio[115] = reg2hw.prio115.q; + assign prio[116] = reg2hw.prio116.q; + assign prio[117] = reg2hw.prio117.q; + assign prio[118] = reg2hw.prio118.q; + assign prio[119] = reg2hw.prio119.q; + assign prio[120] = reg2hw.prio120.q; + assign prio[121] = reg2hw.prio121.q; + assign prio[122] = reg2hw.prio122.q; + assign prio[123] = reg2hw.prio123.q; + assign prio[124] = reg2hw.prio124.q; + assign prio[125] = reg2hw.prio125.q; + assign prio[126] = reg2hw.prio126.q; + assign prio[127] = reg2hw.prio127.q; + assign prio[128] = reg2hw.prio128.q; + assign prio[129] = reg2hw.prio129.q; + assign prio[130] = reg2hw.prio130.q; + assign prio[131] = reg2hw.prio131.q; + assign prio[132] = reg2hw.prio132.q; + assign prio[133] = reg2hw.prio133.q; + assign prio[134] = reg2hw.prio134.q; + assign prio[135] = reg2hw.prio135.q; + assign prio[136] = reg2hw.prio136.q; + assign prio[137] = reg2hw.prio137.q; + assign prio[138] = reg2hw.prio138.q; + assign prio[139] = reg2hw.prio139.q; + assign prio[140] = reg2hw.prio140.q; + assign prio[141] = reg2hw.prio141.q; + assign prio[142] = reg2hw.prio142.q; + assign prio[143] = reg2hw.prio143.q; + assign prio[144] = reg2hw.prio144.q; + assign prio[145] = reg2hw.prio145.q; + assign prio[146] = reg2hw.prio146.q; + assign prio[147] = reg2hw.prio147.q; + assign prio[148] = reg2hw.prio148.q; + assign prio[149] = reg2hw.prio149.q; + assign prio[150] = reg2hw.prio150.q; + assign prio[151] = reg2hw.prio151.q; + assign prio[152] = reg2hw.prio152.q; + assign prio[153] = reg2hw.prio153.q; + assign prio[154] = reg2hw.prio154.q; + assign prio[155] = reg2hw.prio155.q; + assign prio[156] = reg2hw.prio156.q; + assign prio[157] = reg2hw.prio157.q; + assign prio[158] = reg2hw.prio158.q; + assign prio[159] = reg2hw.prio159.q; + + ////////////////////// + // Interrupt Enable // + ////////////////////// + for (genvar s = 0; s < 160; s++) begin : gen_ie0 + assign ie[0][s] = reg2hw.ie0[s].q; + end + + //////////////////////// + // THRESHOLD register // + //////////////////////// + assign threshold[0] = reg2hw.threshold0.q; + + ///////////////// + // CC register // + ///////////////// + assign claim_re[0] = reg2hw.cc0.re; + assign claim_id[0] = irq_id_o[0]; + assign complete_we[0] = reg2hw.cc0.qe; + assign complete_id[0] = reg2hw.cc0.q; + assign hw2reg.cc0.d = cc_id[0]; + + /////////////////// + // MSIP register // + /////////////////// + assign msip_o[0] = reg2hw.msip0.q; + + //////// + // IP // + //////// + for (genvar s = 0; s < 160; s++) begin : gen_ip + assign hw2reg.ip[s].de = 1'b1; // Always write + assign hw2reg.ip[s].d = ip[s]; + end + + ////////////// + // Gateways // + ////////////// + + // Synchronize all incoming interrupt requests. + logic [NumSrc-1:0] intr_src_synced; + prim_flop_2sync #( + .Width(NumSrc) + ) u_prim_flop_2sync ( + .clk_i, + .rst_ni, + .d_i(intr_src_i), + .q_o(intr_src_synced) + ); + + rv_plic_gateway #( + .N_SOURCE (NumSrc) + ) u_gateway ( + .clk_i, + .rst_ni, + + .src_i (intr_src_synced), + .le_i (LevelEdgeTrig), + + .claim_i (claim), + .complete_i (complete), + + .ip_o (ip) + ); + + /////////////////////////////////// + // Target interrupt notification // + /////////////////////////////////// + for (genvar i = 0 ; i < NumTarget ; i++) begin : gen_target + rv_plic_target #( + .N_SOURCE (NumSrc), + .MAX_PRIO (MAX_PRIO) + ) u_target ( + .clk_i, + .rst_ni, + + .ip_i (ip), + .ie_i (ie[i]), + + .prio_i (prio), + .threshold_i (threshold[i]), + + .irq_o (irq_o[i]), + .irq_id_o (irq_id_o[i]) + + ); + end + + //////////// + // Alerts // + //////////// + + logic [NumAlerts-1:0] alert_test, alerts; + + assign alert_test = { + reg2hw.alert_test.q & + reg2hw.alert_test.qe + }; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .IsFatal(1'b1) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[i] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + //////////////////////// + // Register interface // + //////////////////////// + // Limitation of register tool prevents the module from having flexibility to parameters + // So, signals are manually tied at the top. + rv_plic_reg_top u_reg ( + .clk_i, + .rst_ni, + + .tl_i, + .tl_o, + + .reg2hw, + .hw2reg, + + // SEC_CM: BUS.INTEGRITY + .intg_err_o(alerts[0]) + ); + + // Assertions + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready) + `ASSERT_KNOWN(IrqKnownO_A, irq_o) + `ASSERT_KNOWN(MsipKnownO_A, msip_o) + for (genvar k = 0; k < NumTarget; k++) begin : gen_irq_id_known + `ASSERT_KNOWN(IrqIdKnownO_A, irq_id_o[k]) + end + + // Assume + `ASSUME(Irq0Tied_A, intr_src_i[0] == 1'b0) + + // This assertion should be provable in FPV because we don't have a block-level DV environment. It + // is trying to say that any integrity error detected inside the register block (u_reg) will cause + // an alert to be asserted within at most _SEC_CM_ALERT_MAX_CYC cycles. + // + // This isn't *quite* true because there are two extra requirements for prim_alert_sender to send + // an alert with alert_p high: + // + // - The multi-phase alert handshake might not be in the expected phase. Rather than adding an + // assumption that says alert_rx_i acks a signal when it is raised, we cheat and add a + // precondition about the initial state of the prim_alert_sender FSM, guaranteeing that we're + // not waiting for an ack. + // + // - The prim_alert_sender musn't detect a signal integrity issue on the alert signal coming in + // (alert_rx_i). Normally FpvSecCm tests get analysed with an FPV_ALERT_NO_SIGINT_ERR define, + // but we don't have that defined here. To avoid this happening, we want an assertion of the + // form "If no integrity error is detected for _SEC_CM_ALERT_MAX_CYC cycles, the alert_p signal + // must go high". To encode this cleanly in SVA, we actually say "We can't have neither an + // integrity error nor an alert signal for too many cycles". + `ASSERT(FpvSecCmBusIntegrity_A, + ($rose(u_reg.intg_err) && + gen_alert_tx[0].u_prim_alert_sender.state_q == gen_alert_tx[0].u_prim_alert_sender.Idle) + |-> + not ((!gen_alert_tx[0].u_prim_alert_sender.sigint_detected && !alert_tx_o[0].alert_p) + [*`_SEC_CM_ALERT_MAX_CYC])) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0]) +endmodule diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_gateway.sv b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_gateway.sv new file mode 100644 index 0000000000000..aed8d4c9ad2ff --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_gateway.sv @@ -0,0 +1,62 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// RISC-V Platform-Level Interrupt Gateways module + +module rv_plic_gateway #( + parameter int N_SOURCE = 32 +) ( + input clk_i, + input rst_ni, + + input [N_SOURCE-1:0] src_i, + input [N_SOURCE-1:0] le_i, // Level0 Edge1 + + input [N_SOURCE-1:0] claim_i, // $onehot0(claim_i) + input [N_SOURCE-1:0] complete_i, // $onehot0(complete_i) + + output logic [N_SOURCE-1:0] ip_o +); + + logic [N_SOURCE-1:0] ia; // Interrupt Active + + logic [N_SOURCE-1:0] set; // Set: (le_i) ? src_i & ~src_q : src_i ; + logic [N_SOURCE-1:0] src_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) src_q <= '0; + else src_q <= src_i; + end + + always_comb begin + for (int i = 0 ; i < N_SOURCE; i++) begin + set[i] = (le_i[i]) ? src_i[i] & ~src_q[i] : src_i[i] ; + end + end + + // Interrupt pending is set by source (depends on le_i), cleared by claim_i. + // Until interrupt is claimed, set doesn't affect ip_o. + // RISC-V PLIC spec mentioned it can have counter for edge triggered + // But skipped the feature as counter consumes substantial logic size. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + ip_o <= '0; + end else begin + ip_o <= (ip_o | (set & ~ia & ~ip_o)) & (~(ip_o & claim_i)); + end + end + + // Interrupt active is to control ip_o. If ip_o is set then until completed + // by target, ip_o shouldn't be set by source even claim_i can clear ip_o. + // ia can be cleared only when ia was set. If `set` and `complete_i` happen + // at the same time, always `set` wins. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + ia <= '0; + end else begin + ia <= (ia | (set & ~ia)) & (~(ia & complete_i & ~ip_o)); + end + end + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv new file mode 100644 index 0000000000000..177c88d2abd14 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv @@ -0,0 +1,1405 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package rv_plic_reg_pkg; + + // Param list + parameter int NumSrc = 160; + parameter int NumTarget = 1; + parameter int PrioWidth = 2; + parameter int NumAlerts = 1; + + // Address widths within the block + parameter int BlockAw = 27; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio0_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio1_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio2_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio3_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio4_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio5_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio6_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio7_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio8_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio9_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio10_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio11_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio12_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio13_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio14_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio15_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio16_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio17_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio18_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio19_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio20_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio21_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio22_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio23_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio24_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio25_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio26_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio27_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio28_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio29_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio30_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio31_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio32_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio33_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio34_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio35_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio36_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio37_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio38_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio39_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio40_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio41_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio42_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio43_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio44_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio45_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio46_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio47_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio48_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio49_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio50_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio51_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio52_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio53_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio54_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio55_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio56_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio57_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio58_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio59_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio60_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio61_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio62_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio63_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio64_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio65_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio66_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio67_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio68_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio69_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio70_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio71_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio72_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio73_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio74_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio75_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio76_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio77_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio78_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio79_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio80_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio81_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio82_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio83_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio84_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio85_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio86_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio87_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio88_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio89_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio90_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio91_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio92_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio93_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio94_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio95_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio96_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio97_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio98_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio99_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio100_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio101_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio102_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio103_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio104_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio105_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio106_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio107_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio108_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio109_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio110_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio111_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio112_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio113_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio114_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio115_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio116_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio117_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio118_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio119_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio120_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio121_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio122_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio123_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio124_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio125_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio126_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio127_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio128_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio129_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio130_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio131_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio132_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio133_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio134_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio135_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio136_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio137_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio138_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio139_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio140_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio141_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio142_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio143_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio144_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio145_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio146_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio147_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio148_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio149_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio150_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio151_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio152_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio153_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio154_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio155_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio156_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio157_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio158_reg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio159_reg_t; + + typedef struct packed { + logic q; + } rv_plic_reg2hw_ie0_mreg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_threshold0_reg_t; + + typedef struct packed { + logic [7:0] q; + logic qe; + logic re; + } rv_plic_reg2hw_cc0_reg_t; + + typedef struct packed { + logic q; + } rv_plic_reg2hw_msip0_reg_t; + + typedef struct packed { + logic q; + logic qe; + } rv_plic_reg2hw_alert_test_reg_t; + + typedef struct packed { + logic d; + logic de; + } rv_plic_hw2reg_ip_mreg_t; + + typedef struct packed { + logic [7:0] d; + } rv_plic_hw2reg_cc0_reg_t; + + // Register -> HW type + typedef struct packed { + rv_plic_reg2hw_prio0_reg_t prio0; // [494:493] + rv_plic_reg2hw_prio1_reg_t prio1; // [492:491] + rv_plic_reg2hw_prio2_reg_t prio2; // [490:489] + rv_plic_reg2hw_prio3_reg_t prio3; // [488:487] + rv_plic_reg2hw_prio4_reg_t prio4; // [486:485] + rv_plic_reg2hw_prio5_reg_t prio5; // [484:483] + rv_plic_reg2hw_prio6_reg_t prio6; // [482:481] + rv_plic_reg2hw_prio7_reg_t prio7; // [480:479] + rv_plic_reg2hw_prio8_reg_t prio8; // [478:477] + rv_plic_reg2hw_prio9_reg_t prio9; // [476:475] + rv_plic_reg2hw_prio10_reg_t prio10; // [474:473] + rv_plic_reg2hw_prio11_reg_t prio11; // [472:471] + rv_plic_reg2hw_prio12_reg_t prio12; // [470:469] + rv_plic_reg2hw_prio13_reg_t prio13; // [468:467] + rv_plic_reg2hw_prio14_reg_t prio14; // [466:465] + rv_plic_reg2hw_prio15_reg_t prio15; // [464:463] + rv_plic_reg2hw_prio16_reg_t prio16; // [462:461] + rv_plic_reg2hw_prio17_reg_t prio17; // [460:459] + rv_plic_reg2hw_prio18_reg_t prio18; // [458:457] + rv_plic_reg2hw_prio19_reg_t prio19; // [456:455] + rv_plic_reg2hw_prio20_reg_t prio20; // [454:453] + rv_plic_reg2hw_prio21_reg_t prio21; // [452:451] + rv_plic_reg2hw_prio22_reg_t prio22; // [450:449] + rv_plic_reg2hw_prio23_reg_t prio23; // [448:447] + rv_plic_reg2hw_prio24_reg_t prio24; // [446:445] + rv_plic_reg2hw_prio25_reg_t prio25; // [444:443] + rv_plic_reg2hw_prio26_reg_t prio26; // [442:441] + rv_plic_reg2hw_prio27_reg_t prio27; // [440:439] + rv_plic_reg2hw_prio28_reg_t prio28; // [438:437] + rv_plic_reg2hw_prio29_reg_t prio29; // [436:435] + rv_plic_reg2hw_prio30_reg_t prio30; // [434:433] + rv_plic_reg2hw_prio31_reg_t prio31; // [432:431] + rv_plic_reg2hw_prio32_reg_t prio32; // [430:429] + rv_plic_reg2hw_prio33_reg_t prio33; // [428:427] + rv_plic_reg2hw_prio34_reg_t prio34; // [426:425] + rv_plic_reg2hw_prio35_reg_t prio35; // [424:423] + rv_plic_reg2hw_prio36_reg_t prio36; // [422:421] + rv_plic_reg2hw_prio37_reg_t prio37; // [420:419] + rv_plic_reg2hw_prio38_reg_t prio38; // [418:417] + rv_plic_reg2hw_prio39_reg_t prio39; // [416:415] + rv_plic_reg2hw_prio40_reg_t prio40; // [414:413] + rv_plic_reg2hw_prio41_reg_t prio41; // [412:411] + rv_plic_reg2hw_prio42_reg_t prio42; // [410:409] + rv_plic_reg2hw_prio43_reg_t prio43; // [408:407] + rv_plic_reg2hw_prio44_reg_t prio44; // [406:405] + rv_plic_reg2hw_prio45_reg_t prio45; // [404:403] + rv_plic_reg2hw_prio46_reg_t prio46; // [402:401] + rv_plic_reg2hw_prio47_reg_t prio47; // [400:399] + rv_plic_reg2hw_prio48_reg_t prio48; // [398:397] + rv_plic_reg2hw_prio49_reg_t prio49; // [396:395] + rv_plic_reg2hw_prio50_reg_t prio50; // [394:393] + rv_plic_reg2hw_prio51_reg_t prio51; // [392:391] + rv_plic_reg2hw_prio52_reg_t prio52; // [390:389] + rv_plic_reg2hw_prio53_reg_t prio53; // [388:387] + rv_plic_reg2hw_prio54_reg_t prio54; // [386:385] + rv_plic_reg2hw_prio55_reg_t prio55; // [384:383] + rv_plic_reg2hw_prio56_reg_t prio56; // [382:381] + rv_plic_reg2hw_prio57_reg_t prio57; // [380:379] + rv_plic_reg2hw_prio58_reg_t prio58; // [378:377] + rv_plic_reg2hw_prio59_reg_t prio59; // [376:375] + rv_plic_reg2hw_prio60_reg_t prio60; // [374:373] + rv_plic_reg2hw_prio61_reg_t prio61; // [372:371] + rv_plic_reg2hw_prio62_reg_t prio62; // [370:369] + rv_plic_reg2hw_prio63_reg_t prio63; // [368:367] + rv_plic_reg2hw_prio64_reg_t prio64; // [366:365] + rv_plic_reg2hw_prio65_reg_t prio65; // [364:363] + rv_plic_reg2hw_prio66_reg_t prio66; // [362:361] + rv_plic_reg2hw_prio67_reg_t prio67; // [360:359] + rv_plic_reg2hw_prio68_reg_t prio68; // [358:357] + rv_plic_reg2hw_prio69_reg_t prio69; // [356:355] + rv_plic_reg2hw_prio70_reg_t prio70; // [354:353] + rv_plic_reg2hw_prio71_reg_t prio71; // [352:351] + rv_plic_reg2hw_prio72_reg_t prio72; // [350:349] + rv_plic_reg2hw_prio73_reg_t prio73; // [348:347] + rv_plic_reg2hw_prio74_reg_t prio74; // [346:345] + rv_plic_reg2hw_prio75_reg_t prio75; // [344:343] + rv_plic_reg2hw_prio76_reg_t prio76; // [342:341] + rv_plic_reg2hw_prio77_reg_t prio77; // [340:339] + rv_plic_reg2hw_prio78_reg_t prio78; // [338:337] + rv_plic_reg2hw_prio79_reg_t prio79; // [336:335] + rv_plic_reg2hw_prio80_reg_t prio80; // [334:333] + rv_plic_reg2hw_prio81_reg_t prio81; // [332:331] + rv_plic_reg2hw_prio82_reg_t prio82; // [330:329] + rv_plic_reg2hw_prio83_reg_t prio83; // [328:327] + rv_plic_reg2hw_prio84_reg_t prio84; // [326:325] + rv_plic_reg2hw_prio85_reg_t prio85; // [324:323] + rv_plic_reg2hw_prio86_reg_t prio86; // [322:321] + rv_plic_reg2hw_prio87_reg_t prio87; // [320:319] + rv_plic_reg2hw_prio88_reg_t prio88; // [318:317] + rv_plic_reg2hw_prio89_reg_t prio89; // [316:315] + rv_plic_reg2hw_prio90_reg_t prio90; // [314:313] + rv_plic_reg2hw_prio91_reg_t prio91; // [312:311] + rv_plic_reg2hw_prio92_reg_t prio92; // [310:309] + rv_plic_reg2hw_prio93_reg_t prio93; // [308:307] + rv_plic_reg2hw_prio94_reg_t prio94; // [306:305] + rv_plic_reg2hw_prio95_reg_t prio95; // [304:303] + rv_plic_reg2hw_prio96_reg_t prio96; // [302:301] + rv_plic_reg2hw_prio97_reg_t prio97; // [300:299] + rv_plic_reg2hw_prio98_reg_t prio98; // [298:297] + rv_plic_reg2hw_prio99_reg_t prio99; // [296:295] + rv_plic_reg2hw_prio100_reg_t prio100; // [294:293] + rv_plic_reg2hw_prio101_reg_t prio101; // [292:291] + rv_plic_reg2hw_prio102_reg_t prio102; // [290:289] + rv_plic_reg2hw_prio103_reg_t prio103; // [288:287] + rv_plic_reg2hw_prio104_reg_t prio104; // [286:285] + rv_plic_reg2hw_prio105_reg_t prio105; // [284:283] + rv_plic_reg2hw_prio106_reg_t prio106; // [282:281] + rv_plic_reg2hw_prio107_reg_t prio107; // [280:279] + rv_plic_reg2hw_prio108_reg_t prio108; // [278:277] + rv_plic_reg2hw_prio109_reg_t prio109; // [276:275] + rv_plic_reg2hw_prio110_reg_t prio110; // [274:273] + rv_plic_reg2hw_prio111_reg_t prio111; // [272:271] + rv_plic_reg2hw_prio112_reg_t prio112; // [270:269] + rv_plic_reg2hw_prio113_reg_t prio113; // [268:267] + rv_plic_reg2hw_prio114_reg_t prio114; // [266:265] + rv_plic_reg2hw_prio115_reg_t prio115; // [264:263] + rv_plic_reg2hw_prio116_reg_t prio116; // [262:261] + rv_plic_reg2hw_prio117_reg_t prio117; // [260:259] + rv_plic_reg2hw_prio118_reg_t prio118; // [258:257] + rv_plic_reg2hw_prio119_reg_t prio119; // [256:255] + rv_plic_reg2hw_prio120_reg_t prio120; // [254:253] + rv_plic_reg2hw_prio121_reg_t prio121; // [252:251] + rv_plic_reg2hw_prio122_reg_t prio122; // [250:249] + rv_plic_reg2hw_prio123_reg_t prio123; // [248:247] + rv_plic_reg2hw_prio124_reg_t prio124; // [246:245] + rv_plic_reg2hw_prio125_reg_t prio125; // [244:243] + rv_plic_reg2hw_prio126_reg_t prio126; // [242:241] + rv_plic_reg2hw_prio127_reg_t prio127; // [240:239] + rv_plic_reg2hw_prio128_reg_t prio128; // [238:237] + rv_plic_reg2hw_prio129_reg_t prio129; // [236:235] + rv_plic_reg2hw_prio130_reg_t prio130; // [234:233] + rv_plic_reg2hw_prio131_reg_t prio131; // [232:231] + rv_plic_reg2hw_prio132_reg_t prio132; // [230:229] + rv_plic_reg2hw_prio133_reg_t prio133; // [228:227] + rv_plic_reg2hw_prio134_reg_t prio134; // [226:225] + rv_plic_reg2hw_prio135_reg_t prio135; // [224:223] + rv_plic_reg2hw_prio136_reg_t prio136; // [222:221] + rv_plic_reg2hw_prio137_reg_t prio137; // [220:219] + rv_plic_reg2hw_prio138_reg_t prio138; // [218:217] + rv_plic_reg2hw_prio139_reg_t prio139; // [216:215] + rv_plic_reg2hw_prio140_reg_t prio140; // [214:213] + rv_plic_reg2hw_prio141_reg_t prio141; // [212:211] + rv_plic_reg2hw_prio142_reg_t prio142; // [210:209] + rv_plic_reg2hw_prio143_reg_t prio143; // [208:207] + rv_plic_reg2hw_prio144_reg_t prio144; // [206:205] + rv_plic_reg2hw_prio145_reg_t prio145; // [204:203] + rv_plic_reg2hw_prio146_reg_t prio146; // [202:201] + rv_plic_reg2hw_prio147_reg_t prio147; // [200:199] + rv_plic_reg2hw_prio148_reg_t prio148; // [198:197] + rv_plic_reg2hw_prio149_reg_t prio149; // [196:195] + rv_plic_reg2hw_prio150_reg_t prio150; // [194:193] + rv_plic_reg2hw_prio151_reg_t prio151; // [192:191] + rv_plic_reg2hw_prio152_reg_t prio152; // [190:189] + rv_plic_reg2hw_prio153_reg_t prio153; // [188:187] + rv_plic_reg2hw_prio154_reg_t prio154; // [186:185] + rv_plic_reg2hw_prio155_reg_t prio155; // [184:183] + rv_plic_reg2hw_prio156_reg_t prio156; // [182:181] + rv_plic_reg2hw_prio157_reg_t prio157; // [180:179] + rv_plic_reg2hw_prio158_reg_t prio158; // [178:177] + rv_plic_reg2hw_prio159_reg_t prio159; // [176:175] + rv_plic_reg2hw_ie0_mreg_t [159:0] ie0; // [174:15] + rv_plic_reg2hw_threshold0_reg_t threshold0; // [14:13] + rv_plic_reg2hw_cc0_reg_t cc0; // [12:3] + rv_plic_reg2hw_msip0_reg_t msip0; // [2:2] + rv_plic_reg2hw_alert_test_reg_t alert_test; // [1:0] + } rv_plic_reg2hw_t; + + // HW -> register type + typedef struct packed { + rv_plic_hw2reg_ip_mreg_t [159:0] ip; // [327:8] + rv_plic_hw2reg_cc0_reg_t cc0; // [7:0] + } rv_plic_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] RV_PLIC_PRIO0_OFFSET = 27'h 0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO1_OFFSET = 27'h 4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO2_OFFSET = 27'h 8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO3_OFFSET = 27'h c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO4_OFFSET = 27'h 10; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO5_OFFSET = 27'h 14; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO6_OFFSET = 27'h 18; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO7_OFFSET = 27'h 1c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO8_OFFSET = 27'h 20; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO9_OFFSET = 27'h 24; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO10_OFFSET = 27'h 28; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO11_OFFSET = 27'h 2c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO12_OFFSET = 27'h 30; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO13_OFFSET = 27'h 34; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO14_OFFSET = 27'h 38; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO15_OFFSET = 27'h 3c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO16_OFFSET = 27'h 40; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO17_OFFSET = 27'h 44; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO18_OFFSET = 27'h 48; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO19_OFFSET = 27'h 4c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO20_OFFSET = 27'h 50; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO21_OFFSET = 27'h 54; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO22_OFFSET = 27'h 58; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO23_OFFSET = 27'h 5c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO24_OFFSET = 27'h 60; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO25_OFFSET = 27'h 64; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO26_OFFSET = 27'h 68; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO27_OFFSET = 27'h 6c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO28_OFFSET = 27'h 70; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO29_OFFSET = 27'h 74; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO30_OFFSET = 27'h 78; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO31_OFFSET = 27'h 7c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO32_OFFSET = 27'h 80; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO33_OFFSET = 27'h 84; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO34_OFFSET = 27'h 88; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO35_OFFSET = 27'h 8c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO36_OFFSET = 27'h 90; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO37_OFFSET = 27'h 94; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO38_OFFSET = 27'h 98; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO39_OFFSET = 27'h 9c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO40_OFFSET = 27'h a0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO41_OFFSET = 27'h a4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO42_OFFSET = 27'h a8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO43_OFFSET = 27'h ac; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO44_OFFSET = 27'h b0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO45_OFFSET = 27'h b4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO46_OFFSET = 27'h b8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO47_OFFSET = 27'h bc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO48_OFFSET = 27'h c0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO49_OFFSET = 27'h c4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO50_OFFSET = 27'h c8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO51_OFFSET = 27'h cc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO52_OFFSET = 27'h d0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO53_OFFSET = 27'h d4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO54_OFFSET = 27'h d8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO55_OFFSET = 27'h dc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO56_OFFSET = 27'h e0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO57_OFFSET = 27'h e4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO58_OFFSET = 27'h e8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO59_OFFSET = 27'h ec; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO60_OFFSET = 27'h f0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO61_OFFSET = 27'h f4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO62_OFFSET = 27'h f8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO63_OFFSET = 27'h fc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO64_OFFSET = 27'h 100; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO65_OFFSET = 27'h 104; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO66_OFFSET = 27'h 108; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO67_OFFSET = 27'h 10c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO68_OFFSET = 27'h 110; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO69_OFFSET = 27'h 114; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO70_OFFSET = 27'h 118; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO71_OFFSET = 27'h 11c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO72_OFFSET = 27'h 120; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO73_OFFSET = 27'h 124; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO74_OFFSET = 27'h 128; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO75_OFFSET = 27'h 12c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO76_OFFSET = 27'h 130; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO77_OFFSET = 27'h 134; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO78_OFFSET = 27'h 138; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO79_OFFSET = 27'h 13c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO80_OFFSET = 27'h 140; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO81_OFFSET = 27'h 144; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO82_OFFSET = 27'h 148; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO83_OFFSET = 27'h 14c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO84_OFFSET = 27'h 150; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO85_OFFSET = 27'h 154; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO86_OFFSET = 27'h 158; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO87_OFFSET = 27'h 15c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO88_OFFSET = 27'h 160; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO89_OFFSET = 27'h 164; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO90_OFFSET = 27'h 168; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO91_OFFSET = 27'h 16c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO92_OFFSET = 27'h 170; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO93_OFFSET = 27'h 174; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO94_OFFSET = 27'h 178; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO95_OFFSET = 27'h 17c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO96_OFFSET = 27'h 180; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO97_OFFSET = 27'h 184; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO98_OFFSET = 27'h 188; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO99_OFFSET = 27'h 18c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO100_OFFSET = 27'h 190; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO101_OFFSET = 27'h 194; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO102_OFFSET = 27'h 198; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO103_OFFSET = 27'h 19c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO104_OFFSET = 27'h 1a0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO105_OFFSET = 27'h 1a4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO106_OFFSET = 27'h 1a8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO107_OFFSET = 27'h 1ac; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO108_OFFSET = 27'h 1b0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO109_OFFSET = 27'h 1b4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO110_OFFSET = 27'h 1b8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO111_OFFSET = 27'h 1bc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO112_OFFSET = 27'h 1c0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO113_OFFSET = 27'h 1c4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO114_OFFSET = 27'h 1c8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO115_OFFSET = 27'h 1cc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO116_OFFSET = 27'h 1d0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO117_OFFSET = 27'h 1d4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO118_OFFSET = 27'h 1d8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO119_OFFSET = 27'h 1dc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO120_OFFSET = 27'h 1e0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO121_OFFSET = 27'h 1e4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO122_OFFSET = 27'h 1e8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO123_OFFSET = 27'h 1ec; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO124_OFFSET = 27'h 1f0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO125_OFFSET = 27'h 1f4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO126_OFFSET = 27'h 1f8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO127_OFFSET = 27'h 1fc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO128_OFFSET = 27'h 200; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO129_OFFSET = 27'h 204; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO130_OFFSET = 27'h 208; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO131_OFFSET = 27'h 20c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO132_OFFSET = 27'h 210; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO133_OFFSET = 27'h 214; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO134_OFFSET = 27'h 218; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO135_OFFSET = 27'h 21c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO136_OFFSET = 27'h 220; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO137_OFFSET = 27'h 224; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO138_OFFSET = 27'h 228; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO139_OFFSET = 27'h 22c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO140_OFFSET = 27'h 230; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO141_OFFSET = 27'h 234; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO142_OFFSET = 27'h 238; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO143_OFFSET = 27'h 23c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO144_OFFSET = 27'h 240; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO145_OFFSET = 27'h 244; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO146_OFFSET = 27'h 248; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO147_OFFSET = 27'h 24c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO148_OFFSET = 27'h 250; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO149_OFFSET = 27'h 254; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO150_OFFSET = 27'h 258; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO151_OFFSET = 27'h 25c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO152_OFFSET = 27'h 260; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO153_OFFSET = 27'h 264; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO154_OFFSET = 27'h 268; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO155_OFFSET = 27'h 26c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO156_OFFSET = 27'h 270; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO157_OFFSET = 27'h 274; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO158_OFFSET = 27'h 278; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO159_OFFSET = 27'h 27c; + parameter logic [BlockAw-1:0] RV_PLIC_IP_0_OFFSET = 27'h 1000; + parameter logic [BlockAw-1:0] RV_PLIC_IP_1_OFFSET = 27'h 1004; + parameter logic [BlockAw-1:0] RV_PLIC_IP_2_OFFSET = 27'h 1008; + parameter logic [BlockAw-1:0] RV_PLIC_IP_3_OFFSET = 27'h 100c; + parameter logic [BlockAw-1:0] RV_PLIC_IP_4_OFFSET = 27'h 1010; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_0_OFFSET = 27'h 2000; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_1_OFFSET = 27'h 2004; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_2_OFFSET = 27'h 2008; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_3_OFFSET = 27'h 200c; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_4_OFFSET = 27'h 2010; + parameter logic [BlockAw-1:0] RV_PLIC_THRESHOLD0_OFFSET = 27'h 200000; + parameter logic [BlockAw-1:0] RV_PLIC_CC0_OFFSET = 27'h 200004; + parameter logic [BlockAw-1:0] RV_PLIC_MSIP0_OFFSET = 27'h 4000000; + parameter logic [BlockAw-1:0] RV_PLIC_ALERT_TEST_OFFSET = 27'h 4004000; + + // Reset values for hwext registers and their fields + parameter logic [7:0] RV_PLIC_CC0_RESVAL = 8'h 0; + parameter logic [0:0] RV_PLIC_ALERT_TEST_RESVAL = 1'h 0; + + // Register index + typedef enum int { + RV_PLIC_PRIO0, + RV_PLIC_PRIO1, + RV_PLIC_PRIO2, + RV_PLIC_PRIO3, + RV_PLIC_PRIO4, + RV_PLIC_PRIO5, + RV_PLIC_PRIO6, + RV_PLIC_PRIO7, + RV_PLIC_PRIO8, + RV_PLIC_PRIO9, + RV_PLIC_PRIO10, + RV_PLIC_PRIO11, + RV_PLIC_PRIO12, + RV_PLIC_PRIO13, + RV_PLIC_PRIO14, + RV_PLIC_PRIO15, + RV_PLIC_PRIO16, + RV_PLIC_PRIO17, + RV_PLIC_PRIO18, + RV_PLIC_PRIO19, + RV_PLIC_PRIO20, + RV_PLIC_PRIO21, + RV_PLIC_PRIO22, + RV_PLIC_PRIO23, + RV_PLIC_PRIO24, + RV_PLIC_PRIO25, + RV_PLIC_PRIO26, + RV_PLIC_PRIO27, + RV_PLIC_PRIO28, + RV_PLIC_PRIO29, + RV_PLIC_PRIO30, + RV_PLIC_PRIO31, + RV_PLIC_PRIO32, + RV_PLIC_PRIO33, + RV_PLIC_PRIO34, + RV_PLIC_PRIO35, + RV_PLIC_PRIO36, + RV_PLIC_PRIO37, + RV_PLIC_PRIO38, + RV_PLIC_PRIO39, + RV_PLIC_PRIO40, + RV_PLIC_PRIO41, + RV_PLIC_PRIO42, + RV_PLIC_PRIO43, + RV_PLIC_PRIO44, + RV_PLIC_PRIO45, + RV_PLIC_PRIO46, + RV_PLIC_PRIO47, + RV_PLIC_PRIO48, + RV_PLIC_PRIO49, + RV_PLIC_PRIO50, + RV_PLIC_PRIO51, + RV_PLIC_PRIO52, + RV_PLIC_PRIO53, + RV_PLIC_PRIO54, + RV_PLIC_PRIO55, + RV_PLIC_PRIO56, + RV_PLIC_PRIO57, + RV_PLIC_PRIO58, + RV_PLIC_PRIO59, + RV_PLIC_PRIO60, + RV_PLIC_PRIO61, + RV_PLIC_PRIO62, + RV_PLIC_PRIO63, + RV_PLIC_PRIO64, + RV_PLIC_PRIO65, + RV_PLIC_PRIO66, + RV_PLIC_PRIO67, + RV_PLIC_PRIO68, + RV_PLIC_PRIO69, + RV_PLIC_PRIO70, + RV_PLIC_PRIO71, + RV_PLIC_PRIO72, + RV_PLIC_PRIO73, + RV_PLIC_PRIO74, + RV_PLIC_PRIO75, + RV_PLIC_PRIO76, + RV_PLIC_PRIO77, + RV_PLIC_PRIO78, + RV_PLIC_PRIO79, + RV_PLIC_PRIO80, + RV_PLIC_PRIO81, + RV_PLIC_PRIO82, + RV_PLIC_PRIO83, + RV_PLIC_PRIO84, + RV_PLIC_PRIO85, + RV_PLIC_PRIO86, + RV_PLIC_PRIO87, + RV_PLIC_PRIO88, + RV_PLIC_PRIO89, + RV_PLIC_PRIO90, + RV_PLIC_PRIO91, + RV_PLIC_PRIO92, + RV_PLIC_PRIO93, + RV_PLIC_PRIO94, + RV_PLIC_PRIO95, + RV_PLIC_PRIO96, + RV_PLIC_PRIO97, + RV_PLIC_PRIO98, + RV_PLIC_PRIO99, + RV_PLIC_PRIO100, + RV_PLIC_PRIO101, + RV_PLIC_PRIO102, + RV_PLIC_PRIO103, + RV_PLIC_PRIO104, + RV_PLIC_PRIO105, + RV_PLIC_PRIO106, + RV_PLIC_PRIO107, + RV_PLIC_PRIO108, + RV_PLIC_PRIO109, + RV_PLIC_PRIO110, + RV_PLIC_PRIO111, + RV_PLIC_PRIO112, + RV_PLIC_PRIO113, + RV_PLIC_PRIO114, + RV_PLIC_PRIO115, + RV_PLIC_PRIO116, + RV_PLIC_PRIO117, + RV_PLIC_PRIO118, + RV_PLIC_PRIO119, + RV_PLIC_PRIO120, + RV_PLIC_PRIO121, + RV_PLIC_PRIO122, + RV_PLIC_PRIO123, + RV_PLIC_PRIO124, + RV_PLIC_PRIO125, + RV_PLIC_PRIO126, + RV_PLIC_PRIO127, + RV_PLIC_PRIO128, + RV_PLIC_PRIO129, + RV_PLIC_PRIO130, + RV_PLIC_PRIO131, + RV_PLIC_PRIO132, + RV_PLIC_PRIO133, + RV_PLIC_PRIO134, + RV_PLIC_PRIO135, + RV_PLIC_PRIO136, + RV_PLIC_PRIO137, + RV_PLIC_PRIO138, + RV_PLIC_PRIO139, + RV_PLIC_PRIO140, + RV_PLIC_PRIO141, + RV_PLIC_PRIO142, + RV_PLIC_PRIO143, + RV_PLIC_PRIO144, + RV_PLIC_PRIO145, + RV_PLIC_PRIO146, + RV_PLIC_PRIO147, + RV_PLIC_PRIO148, + RV_PLIC_PRIO149, + RV_PLIC_PRIO150, + RV_PLIC_PRIO151, + RV_PLIC_PRIO152, + RV_PLIC_PRIO153, + RV_PLIC_PRIO154, + RV_PLIC_PRIO155, + RV_PLIC_PRIO156, + RV_PLIC_PRIO157, + RV_PLIC_PRIO158, + RV_PLIC_PRIO159, + RV_PLIC_IP_0, + RV_PLIC_IP_1, + RV_PLIC_IP_2, + RV_PLIC_IP_3, + RV_PLIC_IP_4, + RV_PLIC_IE0_0, + RV_PLIC_IE0_1, + RV_PLIC_IE0_2, + RV_PLIC_IE0_3, + RV_PLIC_IE0_4, + RV_PLIC_THRESHOLD0, + RV_PLIC_CC0, + RV_PLIC_MSIP0, + RV_PLIC_ALERT_TEST + } rv_plic_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] RV_PLIC_PERMIT [174] = '{ + 4'b 0001, // index[ 0] RV_PLIC_PRIO0 + 4'b 0001, // index[ 1] RV_PLIC_PRIO1 + 4'b 0001, // index[ 2] RV_PLIC_PRIO2 + 4'b 0001, // index[ 3] RV_PLIC_PRIO3 + 4'b 0001, // index[ 4] RV_PLIC_PRIO4 + 4'b 0001, // index[ 5] RV_PLIC_PRIO5 + 4'b 0001, // index[ 6] RV_PLIC_PRIO6 + 4'b 0001, // index[ 7] RV_PLIC_PRIO7 + 4'b 0001, // index[ 8] RV_PLIC_PRIO8 + 4'b 0001, // index[ 9] RV_PLIC_PRIO9 + 4'b 0001, // index[ 10] RV_PLIC_PRIO10 + 4'b 0001, // index[ 11] RV_PLIC_PRIO11 + 4'b 0001, // index[ 12] RV_PLIC_PRIO12 + 4'b 0001, // index[ 13] RV_PLIC_PRIO13 + 4'b 0001, // index[ 14] RV_PLIC_PRIO14 + 4'b 0001, // index[ 15] RV_PLIC_PRIO15 + 4'b 0001, // index[ 16] RV_PLIC_PRIO16 + 4'b 0001, // index[ 17] RV_PLIC_PRIO17 + 4'b 0001, // index[ 18] RV_PLIC_PRIO18 + 4'b 0001, // index[ 19] RV_PLIC_PRIO19 + 4'b 0001, // index[ 20] RV_PLIC_PRIO20 + 4'b 0001, // index[ 21] RV_PLIC_PRIO21 + 4'b 0001, // index[ 22] RV_PLIC_PRIO22 + 4'b 0001, // index[ 23] RV_PLIC_PRIO23 + 4'b 0001, // index[ 24] RV_PLIC_PRIO24 + 4'b 0001, // index[ 25] RV_PLIC_PRIO25 + 4'b 0001, // index[ 26] RV_PLIC_PRIO26 + 4'b 0001, // index[ 27] RV_PLIC_PRIO27 + 4'b 0001, // index[ 28] RV_PLIC_PRIO28 + 4'b 0001, // index[ 29] RV_PLIC_PRIO29 + 4'b 0001, // index[ 30] RV_PLIC_PRIO30 + 4'b 0001, // index[ 31] RV_PLIC_PRIO31 + 4'b 0001, // index[ 32] RV_PLIC_PRIO32 + 4'b 0001, // index[ 33] RV_PLIC_PRIO33 + 4'b 0001, // index[ 34] RV_PLIC_PRIO34 + 4'b 0001, // index[ 35] RV_PLIC_PRIO35 + 4'b 0001, // index[ 36] RV_PLIC_PRIO36 + 4'b 0001, // index[ 37] RV_PLIC_PRIO37 + 4'b 0001, // index[ 38] RV_PLIC_PRIO38 + 4'b 0001, // index[ 39] RV_PLIC_PRIO39 + 4'b 0001, // index[ 40] RV_PLIC_PRIO40 + 4'b 0001, // index[ 41] RV_PLIC_PRIO41 + 4'b 0001, // index[ 42] RV_PLIC_PRIO42 + 4'b 0001, // index[ 43] RV_PLIC_PRIO43 + 4'b 0001, // index[ 44] RV_PLIC_PRIO44 + 4'b 0001, // index[ 45] RV_PLIC_PRIO45 + 4'b 0001, // index[ 46] RV_PLIC_PRIO46 + 4'b 0001, // index[ 47] RV_PLIC_PRIO47 + 4'b 0001, // index[ 48] RV_PLIC_PRIO48 + 4'b 0001, // index[ 49] RV_PLIC_PRIO49 + 4'b 0001, // index[ 50] RV_PLIC_PRIO50 + 4'b 0001, // index[ 51] RV_PLIC_PRIO51 + 4'b 0001, // index[ 52] RV_PLIC_PRIO52 + 4'b 0001, // index[ 53] RV_PLIC_PRIO53 + 4'b 0001, // index[ 54] RV_PLIC_PRIO54 + 4'b 0001, // index[ 55] RV_PLIC_PRIO55 + 4'b 0001, // index[ 56] RV_PLIC_PRIO56 + 4'b 0001, // index[ 57] RV_PLIC_PRIO57 + 4'b 0001, // index[ 58] RV_PLIC_PRIO58 + 4'b 0001, // index[ 59] RV_PLIC_PRIO59 + 4'b 0001, // index[ 60] RV_PLIC_PRIO60 + 4'b 0001, // index[ 61] RV_PLIC_PRIO61 + 4'b 0001, // index[ 62] RV_PLIC_PRIO62 + 4'b 0001, // index[ 63] RV_PLIC_PRIO63 + 4'b 0001, // index[ 64] RV_PLIC_PRIO64 + 4'b 0001, // index[ 65] RV_PLIC_PRIO65 + 4'b 0001, // index[ 66] RV_PLIC_PRIO66 + 4'b 0001, // index[ 67] RV_PLIC_PRIO67 + 4'b 0001, // index[ 68] RV_PLIC_PRIO68 + 4'b 0001, // index[ 69] RV_PLIC_PRIO69 + 4'b 0001, // index[ 70] RV_PLIC_PRIO70 + 4'b 0001, // index[ 71] RV_PLIC_PRIO71 + 4'b 0001, // index[ 72] RV_PLIC_PRIO72 + 4'b 0001, // index[ 73] RV_PLIC_PRIO73 + 4'b 0001, // index[ 74] RV_PLIC_PRIO74 + 4'b 0001, // index[ 75] RV_PLIC_PRIO75 + 4'b 0001, // index[ 76] RV_PLIC_PRIO76 + 4'b 0001, // index[ 77] RV_PLIC_PRIO77 + 4'b 0001, // index[ 78] RV_PLIC_PRIO78 + 4'b 0001, // index[ 79] RV_PLIC_PRIO79 + 4'b 0001, // index[ 80] RV_PLIC_PRIO80 + 4'b 0001, // index[ 81] RV_PLIC_PRIO81 + 4'b 0001, // index[ 82] RV_PLIC_PRIO82 + 4'b 0001, // index[ 83] RV_PLIC_PRIO83 + 4'b 0001, // index[ 84] RV_PLIC_PRIO84 + 4'b 0001, // index[ 85] RV_PLIC_PRIO85 + 4'b 0001, // index[ 86] RV_PLIC_PRIO86 + 4'b 0001, // index[ 87] RV_PLIC_PRIO87 + 4'b 0001, // index[ 88] RV_PLIC_PRIO88 + 4'b 0001, // index[ 89] RV_PLIC_PRIO89 + 4'b 0001, // index[ 90] RV_PLIC_PRIO90 + 4'b 0001, // index[ 91] RV_PLIC_PRIO91 + 4'b 0001, // index[ 92] RV_PLIC_PRIO92 + 4'b 0001, // index[ 93] RV_PLIC_PRIO93 + 4'b 0001, // index[ 94] RV_PLIC_PRIO94 + 4'b 0001, // index[ 95] RV_PLIC_PRIO95 + 4'b 0001, // index[ 96] RV_PLIC_PRIO96 + 4'b 0001, // index[ 97] RV_PLIC_PRIO97 + 4'b 0001, // index[ 98] RV_PLIC_PRIO98 + 4'b 0001, // index[ 99] RV_PLIC_PRIO99 + 4'b 0001, // index[100] RV_PLIC_PRIO100 + 4'b 0001, // index[101] RV_PLIC_PRIO101 + 4'b 0001, // index[102] RV_PLIC_PRIO102 + 4'b 0001, // index[103] RV_PLIC_PRIO103 + 4'b 0001, // index[104] RV_PLIC_PRIO104 + 4'b 0001, // index[105] RV_PLIC_PRIO105 + 4'b 0001, // index[106] RV_PLIC_PRIO106 + 4'b 0001, // index[107] RV_PLIC_PRIO107 + 4'b 0001, // index[108] RV_PLIC_PRIO108 + 4'b 0001, // index[109] RV_PLIC_PRIO109 + 4'b 0001, // index[110] RV_PLIC_PRIO110 + 4'b 0001, // index[111] RV_PLIC_PRIO111 + 4'b 0001, // index[112] RV_PLIC_PRIO112 + 4'b 0001, // index[113] RV_PLIC_PRIO113 + 4'b 0001, // index[114] RV_PLIC_PRIO114 + 4'b 0001, // index[115] RV_PLIC_PRIO115 + 4'b 0001, // index[116] RV_PLIC_PRIO116 + 4'b 0001, // index[117] RV_PLIC_PRIO117 + 4'b 0001, // index[118] RV_PLIC_PRIO118 + 4'b 0001, // index[119] RV_PLIC_PRIO119 + 4'b 0001, // index[120] RV_PLIC_PRIO120 + 4'b 0001, // index[121] RV_PLIC_PRIO121 + 4'b 0001, // index[122] RV_PLIC_PRIO122 + 4'b 0001, // index[123] RV_PLIC_PRIO123 + 4'b 0001, // index[124] RV_PLIC_PRIO124 + 4'b 0001, // index[125] RV_PLIC_PRIO125 + 4'b 0001, // index[126] RV_PLIC_PRIO126 + 4'b 0001, // index[127] RV_PLIC_PRIO127 + 4'b 0001, // index[128] RV_PLIC_PRIO128 + 4'b 0001, // index[129] RV_PLIC_PRIO129 + 4'b 0001, // index[130] RV_PLIC_PRIO130 + 4'b 0001, // index[131] RV_PLIC_PRIO131 + 4'b 0001, // index[132] RV_PLIC_PRIO132 + 4'b 0001, // index[133] RV_PLIC_PRIO133 + 4'b 0001, // index[134] RV_PLIC_PRIO134 + 4'b 0001, // index[135] RV_PLIC_PRIO135 + 4'b 0001, // index[136] RV_PLIC_PRIO136 + 4'b 0001, // index[137] RV_PLIC_PRIO137 + 4'b 0001, // index[138] RV_PLIC_PRIO138 + 4'b 0001, // index[139] RV_PLIC_PRIO139 + 4'b 0001, // index[140] RV_PLIC_PRIO140 + 4'b 0001, // index[141] RV_PLIC_PRIO141 + 4'b 0001, // index[142] RV_PLIC_PRIO142 + 4'b 0001, // index[143] RV_PLIC_PRIO143 + 4'b 0001, // index[144] RV_PLIC_PRIO144 + 4'b 0001, // index[145] RV_PLIC_PRIO145 + 4'b 0001, // index[146] RV_PLIC_PRIO146 + 4'b 0001, // index[147] RV_PLIC_PRIO147 + 4'b 0001, // index[148] RV_PLIC_PRIO148 + 4'b 0001, // index[149] RV_PLIC_PRIO149 + 4'b 0001, // index[150] RV_PLIC_PRIO150 + 4'b 0001, // index[151] RV_PLIC_PRIO151 + 4'b 0001, // index[152] RV_PLIC_PRIO152 + 4'b 0001, // index[153] RV_PLIC_PRIO153 + 4'b 0001, // index[154] RV_PLIC_PRIO154 + 4'b 0001, // index[155] RV_PLIC_PRIO155 + 4'b 0001, // index[156] RV_PLIC_PRIO156 + 4'b 0001, // index[157] RV_PLIC_PRIO157 + 4'b 0001, // index[158] RV_PLIC_PRIO158 + 4'b 0001, // index[159] RV_PLIC_PRIO159 + 4'b 1111, // index[160] RV_PLIC_IP_0 + 4'b 1111, // index[161] RV_PLIC_IP_1 + 4'b 1111, // index[162] RV_PLIC_IP_2 + 4'b 1111, // index[163] RV_PLIC_IP_3 + 4'b 1111, // index[164] RV_PLIC_IP_4 + 4'b 1111, // index[165] RV_PLIC_IE0_0 + 4'b 1111, // index[166] RV_PLIC_IE0_1 + 4'b 1111, // index[167] RV_PLIC_IE0_2 + 4'b 1111, // index[168] RV_PLIC_IE0_3 + 4'b 1111, // index[169] RV_PLIC_IE0_4 + 4'b 0001, // index[170] RV_PLIC_THRESHOLD0 + 4'b 0001, // index[171] RV_PLIC_CC0 + 4'b 0001, // index[172] RV_PLIC_MSIP0 + 4'b 0001 // index[173] RV_PLIC_ALERT_TEST + }; + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv new file mode 100644 index 0000000000000..3bcb55f1ca191 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv @@ -0,0 +1,16753 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module rv_plic_reg_top ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output rv_plic_reg_pkg::rv_plic_reg2hw_t reg2hw, // Write + input rv_plic_reg_pkg::rv_plic_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import rv_plic_reg_pkg::* ; + + localparam int AW = 27; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [173:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(174) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic prio0_we; + logic [1:0] prio0_qs; + logic [1:0] prio0_wd; + logic prio1_we; + logic [1:0] prio1_qs; + logic [1:0] prio1_wd; + logic prio2_we; + logic [1:0] prio2_qs; + logic [1:0] prio2_wd; + logic prio3_we; + logic [1:0] prio3_qs; + logic [1:0] prio3_wd; + logic prio4_we; + logic [1:0] prio4_qs; + logic [1:0] prio4_wd; + logic prio5_we; + logic [1:0] prio5_qs; + logic [1:0] prio5_wd; + logic prio6_we; + logic [1:0] prio6_qs; + logic [1:0] prio6_wd; + logic prio7_we; + logic [1:0] prio7_qs; + logic [1:0] prio7_wd; + logic prio8_we; + logic [1:0] prio8_qs; + logic [1:0] prio8_wd; + logic prio9_we; + logic [1:0] prio9_qs; + logic [1:0] prio9_wd; + logic prio10_we; + logic [1:0] prio10_qs; + logic [1:0] prio10_wd; + logic prio11_we; + logic [1:0] prio11_qs; + logic [1:0] prio11_wd; + logic prio12_we; + logic [1:0] prio12_qs; + logic [1:0] prio12_wd; + logic prio13_we; + logic [1:0] prio13_qs; + logic [1:0] prio13_wd; + logic prio14_we; + logic [1:0] prio14_qs; + logic [1:0] prio14_wd; + logic prio15_we; + logic [1:0] prio15_qs; + logic [1:0] prio15_wd; + logic prio16_we; + logic [1:0] prio16_qs; + logic [1:0] prio16_wd; + logic prio17_we; + logic [1:0] prio17_qs; + logic [1:0] prio17_wd; + logic prio18_we; + logic [1:0] prio18_qs; + logic [1:0] prio18_wd; + logic prio19_we; + logic [1:0] prio19_qs; + logic [1:0] prio19_wd; + logic prio20_we; + logic [1:0] prio20_qs; + logic [1:0] prio20_wd; + logic prio21_we; + logic [1:0] prio21_qs; + logic [1:0] prio21_wd; + logic prio22_we; + logic [1:0] prio22_qs; + logic [1:0] prio22_wd; + logic prio23_we; + logic [1:0] prio23_qs; + logic [1:0] prio23_wd; + logic prio24_we; + logic [1:0] prio24_qs; + logic [1:0] prio24_wd; + logic prio25_we; + logic [1:0] prio25_qs; + logic [1:0] prio25_wd; + logic prio26_we; + logic [1:0] prio26_qs; + logic [1:0] prio26_wd; + logic prio27_we; + logic [1:0] prio27_qs; + logic [1:0] prio27_wd; + logic prio28_we; + logic [1:0] prio28_qs; + logic [1:0] prio28_wd; + logic prio29_we; + logic [1:0] prio29_qs; + logic [1:0] prio29_wd; + logic prio30_we; + logic [1:0] prio30_qs; + logic [1:0] prio30_wd; + logic prio31_we; + logic [1:0] prio31_qs; + logic [1:0] prio31_wd; + logic prio32_we; + logic [1:0] prio32_qs; + logic [1:0] prio32_wd; + logic prio33_we; + logic [1:0] prio33_qs; + logic [1:0] prio33_wd; + logic prio34_we; + logic [1:0] prio34_qs; + logic [1:0] prio34_wd; + logic prio35_we; + logic [1:0] prio35_qs; + logic [1:0] prio35_wd; + logic prio36_we; + logic [1:0] prio36_qs; + logic [1:0] prio36_wd; + logic prio37_we; + logic [1:0] prio37_qs; + logic [1:0] prio37_wd; + logic prio38_we; + logic [1:0] prio38_qs; + logic [1:0] prio38_wd; + logic prio39_we; + logic [1:0] prio39_qs; + logic [1:0] prio39_wd; + logic prio40_we; + logic [1:0] prio40_qs; + logic [1:0] prio40_wd; + logic prio41_we; + logic [1:0] prio41_qs; + logic [1:0] prio41_wd; + logic prio42_we; + logic [1:0] prio42_qs; + logic [1:0] prio42_wd; + logic prio43_we; + logic [1:0] prio43_qs; + logic [1:0] prio43_wd; + logic prio44_we; + logic [1:0] prio44_qs; + logic [1:0] prio44_wd; + logic prio45_we; + logic [1:0] prio45_qs; + logic [1:0] prio45_wd; + logic prio46_we; + logic [1:0] prio46_qs; + logic [1:0] prio46_wd; + logic prio47_we; + logic [1:0] prio47_qs; + logic [1:0] prio47_wd; + logic prio48_we; + logic [1:0] prio48_qs; + logic [1:0] prio48_wd; + logic prio49_we; + logic [1:0] prio49_qs; + logic [1:0] prio49_wd; + logic prio50_we; + logic [1:0] prio50_qs; + logic [1:0] prio50_wd; + logic prio51_we; + logic [1:0] prio51_qs; + logic [1:0] prio51_wd; + logic prio52_we; + logic [1:0] prio52_qs; + logic [1:0] prio52_wd; + logic prio53_we; + logic [1:0] prio53_qs; + logic [1:0] prio53_wd; + logic prio54_we; + logic [1:0] prio54_qs; + logic [1:0] prio54_wd; + logic prio55_we; + logic [1:0] prio55_qs; + logic [1:0] prio55_wd; + logic prio56_we; + logic [1:0] prio56_qs; + logic [1:0] prio56_wd; + logic prio57_we; + logic [1:0] prio57_qs; + logic [1:0] prio57_wd; + logic prio58_we; + logic [1:0] prio58_qs; + logic [1:0] prio58_wd; + logic prio59_we; + logic [1:0] prio59_qs; + logic [1:0] prio59_wd; + logic prio60_we; + logic [1:0] prio60_qs; + logic [1:0] prio60_wd; + logic prio61_we; + logic [1:0] prio61_qs; + logic [1:0] prio61_wd; + logic prio62_we; + logic [1:0] prio62_qs; + logic [1:0] prio62_wd; + logic prio63_we; + logic [1:0] prio63_qs; + logic [1:0] prio63_wd; + logic prio64_we; + logic [1:0] prio64_qs; + logic [1:0] prio64_wd; + logic prio65_we; + logic [1:0] prio65_qs; + logic [1:0] prio65_wd; + logic prio66_we; + logic [1:0] prio66_qs; + logic [1:0] prio66_wd; + logic prio67_we; + logic [1:0] prio67_qs; + logic [1:0] prio67_wd; + logic prio68_we; + logic [1:0] prio68_qs; + logic [1:0] prio68_wd; + logic prio69_we; + logic [1:0] prio69_qs; + logic [1:0] prio69_wd; + logic prio70_we; + logic [1:0] prio70_qs; + logic [1:0] prio70_wd; + logic prio71_we; + logic [1:0] prio71_qs; + logic [1:0] prio71_wd; + logic prio72_we; + logic [1:0] prio72_qs; + logic [1:0] prio72_wd; + logic prio73_we; + logic [1:0] prio73_qs; + logic [1:0] prio73_wd; + logic prio74_we; + logic [1:0] prio74_qs; + logic [1:0] prio74_wd; + logic prio75_we; + logic [1:0] prio75_qs; + logic [1:0] prio75_wd; + logic prio76_we; + logic [1:0] prio76_qs; + logic [1:0] prio76_wd; + logic prio77_we; + logic [1:0] prio77_qs; + logic [1:0] prio77_wd; + logic prio78_we; + logic [1:0] prio78_qs; + logic [1:0] prio78_wd; + logic prio79_we; + logic [1:0] prio79_qs; + logic [1:0] prio79_wd; + logic prio80_we; + logic [1:0] prio80_qs; + logic [1:0] prio80_wd; + logic prio81_we; + logic [1:0] prio81_qs; + logic [1:0] prio81_wd; + logic prio82_we; + logic [1:0] prio82_qs; + logic [1:0] prio82_wd; + logic prio83_we; + logic [1:0] prio83_qs; + logic [1:0] prio83_wd; + logic prio84_we; + logic [1:0] prio84_qs; + logic [1:0] prio84_wd; + logic prio85_we; + logic [1:0] prio85_qs; + logic [1:0] prio85_wd; + logic prio86_we; + logic [1:0] prio86_qs; + logic [1:0] prio86_wd; + logic prio87_we; + logic [1:0] prio87_qs; + logic [1:0] prio87_wd; + logic prio88_we; + logic [1:0] prio88_qs; + logic [1:0] prio88_wd; + logic prio89_we; + logic [1:0] prio89_qs; + logic [1:0] prio89_wd; + logic prio90_we; + logic [1:0] prio90_qs; + logic [1:0] prio90_wd; + logic prio91_we; + logic [1:0] prio91_qs; + logic [1:0] prio91_wd; + logic prio92_we; + logic [1:0] prio92_qs; + logic [1:0] prio92_wd; + logic prio93_we; + logic [1:0] prio93_qs; + logic [1:0] prio93_wd; + logic prio94_we; + logic [1:0] prio94_qs; + logic [1:0] prio94_wd; + logic prio95_we; + logic [1:0] prio95_qs; + logic [1:0] prio95_wd; + logic prio96_we; + logic [1:0] prio96_qs; + logic [1:0] prio96_wd; + logic prio97_we; + logic [1:0] prio97_qs; + logic [1:0] prio97_wd; + logic prio98_we; + logic [1:0] prio98_qs; + logic [1:0] prio98_wd; + logic prio99_we; + logic [1:0] prio99_qs; + logic [1:0] prio99_wd; + logic prio100_we; + logic [1:0] prio100_qs; + logic [1:0] prio100_wd; + logic prio101_we; + logic [1:0] prio101_qs; + logic [1:0] prio101_wd; + logic prio102_we; + logic [1:0] prio102_qs; + logic [1:0] prio102_wd; + logic prio103_we; + logic [1:0] prio103_qs; + logic [1:0] prio103_wd; + logic prio104_we; + logic [1:0] prio104_qs; + logic [1:0] prio104_wd; + logic prio105_we; + logic [1:0] prio105_qs; + logic [1:0] prio105_wd; + logic prio106_we; + logic [1:0] prio106_qs; + logic [1:0] prio106_wd; + logic prio107_we; + logic [1:0] prio107_qs; + logic [1:0] prio107_wd; + logic prio108_we; + logic [1:0] prio108_qs; + logic [1:0] prio108_wd; + logic prio109_we; + logic [1:0] prio109_qs; + logic [1:0] prio109_wd; + logic prio110_we; + logic [1:0] prio110_qs; + logic [1:0] prio110_wd; + logic prio111_we; + logic [1:0] prio111_qs; + logic [1:0] prio111_wd; + logic prio112_we; + logic [1:0] prio112_qs; + logic [1:0] prio112_wd; + logic prio113_we; + logic [1:0] prio113_qs; + logic [1:0] prio113_wd; + logic prio114_we; + logic [1:0] prio114_qs; + logic [1:0] prio114_wd; + logic prio115_we; + logic [1:0] prio115_qs; + logic [1:0] prio115_wd; + logic prio116_we; + logic [1:0] prio116_qs; + logic [1:0] prio116_wd; + logic prio117_we; + logic [1:0] prio117_qs; + logic [1:0] prio117_wd; + logic prio118_we; + logic [1:0] prio118_qs; + logic [1:0] prio118_wd; + logic prio119_we; + logic [1:0] prio119_qs; + logic [1:0] prio119_wd; + logic prio120_we; + logic [1:0] prio120_qs; + logic [1:0] prio120_wd; + logic prio121_we; + logic [1:0] prio121_qs; + logic [1:0] prio121_wd; + logic prio122_we; + logic [1:0] prio122_qs; + logic [1:0] prio122_wd; + logic prio123_we; + logic [1:0] prio123_qs; + logic [1:0] prio123_wd; + logic prio124_we; + logic [1:0] prio124_qs; + logic [1:0] prio124_wd; + logic prio125_we; + logic [1:0] prio125_qs; + logic [1:0] prio125_wd; + logic prio126_we; + logic [1:0] prio126_qs; + logic [1:0] prio126_wd; + logic prio127_we; + logic [1:0] prio127_qs; + logic [1:0] prio127_wd; + logic prio128_we; + logic [1:0] prio128_qs; + logic [1:0] prio128_wd; + logic prio129_we; + logic [1:0] prio129_qs; + logic [1:0] prio129_wd; + logic prio130_we; + logic [1:0] prio130_qs; + logic [1:0] prio130_wd; + logic prio131_we; + logic [1:0] prio131_qs; + logic [1:0] prio131_wd; + logic prio132_we; + logic [1:0] prio132_qs; + logic [1:0] prio132_wd; + logic prio133_we; + logic [1:0] prio133_qs; + logic [1:0] prio133_wd; + logic prio134_we; + logic [1:0] prio134_qs; + logic [1:0] prio134_wd; + logic prio135_we; + logic [1:0] prio135_qs; + logic [1:0] prio135_wd; + logic prio136_we; + logic [1:0] prio136_qs; + logic [1:0] prio136_wd; + logic prio137_we; + logic [1:0] prio137_qs; + logic [1:0] prio137_wd; + logic prio138_we; + logic [1:0] prio138_qs; + logic [1:0] prio138_wd; + logic prio139_we; + logic [1:0] prio139_qs; + logic [1:0] prio139_wd; + logic prio140_we; + logic [1:0] prio140_qs; + logic [1:0] prio140_wd; + logic prio141_we; + logic [1:0] prio141_qs; + logic [1:0] prio141_wd; + logic prio142_we; + logic [1:0] prio142_qs; + logic [1:0] prio142_wd; + logic prio143_we; + logic [1:0] prio143_qs; + logic [1:0] prio143_wd; + logic prio144_we; + logic [1:0] prio144_qs; + logic [1:0] prio144_wd; + logic prio145_we; + logic [1:0] prio145_qs; + logic [1:0] prio145_wd; + logic prio146_we; + logic [1:0] prio146_qs; + logic [1:0] prio146_wd; + logic prio147_we; + logic [1:0] prio147_qs; + logic [1:0] prio147_wd; + logic prio148_we; + logic [1:0] prio148_qs; + logic [1:0] prio148_wd; + logic prio149_we; + logic [1:0] prio149_qs; + logic [1:0] prio149_wd; + logic prio150_we; + logic [1:0] prio150_qs; + logic [1:0] prio150_wd; + logic prio151_we; + logic [1:0] prio151_qs; + logic [1:0] prio151_wd; + logic prio152_we; + logic [1:0] prio152_qs; + logic [1:0] prio152_wd; + logic prio153_we; + logic [1:0] prio153_qs; + logic [1:0] prio153_wd; + logic prio154_we; + logic [1:0] prio154_qs; + logic [1:0] prio154_wd; + logic prio155_we; + logic [1:0] prio155_qs; + logic [1:0] prio155_wd; + logic prio156_we; + logic [1:0] prio156_qs; + logic [1:0] prio156_wd; + logic prio157_we; + logic [1:0] prio157_qs; + logic [1:0] prio157_wd; + logic prio158_we; + logic [1:0] prio158_qs; + logic [1:0] prio158_wd; + logic prio159_we; + logic [1:0] prio159_qs; + logic [1:0] prio159_wd; + logic ip_0_p_0_qs; + logic ip_0_p_1_qs; + logic ip_0_p_2_qs; + logic ip_0_p_3_qs; + logic ip_0_p_4_qs; + logic ip_0_p_5_qs; + logic ip_0_p_6_qs; + logic ip_0_p_7_qs; + logic ip_0_p_8_qs; + logic ip_0_p_9_qs; + logic ip_0_p_10_qs; + logic ip_0_p_11_qs; + logic ip_0_p_12_qs; + logic ip_0_p_13_qs; + logic ip_0_p_14_qs; + logic ip_0_p_15_qs; + logic ip_0_p_16_qs; + logic ip_0_p_17_qs; + logic ip_0_p_18_qs; + logic ip_0_p_19_qs; + logic ip_0_p_20_qs; + logic ip_0_p_21_qs; + logic ip_0_p_22_qs; + logic ip_0_p_23_qs; + logic ip_0_p_24_qs; + logic ip_0_p_25_qs; + logic ip_0_p_26_qs; + logic ip_0_p_27_qs; + logic ip_0_p_28_qs; + logic ip_0_p_29_qs; + logic ip_0_p_30_qs; + logic ip_0_p_31_qs; + logic ip_1_p_32_qs; + logic ip_1_p_33_qs; + logic ip_1_p_34_qs; + logic ip_1_p_35_qs; + logic ip_1_p_36_qs; + logic ip_1_p_37_qs; + logic ip_1_p_38_qs; + logic ip_1_p_39_qs; + logic ip_1_p_40_qs; + logic ip_1_p_41_qs; + logic ip_1_p_42_qs; + logic ip_1_p_43_qs; + logic ip_1_p_44_qs; + logic ip_1_p_45_qs; + logic ip_1_p_46_qs; + logic ip_1_p_47_qs; + logic ip_1_p_48_qs; + logic ip_1_p_49_qs; + logic ip_1_p_50_qs; + logic ip_1_p_51_qs; + logic ip_1_p_52_qs; + logic ip_1_p_53_qs; + logic ip_1_p_54_qs; + logic ip_1_p_55_qs; + logic ip_1_p_56_qs; + logic ip_1_p_57_qs; + logic ip_1_p_58_qs; + logic ip_1_p_59_qs; + logic ip_1_p_60_qs; + logic ip_1_p_61_qs; + logic ip_1_p_62_qs; + logic ip_1_p_63_qs; + logic ip_2_p_64_qs; + logic ip_2_p_65_qs; + logic ip_2_p_66_qs; + logic ip_2_p_67_qs; + logic ip_2_p_68_qs; + logic ip_2_p_69_qs; + logic ip_2_p_70_qs; + logic ip_2_p_71_qs; + logic ip_2_p_72_qs; + logic ip_2_p_73_qs; + logic ip_2_p_74_qs; + logic ip_2_p_75_qs; + logic ip_2_p_76_qs; + logic ip_2_p_77_qs; + logic ip_2_p_78_qs; + logic ip_2_p_79_qs; + logic ip_2_p_80_qs; + logic ip_2_p_81_qs; + logic ip_2_p_82_qs; + logic ip_2_p_83_qs; + logic ip_2_p_84_qs; + logic ip_2_p_85_qs; + logic ip_2_p_86_qs; + logic ip_2_p_87_qs; + logic ip_2_p_88_qs; + logic ip_2_p_89_qs; + logic ip_2_p_90_qs; + logic ip_2_p_91_qs; + logic ip_2_p_92_qs; + logic ip_2_p_93_qs; + logic ip_2_p_94_qs; + logic ip_2_p_95_qs; + logic ip_3_p_96_qs; + logic ip_3_p_97_qs; + logic ip_3_p_98_qs; + logic ip_3_p_99_qs; + logic ip_3_p_100_qs; + logic ip_3_p_101_qs; + logic ip_3_p_102_qs; + logic ip_3_p_103_qs; + logic ip_3_p_104_qs; + logic ip_3_p_105_qs; + logic ip_3_p_106_qs; + logic ip_3_p_107_qs; + logic ip_3_p_108_qs; + logic ip_3_p_109_qs; + logic ip_3_p_110_qs; + logic ip_3_p_111_qs; + logic ip_3_p_112_qs; + logic ip_3_p_113_qs; + logic ip_3_p_114_qs; + logic ip_3_p_115_qs; + logic ip_3_p_116_qs; + logic ip_3_p_117_qs; + logic ip_3_p_118_qs; + logic ip_3_p_119_qs; + logic ip_3_p_120_qs; + logic ip_3_p_121_qs; + logic ip_3_p_122_qs; + logic ip_3_p_123_qs; + logic ip_3_p_124_qs; + logic ip_3_p_125_qs; + logic ip_3_p_126_qs; + logic ip_3_p_127_qs; + logic ip_4_p_128_qs; + logic ip_4_p_129_qs; + logic ip_4_p_130_qs; + logic ip_4_p_131_qs; + logic ip_4_p_132_qs; + logic ip_4_p_133_qs; + logic ip_4_p_134_qs; + logic ip_4_p_135_qs; + logic ip_4_p_136_qs; + logic ip_4_p_137_qs; + logic ip_4_p_138_qs; + logic ip_4_p_139_qs; + logic ip_4_p_140_qs; + logic ip_4_p_141_qs; + logic ip_4_p_142_qs; + logic ip_4_p_143_qs; + logic ip_4_p_144_qs; + logic ip_4_p_145_qs; + logic ip_4_p_146_qs; + logic ip_4_p_147_qs; + logic ip_4_p_148_qs; + logic ip_4_p_149_qs; + logic ip_4_p_150_qs; + logic ip_4_p_151_qs; + logic ip_4_p_152_qs; + logic ip_4_p_153_qs; + logic ip_4_p_154_qs; + logic ip_4_p_155_qs; + logic ip_4_p_156_qs; + logic ip_4_p_157_qs; + logic ip_4_p_158_qs; + logic ip_4_p_159_qs; + logic ie0_0_we; + logic ie0_0_e_0_qs; + logic ie0_0_e_0_wd; + logic ie0_0_e_1_qs; + logic ie0_0_e_1_wd; + logic ie0_0_e_2_qs; + logic ie0_0_e_2_wd; + logic ie0_0_e_3_qs; + logic ie0_0_e_3_wd; + logic ie0_0_e_4_qs; + logic ie0_0_e_4_wd; + logic ie0_0_e_5_qs; + logic ie0_0_e_5_wd; + logic ie0_0_e_6_qs; + logic ie0_0_e_6_wd; + logic ie0_0_e_7_qs; + logic ie0_0_e_7_wd; + logic ie0_0_e_8_qs; + logic ie0_0_e_8_wd; + logic ie0_0_e_9_qs; + logic ie0_0_e_9_wd; + logic ie0_0_e_10_qs; + logic ie0_0_e_10_wd; + logic ie0_0_e_11_qs; + logic ie0_0_e_11_wd; + logic ie0_0_e_12_qs; + logic ie0_0_e_12_wd; + logic ie0_0_e_13_qs; + logic ie0_0_e_13_wd; + logic ie0_0_e_14_qs; + logic ie0_0_e_14_wd; + logic ie0_0_e_15_qs; + logic ie0_0_e_15_wd; + logic ie0_0_e_16_qs; + logic ie0_0_e_16_wd; + logic ie0_0_e_17_qs; + logic ie0_0_e_17_wd; + logic ie0_0_e_18_qs; + logic ie0_0_e_18_wd; + logic ie0_0_e_19_qs; + logic ie0_0_e_19_wd; + logic ie0_0_e_20_qs; + logic ie0_0_e_20_wd; + logic ie0_0_e_21_qs; + logic ie0_0_e_21_wd; + logic ie0_0_e_22_qs; + logic ie0_0_e_22_wd; + logic ie0_0_e_23_qs; + logic ie0_0_e_23_wd; + logic ie0_0_e_24_qs; + logic ie0_0_e_24_wd; + logic ie0_0_e_25_qs; + logic ie0_0_e_25_wd; + logic ie0_0_e_26_qs; + logic ie0_0_e_26_wd; + logic ie0_0_e_27_qs; + logic ie0_0_e_27_wd; + logic ie0_0_e_28_qs; + logic ie0_0_e_28_wd; + logic ie0_0_e_29_qs; + logic ie0_0_e_29_wd; + logic ie0_0_e_30_qs; + logic ie0_0_e_30_wd; + logic ie0_0_e_31_qs; + logic ie0_0_e_31_wd; + logic ie0_1_we; + logic ie0_1_e_32_qs; + logic ie0_1_e_32_wd; + logic ie0_1_e_33_qs; + logic ie0_1_e_33_wd; + logic ie0_1_e_34_qs; + logic ie0_1_e_34_wd; + logic ie0_1_e_35_qs; + logic ie0_1_e_35_wd; + logic ie0_1_e_36_qs; + logic ie0_1_e_36_wd; + logic ie0_1_e_37_qs; + logic ie0_1_e_37_wd; + logic ie0_1_e_38_qs; + logic ie0_1_e_38_wd; + logic ie0_1_e_39_qs; + logic ie0_1_e_39_wd; + logic ie0_1_e_40_qs; + logic ie0_1_e_40_wd; + logic ie0_1_e_41_qs; + logic ie0_1_e_41_wd; + logic ie0_1_e_42_qs; + logic ie0_1_e_42_wd; + logic ie0_1_e_43_qs; + logic ie0_1_e_43_wd; + logic ie0_1_e_44_qs; + logic ie0_1_e_44_wd; + logic ie0_1_e_45_qs; + logic ie0_1_e_45_wd; + logic ie0_1_e_46_qs; + logic ie0_1_e_46_wd; + logic ie0_1_e_47_qs; + logic ie0_1_e_47_wd; + logic ie0_1_e_48_qs; + logic ie0_1_e_48_wd; + logic ie0_1_e_49_qs; + logic ie0_1_e_49_wd; + logic ie0_1_e_50_qs; + logic ie0_1_e_50_wd; + logic ie0_1_e_51_qs; + logic ie0_1_e_51_wd; + logic ie0_1_e_52_qs; + logic ie0_1_e_52_wd; + logic ie0_1_e_53_qs; + logic ie0_1_e_53_wd; + logic ie0_1_e_54_qs; + logic ie0_1_e_54_wd; + logic ie0_1_e_55_qs; + logic ie0_1_e_55_wd; + logic ie0_1_e_56_qs; + logic ie0_1_e_56_wd; + logic ie0_1_e_57_qs; + logic ie0_1_e_57_wd; + logic ie0_1_e_58_qs; + logic ie0_1_e_58_wd; + logic ie0_1_e_59_qs; + logic ie0_1_e_59_wd; + logic ie0_1_e_60_qs; + logic ie0_1_e_60_wd; + logic ie0_1_e_61_qs; + logic ie0_1_e_61_wd; + logic ie0_1_e_62_qs; + logic ie0_1_e_62_wd; + logic ie0_1_e_63_qs; + logic ie0_1_e_63_wd; + logic ie0_2_we; + logic ie0_2_e_64_qs; + logic ie0_2_e_64_wd; + logic ie0_2_e_65_qs; + logic ie0_2_e_65_wd; + logic ie0_2_e_66_qs; + logic ie0_2_e_66_wd; + logic ie0_2_e_67_qs; + logic ie0_2_e_67_wd; + logic ie0_2_e_68_qs; + logic ie0_2_e_68_wd; + logic ie0_2_e_69_qs; + logic ie0_2_e_69_wd; + logic ie0_2_e_70_qs; + logic ie0_2_e_70_wd; + logic ie0_2_e_71_qs; + logic ie0_2_e_71_wd; + logic ie0_2_e_72_qs; + logic ie0_2_e_72_wd; + logic ie0_2_e_73_qs; + logic ie0_2_e_73_wd; + logic ie0_2_e_74_qs; + logic ie0_2_e_74_wd; + logic ie0_2_e_75_qs; + logic ie0_2_e_75_wd; + logic ie0_2_e_76_qs; + logic ie0_2_e_76_wd; + logic ie0_2_e_77_qs; + logic ie0_2_e_77_wd; + logic ie0_2_e_78_qs; + logic ie0_2_e_78_wd; + logic ie0_2_e_79_qs; + logic ie0_2_e_79_wd; + logic ie0_2_e_80_qs; + logic ie0_2_e_80_wd; + logic ie0_2_e_81_qs; + logic ie0_2_e_81_wd; + logic ie0_2_e_82_qs; + logic ie0_2_e_82_wd; + logic ie0_2_e_83_qs; + logic ie0_2_e_83_wd; + logic ie0_2_e_84_qs; + logic ie0_2_e_84_wd; + logic ie0_2_e_85_qs; + logic ie0_2_e_85_wd; + logic ie0_2_e_86_qs; + logic ie0_2_e_86_wd; + logic ie0_2_e_87_qs; + logic ie0_2_e_87_wd; + logic ie0_2_e_88_qs; + logic ie0_2_e_88_wd; + logic ie0_2_e_89_qs; + logic ie0_2_e_89_wd; + logic ie0_2_e_90_qs; + logic ie0_2_e_90_wd; + logic ie0_2_e_91_qs; + logic ie0_2_e_91_wd; + logic ie0_2_e_92_qs; + logic ie0_2_e_92_wd; + logic ie0_2_e_93_qs; + logic ie0_2_e_93_wd; + logic ie0_2_e_94_qs; + logic ie0_2_e_94_wd; + logic ie0_2_e_95_qs; + logic ie0_2_e_95_wd; + logic ie0_3_we; + logic ie0_3_e_96_qs; + logic ie0_3_e_96_wd; + logic ie0_3_e_97_qs; + logic ie0_3_e_97_wd; + logic ie0_3_e_98_qs; + logic ie0_3_e_98_wd; + logic ie0_3_e_99_qs; + logic ie0_3_e_99_wd; + logic ie0_3_e_100_qs; + logic ie0_3_e_100_wd; + logic ie0_3_e_101_qs; + logic ie0_3_e_101_wd; + logic ie0_3_e_102_qs; + logic ie0_3_e_102_wd; + logic ie0_3_e_103_qs; + logic ie0_3_e_103_wd; + logic ie0_3_e_104_qs; + logic ie0_3_e_104_wd; + logic ie0_3_e_105_qs; + logic ie0_3_e_105_wd; + logic ie0_3_e_106_qs; + logic ie0_3_e_106_wd; + logic ie0_3_e_107_qs; + logic ie0_3_e_107_wd; + logic ie0_3_e_108_qs; + logic ie0_3_e_108_wd; + logic ie0_3_e_109_qs; + logic ie0_3_e_109_wd; + logic ie0_3_e_110_qs; + logic ie0_3_e_110_wd; + logic ie0_3_e_111_qs; + logic ie0_3_e_111_wd; + logic ie0_3_e_112_qs; + logic ie0_3_e_112_wd; + logic ie0_3_e_113_qs; + logic ie0_3_e_113_wd; + logic ie0_3_e_114_qs; + logic ie0_3_e_114_wd; + logic ie0_3_e_115_qs; + logic ie0_3_e_115_wd; + logic ie0_3_e_116_qs; + logic ie0_3_e_116_wd; + logic ie0_3_e_117_qs; + logic ie0_3_e_117_wd; + logic ie0_3_e_118_qs; + logic ie0_3_e_118_wd; + logic ie0_3_e_119_qs; + logic ie0_3_e_119_wd; + logic ie0_3_e_120_qs; + logic ie0_3_e_120_wd; + logic ie0_3_e_121_qs; + logic ie0_3_e_121_wd; + logic ie0_3_e_122_qs; + logic ie0_3_e_122_wd; + logic ie0_3_e_123_qs; + logic ie0_3_e_123_wd; + logic ie0_3_e_124_qs; + logic ie0_3_e_124_wd; + logic ie0_3_e_125_qs; + logic ie0_3_e_125_wd; + logic ie0_3_e_126_qs; + logic ie0_3_e_126_wd; + logic ie0_3_e_127_qs; + logic ie0_3_e_127_wd; + logic ie0_4_we; + logic ie0_4_e_128_qs; + logic ie0_4_e_128_wd; + logic ie0_4_e_129_qs; + logic ie0_4_e_129_wd; + logic ie0_4_e_130_qs; + logic ie0_4_e_130_wd; + logic ie0_4_e_131_qs; + logic ie0_4_e_131_wd; + logic ie0_4_e_132_qs; + logic ie0_4_e_132_wd; + logic ie0_4_e_133_qs; + logic ie0_4_e_133_wd; + logic ie0_4_e_134_qs; + logic ie0_4_e_134_wd; + logic ie0_4_e_135_qs; + logic ie0_4_e_135_wd; + logic ie0_4_e_136_qs; + logic ie0_4_e_136_wd; + logic ie0_4_e_137_qs; + logic ie0_4_e_137_wd; + logic ie0_4_e_138_qs; + logic ie0_4_e_138_wd; + logic ie0_4_e_139_qs; + logic ie0_4_e_139_wd; + logic ie0_4_e_140_qs; + logic ie0_4_e_140_wd; + logic ie0_4_e_141_qs; + logic ie0_4_e_141_wd; + logic ie0_4_e_142_qs; + logic ie0_4_e_142_wd; + logic ie0_4_e_143_qs; + logic ie0_4_e_143_wd; + logic ie0_4_e_144_qs; + logic ie0_4_e_144_wd; + logic ie0_4_e_145_qs; + logic ie0_4_e_145_wd; + logic ie0_4_e_146_qs; + logic ie0_4_e_146_wd; + logic ie0_4_e_147_qs; + logic ie0_4_e_147_wd; + logic ie0_4_e_148_qs; + logic ie0_4_e_148_wd; + logic ie0_4_e_149_qs; + logic ie0_4_e_149_wd; + logic ie0_4_e_150_qs; + logic ie0_4_e_150_wd; + logic ie0_4_e_151_qs; + logic ie0_4_e_151_wd; + logic ie0_4_e_152_qs; + logic ie0_4_e_152_wd; + logic ie0_4_e_153_qs; + logic ie0_4_e_153_wd; + logic ie0_4_e_154_qs; + logic ie0_4_e_154_wd; + logic ie0_4_e_155_qs; + logic ie0_4_e_155_wd; + logic ie0_4_e_156_qs; + logic ie0_4_e_156_wd; + logic ie0_4_e_157_qs; + logic ie0_4_e_157_wd; + logic ie0_4_e_158_qs; + logic ie0_4_e_158_wd; + logic ie0_4_e_159_qs; + logic ie0_4_e_159_wd; + logic threshold0_we; + logic [1:0] threshold0_qs; + logic [1:0] threshold0_wd; + logic cc0_re; + logic cc0_we; + logic [7:0] cc0_qs; + logic [7:0] cc0_wd; + logic msip0_we; + logic msip0_qs; + logic msip0_wd; + logic alert_test_we; + logic alert_test_wd; + + // Register instances + // R[prio0]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio0_we), + .wd (prio0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio0.q), + .ds (), + + // to register interface (read) + .qs (prio0_qs) + ); + + + // R[prio1]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio1_we), + .wd (prio1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio1.q), + .ds (), + + // to register interface (read) + .qs (prio1_qs) + ); + + + // R[prio2]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio2_we), + .wd (prio2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio2.q), + .ds (), + + // to register interface (read) + .qs (prio2_qs) + ); + + + // R[prio3]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio3_we), + .wd (prio3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio3.q), + .ds (), + + // to register interface (read) + .qs (prio3_qs) + ); + + + // R[prio4]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio4_we), + .wd (prio4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio4.q), + .ds (), + + // to register interface (read) + .qs (prio4_qs) + ); + + + // R[prio5]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio5_we), + .wd (prio5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio5.q), + .ds (), + + // to register interface (read) + .qs (prio5_qs) + ); + + + // R[prio6]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio6_we), + .wd (prio6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio6.q), + .ds (), + + // to register interface (read) + .qs (prio6_qs) + ); + + + // R[prio7]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio7_we), + .wd (prio7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio7.q), + .ds (), + + // to register interface (read) + .qs (prio7_qs) + ); + + + // R[prio8]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio8_we), + .wd (prio8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio8.q), + .ds (), + + // to register interface (read) + .qs (prio8_qs) + ); + + + // R[prio9]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio9_we), + .wd (prio9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio9.q), + .ds (), + + // to register interface (read) + .qs (prio9_qs) + ); + + + // R[prio10]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio10_we), + .wd (prio10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio10.q), + .ds (), + + // to register interface (read) + .qs (prio10_qs) + ); + + + // R[prio11]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio11_we), + .wd (prio11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio11.q), + .ds (), + + // to register interface (read) + .qs (prio11_qs) + ); + + + // R[prio12]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio12_we), + .wd (prio12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio12.q), + .ds (), + + // to register interface (read) + .qs (prio12_qs) + ); + + + // R[prio13]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio13_we), + .wd (prio13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio13.q), + .ds (), + + // to register interface (read) + .qs (prio13_qs) + ); + + + // R[prio14]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio14_we), + .wd (prio14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio14.q), + .ds (), + + // to register interface (read) + .qs (prio14_qs) + ); + + + // R[prio15]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio15_we), + .wd (prio15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio15.q), + .ds (), + + // to register interface (read) + .qs (prio15_qs) + ); + + + // R[prio16]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio16_we), + .wd (prio16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio16.q), + .ds (), + + // to register interface (read) + .qs (prio16_qs) + ); + + + // R[prio17]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio17_we), + .wd (prio17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio17.q), + .ds (), + + // to register interface (read) + .qs (prio17_qs) + ); + + + // R[prio18]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio18_we), + .wd (prio18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio18.q), + .ds (), + + // to register interface (read) + .qs (prio18_qs) + ); + + + // R[prio19]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio19_we), + .wd (prio19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio19.q), + .ds (), + + // to register interface (read) + .qs (prio19_qs) + ); + + + // R[prio20]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio20_we), + .wd (prio20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio20.q), + .ds (), + + // to register interface (read) + .qs (prio20_qs) + ); + + + // R[prio21]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio21_we), + .wd (prio21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio21.q), + .ds (), + + // to register interface (read) + .qs (prio21_qs) + ); + + + // R[prio22]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio22_we), + .wd (prio22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio22.q), + .ds (), + + // to register interface (read) + .qs (prio22_qs) + ); + + + // R[prio23]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio23_we), + .wd (prio23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio23.q), + .ds (), + + // to register interface (read) + .qs (prio23_qs) + ); + + + // R[prio24]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio24_we), + .wd (prio24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio24.q), + .ds (), + + // to register interface (read) + .qs (prio24_qs) + ); + + + // R[prio25]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio25_we), + .wd (prio25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio25.q), + .ds (), + + // to register interface (read) + .qs (prio25_qs) + ); + + + // R[prio26]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio26_we), + .wd (prio26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio26.q), + .ds (), + + // to register interface (read) + .qs (prio26_qs) + ); + + + // R[prio27]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio27_we), + .wd (prio27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio27.q), + .ds (), + + // to register interface (read) + .qs (prio27_qs) + ); + + + // R[prio28]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio28_we), + .wd (prio28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio28.q), + .ds (), + + // to register interface (read) + .qs (prio28_qs) + ); + + + // R[prio29]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio29_we), + .wd (prio29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio29.q), + .ds (), + + // to register interface (read) + .qs (prio29_qs) + ); + + + // R[prio30]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio30_we), + .wd (prio30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio30.q), + .ds (), + + // to register interface (read) + .qs (prio30_qs) + ); + + + // R[prio31]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio31_we), + .wd (prio31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio31.q), + .ds (), + + // to register interface (read) + .qs (prio31_qs) + ); + + + // R[prio32]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio32_we), + .wd (prio32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio32.q), + .ds (), + + // to register interface (read) + .qs (prio32_qs) + ); + + + // R[prio33]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio33_we), + .wd (prio33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio33.q), + .ds (), + + // to register interface (read) + .qs (prio33_qs) + ); + + + // R[prio34]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio34_we), + .wd (prio34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio34.q), + .ds (), + + // to register interface (read) + .qs (prio34_qs) + ); + + + // R[prio35]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio35_we), + .wd (prio35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio35.q), + .ds (), + + // to register interface (read) + .qs (prio35_qs) + ); + + + // R[prio36]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio36_we), + .wd (prio36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio36.q), + .ds (), + + // to register interface (read) + .qs (prio36_qs) + ); + + + // R[prio37]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio37_we), + .wd (prio37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio37.q), + .ds (), + + // to register interface (read) + .qs (prio37_qs) + ); + + + // R[prio38]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio38_we), + .wd (prio38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio38.q), + .ds (), + + // to register interface (read) + .qs (prio38_qs) + ); + + + // R[prio39]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio39_we), + .wd (prio39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio39.q), + .ds (), + + // to register interface (read) + .qs (prio39_qs) + ); + + + // R[prio40]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio40_we), + .wd (prio40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio40.q), + .ds (), + + // to register interface (read) + .qs (prio40_qs) + ); + + + // R[prio41]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio41_we), + .wd (prio41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio41.q), + .ds (), + + // to register interface (read) + .qs (prio41_qs) + ); + + + // R[prio42]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio42_we), + .wd (prio42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio42.q), + .ds (), + + // to register interface (read) + .qs (prio42_qs) + ); + + + // R[prio43]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio43_we), + .wd (prio43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio43.q), + .ds (), + + // to register interface (read) + .qs (prio43_qs) + ); + + + // R[prio44]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio44_we), + .wd (prio44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio44.q), + .ds (), + + // to register interface (read) + .qs (prio44_qs) + ); + + + // R[prio45]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio45_we), + .wd (prio45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio45.q), + .ds (), + + // to register interface (read) + .qs (prio45_qs) + ); + + + // R[prio46]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio46_we), + .wd (prio46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio46.q), + .ds (), + + // to register interface (read) + .qs (prio46_qs) + ); + + + // R[prio47]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio47_we), + .wd (prio47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio47.q), + .ds (), + + // to register interface (read) + .qs (prio47_qs) + ); + + + // R[prio48]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio48_we), + .wd (prio48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio48.q), + .ds (), + + // to register interface (read) + .qs (prio48_qs) + ); + + + // R[prio49]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio49_we), + .wd (prio49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio49.q), + .ds (), + + // to register interface (read) + .qs (prio49_qs) + ); + + + // R[prio50]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio50_we), + .wd (prio50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio50.q), + .ds (), + + // to register interface (read) + .qs (prio50_qs) + ); + + + // R[prio51]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio51_we), + .wd (prio51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio51.q), + .ds (), + + // to register interface (read) + .qs (prio51_qs) + ); + + + // R[prio52]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio52_we), + .wd (prio52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio52.q), + .ds (), + + // to register interface (read) + .qs (prio52_qs) + ); + + + // R[prio53]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio53_we), + .wd (prio53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio53.q), + .ds (), + + // to register interface (read) + .qs (prio53_qs) + ); + + + // R[prio54]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio54_we), + .wd (prio54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio54.q), + .ds (), + + // to register interface (read) + .qs (prio54_qs) + ); + + + // R[prio55]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio55_we), + .wd (prio55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio55.q), + .ds (), + + // to register interface (read) + .qs (prio55_qs) + ); + + + // R[prio56]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio56_we), + .wd (prio56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio56.q), + .ds (), + + // to register interface (read) + .qs (prio56_qs) + ); + + + // R[prio57]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio57_we), + .wd (prio57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio57.q), + .ds (), + + // to register interface (read) + .qs (prio57_qs) + ); + + + // R[prio58]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio58_we), + .wd (prio58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio58.q), + .ds (), + + // to register interface (read) + .qs (prio58_qs) + ); + + + // R[prio59]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio59_we), + .wd (prio59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio59.q), + .ds (), + + // to register interface (read) + .qs (prio59_qs) + ); + + + // R[prio60]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio60_we), + .wd (prio60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio60.q), + .ds (), + + // to register interface (read) + .qs (prio60_qs) + ); + + + // R[prio61]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio61_we), + .wd (prio61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio61.q), + .ds (), + + // to register interface (read) + .qs (prio61_qs) + ); + + + // R[prio62]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio62_we), + .wd (prio62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio62.q), + .ds (), + + // to register interface (read) + .qs (prio62_qs) + ); + + + // R[prio63]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio63_we), + .wd (prio63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio63.q), + .ds (), + + // to register interface (read) + .qs (prio63_qs) + ); + + + // R[prio64]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio64_we), + .wd (prio64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio64.q), + .ds (), + + // to register interface (read) + .qs (prio64_qs) + ); + + + // R[prio65]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio65_we), + .wd (prio65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio65.q), + .ds (), + + // to register interface (read) + .qs (prio65_qs) + ); + + + // R[prio66]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio66_we), + .wd (prio66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio66.q), + .ds (), + + // to register interface (read) + .qs (prio66_qs) + ); + + + // R[prio67]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio67_we), + .wd (prio67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio67.q), + .ds (), + + // to register interface (read) + .qs (prio67_qs) + ); + + + // R[prio68]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio68_we), + .wd (prio68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio68.q), + .ds (), + + // to register interface (read) + .qs (prio68_qs) + ); + + + // R[prio69]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio69_we), + .wd (prio69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio69.q), + .ds (), + + // to register interface (read) + .qs (prio69_qs) + ); + + + // R[prio70]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio70_we), + .wd (prio70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio70.q), + .ds (), + + // to register interface (read) + .qs (prio70_qs) + ); + + + // R[prio71]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio71_we), + .wd (prio71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio71.q), + .ds (), + + // to register interface (read) + .qs (prio71_qs) + ); + + + // R[prio72]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio72_we), + .wd (prio72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio72.q), + .ds (), + + // to register interface (read) + .qs (prio72_qs) + ); + + + // R[prio73]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio73_we), + .wd (prio73_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio73.q), + .ds (), + + // to register interface (read) + .qs (prio73_qs) + ); + + + // R[prio74]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio74_we), + .wd (prio74_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio74.q), + .ds (), + + // to register interface (read) + .qs (prio74_qs) + ); + + + // R[prio75]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio75_we), + .wd (prio75_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio75.q), + .ds (), + + // to register interface (read) + .qs (prio75_qs) + ); + + + // R[prio76]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio76_we), + .wd (prio76_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio76.q), + .ds (), + + // to register interface (read) + .qs (prio76_qs) + ); + + + // R[prio77]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio77_we), + .wd (prio77_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio77.q), + .ds (), + + // to register interface (read) + .qs (prio77_qs) + ); + + + // R[prio78]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio78_we), + .wd (prio78_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio78.q), + .ds (), + + // to register interface (read) + .qs (prio78_qs) + ); + + + // R[prio79]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio79_we), + .wd (prio79_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio79.q), + .ds (), + + // to register interface (read) + .qs (prio79_qs) + ); + + + // R[prio80]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio80_we), + .wd (prio80_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio80.q), + .ds (), + + // to register interface (read) + .qs (prio80_qs) + ); + + + // R[prio81]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio81_we), + .wd (prio81_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio81.q), + .ds (), + + // to register interface (read) + .qs (prio81_qs) + ); + + + // R[prio82]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio82_we), + .wd (prio82_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio82.q), + .ds (), + + // to register interface (read) + .qs (prio82_qs) + ); + + + // R[prio83]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio83_we), + .wd (prio83_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio83.q), + .ds (), + + // to register interface (read) + .qs (prio83_qs) + ); + + + // R[prio84]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio84_we), + .wd (prio84_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio84.q), + .ds (), + + // to register interface (read) + .qs (prio84_qs) + ); + + + // R[prio85]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio85_we), + .wd (prio85_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio85.q), + .ds (), + + // to register interface (read) + .qs (prio85_qs) + ); + + + // R[prio86]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio86_we), + .wd (prio86_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio86.q), + .ds (), + + // to register interface (read) + .qs (prio86_qs) + ); + + + // R[prio87]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio87_we), + .wd (prio87_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio87.q), + .ds (), + + // to register interface (read) + .qs (prio87_qs) + ); + + + // R[prio88]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio88_we), + .wd (prio88_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio88.q), + .ds (), + + // to register interface (read) + .qs (prio88_qs) + ); + + + // R[prio89]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio89_we), + .wd (prio89_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio89.q), + .ds (), + + // to register interface (read) + .qs (prio89_qs) + ); + + + // R[prio90]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio90_we), + .wd (prio90_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio90.q), + .ds (), + + // to register interface (read) + .qs (prio90_qs) + ); + + + // R[prio91]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio91_we), + .wd (prio91_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio91.q), + .ds (), + + // to register interface (read) + .qs (prio91_qs) + ); + + + // R[prio92]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio92_we), + .wd (prio92_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio92.q), + .ds (), + + // to register interface (read) + .qs (prio92_qs) + ); + + + // R[prio93]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio93_we), + .wd (prio93_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio93.q), + .ds (), + + // to register interface (read) + .qs (prio93_qs) + ); + + + // R[prio94]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio94_we), + .wd (prio94_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio94.q), + .ds (), + + // to register interface (read) + .qs (prio94_qs) + ); + + + // R[prio95]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio95_we), + .wd (prio95_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio95.q), + .ds (), + + // to register interface (read) + .qs (prio95_qs) + ); + + + // R[prio96]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio96_we), + .wd (prio96_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio96.q), + .ds (), + + // to register interface (read) + .qs (prio96_qs) + ); + + + // R[prio97]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio97_we), + .wd (prio97_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio97.q), + .ds (), + + // to register interface (read) + .qs (prio97_qs) + ); + + + // R[prio98]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio98_we), + .wd (prio98_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio98.q), + .ds (), + + // to register interface (read) + .qs (prio98_qs) + ); + + + // R[prio99]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio99 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio99_we), + .wd (prio99_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio99.q), + .ds (), + + // to register interface (read) + .qs (prio99_qs) + ); + + + // R[prio100]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio100 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio100_we), + .wd (prio100_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio100.q), + .ds (), + + // to register interface (read) + .qs (prio100_qs) + ); + + + // R[prio101]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio101 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio101_we), + .wd (prio101_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio101.q), + .ds (), + + // to register interface (read) + .qs (prio101_qs) + ); + + + // R[prio102]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio102 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio102_we), + .wd (prio102_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio102.q), + .ds (), + + // to register interface (read) + .qs (prio102_qs) + ); + + + // R[prio103]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio103 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio103_we), + .wd (prio103_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio103.q), + .ds (), + + // to register interface (read) + .qs (prio103_qs) + ); + + + // R[prio104]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio104 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio104_we), + .wd (prio104_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio104.q), + .ds (), + + // to register interface (read) + .qs (prio104_qs) + ); + + + // R[prio105]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio105 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio105_we), + .wd (prio105_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio105.q), + .ds (), + + // to register interface (read) + .qs (prio105_qs) + ); + + + // R[prio106]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio106 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio106_we), + .wd (prio106_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio106.q), + .ds (), + + // to register interface (read) + .qs (prio106_qs) + ); + + + // R[prio107]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio107 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio107_we), + .wd (prio107_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio107.q), + .ds (), + + // to register interface (read) + .qs (prio107_qs) + ); + + + // R[prio108]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio108 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio108_we), + .wd (prio108_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio108.q), + .ds (), + + // to register interface (read) + .qs (prio108_qs) + ); + + + // R[prio109]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio109 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio109_we), + .wd (prio109_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio109.q), + .ds (), + + // to register interface (read) + .qs (prio109_qs) + ); + + + // R[prio110]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio110 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio110_we), + .wd (prio110_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio110.q), + .ds (), + + // to register interface (read) + .qs (prio110_qs) + ); + + + // R[prio111]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio111 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio111_we), + .wd (prio111_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio111.q), + .ds (), + + // to register interface (read) + .qs (prio111_qs) + ); + + + // R[prio112]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio112 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio112_we), + .wd (prio112_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio112.q), + .ds (), + + // to register interface (read) + .qs (prio112_qs) + ); + + + // R[prio113]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio113 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio113_we), + .wd (prio113_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio113.q), + .ds (), + + // to register interface (read) + .qs (prio113_qs) + ); + + + // R[prio114]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio114 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio114_we), + .wd (prio114_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio114.q), + .ds (), + + // to register interface (read) + .qs (prio114_qs) + ); + + + // R[prio115]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio115 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio115_we), + .wd (prio115_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio115.q), + .ds (), + + // to register interface (read) + .qs (prio115_qs) + ); + + + // R[prio116]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio116 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio116_we), + .wd (prio116_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio116.q), + .ds (), + + // to register interface (read) + .qs (prio116_qs) + ); + + + // R[prio117]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio117 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio117_we), + .wd (prio117_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio117.q), + .ds (), + + // to register interface (read) + .qs (prio117_qs) + ); + + + // R[prio118]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio118 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio118_we), + .wd (prio118_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio118.q), + .ds (), + + // to register interface (read) + .qs (prio118_qs) + ); + + + // R[prio119]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio119 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio119_we), + .wd (prio119_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio119.q), + .ds (), + + // to register interface (read) + .qs (prio119_qs) + ); + + + // R[prio120]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio120 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio120_we), + .wd (prio120_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio120.q), + .ds (), + + // to register interface (read) + .qs (prio120_qs) + ); + + + // R[prio121]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio121 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio121_we), + .wd (prio121_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio121.q), + .ds (), + + // to register interface (read) + .qs (prio121_qs) + ); + + + // R[prio122]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio122 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio122_we), + .wd (prio122_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio122.q), + .ds (), + + // to register interface (read) + .qs (prio122_qs) + ); + + + // R[prio123]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio123 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio123_we), + .wd (prio123_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio123.q), + .ds (), + + // to register interface (read) + .qs (prio123_qs) + ); + + + // R[prio124]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio124 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio124_we), + .wd (prio124_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio124.q), + .ds (), + + // to register interface (read) + .qs (prio124_qs) + ); + + + // R[prio125]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio125 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio125_we), + .wd (prio125_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio125.q), + .ds (), + + // to register interface (read) + .qs (prio125_qs) + ); + + + // R[prio126]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio126 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio126_we), + .wd (prio126_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio126.q), + .ds (), + + // to register interface (read) + .qs (prio126_qs) + ); + + + // R[prio127]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio127 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio127_we), + .wd (prio127_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio127.q), + .ds (), + + // to register interface (read) + .qs (prio127_qs) + ); + + + // R[prio128]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio128 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio128_we), + .wd (prio128_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio128.q), + .ds (), + + // to register interface (read) + .qs (prio128_qs) + ); + + + // R[prio129]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio129 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio129_we), + .wd (prio129_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio129.q), + .ds (), + + // to register interface (read) + .qs (prio129_qs) + ); + + + // R[prio130]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio130 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio130_we), + .wd (prio130_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio130.q), + .ds (), + + // to register interface (read) + .qs (prio130_qs) + ); + + + // R[prio131]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio131 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio131_we), + .wd (prio131_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio131.q), + .ds (), + + // to register interface (read) + .qs (prio131_qs) + ); + + + // R[prio132]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio132 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio132_we), + .wd (prio132_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio132.q), + .ds (), + + // to register interface (read) + .qs (prio132_qs) + ); + + + // R[prio133]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio133 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio133_we), + .wd (prio133_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio133.q), + .ds (), + + // to register interface (read) + .qs (prio133_qs) + ); + + + // R[prio134]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio134 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio134_we), + .wd (prio134_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio134.q), + .ds (), + + // to register interface (read) + .qs (prio134_qs) + ); + + + // R[prio135]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio135 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio135_we), + .wd (prio135_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio135.q), + .ds (), + + // to register interface (read) + .qs (prio135_qs) + ); + + + // R[prio136]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio136 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio136_we), + .wd (prio136_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio136.q), + .ds (), + + // to register interface (read) + .qs (prio136_qs) + ); + + + // R[prio137]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio137 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio137_we), + .wd (prio137_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio137.q), + .ds (), + + // to register interface (read) + .qs (prio137_qs) + ); + + + // R[prio138]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio138 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio138_we), + .wd (prio138_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio138.q), + .ds (), + + // to register interface (read) + .qs (prio138_qs) + ); + + + // R[prio139]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio139 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio139_we), + .wd (prio139_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio139.q), + .ds (), + + // to register interface (read) + .qs (prio139_qs) + ); + + + // R[prio140]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio140 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio140_we), + .wd (prio140_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio140.q), + .ds (), + + // to register interface (read) + .qs (prio140_qs) + ); + + + // R[prio141]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio141 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio141_we), + .wd (prio141_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio141.q), + .ds (), + + // to register interface (read) + .qs (prio141_qs) + ); + + + // R[prio142]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio142 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio142_we), + .wd (prio142_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio142.q), + .ds (), + + // to register interface (read) + .qs (prio142_qs) + ); + + + // R[prio143]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio143 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio143_we), + .wd (prio143_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio143.q), + .ds (), + + // to register interface (read) + .qs (prio143_qs) + ); + + + // R[prio144]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio144 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio144_we), + .wd (prio144_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio144.q), + .ds (), + + // to register interface (read) + .qs (prio144_qs) + ); + + + // R[prio145]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio145 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio145_we), + .wd (prio145_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio145.q), + .ds (), + + // to register interface (read) + .qs (prio145_qs) + ); + + + // R[prio146]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio146 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio146_we), + .wd (prio146_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio146.q), + .ds (), + + // to register interface (read) + .qs (prio146_qs) + ); + + + // R[prio147]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio147 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio147_we), + .wd (prio147_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio147.q), + .ds (), + + // to register interface (read) + .qs (prio147_qs) + ); + + + // R[prio148]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio148 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio148_we), + .wd (prio148_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio148.q), + .ds (), + + // to register interface (read) + .qs (prio148_qs) + ); + + + // R[prio149]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio149 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio149_we), + .wd (prio149_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio149.q), + .ds (), + + // to register interface (read) + .qs (prio149_qs) + ); + + + // R[prio150]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio150 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio150_we), + .wd (prio150_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio150.q), + .ds (), + + // to register interface (read) + .qs (prio150_qs) + ); + + + // R[prio151]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio151 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio151_we), + .wd (prio151_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio151.q), + .ds (), + + // to register interface (read) + .qs (prio151_qs) + ); + + + // R[prio152]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio152 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio152_we), + .wd (prio152_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio152.q), + .ds (), + + // to register interface (read) + .qs (prio152_qs) + ); + + + // R[prio153]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio153 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio153_we), + .wd (prio153_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio153.q), + .ds (), + + // to register interface (read) + .qs (prio153_qs) + ); + + + // R[prio154]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio154 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio154_we), + .wd (prio154_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio154.q), + .ds (), + + // to register interface (read) + .qs (prio154_qs) + ); + + + // R[prio155]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio155 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio155_we), + .wd (prio155_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio155.q), + .ds (), + + // to register interface (read) + .qs (prio155_qs) + ); + + + // R[prio156]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio156 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio156_we), + .wd (prio156_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio156.q), + .ds (), + + // to register interface (read) + .qs (prio156_qs) + ); + + + // R[prio157]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio157 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio157_we), + .wd (prio157_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio157.q), + .ds (), + + // to register interface (read) + .qs (prio157_qs) + ); + + + // R[prio158]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio158 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio158_we), + .wd (prio158_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio158.q), + .ds (), + + // to register interface (read) + .qs (prio158_qs) + ); + + + // R[prio159]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio159 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio159_we), + .wd (prio159_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio159.q), + .ds (), + + // to register interface (read) + .qs (prio159_qs) + ); + + + // Subregister 0 of Multireg ip + // R[ip_0]: V(False) + // F[p_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[0].de), + .d (hw2reg.ip[0].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_0_qs) + ); + + // F[p_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[1].de), + .d (hw2reg.ip[1].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_1_qs) + ); + + // F[p_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[2].de), + .d (hw2reg.ip[2].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_2_qs) + ); + + // F[p_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[3].de), + .d (hw2reg.ip[3].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_3_qs) + ); + + // F[p_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[4].de), + .d (hw2reg.ip[4].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_4_qs) + ); + + // F[p_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[5].de), + .d (hw2reg.ip[5].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_5_qs) + ); + + // F[p_6]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[6].de), + .d (hw2reg.ip[6].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_6_qs) + ); + + // F[p_7]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[7].de), + .d (hw2reg.ip[7].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_7_qs) + ); + + // F[p_8]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[8].de), + .d (hw2reg.ip[8].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_8_qs) + ); + + // F[p_9]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[9].de), + .d (hw2reg.ip[9].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_9_qs) + ); + + // F[p_10]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[10].de), + .d (hw2reg.ip[10].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_10_qs) + ); + + // F[p_11]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[11].de), + .d (hw2reg.ip[11].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_11_qs) + ); + + // F[p_12]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[12].de), + .d (hw2reg.ip[12].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_12_qs) + ); + + // F[p_13]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[13].de), + .d (hw2reg.ip[13].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_13_qs) + ); + + // F[p_14]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[14].de), + .d (hw2reg.ip[14].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_14_qs) + ); + + // F[p_15]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[15].de), + .d (hw2reg.ip[15].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_15_qs) + ); + + // F[p_16]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[16].de), + .d (hw2reg.ip[16].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_16_qs) + ); + + // F[p_17]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[17].de), + .d (hw2reg.ip[17].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_17_qs) + ); + + // F[p_18]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[18].de), + .d (hw2reg.ip[18].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_18_qs) + ); + + // F[p_19]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[19].de), + .d (hw2reg.ip[19].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_19_qs) + ); + + // F[p_20]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[20].de), + .d (hw2reg.ip[20].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_20_qs) + ); + + // F[p_21]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[21].de), + .d (hw2reg.ip[21].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_21_qs) + ); + + // F[p_22]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[22].de), + .d (hw2reg.ip[22].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_22_qs) + ); + + // F[p_23]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[23].de), + .d (hw2reg.ip[23].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_23_qs) + ); + + // F[p_24]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[24].de), + .d (hw2reg.ip[24].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_24_qs) + ); + + // F[p_25]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[25].de), + .d (hw2reg.ip[25].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_25_qs) + ); + + // F[p_26]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[26].de), + .d (hw2reg.ip[26].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_26_qs) + ); + + // F[p_27]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[27].de), + .d (hw2reg.ip[27].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_27_qs) + ); + + // F[p_28]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[28].de), + .d (hw2reg.ip[28].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_28_qs) + ); + + // F[p_29]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[29].de), + .d (hw2reg.ip[29].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_29_qs) + ); + + // F[p_30]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[30].de), + .d (hw2reg.ip[30].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_30_qs) + ); + + // F[p_31]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[31].de), + .d (hw2reg.ip[31].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_31_qs) + ); + + + // Subregister 1 of Multireg ip + // R[ip_1]: V(False) + // F[p_32]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[32].de), + .d (hw2reg.ip[32].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_32_qs) + ); + + // F[p_33]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[33].de), + .d (hw2reg.ip[33].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_33_qs) + ); + + // F[p_34]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[34].de), + .d (hw2reg.ip[34].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_34_qs) + ); + + // F[p_35]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[35].de), + .d (hw2reg.ip[35].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_35_qs) + ); + + // F[p_36]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[36].de), + .d (hw2reg.ip[36].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_36_qs) + ); + + // F[p_37]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[37].de), + .d (hw2reg.ip[37].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_37_qs) + ); + + // F[p_38]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[38].de), + .d (hw2reg.ip[38].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_38_qs) + ); + + // F[p_39]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[39].de), + .d (hw2reg.ip[39].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_39_qs) + ); + + // F[p_40]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[40].de), + .d (hw2reg.ip[40].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_40_qs) + ); + + // F[p_41]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[41].de), + .d (hw2reg.ip[41].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_41_qs) + ); + + // F[p_42]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[42].de), + .d (hw2reg.ip[42].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_42_qs) + ); + + // F[p_43]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[43].de), + .d (hw2reg.ip[43].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_43_qs) + ); + + // F[p_44]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[44].de), + .d (hw2reg.ip[44].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_44_qs) + ); + + // F[p_45]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[45].de), + .d (hw2reg.ip[45].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_45_qs) + ); + + // F[p_46]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[46].de), + .d (hw2reg.ip[46].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_46_qs) + ); + + // F[p_47]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[47].de), + .d (hw2reg.ip[47].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_47_qs) + ); + + // F[p_48]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[48].de), + .d (hw2reg.ip[48].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_48_qs) + ); + + // F[p_49]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[49].de), + .d (hw2reg.ip[49].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_49_qs) + ); + + // F[p_50]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[50].de), + .d (hw2reg.ip[50].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_50_qs) + ); + + // F[p_51]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[51].de), + .d (hw2reg.ip[51].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_51_qs) + ); + + // F[p_52]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[52].de), + .d (hw2reg.ip[52].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_52_qs) + ); + + // F[p_53]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[53].de), + .d (hw2reg.ip[53].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_53_qs) + ); + + // F[p_54]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[54].de), + .d (hw2reg.ip[54].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_54_qs) + ); + + // F[p_55]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[55].de), + .d (hw2reg.ip[55].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_55_qs) + ); + + // F[p_56]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[56].de), + .d (hw2reg.ip[56].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_56_qs) + ); + + // F[p_57]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[57].de), + .d (hw2reg.ip[57].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_57_qs) + ); + + // F[p_58]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[58].de), + .d (hw2reg.ip[58].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_58_qs) + ); + + // F[p_59]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[59].de), + .d (hw2reg.ip[59].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_59_qs) + ); + + // F[p_60]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[60].de), + .d (hw2reg.ip[60].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_60_qs) + ); + + // F[p_61]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[61].de), + .d (hw2reg.ip[61].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_61_qs) + ); + + // F[p_62]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[62].de), + .d (hw2reg.ip[62].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_62_qs) + ); + + // F[p_63]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[63].de), + .d (hw2reg.ip[63].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_63_qs) + ); + + + // Subregister 2 of Multireg ip + // R[ip_2]: V(False) + // F[p_64]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[64].de), + .d (hw2reg.ip[64].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_64_qs) + ); + + // F[p_65]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[65].de), + .d (hw2reg.ip[65].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_65_qs) + ); + + // F[p_66]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[66].de), + .d (hw2reg.ip[66].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_66_qs) + ); + + // F[p_67]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[67].de), + .d (hw2reg.ip[67].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_67_qs) + ); + + // F[p_68]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[68].de), + .d (hw2reg.ip[68].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_68_qs) + ); + + // F[p_69]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[69].de), + .d (hw2reg.ip[69].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_69_qs) + ); + + // F[p_70]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[70].de), + .d (hw2reg.ip[70].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_70_qs) + ); + + // F[p_71]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[71].de), + .d (hw2reg.ip[71].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_71_qs) + ); + + // F[p_72]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[72].de), + .d (hw2reg.ip[72].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_72_qs) + ); + + // F[p_73]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[73].de), + .d (hw2reg.ip[73].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_73_qs) + ); + + // F[p_74]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[74].de), + .d (hw2reg.ip[74].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_74_qs) + ); + + // F[p_75]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[75].de), + .d (hw2reg.ip[75].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_75_qs) + ); + + // F[p_76]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[76].de), + .d (hw2reg.ip[76].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_76_qs) + ); + + // F[p_77]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[77].de), + .d (hw2reg.ip[77].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_77_qs) + ); + + // F[p_78]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[78].de), + .d (hw2reg.ip[78].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_78_qs) + ); + + // F[p_79]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[79].de), + .d (hw2reg.ip[79].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_79_qs) + ); + + // F[p_80]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[80].de), + .d (hw2reg.ip[80].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_80_qs) + ); + + // F[p_81]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[81].de), + .d (hw2reg.ip[81].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_81_qs) + ); + + // F[p_82]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[82].de), + .d (hw2reg.ip[82].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_82_qs) + ); + + // F[p_83]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[83].de), + .d (hw2reg.ip[83].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_83_qs) + ); + + // F[p_84]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[84].de), + .d (hw2reg.ip[84].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_84_qs) + ); + + // F[p_85]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[85].de), + .d (hw2reg.ip[85].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_85_qs) + ); + + // F[p_86]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[86].de), + .d (hw2reg.ip[86].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_86_qs) + ); + + // F[p_87]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[87].de), + .d (hw2reg.ip[87].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_87_qs) + ); + + // F[p_88]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[88].de), + .d (hw2reg.ip[88].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_88_qs) + ); + + // F[p_89]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[89].de), + .d (hw2reg.ip[89].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_89_qs) + ); + + // F[p_90]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[90].de), + .d (hw2reg.ip[90].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_90_qs) + ); + + // F[p_91]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[91].de), + .d (hw2reg.ip[91].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_91_qs) + ); + + // F[p_92]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[92].de), + .d (hw2reg.ip[92].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_92_qs) + ); + + // F[p_93]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[93].de), + .d (hw2reg.ip[93].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_93_qs) + ); + + // F[p_94]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[94].de), + .d (hw2reg.ip[94].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_94_qs) + ); + + // F[p_95]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[95].de), + .d (hw2reg.ip[95].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_95_qs) + ); + + + // Subregister 3 of Multireg ip + // R[ip_3]: V(False) + // F[p_96]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[96].de), + .d (hw2reg.ip[96].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_96_qs) + ); + + // F[p_97]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[97].de), + .d (hw2reg.ip[97].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_97_qs) + ); + + // F[p_98]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[98].de), + .d (hw2reg.ip[98].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_98_qs) + ); + + // F[p_99]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_99 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[99].de), + .d (hw2reg.ip[99].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_99_qs) + ); + + // F[p_100]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_100 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[100].de), + .d (hw2reg.ip[100].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_100_qs) + ); + + // F[p_101]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_101 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[101].de), + .d (hw2reg.ip[101].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_101_qs) + ); + + // F[p_102]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_102 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[102].de), + .d (hw2reg.ip[102].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_102_qs) + ); + + // F[p_103]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_103 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[103].de), + .d (hw2reg.ip[103].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_103_qs) + ); + + // F[p_104]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_104 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[104].de), + .d (hw2reg.ip[104].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_104_qs) + ); + + // F[p_105]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_105 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[105].de), + .d (hw2reg.ip[105].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_105_qs) + ); + + // F[p_106]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_106 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[106].de), + .d (hw2reg.ip[106].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_106_qs) + ); + + // F[p_107]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_107 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[107].de), + .d (hw2reg.ip[107].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_107_qs) + ); + + // F[p_108]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_108 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[108].de), + .d (hw2reg.ip[108].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_108_qs) + ); + + // F[p_109]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_109 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[109].de), + .d (hw2reg.ip[109].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_109_qs) + ); + + // F[p_110]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_110 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[110].de), + .d (hw2reg.ip[110].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_110_qs) + ); + + // F[p_111]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_111 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[111].de), + .d (hw2reg.ip[111].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_111_qs) + ); + + // F[p_112]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_112 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[112].de), + .d (hw2reg.ip[112].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_112_qs) + ); + + // F[p_113]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_113 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[113].de), + .d (hw2reg.ip[113].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_113_qs) + ); + + // F[p_114]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_114 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[114].de), + .d (hw2reg.ip[114].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_114_qs) + ); + + // F[p_115]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_115 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[115].de), + .d (hw2reg.ip[115].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_115_qs) + ); + + // F[p_116]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_116 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[116].de), + .d (hw2reg.ip[116].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_116_qs) + ); + + // F[p_117]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_117 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[117].de), + .d (hw2reg.ip[117].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_117_qs) + ); + + // F[p_118]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_118 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[118].de), + .d (hw2reg.ip[118].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_118_qs) + ); + + // F[p_119]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_119 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[119].de), + .d (hw2reg.ip[119].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_119_qs) + ); + + // F[p_120]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_120 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[120].de), + .d (hw2reg.ip[120].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_120_qs) + ); + + // F[p_121]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_121 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[121].de), + .d (hw2reg.ip[121].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_121_qs) + ); + + // F[p_122]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_122 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[122].de), + .d (hw2reg.ip[122].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_122_qs) + ); + + // F[p_123]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_123 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[123].de), + .d (hw2reg.ip[123].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_123_qs) + ); + + // F[p_124]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_124 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[124].de), + .d (hw2reg.ip[124].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_124_qs) + ); + + // F[p_125]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_125 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[125].de), + .d (hw2reg.ip[125].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_125_qs) + ); + + // F[p_126]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_126 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[126].de), + .d (hw2reg.ip[126].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_126_qs) + ); + + // F[p_127]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_127 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[127].de), + .d (hw2reg.ip[127].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_127_qs) + ); + + + // Subregister 4 of Multireg ip + // R[ip_4]: V(False) + // F[p_128]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_128 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[128].de), + .d (hw2reg.ip[128].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_128_qs) + ); + + // F[p_129]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_129 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[129].de), + .d (hw2reg.ip[129].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_129_qs) + ); + + // F[p_130]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_130 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[130].de), + .d (hw2reg.ip[130].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_130_qs) + ); + + // F[p_131]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_131 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[131].de), + .d (hw2reg.ip[131].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_131_qs) + ); + + // F[p_132]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_132 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[132].de), + .d (hw2reg.ip[132].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_132_qs) + ); + + // F[p_133]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_133 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[133].de), + .d (hw2reg.ip[133].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_133_qs) + ); + + // F[p_134]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_134 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[134].de), + .d (hw2reg.ip[134].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_134_qs) + ); + + // F[p_135]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_135 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[135].de), + .d (hw2reg.ip[135].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_135_qs) + ); + + // F[p_136]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_136 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[136].de), + .d (hw2reg.ip[136].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_136_qs) + ); + + // F[p_137]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_137 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[137].de), + .d (hw2reg.ip[137].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_137_qs) + ); + + // F[p_138]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_138 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[138].de), + .d (hw2reg.ip[138].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_138_qs) + ); + + // F[p_139]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_139 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[139].de), + .d (hw2reg.ip[139].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_139_qs) + ); + + // F[p_140]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_140 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[140].de), + .d (hw2reg.ip[140].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_140_qs) + ); + + // F[p_141]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_141 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[141].de), + .d (hw2reg.ip[141].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_141_qs) + ); + + // F[p_142]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_142 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[142].de), + .d (hw2reg.ip[142].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_142_qs) + ); + + // F[p_143]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_143 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[143].de), + .d (hw2reg.ip[143].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_143_qs) + ); + + // F[p_144]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_144 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[144].de), + .d (hw2reg.ip[144].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_144_qs) + ); + + // F[p_145]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_145 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[145].de), + .d (hw2reg.ip[145].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_145_qs) + ); + + // F[p_146]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_146 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[146].de), + .d (hw2reg.ip[146].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_146_qs) + ); + + // F[p_147]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_147 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[147].de), + .d (hw2reg.ip[147].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_147_qs) + ); + + // F[p_148]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_148 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[148].de), + .d (hw2reg.ip[148].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_148_qs) + ); + + // F[p_149]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_149 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[149].de), + .d (hw2reg.ip[149].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_149_qs) + ); + + // F[p_150]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_150 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[150].de), + .d (hw2reg.ip[150].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_150_qs) + ); + + // F[p_151]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_151 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[151].de), + .d (hw2reg.ip[151].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_151_qs) + ); + + // F[p_152]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_152 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[152].de), + .d (hw2reg.ip[152].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_152_qs) + ); + + // F[p_153]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_153 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[153].de), + .d (hw2reg.ip[153].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_153_qs) + ); + + // F[p_154]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_154 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[154].de), + .d (hw2reg.ip[154].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_154_qs) + ); + + // F[p_155]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_155 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[155].de), + .d (hw2reg.ip[155].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_155_qs) + ); + + // F[p_156]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_156 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[156].de), + .d (hw2reg.ip[156].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_156_qs) + ); + + // F[p_157]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_157 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[157].de), + .d (hw2reg.ip[157].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_157_qs) + ); + + // F[p_158]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_158 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[158].de), + .d (hw2reg.ip[158].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_158_qs) + ); + + // F[p_159]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_159 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[159].de), + .d (hw2reg.ip[159].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_159_qs) + ); + + + // Subregister 0 of Multireg ie0 + // R[ie0_0]: V(False) + // F[e_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[0].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_0_qs) + ); + + // F[e_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[1].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_1_qs) + ); + + // F[e_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[2].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_2_qs) + ); + + // F[e_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[3].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_3_qs) + ); + + // F[e_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[4].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_4_qs) + ); + + // F[e_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[5].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_5_qs) + ); + + // F[e_6]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[6].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_6_qs) + ); + + // F[e_7]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[7].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_7_qs) + ); + + // F[e_8]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[8].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_8_qs) + ); + + // F[e_9]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[9].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_9_qs) + ); + + // F[e_10]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[10].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_10_qs) + ); + + // F[e_11]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[11].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_11_qs) + ); + + // F[e_12]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[12].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_12_qs) + ); + + // F[e_13]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[13].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_13_qs) + ); + + // F[e_14]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[14].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_14_qs) + ); + + // F[e_15]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[15].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_15_qs) + ); + + // F[e_16]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[16].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_16_qs) + ); + + // F[e_17]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[17].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_17_qs) + ); + + // F[e_18]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[18].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_18_qs) + ); + + // F[e_19]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[19].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_19_qs) + ); + + // F[e_20]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[20].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_20_qs) + ); + + // F[e_21]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[21].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_21_qs) + ); + + // F[e_22]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[22].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_22_qs) + ); + + // F[e_23]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[23].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_23_qs) + ); + + // F[e_24]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[24].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_24_qs) + ); + + // F[e_25]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[25].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_25_qs) + ); + + // F[e_26]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[26].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_26_qs) + ); + + // F[e_27]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[27].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_27_qs) + ); + + // F[e_28]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[28].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_28_qs) + ); + + // F[e_29]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[29].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_29_qs) + ); + + // F[e_30]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[30].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_30_qs) + ); + + // F[e_31]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[31].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_31_qs) + ); + + + // Subregister 1 of Multireg ie0 + // R[ie0_1]: V(False) + // F[e_32]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[32].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_32_qs) + ); + + // F[e_33]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[33].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_33_qs) + ); + + // F[e_34]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[34].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_34_qs) + ); + + // F[e_35]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[35].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_35_qs) + ); + + // F[e_36]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[36].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_36_qs) + ); + + // F[e_37]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[37].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_37_qs) + ); + + // F[e_38]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[38].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_38_qs) + ); + + // F[e_39]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[39].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_39_qs) + ); + + // F[e_40]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[40].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_40_qs) + ); + + // F[e_41]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[41].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_41_qs) + ); + + // F[e_42]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[42].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_42_qs) + ); + + // F[e_43]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[43].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_43_qs) + ); + + // F[e_44]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[44].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_44_qs) + ); + + // F[e_45]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[45].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_45_qs) + ); + + // F[e_46]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[46].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_46_qs) + ); + + // F[e_47]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[47].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_47_qs) + ); + + // F[e_48]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[48].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_48_qs) + ); + + // F[e_49]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[49].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_49_qs) + ); + + // F[e_50]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[50].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_50_qs) + ); + + // F[e_51]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[51].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_51_qs) + ); + + // F[e_52]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[52].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_52_qs) + ); + + // F[e_53]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[53].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_53_qs) + ); + + // F[e_54]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[54].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_54_qs) + ); + + // F[e_55]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[55].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_55_qs) + ); + + // F[e_56]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[56].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_56_qs) + ); + + // F[e_57]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[57].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_57_qs) + ); + + // F[e_58]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[58].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_58_qs) + ); + + // F[e_59]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[59].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_59_qs) + ); + + // F[e_60]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[60].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_60_qs) + ); + + // F[e_61]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[61].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_61_qs) + ); + + // F[e_62]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[62].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_62_qs) + ); + + // F[e_63]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[63].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_63_qs) + ); + + + // Subregister 2 of Multireg ie0 + // R[ie0_2]: V(False) + // F[e_64]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[64].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_64_qs) + ); + + // F[e_65]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[65].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_65_qs) + ); + + // F[e_66]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[66].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_66_qs) + ); + + // F[e_67]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[67].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_67_qs) + ); + + // F[e_68]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[68].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_68_qs) + ); + + // F[e_69]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[69].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_69_qs) + ); + + // F[e_70]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[70].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_70_qs) + ); + + // F[e_71]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[71].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_71_qs) + ); + + // F[e_72]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[72].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_72_qs) + ); + + // F[e_73]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_73_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[73].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_73_qs) + ); + + // F[e_74]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_74_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[74].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_74_qs) + ); + + // F[e_75]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_75_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[75].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_75_qs) + ); + + // F[e_76]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_76_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[76].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_76_qs) + ); + + // F[e_77]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_77_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[77].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_77_qs) + ); + + // F[e_78]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_78_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[78].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_78_qs) + ); + + // F[e_79]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_79_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[79].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_79_qs) + ); + + // F[e_80]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_80_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[80].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_80_qs) + ); + + // F[e_81]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_81_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[81].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_81_qs) + ); + + // F[e_82]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_82_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[82].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_82_qs) + ); + + // F[e_83]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_83_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[83].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_83_qs) + ); + + // F[e_84]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_84_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[84].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_84_qs) + ); + + // F[e_85]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_85_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[85].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_85_qs) + ); + + // F[e_86]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_86_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[86].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_86_qs) + ); + + // F[e_87]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_87_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[87].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_87_qs) + ); + + // F[e_88]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_88_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[88].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_88_qs) + ); + + // F[e_89]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_89_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[89].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_89_qs) + ); + + // F[e_90]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_90_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[90].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_90_qs) + ); + + // F[e_91]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_91_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[91].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_91_qs) + ); + + // F[e_92]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_92_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[92].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_92_qs) + ); + + // F[e_93]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_93_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[93].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_93_qs) + ); + + // F[e_94]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_94_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[94].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_94_qs) + ); + + // F[e_95]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_95_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[95].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_95_qs) + ); + + + // Subregister 3 of Multireg ie0 + // R[ie0_3]: V(False) + // F[e_96]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_96_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[96].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_96_qs) + ); + + // F[e_97]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_97_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[97].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_97_qs) + ); + + // F[e_98]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_98_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[98].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_98_qs) + ); + + // F[e_99]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_99 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_99_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[99].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_99_qs) + ); + + // F[e_100]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_100 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_100_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[100].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_100_qs) + ); + + // F[e_101]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_101 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_101_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[101].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_101_qs) + ); + + // F[e_102]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_102 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_102_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[102].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_102_qs) + ); + + // F[e_103]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_103 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_103_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[103].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_103_qs) + ); + + // F[e_104]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_104 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_104_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[104].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_104_qs) + ); + + // F[e_105]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_105 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_105_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[105].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_105_qs) + ); + + // F[e_106]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_106 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_106_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[106].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_106_qs) + ); + + // F[e_107]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_107 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_107_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[107].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_107_qs) + ); + + // F[e_108]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_108 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_108_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[108].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_108_qs) + ); + + // F[e_109]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_109 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_109_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[109].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_109_qs) + ); + + // F[e_110]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_110 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_110_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[110].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_110_qs) + ); + + // F[e_111]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_111 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_111_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[111].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_111_qs) + ); + + // F[e_112]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_112 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_112_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[112].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_112_qs) + ); + + // F[e_113]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_113 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_113_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[113].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_113_qs) + ); + + // F[e_114]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_114 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_114_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[114].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_114_qs) + ); + + // F[e_115]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_115 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_115_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[115].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_115_qs) + ); + + // F[e_116]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_116 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_116_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[116].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_116_qs) + ); + + // F[e_117]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_117 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_117_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[117].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_117_qs) + ); + + // F[e_118]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_118 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_118_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[118].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_118_qs) + ); + + // F[e_119]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_119 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_119_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[119].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_119_qs) + ); + + // F[e_120]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_120 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_120_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[120].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_120_qs) + ); + + // F[e_121]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_121 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_121_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[121].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_121_qs) + ); + + // F[e_122]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_122 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_122_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[122].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_122_qs) + ); + + // F[e_123]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_123 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_123_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[123].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_123_qs) + ); + + // F[e_124]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_124 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_124_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[124].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_124_qs) + ); + + // F[e_125]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_125 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_125_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[125].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_125_qs) + ); + + // F[e_126]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_126 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_126_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[126].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_126_qs) + ); + + // F[e_127]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_127 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_127_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[127].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_127_qs) + ); + + + // Subregister 4 of Multireg ie0 + // R[ie0_4]: V(False) + // F[e_128]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_128 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_128_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[128].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_128_qs) + ); + + // F[e_129]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_129 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_129_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[129].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_129_qs) + ); + + // F[e_130]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_130 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_130_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[130].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_130_qs) + ); + + // F[e_131]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_131 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_131_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[131].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_131_qs) + ); + + // F[e_132]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_132 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_132_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[132].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_132_qs) + ); + + // F[e_133]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_133 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_133_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[133].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_133_qs) + ); + + // F[e_134]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_134 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_134_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[134].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_134_qs) + ); + + // F[e_135]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_135 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_135_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[135].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_135_qs) + ); + + // F[e_136]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_136 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_136_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[136].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_136_qs) + ); + + // F[e_137]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_137 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_137_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[137].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_137_qs) + ); + + // F[e_138]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_138 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_138_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[138].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_138_qs) + ); + + // F[e_139]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_139 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_139_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[139].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_139_qs) + ); + + // F[e_140]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_140 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_140_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[140].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_140_qs) + ); + + // F[e_141]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_141 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_141_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[141].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_141_qs) + ); + + // F[e_142]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_142 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_142_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[142].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_142_qs) + ); + + // F[e_143]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_143 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_143_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[143].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_143_qs) + ); + + // F[e_144]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_144 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_144_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[144].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_144_qs) + ); + + // F[e_145]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_145 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_145_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[145].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_145_qs) + ); + + // F[e_146]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_146 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_146_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[146].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_146_qs) + ); + + // F[e_147]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_147 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_147_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[147].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_147_qs) + ); + + // F[e_148]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_148 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_148_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[148].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_148_qs) + ); + + // F[e_149]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_149 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_149_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[149].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_149_qs) + ); + + // F[e_150]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_150 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_150_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[150].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_150_qs) + ); + + // F[e_151]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_151 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_151_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[151].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_151_qs) + ); + + // F[e_152]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_152 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_152_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[152].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_152_qs) + ); + + // F[e_153]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_153 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_153_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[153].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_153_qs) + ); + + // F[e_154]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_154 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_154_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[154].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_154_qs) + ); + + // F[e_155]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_155 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_155_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[155].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_155_qs) + ); + + // F[e_156]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_156 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_156_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[156].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_156_qs) + ); + + // F[e_157]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_157 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_157_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[157].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_157_qs) + ); + + // F[e_158]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_158 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_158_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[158].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_158_qs) + ); + + // F[e_159]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_159 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_159_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[159].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_159_qs) + ); + + + // R[threshold0]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_threshold0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (threshold0_we), + .wd (threshold0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.threshold0.q), + .ds (), + + // to register interface (read) + .qs (threshold0_qs) + ); + + + // R[cc0]: V(True) + logic cc0_qe; + logic [0:0] cc0_flds_we; + assign cc0_qe = &cc0_flds_we; + prim_subreg_ext #( + .DW (8) + ) u_cc0 ( + .re (cc0_re), + .we (cc0_we), + .wd (cc0_wd), + .d (hw2reg.cc0.d), + .qre (reg2hw.cc0.re), + .qe (cc0_flds_we[0]), + .q (reg2hw.cc0.q), + .ds (), + .qs (cc0_qs) + ); + assign reg2hw.cc0.qe = cc0_qe; + + + // R[msip0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_msip0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (msip0_we), + .wd (msip0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.msip0.q), + .ds (), + + // to register interface (read) + .qs (msip0_qs) + ); + + + // R[alert_test]: V(True) + logic alert_test_qe; + logic [0:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_alert_test ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.qe = alert_test_qe; + + + + logic [173:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == RV_PLIC_PRIO0_OFFSET); + addr_hit[ 1] = (reg_addr == RV_PLIC_PRIO1_OFFSET); + addr_hit[ 2] = (reg_addr == RV_PLIC_PRIO2_OFFSET); + addr_hit[ 3] = (reg_addr == RV_PLIC_PRIO3_OFFSET); + addr_hit[ 4] = (reg_addr == RV_PLIC_PRIO4_OFFSET); + addr_hit[ 5] = (reg_addr == RV_PLIC_PRIO5_OFFSET); + addr_hit[ 6] = (reg_addr == RV_PLIC_PRIO6_OFFSET); + addr_hit[ 7] = (reg_addr == RV_PLIC_PRIO7_OFFSET); + addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO8_OFFSET); + addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO9_OFFSET); + addr_hit[ 10] = (reg_addr == RV_PLIC_PRIO10_OFFSET); + addr_hit[ 11] = (reg_addr == RV_PLIC_PRIO11_OFFSET); + addr_hit[ 12] = (reg_addr == RV_PLIC_PRIO12_OFFSET); + addr_hit[ 13] = (reg_addr == RV_PLIC_PRIO13_OFFSET); + addr_hit[ 14] = (reg_addr == RV_PLIC_PRIO14_OFFSET); + addr_hit[ 15] = (reg_addr == RV_PLIC_PRIO15_OFFSET); + addr_hit[ 16] = (reg_addr == RV_PLIC_PRIO16_OFFSET); + addr_hit[ 17] = (reg_addr == RV_PLIC_PRIO17_OFFSET); + addr_hit[ 18] = (reg_addr == RV_PLIC_PRIO18_OFFSET); + addr_hit[ 19] = (reg_addr == RV_PLIC_PRIO19_OFFSET); + addr_hit[ 20] = (reg_addr == RV_PLIC_PRIO20_OFFSET); + addr_hit[ 21] = (reg_addr == RV_PLIC_PRIO21_OFFSET); + addr_hit[ 22] = (reg_addr == RV_PLIC_PRIO22_OFFSET); + addr_hit[ 23] = (reg_addr == RV_PLIC_PRIO23_OFFSET); + addr_hit[ 24] = (reg_addr == RV_PLIC_PRIO24_OFFSET); + addr_hit[ 25] = (reg_addr == RV_PLIC_PRIO25_OFFSET); + addr_hit[ 26] = (reg_addr == RV_PLIC_PRIO26_OFFSET); + addr_hit[ 27] = (reg_addr == RV_PLIC_PRIO27_OFFSET); + addr_hit[ 28] = (reg_addr == RV_PLIC_PRIO28_OFFSET); + addr_hit[ 29] = (reg_addr == RV_PLIC_PRIO29_OFFSET); + addr_hit[ 30] = (reg_addr == RV_PLIC_PRIO30_OFFSET); + addr_hit[ 31] = (reg_addr == RV_PLIC_PRIO31_OFFSET); + addr_hit[ 32] = (reg_addr == RV_PLIC_PRIO32_OFFSET); + addr_hit[ 33] = (reg_addr == RV_PLIC_PRIO33_OFFSET); + addr_hit[ 34] = (reg_addr == RV_PLIC_PRIO34_OFFSET); + addr_hit[ 35] = (reg_addr == RV_PLIC_PRIO35_OFFSET); + addr_hit[ 36] = (reg_addr == RV_PLIC_PRIO36_OFFSET); + addr_hit[ 37] = (reg_addr == RV_PLIC_PRIO37_OFFSET); + addr_hit[ 38] = (reg_addr == RV_PLIC_PRIO38_OFFSET); + addr_hit[ 39] = (reg_addr == RV_PLIC_PRIO39_OFFSET); + addr_hit[ 40] = (reg_addr == RV_PLIC_PRIO40_OFFSET); + addr_hit[ 41] = (reg_addr == RV_PLIC_PRIO41_OFFSET); + addr_hit[ 42] = (reg_addr == RV_PLIC_PRIO42_OFFSET); + addr_hit[ 43] = (reg_addr == RV_PLIC_PRIO43_OFFSET); + addr_hit[ 44] = (reg_addr == RV_PLIC_PRIO44_OFFSET); + addr_hit[ 45] = (reg_addr == RV_PLIC_PRIO45_OFFSET); + addr_hit[ 46] = (reg_addr == RV_PLIC_PRIO46_OFFSET); + addr_hit[ 47] = (reg_addr == RV_PLIC_PRIO47_OFFSET); + addr_hit[ 48] = (reg_addr == RV_PLIC_PRIO48_OFFSET); + addr_hit[ 49] = (reg_addr == RV_PLIC_PRIO49_OFFSET); + addr_hit[ 50] = (reg_addr == RV_PLIC_PRIO50_OFFSET); + addr_hit[ 51] = (reg_addr == RV_PLIC_PRIO51_OFFSET); + addr_hit[ 52] = (reg_addr == RV_PLIC_PRIO52_OFFSET); + addr_hit[ 53] = (reg_addr == RV_PLIC_PRIO53_OFFSET); + addr_hit[ 54] = (reg_addr == RV_PLIC_PRIO54_OFFSET); + addr_hit[ 55] = (reg_addr == RV_PLIC_PRIO55_OFFSET); + addr_hit[ 56] = (reg_addr == RV_PLIC_PRIO56_OFFSET); + addr_hit[ 57] = (reg_addr == RV_PLIC_PRIO57_OFFSET); + addr_hit[ 58] = (reg_addr == RV_PLIC_PRIO58_OFFSET); + addr_hit[ 59] = (reg_addr == RV_PLIC_PRIO59_OFFSET); + addr_hit[ 60] = (reg_addr == RV_PLIC_PRIO60_OFFSET); + addr_hit[ 61] = (reg_addr == RV_PLIC_PRIO61_OFFSET); + addr_hit[ 62] = (reg_addr == RV_PLIC_PRIO62_OFFSET); + addr_hit[ 63] = (reg_addr == RV_PLIC_PRIO63_OFFSET); + addr_hit[ 64] = (reg_addr == RV_PLIC_PRIO64_OFFSET); + addr_hit[ 65] = (reg_addr == RV_PLIC_PRIO65_OFFSET); + addr_hit[ 66] = (reg_addr == RV_PLIC_PRIO66_OFFSET); + addr_hit[ 67] = (reg_addr == RV_PLIC_PRIO67_OFFSET); + addr_hit[ 68] = (reg_addr == RV_PLIC_PRIO68_OFFSET); + addr_hit[ 69] = (reg_addr == RV_PLIC_PRIO69_OFFSET); + addr_hit[ 70] = (reg_addr == RV_PLIC_PRIO70_OFFSET); + addr_hit[ 71] = (reg_addr == RV_PLIC_PRIO71_OFFSET); + addr_hit[ 72] = (reg_addr == RV_PLIC_PRIO72_OFFSET); + addr_hit[ 73] = (reg_addr == RV_PLIC_PRIO73_OFFSET); + addr_hit[ 74] = (reg_addr == RV_PLIC_PRIO74_OFFSET); + addr_hit[ 75] = (reg_addr == RV_PLIC_PRIO75_OFFSET); + addr_hit[ 76] = (reg_addr == RV_PLIC_PRIO76_OFFSET); + addr_hit[ 77] = (reg_addr == RV_PLIC_PRIO77_OFFSET); + addr_hit[ 78] = (reg_addr == RV_PLIC_PRIO78_OFFSET); + addr_hit[ 79] = (reg_addr == RV_PLIC_PRIO79_OFFSET); + addr_hit[ 80] = (reg_addr == RV_PLIC_PRIO80_OFFSET); + addr_hit[ 81] = (reg_addr == RV_PLIC_PRIO81_OFFSET); + addr_hit[ 82] = (reg_addr == RV_PLIC_PRIO82_OFFSET); + addr_hit[ 83] = (reg_addr == RV_PLIC_PRIO83_OFFSET); + addr_hit[ 84] = (reg_addr == RV_PLIC_PRIO84_OFFSET); + addr_hit[ 85] = (reg_addr == RV_PLIC_PRIO85_OFFSET); + addr_hit[ 86] = (reg_addr == RV_PLIC_PRIO86_OFFSET); + addr_hit[ 87] = (reg_addr == RV_PLIC_PRIO87_OFFSET); + addr_hit[ 88] = (reg_addr == RV_PLIC_PRIO88_OFFSET); + addr_hit[ 89] = (reg_addr == RV_PLIC_PRIO89_OFFSET); + addr_hit[ 90] = (reg_addr == RV_PLIC_PRIO90_OFFSET); + addr_hit[ 91] = (reg_addr == RV_PLIC_PRIO91_OFFSET); + addr_hit[ 92] = (reg_addr == RV_PLIC_PRIO92_OFFSET); + addr_hit[ 93] = (reg_addr == RV_PLIC_PRIO93_OFFSET); + addr_hit[ 94] = (reg_addr == RV_PLIC_PRIO94_OFFSET); + addr_hit[ 95] = (reg_addr == RV_PLIC_PRIO95_OFFSET); + addr_hit[ 96] = (reg_addr == RV_PLIC_PRIO96_OFFSET); + addr_hit[ 97] = (reg_addr == RV_PLIC_PRIO97_OFFSET); + addr_hit[ 98] = (reg_addr == RV_PLIC_PRIO98_OFFSET); + addr_hit[ 99] = (reg_addr == RV_PLIC_PRIO99_OFFSET); + addr_hit[100] = (reg_addr == RV_PLIC_PRIO100_OFFSET); + addr_hit[101] = (reg_addr == RV_PLIC_PRIO101_OFFSET); + addr_hit[102] = (reg_addr == RV_PLIC_PRIO102_OFFSET); + addr_hit[103] = (reg_addr == RV_PLIC_PRIO103_OFFSET); + addr_hit[104] = (reg_addr == RV_PLIC_PRIO104_OFFSET); + addr_hit[105] = (reg_addr == RV_PLIC_PRIO105_OFFSET); + addr_hit[106] = (reg_addr == RV_PLIC_PRIO106_OFFSET); + addr_hit[107] = (reg_addr == RV_PLIC_PRIO107_OFFSET); + addr_hit[108] = (reg_addr == RV_PLIC_PRIO108_OFFSET); + addr_hit[109] = (reg_addr == RV_PLIC_PRIO109_OFFSET); + addr_hit[110] = (reg_addr == RV_PLIC_PRIO110_OFFSET); + addr_hit[111] = (reg_addr == RV_PLIC_PRIO111_OFFSET); + addr_hit[112] = (reg_addr == RV_PLIC_PRIO112_OFFSET); + addr_hit[113] = (reg_addr == RV_PLIC_PRIO113_OFFSET); + addr_hit[114] = (reg_addr == RV_PLIC_PRIO114_OFFSET); + addr_hit[115] = (reg_addr == RV_PLIC_PRIO115_OFFSET); + addr_hit[116] = (reg_addr == RV_PLIC_PRIO116_OFFSET); + addr_hit[117] = (reg_addr == RV_PLIC_PRIO117_OFFSET); + addr_hit[118] = (reg_addr == RV_PLIC_PRIO118_OFFSET); + addr_hit[119] = (reg_addr == RV_PLIC_PRIO119_OFFSET); + addr_hit[120] = (reg_addr == RV_PLIC_PRIO120_OFFSET); + addr_hit[121] = (reg_addr == RV_PLIC_PRIO121_OFFSET); + addr_hit[122] = (reg_addr == RV_PLIC_PRIO122_OFFSET); + addr_hit[123] = (reg_addr == RV_PLIC_PRIO123_OFFSET); + addr_hit[124] = (reg_addr == RV_PLIC_PRIO124_OFFSET); + addr_hit[125] = (reg_addr == RV_PLIC_PRIO125_OFFSET); + addr_hit[126] = (reg_addr == RV_PLIC_PRIO126_OFFSET); + addr_hit[127] = (reg_addr == RV_PLIC_PRIO127_OFFSET); + addr_hit[128] = (reg_addr == RV_PLIC_PRIO128_OFFSET); + addr_hit[129] = (reg_addr == RV_PLIC_PRIO129_OFFSET); + addr_hit[130] = (reg_addr == RV_PLIC_PRIO130_OFFSET); + addr_hit[131] = (reg_addr == RV_PLIC_PRIO131_OFFSET); + addr_hit[132] = (reg_addr == RV_PLIC_PRIO132_OFFSET); + addr_hit[133] = (reg_addr == RV_PLIC_PRIO133_OFFSET); + addr_hit[134] = (reg_addr == RV_PLIC_PRIO134_OFFSET); + addr_hit[135] = (reg_addr == RV_PLIC_PRIO135_OFFSET); + addr_hit[136] = (reg_addr == RV_PLIC_PRIO136_OFFSET); + addr_hit[137] = (reg_addr == RV_PLIC_PRIO137_OFFSET); + addr_hit[138] = (reg_addr == RV_PLIC_PRIO138_OFFSET); + addr_hit[139] = (reg_addr == RV_PLIC_PRIO139_OFFSET); + addr_hit[140] = (reg_addr == RV_PLIC_PRIO140_OFFSET); + addr_hit[141] = (reg_addr == RV_PLIC_PRIO141_OFFSET); + addr_hit[142] = (reg_addr == RV_PLIC_PRIO142_OFFSET); + addr_hit[143] = (reg_addr == RV_PLIC_PRIO143_OFFSET); + addr_hit[144] = (reg_addr == RV_PLIC_PRIO144_OFFSET); + addr_hit[145] = (reg_addr == RV_PLIC_PRIO145_OFFSET); + addr_hit[146] = (reg_addr == RV_PLIC_PRIO146_OFFSET); + addr_hit[147] = (reg_addr == RV_PLIC_PRIO147_OFFSET); + addr_hit[148] = (reg_addr == RV_PLIC_PRIO148_OFFSET); + addr_hit[149] = (reg_addr == RV_PLIC_PRIO149_OFFSET); + addr_hit[150] = (reg_addr == RV_PLIC_PRIO150_OFFSET); + addr_hit[151] = (reg_addr == RV_PLIC_PRIO151_OFFSET); + addr_hit[152] = (reg_addr == RV_PLIC_PRIO152_OFFSET); + addr_hit[153] = (reg_addr == RV_PLIC_PRIO153_OFFSET); + addr_hit[154] = (reg_addr == RV_PLIC_PRIO154_OFFSET); + addr_hit[155] = (reg_addr == RV_PLIC_PRIO155_OFFSET); + addr_hit[156] = (reg_addr == RV_PLIC_PRIO156_OFFSET); + addr_hit[157] = (reg_addr == RV_PLIC_PRIO157_OFFSET); + addr_hit[158] = (reg_addr == RV_PLIC_PRIO158_OFFSET); + addr_hit[159] = (reg_addr == RV_PLIC_PRIO159_OFFSET); + addr_hit[160] = (reg_addr == RV_PLIC_IP_0_OFFSET); + addr_hit[161] = (reg_addr == RV_PLIC_IP_1_OFFSET); + addr_hit[162] = (reg_addr == RV_PLIC_IP_2_OFFSET); + addr_hit[163] = (reg_addr == RV_PLIC_IP_3_OFFSET); + addr_hit[164] = (reg_addr == RV_PLIC_IP_4_OFFSET); + addr_hit[165] = (reg_addr == RV_PLIC_IE0_0_OFFSET); + addr_hit[166] = (reg_addr == RV_PLIC_IE0_1_OFFSET); + addr_hit[167] = (reg_addr == RV_PLIC_IE0_2_OFFSET); + addr_hit[168] = (reg_addr == RV_PLIC_IE0_3_OFFSET); + addr_hit[169] = (reg_addr == RV_PLIC_IE0_4_OFFSET); + addr_hit[170] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET); + addr_hit[171] = (reg_addr == RV_PLIC_CC0_OFFSET); + addr_hit[172] = (reg_addr == RV_PLIC_MSIP0_OFFSET); + addr_hit[173] = (reg_addr == RV_PLIC_ALERT_TEST_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(RV_PLIC_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(RV_PLIC_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(RV_PLIC_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(RV_PLIC_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(RV_PLIC_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(RV_PLIC_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(RV_PLIC_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(RV_PLIC_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(RV_PLIC_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(RV_PLIC_PERMIT[ 9] & ~reg_be))) | + (addr_hit[ 10] & (|(RV_PLIC_PERMIT[ 10] & ~reg_be))) | + (addr_hit[ 11] & (|(RV_PLIC_PERMIT[ 11] & ~reg_be))) | + (addr_hit[ 12] & (|(RV_PLIC_PERMIT[ 12] & ~reg_be))) | + (addr_hit[ 13] & (|(RV_PLIC_PERMIT[ 13] & ~reg_be))) | + (addr_hit[ 14] & (|(RV_PLIC_PERMIT[ 14] & ~reg_be))) | + (addr_hit[ 15] & (|(RV_PLIC_PERMIT[ 15] & ~reg_be))) | + (addr_hit[ 16] & (|(RV_PLIC_PERMIT[ 16] & ~reg_be))) | + (addr_hit[ 17] & (|(RV_PLIC_PERMIT[ 17] & ~reg_be))) | + (addr_hit[ 18] & (|(RV_PLIC_PERMIT[ 18] & ~reg_be))) | + (addr_hit[ 19] & (|(RV_PLIC_PERMIT[ 19] & ~reg_be))) | + (addr_hit[ 20] & (|(RV_PLIC_PERMIT[ 20] & ~reg_be))) | + (addr_hit[ 21] & (|(RV_PLIC_PERMIT[ 21] & ~reg_be))) | + (addr_hit[ 22] & (|(RV_PLIC_PERMIT[ 22] & ~reg_be))) | + (addr_hit[ 23] & (|(RV_PLIC_PERMIT[ 23] & ~reg_be))) | + (addr_hit[ 24] & (|(RV_PLIC_PERMIT[ 24] & ~reg_be))) | + (addr_hit[ 25] & (|(RV_PLIC_PERMIT[ 25] & ~reg_be))) | + (addr_hit[ 26] & (|(RV_PLIC_PERMIT[ 26] & ~reg_be))) | + (addr_hit[ 27] & (|(RV_PLIC_PERMIT[ 27] & ~reg_be))) | + (addr_hit[ 28] & (|(RV_PLIC_PERMIT[ 28] & ~reg_be))) | + (addr_hit[ 29] & (|(RV_PLIC_PERMIT[ 29] & ~reg_be))) | + (addr_hit[ 30] & (|(RV_PLIC_PERMIT[ 30] & ~reg_be))) | + (addr_hit[ 31] & (|(RV_PLIC_PERMIT[ 31] & ~reg_be))) | + (addr_hit[ 32] & (|(RV_PLIC_PERMIT[ 32] & ~reg_be))) | + (addr_hit[ 33] & (|(RV_PLIC_PERMIT[ 33] & ~reg_be))) | + (addr_hit[ 34] & (|(RV_PLIC_PERMIT[ 34] & ~reg_be))) | + (addr_hit[ 35] & (|(RV_PLIC_PERMIT[ 35] & ~reg_be))) | + (addr_hit[ 36] & (|(RV_PLIC_PERMIT[ 36] & ~reg_be))) | + (addr_hit[ 37] & (|(RV_PLIC_PERMIT[ 37] & ~reg_be))) | + (addr_hit[ 38] & (|(RV_PLIC_PERMIT[ 38] & ~reg_be))) | + (addr_hit[ 39] & (|(RV_PLIC_PERMIT[ 39] & ~reg_be))) | + (addr_hit[ 40] & (|(RV_PLIC_PERMIT[ 40] & ~reg_be))) | + (addr_hit[ 41] & (|(RV_PLIC_PERMIT[ 41] & ~reg_be))) | + (addr_hit[ 42] & (|(RV_PLIC_PERMIT[ 42] & ~reg_be))) | + (addr_hit[ 43] & (|(RV_PLIC_PERMIT[ 43] & ~reg_be))) | + (addr_hit[ 44] & (|(RV_PLIC_PERMIT[ 44] & ~reg_be))) | + (addr_hit[ 45] & (|(RV_PLIC_PERMIT[ 45] & ~reg_be))) | + (addr_hit[ 46] & (|(RV_PLIC_PERMIT[ 46] & ~reg_be))) | + (addr_hit[ 47] & (|(RV_PLIC_PERMIT[ 47] & ~reg_be))) | + (addr_hit[ 48] & (|(RV_PLIC_PERMIT[ 48] & ~reg_be))) | + (addr_hit[ 49] & (|(RV_PLIC_PERMIT[ 49] & ~reg_be))) | + (addr_hit[ 50] & (|(RV_PLIC_PERMIT[ 50] & ~reg_be))) | + (addr_hit[ 51] & (|(RV_PLIC_PERMIT[ 51] & ~reg_be))) | + (addr_hit[ 52] & (|(RV_PLIC_PERMIT[ 52] & ~reg_be))) | + (addr_hit[ 53] & (|(RV_PLIC_PERMIT[ 53] & ~reg_be))) | + (addr_hit[ 54] & (|(RV_PLIC_PERMIT[ 54] & ~reg_be))) | + (addr_hit[ 55] & (|(RV_PLIC_PERMIT[ 55] & ~reg_be))) | + (addr_hit[ 56] & (|(RV_PLIC_PERMIT[ 56] & ~reg_be))) | + (addr_hit[ 57] & (|(RV_PLIC_PERMIT[ 57] & ~reg_be))) | + (addr_hit[ 58] & (|(RV_PLIC_PERMIT[ 58] & ~reg_be))) | + (addr_hit[ 59] & (|(RV_PLIC_PERMIT[ 59] & ~reg_be))) | + (addr_hit[ 60] & (|(RV_PLIC_PERMIT[ 60] & ~reg_be))) | + (addr_hit[ 61] & (|(RV_PLIC_PERMIT[ 61] & ~reg_be))) | + (addr_hit[ 62] & (|(RV_PLIC_PERMIT[ 62] & ~reg_be))) | + (addr_hit[ 63] & (|(RV_PLIC_PERMIT[ 63] & ~reg_be))) | + (addr_hit[ 64] & (|(RV_PLIC_PERMIT[ 64] & ~reg_be))) | + (addr_hit[ 65] & (|(RV_PLIC_PERMIT[ 65] & ~reg_be))) | + (addr_hit[ 66] & (|(RV_PLIC_PERMIT[ 66] & ~reg_be))) | + (addr_hit[ 67] & (|(RV_PLIC_PERMIT[ 67] & ~reg_be))) | + (addr_hit[ 68] & (|(RV_PLIC_PERMIT[ 68] & ~reg_be))) | + (addr_hit[ 69] & (|(RV_PLIC_PERMIT[ 69] & ~reg_be))) | + (addr_hit[ 70] & (|(RV_PLIC_PERMIT[ 70] & ~reg_be))) | + (addr_hit[ 71] & (|(RV_PLIC_PERMIT[ 71] & ~reg_be))) | + (addr_hit[ 72] & (|(RV_PLIC_PERMIT[ 72] & ~reg_be))) | + (addr_hit[ 73] & (|(RV_PLIC_PERMIT[ 73] & ~reg_be))) | + (addr_hit[ 74] & (|(RV_PLIC_PERMIT[ 74] & ~reg_be))) | + (addr_hit[ 75] & (|(RV_PLIC_PERMIT[ 75] & ~reg_be))) | + (addr_hit[ 76] & (|(RV_PLIC_PERMIT[ 76] & ~reg_be))) | + (addr_hit[ 77] & (|(RV_PLIC_PERMIT[ 77] & ~reg_be))) | + (addr_hit[ 78] & (|(RV_PLIC_PERMIT[ 78] & ~reg_be))) | + (addr_hit[ 79] & (|(RV_PLIC_PERMIT[ 79] & ~reg_be))) | + (addr_hit[ 80] & (|(RV_PLIC_PERMIT[ 80] & ~reg_be))) | + (addr_hit[ 81] & (|(RV_PLIC_PERMIT[ 81] & ~reg_be))) | + (addr_hit[ 82] & (|(RV_PLIC_PERMIT[ 82] & ~reg_be))) | + (addr_hit[ 83] & (|(RV_PLIC_PERMIT[ 83] & ~reg_be))) | + (addr_hit[ 84] & (|(RV_PLIC_PERMIT[ 84] & ~reg_be))) | + (addr_hit[ 85] & (|(RV_PLIC_PERMIT[ 85] & ~reg_be))) | + (addr_hit[ 86] & (|(RV_PLIC_PERMIT[ 86] & ~reg_be))) | + (addr_hit[ 87] & (|(RV_PLIC_PERMIT[ 87] & ~reg_be))) | + (addr_hit[ 88] & (|(RV_PLIC_PERMIT[ 88] & ~reg_be))) | + (addr_hit[ 89] & (|(RV_PLIC_PERMIT[ 89] & ~reg_be))) | + (addr_hit[ 90] & (|(RV_PLIC_PERMIT[ 90] & ~reg_be))) | + (addr_hit[ 91] & (|(RV_PLIC_PERMIT[ 91] & ~reg_be))) | + (addr_hit[ 92] & (|(RV_PLIC_PERMIT[ 92] & ~reg_be))) | + (addr_hit[ 93] & (|(RV_PLIC_PERMIT[ 93] & ~reg_be))) | + (addr_hit[ 94] & (|(RV_PLIC_PERMIT[ 94] & ~reg_be))) | + (addr_hit[ 95] & (|(RV_PLIC_PERMIT[ 95] & ~reg_be))) | + (addr_hit[ 96] & (|(RV_PLIC_PERMIT[ 96] & ~reg_be))) | + (addr_hit[ 97] & (|(RV_PLIC_PERMIT[ 97] & ~reg_be))) | + (addr_hit[ 98] & (|(RV_PLIC_PERMIT[ 98] & ~reg_be))) | + (addr_hit[ 99] & (|(RV_PLIC_PERMIT[ 99] & ~reg_be))) | + (addr_hit[100] & (|(RV_PLIC_PERMIT[100] & ~reg_be))) | + (addr_hit[101] & (|(RV_PLIC_PERMIT[101] & ~reg_be))) | + (addr_hit[102] & (|(RV_PLIC_PERMIT[102] & ~reg_be))) | + (addr_hit[103] & (|(RV_PLIC_PERMIT[103] & ~reg_be))) | + (addr_hit[104] & (|(RV_PLIC_PERMIT[104] & ~reg_be))) | + (addr_hit[105] & (|(RV_PLIC_PERMIT[105] & ~reg_be))) | + (addr_hit[106] & (|(RV_PLIC_PERMIT[106] & ~reg_be))) | + (addr_hit[107] & (|(RV_PLIC_PERMIT[107] & ~reg_be))) | + (addr_hit[108] & (|(RV_PLIC_PERMIT[108] & ~reg_be))) | + (addr_hit[109] & (|(RV_PLIC_PERMIT[109] & ~reg_be))) | + (addr_hit[110] & (|(RV_PLIC_PERMIT[110] & ~reg_be))) | + (addr_hit[111] & (|(RV_PLIC_PERMIT[111] & ~reg_be))) | + (addr_hit[112] & (|(RV_PLIC_PERMIT[112] & ~reg_be))) | + (addr_hit[113] & (|(RV_PLIC_PERMIT[113] & ~reg_be))) | + (addr_hit[114] & (|(RV_PLIC_PERMIT[114] & ~reg_be))) | + (addr_hit[115] & (|(RV_PLIC_PERMIT[115] & ~reg_be))) | + (addr_hit[116] & (|(RV_PLIC_PERMIT[116] & ~reg_be))) | + (addr_hit[117] & (|(RV_PLIC_PERMIT[117] & ~reg_be))) | + (addr_hit[118] & (|(RV_PLIC_PERMIT[118] & ~reg_be))) | + (addr_hit[119] & (|(RV_PLIC_PERMIT[119] & ~reg_be))) | + (addr_hit[120] & (|(RV_PLIC_PERMIT[120] & ~reg_be))) | + (addr_hit[121] & (|(RV_PLIC_PERMIT[121] & ~reg_be))) | + (addr_hit[122] & (|(RV_PLIC_PERMIT[122] & ~reg_be))) | + (addr_hit[123] & (|(RV_PLIC_PERMIT[123] & ~reg_be))) | + (addr_hit[124] & (|(RV_PLIC_PERMIT[124] & ~reg_be))) | + (addr_hit[125] & (|(RV_PLIC_PERMIT[125] & ~reg_be))) | + (addr_hit[126] & (|(RV_PLIC_PERMIT[126] & ~reg_be))) | + (addr_hit[127] & (|(RV_PLIC_PERMIT[127] & ~reg_be))) | + (addr_hit[128] & (|(RV_PLIC_PERMIT[128] & ~reg_be))) | + (addr_hit[129] & (|(RV_PLIC_PERMIT[129] & ~reg_be))) | + (addr_hit[130] & (|(RV_PLIC_PERMIT[130] & ~reg_be))) | + (addr_hit[131] & (|(RV_PLIC_PERMIT[131] & ~reg_be))) | + (addr_hit[132] & (|(RV_PLIC_PERMIT[132] & ~reg_be))) | + (addr_hit[133] & (|(RV_PLIC_PERMIT[133] & ~reg_be))) | + (addr_hit[134] & (|(RV_PLIC_PERMIT[134] & ~reg_be))) | + (addr_hit[135] & (|(RV_PLIC_PERMIT[135] & ~reg_be))) | + (addr_hit[136] & (|(RV_PLIC_PERMIT[136] & ~reg_be))) | + (addr_hit[137] & (|(RV_PLIC_PERMIT[137] & ~reg_be))) | + (addr_hit[138] & (|(RV_PLIC_PERMIT[138] & ~reg_be))) | + (addr_hit[139] & (|(RV_PLIC_PERMIT[139] & ~reg_be))) | + (addr_hit[140] & (|(RV_PLIC_PERMIT[140] & ~reg_be))) | + (addr_hit[141] & (|(RV_PLIC_PERMIT[141] & ~reg_be))) | + (addr_hit[142] & (|(RV_PLIC_PERMIT[142] & ~reg_be))) | + (addr_hit[143] & (|(RV_PLIC_PERMIT[143] & ~reg_be))) | + (addr_hit[144] & (|(RV_PLIC_PERMIT[144] & ~reg_be))) | + (addr_hit[145] & (|(RV_PLIC_PERMIT[145] & ~reg_be))) | + (addr_hit[146] & (|(RV_PLIC_PERMIT[146] & ~reg_be))) | + (addr_hit[147] & (|(RV_PLIC_PERMIT[147] & ~reg_be))) | + (addr_hit[148] & (|(RV_PLIC_PERMIT[148] & ~reg_be))) | + (addr_hit[149] & (|(RV_PLIC_PERMIT[149] & ~reg_be))) | + (addr_hit[150] & (|(RV_PLIC_PERMIT[150] & ~reg_be))) | + (addr_hit[151] & (|(RV_PLIC_PERMIT[151] & ~reg_be))) | + (addr_hit[152] & (|(RV_PLIC_PERMIT[152] & ~reg_be))) | + (addr_hit[153] & (|(RV_PLIC_PERMIT[153] & ~reg_be))) | + (addr_hit[154] & (|(RV_PLIC_PERMIT[154] & ~reg_be))) | + (addr_hit[155] & (|(RV_PLIC_PERMIT[155] & ~reg_be))) | + (addr_hit[156] & (|(RV_PLIC_PERMIT[156] & ~reg_be))) | + (addr_hit[157] & (|(RV_PLIC_PERMIT[157] & ~reg_be))) | + (addr_hit[158] & (|(RV_PLIC_PERMIT[158] & ~reg_be))) | + (addr_hit[159] & (|(RV_PLIC_PERMIT[159] & ~reg_be))) | + (addr_hit[160] & (|(RV_PLIC_PERMIT[160] & ~reg_be))) | + (addr_hit[161] & (|(RV_PLIC_PERMIT[161] & ~reg_be))) | + (addr_hit[162] & (|(RV_PLIC_PERMIT[162] & ~reg_be))) | + (addr_hit[163] & (|(RV_PLIC_PERMIT[163] & ~reg_be))) | + (addr_hit[164] & (|(RV_PLIC_PERMIT[164] & ~reg_be))) | + (addr_hit[165] & (|(RV_PLIC_PERMIT[165] & ~reg_be))) | + (addr_hit[166] & (|(RV_PLIC_PERMIT[166] & ~reg_be))) | + (addr_hit[167] & (|(RV_PLIC_PERMIT[167] & ~reg_be))) | + (addr_hit[168] & (|(RV_PLIC_PERMIT[168] & ~reg_be))) | + (addr_hit[169] & (|(RV_PLIC_PERMIT[169] & ~reg_be))) | + (addr_hit[170] & (|(RV_PLIC_PERMIT[170] & ~reg_be))) | + (addr_hit[171] & (|(RV_PLIC_PERMIT[171] & ~reg_be))) | + (addr_hit[172] & (|(RV_PLIC_PERMIT[172] & ~reg_be))) | + (addr_hit[173] & (|(RV_PLIC_PERMIT[173] & ~reg_be))))); + end + + // Generate write-enables + assign prio0_we = addr_hit[0] & reg_we & !reg_error; + + assign prio0_wd = reg_wdata[1:0]; + assign prio1_we = addr_hit[1] & reg_we & !reg_error; + + assign prio1_wd = reg_wdata[1:0]; + assign prio2_we = addr_hit[2] & reg_we & !reg_error; + + assign prio2_wd = reg_wdata[1:0]; + assign prio3_we = addr_hit[3] & reg_we & !reg_error; + + assign prio3_wd = reg_wdata[1:0]; + assign prio4_we = addr_hit[4] & reg_we & !reg_error; + + assign prio4_wd = reg_wdata[1:0]; + assign prio5_we = addr_hit[5] & reg_we & !reg_error; + + assign prio5_wd = reg_wdata[1:0]; + assign prio6_we = addr_hit[6] & reg_we & !reg_error; + + assign prio6_wd = reg_wdata[1:0]; + assign prio7_we = addr_hit[7] & reg_we & !reg_error; + + assign prio7_wd = reg_wdata[1:0]; + assign prio8_we = addr_hit[8] & reg_we & !reg_error; + + assign prio8_wd = reg_wdata[1:0]; + assign prio9_we = addr_hit[9] & reg_we & !reg_error; + + assign prio9_wd = reg_wdata[1:0]; + assign prio10_we = addr_hit[10] & reg_we & !reg_error; + + assign prio10_wd = reg_wdata[1:0]; + assign prio11_we = addr_hit[11] & reg_we & !reg_error; + + assign prio11_wd = reg_wdata[1:0]; + assign prio12_we = addr_hit[12] & reg_we & !reg_error; + + assign prio12_wd = reg_wdata[1:0]; + assign prio13_we = addr_hit[13] & reg_we & !reg_error; + + assign prio13_wd = reg_wdata[1:0]; + assign prio14_we = addr_hit[14] & reg_we & !reg_error; + + assign prio14_wd = reg_wdata[1:0]; + assign prio15_we = addr_hit[15] & reg_we & !reg_error; + + assign prio15_wd = reg_wdata[1:0]; + assign prio16_we = addr_hit[16] & reg_we & !reg_error; + + assign prio16_wd = reg_wdata[1:0]; + assign prio17_we = addr_hit[17] & reg_we & !reg_error; + + assign prio17_wd = reg_wdata[1:0]; + assign prio18_we = addr_hit[18] & reg_we & !reg_error; + + assign prio18_wd = reg_wdata[1:0]; + assign prio19_we = addr_hit[19] & reg_we & !reg_error; + + assign prio19_wd = reg_wdata[1:0]; + assign prio20_we = addr_hit[20] & reg_we & !reg_error; + + assign prio20_wd = reg_wdata[1:0]; + assign prio21_we = addr_hit[21] & reg_we & !reg_error; + + assign prio21_wd = reg_wdata[1:0]; + assign prio22_we = addr_hit[22] & reg_we & !reg_error; + + assign prio22_wd = reg_wdata[1:0]; + assign prio23_we = addr_hit[23] & reg_we & !reg_error; + + assign prio23_wd = reg_wdata[1:0]; + assign prio24_we = addr_hit[24] & reg_we & !reg_error; + + assign prio24_wd = reg_wdata[1:0]; + assign prio25_we = addr_hit[25] & reg_we & !reg_error; + + assign prio25_wd = reg_wdata[1:0]; + assign prio26_we = addr_hit[26] & reg_we & !reg_error; + + assign prio26_wd = reg_wdata[1:0]; + assign prio27_we = addr_hit[27] & reg_we & !reg_error; + + assign prio27_wd = reg_wdata[1:0]; + assign prio28_we = addr_hit[28] & reg_we & !reg_error; + + assign prio28_wd = reg_wdata[1:0]; + assign prio29_we = addr_hit[29] & reg_we & !reg_error; + + assign prio29_wd = reg_wdata[1:0]; + assign prio30_we = addr_hit[30] & reg_we & !reg_error; + + assign prio30_wd = reg_wdata[1:0]; + assign prio31_we = addr_hit[31] & reg_we & !reg_error; + + assign prio31_wd = reg_wdata[1:0]; + assign prio32_we = addr_hit[32] & reg_we & !reg_error; + + assign prio32_wd = reg_wdata[1:0]; + assign prio33_we = addr_hit[33] & reg_we & !reg_error; + + assign prio33_wd = reg_wdata[1:0]; + assign prio34_we = addr_hit[34] & reg_we & !reg_error; + + assign prio34_wd = reg_wdata[1:0]; + assign prio35_we = addr_hit[35] & reg_we & !reg_error; + + assign prio35_wd = reg_wdata[1:0]; + assign prio36_we = addr_hit[36] & reg_we & !reg_error; + + assign prio36_wd = reg_wdata[1:0]; + assign prio37_we = addr_hit[37] & reg_we & !reg_error; + + assign prio37_wd = reg_wdata[1:0]; + assign prio38_we = addr_hit[38] & reg_we & !reg_error; + + assign prio38_wd = reg_wdata[1:0]; + assign prio39_we = addr_hit[39] & reg_we & !reg_error; + + assign prio39_wd = reg_wdata[1:0]; + assign prio40_we = addr_hit[40] & reg_we & !reg_error; + + assign prio40_wd = reg_wdata[1:0]; + assign prio41_we = addr_hit[41] & reg_we & !reg_error; + + assign prio41_wd = reg_wdata[1:0]; + assign prio42_we = addr_hit[42] & reg_we & !reg_error; + + assign prio42_wd = reg_wdata[1:0]; + assign prio43_we = addr_hit[43] & reg_we & !reg_error; + + assign prio43_wd = reg_wdata[1:0]; + assign prio44_we = addr_hit[44] & reg_we & !reg_error; + + assign prio44_wd = reg_wdata[1:0]; + assign prio45_we = addr_hit[45] & reg_we & !reg_error; + + assign prio45_wd = reg_wdata[1:0]; + assign prio46_we = addr_hit[46] & reg_we & !reg_error; + + assign prio46_wd = reg_wdata[1:0]; + assign prio47_we = addr_hit[47] & reg_we & !reg_error; + + assign prio47_wd = reg_wdata[1:0]; + assign prio48_we = addr_hit[48] & reg_we & !reg_error; + + assign prio48_wd = reg_wdata[1:0]; + assign prio49_we = addr_hit[49] & reg_we & !reg_error; + + assign prio49_wd = reg_wdata[1:0]; + assign prio50_we = addr_hit[50] & reg_we & !reg_error; + + assign prio50_wd = reg_wdata[1:0]; + assign prio51_we = addr_hit[51] & reg_we & !reg_error; + + assign prio51_wd = reg_wdata[1:0]; + assign prio52_we = addr_hit[52] & reg_we & !reg_error; + + assign prio52_wd = reg_wdata[1:0]; + assign prio53_we = addr_hit[53] & reg_we & !reg_error; + + assign prio53_wd = reg_wdata[1:0]; + assign prio54_we = addr_hit[54] & reg_we & !reg_error; + + assign prio54_wd = reg_wdata[1:0]; + assign prio55_we = addr_hit[55] & reg_we & !reg_error; + + assign prio55_wd = reg_wdata[1:0]; + assign prio56_we = addr_hit[56] & reg_we & !reg_error; + + assign prio56_wd = reg_wdata[1:0]; + assign prio57_we = addr_hit[57] & reg_we & !reg_error; + + assign prio57_wd = reg_wdata[1:0]; + assign prio58_we = addr_hit[58] & reg_we & !reg_error; + + assign prio58_wd = reg_wdata[1:0]; + assign prio59_we = addr_hit[59] & reg_we & !reg_error; + + assign prio59_wd = reg_wdata[1:0]; + assign prio60_we = addr_hit[60] & reg_we & !reg_error; + + assign prio60_wd = reg_wdata[1:0]; + assign prio61_we = addr_hit[61] & reg_we & !reg_error; + + assign prio61_wd = reg_wdata[1:0]; + assign prio62_we = addr_hit[62] & reg_we & !reg_error; + + assign prio62_wd = reg_wdata[1:0]; + assign prio63_we = addr_hit[63] & reg_we & !reg_error; + + assign prio63_wd = reg_wdata[1:0]; + assign prio64_we = addr_hit[64] & reg_we & !reg_error; + + assign prio64_wd = reg_wdata[1:0]; + assign prio65_we = addr_hit[65] & reg_we & !reg_error; + + assign prio65_wd = reg_wdata[1:0]; + assign prio66_we = addr_hit[66] & reg_we & !reg_error; + + assign prio66_wd = reg_wdata[1:0]; + assign prio67_we = addr_hit[67] & reg_we & !reg_error; + + assign prio67_wd = reg_wdata[1:0]; + assign prio68_we = addr_hit[68] & reg_we & !reg_error; + + assign prio68_wd = reg_wdata[1:0]; + assign prio69_we = addr_hit[69] & reg_we & !reg_error; + + assign prio69_wd = reg_wdata[1:0]; + assign prio70_we = addr_hit[70] & reg_we & !reg_error; + + assign prio70_wd = reg_wdata[1:0]; + assign prio71_we = addr_hit[71] & reg_we & !reg_error; + + assign prio71_wd = reg_wdata[1:0]; + assign prio72_we = addr_hit[72] & reg_we & !reg_error; + + assign prio72_wd = reg_wdata[1:0]; + assign prio73_we = addr_hit[73] & reg_we & !reg_error; + + assign prio73_wd = reg_wdata[1:0]; + assign prio74_we = addr_hit[74] & reg_we & !reg_error; + + assign prio74_wd = reg_wdata[1:0]; + assign prio75_we = addr_hit[75] & reg_we & !reg_error; + + assign prio75_wd = reg_wdata[1:0]; + assign prio76_we = addr_hit[76] & reg_we & !reg_error; + + assign prio76_wd = reg_wdata[1:0]; + assign prio77_we = addr_hit[77] & reg_we & !reg_error; + + assign prio77_wd = reg_wdata[1:0]; + assign prio78_we = addr_hit[78] & reg_we & !reg_error; + + assign prio78_wd = reg_wdata[1:0]; + assign prio79_we = addr_hit[79] & reg_we & !reg_error; + + assign prio79_wd = reg_wdata[1:0]; + assign prio80_we = addr_hit[80] & reg_we & !reg_error; + + assign prio80_wd = reg_wdata[1:0]; + assign prio81_we = addr_hit[81] & reg_we & !reg_error; + + assign prio81_wd = reg_wdata[1:0]; + assign prio82_we = addr_hit[82] & reg_we & !reg_error; + + assign prio82_wd = reg_wdata[1:0]; + assign prio83_we = addr_hit[83] & reg_we & !reg_error; + + assign prio83_wd = reg_wdata[1:0]; + assign prio84_we = addr_hit[84] & reg_we & !reg_error; + + assign prio84_wd = reg_wdata[1:0]; + assign prio85_we = addr_hit[85] & reg_we & !reg_error; + + assign prio85_wd = reg_wdata[1:0]; + assign prio86_we = addr_hit[86] & reg_we & !reg_error; + + assign prio86_wd = reg_wdata[1:0]; + assign prio87_we = addr_hit[87] & reg_we & !reg_error; + + assign prio87_wd = reg_wdata[1:0]; + assign prio88_we = addr_hit[88] & reg_we & !reg_error; + + assign prio88_wd = reg_wdata[1:0]; + assign prio89_we = addr_hit[89] & reg_we & !reg_error; + + assign prio89_wd = reg_wdata[1:0]; + assign prio90_we = addr_hit[90] & reg_we & !reg_error; + + assign prio90_wd = reg_wdata[1:0]; + assign prio91_we = addr_hit[91] & reg_we & !reg_error; + + assign prio91_wd = reg_wdata[1:0]; + assign prio92_we = addr_hit[92] & reg_we & !reg_error; + + assign prio92_wd = reg_wdata[1:0]; + assign prio93_we = addr_hit[93] & reg_we & !reg_error; + + assign prio93_wd = reg_wdata[1:0]; + assign prio94_we = addr_hit[94] & reg_we & !reg_error; + + assign prio94_wd = reg_wdata[1:0]; + assign prio95_we = addr_hit[95] & reg_we & !reg_error; + + assign prio95_wd = reg_wdata[1:0]; + assign prio96_we = addr_hit[96] & reg_we & !reg_error; + + assign prio96_wd = reg_wdata[1:0]; + assign prio97_we = addr_hit[97] & reg_we & !reg_error; + + assign prio97_wd = reg_wdata[1:0]; + assign prio98_we = addr_hit[98] & reg_we & !reg_error; + + assign prio98_wd = reg_wdata[1:0]; + assign prio99_we = addr_hit[99] & reg_we & !reg_error; + + assign prio99_wd = reg_wdata[1:0]; + assign prio100_we = addr_hit[100] & reg_we & !reg_error; + + assign prio100_wd = reg_wdata[1:0]; + assign prio101_we = addr_hit[101] & reg_we & !reg_error; + + assign prio101_wd = reg_wdata[1:0]; + assign prio102_we = addr_hit[102] & reg_we & !reg_error; + + assign prio102_wd = reg_wdata[1:0]; + assign prio103_we = addr_hit[103] & reg_we & !reg_error; + + assign prio103_wd = reg_wdata[1:0]; + assign prio104_we = addr_hit[104] & reg_we & !reg_error; + + assign prio104_wd = reg_wdata[1:0]; + assign prio105_we = addr_hit[105] & reg_we & !reg_error; + + assign prio105_wd = reg_wdata[1:0]; + assign prio106_we = addr_hit[106] & reg_we & !reg_error; + + assign prio106_wd = reg_wdata[1:0]; + assign prio107_we = addr_hit[107] & reg_we & !reg_error; + + assign prio107_wd = reg_wdata[1:0]; + assign prio108_we = addr_hit[108] & reg_we & !reg_error; + + assign prio108_wd = reg_wdata[1:0]; + assign prio109_we = addr_hit[109] & reg_we & !reg_error; + + assign prio109_wd = reg_wdata[1:0]; + assign prio110_we = addr_hit[110] & reg_we & !reg_error; + + assign prio110_wd = reg_wdata[1:0]; + assign prio111_we = addr_hit[111] & reg_we & !reg_error; + + assign prio111_wd = reg_wdata[1:0]; + assign prio112_we = addr_hit[112] & reg_we & !reg_error; + + assign prio112_wd = reg_wdata[1:0]; + assign prio113_we = addr_hit[113] & reg_we & !reg_error; + + assign prio113_wd = reg_wdata[1:0]; + assign prio114_we = addr_hit[114] & reg_we & !reg_error; + + assign prio114_wd = reg_wdata[1:0]; + assign prio115_we = addr_hit[115] & reg_we & !reg_error; + + assign prio115_wd = reg_wdata[1:0]; + assign prio116_we = addr_hit[116] & reg_we & !reg_error; + + assign prio116_wd = reg_wdata[1:0]; + assign prio117_we = addr_hit[117] & reg_we & !reg_error; + + assign prio117_wd = reg_wdata[1:0]; + assign prio118_we = addr_hit[118] & reg_we & !reg_error; + + assign prio118_wd = reg_wdata[1:0]; + assign prio119_we = addr_hit[119] & reg_we & !reg_error; + + assign prio119_wd = reg_wdata[1:0]; + assign prio120_we = addr_hit[120] & reg_we & !reg_error; + + assign prio120_wd = reg_wdata[1:0]; + assign prio121_we = addr_hit[121] & reg_we & !reg_error; + + assign prio121_wd = reg_wdata[1:0]; + assign prio122_we = addr_hit[122] & reg_we & !reg_error; + + assign prio122_wd = reg_wdata[1:0]; + assign prio123_we = addr_hit[123] & reg_we & !reg_error; + + assign prio123_wd = reg_wdata[1:0]; + assign prio124_we = addr_hit[124] & reg_we & !reg_error; + + assign prio124_wd = reg_wdata[1:0]; + assign prio125_we = addr_hit[125] & reg_we & !reg_error; + + assign prio125_wd = reg_wdata[1:0]; + assign prio126_we = addr_hit[126] & reg_we & !reg_error; + + assign prio126_wd = reg_wdata[1:0]; + assign prio127_we = addr_hit[127] & reg_we & !reg_error; + + assign prio127_wd = reg_wdata[1:0]; + assign prio128_we = addr_hit[128] & reg_we & !reg_error; + + assign prio128_wd = reg_wdata[1:0]; + assign prio129_we = addr_hit[129] & reg_we & !reg_error; + + assign prio129_wd = reg_wdata[1:0]; + assign prio130_we = addr_hit[130] & reg_we & !reg_error; + + assign prio130_wd = reg_wdata[1:0]; + assign prio131_we = addr_hit[131] & reg_we & !reg_error; + + assign prio131_wd = reg_wdata[1:0]; + assign prio132_we = addr_hit[132] & reg_we & !reg_error; + + assign prio132_wd = reg_wdata[1:0]; + assign prio133_we = addr_hit[133] & reg_we & !reg_error; + + assign prio133_wd = reg_wdata[1:0]; + assign prio134_we = addr_hit[134] & reg_we & !reg_error; + + assign prio134_wd = reg_wdata[1:0]; + assign prio135_we = addr_hit[135] & reg_we & !reg_error; + + assign prio135_wd = reg_wdata[1:0]; + assign prio136_we = addr_hit[136] & reg_we & !reg_error; + + assign prio136_wd = reg_wdata[1:0]; + assign prio137_we = addr_hit[137] & reg_we & !reg_error; + + assign prio137_wd = reg_wdata[1:0]; + assign prio138_we = addr_hit[138] & reg_we & !reg_error; + + assign prio138_wd = reg_wdata[1:0]; + assign prio139_we = addr_hit[139] & reg_we & !reg_error; + + assign prio139_wd = reg_wdata[1:0]; + assign prio140_we = addr_hit[140] & reg_we & !reg_error; + + assign prio140_wd = reg_wdata[1:0]; + assign prio141_we = addr_hit[141] & reg_we & !reg_error; + + assign prio141_wd = reg_wdata[1:0]; + assign prio142_we = addr_hit[142] & reg_we & !reg_error; + + assign prio142_wd = reg_wdata[1:0]; + assign prio143_we = addr_hit[143] & reg_we & !reg_error; + + assign prio143_wd = reg_wdata[1:0]; + assign prio144_we = addr_hit[144] & reg_we & !reg_error; + + assign prio144_wd = reg_wdata[1:0]; + assign prio145_we = addr_hit[145] & reg_we & !reg_error; + + assign prio145_wd = reg_wdata[1:0]; + assign prio146_we = addr_hit[146] & reg_we & !reg_error; + + assign prio146_wd = reg_wdata[1:0]; + assign prio147_we = addr_hit[147] & reg_we & !reg_error; + + assign prio147_wd = reg_wdata[1:0]; + assign prio148_we = addr_hit[148] & reg_we & !reg_error; + + assign prio148_wd = reg_wdata[1:0]; + assign prio149_we = addr_hit[149] & reg_we & !reg_error; + + assign prio149_wd = reg_wdata[1:0]; + assign prio150_we = addr_hit[150] & reg_we & !reg_error; + + assign prio150_wd = reg_wdata[1:0]; + assign prio151_we = addr_hit[151] & reg_we & !reg_error; + + assign prio151_wd = reg_wdata[1:0]; + assign prio152_we = addr_hit[152] & reg_we & !reg_error; + + assign prio152_wd = reg_wdata[1:0]; + assign prio153_we = addr_hit[153] & reg_we & !reg_error; + + assign prio153_wd = reg_wdata[1:0]; + assign prio154_we = addr_hit[154] & reg_we & !reg_error; + + assign prio154_wd = reg_wdata[1:0]; + assign prio155_we = addr_hit[155] & reg_we & !reg_error; + + assign prio155_wd = reg_wdata[1:0]; + assign prio156_we = addr_hit[156] & reg_we & !reg_error; + + assign prio156_wd = reg_wdata[1:0]; + assign prio157_we = addr_hit[157] & reg_we & !reg_error; + + assign prio157_wd = reg_wdata[1:0]; + assign prio158_we = addr_hit[158] & reg_we & !reg_error; + + assign prio158_wd = reg_wdata[1:0]; + assign prio159_we = addr_hit[159] & reg_we & !reg_error; + + assign prio159_wd = reg_wdata[1:0]; + assign ie0_0_we = addr_hit[165] & reg_we & !reg_error; + + assign ie0_0_e_0_wd = reg_wdata[0]; + + assign ie0_0_e_1_wd = reg_wdata[1]; + + assign ie0_0_e_2_wd = reg_wdata[2]; + + assign ie0_0_e_3_wd = reg_wdata[3]; + + assign ie0_0_e_4_wd = reg_wdata[4]; + + assign ie0_0_e_5_wd = reg_wdata[5]; + + assign ie0_0_e_6_wd = reg_wdata[6]; + + assign ie0_0_e_7_wd = reg_wdata[7]; + + assign ie0_0_e_8_wd = reg_wdata[8]; + + assign ie0_0_e_9_wd = reg_wdata[9]; + + assign ie0_0_e_10_wd = reg_wdata[10]; + + assign ie0_0_e_11_wd = reg_wdata[11]; + + assign ie0_0_e_12_wd = reg_wdata[12]; + + assign ie0_0_e_13_wd = reg_wdata[13]; + + assign ie0_0_e_14_wd = reg_wdata[14]; + + assign ie0_0_e_15_wd = reg_wdata[15]; + + assign ie0_0_e_16_wd = reg_wdata[16]; + + assign ie0_0_e_17_wd = reg_wdata[17]; + + assign ie0_0_e_18_wd = reg_wdata[18]; + + assign ie0_0_e_19_wd = reg_wdata[19]; + + assign ie0_0_e_20_wd = reg_wdata[20]; + + assign ie0_0_e_21_wd = reg_wdata[21]; + + assign ie0_0_e_22_wd = reg_wdata[22]; + + assign ie0_0_e_23_wd = reg_wdata[23]; + + assign ie0_0_e_24_wd = reg_wdata[24]; + + assign ie0_0_e_25_wd = reg_wdata[25]; + + assign ie0_0_e_26_wd = reg_wdata[26]; + + assign ie0_0_e_27_wd = reg_wdata[27]; + + assign ie0_0_e_28_wd = reg_wdata[28]; + + assign ie0_0_e_29_wd = reg_wdata[29]; + + assign ie0_0_e_30_wd = reg_wdata[30]; + + assign ie0_0_e_31_wd = reg_wdata[31]; + assign ie0_1_we = addr_hit[166] & reg_we & !reg_error; + + assign ie0_1_e_32_wd = reg_wdata[0]; + + assign ie0_1_e_33_wd = reg_wdata[1]; + + assign ie0_1_e_34_wd = reg_wdata[2]; + + assign ie0_1_e_35_wd = reg_wdata[3]; + + assign ie0_1_e_36_wd = reg_wdata[4]; + + assign ie0_1_e_37_wd = reg_wdata[5]; + + assign ie0_1_e_38_wd = reg_wdata[6]; + + assign ie0_1_e_39_wd = reg_wdata[7]; + + assign ie0_1_e_40_wd = reg_wdata[8]; + + assign ie0_1_e_41_wd = reg_wdata[9]; + + assign ie0_1_e_42_wd = reg_wdata[10]; + + assign ie0_1_e_43_wd = reg_wdata[11]; + + assign ie0_1_e_44_wd = reg_wdata[12]; + + assign ie0_1_e_45_wd = reg_wdata[13]; + + assign ie0_1_e_46_wd = reg_wdata[14]; + + assign ie0_1_e_47_wd = reg_wdata[15]; + + assign ie0_1_e_48_wd = reg_wdata[16]; + + assign ie0_1_e_49_wd = reg_wdata[17]; + + assign ie0_1_e_50_wd = reg_wdata[18]; + + assign ie0_1_e_51_wd = reg_wdata[19]; + + assign ie0_1_e_52_wd = reg_wdata[20]; + + assign ie0_1_e_53_wd = reg_wdata[21]; + + assign ie0_1_e_54_wd = reg_wdata[22]; + + assign ie0_1_e_55_wd = reg_wdata[23]; + + assign ie0_1_e_56_wd = reg_wdata[24]; + + assign ie0_1_e_57_wd = reg_wdata[25]; + + assign ie0_1_e_58_wd = reg_wdata[26]; + + assign ie0_1_e_59_wd = reg_wdata[27]; + + assign ie0_1_e_60_wd = reg_wdata[28]; + + assign ie0_1_e_61_wd = reg_wdata[29]; + + assign ie0_1_e_62_wd = reg_wdata[30]; + + assign ie0_1_e_63_wd = reg_wdata[31]; + assign ie0_2_we = addr_hit[167] & reg_we & !reg_error; + + assign ie0_2_e_64_wd = reg_wdata[0]; + + assign ie0_2_e_65_wd = reg_wdata[1]; + + assign ie0_2_e_66_wd = reg_wdata[2]; + + assign ie0_2_e_67_wd = reg_wdata[3]; + + assign ie0_2_e_68_wd = reg_wdata[4]; + + assign ie0_2_e_69_wd = reg_wdata[5]; + + assign ie0_2_e_70_wd = reg_wdata[6]; + + assign ie0_2_e_71_wd = reg_wdata[7]; + + assign ie0_2_e_72_wd = reg_wdata[8]; + + assign ie0_2_e_73_wd = reg_wdata[9]; + + assign ie0_2_e_74_wd = reg_wdata[10]; + + assign ie0_2_e_75_wd = reg_wdata[11]; + + assign ie0_2_e_76_wd = reg_wdata[12]; + + assign ie0_2_e_77_wd = reg_wdata[13]; + + assign ie0_2_e_78_wd = reg_wdata[14]; + + assign ie0_2_e_79_wd = reg_wdata[15]; + + assign ie0_2_e_80_wd = reg_wdata[16]; + + assign ie0_2_e_81_wd = reg_wdata[17]; + + assign ie0_2_e_82_wd = reg_wdata[18]; + + assign ie0_2_e_83_wd = reg_wdata[19]; + + assign ie0_2_e_84_wd = reg_wdata[20]; + + assign ie0_2_e_85_wd = reg_wdata[21]; + + assign ie0_2_e_86_wd = reg_wdata[22]; + + assign ie0_2_e_87_wd = reg_wdata[23]; + + assign ie0_2_e_88_wd = reg_wdata[24]; + + assign ie0_2_e_89_wd = reg_wdata[25]; + + assign ie0_2_e_90_wd = reg_wdata[26]; + + assign ie0_2_e_91_wd = reg_wdata[27]; + + assign ie0_2_e_92_wd = reg_wdata[28]; + + assign ie0_2_e_93_wd = reg_wdata[29]; + + assign ie0_2_e_94_wd = reg_wdata[30]; + + assign ie0_2_e_95_wd = reg_wdata[31]; + assign ie0_3_we = addr_hit[168] & reg_we & !reg_error; + + assign ie0_3_e_96_wd = reg_wdata[0]; + + assign ie0_3_e_97_wd = reg_wdata[1]; + + assign ie0_3_e_98_wd = reg_wdata[2]; + + assign ie0_3_e_99_wd = reg_wdata[3]; + + assign ie0_3_e_100_wd = reg_wdata[4]; + + assign ie0_3_e_101_wd = reg_wdata[5]; + + assign ie0_3_e_102_wd = reg_wdata[6]; + + assign ie0_3_e_103_wd = reg_wdata[7]; + + assign ie0_3_e_104_wd = reg_wdata[8]; + + assign ie0_3_e_105_wd = reg_wdata[9]; + + assign ie0_3_e_106_wd = reg_wdata[10]; + + assign ie0_3_e_107_wd = reg_wdata[11]; + + assign ie0_3_e_108_wd = reg_wdata[12]; + + assign ie0_3_e_109_wd = reg_wdata[13]; + + assign ie0_3_e_110_wd = reg_wdata[14]; + + assign ie0_3_e_111_wd = reg_wdata[15]; + + assign ie0_3_e_112_wd = reg_wdata[16]; + + assign ie0_3_e_113_wd = reg_wdata[17]; + + assign ie0_3_e_114_wd = reg_wdata[18]; + + assign ie0_3_e_115_wd = reg_wdata[19]; + + assign ie0_3_e_116_wd = reg_wdata[20]; + + assign ie0_3_e_117_wd = reg_wdata[21]; + + assign ie0_3_e_118_wd = reg_wdata[22]; + + assign ie0_3_e_119_wd = reg_wdata[23]; + + assign ie0_3_e_120_wd = reg_wdata[24]; + + assign ie0_3_e_121_wd = reg_wdata[25]; + + assign ie0_3_e_122_wd = reg_wdata[26]; + + assign ie0_3_e_123_wd = reg_wdata[27]; + + assign ie0_3_e_124_wd = reg_wdata[28]; + + assign ie0_3_e_125_wd = reg_wdata[29]; + + assign ie0_3_e_126_wd = reg_wdata[30]; + + assign ie0_3_e_127_wd = reg_wdata[31]; + assign ie0_4_we = addr_hit[169] & reg_we & !reg_error; + + assign ie0_4_e_128_wd = reg_wdata[0]; + + assign ie0_4_e_129_wd = reg_wdata[1]; + + assign ie0_4_e_130_wd = reg_wdata[2]; + + assign ie0_4_e_131_wd = reg_wdata[3]; + + assign ie0_4_e_132_wd = reg_wdata[4]; + + assign ie0_4_e_133_wd = reg_wdata[5]; + + assign ie0_4_e_134_wd = reg_wdata[6]; + + assign ie0_4_e_135_wd = reg_wdata[7]; + + assign ie0_4_e_136_wd = reg_wdata[8]; + + assign ie0_4_e_137_wd = reg_wdata[9]; + + assign ie0_4_e_138_wd = reg_wdata[10]; + + assign ie0_4_e_139_wd = reg_wdata[11]; + + assign ie0_4_e_140_wd = reg_wdata[12]; + + assign ie0_4_e_141_wd = reg_wdata[13]; + + assign ie0_4_e_142_wd = reg_wdata[14]; + + assign ie0_4_e_143_wd = reg_wdata[15]; + + assign ie0_4_e_144_wd = reg_wdata[16]; + + assign ie0_4_e_145_wd = reg_wdata[17]; + + assign ie0_4_e_146_wd = reg_wdata[18]; + + assign ie0_4_e_147_wd = reg_wdata[19]; + + assign ie0_4_e_148_wd = reg_wdata[20]; + + assign ie0_4_e_149_wd = reg_wdata[21]; + + assign ie0_4_e_150_wd = reg_wdata[22]; + + assign ie0_4_e_151_wd = reg_wdata[23]; + + assign ie0_4_e_152_wd = reg_wdata[24]; + + assign ie0_4_e_153_wd = reg_wdata[25]; + + assign ie0_4_e_154_wd = reg_wdata[26]; + + assign ie0_4_e_155_wd = reg_wdata[27]; + + assign ie0_4_e_156_wd = reg_wdata[28]; + + assign ie0_4_e_157_wd = reg_wdata[29]; + + assign ie0_4_e_158_wd = reg_wdata[30]; + + assign ie0_4_e_159_wd = reg_wdata[31]; + assign threshold0_we = addr_hit[170] & reg_we & !reg_error; + + assign threshold0_wd = reg_wdata[1:0]; + assign cc0_re = addr_hit[171] & reg_re & !reg_error; + assign cc0_we = addr_hit[171] & reg_we & !reg_error; + + assign cc0_wd = reg_wdata[7:0]; + assign msip0_we = addr_hit[172] & reg_we & !reg_error; + + assign msip0_wd = reg_wdata[0]; + assign alert_test_we = addr_hit[173] & reg_we & !reg_error; + + assign alert_test_wd = reg_wdata[0]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check = '0; + reg_we_check[0] = prio0_we; + reg_we_check[1] = prio1_we; + reg_we_check[2] = prio2_we; + reg_we_check[3] = prio3_we; + reg_we_check[4] = prio4_we; + reg_we_check[5] = prio5_we; + reg_we_check[6] = prio6_we; + reg_we_check[7] = prio7_we; + reg_we_check[8] = prio8_we; + reg_we_check[9] = prio9_we; + reg_we_check[10] = prio10_we; + reg_we_check[11] = prio11_we; + reg_we_check[12] = prio12_we; + reg_we_check[13] = prio13_we; + reg_we_check[14] = prio14_we; + reg_we_check[15] = prio15_we; + reg_we_check[16] = prio16_we; + reg_we_check[17] = prio17_we; + reg_we_check[18] = prio18_we; + reg_we_check[19] = prio19_we; + reg_we_check[20] = prio20_we; + reg_we_check[21] = prio21_we; + reg_we_check[22] = prio22_we; + reg_we_check[23] = prio23_we; + reg_we_check[24] = prio24_we; + reg_we_check[25] = prio25_we; + reg_we_check[26] = prio26_we; + reg_we_check[27] = prio27_we; + reg_we_check[28] = prio28_we; + reg_we_check[29] = prio29_we; + reg_we_check[30] = prio30_we; + reg_we_check[31] = prio31_we; + reg_we_check[32] = prio32_we; + reg_we_check[33] = prio33_we; + reg_we_check[34] = prio34_we; + reg_we_check[35] = prio35_we; + reg_we_check[36] = prio36_we; + reg_we_check[37] = prio37_we; + reg_we_check[38] = prio38_we; + reg_we_check[39] = prio39_we; + reg_we_check[40] = prio40_we; + reg_we_check[41] = prio41_we; + reg_we_check[42] = prio42_we; + reg_we_check[43] = prio43_we; + reg_we_check[44] = prio44_we; + reg_we_check[45] = prio45_we; + reg_we_check[46] = prio46_we; + reg_we_check[47] = prio47_we; + reg_we_check[48] = prio48_we; + reg_we_check[49] = prio49_we; + reg_we_check[50] = prio50_we; + reg_we_check[51] = prio51_we; + reg_we_check[52] = prio52_we; + reg_we_check[53] = prio53_we; + reg_we_check[54] = prio54_we; + reg_we_check[55] = prio55_we; + reg_we_check[56] = prio56_we; + reg_we_check[57] = prio57_we; + reg_we_check[58] = prio58_we; + reg_we_check[59] = prio59_we; + reg_we_check[60] = prio60_we; + reg_we_check[61] = prio61_we; + reg_we_check[62] = prio62_we; + reg_we_check[63] = prio63_we; + reg_we_check[64] = prio64_we; + reg_we_check[65] = prio65_we; + reg_we_check[66] = prio66_we; + reg_we_check[67] = prio67_we; + reg_we_check[68] = prio68_we; + reg_we_check[69] = prio69_we; + reg_we_check[70] = prio70_we; + reg_we_check[71] = prio71_we; + reg_we_check[72] = prio72_we; + reg_we_check[73] = prio73_we; + reg_we_check[74] = prio74_we; + reg_we_check[75] = prio75_we; + reg_we_check[76] = prio76_we; + reg_we_check[77] = prio77_we; + reg_we_check[78] = prio78_we; + reg_we_check[79] = prio79_we; + reg_we_check[80] = prio80_we; + reg_we_check[81] = prio81_we; + reg_we_check[82] = prio82_we; + reg_we_check[83] = prio83_we; + reg_we_check[84] = prio84_we; + reg_we_check[85] = prio85_we; + reg_we_check[86] = prio86_we; + reg_we_check[87] = prio87_we; + reg_we_check[88] = prio88_we; + reg_we_check[89] = prio89_we; + reg_we_check[90] = prio90_we; + reg_we_check[91] = prio91_we; + reg_we_check[92] = prio92_we; + reg_we_check[93] = prio93_we; + reg_we_check[94] = prio94_we; + reg_we_check[95] = prio95_we; + reg_we_check[96] = prio96_we; + reg_we_check[97] = prio97_we; + reg_we_check[98] = prio98_we; + reg_we_check[99] = prio99_we; + reg_we_check[100] = prio100_we; + reg_we_check[101] = prio101_we; + reg_we_check[102] = prio102_we; + reg_we_check[103] = prio103_we; + reg_we_check[104] = prio104_we; + reg_we_check[105] = prio105_we; + reg_we_check[106] = prio106_we; + reg_we_check[107] = prio107_we; + reg_we_check[108] = prio108_we; + reg_we_check[109] = prio109_we; + reg_we_check[110] = prio110_we; + reg_we_check[111] = prio111_we; + reg_we_check[112] = prio112_we; + reg_we_check[113] = prio113_we; + reg_we_check[114] = prio114_we; + reg_we_check[115] = prio115_we; + reg_we_check[116] = prio116_we; + reg_we_check[117] = prio117_we; + reg_we_check[118] = prio118_we; + reg_we_check[119] = prio119_we; + reg_we_check[120] = prio120_we; + reg_we_check[121] = prio121_we; + reg_we_check[122] = prio122_we; + reg_we_check[123] = prio123_we; + reg_we_check[124] = prio124_we; + reg_we_check[125] = prio125_we; + reg_we_check[126] = prio126_we; + reg_we_check[127] = prio127_we; + reg_we_check[128] = prio128_we; + reg_we_check[129] = prio129_we; + reg_we_check[130] = prio130_we; + reg_we_check[131] = prio131_we; + reg_we_check[132] = prio132_we; + reg_we_check[133] = prio133_we; + reg_we_check[134] = prio134_we; + reg_we_check[135] = prio135_we; + reg_we_check[136] = prio136_we; + reg_we_check[137] = prio137_we; + reg_we_check[138] = prio138_we; + reg_we_check[139] = prio139_we; + reg_we_check[140] = prio140_we; + reg_we_check[141] = prio141_we; + reg_we_check[142] = prio142_we; + reg_we_check[143] = prio143_we; + reg_we_check[144] = prio144_we; + reg_we_check[145] = prio145_we; + reg_we_check[146] = prio146_we; + reg_we_check[147] = prio147_we; + reg_we_check[148] = prio148_we; + reg_we_check[149] = prio149_we; + reg_we_check[150] = prio150_we; + reg_we_check[151] = prio151_we; + reg_we_check[152] = prio152_we; + reg_we_check[153] = prio153_we; + reg_we_check[154] = prio154_we; + reg_we_check[155] = prio155_we; + reg_we_check[156] = prio156_we; + reg_we_check[157] = prio157_we; + reg_we_check[158] = prio158_we; + reg_we_check[159] = prio159_we; + reg_we_check[160] = 1'b0; + reg_we_check[161] = 1'b0; + reg_we_check[162] = 1'b0; + reg_we_check[163] = 1'b0; + reg_we_check[164] = 1'b0; + reg_we_check[165] = ie0_0_we; + reg_we_check[166] = ie0_1_we; + reg_we_check[167] = ie0_2_we; + reg_we_check[168] = ie0_3_we; + reg_we_check[169] = ie0_4_we; + reg_we_check[170] = threshold0_we; + reg_we_check[171] = cc0_we; + reg_we_check[172] = msip0_we; + reg_we_check[173] = alert_test_we; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[1:0] = prio0_qs; + end + + addr_hit[1]: begin + reg_rdata_next[1:0] = prio1_qs; + end + + addr_hit[2]: begin + reg_rdata_next[1:0] = prio2_qs; + end + + addr_hit[3]: begin + reg_rdata_next[1:0] = prio3_qs; + end + + addr_hit[4]: begin + reg_rdata_next[1:0] = prio4_qs; + end + + addr_hit[5]: begin + reg_rdata_next[1:0] = prio5_qs; + end + + addr_hit[6]: begin + reg_rdata_next[1:0] = prio6_qs; + end + + addr_hit[7]: begin + reg_rdata_next[1:0] = prio7_qs; + end + + addr_hit[8]: begin + reg_rdata_next[1:0] = prio8_qs; + end + + addr_hit[9]: begin + reg_rdata_next[1:0] = prio9_qs; + end + + addr_hit[10]: begin + reg_rdata_next[1:0] = prio10_qs; + end + + addr_hit[11]: begin + reg_rdata_next[1:0] = prio11_qs; + end + + addr_hit[12]: begin + reg_rdata_next[1:0] = prio12_qs; + end + + addr_hit[13]: begin + reg_rdata_next[1:0] = prio13_qs; + end + + addr_hit[14]: begin + reg_rdata_next[1:0] = prio14_qs; + end + + addr_hit[15]: begin + reg_rdata_next[1:0] = prio15_qs; + end + + addr_hit[16]: begin + reg_rdata_next[1:0] = prio16_qs; + end + + addr_hit[17]: begin + reg_rdata_next[1:0] = prio17_qs; + end + + addr_hit[18]: begin + reg_rdata_next[1:0] = prio18_qs; + end + + addr_hit[19]: begin + reg_rdata_next[1:0] = prio19_qs; + end + + addr_hit[20]: begin + reg_rdata_next[1:0] = prio20_qs; + end + + addr_hit[21]: begin + reg_rdata_next[1:0] = prio21_qs; + end + + addr_hit[22]: begin + reg_rdata_next[1:0] = prio22_qs; + end + + addr_hit[23]: begin + reg_rdata_next[1:0] = prio23_qs; + end + + addr_hit[24]: begin + reg_rdata_next[1:0] = prio24_qs; + end + + addr_hit[25]: begin + reg_rdata_next[1:0] = prio25_qs; + end + + addr_hit[26]: begin + reg_rdata_next[1:0] = prio26_qs; + end + + addr_hit[27]: begin + reg_rdata_next[1:0] = prio27_qs; + end + + addr_hit[28]: begin + reg_rdata_next[1:0] = prio28_qs; + end + + addr_hit[29]: begin + reg_rdata_next[1:0] = prio29_qs; + end + + addr_hit[30]: begin + reg_rdata_next[1:0] = prio30_qs; + end + + addr_hit[31]: begin + reg_rdata_next[1:0] = prio31_qs; + end + + addr_hit[32]: begin + reg_rdata_next[1:0] = prio32_qs; + end + + addr_hit[33]: begin + reg_rdata_next[1:0] = prio33_qs; + end + + addr_hit[34]: begin + reg_rdata_next[1:0] = prio34_qs; + end + + addr_hit[35]: begin + reg_rdata_next[1:0] = prio35_qs; + end + + addr_hit[36]: begin + reg_rdata_next[1:0] = prio36_qs; + end + + addr_hit[37]: begin + reg_rdata_next[1:0] = prio37_qs; + end + + addr_hit[38]: begin + reg_rdata_next[1:0] = prio38_qs; + end + + addr_hit[39]: begin + reg_rdata_next[1:0] = prio39_qs; + end + + addr_hit[40]: begin + reg_rdata_next[1:0] = prio40_qs; + end + + addr_hit[41]: begin + reg_rdata_next[1:0] = prio41_qs; + end + + addr_hit[42]: begin + reg_rdata_next[1:0] = prio42_qs; + end + + addr_hit[43]: begin + reg_rdata_next[1:0] = prio43_qs; + end + + addr_hit[44]: begin + reg_rdata_next[1:0] = prio44_qs; + end + + addr_hit[45]: begin + reg_rdata_next[1:0] = prio45_qs; + end + + addr_hit[46]: begin + reg_rdata_next[1:0] = prio46_qs; + end + + addr_hit[47]: begin + reg_rdata_next[1:0] = prio47_qs; + end + + addr_hit[48]: begin + reg_rdata_next[1:0] = prio48_qs; + end + + addr_hit[49]: begin + reg_rdata_next[1:0] = prio49_qs; + end + + addr_hit[50]: begin + reg_rdata_next[1:0] = prio50_qs; + end + + addr_hit[51]: begin + reg_rdata_next[1:0] = prio51_qs; + end + + addr_hit[52]: begin + reg_rdata_next[1:0] = prio52_qs; + end + + addr_hit[53]: begin + reg_rdata_next[1:0] = prio53_qs; + end + + addr_hit[54]: begin + reg_rdata_next[1:0] = prio54_qs; + end + + addr_hit[55]: begin + reg_rdata_next[1:0] = prio55_qs; + end + + addr_hit[56]: begin + reg_rdata_next[1:0] = prio56_qs; + end + + addr_hit[57]: begin + reg_rdata_next[1:0] = prio57_qs; + end + + addr_hit[58]: begin + reg_rdata_next[1:0] = prio58_qs; + end + + addr_hit[59]: begin + reg_rdata_next[1:0] = prio59_qs; + end + + addr_hit[60]: begin + reg_rdata_next[1:0] = prio60_qs; + end + + addr_hit[61]: begin + reg_rdata_next[1:0] = prio61_qs; + end + + addr_hit[62]: begin + reg_rdata_next[1:0] = prio62_qs; + end + + addr_hit[63]: begin + reg_rdata_next[1:0] = prio63_qs; + end + + addr_hit[64]: begin + reg_rdata_next[1:0] = prio64_qs; + end + + addr_hit[65]: begin + reg_rdata_next[1:0] = prio65_qs; + end + + addr_hit[66]: begin + reg_rdata_next[1:0] = prio66_qs; + end + + addr_hit[67]: begin + reg_rdata_next[1:0] = prio67_qs; + end + + addr_hit[68]: begin + reg_rdata_next[1:0] = prio68_qs; + end + + addr_hit[69]: begin + reg_rdata_next[1:0] = prio69_qs; + end + + addr_hit[70]: begin + reg_rdata_next[1:0] = prio70_qs; + end + + addr_hit[71]: begin + reg_rdata_next[1:0] = prio71_qs; + end + + addr_hit[72]: begin + reg_rdata_next[1:0] = prio72_qs; + end + + addr_hit[73]: begin + reg_rdata_next[1:0] = prio73_qs; + end + + addr_hit[74]: begin + reg_rdata_next[1:0] = prio74_qs; + end + + addr_hit[75]: begin + reg_rdata_next[1:0] = prio75_qs; + end + + addr_hit[76]: begin + reg_rdata_next[1:0] = prio76_qs; + end + + addr_hit[77]: begin + reg_rdata_next[1:0] = prio77_qs; + end + + addr_hit[78]: begin + reg_rdata_next[1:0] = prio78_qs; + end + + addr_hit[79]: begin + reg_rdata_next[1:0] = prio79_qs; + end + + addr_hit[80]: begin + reg_rdata_next[1:0] = prio80_qs; + end + + addr_hit[81]: begin + reg_rdata_next[1:0] = prio81_qs; + end + + addr_hit[82]: begin + reg_rdata_next[1:0] = prio82_qs; + end + + addr_hit[83]: begin + reg_rdata_next[1:0] = prio83_qs; + end + + addr_hit[84]: begin + reg_rdata_next[1:0] = prio84_qs; + end + + addr_hit[85]: begin + reg_rdata_next[1:0] = prio85_qs; + end + + addr_hit[86]: begin + reg_rdata_next[1:0] = prio86_qs; + end + + addr_hit[87]: begin + reg_rdata_next[1:0] = prio87_qs; + end + + addr_hit[88]: begin + reg_rdata_next[1:0] = prio88_qs; + end + + addr_hit[89]: begin + reg_rdata_next[1:0] = prio89_qs; + end + + addr_hit[90]: begin + reg_rdata_next[1:0] = prio90_qs; + end + + addr_hit[91]: begin + reg_rdata_next[1:0] = prio91_qs; + end + + addr_hit[92]: begin + reg_rdata_next[1:0] = prio92_qs; + end + + addr_hit[93]: begin + reg_rdata_next[1:0] = prio93_qs; + end + + addr_hit[94]: begin + reg_rdata_next[1:0] = prio94_qs; + end + + addr_hit[95]: begin + reg_rdata_next[1:0] = prio95_qs; + end + + addr_hit[96]: begin + reg_rdata_next[1:0] = prio96_qs; + end + + addr_hit[97]: begin + reg_rdata_next[1:0] = prio97_qs; + end + + addr_hit[98]: begin + reg_rdata_next[1:0] = prio98_qs; + end + + addr_hit[99]: begin + reg_rdata_next[1:0] = prio99_qs; + end + + addr_hit[100]: begin + reg_rdata_next[1:0] = prio100_qs; + end + + addr_hit[101]: begin + reg_rdata_next[1:0] = prio101_qs; + end + + addr_hit[102]: begin + reg_rdata_next[1:0] = prio102_qs; + end + + addr_hit[103]: begin + reg_rdata_next[1:0] = prio103_qs; + end + + addr_hit[104]: begin + reg_rdata_next[1:0] = prio104_qs; + end + + addr_hit[105]: begin + reg_rdata_next[1:0] = prio105_qs; + end + + addr_hit[106]: begin + reg_rdata_next[1:0] = prio106_qs; + end + + addr_hit[107]: begin + reg_rdata_next[1:0] = prio107_qs; + end + + addr_hit[108]: begin + reg_rdata_next[1:0] = prio108_qs; + end + + addr_hit[109]: begin + reg_rdata_next[1:0] = prio109_qs; + end + + addr_hit[110]: begin + reg_rdata_next[1:0] = prio110_qs; + end + + addr_hit[111]: begin + reg_rdata_next[1:0] = prio111_qs; + end + + addr_hit[112]: begin + reg_rdata_next[1:0] = prio112_qs; + end + + addr_hit[113]: begin + reg_rdata_next[1:0] = prio113_qs; + end + + addr_hit[114]: begin + reg_rdata_next[1:0] = prio114_qs; + end + + addr_hit[115]: begin + reg_rdata_next[1:0] = prio115_qs; + end + + addr_hit[116]: begin + reg_rdata_next[1:0] = prio116_qs; + end + + addr_hit[117]: begin + reg_rdata_next[1:0] = prio117_qs; + end + + addr_hit[118]: begin + reg_rdata_next[1:0] = prio118_qs; + end + + addr_hit[119]: begin + reg_rdata_next[1:0] = prio119_qs; + end + + addr_hit[120]: begin + reg_rdata_next[1:0] = prio120_qs; + end + + addr_hit[121]: begin + reg_rdata_next[1:0] = prio121_qs; + end + + addr_hit[122]: begin + reg_rdata_next[1:0] = prio122_qs; + end + + addr_hit[123]: begin + reg_rdata_next[1:0] = prio123_qs; + end + + addr_hit[124]: begin + reg_rdata_next[1:0] = prio124_qs; + end + + addr_hit[125]: begin + reg_rdata_next[1:0] = prio125_qs; + end + + addr_hit[126]: begin + reg_rdata_next[1:0] = prio126_qs; + end + + addr_hit[127]: begin + reg_rdata_next[1:0] = prio127_qs; + end + + addr_hit[128]: begin + reg_rdata_next[1:0] = prio128_qs; + end + + addr_hit[129]: begin + reg_rdata_next[1:0] = prio129_qs; + end + + addr_hit[130]: begin + reg_rdata_next[1:0] = prio130_qs; + end + + addr_hit[131]: begin + reg_rdata_next[1:0] = prio131_qs; + end + + addr_hit[132]: begin + reg_rdata_next[1:0] = prio132_qs; + end + + addr_hit[133]: begin + reg_rdata_next[1:0] = prio133_qs; + end + + addr_hit[134]: begin + reg_rdata_next[1:0] = prio134_qs; + end + + addr_hit[135]: begin + reg_rdata_next[1:0] = prio135_qs; + end + + addr_hit[136]: begin + reg_rdata_next[1:0] = prio136_qs; + end + + addr_hit[137]: begin + reg_rdata_next[1:0] = prio137_qs; + end + + addr_hit[138]: begin + reg_rdata_next[1:0] = prio138_qs; + end + + addr_hit[139]: begin + reg_rdata_next[1:0] = prio139_qs; + end + + addr_hit[140]: begin + reg_rdata_next[1:0] = prio140_qs; + end + + addr_hit[141]: begin + reg_rdata_next[1:0] = prio141_qs; + end + + addr_hit[142]: begin + reg_rdata_next[1:0] = prio142_qs; + end + + addr_hit[143]: begin + reg_rdata_next[1:0] = prio143_qs; + end + + addr_hit[144]: begin + reg_rdata_next[1:0] = prio144_qs; + end + + addr_hit[145]: begin + reg_rdata_next[1:0] = prio145_qs; + end + + addr_hit[146]: begin + reg_rdata_next[1:0] = prio146_qs; + end + + addr_hit[147]: begin + reg_rdata_next[1:0] = prio147_qs; + end + + addr_hit[148]: begin + reg_rdata_next[1:0] = prio148_qs; + end + + addr_hit[149]: begin + reg_rdata_next[1:0] = prio149_qs; + end + + addr_hit[150]: begin + reg_rdata_next[1:0] = prio150_qs; + end + + addr_hit[151]: begin + reg_rdata_next[1:0] = prio151_qs; + end + + addr_hit[152]: begin + reg_rdata_next[1:0] = prio152_qs; + end + + addr_hit[153]: begin + reg_rdata_next[1:0] = prio153_qs; + end + + addr_hit[154]: begin + reg_rdata_next[1:0] = prio154_qs; + end + + addr_hit[155]: begin + reg_rdata_next[1:0] = prio155_qs; + end + + addr_hit[156]: begin + reg_rdata_next[1:0] = prio156_qs; + end + + addr_hit[157]: begin + reg_rdata_next[1:0] = prio157_qs; + end + + addr_hit[158]: begin + reg_rdata_next[1:0] = prio158_qs; + end + + addr_hit[159]: begin + reg_rdata_next[1:0] = prio159_qs; + end + + addr_hit[160]: begin + reg_rdata_next[0] = ip_0_p_0_qs; + reg_rdata_next[1] = ip_0_p_1_qs; + reg_rdata_next[2] = ip_0_p_2_qs; + reg_rdata_next[3] = ip_0_p_3_qs; + reg_rdata_next[4] = ip_0_p_4_qs; + reg_rdata_next[5] = ip_0_p_5_qs; + reg_rdata_next[6] = ip_0_p_6_qs; + reg_rdata_next[7] = ip_0_p_7_qs; + reg_rdata_next[8] = ip_0_p_8_qs; + reg_rdata_next[9] = ip_0_p_9_qs; + reg_rdata_next[10] = ip_0_p_10_qs; + reg_rdata_next[11] = ip_0_p_11_qs; + reg_rdata_next[12] = ip_0_p_12_qs; + reg_rdata_next[13] = ip_0_p_13_qs; + reg_rdata_next[14] = ip_0_p_14_qs; + reg_rdata_next[15] = ip_0_p_15_qs; + reg_rdata_next[16] = ip_0_p_16_qs; + reg_rdata_next[17] = ip_0_p_17_qs; + reg_rdata_next[18] = ip_0_p_18_qs; + reg_rdata_next[19] = ip_0_p_19_qs; + reg_rdata_next[20] = ip_0_p_20_qs; + reg_rdata_next[21] = ip_0_p_21_qs; + reg_rdata_next[22] = ip_0_p_22_qs; + reg_rdata_next[23] = ip_0_p_23_qs; + reg_rdata_next[24] = ip_0_p_24_qs; + reg_rdata_next[25] = ip_0_p_25_qs; + reg_rdata_next[26] = ip_0_p_26_qs; + reg_rdata_next[27] = ip_0_p_27_qs; + reg_rdata_next[28] = ip_0_p_28_qs; + reg_rdata_next[29] = ip_0_p_29_qs; + reg_rdata_next[30] = ip_0_p_30_qs; + reg_rdata_next[31] = ip_0_p_31_qs; + end + + addr_hit[161]: begin + reg_rdata_next[0] = ip_1_p_32_qs; + reg_rdata_next[1] = ip_1_p_33_qs; + reg_rdata_next[2] = ip_1_p_34_qs; + reg_rdata_next[3] = ip_1_p_35_qs; + reg_rdata_next[4] = ip_1_p_36_qs; + reg_rdata_next[5] = ip_1_p_37_qs; + reg_rdata_next[6] = ip_1_p_38_qs; + reg_rdata_next[7] = ip_1_p_39_qs; + reg_rdata_next[8] = ip_1_p_40_qs; + reg_rdata_next[9] = ip_1_p_41_qs; + reg_rdata_next[10] = ip_1_p_42_qs; + reg_rdata_next[11] = ip_1_p_43_qs; + reg_rdata_next[12] = ip_1_p_44_qs; + reg_rdata_next[13] = ip_1_p_45_qs; + reg_rdata_next[14] = ip_1_p_46_qs; + reg_rdata_next[15] = ip_1_p_47_qs; + reg_rdata_next[16] = ip_1_p_48_qs; + reg_rdata_next[17] = ip_1_p_49_qs; + reg_rdata_next[18] = ip_1_p_50_qs; + reg_rdata_next[19] = ip_1_p_51_qs; + reg_rdata_next[20] = ip_1_p_52_qs; + reg_rdata_next[21] = ip_1_p_53_qs; + reg_rdata_next[22] = ip_1_p_54_qs; + reg_rdata_next[23] = ip_1_p_55_qs; + reg_rdata_next[24] = ip_1_p_56_qs; + reg_rdata_next[25] = ip_1_p_57_qs; + reg_rdata_next[26] = ip_1_p_58_qs; + reg_rdata_next[27] = ip_1_p_59_qs; + reg_rdata_next[28] = ip_1_p_60_qs; + reg_rdata_next[29] = ip_1_p_61_qs; + reg_rdata_next[30] = ip_1_p_62_qs; + reg_rdata_next[31] = ip_1_p_63_qs; + end + + addr_hit[162]: begin + reg_rdata_next[0] = ip_2_p_64_qs; + reg_rdata_next[1] = ip_2_p_65_qs; + reg_rdata_next[2] = ip_2_p_66_qs; + reg_rdata_next[3] = ip_2_p_67_qs; + reg_rdata_next[4] = ip_2_p_68_qs; + reg_rdata_next[5] = ip_2_p_69_qs; + reg_rdata_next[6] = ip_2_p_70_qs; + reg_rdata_next[7] = ip_2_p_71_qs; + reg_rdata_next[8] = ip_2_p_72_qs; + reg_rdata_next[9] = ip_2_p_73_qs; + reg_rdata_next[10] = ip_2_p_74_qs; + reg_rdata_next[11] = ip_2_p_75_qs; + reg_rdata_next[12] = ip_2_p_76_qs; + reg_rdata_next[13] = ip_2_p_77_qs; + reg_rdata_next[14] = ip_2_p_78_qs; + reg_rdata_next[15] = ip_2_p_79_qs; + reg_rdata_next[16] = ip_2_p_80_qs; + reg_rdata_next[17] = ip_2_p_81_qs; + reg_rdata_next[18] = ip_2_p_82_qs; + reg_rdata_next[19] = ip_2_p_83_qs; + reg_rdata_next[20] = ip_2_p_84_qs; + reg_rdata_next[21] = ip_2_p_85_qs; + reg_rdata_next[22] = ip_2_p_86_qs; + reg_rdata_next[23] = ip_2_p_87_qs; + reg_rdata_next[24] = ip_2_p_88_qs; + reg_rdata_next[25] = ip_2_p_89_qs; + reg_rdata_next[26] = ip_2_p_90_qs; + reg_rdata_next[27] = ip_2_p_91_qs; + reg_rdata_next[28] = ip_2_p_92_qs; + reg_rdata_next[29] = ip_2_p_93_qs; + reg_rdata_next[30] = ip_2_p_94_qs; + reg_rdata_next[31] = ip_2_p_95_qs; + end + + addr_hit[163]: begin + reg_rdata_next[0] = ip_3_p_96_qs; + reg_rdata_next[1] = ip_3_p_97_qs; + reg_rdata_next[2] = ip_3_p_98_qs; + reg_rdata_next[3] = ip_3_p_99_qs; + reg_rdata_next[4] = ip_3_p_100_qs; + reg_rdata_next[5] = ip_3_p_101_qs; + reg_rdata_next[6] = ip_3_p_102_qs; + reg_rdata_next[7] = ip_3_p_103_qs; + reg_rdata_next[8] = ip_3_p_104_qs; + reg_rdata_next[9] = ip_3_p_105_qs; + reg_rdata_next[10] = ip_3_p_106_qs; + reg_rdata_next[11] = ip_3_p_107_qs; + reg_rdata_next[12] = ip_3_p_108_qs; + reg_rdata_next[13] = ip_3_p_109_qs; + reg_rdata_next[14] = ip_3_p_110_qs; + reg_rdata_next[15] = ip_3_p_111_qs; + reg_rdata_next[16] = ip_3_p_112_qs; + reg_rdata_next[17] = ip_3_p_113_qs; + reg_rdata_next[18] = ip_3_p_114_qs; + reg_rdata_next[19] = ip_3_p_115_qs; + reg_rdata_next[20] = ip_3_p_116_qs; + reg_rdata_next[21] = ip_3_p_117_qs; + reg_rdata_next[22] = ip_3_p_118_qs; + reg_rdata_next[23] = ip_3_p_119_qs; + reg_rdata_next[24] = ip_3_p_120_qs; + reg_rdata_next[25] = ip_3_p_121_qs; + reg_rdata_next[26] = ip_3_p_122_qs; + reg_rdata_next[27] = ip_3_p_123_qs; + reg_rdata_next[28] = ip_3_p_124_qs; + reg_rdata_next[29] = ip_3_p_125_qs; + reg_rdata_next[30] = ip_3_p_126_qs; + reg_rdata_next[31] = ip_3_p_127_qs; + end + + addr_hit[164]: begin + reg_rdata_next[0] = ip_4_p_128_qs; + reg_rdata_next[1] = ip_4_p_129_qs; + reg_rdata_next[2] = ip_4_p_130_qs; + reg_rdata_next[3] = ip_4_p_131_qs; + reg_rdata_next[4] = ip_4_p_132_qs; + reg_rdata_next[5] = ip_4_p_133_qs; + reg_rdata_next[6] = ip_4_p_134_qs; + reg_rdata_next[7] = ip_4_p_135_qs; + reg_rdata_next[8] = ip_4_p_136_qs; + reg_rdata_next[9] = ip_4_p_137_qs; + reg_rdata_next[10] = ip_4_p_138_qs; + reg_rdata_next[11] = ip_4_p_139_qs; + reg_rdata_next[12] = ip_4_p_140_qs; + reg_rdata_next[13] = ip_4_p_141_qs; + reg_rdata_next[14] = ip_4_p_142_qs; + reg_rdata_next[15] = ip_4_p_143_qs; + reg_rdata_next[16] = ip_4_p_144_qs; + reg_rdata_next[17] = ip_4_p_145_qs; + reg_rdata_next[18] = ip_4_p_146_qs; + reg_rdata_next[19] = ip_4_p_147_qs; + reg_rdata_next[20] = ip_4_p_148_qs; + reg_rdata_next[21] = ip_4_p_149_qs; + reg_rdata_next[22] = ip_4_p_150_qs; + reg_rdata_next[23] = ip_4_p_151_qs; + reg_rdata_next[24] = ip_4_p_152_qs; + reg_rdata_next[25] = ip_4_p_153_qs; + reg_rdata_next[26] = ip_4_p_154_qs; + reg_rdata_next[27] = ip_4_p_155_qs; + reg_rdata_next[28] = ip_4_p_156_qs; + reg_rdata_next[29] = ip_4_p_157_qs; + reg_rdata_next[30] = ip_4_p_158_qs; + reg_rdata_next[31] = ip_4_p_159_qs; + end + + addr_hit[165]: begin + reg_rdata_next[0] = ie0_0_e_0_qs; + reg_rdata_next[1] = ie0_0_e_1_qs; + reg_rdata_next[2] = ie0_0_e_2_qs; + reg_rdata_next[3] = ie0_0_e_3_qs; + reg_rdata_next[4] = ie0_0_e_4_qs; + reg_rdata_next[5] = ie0_0_e_5_qs; + reg_rdata_next[6] = ie0_0_e_6_qs; + reg_rdata_next[7] = ie0_0_e_7_qs; + reg_rdata_next[8] = ie0_0_e_8_qs; + reg_rdata_next[9] = ie0_0_e_9_qs; + reg_rdata_next[10] = ie0_0_e_10_qs; + reg_rdata_next[11] = ie0_0_e_11_qs; + reg_rdata_next[12] = ie0_0_e_12_qs; + reg_rdata_next[13] = ie0_0_e_13_qs; + reg_rdata_next[14] = ie0_0_e_14_qs; + reg_rdata_next[15] = ie0_0_e_15_qs; + reg_rdata_next[16] = ie0_0_e_16_qs; + reg_rdata_next[17] = ie0_0_e_17_qs; + reg_rdata_next[18] = ie0_0_e_18_qs; + reg_rdata_next[19] = ie0_0_e_19_qs; + reg_rdata_next[20] = ie0_0_e_20_qs; + reg_rdata_next[21] = ie0_0_e_21_qs; + reg_rdata_next[22] = ie0_0_e_22_qs; + reg_rdata_next[23] = ie0_0_e_23_qs; + reg_rdata_next[24] = ie0_0_e_24_qs; + reg_rdata_next[25] = ie0_0_e_25_qs; + reg_rdata_next[26] = ie0_0_e_26_qs; + reg_rdata_next[27] = ie0_0_e_27_qs; + reg_rdata_next[28] = ie0_0_e_28_qs; + reg_rdata_next[29] = ie0_0_e_29_qs; + reg_rdata_next[30] = ie0_0_e_30_qs; + reg_rdata_next[31] = ie0_0_e_31_qs; + end + + addr_hit[166]: begin + reg_rdata_next[0] = ie0_1_e_32_qs; + reg_rdata_next[1] = ie0_1_e_33_qs; + reg_rdata_next[2] = ie0_1_e_34_qs; + reg_rdata_next[3] = ie0_1_e_35_qs; + reg_rdata_next[4] = ie0_1_e_36_qs; + reg_rdata_next[5] = ie0_1_e_37_qs; + reg_rdata_next[6] = ie0_1_e_38_qs; + reg_rdata_next[7] = ie0_1_e_39_qs; + reg_rdata_next[8] = ie0_1_e_40_qs; + reg_rdata_next[9] = ie0_1_e_41_qs; + reg_rdata_next[10] = ie0_1_e_42_qs; + reg_rdata_next[11] = ie0_1_e_43_qs; + reg_rdata_next[12] = ie0_1_e_44_qs; + reg_rdata_next[13] = ie0_1_e_45_qs; + reg_rdata_next[14] = ie0_1_e_46_qs; + reg_rdata_next[15] = ie0_1_e_47_qs; + reg_rdata_next[16] = ie0_1_e_48_qs; + reg_rdata_next[17] = ie0_1_e_49_qs; + reg_rdata_next[18] = ie0_1_e_50_qs; + reg_rdata_next[19] = ie0_1_e_51_qs; + reg_rdata_next[20] = ie0_1_e_52_qs; + reg_rdata_next[21] = ie0_1_e_53_qs; + reg_rdata_next[22] = ie0_1_e_54_qs; + reg_rdata_next[23] = ie0_1_e_55_qs; + reg_rdata_next[24] = ie0_1_e_56_qs; + reg_rdata_next[25] = ie0_1_e_57_qs; + reg_rdata_next[26] = ie0_1_e_58_qs; + reg_rdata_next[27] = ie0_1_e_59_qs; + reg_rdata_next[28] = ie0_1_e_60_qs; + reg_rdata_next[29] = ie0_1_e_61_qs; + reg_rdata_next[30] = ie0_1_e_62_qs; + reg_rdata_next[31] = ie0_1_e_63_qs; + end + + addr_hit[167]: begin + reg_rdata_next[0] = ie0_2_e_64_qs; + reg_rdata_next[1] = ie0_2_e_65_qs; + reg_rdata_next[2] = ie0_2_e_66_qs; + reg_rdata_next[3] = ie0_2_e_67_qs; + reg_rdata_next[4] = ie0_2_e_68_qs; + reg_rdata_next[5] = ie0_2_e_69_qs; + reg_rdata_next[6] = ie0_2_e_70_qs; + reg_rdata_next[7] = ie0_2_e_71_qs; + reg_rdata_next[8] = ie0_2_e_72_qs; + reg_rdata_next[9] = ie0_2_e_73_qs; + reg_rdata_next[10] = ie0_2_e_74_qs; + reg_rdata_next[11] = ie0_2_e_75_qs; + reg_rdata_next[12] = ie0_2_e_76_qs; + reg_rdata_next[13] = ie0_2_e_77_qs; + reg_rdata_next[14] = ie0_2_e_78_qs; + reg_rdata_next[15] = ie0_2_e_79_qs; + reg_rdata_next[16] = ie0_2_e_80_qs; + reg_rdata_next[17] = ie0_2_e_81_qs; + reg_rdata_next[18] = ie0_2_e_82_qs; + reg_rdata_next[19] = ie0_2_e_83_qs; + reg_rdata_next[20] = ie0_2_e_84_qs; + reg_rdata_next[21] = ie0_2_e_85_qs; + reg_rdata_next[22] = ie0_2_e_86_qs; + reg_rdata_next[23] = ie0_2_e_87_qs; + reg_rdata_next[24] = ie0_2_e_88_qs; + reg_rdata_next[25] = ie0_2_e_89_qs; + reg_rdata_next[26] = ie0_2_e_90_qs; + reg_rdata_next[27] = ie0_2_e_91_qs; + reg_rdata_next[28] = ie0_2_e_92_qs; + reg_rdata_next[29] = ie0_2_e_93_qs; + reg_rdata_next[30] = ie0_2_e_94_qs; + reg_rdata_next[31] = ie0_2_e_95_qs; + end + + addr_hit[168]: begin + reg_rdata_next[0] = ie0_3_e_96_qs; + reg_rdata_next[1] = ie0_3_e_97_qs; + reg_rdata_next[2] = ie0_3_e_98_qs; + reg_rdata_next[3] = ie0_3_e_99_qs; + reg_rdata_next[4] = ie0_3_e_100_qs; + reg_rdata_next[5] = ie0_3_e_101_qs; + reg_rdata_next[6] = ie0_3_e_102_qs; + reg_rdata_next[7] = ie0_3_e_103_qs; + reg_rdata_next[8] = ie0_3_e_104_qs; + reg_rdata_next[9] = ie0_3_e_105_qs; + reg_rdata_next[10] = ie0_3_e_106_qs; + reg_rdata_next[11] = ie0_3_e_107_qs; + reg_rdata_next[12] = ie0_3_e_108_qs; + reg_rdata_next[13] = ie0_3_e_109_qs; + reg_rdata_next[14] = ie0_3_e_110_qs; + reg_rdata_next[15] = ie0_3_e_111_qs; + reg_rdata_next[16] = ie0_3_e_112_qs; + reg_rdata_next[17] = ie0_3_e_113_qs; + reg_rdata_next[18] = ie0_3_e_114_qs; + reg_rdata_next[19] = ie0_3_e_115_qs; + reg_rdata_next[20] = ie0_3_e_116_qs; + reg_rdata_next[21] = ie0_3_e_117_qs; + reg_rdata_next[22] = ie0_3_e_118_qs; + reg_rdata_next[23] = ie0_3_e_119_qs; + reg_rdata_next[24] = ie0_3_e_120_qs; + reg_rdata_next[25] = ie0_3_e_121_qs; + reg_rdata_next[26] = ie0_3_e_122_qs; + reg_rdata_next[27] = ie0_3_e_123_qs; + reg_rdata_next[28] = ie0_3_e_124_qs; + reg_rdata_next[29] = ie0_3_e_125_qs; + reg_rdata_next[30] = ie0_3_e_126_qs; + reg_rdata_next[31] = ie0_3_e_127_qs; + end + + addr_hit[169]: begin + reg_rdata_next[0] = ie0_4_e_128_qs; + reg_rdata_next[1] = ie0_4_e_129_qs; + reg_rdata_next[2] = ie0_4_e_130_qs; + reg_rdata_next[3] = ie0_4_e_131_qs; + reg_rdata_next[4] = ie0_4_e_132_qs; + reg_rdata_next[5] = ie0_4_e_133_qs; + reg_rdata_next[6] = ie0_4_e_134_qs; + reg_rdata_next[7] = ie0_4_e_135_qs; + reg_rdata_next[8] = ie0_4_e_136_qs; + reg_rdata_next[9] = ie0_4_e_137_qs; + reg_rdata_next[10] = ie0_4_e_138_qs; + reg_rdata_next[11] = ie0_4_e_139_qs; + reg_rdata_next[12] = ie0_4_e_140_qs; + reg_rdata_next[13] = ie0_4_e_141_qs; + reg_rdata_next[14] = ie0_4_e_142_qs; + reg_rdata_next[15] = ie0_4_e_143_qs; + reg_rdata_next[16] = ie0_4_e_144_qs; + reg_rdata_next[17] = ie0_4_e_145_qs; + reg_rdata_next[18] = ie0_4_e_146_qs; + reg_rdata_next[19] = ie0_4_e_147_qs; + reg_rdata_next[20] = ie0_4_e_148_qs; + reg_rdata_next[21] = ie0_4_e_149_qs; + reg_rdata_next[22] = ie0_4_e_150_qs; + reg_rdata_next[23] = ie0_4_e_151_qs; + reg_rdata_next[24] = ie0_4_e_152_qs; + reg_rdata_next[25] = ie0_4_e_153_qs; + reg_rdata_next[26] = ie0_4_e_154_qs; + reg_rdata_next[27] = ie0_4_e_155_qs; + reg_rdata_next[28] = ie0_4_e_156_qs; + reg_rdata_next[29] = ie0_4_e_157_qs; + reg_rdata_next[30] = ie0_4_e_158_qs; + reg_rdata_next[31] = ie0_4_e_159_qs; + end + + addr_hit[170]: begin + reg_rdata_next[1:0] = threshold0_qs; + end + + addr_hit[171]: begin + reg_rdata_next[7:0] = cc0_qs; + end + + addr_hit[172]: begin + reg_rdata_next[0] = msip0_qs; + end + + addr_hit[173]: begin + reg_rdata_next[0] = '0; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_target.sv b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_target.sv new file mode 100644 index 0000000000000..301dff3e99f8a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic_target.sv @@ -0,0 +1,74 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// RISC-V Platform-Level Interrupt Generator for Target +// +// This module basically doing IE & IP based on priority and threshold_i. +// Keep in mind that increasing MAX_PRIO affects logic size a lot. +// +// The module implements a binary tree to find the maximal entry. the solution +// has O(N) area and O(log(N)) delay complexity, and thus scales well with +// many input sources. +// + +`include "prim_assert.sv" + +module rv_plic_target #( + parameter int N_SOURCE = 32, + parameter int MAX_PRIO = 7, + + // Local param (Do not change this through parameter + localparam int SrcWidth = $clog2(N_SOURCE), // derived parameter + localparam int PrioWidth = $clog2(MAX_PRIO+1) // derived parameter +) ( + input clk_i, + input rst_ni, + + input [N_SOURCE-1:0] ip_i, + input [N_SOURCE-1:0] ie_i, + + input [N_SOURCE-1:0][PrioWidth-1:0] prio_i, + input [PrioWidth-1:0] threshold_i, + + output logic irq_o, + output logic [SrcWidth-1:0] irq_id_o +); + + // Find maximum value and index using a binary tree implementation. + logic max_valid; + logic [PrioWidth-1:0] max_value; + logic [SrcWidth-1:0] max_idx; + prim_max_tree #( + .NumSrc(N_SOURCE), + .Width(PrioWidth) + ) u_prim_max_tree ( + .clk_i, + .rst_ni, + .values_i(prio_i), + .valid_i(ip_i & ie_i), + .max_value_o(max_value), + .max_idx_o(max_idx), + .max_valid_o(max_valid) + ); + + logic irq_d, irq_q; + logic [SrcWidth-1:0] irq_id_d, irq_id_q; + + assign irq_d = (max_value > threshold_i) ? max_valid : 1'b0; + assign irq_id_d = (max_valid) ? max_idx : '0; + + always_ff @(posedge clk_i or negedge rst_ni) begin : gen_regs + if (!rst_ni) begin + irq_q <= 1'b0; + irq_id_q <= '0; + end else begin + irq_q <= irq_d; + irq_id_q <= irq_id_d; + end + end + + assign irq_o = irq_q; + assign irq_id_o = irq_id_q; + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/rv_plic.core b/hw/top_darjeeling/ip_autogen/rv_plic/rv_plic.core new file mode 100644 index 0000000000000..ea68a50321017 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/rv_plic.core @@ -0,0 +1,40 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_rv_plic +description: "RISC-V Platform Interrupt Controller (PLIC)" + +filesets: + files_rtl: + depend: + - lowrisc:ip:rv_plic_component + - lowrisc:ip:tlul + - lowrisc:prim:subreg + files: + - rtl/rv_plic_reg_pkg.sv + - rtl/rv_plic_reg_top.sv + - rtl/rv_plic.sv + file_type: systemVerilogSource + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: rv_plic + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling/ip_autogen/rv_plic/rv_plic_component.core b/hw/top_darjeeling/ip_autogen/rv_plic/rv_plic_component.core new file mode 100644 index 0000000000000..73a4488a2d439 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/rv_plic/rv_plic_component.core @@ -0,0 +1,51 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:ip:rv_plic_component:0.1" +description: "RISC-V Platform Interrupt Controller (PLIC)" + +filesets: + files_rtl: + depend: + - lowrisc:prim:assert + - lowrisc:prim:alert + - lowrisc:prim:max_tree + - lowrisc:prim:flop_2sync + - lowrisc:prim:reg_we_check + files: + - rtl/rv_plic_gateway.sv + - rtl/rv_plic_target.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/rv_plic.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/rv_plic.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +targets: + default: + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl diff --git a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv new file mode 100644 index 0000000000000..c98d718cf7d09 --- /dev/null +++ b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv @@ -0,0 +1,1690 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \ +// -o hw/top_darjeeling/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + + +module chip_darjeeling_asic #( + parameter bit SecRomCtrl0DisableScrambling = 1'b0, + parameter bit SecRomCtrl1DisableScrambling = 1'b0 +) ( + // Dedicated Pads + inout POR_N, // Manual Pad + inout JTAG_TCK, // Manual Pad + inout JTAG_TMS, // Manual Pad + inout JTAG_TDI, // Manual Pad + inout JTAG_TDO, // Manual Pad + inout JTAG_TRST_N, // Manual Pad + inout OTP_EXT_VOLT, // Manual Pad + inout SPI_HOST_D0, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_D1, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_D2, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_D3, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_CLK, // Dedicated Pad for spi_host0_sck + inout SPI_HOST_CS_L, // Dedicated Pad for spi_host0_csb + inout SPI_DEV_D0, // Dedicated Pad for spi_device_sd + inout SPI_DEV_D1, // Dedicated Pad for spi_device_sd + inout SPI_DEV_D2, // Dedicated Pad for spi_device_sd + inout SPI_DEV_D3, // Dedicated Pad for spi_device_sd + inout SPI_DEV_CLK, // Dedicated Pad for spi_device_sck + inout SPI_DEV_CS_L, // Dedicated Pad for spi_device_csb + inout SPI_DEV_TPM_CS_L, // Dedicated Pad for spi_device_tpm_csb + inout UART_RX, // Dedicated Pad for uart0_rx + inout UART_TX, // Dedicated Pad for uart0_tx + inout I2C_SCL, // Dedicated Pad for i2c0_scl + inout I2C_SDA, // Dedicated Pad for i2c0_sda + inout GPIO0, // Dedicated Pad for gpio_gpio + inout GPIO1, // Dedicated Pad for gpio_gpio + inout GPIO2, // Dedicated Pad for gpio_gpio + inout GPIO3, // Dedicated Pad for gpio_gpio + inout GPIO4, // Dedicated Pad for gpio_gpio + inout GPIO5, // Dedicated Pad for gpio_gpio + inout GPIO6, // Dedicated Pad for gpio_gpio + inout GPIO7, // Dedicated Pad for gpio_gpio + inout GPIO8, // Dedicated Pad for gpio_gpio + inout GPIO9, // Dedicated Pad for gpio_gpio + inout GPIO10, // Dedicated Pad for gpio_gpio + inout GPIO11, // Dedicated Pad for gpio_gpio + inout GPIO12, // Dedicated Pad for gpio_gpio + inout GPIO13, // Dedicated Pad for gpio_gpio + inout GPIO14, // Dedicated Pad for gpio_gpio + inout GPIO15, // Dedicated Pad for gpio_gpio + inout GPIO16, // Dedicated Pad for gpio_gpio + inout GPIO17, // Dedicated Pad for gpio_gpio + inout GPIO18, // Dedicated Pad for gpio_gpio + inout GPIO19, // Dedicated Pad for gpio_gpio + inout GPIO20, // Dedicated Pad for gpio_gpio + inout GPIO21, // Dedicated Pad for gpio_gpio + inout GPIO22, // Dedicated Pad for gpio_gpio + inout GPIO23, // Dedicated Pad for gpio_gpio + inout GPIO24, // Dedicated Pad for gpio_gpio + inout GPIO25, // Dedicated Pad for gpio_gpio + inout GPIO26, // Dedicated Pad for gpio_gpio + inout GPIO27, // Dedicated Pad for gpio_gpio + inout GPIO28, // Dedicated Pad for gpio_gpio + inout GPIO29, // Dedicated Pad for gpio_gpio + inout GPIO30, // Dedicated Pad for gpio_gpio + inout GPIO31, // Dedicated Pad for gpio_gpio + inout SOC_GPI0, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI1, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI2, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI3, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI4, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI5, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI6, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI7, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI8, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI9, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI10, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI11, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPO0, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO1, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO2, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO3, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO4, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO5, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO6, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO7, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO8, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO9, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO10, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO11, // Dedicated Pad for soc_proxy_soc_gpo + + // Muxed Pads + inout MIO0, // MIO Pad 0 + inout MIO1, // MIO Pad 1 + inout MIO2, // MIO Pad 2 + inout MIO3, // MIO Pad 3 + inout MIO4, // MIO Pad 4 + inout MIO5, // MIO Pad 5 + inout MIO6, // MIO Pad 6 + inout MIO7, // MIO Pad 7 + inout MIO8, // MIO Pad 8 + inout MIO9, // MIO Pad 9 + inout MIO10, // MIO Pad 10 + inout MIO11 // MIO Pad 11 +); + + import top_darjeeling_pkg::*; + import prim_pad_wrapper_pkg::*; + + //////////////////////////// + // Special Signal Indices // + //////////////////////////// + + localparam int Tap0PadIdx = 0; + localparam int Tap1PadIdx = 1; + localparam int Dft0PadIdx = 2; + localparam int Dft1PadIdx = 3; + localparam int TckPadIdx = 4; + localparam int TmsPadIdx = 5; + localparam int TrstNPadIdx = 6; + localparam int TdiPadIdx = 7; + localparam int TdoPadIdx = 8; + + // DFT and Debug signal positions in the pinout. + localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ + tck_idx: TckPadIdx, + tms_idx: TmsPadIdx, + trst_idx: TrstNPadIdx, + tdi_idx: TdiPadIdx, + tdo_idx: TdoPadIdx, + tap_strap0_idx: Tap0PadIdx, + tap_strap1_idx: Tap1PadIdx, + dft_strap0_idx: Dft0PadIdx, + dft_strap1_idx: Dft1PadIdx, + // TODO: check whether there is a better way to pass these USB-specific params + // The use of these indexes is gated behind a parameter, but to synthesize they + // need to exist even if the code-path is never used (pinmux.sv:UsbWkupModuleEn). + // Hence, set to zero. + usb_dp_idx: 0, + usb_dn_idx: 0, + usb_sense_idx: 0, + // Pad types for attribute WARL behavior + dio_pad_type: { + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO uart0_tx + BidirStd, // DIO spi_host0_csb + BidirStd, // DIO spi_host0_sck + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO uart0_rx + InputStd, // DIO spi_device_tpm_csb + InputStd, // DIO spi_device_csb + InputStd, // DIO spi_device_sck + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO i2c0_sda + BidirStd, // DIO i2c0_scl + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd // DIO spi_host0_sd + }, + mio_pad_type: { + BidirStd, // MIO Pad 11 + BidirStd, // MIO Pad 10 + BidirStd, // MIO Pad 9 + BidirStd, // MIO Pad 8 + BidirStd, // MIO Pad 7 + BidirStd, // MIO Pad 6 + BidirStd, // MIO Pad 5 + BidirStd, // MIO Pad 4 + BidirStd, // MIO Pad 3 + BidirStd, // MIO Pad 2 + BidirStd, // MIO Pad 1 + BidirStd // MIO Pad 0 + } + }; + + //////////////////////// + // Signal definitions // + //////////////////////// + + + pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr; + pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_out; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_raw; + logic [80-1:0] dio_in_raw; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_out; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_in; + + logic unused_mio_in_raw; + logic unused_dio_in_raw; + assign unused_mio_in_raw = ^mio_in_raw; + assign unused_dio_in_raw = ^dio_in_raw; + + // Manual pads + logic manual_in_por_n, manual_out_por_n, manual_oe_por_n; + logic manual_in_jtag_tck, manual_out_jtag_tck, manual_oe_jtag_tck; + logic manual_in_jtag_tms, manual_out_jtag_tms, manual_oe_jtag_tms; + logic manual_in_jtag_tdi, manual_out_jtag_tdi, manual_oe_jtag_tdi; + logic manual_in_jtag_tdo, manual_out_jtag_tdo, manual_oe_jtag_tdo; + logic manual_in_jtag_trst_n, manual_out_jtag_trst_n, manual_oe_jtag_trst_n; + logic manual_in_otp_ext_volt, manual_out_otp_ext_volt, manual_oe_otp_ext_volt; + + pad_attr_t manual_attr_por_n; + pad_attr_t manual_attr_jtag_tck; + pad_attr_t manual_attr_jtag_tms; + pad_attr_t manual_attr_jtag_tdi; + pad_attr_t manual_attr_jtag_tdo; + pad_attr_t manual_attr_jtag_trst_n; + pad_attr_t manual_attr_otp_ext_volt; + + + ////////////////////// + // Padring Instance // + ////////////////////// + + ast_pkg::ast_clks_t ast_base_clks; + + // AST signals needed in padring + logic scan_rst_n; + prim_mubi_pkg::mubi4_t scanmode; + + padring #( + // Padring specific counts may differ from pinmux config due + // to custom, stubbed or added pads. + .NDioPads(80), + .NMioPads(12), + .PhysicalPads(1), + .NIoBanks(int'(IoBankCount)), + .DioScanRole ({ + scan_role_pkg::DioPadSocGpo11ScanRole, + scan_role_pkg::DioPadSocGpo10ScanRole, + scan_role_pkg::DioPadSocGpo9ScanRole, + scan_role_pkg::DioPadSocGpo8ScanRole, + scan_role_pkg::DioPadSocGpo7ScanRole, + scan_role_pkg::DioPadSocGpo6ScanRole, + scan_role_pkg::DioPadSocGpo5ScanRole, + scan_role_pkg::DioPadSocGpo4ScanRole, + scan_role_pkg::DioPadSocGpo3ScanRole, + scan_role_pkg::DioPadSocGpo2ScanRole, + scan_role_pkg::DioPadSocGpo1ScanRole, + scan_role_pkg::DioPadSocGpo0ScanRole, + scan_role_pkg::DioPadSocGpi11ScanRole, + scan_role_pkg::DioPadSocGpi10ScanRole, + scan_role_pkg::DioPadSocGpi9ScanRole, + scan_role_pkg::DioPadSocGpi8ScanRole, + scan_role_pkg::DioPadSocGpi7ScanRole, + scan_role_pkg::DioPadSocGpi6ScanRole, + scan_role_pkg::DioPadSocGpi5ScanRole, + scan_role_pkg::DioPadSocGpi4ScanRole, + scan_role_pkg::DioPadSocGpi3ScanRole, + scan_role_pkg::DioPadSocGpi2ScanRole, + scan_role_pkg::DioPadSocGpi1ScanRole, + scan_role_pkg::DioPadSocGpi0ScanRole, + scan_role_pkg::DioPadGpio31ScanRole, + scan_role_pkg::DioPadGpio30ScanRole, + scan_role_pkg::DioPadGpio29ScanRole, + scan_role_pkg::DioPadGpio28ScanRole, + scan_role_pkg::DioPadGpio27ScanRole, + scan_role_pkg::DioPadGpio26ScanRole, + scan_role_pkg::DioPadGpio25ScanRole, + scan_role_pkg::DioPadGpio24ScanRole, + scan_role_pkg::DioPadGpio23ScanRole, + scan_role_pkg::DioPadGpio22ScanRole, + scan_role_pkg::DioPadGpio21ScanRole, + scan_role_pkg::DioPadGpio20ScanRole, + scan_role_pkg::DioPadGpio19ScanRole, + scan_role_pkg::DioPadGpio18ScanRole, + scan_role_pkg::DioPadGpio17ScanRole, + scan_role_pkg::DioPadGpio16ScanRole, + scan_role_pkg::DioPadGpio15ScanRole, + scan_role_pkg::DioPadGpio14ScanRole, + scan_role_pkg::DioPadGpio13ScanRole, + scan_role_pkg::DioPadGpio12ScanRole, + scan_role_pkg::DioPadGpio11ScanRole, + scan_role_pkg::DioPadGpio10ScanRole, + scan_role_pkg::DioPadGpio9ScanRole, + scan_role_pkg::DioPadGpio8ScanRole, + scan_role_pkg::DioPadGpio7ScanRole, + scan_role_pkg::DioPadGpio6ScanRole, + scan_role_pkg::DioPadGpio5ScanRole, + scan_role_pkg::DioPadGpio4ScanRole, + scan_role_pkg::DioPadGpio3ScanRole, + scan_role_pkg::DioPadGpio2ScanRole, + scan_role_pkg::DioPadGpio1ScanRole, + scan_role_pkg::DioPadGpio0ScanRole, + scan_role_pkg::DioPadI2cSdaScanRole, + scan_role_pkg::DioPadI2cSclScanRole, + scan_role_pkg::DioPadUartTxScanRole, + scan_role_pkg::DioPadUartRxScanRole, + scan_role_pkg::DioPadSpiDevTpmCsLScanRole, + scan_role_pkg::DioPadSpiDevCsLScanRole, + scan_role_pkg::DioPadSpiDevClkScanRole, + scan_role_pkg::DioPadSpiDevD3ScanRole, + scan_role_pkg::DioPadSpiDevD2ScanRole, + scan_role_pkg::DioPadSpiDevD1ScanRole, + scan_role_pkg::DioPadSpiDevD0ScanRole, + scan_role_pkg::DioPadSpiHostCsLScanRole, + scan_role_pkg::DioPadSpiHostClkScanRole, + scan_role_pkg::DioPadSpiHostD3ScanRole, + scan_role_pkg::DioPadSpiHostD2ScanRole, + scan_role_pkg::DioPadSpiHostD1ScanRole, + scan_role_pkg::DioPadSpiHostD0ScanRole, + scan_role_pkg::DioPadOtpExtVoltScanRole, + scan_role_pkg::DioPadJtagTrstNScanRole, + scan_role_pkg::DioPadJtagTdoScanRole, + scan_role_pkg::DioPadJtagTdiScanRole, + scan_role_pkg::DioPadJtagTmsScanRole, + scan_role_pkg::DioPadJtagTckScanRole, + scan_role_pkg::DioPadPorNScanRole + }), + .MioScanRole ({ + scan_role_pkg::MioPadMio11ScanRole, + scan_role_pkg::MioPadMio10ScanRole, + scan_role_pkg::MioPadMio9ScanRole, + scan_role_pkg::MioPadMio8ScanRole, + scan_role_pkg::MioPadMio7ScanRole, + scan_role_pkg::MioPadMio6ScanRole, + scan_role_pkg::MioPadMio5ScanRole, + scan_role_pkg::MioPadMio4ScanRole, + scan_role_pkg::MioPadMio3ScanRole, + scan_role_pkg::MioPadMio2ScanRole, + scan_role_pkg::MioPadMio1ScanRole, + scan_role_pkg::MioPadMio0ScanRole + }), + .DioPadBank ({ + IoBankVio, // SOC_GPO11 + IoBankVio, // SOC_GPO10 + IoBankVio, // SOC_GPO9 + IoBankVio, // SOC_GPO8 + IoBankVio, // SOC_GPO7 + IoBankVio, // SOC_GPO6 + IoBankVio, // SOC_GPO5 + IoBankVio, // SOC_GPO4 + IoBankVio, // SOC_GPO3 + IoBankVio, // SOC_GPO2 + IoBankVio, // SOC_GPO1 + IoBankVio, // SOC_GPO0 + IoBankVio, // SOC_GPI11 + IoBankVio, // SOC_GPI10 + IoBankVio, // SOC_GPI9 + IoBankVio, // SOC_GPI8 + IoBankVio, // SOC_GPI7 + IoBankVio, // SOC_GPI6 + IoBankVio, // SOC_GPI5 + IoBankVio, // SOC_GPI4 + IoBankVio, // SOC_GPI3 + IoBankVio, // SOC_GPI2 + IoBankVio, // SOC_GPI1 + IoBankVio, // SOC_GPI0 + IoBankVio, // GPIO31 + IoBankVio, // GPIO30 + IoBankVio, // GPIO29 + IoBankVio, // GPIO28 + IoBankVio, // GPIO27 + IoBankVio, // GPIO26 + IoBankVio, // GPIO25 + IoBankVio, // GPIO24 + IoBankVio, // GPIO23 + IoBankVio, // GPIO22 + IoBankVio, // GPIO21 + IoBankVio, // GPIO20 + IoBankVio, // GPIO19 + IoBankVio, // GPIO18 + IoBankVio, // GPIO17 + IoBankVio, // GPIO16 + IoBankVio, // GPIO15 + IoBankVio, // GPIO14 + IoBankVio, // GPIO13 + IoBankVio, // GPIO12 + IoBankVio, // GPIO11 + IoBankVio, // GPIO10 + IoBankVio, // GPIO9 + IoBankVio, // GPIO8 + IoBankVio, // GPIO7 + IoBankVio, // GPIO6 + IoBankVio, // GPIO5 + IoBankVio, // GPIO4 + IoBankVio, // GPIO3 + IoBankVio, // GPIO2 + IoBankVio, // GPIO1 + IoBankVio, // GPIO0 + IoBankVio, // I2C_SDA + IoBankVio, // I2C_SCL + IoBankVio, // UART_TX + IoBankVio, // UART_RX + IoBankVio, // SPI_DEV_TPM_CS_L + IoBankVio, // SPI_DEV_CS_L + IoBankVio, // SPI_DEV_CLK + IoBankVio, // SPI_DEV_D3 + IoBankVio, // SPI_DEV_D2 + IoBankVio, // SPI_DEV_D1 + IoBankVio, // SPI_DEV_D0 + IoBankVio, // SPI_HOST_CS_L + IoBankVio, // SPI_HOST_CLK + IoBankVio, // SPI_HOST_D3 + IoBankVio, // SPI_HOST_D2 + IoBankVio, // SPI_HOST_D1 + IoBankVio, // SPI_HOST_D0 + IoBankVio, // OTP_EXT_VOLT + IoBankVio, // JTAG_TRST_N + IoBankVio, // JTAG_TDO + IoBankVio, // JTAG_TDI + IoBankVio, // JTAG_TMS + IoBankVio, // JTAG_TCK + IoBankVio // POR_N + }), + .MioPadBank ({ + IoBankVio, // MIO11 + IoBankVio, // MIO10 + IoBankVio, // MIO9 + IoBankVio, // MIO8 + IoBankVio, // MIO7 + IoBankVio, // MIO6 + IoBankVio, // MIO5 + IoBankVio, // MIO4 + IoBankVio, // MIO3 + IoBankVio, // MIO2 + IoBankVio, // MIO1 + IoBankVio // MIO0 + }), + .DioPadType ({ + BidirStd, // SOC_GPO11 + BidirStd, // SOC_GPO10 + BidirStd, // SOC_GPO9 + BidirStd, // SOC_GPO8 + BidirStd, // SOC_GPO7 + BidirStd, // SOC_GPO6 + BidirStd, // SOC_GPO5 + BidirStd, // SOC_GPO4 + BidirStd, // SOC_GPO3 + BidirStd, // SOC_GPO2 + BidirStd, // SOC_GPO1 + BidirStd, // SOC_GPO0 + InputStd, // SOC_GPI11 + InputStd, // SOC_GPI10 + InputStd, // SOC_GPI9 + InputStd, // SOC_GPI8 + InputStd, // SOC_GPI7 + InputStd, // SOC_GPI6 + InputStd, // SOC_GPI5 + InputStd, // SOC_GPI4 + InputStd, // SOC_GPI3 + InputStd, // SOC_GPI2 + InputStd, // SOC_GPI1 + InputStd, // SOC_GPI0 + BidirStd, // GPIO31 + BidirStd, // GPIO30 + BidirStd, // GPIO29 + BidirStd, // GPIO28 + BidirStd, // GPIO27 + BidirStd, // GPIO26 + BidirStd, // GPIO25 + BidirStd, // GPIO24 + BidirStd, // GPIO23 + BidirStd, // GPIO22 + BidirStd, // GPIO21 + BidirStd, // GPIO20 + BidirStd, // GPIO19 + BidirStd, // GPIO18 + BidirStd, // GPIO17 + BidirStd, // GPIO16 + BidirStd, // GPIO15 + BidirStd, // GPIO14 + BidirStd, // GPIO13 + BidirStd, // GPIO12 + BidirStd, // GPIO11 + BidirStd, // GPIO10 + BidirStd, // GPIO9 + BidirStd, // GPIO8 + BidirStd, // GPIO7 + BidirStd, // GPIO6 + BidirStd, // GPIO5 + BidirStd, // GPIO4 + BidirStd, // GPIO3 + BidirStd, // GPIO2 + BidirStd, // GPIO1 + BidirStd, // GPIO0 + BidirStd, // I2C_SDA + BidirStd, // I2C_SCL + BidirStd, // UART_TX + InputStd, // UART_RX + InputStd, // SPI_DEV_TPM_CS_L + InputStd, // SPI_DEV_CS_L + InputStd, // SPI_DEV_CLK + BidirStd, // SPI_DEV_D3 + BidirStd, // SPI_DEV_D2 + BidirStd, // SPI_DEV_D1 + BidirStd, // SPI_DEV_D0 + BidirStd, // SPI_HOST_CS_L + BidirStd, // SPI_HOST_CLK + BidirStd, // SPI_HOST_D3 + BidirStd, // SPI_HOST_D2 + BidirStd, // SPI_HOST_D1 + BidirStd, // SPI_HOST_D0 + AnalogIn1, // OTP_EXT_VOLT + InputStd, // JTAG_TRST_N + BidirStd, // JTAG_TDO + InputStd, // JTAG_TDI + InputStd, // JTAG_TMS + InputStd, // JTAG_TCK + InputStd // POR_N + }), + .MioPadType ({ + BidirStd, // MIO11 + BidirStd, // MIO10 + BidirStd, // MIO9 + BidirStd, // MIO8 + BidirStd, // MIO7 + BidirStd, // MIO6 + BidirStd, // MIO5 + BidirStd, // MIO4 + BidirStd, // MIO3 + BidirStd, // MIO2 + BidirStd, // MIO1 + BidirStd // MIO0 + }) + ) u_padring ( + // This is only used for scan and DFT purposes + .clk_scan_i ( ast_base_clks.clk_sys ), + .scanmode_i ( scanmode ), + .dio_in_raw_o ( dio_in_raw ), + // Chip IOs + .dio_pad_io ({ + SOC_GPO11, + SOC_GPO10, + SOC_GPO9, + SOC_GPO8, + SOC_GPO7, + SOC_GPO6, + SOC_GPO5, + SOC_GPO4, + SOC_GPO3, + SOC_GPO2, + SOC_GPO1, + SOC_GPO0, + SOC_GPI11, + SOC_GPI10, + SOC_GPI9, + SOC_GPI8, + SOC_GPI7, + SOC_GPI6, + SOC_GPI5, + SOC_GPI4, + SOC_GPI3, + SOC_GPI2, + SOC_GPI1, + SOC_GPI0, + GPIO31, + GPIO30, + GPIO29, + GPIO28, + GPIO27, + GPIO26, + GPIO25, + GPIO24, + GPIO23, + GPIO22, + GPIO21, + GPIO20, + GPIO19, + GPIO18, + GPIO17, + GPIO16, + GPIO15, + GPIO14, + GPIO13, + GPIO12, + GPIO11, + GPIO10, + GPIO9, + GPIO8, + GPIO7, + GPIO6, + GPIO5, + GPIO4, + GPIO3, + GPIO2, + GPIO1, + GPIO0, + I2C_SDA, + I2C_SCL, + UART_TX, + UART_RX, + SPI_DEV_TPM_CS_L, + SPI_DEV_CS_L, + SPI_DEV_CLK, + SPI_DEV_D3, + SPI_DEV_D2, + SPI_DEV_D1, + SPI_DEV_D0, + SPI_HOST_CS_L, + SPI_HOST_CLK, + SPI_HOST_D3, + SPI_HOST_D2, + SPI_HOST_D1, + SPI_HOST_D0, + OTP_EXT_VOLT, + JTAG_TRST_N, + JTAG_TDO, + JTAG_TDI, + JTAG_TMS, + JTAG_TCK, + POR_N + }), + + .mio_pad_io ({ + MIO11, + MIO10, + MIO9, + MIO8, + MIO7, + MIO6, + MIO5, + MIO4, + MIO3, + MIO2, + MIO1, + MIO0 + }), + + // Core-facing + .dio_in_o ({ + dio_in[DioSocProxySocGpo11], + dio_in[DioSocProxySocGpo10], + dio_in[DioSocProxySocGpo9], + dio_in[DioSocProxySocGpo8], + dio_in[DioSocProxySocGpo7], + dio_in[DioSocProxySocGpo6], + dio_in[DioSocProxySocGpo5], + dio_in[DioSocProxySocGpo4], + dio_in[DioSocProxySocGpo3], + dio_in[DioSocProxySocGpo2], + dio_in[DioSocProxySocGpo1], + dio_in[DioSocProxySocGpo0], + dio_in[DioSocProxySocGpi11], + dio_in[DioSocProxySocGpi10], + dio_in[DioSocProxySocGpi9], + dio_in[DioSocProxySocGpi8], + dio_in[DioSocProxySocGpi7], + dio_in[DioSocProxySocGpi6], + dio_in[DioSocProxySocGpi5], + dio_in[DioSocProxySocGpi4], + dio_in[DioSocProxySocGpi3], + dio_in[DioSocProxySocGpi2], + dio_in[DioSocProxySocGpi1], + dio_in[DioSocProxySocGpi0], + dio_in[DioGpioGpio31], + dio_in[DioGpioGpio30], + dio_in[DioGpioGpio29], + dio_in[DioGpioGpio28], + dio_in[DioGpioGpio27], + dio_in[DioGpioGpio26], + dio_in[DioGpioGpio25], + dio_in[DioGpioGpio24], + dio_in[DioGpioGpio23], + dio_in[DioGpioGpio22], + dio_in[DioGpioGpio21], + dio_in[DioGpioGpio20], + dio_in[DioGpioGpio19], + dio_in[DioGpioGpio18], + dio_in[DioGpioGpio17], + dio_in[DioGpioGpio16], + dio_in[DioGpioGpio15], + dio_in[DioGpioGpio14], + dio_in[DioGpioGpio13], + dio_in[DioGpioGpio12], + dio_in[DioGpioGpio11], + dio_in[DioGpioGpio10], + dio_in[DioGpioGpio9], + dio_in[DioGpioGpio8], + dio_in[DioGpioGpio7], + dio_in[DioGpioGpio6], + dio_in[DioGpioGpio5], + dio_in[DioGpioGpio4], + dio_in[DioGpioGpio3], + dio_in[DioGpioGpio2], + dio_in[DioGpioGpio1], + dio_in[DioGpioGpio0], + dio_in[DioI2c0Sda], + dio_in[DioI2c0Scl], + dio_in[DioUart0Tx], + dio_in[DioUart0Rx], + dio_in[DioSpiDeviceTpmCsb], + dio_in[DioSpiDeviceCsb], + dio_in[DioSpiDeviceSck], + dio_in[DioSpiDeviceSd3], + dio_in[DioSpiDeviceSd2], + dio_in[DioSpiDeviceSd1], + dio_in[DioSpiDeviceSd0], + dio_in[DioSpiHost0Csb], + dio_in[DioSpiHost0Sck], + dio_in[DioSpiHost0Sd3], + dio_in[DioSpiHost0Sd2], + dio_in[DioSpiHost0Sd1], + dio_in[DioSpiHost0Sd0], + manual_in_otp_ext_volt, + manual_in_jtag_trst_n, + manual_in_jtag_tdo, + manual_in_jtag_tdi, + manual_in_jtag_tms, + manual_in_jtag_tck, + manual_in_por_n + }), + .dio_out_i ({ + dio_out[DioSocProxySocGpo11], + dio_out[DioSocProxySocGpo10], + dio_out[DioSocProxySocGpo9], + dio_out[DioSocProxySocGpo8], + dio_out[DioSocProxySocGpo7], + dio_out[DioSocProxySocGpo6], + dio_out[DioSocProxySocGpo5], + dio_out[DioSocProxySocGpo4], + dio_out[DioSocProxySocGpo3], + dio_out[DioSocProxySocGpo2], + dio_out[DioSocProxySocGpo1], + dio_out[DioSocProxySocGpo0], + dio_out[DioSocProxySocGpi11], + dio_out[DioSocProxySocGpi10], + dio_out[DioSocProxySocGpi9], + dio_out[DioSocProxySocGpi8], + dio_out[DioSocProxySocGpi7], + dio_out[DioSocProxySocGpi6], + dio_out[DioSocProxySocGpi5], + dio_out[DioSocProxySocGpi4], + dio_out[DioSocProxySocGpi3], + dio_out[DioSocProxySocGpi2], + dio_out[DioSocProxySocGpi1], + dio_out[DioSocProxySocGpi0], + dio_out[DioGpioGpio31], + dio_out[DioGpioGpio30], + dio_out[DioGpioGpio29], + dio_out[DioGpioGpio28], + dio_out[DioGpioGpio27], + dio_out[DioGpioGpio26], + dio_out[DioGpioGpio25], + dio_out[DioGpioGpio24], + dio_out[DioGpioGpio23], + dio_out[DioGpioGpio22], + dio_out[DioGpioGpio21], + dio_out[DioGpioGpio20], + dio_out[DioGpioGpio19], + dio_out[DioGpioGpio18], + dio_out[DioGpioGpio17], + dio_out[DioGpioGpio16], + dio_out[DioGpioGpio15], + dio_out[DioGpioGpio14], + dio_out[DioGpioGpio13], + dio_out[DioGpioGpio12], + dio_out[DioGpioGpio11], + dio_out[DioGpioGpio10], + dio_out[DioGpioGpio9], + dio_out[DioGpioGpio8], + dio_out[DioGpioGpio7], + dio_out[DioGpioGpio6], + dio_out[DioGpioGpio5], + dio_out[DioGpioGpio4], + dio_out[DioGpioGpio3], + dio_out[DioGpioGpio2], + dio_out[DioGpioGpio1], + dio_out[DioGpioGpio0], + dio_out[DioI2c0Sda], + dio_out[DioI2c0Scl], + dio_out[DioUart0Tx], + dio_out[DioUart0Rx], + dio_out[DioSpiDeviceTpmCsb], + dio_out[DioSpiDeviceCsb], + dio_out[DioSpiDeviceSck], + dio_out[DioSpiDeviceSd3], + dio_out[DioSpiDeviceSd2], + dio_out[DioSpiDeviceSd1], + dio_out[DioSpiDeviceSd0], + dio_out[DioSpiHost0Csb], + dio_out[DioSpiHost0Sck], + dio_out[DioSpiHost0Sd3], + dio_out[DioSpiHost0Sd2], + dio_out[DioSpiHost0Sd1], + dio_out[DioSpiHost0Sd0], + manual_out_otp_ext_volt, + manual_out_jtag_trst_n, + manual_out_jtag_tdo, + manual_out_jtag_tdi, + manual_out_jtag_tms, + manual_out_jtag_tck, + manual_out_por_n + }), + .dio_oe_i ({ + dio_oe[DioSocProxySocGpo11], + dio_oe[DioSocProxySocGpo10], + dio_oe[DioSocProxySocGpo9], + dio_oe[DioSocProxySocGpo8], + dio_oe[DioSocProxySocGpo7], + dio_oe[DioSocProxySocGpo6], + dio_oe[DioSocProxySocGpo5], + dio_oe[DioSocProxySocGpo4], + dio_oe[DioSocProxySocGpo3], + dio_oe[DioSocProxySocGpo2], + dio_oe[DioSocProxySocGpo1], + dio_oe[DioSocProxySocGpo0], + dio_oe[DioSocProxySocGpi11], + dio_oe[DioSocProxySocGpi10], + dio_oe[DioSocProxySocGpi9], + dio_oe[DioSocProxySocGpi8], + dio_oe[DioSocProxySocGpi7], + dio_oe[DioSocProxySocGpi6], + dio_oe[DioSocProxySocGpi5], + dio_oe[DioSocProxySocGpi4], + dio_oe[DioSocProxySocGpi3], + dio_oe[DioSocProxySocGpi2], + dio_oe[DioSocProxySocGpi1], + dio_oe[DioSocProxySocGpi0], + dio_oe[DioGpioGpio31], + dio_oe[DioGpioGpio30], + dio_oe[DioGpioGpio29], + dio_oe[DioGpioGpio28], + dio_oe[DioGpioGpio27], + dio_oe[DioGpioGpio26], + dio_oe[DioGpioGpio25], + dio_oe[DioGpioGpio24], + dio_oe[DioGpioGpio23], + dio_oe[DioGpioGpio22], + dio_oe[DioGpioGpio21], + dio_oe[DioGpioGpio20], + dio_oe[DioGpioGpio19], + dio_oe[DioGpioGpio18], + dio_oe[DioGpioGpio17], + dio_oe[DioGpioGpio16], + dio_oe[DioGpioGpio15], + dio_oe[DioGpioGpio14], + dio_oe[DioGpioGpio13], + dio_oe[DioGpioGpio12], + dio_oe[DioGpioGpio11], + dio_oe[DioGpioGpio10], + dio_oe[DioGpioGpio9], + dio_oe[DioGpioGpio8], + dio_oe[DioGpioGpio7], + dio_oe[DioGpioGpio6], + dio_oe[DioGpioGpio5], + dio_oe[DioGpioGpio4], + dio_oe[DioGpioGpio3], + dio_oe[DioGpioGpio2], + dio_oe[DioGpioGpio1], + dio_oe[DioGpioGpio0], + dio_oe[DioI2c0Sda], + dio_oe[DioI2c0Scl], + dio_oe[DioUart0Tx], + dio_oe[DioUart0Rx], + dio_oe[DioSpiDeviceTpmCsb], + dio_oe[DioSpiDeviceCsb], + dio_oe[DioSpiDeviceSck], + dio_oe[DioSpiDeviceSd3], + dio_oe[DioSpiDeviceSd2], + dio_oe[DioSpiDeviceSd1], + dio_oe[DioSpiDeviceSd0], + dio_oe[DioSpiHost0Csb], + dio_oe[DioSpiHost0Sck], + dio_oe[DioSpiHost0Sd3], + dio_oe[DioSpiHost0Sd2], + dio_oe[DioSpiHost0Sd1], + dio_oe[DioSpiHost0Sd0], + manual_oe_otp_ext_volt, + manual_oe_jtag_trst_n, + manual_oe_jtag_tdo, + manual_oe_jtag_tdi, + manual_oe_jtag_tms, + manual_oe_jtag_tck, + manual_oe_por_n + }), + .dio_attr_i ({ + dio_attr[DioSocProxySocGpo11], + dio_attr[DioSocProxySocGpo10], + dio_attr[DioSocProxySocGpo9], + dio_attr[DioSocProxySocGpo8], + dio_attr[DioSocProxySocGpo7], + dio_attr[DioSocProxySocGpo6], + dio_attr[DioSocProxySocGpo5], + dio_attr[DioSocProxySocGpo4], + dio_attr[DioSocProxySocGpo3], + dio_attr[DioSocProxySocGpo2], + dio_attr[DioSocProxySocGpo1], + dio_attr[DioSocProxySocGpo0], + dio_attr[DioSocProxySocGpi11], + dio_attr[DioSocProxySocGpi10], + dio_attr[DioSocProxySocGpi9], + dio_attr[DioSocProxySocGpi8], + dio_attr[DioSocProxySocGpi7], + dio_attr[DioSocProxySocGpi6], + dio_attr[DioSocProxySocGpi5], + dio_attr[DioSocProxySocGpi4], + dio_attr[DioSocProxySocGpi3], + dio_attr[DioSocProxySocGpi2], + dio_attr[DioSocProxySocGpi1], + dio_attr[DioSocProxySocGpi0], + dio_attr[DioGpioGpio31], + dio_attr[DioGpioGpio30], + dio_attr[DioGpioGpio29], + dio_attr[DioGpioGpio28], + dio_attr[DioGpioGpio27], + dio_attr[DioGpioGpio26], + dio_attr[DioGpioGpio25], + dio_attr[DioGpioGpio24], + dio_attr[DioGpioGpio23], + dio_attr[DioGpioGpio22], + dio_attr[DioGpioGpio21], + dio_attr[DioGpioGpio20], + dio_attr[DioGpioGpio19], + dio_attr[DioGpioGpio18], + dio_attr[DioGpioGpio17], + dio_attr[DioGpioGpio16], + dio_attr[DioGpioGpio15], + dio_attr[DioGpioGpio14], + dio_attr[DioGpioGpio13], + dio_attr[DioGpioGpio12], + dio_attr[DioGpioGpio11], + dio_attr[DioGpioGpio10], + dio_attr[DioGpioGpio9], + dio_attr[DioGpioGpio8], + dio_attr[DioGpioGpio7], + dio_attr[DioGpioGpio6], + dio_attr[DioGpioGpio5], + dio_attr[DioGpioGpio4], + dio_attr[DioGpioGpio3], + dio_attr[DioGpioGpio2], + dio_attr[DioGpioGpio1], + dio_attr[DioGpioGpio0], + dio_attr[DioI2c0Sda], + dio_attr[DioI2c0Scl], + dio_attr[DioUart0Tx], + dio_attr[DioUart0Rx], + dio_attr[DioSpiDeviceTpmCsb], + dio_attr[DioSpiDeviceCsb], + dio_attr[DioSpiDeviceSck], + dio_attr[DioSpiDeviceSd3], + dio_attr[DioSpiDeviceSd2], + dio_attr[DioSpiDeviceSd1], + dio_attr[DioSpiDeviceSd0], + dio_attr[DioSpiHost0Csb], + dio_attr[DioSpiHost0Sck], + dio_attr[DioSpiHost0Sd3], + dio_attr[DioSpiHost0Sd2], + dio_attr[DioSpiHost0Sd1], + dio_attr[DioSpiHost0Sd0], + manual_attr_otp_ext_volt, + manual_attr_jtag_trst_n, + manual_attr_jtag_tdo, + manual_attr_jtag_tdi, + manual_attr_jtag_tms, + manual_attr_jtag_tck, + manual_attr_por_n + }), + + .mio_in_o (mio_in[11:0]), + .mio_out_i (mio_out[11:0]), + .mio_oe_i (mio_oe[11:0]), + .mio_attr_i (mio_attr[11:0]), + .mio_in_raw_o (mio_in_raw[11:0]) + ); + + + + + + ////////////////////////////////// + // AST - Common for all targets // + ////////////////////////////////// + + // pwrmgr interface + pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; + pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; + + // assorted ast status + ast_pkg::ast_pwst_t ast_pwst; + + // TLUL interface + tlul_pkg::tl_h2d_t base_ast_bus; + tlul_pkg::tl_d2h_t ast_base_bus; + + // synchronization clocks / rests + clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks; + rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets; + + // external clock + logic ext_clk; + + // monitored clock + logic sck_monitor; + + // observe interface + logic [7:0] otp_obs; + ast_pkg::ast_obs_ctrl_t obs_ctrl; + + // otp power sequence + otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq; + otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h; + + // entropy source interface + // The entropy source pacakge definition should eventually be moved to es + entropy_src_pkg::entropy_src_hw_if_req_t entropy_src_hw_if_req; + entropy_src_pkg::entropy_src_hw_if_rsp_t entropy_src_hw_if_rsp; + + // entropy distribution network + edn_pkg::edn_req_t ast_edn_edn_req; + edn_pkg::edn_rsp_t ast_edn_edn_rsp; + + // alerts interface + ast_pkg::ast_alert_rsp_t ast_alert_rsp; + ast_pkg::ast_alert_req_t ast_alert_req; + + // clock bypass req/ack + prim_mubi_pkg::mubi4_t io_clk_byp_req; + prim_mubi_pkg::mubi4_t io_clk_byp_ack; + prim_mubi_pkg::mubi4_t all_clk_byp_req; + prim_mubi_pkg::mubi4_t all_clk_byp_ack; + prim_mubi_pkg::mubi4_t hi_speed_sel; + prim_mubi_pkg::mubi4_t div_step_down_req; + + // DFT connections + logic scan_en; + lc_ctrl_pkg::lc_tx_t lc_dft_en; + pinmux_pkg::dft_strap_test_req_t dft_strap_test; + + // Jitter enable + prim_mubi_pkg::mubi4_t jen; + + // reset domain connections + import rstmgr_pkg::PowerDomains; + import rstmgr_pkg::DomainAonSel; + import rstmgr_pkg::Domain0Sel; + + // Memory configuration connections + ast_pkg::spm_rm_t ast_ram_1p_cfg; + ast_pkg::spm_rm_t ast_rf_cfg; + ast_pkg::spm_rm_t ast_rom_cfg; + ast_pkg::dpm_rm_t ast_ram_2p_fcfg; + ast_pkg::dpm_rm_t ast_ram_2p_lcfg; + + // conversion from ast structure to memory centric structures + prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg; + assign ram_1p_cfg = '{ + ram_cfg: '{ + cfg_en: ast_ram_1p_cfg.marg_en, + cfg: ast_ram_1p_cfg.marg + }, + rf_cfg: '{ + cfg_en: ast_rf_cfg.marg_en, + cfg: ast_rf_cfg.marg + } + }; + + logic unused_usb_ram_2p_cfg; + assign unused_usb_ram_2p_cfg = ^{ast_ram_2p_fcfg.marg_en_a, + ast_ram_2p_fcfg.marg_a, + ast_ram_2p_fcfg.marg_en_b, + ast_ram_2p_fcfg.marg_b}; + + // this maps as follows: + // assign spi_ram_2p_cfg = {10'h000, ram_2p_cfg_i.a_ram_lcfg, ram_2p_cfg_i.b_ram_lcfg}; + prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg; + assign spi_ram_2p_cfg = '{ + a_ram_lcfg: '{ + cfg_en: ast_ram_2p_lcfg.marg_en_a, + cfg: ast_ram_2p_lcfg.marg_a + }, + b_ram_lcfg: '{ + cfg_en: ast_ram_2p_lcfg.marg_en_b, + cfg: ast_ram_2p_lcfg.marg_b + }, + default: '0 + }; + + prim_rom_pkg::rom_cfg_t rom_cfg; + assign rom_cfg = '{ + cfg_en: ast_rom_cfg.marg_en, + cfg: ast_rom_cfg.marg + }; + + + ////////////////////////////////// + // AST - Custom for targets // + ////////////////////////////////// + + + assign ast_base_pwr.main_pok = ast_pwst.main_pok; + + logic [rstmgr_pkg::PowerDomains-1:0] por_n; + assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok}; + + + // external clock comes in at a fixed position + assign ext_clk = mio_in_raw[MioPadMio11]; + + wire unused_t0, unused_t1; + assign unused_t0 = 1'b0; + assign unused_t1 = 1'b0; + + // AST does not use all clocks / resets forwarded to it + logic unused_slow_clk_en; + assign unused_slow_clk_en = base_ast_pwr.slow_clk_en; + + logic unused_pwr_clamp; + assign unused_pwr_clamp = base_ast_pwr.pwr_clamp; + + + prim_mubi_pkg::mubi4_t ast_init_done; + + ast #( + .EntropyStreams(ast_pkg::EntropyStreams), + .AdcChannels(ast_pkg::AdcChannels), + .AdcDataWidth(ast_pkg::AdcDataWidth), + .UsbCalibWidth(ast_pkg::UsbCalibWidth), + .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth), + .Pad2AstInWidth(ast_pkg::Pad2AstInWidth) + ) u_ast ( + // external POR + .por_ni ( manual_in_por_n ), + + // USB IO Pull-up Calibration Setting + .usb_io_pu_cal_o ( ), + + // adc + .adc_a0_ai ( '0 ), + .adc_a1_ai ( '0 ), + + // Direct short to PAD + .ast2pad_t0_ao ( unused_t0 ), + .ast2pad_t1_ao ( unused_t1 ), + // clocks and resets supplied for detection + .sns_clks_i ( clkmgr_aon_clocks ), + .sns_rsts_i ( rstmgr_aon_resets ), + .sns_spi_ext_clk_i ( sck_monitor ), + // tlul + .tl_i ( base_ast_bus ), + .tl_o ( ast_base_bus ), + // init done indication + .ast_init_done_o ( ast_init_done ), + // buffered clocks & resets + .clk_ast_tlul_i (clkmgr_aon_clocks.clk_io_div4_infra), + .clk_ast_adc_i (clkmgr_aon_clocks.clk_aon_peri), + .clk_ast_alert_i (clkmgr_aon_clocks.clk_io_div4_secure), + .clk_ast_es_i (clkmgr_aon_clocks.clk_main_secure), + .clk_ast_rng_i (clkmgr_aon_clocks.clk_main_secure), + .clk_ast_usb_i (clkmgr_aon_clocks.clk_usb_peri), + .rst_ast_tlul_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_ast_adc_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]), + .rst_ast_alert_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_ast_es_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_ast_rng_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_ast_usb_ni (rstmgr_aon_resets.rst_por_usb_n[rstmgr_pkg::Domain0Sel]), + .clk_ast_ext_i ( ext_clk ), + + // pok test for FPGA + .vcc_supp_i ( 1'b1 ), + .vcaon_supp_i ( 1'b1 ), + .vcmain_supp_i ( 1'b1 ), + .vioa_supp_i ( 1'b1 ), + .viob_supp_i ( 1'b1 ), + // pok + .ast_pwst_o ( ast_pwst ), + .ast_pwst_h_o ( ), + // main regulator + .main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ), + .main_pd_ni ( base_ast_pwr.main_pd_n ), + // pdm control (flash)/otp + .flash_power_down_h_o ( ), + .flash_power_ready_h_o ( ), + .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ), + .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ), + // system source clock + .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ), + // need to add function in clkmgr + .clk_src_sys_jen_i ( jen ), + .clk_src_sys_o ( ast_base_clks.clk_sys ), + .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ), + // aon source clock + .clk_src_aon_o ( ast_base_clks.clk_aon ), + .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ), + // io source clock + .clk_src_io_en_i ( base_ast_pwr.io_clk_en ), + .clk_src_io_o ( ast_base_clks.clk_io ), + .clk_src_io_val_o ( ast_base_pwr.io_clk_val ), + .clk_src_io_48m_o ( div_step_down_req ), + // usb source clock + .usb_ref_pulse_i ( '0 ), + .usb_ref_val_i ( '0 ), + .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ), + .clk_src_usb_o ( ast_base_clks.clk_usb ), + .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ), + // entropy_src + .es_req_i ( entropy_src_hw_if_req ), + .es_rsp_o ( entropy_src_hw_if_rsp ), + // adc + .adc_pd_i ( '0 ), + .adc_chnsel_i ( '0 ), + .adc_d_o ( ), + .adc_d_val_o ( ), + // entropy + .entropy_rsp_i ( ast_edn_edn_rsp ), + .entropy_req_o ( ast_edn_edn_req ), + // alerts + .alert_rsp_i ( ast_alert_rsp ), + .alert_req_o ( ast_alert_req ), + // dft + .dft_strap_test_i ( dft_strap_test ), + .lc_dft_en_i ( lc_dft_en ), + .fla_obs_i ( '0 ), + .usb_obs_i ( '0 ), + .otp_obs_i ( otp_obs ), + .otm_obs_i ( '0 ), + .obs_ctrl_o ( obs_ctrl ), + // pinmux related + .padmux2ast_i ( '0 ), + .ast2padmux_o ( ), + .ext_freq_is_96m_i ( hi_speed_sel ), + .all_clk_byp_req_i ( all_clk_byp_req ), + .all_clk_byp_ack_o ( all_clk_byp_ack ), + .io_clk_byp_req_i ( io_clk_byp_req ), + .io_clk_byp_ack_o ( io_clk_byp_ack ), + .flash_bist_en_o ( ), + // Memory configuration connections + .dpram_rmf_o ( ast_ram_2p_fcfg ), + .dpram_rml_o ( ast_ram_2p_lcfg ), + .spram_rm_o ( ast_ram_1p_cfg ), + .sprgf_rm_o ( ast_rf_cfg ), + .sprom_rm_o ( ast_rom_cfg ), + // scan + .dft_scan_md_o ( scanmode ), + .scan_shift_en_o ( scan_en ), + .scan_reset_no ( scan_rst_n ) + ); + + ////////////////// + // TAP Instance // + ////////////////// + + tlul_pkg::tl_h2d_t dmi_h2d; + tlul_pkg::tl_d2h_t dmi_d2h; + jtag_pkg::jtag_req_t jtag_req; + jtag_pkg::jtag_rsp_t jtag_rsp; + + assign jtag_req.tck = manual_in_jtag_tck; + assign jtag_req.tms = manual_in_jtag_tms; + assign jtag_req.trst_n = manual_in_jtag_trst_n; + assign jtag_req.tdi = manual_in_jtag_tdi; + + assign manual_out_jtag_tck = '0; + assign manual_out_jtag_tms = '0; + assign manual_out_jtag_trst_n = '0; + assign manual_out_jtag_tdi = '0; + assign manual_oe_jtag_tck = '0; + assign manual_oe_jtag_tms = '0; + assign manual_oe_jtag_trst_n = '0; + assign manual_oe_jtag_tdi = '0; + assign manual_attr_jtag_tck = '0; + assign manual_attr_jtag_tms = '0; + assign manual_attr_jtag_trst_n = '0; + assign manual_attr_jtag_tdi = '0; + + assign manual_out_jtag_tdo = jtag_rsp.tdo; + assign manual_oe_jtag_tdo = jtag_rsp.tdo_oe; + assign manual_attr_jtag_tdo = '0; + + logic unused_manual_jtag_sigs; + assign unused_manual_jtag_sigs = ^{ + manual_in_jtag_tdo + }; + + tlul_jtag_dtm #( + .IdcodeValue(jtag_id_pkg::LC_DM_COMBINED_JTAG_IDCODE), + // Notes: + // - one RV_DM instance uses 9bits + // - our crossbar tooling expects individual IPs to be spaced apart by 12bits at the moment + // - the DMI address shifted through jtag is a word address and hence 2bits smaller than this + // - setting this to 18bits effectively gives us 2^6 = 64 addressable 12bit ranges + .NumDmiByteAbits(18) + ) u_tlul_jtag_dtm ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]), + .jtag_i (jtag_req), + .jtag_o (jtag_rsp), + .scan_rst_ni(scan_rst_n), + .scanmode_i (scanmode), + .tl_h2d_o (dmi_h2d), + .tl_d2h_i (dmi_d2h) + ); + + //////////////// + // CTN M-to-1 // + //////////////// + + tlul_pkg::tl_h2d_t ctn_tl_h2d[2]; + tlul_pkg::tl_d2h_t ctn_tl_d2h[2]; + + tlul_pkg::tl_h2d_t ctn_sm1_to_s1n_tl_h2d; + tlul_pkg::tl_d2h_t ctn_sm1_to_s1n_tl_d2h; + + tlul_socket_m1 #( + .M (2), + .HReqPass ({2{1'b1}}), + .HRspPass ({2{1'b1}}), + .HReqDepth ({2{4'd0}}), + .HRspDepth ({2{4'd0}}), + .DReqPass (1'b1), + .DRspPass (1'b1), + .DReqDepth (4'd0), + .DRspDepth (4'd0) + ) u_ctn_sm1 ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_h_i (ctn_tl_h2d), + .tl_h_o (ctn_tl_d2h), + .tl_d_o (ctn_sm1_to_s1n_tl_h2d), + .tl_d_i (ctn_sm1_to_s1n_tl_d2h) + ); + + //////////////////////////////////////////// + // CTN Address decoding and SRAM Instance // + //////////////////////////////////////////// + + localparam int CtnSramDw = top_pkg::TL_DW + tlul_pkg::DataIntgWidth; + + tlul_pkg::tl_h2d_t ctn_s1n_tl_h2d[1]; + tlul_pkg::tl_d2h_t ctn_s1n_tl_d2h[1]; + + // Steering signal for address decoding. + logic [0:0] ctn_dev_sel_s1n; + + logic sram_req, sram_we, sram_rvalid; + logic [top_pkg::CtnSramAw-1:0] sram_addr; + logic [CtnSramDw-1:0] sram_wdata, sram_wmask, sram_rdata; + + // Steering of requests. + // Addresses leaving the RoT through the CTN port are mapped to an internal 1G address space of + // 0x4000_0000 - 0x8000_0000. However, the CTN RAM only covers a 1MB region inside that space, + // and hence additional decoding and steering logic is needed here. + // TODO: this should in the future be replaced by an automatically generated crossbar. + always_comb begin + // Default steering to generate error response if address is not within the range + ctn_dev_sel_s1n = 1'b1; + // Steering to CTN SRAM. + if ((ctn_sm1_to_s1n_tl_h2d.a_address & ~(TOP_DARJEELING_RAM_CTN_SIZE_BYTES-1)) == + TOP_DARJEELING_RAM_CTN_BASE_ADDR) begin + ctn_dev_sel_s1n = 1'd0; + end + end + + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (8'h0), + .DRspDepth (8'h0), + .N (1) + ) u_ctn_s1n ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_h_i (ctn_sm1_to_s1n_tl_h2d), + .tl_h_o (ctn_sm1_to_s1n_tl_d2h), + .tl_d_o (ctn_s1n_tl_h2d), + .tl_d_i (ctn_s1n_tl_d2h), + .dev_select_i (ctn_dev_sel_s1n) + ); + + tlul_adapter_sram #( + .SramAw(top_pkg::CtnSramAw), + .SramDw(CtnSramDw - tlul_pkg::DataIntgWidth), + .Outstanding(2), + .ByteAccess(1), + .CmdIntgCheck(1), + .EnableRspIntgGen(1), + .EnableDataIntgGen(0), + .EnableDataIntgPt(1), + .SecFifoPtr (0) + ) u_tlul_adapter_sram_ctn ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_i (ctn_s1n_tl_h2d[0]), + .tl_o (ctn_s1n_tl_d2h[0]), + // Ifetch is explicitly allowed + .en_ifetch_i (prim_mubi_pkg::MuBi4True), + .req_o (sram_req), + .req_type_o (), + // SRAM can always accept a request. + .gnt_i (1'b1), + .we_o (sram_we), + .addr_o (sram_addr), + .wdata_o (sram_wdata), + .wmask_o (sram_wmask), + .intg_error_o(), + .rdata_i (sram_rdata), + .rvalid_i (sram_rvalid), + .rerror_i ('0) + ); + + prim_ram_1p_adv #( + .Depth(top_pkg::CtnSramDepth), + .Width(CtnSramDw), + .DataBitsPerMask(CtnSramDw), + .EnableECC(0), + .EnableParity(0), + .EnableInputPipeline(1), + .EnableOutputPipeline(1) + ) u_prim_ram_1p_adv_ctn ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .req_i (sram_req), + .write_i (sram_we), + .addr_i (sram_addr), + .wdata_i (sram_wdata), + .wmask_i (sram_wmask), + .rdata_o (sram_rdata), + .rvalid_o (sram_rvalid), + // No error detection is enabled inside SRAM. + // Bus ECC is checked at the consumer side. + .rerror_o (), + .cfg_i (ram_1p_cfg) + ); + + + + ////////////////////////////////// + // Manual Pad / Signal Tie-offs // + ////////////////////////////////// + + assign manual_out_por_n = 1'b0; + assign manual_oe_por_n = 1'b0; + + assign manual_out_otp_ext_volt = 1'b0; + assign manual_oe_otp_ext_volt = 1'b0; + + // These pad attributes currently tied off permanently (these are all input-only pads). + assign manual_attr_por_n = '0; + assign manual_attr_otp_ext_volt = '0; + + logic unused_manual_sigs; + assign unused_manual_sigs = ^{ + manual_in_otp_ext_volt + }; + + + soc_proxy_pkg::soc_alert_req_t [soc_proxy_pkg::NumFatalExternalAlerts-1:0] soc_fatal_alert_req; + soc_proxy_pkg::soc_alert_req_t [soc_proxy_pkg::NumRecovExternalAlerts-1:0] soc_recov_alert_req; + assign soc_fatal_alert_req = + {soc_proxy_pkg::NumFatalExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}}; + assign soc_recov_alert_req = + {soc_proxy_pkg::NumRecovExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}}; + // The logic below is a is a loopback path. It listens to the internal reset request generated by + // the power manager and translates this request into a stretched pulse (modeled by the counter). + // The stretched pulse is fed back to top_darjeeling as external async SoC reset request. + // TODO(#22710): This should be moved to the DV environment, and we need to extend the code to be + // able to asynchronously assert the external reset pin without any internal request. + logic internal_request_d, internal_request_q; + logic external_reset, count_up; + logic [3:0] count; + assign internal_request_d = pwrmgr_boot_status.light_reset_req; + always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin + if (!por_n[0]) begin + external_reset <= 1'b0; + internal_request_q <= 1'b0; + count_up <= '0; + count <= '0; + end else begin + internal_request_q <= internal_request_d; + if (!internal_request_q && internal_request_d) begin + count_up <= 1'b1; + external_reset <= 1; + end else if (count == 'd8) begin + count_up <= 0; + external_reset <= 0; + count <= '0; + end else if (count_up) begin + count <= count + 1; + end + end + end + + ////////////////////// + // Top-level design // + ////////////////////// + top_darjeeling #( + .PinmuxAonTargetCfg(PinmuxTargetCfg), + .SecAesAllowForcingMasks(1'b1), + .SecRomCtrl0DisableScrambling(SecRomCtrl0DisableScrambling), + .SecRomCtrl1DisableScrambling(SecRomCtrl1DisableScrambling) + ) top_darjeeling ( + // ast connections + .por_n_i ( por_n ), + .clk_main_i ( ast_base_clks.clk_sys ), + .clk_io_i ( ast_base_clks.clk_io ), + .clk_usb_i ( ast_base_clks.clk_usb ), + .clk_aon_i ( ast_base_clks.clk_aon ), + .clks_ast_o ( clkmgr_aon_clocks ), + .clk_main_jitter_en_o ( jen ), + .rsts_ast_o ( rstmgr_aon_resets ), + .sck_monitor_o ( sck_monitor ), + .pwrmgr_ast_req_o ( base_ast_pwr ), + .pwrmgr_ast_rsp_i ( ast_base_pwr ), + .sensor_ctrl_ast_alert_req_i ( ast_alert_req ), + .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ), + .sensor_ctrl_ast_status_i ( ast_pwst.io_pok ), + .ast_edn_req_i ( ast_edn_edn_req ), + .ast_edn_rsp_o ( ast_edn_edn_rsp ), + .ast_tl_req_o ( base_ast_bus ), + .ast_tl_rsp_i ( ast_base_bus ), + .obs_ctrl_i ( obs_ctrl ), + .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ), + .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ), + .otp_obs_o ( otp_obs ), + .ctn_tl_h2d_o ( ctn_tl_h2d[0] ), + .ctn_tl_d2h_i ( ctn_tl_d2h[0] ), + .soc_gpi_async_o ( ), + .soc_gpo_async_i ( '0 ), + .dma_sys_req_o ( ), + .dma_sys_rsp_i ( '0 ), + .dma_ctn_tl_h2d_o ( ctn_tl_h2d[1] ), + .dma_ctn_tl_d2h_i ( ctn_tl_d2h[1] ), + .mbx_tl_req_i ( tlul_pkg::TL_H2D_DEFAULT ), + .mbx_tl_rsp_o ( ), + .pwrmgr_boot_status_o ( pwrmgr_boot_status ), + .soc_fatal_alert_req_i ( soc_fatal_alert_req ), + .soc_fatal_alert_rsp_o ( ), + .soc_recov_alert_req_i ( soc_recov_alert_req ), + .soc_recov_alert_rsp_o ( ), + .soc_intr_async_i ( '0 ), + .soc_wkup_async_i ( 1'b0 ), + // TODO(#22710): this should come from modeled SoC (e.g., from TB). + .soc_rst_req_async_i ( external_reset ), + .soc_lsio_trigger_i ( '0 ), + .entropy_src_hw_if_req_o ( entropy_src_hw_if_req ), + .entropy_src_hw_if_rsp_i ( entropy_src_hw_if_rsp ), + .mbx0_doe_intr_en_o ( ), + .mbx0_doe_intr_o ( ), + .mbx0_doe_intr_support_o ( ), + .mbx0_doe_async_msg_support_o ( ), + .mbx1_doe_intr_en_o ( ), + .mbx1_doe_intr_o ( ), + .mbx1_doe_intr_support_o ( ), + .mbx1_doe_async_msg_support_o ( ), + .mbx2_doe_intr_en_o ( ), + .mbx2_doe_intr_o ( ), + .mbx2_doe_intr_support_o ( ), + .mbx2_doe_async_msg_support_o ( ), + .mbx3_doe_intr_en_o ( ), + .mbx3_doe_intr_o ( ), + .mbx3_doe_intr_support_o ( ), + .mbx3_doe_async_msg_support_o ( ), + .mbx4_doe_intr_en_o ( ), + .mbx4_doe_intr_o ( ), + .mbx4_doe_intr_support_o ( ), + .mbx4_doe_async_msg_support_o ( ), + .mbx5_doe_intr_en_o ( ), + .mbx5_doe_intr_o ( ), + .mbx5_doe_intr_support_o ( ), + .mbx5_doe_async_msg_support_o ( ), + .mbx6_doe_intr_en_o ( ), + .mbx6_doe_intr_o ( ), + .mbx6_doe_intr_support_o ( ), + .mbx6_doe_async_msg_support_o ( ), + .mbx_jtag_doe_intr_en_o ( ), + .mbx_jtag_doe_intr_o ( ), + .mbx_jtag_doe_intr_support_o ( ), + .mbx_jtag_doe_async_msg_support_o ( ), + .mbx_pcie0_doe_intr_en_o ( ), + .mbx_pcie0_doe_intr_o ( ), + .mbx_pcie0_doe_intr_support_o ( ), + .mbx_pcie0_doe_async_msg_support_o ( ), + .mbx_pcie1_doe_intr_en_o ( ), + .mbx_pcie1_doe_intr_o ( ), + .mbx_pcie1_doe_intr_support_o ( ), + .mbx_pcie1_doe_async_msg_support_o ( ), + .io_clk_byp_req_o ( io_clk_byp_req ), + .io_clk_byp_ack_i ( io_clk_byp_ack ), + .all_clk_byp_req_o ( all_clk_byp_req ), + .all_clk_byp_ack_i ( all_clk_byp_ack ), + .hi_speed_sel_o ( hi_speed_sel ), + .div_step_down_req_i ( div_step_down_req ), + .calib_rdy_i ( ast_init_done ), + .ast_init_done_i ( ast_init_done ), + + // OTP external voltage + .otp_ext_voltage_h_io ( OTP_EXT_VOLT ), + + // DMI TL-UL + .dbg_tl_req_i ( dmi_h2d ), + .dbg_tl_rsp_o ( dmi_d2h ), + // Quasi-static word address for next_dm register value. + .rv_dm_next_dm_addr_i ( '0 ), + // Multiplexed I/O + .mio_in_i ( mio_in ), + .mio_out_o ( mio_out ), + .mio_oe_o ( mio_oe ), + + // Dedicated I/O + .dio_in_i ( dio_in ), + .dio_out_o ( dio_out ), + .dio_oe_o ( dio_oe ), + + // Pad attributes + .mio_attr_o ( mio_attr ), + .dio_attr_o ( dio_attr ), + + // Memory attributes + .ram_1p_cfg_i ( ram_1p_cfg ), + .spi_ram_2p_cfg_i ( spi_ram_2p_cfg ), + + .rom_cfg_i ( rom_cfg ), + + // DFT signals + .ast_lc_dft_en_o ( lc_dft_en ), + .ast_lc_hw_debug_en_o ( ), + .dft_strap_test_o ( dft_strap_test ), + .dft_hold_tap_sel_i ( '0 ), + .scan_rst_ni ( scan_rst_n ), + .scan_en_i ( scan_en ), + .scanmode_i ( scanmode ), + + // FPGA build info + .fpga_info_i ( '0 ) + ); + + + +endmodule : chip_darjeeling_asic diff --git a/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv new file mode 100644 index 0000000000000..06cb01473015c --- /dev/null +++ b/hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv @@ -0,0 +1,1565 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \ +// -o hw/top_darjeeling/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + + +module chip_darjeeling_cw310 #( + // Path to a VMEM file containing the contents of the boot ROM, which will be + // baked into the FPGA bitstream. + parameter BootRomInitFile = "test_rom_fpga_cw310.32.vmem", + // Path to a VMEM file containing the contents of the emulated OTP, which will be + // baked into the FPGA bitstream. + parameter OtpCtrlMemInitFile = "otp_img_fpga_cw310.vmem" +) ( + // Dedicated Pads + inout POR_N, // Manual Pad + inout JTAG_TCK, // Manual Pad + inout JTAG_TMS, // Manual Pad + inout JTAG_TDI, // Manual Pad + inout JTAG_TDO, // Manual Pad + inout JTAG_TRST_N, // Manual Pad + inout SPI_HOST_D0, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_D1, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_D2, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_D3, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_CLK, // Dedicated Pad for spi_host0_sck + inout SPI_HOST_CS_L, // Dedicated Pad for spi_host0_csb + inout SPI_DEV_D0, // Dedicated Pad for spi_device_sd + inout SPI_DEV_D1, // Dedicated Pad for spi_device_sd + inout SPI_DEV_D2, // Dedicated Pad for spi_device_sd + inout SPI_DEV_D3, // Dedicated Pad for spi_device_sd + inout SPI_DEV_CLK, // Dedicated Pad for spi_device_sck + inout SPI_DEV_CS_L, // Dedicated Pad for spi_device_csb + inout SPI_DEV_TPM_CS_L, // Dedicated Pad for spi_device_tpm_csb + inout UART_RX, // Dedicated Pad for uart0_rx + inout UART_TX, // Dedicated Pad for uart0_tx + inout I2C_SCL, // Dedicated Pad for i2c0_scl + inout I2C_SDA, // Dedicated Pad for i2c0_sda + inout GPIO0, // Dedicated Pad for gpio_gpio + inout GPIO1, // Dedicated Pad for gpio_gpio + inout GPIO2, // Dedicated Pad for gpio_gpio + inout GPIO3, // Dedicated Pad for gpio_gpio + inout GPIO4, // Dedicated Pad for gpio_gpio + inout GPIO5, // Dedicated Pad for gpio_gpio + inout GPIO6, // Dedicated Pad for gpio_gpio + inout GPIO7, // Dedicated Pad for gpio_gpio + inout GPIO8, // Dedicated Pad for gpio_gpio + inout GPIO9, // Dedicated Pad for gpio_gpio + inout GPIO10, // Dedicated Pad for gpio_gpio + inout GPIO11, // Dedicated Pad for gpio_gpio + inout GPIO12, // Dedicated Pad for gpio_gpio + inout GPIO13, // Dedicated Pad for gpio_gpio + inout GPIO14, // Dedicated Pad for gpio_gpio + inout GPIO15, // Dedicated Pad for gpio_gpio + inout GPIO16, // Dedicated Pad for gpio_gpio + inout GPIO17, // Dedicated Pad for gpio_gpio + inout GPIO18, // Dedicated Pad for gpio_gpio + inout GPIO19, // Dedicated Pad for gpio_gpio + inout GPIO20, // Dedicated Pad for gpio_gpio + inout GPIO21, // Dedicated Pad for gpio_gpio + inout GPIO22, // Dedicated Pad for gpio_gpio + inout GPIO23, // Dedicated Pad for gpio_gpio + inout GPIO24, // Dedicated Pad for gpio_gpio + inout GPIO25, // Dedicated Pad for gpio_gpio + inout GPIO26, // Dedicated Pad for gpio_gpio + inout GPIO27, // Dedicated Pad for gpio_gpio + inout GPIO28, // Dedicated Pad for gpio_gpio + inout GPIO29, // Dedicated Pad for gpio_gpio + inout GPIO30, // Dedicated Pad for gpio_gpio + inout GPIO31, // Dedicated Pad for gpio_gpio + inout SOC_GPI0, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI1, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI2, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI3, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI4, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI5, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI6, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI7, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI8, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI9, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI10, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI11, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPO0, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO1, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO2, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO3, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO4, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO5, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO6, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO7, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO8, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO9, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO10, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO11, // Dedicated Pad for soc_proxy_soc_gpo + inout IO_CLK, // Manual Pad + inout POR_BUTTON_N, // Manual Pad + inout IO_CLKOUT, // Manual Pad + inout IO_TRIGGER, // Manual Pad + + // Muxed Pads + inout MIO0, // MIO Pad 0 + inout MIO1, // MIO Pad 1 + inout MIO2, // MIO Pad 2 + inout MIO3, // MIO Pad 3 + inout MIO4, // MIO Pad 4 + inout MIO5, // MIO Pad 5 + inout MIO6, // MIO Pad 6 + inout MIO7, // MIO Pad 7 + inout MIO8, // MIO Pad 8 + inout MIO9, // MIO Pad 9 + inout MIO10, // MIO Pad 10 + inout MIO11 // MIO Pad 11 +); + + import top_darjeeling_pkg::*; + import prim_pad_wrapper_pkg::*; + + //////////////////////////// + // Special Signal Indices // + //////////////////////////// + + localparam int Tap0PadIdx = 0; + localparam int Tap1PadIdx = 1; + localparam int Dft0PadIdx = 2; + localparam int Dft1PadIdx = 3; + localparam int TckPadIdx = 4; + localparam int TmsPadIdx = 5; + localparam int TrstNPadIdx = 6; + localparam int TdiPadIdx = 7; + localparam int TdoPadIdx = 8; + + // DFT and Debug signal positions in the pinout. + localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ + tck_idx: TckPadIdx, + tms_idx: TmsPadIdx, + trst_idx: TrstNPadIdx, + tdi_idx: TdiPadIdx, + tdo_idx: TdoPadIdx, + tap_strap0_idx: Tap0PadIdx, + tap_strap1_idx: Tap1PadIdx, + dft_strap0_idx: Dft0PadIdx, + dft_strap1_idx: Dft1PadIdx, + // TODO: check whether there is a better way to pass these USB-specific params + // The use of these indexes is gated behind a parameter, but to synthesize they + // need to exist even if the code-path is never used (pinmux.sv:UsbWkupModuleEn). + // Hence, set to zero. + usb_dp_idx: 0, + usb_dn_idx: 0, + usb_sense_idx: 0, + // Pad types for attribute WARL behavior + dio_pad_type: { + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO uart0_tx + BidirStd, // DIO spi_host0_csb + BidirStd, // DIO spi_host0_sck + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO uart0_rx + InputStd, // DIO spi_device_tpm_csb + InputStd, // DIO spi_device_csb + InputStd, // DIO spi_device_sck + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO i2c0_sda + BidirStd, // DIO i2c0_scl + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd // DIO spi_host0_sd + }, + mio_pad_type: { + BidirStd, // MIO Pad 11 + BidirStd, // MIO Pad 10 + BidirStd, // MIO Pad 9 + BidirStd, // MIO Pad 8 + BidirStd, // MIO Pad 7 + BidirStd, // MIO Pad 6 + BidirStd, // MIO Pad 5 + BidirStd, // MIO Pad 4 + BidirStd, // MIO Pad 3 + BidirStd, // MIO Pad 2 + BidirStd, // MIO Pad 1 + BidirStd // MIO Pad 0 + } + }; + + //////////////////////// + // Signal definitions // + //////////////////////// + + + pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr; + pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_out; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_raw; + logic [83-1:0] dio_in_raw; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_out; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_in; + + logic unused_mio_in_raw; + logic unused_dio_in_raw; + assign unused_mio_in_raw = ^mio_in_raw; + assign unused_dio_in_raw = ^dio_in_raw; + + // Manual pads + logic manual_in_por_n, manual_out_por_n, manual_oe_por_n; + logic manual_in_jtag_tck, manual_out_jtag_tck, manual_oe_jtag_tck; + logic manual_in_jtag_tms, manual_out_jtag_tms, manual_oe_jtag_tms; + logic manual_in_jtag_tdi, manual_out_jtag_tdi, manual_oe_jtag_tdi; + logic manual_in_jtag_tdo, manual_out_jtag_tdo, manual_oe_jtag_tdo; + logic manual_in_jtag_trst_n, manual_out_jtag_trst_n, manual_oe_jtag_trst_n; + logic manual_in_io_clk, manual_out_io_clk, manual_oe_io_clk; + logic manual_in_por_button_n, manual_out_por_button_n, manual_oe_por_button_n; + logic manual_in_io_clkout, manual_out_io_clkout, manual_oe_io_clkout; + logic manual_in_io_trigger, manual_out_io_trigger, manual_oe_io_trigger; + + pad_attr_t manual_attr_por_n; + pad_attr_t manual_attr_jtag_tck; + pad_attr_t manual_attr_jtag_tms; + pad_attr_t manual_attr_jtag_tdi; + pad_attr_t manual_attr_jtag_tdo; + pad_attr_t manual_attr_jtag_trst_n; + pad_attr_t manual_attr_io_clk; + pad_attr_t manual_attr_por_button_n; + pad_attr_t manual_attr_io_clkout; + pad_attr_t manual_attr_io_trigger; + + ///////////////////////// + // Stubbed pad tie-off // + ///////////////////////// + + // Only signals going to non-custom pads need to be tied off. + logic [91:0] unused_sig; + + ////////////////////// + // Padring Instance // + ////////////////////// + + ast_pkg::ast_clks_t ast_base_clks; + + + padring #( + // Padring specific counts may differ from pinmux config due + // to custom, stubbed or added pads. + .NDioPads(83), + .NMioPads(12), + .DioPadType ({ + BidirStd, // IO_TRIGGER + BidirStd, // IO_CLKOUT + InputStd, // POR_BUTTON_N + InputStd, // IO_CLK + BidirStd, // SOC_GPO11 + BidirStd, // SOC_GPO10 + BidirStd, // SOC_GPO9 + BidirStd, // SOC_GPO8 + BidirStd, // SOC_GPO7 + BidirStd, // SOC_GPO6 + BidirStd, // SOC_GPO5 + BidirStd, // SOC_GPO4 + BidirStd, // SOC_GPO3 + BidirStd, // SOC_GPO2 + BidirStd, // SOC_GPO1 + BidirStd, // SOC_GPO0 + InputStd, // SOC_GPI11 + InputStd, // SOC_GPI10 + InputStd, // SOC_GPI9 + InputStd, // SOC_GPI8 + InputStd, // SOC_GPI7 + InputStd, // SOC_GPI6 + InputStd, // SOC_GPI5 + InputStd, // SOC_GPI4 + InputStd, // SOC_GPI3 + InputStd, // SOC_GPI2 + InputStd, // SOC_GPI1 + InputStd, // SOC_GPI0 + BidirStd, // GPIO31 + BidirStd, // GPIO30 + BidirStd, // GPIO29 + BidirStd, // GPIO28 + BidirStd, // GPIO27 + BidirStd, // GPIO26 + BidirStd, // GPIO25 + BidirStd, // GPIO24 + BidirStd, // GPIO23 + BidirStd, // GPIO22 + BidirStd, // GPIO21 + BidirStd, // GPIO20 + BidirStd, // GPIO19 + BidirStd, // GPIO18 + BidirStd, // GPIO17 + BidirStd, // GPIO16 + BidirStd, // GPIO15 + BidirStd, // GPIO14 + BidirStd, // GPIO13 + BidirStd, // GPIO12 + BidirStd, // GPIO11 + BidirStd, // GPIO10 + BidirStd, // GPIO9 + BidirStd, // GPIO8 + BidirStd, // GPIO7 + BidirStd, // GPIO6 + BidirStd, // GPIO5 + BidirStd, // GPIO4 + BidirStd, // GPIO3 + BidirStd, // GPIO2 + BidirStd, // GPIO1 + BidirStd, // GPIO0 + BidirStd, // I2C_SDA + BidirStd, // I2C_SCL + BidirStd, // UART_TX + InputStd, // UART_RX + InputStd, // SPI_DEV_TPM_CS_L + InputStd, // SPI_DEV_CS_L + InputStd, // SPI_DEV_CLK + BidirStd, // SPI_DEV_D3 + BidirStd, // SPI_DEV_D2 + BidirStd, // SPI_DEV_D1 + BidirStd, // SPI_DEV_D0 + BidirStd, // SPI_HOST_CS_L + BidirStd, // SPI_HOST_CLK + BidirStd, // SPI_HOST_D3 + BidirStd, // SPI_HOST_D2 + BidirStd, // SPI_HOST_D1 + BidirStd, // SPI_HOST_D0 + InputStd, // JTAG_TRST_N + BidirStd, // JTAG_TDO + InputStd, // JTAG_TDI + InputStd, // JTAG_TMS + InputStd, // JTAG_TCK + InputStd // POR_N + }), + .MioPadType ({ + BidirStd, // MIO11 + BidirStd, // MIO10 + BidirStd, // MIO9 + BidirStd, // MIO8 + BidirStd, // MIO7 + BidirStd, // MIO6 + BidirStd, // MIO5 + BidirStd, // MIO4 + BidirStd, // MIO3 + BidirStd, // MIO2 + BidirStd, // MIO1 + BidirStd // MIO0 + }) + ) u_padring ( + // This is only used for scan and DFT purposes + .clk_scan_i ( 1'b0 ), + .scanmode_i ( prim_mubi_pkg::MuBi4False ), + .dio_in_raw_o ( dio_in_raw ), + // Chip IOs + .dio_pad_io ({ + IO_TRIGGER, + IO_CLKOUT, + POR_BUTTON_N, + IO_CLK, + SOC_GPO11, + SOC_GPO10, + SOC_GPO9, + SOC_GPO8, + SOC_GPO7, + SOC_GPO6, + SOC_GPO5, + SOC_GPO4, + SOC_GPO3, + SOC_GPO2, + SOC_GPO1, + SOC_GPO0, + SOC_GPI11, + SOC_GPI10, + SOC_GPI9, + SOC_GPI8, + SOC_GPI7, + SOC_GPI6, + SOC_GPI5, + SOC_GPI4, + SOC_GPI3, + SOC_GPI2, + SOC_GPI1, + SOC_GPI0, + GPIO31, + GPIO30, + GPIO29, + GPIO28, + GPIO27, + GPIO26, + GPIO25, + GPIO24, + GPIO23, + GPIO22, + GPIO21, + GPIO20, + GPIO19, + GPIO18, + GPIO17, + GPIO16, + GPIO15, + GPIO14, + GPIO13, + GPIO12, + GPIO11, + GPIO10, + GPIO9, + GPIO8, + GPIO7, + GPIO6, + GPIO5, + GPIO4, + GPIO3, + GPIO2, + GPIO1, + GPIO0, + I2C_SDA, + I2C_SCL, + UART_TX, + UART_RX, + SPI_DEV_TPM_CS_L, + SPI_DEV_CS_L, + SPI_DEV_CLK, + SPI_DEV_D3, + SPI_DEV_D2, + SPI_DEV_D1, + SPI_DEV_D0, + SPI_HOST_CS_L, + SPI_HOST_CLK, + SPI_HOST_D3, + SPI_HOST_D2, + SPI_HOST_D1, + SPI_HOST_D0, + JTAG_TRST_N, + JTAG_TDO, + JTAG_TDI, + JTAG_TMS, + JTAG_TCK, + POR_N + }), + + .mio_pad_io ({ + MIO11, + MIO10, + MIO9, + MIO8, + MIO7, + MIO6, + MIO5, + MIO4, + MIO3, + MIO2, + MIO1, + MIO0 + }), + + // Core-facing + .dio_in_o ({ + manual_in_io_trigger, + manual_in_io_clkout, + manual_in_por_button_n, + manual_in_io_clk, + dio_in[DioSocProxySocGpo11], + dio_in[DioSocProxySocGpo10], + dio_in[DioSocProxySocGpo9], + dio_in[DioSocProxySocGpo8], + dio_in[DioSocProxySocGpo7], + dio_in[DioSocProxySocGpo6], + dio_in[DioSocProxySocGpo5], + dio_in[DioSocProxySocGpo4], + dio_in[DioSocProxySocGpo3], + dio_in[DioSocProxySocGpo2], + dio_in[DioSocProxySocGpo1], + dio_in[DioSocProxySocGpo0], + dio_in[DioSocProxySocGpi11], + dio_in[DioSocProxySocGpi10], + dio_in[DioSocProxySocGpi9], + dio_in[DioSocProxySocGpi8], + dio_in[DioSocProxySocGpi7], + dio_in[DioSocProxySocGpi6], + dio_in[DioSocProxySocGpi5], + dio_in[DioSocProxySocGpi4], + dio_in[DioSocProxySocGpi3], + dio_in[DioSocProxySocGpi2], + dio_in[DioSocProxySocGpi1], + dio_in[DioSocProxySocGpi0], + dio_in[DioGpioGpio31], + dio_in[DioGpioGpio30], + dio_in[DioGpioGpio29], + dio_in[DioGpioGpio28], + dio_in[DioGpioGpio27], + dio_in[DioGpioGpio26], + dio_in[DioGpioGpio25], + dio_in[DioGpioGpio24], + dio_in[DioGpioGpio23], + dio_in[DioGpioGpio22], + dio_in[DioGpioGpio21], + dio_in[DioGpioGpio20], + dio_in[DioGpioGpio19], + dio_in[DioGpioGpio18], + dio_in[DioGpioGpio17], + dio_in[DioGpioGpio16], + dio_in[DioGpioGpio15], + dio_in[DioGpioGpio14], + dio_in[DioGpioGpio13], + dio_in[DioGpioGpio12], + dio_in[DioGpioGpio11], + dio_in[DioGpioGpio10], + dio_in[DioGpioGpio9], + dio_in[DioGpioGpio8], + dio_in[DioGpioGpio7], + dio_in[DioGpioGpio6], + dio_in[DioGpioGpio5], + dio_in[DioGpioGpio4], + dio_in[DioGpioGpio3], + dio_in[DioGpioGpio2], + dio_in[DioGpioGpio1], + dio_in[DioGpioGpio0], + dio_in[DioI2c0Sda], + dio_in[DioI2c0Scl], + dio_in[DioUart0Tx], + dio_in[DioUart0Rx], + dio_in[DioSpiDeviceTpmCsb], + dio_in[DioSpiDeviceCsb], + dio_in[DioSpiDeviceSck], + dio_in[DioSpiDeviceSd3], + dio_in[DioSpiDeviceSd2], + dio_in[DioSpiDeviceSd1], + dio_in[DioSpiDeviceSd0], + dio_in[DioSpiHost0Csb], + dio_in[DioSpiHost0Sck], + dio_in[DioSpiHost0Sd3], + dio_in[DioSpiHost0Sd2], + dio_in[DioSpiHost0Sd1], + dio_in[DioSpiHost0Sd0], + manual_in_jtag_trst_n, + manual_in_jtag_tdo, + manual_in_jtag_tdi, + manual_in_jtag_tms, + manual_in_jtag_tck, + manual_in_por_n + }), + .dio_out_i ({ + manual_out_io_trigger, + manual_out_io_clkout, + manual_out_por_button_n, + manual_out_io_clk, + dio_out[DioSocProxySocGpo11], + dio_out[DioSocProxySocGpo10], + dio_out[DioSocProxySocGpo9], + dio_out[DioSocProxySocGpo8], + dio_out[DioSocProxySocGpo7], + dio_out[DioSocProxySocGpo6], + dio_out[DioSocProxySocGpo5], + dio_out[DioSocProxySocGpo4], + dio_out[DioSocProxySocGpo3], + dio_out[DioSocProxySocGpo2], + dio_out[DioSocProxySocGpo1], + dio_out[DioSocProxySocGpo0], + dio_out[DioSocProxySocGpi11], + dio_out[DioSocProxySocGpi10], + dio_out[DioSocProxySocGpi9], + dio_out[DioSocProxySocGpi8], + dio_out[DioSocProxySocGpi7], + dio_out[DioSocProxySocGpi6], + dio_out[DioSocProxySocGpi5], + dio_out[DioSocProxySocGpi4], + dio_out[DioSocProxySocGpi3], + dio_out[DioSocProxySocGpi2], + dio_out[DioSocProxySocGpi1], + dio_out[DioSocProxySocGpi0], + dio_out[DioGpioGpio31], + dio_out[DioGpioGpio30], + dio_out[DioGpioGpio29], + dio_out[DioGpioGpio28], + dio_out[DioGpioGpio27], + dio_out[DioGpioGpio26], + dio_out[DioGpioGpio25], + dio_out[DioGpioGpio24], + dio_out[DioGpioGpio23], + dio_out[DioGpioGpio22], + dio_out[DioGpioGpio21], + dio_out[DioGpioGpio20], + dio_out[DioGpioGpio19], + dio_out[DioGpioGpio18], + dio_out[DioGpioGpio17], + dio_out[DioGpioGpio16], + dio_out[DioGpioGpio15], + dio_out[DioGpioGpio14], + dio_out[DioGpioGpio13], + dio_out[DioGpioGpio12], + dio_out[DioGpioGpio11], + dio_out[DioGpioGpio10], + dio_out[DioGpioGpio9], + dio_out[DioGpioGpio8], + dio_out[DioGpioGpio7], + dio_out[DioGpioGpio6], + dio_out[DioGpioGpio5], + dio_out[DioGpioGpio4], + dio_out[DioGpioGpio3], + dio_out[DioGpioGpio2], + dio_out[DioGpioGpio1], + dio_out[DioGpioGpio0], + dio_out[DioI2c0Sda], + dio_out[DioI2c0Scl], + dio_out[DioUart0Tx], + dio_out[DioUart0Rx], + dio_out[DioSpiDeviceTpmCsb], + dio_out[DioSpiDeviceCsb], + dio_out[DioSpiDeviceSck], + dio_out[DioSpiDeviceSd3], + dio_out[DioSpiDeviceSd2], + dio_out[DioSpiDeviceSd1], + dio_out[DioSpiDeviceSd0], + dio_out[DioSpiHost0Csb], + dio_out[DioSpiHost0Sck], + dio_out[DioSpiHost0Sd3], + dio_out[DioSpiHost0Sd2], + dio_out[DioSpiHost0Sd1], + dio_out[DioSpiHost0Sd0], + manual_out_jtag_trst_n, + manual_out_jtag_tdo, + manual_out_jtag_tdi, + manual_out_jtag_tms, + manual_out_jtag_tck, + manual_out_por_n + }), + .dio_oe_i ({ + manual_oe_io_trigger, + manual_oe_io_clkout, + manual_oe_por_button_n, + manual_oe_io_clk, + dio_oe[DioSocProxySocGpo11], + dio_oe[DioSocProxySocGpo10], + dio_oe[DioSocProxySocGpo9], + dio_oe[DioSocProxySocGpo8], + dio_oe[DioSocProxySocGpo7], + dio_oe[DioSocProxySocGpo6], + dio_oe[DioSocProxySocGpo5], + dio_oe[DioSocProxySocGpo4], + dio_oe[DioSocProxySocGpo3], + dio_oe[DioSocProxySocGpo2], + dio_oe[DioSocProxySocGpo1], + dio_oe[DioSocProxySocGpo0], + dio_oe[DioSocProxySocGpi11], + dio_oe[DioSocProxySocGpi10], + dio_oe[DioSocProxySocGpi9], + dio_oe[DioSocProxySocGpi8], + dio_oe[DioSocProxySocGpi7], + dio_oe[DioSocProxySocGpi6], + dio_oe[DioSocProxySocGpi5], + dio_oe[DioSocProxySocGpi4], + dio_oe[DioSocProxySocGpi3], + dio_oe[DioSocProxySocGpi2], + dio_oe[DioSocProxySocGpi1], + dio_oe[DioSocProxySocGpi0], + dio_oe[DioGpioGpio31], + dio_oe[DioGpioGpio30], + dio_oe[DioGpioGpio29], + dio_oe[DioGpioGpio28], + dio_oe[DioGpioGpio27], + dio_oe[DioGpioGpio26], + dio_oe[DioGpioGpio25], + dio_oe[DioGpioGpio24], + dio_oe[DioGpioGpio23], + dio_oe[DioGpioGpio22], + dio_oe[DioGpioGpio21], + dio_oe[DioGpioGpio20], + dio_oe[DioGpioGpio19], + dio_oe[DioGpioGpio18], + dio_oe[DioGpioGpio17], + dio_oe[DioGpioGpio16], + dio_oe[DioGpioGpio15], + dio_oe[DioGpioGpio14], + dio_oe[DioGpioGpio13], + dio_oe[DioGpioGpio12], + dio_oe[DioGpioGpio11], + dio_oe[DioGpioGpio10], + dio_oe[DioGpioGpio9], + dio_oe[DioGpioGpio8], + dio_oe[DioGpioGpio7], + dio_oe[DioGpioGpio6], + dio_oe[DioGpioGpio5], + dio_oe[DioGpioGpio4], + dio_oe[DioGpioGpio3], + dio_oe[DioGpioGpio2], + dio_oe[DioGpioGpio1], + dio_oe[DioGpioGpio0], + dio_oe[DioI2c0Sda], + dio_oe[DioI2c0Scl], + dio_oe[DioUart0Tx], + dio_oe[DioUart0Rx], + dio_oe[DioSpiDeviceTpmCsb], + dio_oe[DioSpiDeviceCsb], + dio_oe[DioSpiDeviceSck], + dio_oe[DioSpiDeviceSd3], + dio_oe[DioSpiDeviceSd2], + dio_oe[DioSpiDeviceSd1], + dio_oe[DioSpiDeviceSd0], + dio_oe[DioSpiHost0Csb], + dio_oe[DioSpiHost0Sck], + dio_oe[DioSpiHost0Sd3], + dio_oe[DioSpiHost0Sd2], + dio_oe[DioSpiHost0Sd1], + dio_oe[DioSpiHost0Sd0], + manual_oe_jtag_trst_n, + manual_oe_jtag_tdo, + manual_oe_jtag_tdi, + manual_oe_jtag_tms, + manual_oe_jtag_tck, + manual_oe_por_n + }), + .dio_attr_i ({ + manual_attr_io_trigger, + manual_attr_io_clkout, + manual_attr_por_button_n, + manual_attr_io_clk, + dio_attr[DioSocProxySocGpo11], + dio_attr[DioSocProxySocGpo10], + dio_attr[DioSocProxySocGpo9], + dio_attr[DioSocProxySocGpo8], + dio_attr[DioSocProxySocGpo7], + dio_attr[DioSocProxySocGpo6], + dio_attr[DioSocProxySocGpo5], + dio_attr[DioSocProxySocGpo4], + dio_attr[DioSocProxySocGpo3], + dio_attr[DioSocProxySocGpo2], + dio_attr[DioSocProxySocGpo1], + dio_attr[DioSocProxySocGpo0], + dio_attr[DioSocProxySocGpi11], + dio_attr[DioSocProxySocGpi10], + dio_attr[DioSocProxySocGpi9], + dio_attr[DioSocProxySocGpi8], + dio_attr[DioSocProxySocGpi7], + dio_attr[DioSocProxySocGpi6], + dio_attr[DioSocProxySocGpi5], + dio_attr[DioSocProxySocGpi4], + dio_attr[DioSocProxySocGpi3], + dio_attr[DioSocProxySocGpi2], + dio_attr[DioSocProxySocGpi1], + dio_attr[DioSocProxySocGpi0], + dio_attr[DioGpioGpio31], + dio_attr[DioGpioGpio30], + dio_attr[DioGpioGpio29], + dio_attr[DioGpioGpio28], + dio_attr[DioGpioGpio27], + dio_attr[DioGpioGpio26], + dio_attr[DioGpioGpio25], + dio_attr[DioGpioGpio24], + dio_attr[DioGpioGpio23], + dio_attr[DioGpioGpio22], + dio_attr[DioGpioGpio21], + dio_attr[DioGpioGpio20], + dio_attr[DioGpioGpio19], + dio_attr[DioGpioGpio18], + dio_attr[DioGpioGpio17], + dio_attr[DioGpioGpio16], + dio_attr[DioGpioGpio15], + dio_attr[DioGpioGpio14], + dio_attr[DioGpioGpio13], + dio_attr[DioGpioGpio12], + dio_attr[DioGpioGpio11], + dio_attr[DioGpioGpio10], + dio_attr[DioGpioGpio9], + dio_attr[DioGpioGpio8], + dio_attr[DioGpioGpio7], + dio_attr[DioGpioGpio6], + dio_attr[DioGpioGpio5], + dio_attr[DioGpioGpio4], + dio_attr[DioGpioGpio3], + dio_attr[DioGpioGpio2], + dio_attr[DioGpioGpio1], + dio_attr[DioGpioGpio0], + dio_attr[DioI2c0Sda], + dio_attr[DioI2c0Scl], + dio_attr[DioUart0Tx], + dio_attr[DioUart0Rx], + dio_attr[DioSpiDeviceTpmCsb], + dio_attr[DioSpiDeviceCsb], + dio_attr[DioSpiDeviceSck], + dio_attr[DioSpiDeviceSd3], + dio_attr[DioSpiDeviceSd2], + dio_attr[DioSpiDeviceSd1], + dio_attr[DioSpiDeviceSd0], + dio_attr[DioSpiHost0Csb], + dio_attr[DioSpiHost0Sck], + dio_attr[DioSpiHost0Sd3], + dio_attr[DioSpiHost0Sd2], + dio_attr[DioSpiHost0Sd1], + dio_attr[DioSpiHost0Sd0], + manual_attr_jtag_trst_n, + manual_attr_jtag_tdo, + manual_attr_jtag_tdi, + manual_attr_jtag_tms, + manual_attr_jtag_tck, + manual_attr_por_n + }), + + .mio_in_o (mio_in[11:0]), + .mio_out_i (mio_out[11:0]), + .mio_oe_i (mio_oe[11:0]), + .mio_attr_i (mio_attr[11:0]), + .mio_in_raw_o (mio_in_raw[11:0]) + ); + + + + + + ////////////////////////////////// + // AST - Common for all targets // + ////////////////////////////////// + + // pwrmgr interface + pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; + pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; + + // assorted ast status + ast_pkg::ast_pwst_t ast_pwst; + + // TLUL interface + tlul_pkg::tl_h2d_t base_ast_bus; + tlul_pkg::tl_d2h_t ast_base_bus; + + // synchronization clocks / rests + clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks; + rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets; + + // external clock + logic ext_clk; + + // monitored clock + logic sck_monitor; + + // observe interface + logic [7:0] otp_obs; + ast_pkg::ast_obs_ctrl_t obs_ctrl; + + // otp power sequence + otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq; + otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h; + + // entropy source interface + // The entropy source pacakge definition should eventually be moved to es + entropy_src_pkg::entropy_src_hw_if_req_t entropy_src_hw_if_req; + entropy_src_pkg::entropy_src_hw_if_rsp_t entropy_src_hw_if_rsp; + + // entropy distribution network + edn_pkg::edn_req_t ast_edn_edn_req; + edn_pkg::edn_rsp_t ast_edn_edn_rsp; + + // alerts interface + ast_pkg::ast_alert_rsp_t ast_alert_rsp; + ast_pkg::ast_alert_req_t ast_alert_req; + + // clock bypass req/ack + prim_mubi_pkg::mubi4_t io_clk_byp_req; + prim_mubi_pkg::mubi4_t io_clk_byp_ack; + prim_mubi_pkg::mubi4_t all_clk_byp_req; + prim_mubi_pkg::mubi4_t all_clk_byp_ack; + prim_mubi_pkg::mubi4_t hi_speed_sel; + prim_mubi_pkg::mubi4_t div_step_down_req; + + // DFT connections + logic scan_en; + lc_ctrl_pkg::lc_tx_t lc_dft_en; + pinmux_pkg::dft_strap_test_req_t dft_strap_test; + + // Jitter enable + prim_mubi_pkg::mubi4_t jen; + + // reset domain connections + import rstmgr_pkg::PowerDomains; + import rstmgr_pkg::DomainAonSel; + import rstmgr_pkg::Domain0Sel; + + // Memory configuration connections + ast_pkg::spm_rm_t ast_ram_1p_cfg; + ast_pkg::spm_rm_t ast_rf_cfg; + ast_pkg::spm_rm_t ast_rom_cfg; + ast_pkg::dpm_rm_t ast_ram_2p_fcfg; + ast_pkg::dpm_rm_t ast_ram_2p_lcfg; + + // conversion from ast structure to memory centric structures + prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg; + assign ram_1p_cfg = '{ + ram_cfg: '{ + cfg_en: ast_ram_1p_cfg.marg_en, + cfg: ast_ram_1p_cfg.marg + }, + rf_cfg: '{ + cfg_en: ast_rf_cfg.marg_en, + cfg: ast_rf_cfg.marg + } + }; + + logic unused_usb_ram_2p_cfg; + assign unused_usb_ram_2p_cfg = ^{ast_ram_2p_fcfg.marg_en_a, + ast_ram_2p_fcfg.marg_a, + ast_ram_2p_fcfg.marg_en_b, + ast_ram_2p_fcfg.marg_b}; + + // this maps as follows: + // assign spi_ram_2p_cfg = {10'h000, ram_2p_cfg_i.a_ram_lcfg, ram_2p_cfg_i.b_ram_lcfg}; + prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg; + assign spi_ram_2p_cfg = '{ + a_ram_lcfg: '{ + cfg_en: ast_ram_2p_lcfg.marg_en_a, + cfg: ast_ram_2p_lcfg.marg_a + }, + b_ram_lcfg: '{ + cfg_en: ast_ram_2p_lcfg.marg_en_b, + cfg: ast_ram_2p_lcfg.marg_b + }, + default: '0 + }; + + prim_rom_pkg::rom_cfg_t rom_cfg; + assign rom_cfg = '{ + cfg_en: ast_rom_cfg.marg_en, + cfg: ast_rom_cfg.marg + }; + + + ////////////////////////////////// + // AST - Custom for targets // + ////////////////////////////////// + + + assign ast_base_pwr.main_pok = ast_pwst.main_pok; + + logic [rstmgr_pkg::PowerDomains-1:0] por_n; + assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok}; + + // TODO: Hook this up when FPGA pads are updated + assign ext_clk = '0; + assign pad2ast = '0; + + logic clk_main, clk_usb_48mhz, clk_aon, rst_n, srst_n; + clkgen_xil7series # ( + .AddClkBuf(0) + ) clkgen ( + .clk_i(manual_in_io_clk), + .rst_ni(manual_in_por_n), + .srst_ni(srst_n), + .clk_main_o(clk_main), + .clk_48MHz_o(clk_usb_48mhz), + .clk_aon_o(clk_aon), + .rst_no(rst_n) + ); + + logic [31:0] fpga_info; + usr_access_xil7series u_info ( + .info_o(fpga_info) + ); + + ast_pkg::clks_osc_byp_t clks_osc_byp; + assign clks_osc_byp = '{ + usb: clk_usb_48mhz, + sys: clk_main, + io: clk_main, + aon: clk_aon + }; + + + prim_mubi_pkg::mubi4_t ast_init_done; + + ast #( + .EntropyStreams(ast_pkg::EntropyStreams), + .AdcChannels(ast_pkg::AdcChannels), + .AdcDataWidth(ast_pkg::AdcDataWidth), + .UsbCalibWidth(ast_pkg::UsbCalibWidth), + .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth), + .Pad2AstInWidth(ast_pkg::Pad2AstInWidth) + ) u_ast ( + // external POR + .por_ni ( rst_n ), + + // USB IO Pull-up Calibration Setting + .usb_io_pu_cal_o ( ), + + // clocks' oschillator bypass for FPGA + .clk_osc_byp_i ( clks_osc_byp ), + + // adc + .adc_a0_ai ( '0 ), + .adc_a1_ai ( '0 ), + + // Direct short to PAD + .ast2pad_t0_ao ( ), + .ast2pad_t1_ao ( ), + + // clocks and resets supplied for detection + .sns_clks_i ( clkmgr_aon_clocks ), + .sns_rsts_i ( rstmgr_aon_resets ), + .sns_spi_ext_clk_i ( sck_monitor ), + // tlul + .tl_i ( base_ast_bus ), + .tl_o ( ast_base_bus ), + // init done indication + .ast_init_done_o ( ast_init_done ), + // buffered clocks & resets + .clk_ast_tlul_i (clkmgr_aon_clocks.clk_io_div4_infra), + .clk_ast_adc_i (clkmgr_aon_clocks.clk_aon_peri), + .clk_ast_alert_i (clkmgr_aon_clocks.clk_io_div4_secure), + .clk_ast_es_i (clkmgr_aon_clocks.clk_main_secure), + .clk_ast_rng_i (clkmgr_aon_clocks.clk_main_secure), + .clk_ast_usb_i (clkmgr_aon_clocks.clk_usb_peri), + .rst_ast_tlul_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_ast_adc_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]), + .rst_ast_alert_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_ast_es_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_ast_rng_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_ast_usb_ni (rstmgr_aon_resets.rst_por_usb_n[rstmgr_pkg::Domain0Sel]), + .clk_ast_ext_i ( ext_clk ), + + // pok test for FPGA + .vcc_supp_i ( 1'b1 ), + .vcaon_supp_i ( 1'b1 ), + .vcmain_supp_i ( 1'b1 ), + .vioa_supp_i ( 1'b1 ), + .viob_supp_i ( 1'b1 ), + // pok + .ast_pwst_o ( ast_pwst ), + .ast_pwst_h_o ( ), + // main regulator + .main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ), + .main_pd_ni ( base_ast_pwr.main_pd_n ), + // pdm control (flash)/otp + .flash_power_down_h_o ( ), + .flash_power_ready_h_o ( ), + .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ), + .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ), + // system source clock + .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ), + // need to add function in clkmgr + .clk_src_sys_jen_i ( jen ), + .clk_src_sys_o ( ast_base_clks.clk_sys ), + .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ), + // aon source clock + .clk_src_aon_o ( ast_base_clks.clk_aon ), + .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ), + // io source clock + .clk_src_io_en_i ( base_ast_pwr.io_clk_en ), + .clk_src_io_o ( ast_base_clks.clk_io ), + .clk_src_io_val_o ( ast_base_pwr.io_clk_val ), + .clk_src_io_48m_o ( div_step_down_req ), + // usb source clock + .usb_ref_pulse_i ( '0 ), + .usb_ref_val_i ( '0 ), + .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ), + .clk_src_usb_o ( ast_base_clks.clk_usb ), + .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ), + // entropy_src + .es_req_i ( entropy_src_hw_if_req ), + .es_rsp_o ( entropy_src_hw_if_rsp ), + // adc + .adc_pd_i ( '0 ), + .adc_chnsel_i ( '0 ), + .adc_d_o ( ), + .adc_d_val_o ( ), + // entropy + .entropy_rsp_i ( ast_edn_edn_rsp ), + .entropy_req_o ( ast_edn_edn_req ), + // alerts + .alert_rsp_i ( ast_alert_rsp ), + .alert_req_o ( ast_alert_req ), + // dft + .dft_strap_test_i ( dft_strap_test ), + .lc_dft_en_i ( lc_dft_en ), + .fla_obs_i ( '0 ), + .usb_obs_i ( '0 ), + .otp_obs_i ( otp_obs ), + .otm_obs_i ( '0 ), + .obs_ctrl_o ( obs_ctrl ), + // pinmux related + .padmux2ast_i ( '0 ), + .ast2padmux_o ( ), + .ext_freq_is_96m_i ( hi_speed_sel ), + .all_clk_byp_req_i ( all_clk_byp_req ), + .all_clk_byp_ack_o ( all_clk_byp_ack ), + .io_clk_byp_req_i ( io_clk_byp_req ), + .io_clk_byp_ack_o ( io_clk_byp_ack ), + .flash_bist_en_o ( ), + // Memory configuration connections + .dpram_rmf_o ( ast_ram_2p_fcfg ), + .dpram_rml_o ( ast_ram_2p_lcfg ), + .spram_rm_o ( ast_ram_1p_cfg ), + .sprgf_rm_o ( ast_rf_cfg ), + .sprom_rm_o ( ast_rom_cfg ), + // scan + .dft_scan_md_o ( scanmode ), + .scan_shift_en_o ( scan_en ), + .scan_reset_no ( scan_rst_n ) + ); + + ////////////////// + // TAP Instance // + ////////////////// + + tlul_pkg::tl_h2d_t dmi_h2d; + tlul_pkg::tl_d2h_t dmi_d2h; + jtag_pkg::jtag_req_t jtag_req; + jtag_pkg::jtag_rsp_t jtag_rsp; + + assign jtag_req.tck = manual_in_jtag_tck; + assign jtag_req.tms = manual_in_jtag_tms; + assign jtag_req.trst_n = manual_in_jtag_trst_n; + assign jtag_req.tdi = manual_in_jtag_tdi; + + assign manual_out_jtag_tck = '0; + assign manual_out_jtag_tms = '0; + assign manual_out_jtag_trst_n = '0; + assign manual_out_jtag_tdi = '0; + assign manual_oe_jtag_tck = '0; + assign manual_oe_jtag_tms = '0; + assign manual_oe_jtag_trst_n = '0; + assign manual_oe_jtag_tdi = '0; + assign manual_attr_jtag_tck = '0; + assign manual_attr_jtag_tms = '0; + assign manual_attr_jtag_trst_n = '0; + assign manual_attr_jtag_tdi = '0; + + assign manual_out_jtag_tdo = jtag_rsp.tdo; + assign manual_oe_jtag_tdo = jtag_rsp.tdo_oe; + assign manual_attr_jtag_tdo = '0; + + logic unused_manual_jtag_sigs; + assign unused_manual_jtag_sigs = ^{ + manual_in_jtag_tdo + }; + + tlul_jtag_dtm #( + .IdcodeValue(jtag_id_pkg::LC_DM_COMBINED_JTAG_IDCODE), + // Notes: + // - one RV_DM instance uses 9bits + // - our crossbar tooling expects individual IPs to be spaced apart by 12bits at the moment + // - the DMI address shifted through jtag is a word address and hence 2bits smaller than this + // - setting this to 18bits effectively gives us 2^6 = 64 addressable 12bit ranges + .NumDmiByteAbits(18) + ) u_tlul_jtag_dtm ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]), + .jtag_i (jtag_req), + .jtag_o (jtag_rsp), + .scan_rst_ni(scan_rst_n), + .scanmode_i (scanmode), + .tl_h2d_o (dmi_h2d), + .tl_d2h_i (dmi_d2h) + ); + + //////////////// + // CTN M-to-1 // + //////////////// + + tlul_pkg::tl_h2d_t ctn_tl_h2d[2]; + tlul_pkg::tl_d2h_t ctn_tl_d2h[2]; + + tlul_pkg::tl_h2d_t ctn_sm1_to_s1n_tl_h2d; + tlul_pkg::tl_d2h_t ctn_sm1_to_s1n_tl_d2h; + + tlul_socket_m1 #( + .M (2), + .HReqPass ({2{1'b1}}), + .HRspPass ({2{1'b1}}), + .HReqDepth ({2{4'd0}}), + .HRspDepth ({2{4'd0}}), + .DReqPass (1'b1), + .DRspPass (1'b1), + .DReqDepth (4'd0), + .DRspDepth (4'd0) + ) u_ctn_sm1 ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_h_i (ctn_tl_h2d), + .tl_h_o (ctn_tl_d2h), + .tl_d_o (ctn_sm1_to_s1n_tl_h2d), + .tl_d_i (ctn_sm1_to_s1n_tl_d2h) + ); + + //////////////////////////////////////////// + // CTN Address decoding and SRAM Instance // + //////////////////////////////////////////// + + localparam int CtnSramDw = top_pkg::TL_DW + tlul_pkg::DataIntgWidth; + + tlul_pkg::tl_h2d_t ctn_s1n_tl_h2d[1]; + tlul_pkg::tl_d2h_t ctn_s1n_tl_d2h[1]; + + // Steering signal for address decoding. + logic [0:0] ctn_dev_sel_s1n; + + logic sram_req, sram_we, sram_rvalid; + logic [top_pkg::CtnSramAw-1:0] sram_addr; + logic [CtnSramDw-1:0] sram_wdata, sram_wmask, sram_rdata; + + // Steering of requests. + // Addresses leaving the RoT through the CTN port are mapped to an internal 1G address space of + // 0x4000_0000 - 0x8000_0000. However, the CTN RAM only covers a 1MB region inside that space, + // and hence additional decoding and steering logic is needed here. + // TODO: this should in the future be replaced by an automatically generated crossbar. + always_comb begin + // Default steering to generate error response if address is not within the range + ctn_dev_sel_s1n = 1'b1; + // Steering to CTN SRAM. + if ((ctn_sm1_to_s1n_tl_h2d.a_address & ~(TOP_DARJEELING_RAM_CTN_SIZE_BYTES-1)) == + TOP_DARJEELING_RAM_CTN_BASE_ADDR) begin + ctn_dev_sel_s1n = 1'd0; + end + end + + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (8'h0), + .DRspDepth (8'h0), + .N (1) + ) u_ctn_s1n ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_h_i (ctn_sm1_to_s1n_tl_h2d), + .tl_h_o (ctn_sm1_to_s1n_tl_d2h), + .tl_d_o (ctn_s1n_tl_h2d), + .tl_d_i (ctn_s1n_tl_d2h), + .dev_select_i (ctn_dev_sel_s1n) + ); + + tlul_adapter_sram #( + .SramAw(top_pkg::CtnSramAw), + .SramDw(CtnSramDw - tlul_pkg::DataIntgWidth), + .Outstanding(2), + .ByteAccess(1), + .CmdIntgCheck(1), + .EnableRspIntgGen(1), + .EnableDataIntgGen(0), + .EnableDataIntgPt(1), + .SecFifoPtr (0) + ) u_tlul_adapter_sram_ctn ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_i (ctn_s1n_tl_h2d[0]), + .tl_o (ctn_s1n_tl_d2h[0]), + // Ifetch is explicitly allowed + .en_ifetch_i (prim_mubi_pkg::MuBi4True), + .req_o (sram_req), + .req_type_o (), + // SRAM can always accept a request. + .gnt_i (1'b1), + .we_o (sram_we), + .addr_o (sram_addr), + .wdata_o (sram_wdata), + .wmask_o (sram_wmask), + .intg_error_o(), + .rdata_i (sram_rdata), + .rvalid_i (sram_rvalid), + .rerror_i ('0) + ); + + prim_ram_1p_adv #( + .Depth(top_pkg::CtnSramDepth), + .Width(CtnSramDw), + .DataBitsPerMask(CtnSramDw), + .EnableECC(0), + .EnableParity(0), + .EnableInputPipeline(1), + .EnableOutputPipeline(1) + ) u_prim_ram_1p_adv_ctn ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .req_i (sram_req), + .write_i (sram_we), + .addr_i (sram_addr), + .wdata_i (sram_wdata), + .wmask_i (sram_wmask), + .rdata_o (sram_rdata), + .rvalid_o (sram_rvalid), + // No error detection is enabled inside SRAM. + // Bus ECC is checked at the consumer side. + .rerror_o (), + .cfg_i (ram_1p_cfg) + ); + + + + ////////////////// + // PLL for FPGA // + ////////////////// + + assign manual_attr_io_clk = '0; + assign manual_out_io_clk = 1'b0; + assign manual_oe_io_clk = 1'b0; + assign manual_attr_por_n = '0; + assign manual_out_por_n = 1'b0; + assign manual_oe_por_n = 1'b0; + assign manual_attr_por_button_n = '0; + assign manual_out_por_button_n = 1'b0; + assign manual_oe_por_button_n = 1'b0; + + assign srst_n = manual_in_por_button_n; + + + + ////////////////////// + // Top-level design // + ////////////////////// + + // the rst_ni pin only goes to AST + // the rest of the logic generates reset based on the 'pok' signal. + // for verilator purposes, make these two the same. + prim_mubi_pkg::mubi4_t lc_clk_bypass; // TODO Tim + +// TODO: align this with ASIC version to minimize the duplication. +// Also need to add AST simulation and FPGA emulation models for things like entropy source - +// otherwise Verilator / FPGA will hang. + top_darjeeling #( + .SecAesMasking(1'b1), + .SecAesSBoxImpl(aes_pkg::SBoxImplDom), + .SecAesStartTriggerDelay(320), + .SecAesAllowForcingMasks(1'b1), + .KmacEnMasking(0), + .KmacSwKeyMasked(1), + .SecKmacCmdDelay(320), + .SecKmacIdleAcceptSwMsg(1'b1), + .KeymgrDpeKmacEnMasking(0), + .CsrngSBoxImpl(aes_pkg::SBoxImplLut), + .OtbnRegFile(otbn_pkg::RegFileFPGA), + .SecOtbnMuteUrnd(1'b1), + .SecOtbnSkipUrndReseedAtStart(1'b1), + .OtpCtrlMemInitFile(OtpCtrlMemInitFile), + .RvCoreIbexPipeLine(1), + .SramCtrlRetAonInstrExec(0), + // TODO(opentitan-integrated/issues/251): + // Enable hashing below once the build infrastructure can + // load scrambled images on FPGA platforms. The DV can + // already partially handle it by initializing the 2nd ROM + // with random data via the backdoor loading interface - it + // can't load "real" SW images yet since that requires + // additional build infrastructure. + .SecRomCtrl1DisableScrambling(1), + .RomCtrl0BootRomInitFile(BootRomInitFile), + .RvCoreIbexRegFile(ibex_pkg::RegFileFPGA), + .RvCoreIbexSecureIbex(0), + .SramCtrlMainInstrExec(1), + .PinmuxAonTargetCfg(PinmuxTargetCfg) + ) top_darjeeling ( + .por_n_i ( por_n ), + .clk_main_i ( ast_base_clks.clk_sys ), + .clk_io_i ( ast_base_clks.clk_io ), + .clk_usb_i ( ast_base_clks.clk_usb ), + .clk_aon_i ( ast_base_clks.clk_aon ), + .clks_ast_o ( clkmgr_aon_clocks ), + .clk_main_jitter_en_o ( jen ), + .rsts_ast_o ( rstmgr_aon_resets ), + .sck_monitor_o ( sck_monitor ), + .pwrmgr_ast_req_o ( base_ast_pwr ), + .pwrmgr_ast_rsp_i ( ast_base_pwr ), + .ast_edn_req_i ( ast_edn_edn_req ), + .ast_edn_rsp_o ( ast_edn_edn_rsp ), + .obs_ctrl_i ( obs_ctrl ), + .io_clk_byp_req_o ( io_clk_byp_req ), + .io_clk_byp_ack_i ( io_clk_byp_ack ), + .all_clk_byp_req_o ( all_clk_byp_req ), + .all_clk_byp_ack_i ( all_clk_byp_ack ), + .hi_speed_sel_o ( hi_speed_sel ), + .div_step_down_req_i ( div_step_down_req ), + .fpga_info_i ( fpga_info ), + .ast_tl_req_o ( base_ast_bus ), + .ast_tl_rsp_i ( ast_base_bus ), + .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ), + .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ), + .otp_obs_o ( otp_obs ), + .sensor_ctrl_ast_alert_req_i ( ast_alert_req ), + .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ), + .sensor_ctrl_ast_status_i ( ast_pwst.io_pok ), + .ctn_tl_h2d_o ( ctn_tl_h2d[0] ), + .ctn_tl_d2h_i ( ctn_tl_d2h[0] ), + .soc_gpi_async_o ( ), + .soc_gpo_async_i ( '0 ), + .dma_sys_req_o ( ), + .dma_sys_rsp_i ( '0 ), + .dma_ctn_tl_h2d_o ( ctn_tl_h2d[1] ), + .dma_ctn_tl_d2h_i ( ctn_tl_d2h[1] ), + .entropy_src_hw_if_req_o ( entropy_src_hw_if_req ), + .entropy_src_hw_if_rsp_i ( entropy_src_hw_if_rsp ), + .calib_rdy_i ( ast_init_done ), + .ast_init_done_i ( ast_init_done ), + + // DMI TL-UL + .dbg_tl_req_i ( dmi_h2d ), + .dbg_tl_rsp_o ( dmi_d2h ), + // Quasi-static word address for next_dm register value. + .rv_dm_next_dm_addr_i ( '0 ), + // Multiplexed I/O + .mio_in_i ( mio_in ), + .mio_out_o ( mio_out ), + .mio_oe_o ( mio_oe ), + + // Dedicated I/O + .dio_in_i ( dio_in ), + .dio_out_o ( dio_out ), + .dio_oe_o ( dio_oe ), + + // Pad attributes + .mio_attr_o ( mio_attr ), + .dio_attr_o ( dio_attr ), + + // Memory attributes + .ram_1p_cfg_i ( '0 ), + .spi_ram_2p_cfg_i( '0 ), + .rom_cfg_i ( '0 ), + + // DFT signals + .ast_lc_dft_en_o ( lc_dft_en ), + .ast_lc_hw_debug_en_o ( ), + // DFT signals + .dft_hold_tap_sel_i ( '0 ), + .scan_rst_ni ( 1'b1 ), + .scan_en_i ( 1'b0 ), + .scanmode_i ( prim_mubi_pkg::MuBi4False ) + ); + + + ///////////////////////////////////////////////////// + // ChipWhisperer CW310/305 Capture Board Interface // + ///////////////////////////////////////////////////// + // This is used to interface OpenTitan as a target with a capture board trough the ChipWhisperer + // 20-pin connector. This is used for SCA/FI experiments only. + + logic unused_inputs; + assign unused_inputs = manual_in_io_clkout ^ manual_in_io_trigger; + + // Synchronous clock output to capture board. + assign manual_out_io_clkout = manual_in_io_clk; + assign manual_oe_io_clkout = 1'b1; + + // Capture trigger. + // We use the clkmgr_aon_idle signal of the IP of interest to form a precise capture trigger. + // GPIO[11:10] is used for selecting the IP of interest. The encoding is as follows (see + // hint_names_e enum in clkmgr_pkg.sv for details). + // + // IP - GPIO[11:10] - Index for clkmgr_aon_idle + // ------------------------------------------------------------- + // AES - 00 - 0 + // HMAC - 01 - 1 - not implemented on CW305 + // KMAC - 10 - 2 - not implemented on CW305 + // OTBN - 11 - 3 - not implemented on CW305 + // + // GPIO9 is used for gating the selected capture trigger in software. Alternatively, GPIO8 + // can be used to implement a less precise but fully software-controlled capture trigger + // similar to what can be done on ASIC. + // + // Note that on the CW305, GPIO[9,8] are connected to LED[5(Green),7(Red)]. + + prim_mubi_pkg::mubi4_t clk_trans_idle, manual_in_io_clk_idle; + + clkmgr_pkg::hint_names_e trigger_sel; + always_comb begin : trigger_sel_mux + unique case ({mio_out[MioOutGpioGpio11], mio_out[MioOutGpioGpio10]}) + 2'b00: trigger_sel = clkmgr_pkg::HintMainAes; + 2'b01: trigger_sel = clkmgr_pkg::HintMainHmac; + 2'b10: trigger_sel = clkmgr_pkg::HintMainKmac; + 2'b11: trigger_sel = clkmgr_pkg::HintMainOtbn; + default: trigger_sel = clkmgr_pkg::HintMainAes; + endcase; + end + assign clk_trans_idle = top_darjeeling.clkmgr_aon_idle[trigger_sel]; + + logic clk_io_div4_trigger_hw_en, manual_in_io_clk_trigger_hw_en; + logic clk_io_div4_trigger_hw_oe, manual_in_io_clk_trigger_hw_oe; + logic clk_io_div4_trigger_sw_en, manual_in_io_clk_trigger_sw_en; + logic clk_io_div4_trigger_sw_oe, manual_in_io_clk_trigger_sw_oe; + assign clk_io_div4_trigger_hw_en = mio_out[MioOutGpioGpio9]; + assign clk_io_div4_trigger_hw_oe = mio_oe[MioOutGpioGpio9]; + assign clk_io_div4_trigger_sw_en = mio_out[MioOutGpioGpio8]; + assign clk_io_div4_trigger_sw_oe = mio_oe[MioOutGpioGpio8]; + + // Synchronize signals to manual_in_io_clk. + prim_flop_2sync #( + .Width ($bits(clk_trans_idle) + 4) + ) u_sync_trigger ( + .clk_i (manual_in_io_clk), + .rst_ni(manual_in_por_n), + .d_i ({clk_trans_idle, + clk_io_div4_trigger_hw_en, + clk_io_div4_trigger_hw_oe, + clk_io_div4_trigger_sw_en, + clk_io_div4_trigger_sw_oe}), + .q_o ({manual_in_io_clk_idle, + manual_in_io_clk_trigger_hw_en, + manual_in_io_clk_trigger_hw_oe, + manual_in_io_clk_trigger_sw_en, + manual_in_io_clk_trigger_sw_oe}) + ); + + // Generate the actual trigger signal as trigger_sw OR trigger_hw. + assign manual_attr_io_trigger = '0; + assign manual_oe_io_trigger = + manual_in_io_clk_trigger_sw_oe | manual_in_io_clk_trigger_hw_oe; + assign manual_out_io_trigger = + manual_in_io_clk_trigger_sw_en | (manual_in_io_clk_trigger_hw_en & + prim_mubi_pkg::mubi4_test_false_strict(manual_in_io_clk_idle)); + +endmodule : chip_darjeeling_cw310 diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv new file mode 100644 index 0000000000000..e34c76f777023 --- /dev/null +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv @@ -0,0 +1,3225 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \ +// -o hw/top_darjeeling/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + +`include "prim_assert.sv" + +module top_darjeeling #( + // Manually defined parameters + + // Auto-inferred parameters + // parameters for uart0 + // parameters for gpio + parameter bit GpioGpioAsyncOn = 1, + parameter bit GpioGpioAsHwStrapsEn = 1, + // parameters for spi_device + parameter spi_device_pkg::sram_type_e SpiDeviceSramType = spi_device_pkg::SramType1r1w, + // parameters for i2c0 + parameter int I2c0InputDelayCycles = 0, + // parameters for rv_timer + // parameters for otp_ctrl + parameter OtpCtrlMemInitFile = "", + // parameters for lc_ctrl + parameter bit SecLcCtrlVolatileRawUnlockEn = top_pkg::SecVolatileRawUnlockEn, + parameter bit LcCtrlUseDmiInterface = 1, + parameter logic [15:0] LcCtrlSiliconCreatorId = 16'h 4002, + parameter logic [15:0] LcCtrlProductId = 16'h 4000, + parameter logic [7:0] LcCtrlRevisionId = 8'h 01, + parameter logic [31:0] LcCtrlIdcodeValue = 32'h00000001, + // parameters for alert_handler + // parameters for spi_host0 + // parameters for pwrmgr_aon + // parameters for rstmgr_aon + parameter bit SecRstmgrAonCheck = 1'b1, + parameter int SecRstmgrAonMaxSyncDelay = 2, + // parameters for clkmgr_aon + // parameters for pinmux_aon + parameter bit SecPinmuxAonVolatileRawUnlockEn = top_pkg::SecVolatileRawUnlockEn, + parameter pinmux_pkg::target_cfg_t PinmuxAonTargetCfg = pinmux_pkg::DefaultTargetCfg, + // parameters for aon_timer_aon + // parameters for sensor_ctrl + // parameters for soc_proxy + // parameters for sram_ctrl_ret_aon + parameter bit SramCtrlRetAonInstrExec = 0, + parameter int SramCtrlRetAonNumPrinceRoundsHalf = 3, + // parameters for rv_dm + parameter logic [31:0] RvDmIdcodeValue = 32'h 0000_0001, + parameter bit RvDmUseDmiInterface = 1, + parameter bit SecRvDmVolatileRawUnlockEn = top_pkg::SecVolatileRawUnlockEn, + // parameters for rv_plic + // parameters for aes + parameter bit SecAesMasking = 1, + parameter aes_pkg::sbox_impl_e SecAesSBoxImpl = aes_pkg::SBoxImplDom, + parameter int unsigned SecAesStartTriggerDelay = 0, + parameter bit SecAesAllowForcingMasks = 1'b0, + parameter bit SecAesSkipPRNGReseeding = 1'b0, + // parameters for hmac + // parameters for kmac + parameter bit KmacEnMasking = 1, + parameter bit KmacSwKeyMasked = 0, + parameter int SecKmacCmdDelay = 0, + parameter bit SecKmacIdleAcceptSwMsg = 0, + parameter int KmacNumAppIntf = 4, + parameter kmac_pkg::app_config_t KmacAppCfg[KmacNumAppIntf] = + '{kmac_pkg::AppCfgKeyMgr, kmac_pkg::AppCfgLcCtrl, kmac_pkg::AppCfgRomCtrl, kmac_pkg::AppCfgRomCtrl}, + // parameters for otbn + parameter bit OtbnStub = 0, + parameter otbn_pkg::regfile_e OtbnRegFile = otbn_pkg::RegFileFF, + parameter bit SecOtbnMuteUrnd = 0, + parameter bit SecOtbnSkipUrndReseedAtStart = 0, + // parameters for keymgr_dpe + parameter bit KeymgrDpeKmacEnMasking = 1, + // parameters for csrng + parameter aes_pkg::sbox_impl_e CsrngSBoxImpl = aes_pkg::SBoxImplCanright, + // parameters for edn0 + // parameters for edn1 + // parameters for sram_ctrl_main + parameter bit SramCtrlMainInstrExec = 1, + parameter int SramCtrlMainNumPrinceRoundsHalf = 3, + // parameters for sram_ctrl_mbox + parameter bit SramCtrlMboxInstrExec = 0, + parameter int SramCtrlMboxNumPrinceRoundsHalf = 3, + // parameters for rom_ctrl0 + parameter RomCtrl0BootRomInitFile = "", + parameter bit SecRomCtrl0DisableScrambling = 1'b0, + // parameters for rom_ctrl1 + parameter RomCtrl1BootRomInitFile = "", + parameter bit SecRomCtrl1DisableScrambling = 1'b0, + // parameters for dma + parameter bit DmaEnableDataIntgGen = 1'b1, + parameter bit DmaEnableRspDataIntgCheck = 1'b1, + parameter logic [tlul_pkg::RsvdWidth-1:0] DmaTlUserRsvd = '0, + parameter logic [dma_pkg::SYS_RACL_WIDTH-1:0] DmaSysRacl = '0, + parameter int unsigned DmaOtAgentId = 0, + // parameters for mbx0 + // parameters for mbx1 + // parameters for mbx2 + // parameters for mbx3 + // parameters for mbx4 + // parameters for mbx5 + // parameters for mbx6 + // parameters for mbx_jtag + // parameters for mbx_pcie0 + // parameters for mbx_pcie1 + // parameters for rv_core_ibex + parameter bit RvCoreIbexPMPEnable = 1, + parameter int unsigned RvCoreIbexPMPGranularity = 0, + parameter int unsigned RvCoreIbexPMPNumRegions = 16, + parameter int unsigned RvCoreIbexMHPMCounterNum = 10, + parameter int unsigned RvCoreIbexMHPMCounterWidth = 32, + parameter ibex_pkg::pmp_cfg_t RvCoreIbexPMPRstCfg[16] = ibex_pkg::PmpCfgRst, + parameter logic [33:0] RvCoreIbexPMPRstAddr[16] = ibex_pkg::PmpAddrRst, + parameter ibex_pkg::pmp_mseccfg_t RvCoreIbexPMPRstMsecCfg = ibex_pkg::PmpMseccfgRst, + parameter bit RvCoreIbexRV32E = 0, + parameter ibex_pkg::rv32m_e RvCoreIbexRV32M = ibex_pkg::RV32MSingleCycle, + parameter ibex_pkg::rv32b_e RvCoreIbexRV32B = ibex_pkg::RV32BOTEarlGrey, + parameter ibex_pkg::regfile_e RvCoreIbexRegFile = ibex_pkg::RegFileFF, + parameter bit RvCoreIbexBranchTargetALU = 1, + parameter bit RvCoreIbexWritebackStage = 1, + parameter bit RvCoreIbexICache = 1, + parameter bit RvCoreIbexICacheECC = 1, + parameter bit RvCoreIbexICacheScramble = 1, + parameter bit RvCoreIbexBranchPredictor = 0, + parameter bit RvCoreIbexDbgTriggerEn = 1, + parameter int RvCoreIbexDbgHwBreakNum = 4, + parameter bit RvCoreIbexSecureIbex = 1, + parameter int unsigned RvCoreIbexDmHaltAddr = + tl_main_pkg::ADDR_SPACE_RV_DM__MEM + dm::HaltAddress[31:0], + parameter int unsigned RvCoreIbexDmExceptionAddr = + tl_main_pkg::ADDR_SPACE_RV_DM__MEM + dm::ExceptionAddress[31:0], + parameter bit RvCoreIbexPipeLine = 0 +) ( + // Multiplexed I/O + input [11:0] mio_in_i, + output logic [11:0] mio_out_o, + output logic [11:0] mio_oe_o, + // Dedicated I/O + input [72:0] dio_in_i, + output logic [72:0] dio_out_o, + output logic [72:0] dio_oe_o, + + // pad attributes to padring + output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr_o, + output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr_o, + + + // Inter-module Signal External type + input edn_pkg::edn_req_t ast_edn_req_i, + output edn_pkg::edn_rsp_t ast_edn_rsp_o, + output lc_ctrl_pkg::lc_tx_t ast_lc_dft_en_o, + output lc_ctrl_pkg::lc_tx_t ast_lc_hw_debug_en_o, + input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, + input prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg_i, + input prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg_i, + input prim_rom_pkg::rom_cfg_t rom_cfg_i, + output prim_mubi_pkg::mubi4_t clk_main_jitter_en_o, + output prim_mubi_pkg::mubi4_t io_clk_byp_req_o, + input prim_mubi_pkg::mubi4_t io_clk_byp_ack_i, + output prim_mubi_pkg::mubi4_t all_clk_byp_req_o, + input prim_mubi_pkg::mubi4_t all_clk_byp_ack_i, + output prim_mubi_pkg::mubi4_t hi_speed_sel_o, + input prim_mubi_pkg::mubi4_t div_step_down_req_i, + input prim_mubi_pkg::mubi4_t calib_rdy_i, + output entropy_src_pkg::entropy_src_hw_if_req_t entropy_src_hw_if_req_o, + input entropy_src_pkg::entropy_src_hw_if_rsp_t entropy_src_hw_if_rsp_i, + output dma_pkg::sys_req_t dma_sys_req_o, + input dma_pkg::sys_rsp_t dma_sys_rsp_i, + output tlul_pkg::tl_h2d_t dma_ctn_tl_h2d_o, + input tlul_pkg::tl_d2h_t dma_ctn_tl_d2h_i, + input tlul_pkg::tl_h2d_t mbx_tl_req_i, + output tlul_pkg::tl_d2h_t mbx_tl_rsp_o, + output logic mbx0_doe_intr_o, + output logic mbx0_doe_intr_en_o, + output logic mbx0_doe_intr_support_o, + output logic mbx0_doe_async_msg_support_o, + output logic mbx1_doe_intr_o, + output logic mbx1_doe_intr_en_o, + output logic mbx1_doe_intr_support_o, + output logic mbx1_doe_async_msg_support_o, + output logic mbx2_doe_intr_o, + output logic mbx2_doe_intr_en_o, + output logic mbx2_doe_intr_support_o, + output logic mbx2_doe_async_msg_support_o, + output logic mbx3_doe_intr_o, + output logic mbx3_doe_intr_en_o, + output logic mbx3_doe_intr_support_o, + output logic mbx3_doe_async_msg_support_o, + output logic mbx4_doe_intr_o, + output logic mbx4_doe_intr_en_o, + output logic mbx4_doe_intr_support_o, + output logic mbx4_doe_async_msg_support_o, + output logic mbx5_doe_intr_o, + output logic mbx5_doe_intr_en_o, + output logic mbx5_doe_intr_support_o, + output logic mbx5_doe_async_msg_support_o, + output logic mbx6_doe_intr_o, + output logic mbx6_doe_intr_en_o, + output logic mbx6_doe_intr_support_o, + output logic mbx6_doe_async_msg_support_o, + output logic mbx_jtag_doe_intr_o, + output logic mbx_jtag_doe_intr_en_o, + output logic mbx_jtag_doe_intr_support_o, + output logic mbx_jtag_doe_async_msg_support_o, + output logic mbx_pcie0_doe_intr_o, + output logic mbx_pcie0_doe_intr_en_o, + output logic mbx_pcie0_doe_intr_support_o, + output logic mbx_pcie0_doe_async_msg_support_o, + output logic mbx_pcie1_doe_intr_o, + output logic mbx_pcie1_doe_intr_en_o, + output logic mbx_pcie1_doe_intr_support_o, + output logic mbx_pcie1_doe_async_msg_support_o, + input tlul_pkg::tl_h2d_t dbg_tl_req_i, + output tlul_pkg::tl_d2h_t dbg_tl_rsp_o, + input rv_dm_pkg::next_dm_addr_t rv_dm_next_dm_addr_i, + output tlul_pkg::tl_h2d_t ast_tl_req_o, + input tlul_pkg::tl_d2h_t ast_tl_rsp_i, + output pinmux_pkg::dft_strap_test_req_t dft_strap_test_o, + input logic dft_hold_tap_sel_i, + output pwrmgr_pkg::pwr_ast_req_t pwrmgr_ast_req_o, + input pwrmgr_pkg::pwr_ast_rsp_t pwrmgr_ast_rsp_i, + output otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq_o, + input otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h_i, + inout otp_ext_voltage_h_io, + output logic [7:0] otp_obs_o, + input logic [1:0] por_n_i, + input logic [31:0] fpga_info_i, + input ast_pkg::ast_alert_req_t sensor_ctrl_ast_alert_req_i, + output ast_pkg::ast_alert_rsp_t sensor_ctrl_ast_alert_rsp_o, + input ast_pkg::ast_status_t sensor_ctrl_ast_status_i, + input prim_mubi_pkg::mubi4_t ast_init_done_i, + output tlul_pkg::tl_h2d_t ctn_tl_h2d_o, + input tlul_pkg::tl_d2h_t ctn_tl_d2h_i, + input soc_proxy_pkg::soc_alert_req_t [23:0] soc_fatal_alert_req_i, + output soc_proxy_pkg::soc_alert_rsp_t [23:0] soc_fatal_alert_rsp_o, + input soc_proxy_pkg::soc_alert_req_t [3:0] soc_recov_alert_req_i, + output soc_proxy_pkg::soc_alert_rsp_t [3:0] soc_recov_alert_rsp_o, + input logic soc_wkup_async_i, + input logic soc_rst_req_async_i, + input logic [31:0] soc_intr_async_i, + input logic [7:0] soc_lsio_trigger_i, + output logic [15:0] soc_gpi_async_o, + input logic [15:0] soc_gpo_async_i, + output logic sck_monitor_o, + + + // All externally supplied clocks + input clk_main_i, + input clk_io_i, + input clk_usb_i, + input clk_aon_i, + + // All clocks forwarded to ast + output clkmgr_pkg::clkmgr_out_t clks_ast_o, + output rstmgr_pkg::rstmgr_out_t rsts_ast_o, + + input scan_rst_ni, // reset used for test mode + input scan_en_i, + input prim_mubi_pkg::mubi4_t scanmode_i // lc_ctrl_pkg::On for Scan +); + + import tlul_pkg::*; + import top_pkg::*; + import tl_main_pkg::*; + import top_darjeeling_pkg::*; + // Compile-time random constants + import top_darjeeling_rnd_cnst_pkg::*; + + // Local Parameters + + // Signals + logic [3:0] mio_p2d; + logic [4:0] mio_d2p; + logic [4:0] mio_en_d2p; + logic [72:0] dio_p2d; + logic [72:0] dio_d2p; + logic [72:0] dio_en_d2p; + // uart0 + logic cio_uart0_rx_p2d; + logic cio_uart0_tx_d2p; + logic cio_uart0_tx_en_d2p; + // gpio + logic [31:0] cio_gpio_gpio_p2d; + logic [31:0] cio_gpio_gpio_d2p; + logic [31:0] cio_gpio_gpio_en_d2p; + // spi_device + logic cio_spi_device_sck_p2d; + logic cio_spi_device_csb_p2d; + logic cio_spi_device_tpm_csb_p2d; + logic [3:0] cio_spi_device_sd_p2d; + logic [3:0] cio_spi_device_sd_d2p; + logic [3:0] cio_spi_device_sd_en_d2p; + // i2c0 + logic cio_i2c0_sda_p2d; + logic cio_i2c0_scl_p2d; + logic cio_i2c0_sda_d2p; + logic cio_i2c0_sda_en_d2p; + logic cio_i2c0_scl_d2p; + logic cio_i2c0_scl_en_d2p; + // rv_timer + // otp_ctrl + logic [7:0] cio_otp_ctrl_test_d2p; + logic [7:0] cio_otp_ctrl_test_en_d2p; + // lc_ctrl + // alert_handler + // spi_host0 + logic [3:0] cio_spi_host0_sd_p2d; + logic cio_spi_host0_sck_d2p; + logic cio_spi_host0_sck_en_d2p; + logic cio_spi_host0_csb_d2p; + logic cio_spi_host0_csb_en_d2p; + logic [3:0] cio_spi_host0_sd_d2p; + logic [3:0] cio_spi_host0_sd_en_d2p; + // pwrmgr_aon + // rstmgr_aon + // clkmgr_aon + // pinmux_aon + // aon_timer_aon + // sensor_ctrl + // soc_proxy + logic [15:0] cio_soc_proxy_soc_gpi_p2d; + logic [15:0] cio_soc_proxy_soc_gpo_d2p; + logic [15:0] cio_soc_proxy_soc_gpo_en_d2p; + // sram_ctrl_ret_aon + // rv_dm + // rv_plic + // aes + // hmac + // kmac + // otbn + // keymgr_dpe + // csrng + // edn0 + // edn1 + // sram_ctrl_main + // sram_ctrl_mbox + // rom_ctrl0 + // rom_ctrl1 + // dma + // mbx0 + // mbx1 + // mbx2 + // mbx3 + // mbx4 + // mbx5 + // mbx6 + // mbx_jtag + // mbx_pcie0 + // mbx_pcie1 + // rv_core_ibex + + + logic [159:0] intr_vector; + // Interrupt source list + logic intr_uart0_tx_watermark; + logic intr_uart0_rx_watermark; + logic intr_uart0_tx_done; + logic intr_uart0_rx_overflow; + logic intr_uart0_rx_frame_err; + logic intr_uart0_rx_break_err; + logic intr_uart0_rx_timeout; + logic intr_uart0_rx_parity_err; + logic intr_uart0_tx_empty; + logic [31:0] intr_gpio_gpio; + logic intr_spi_device_upload_cmdfifo_not_empty; + logic intr_spi_device_upload_payload_not_empty; + logic intr_spi_device_upload_payload_overflow; + logic intr_spi_device_readbuf_watermark; + logic intr_spi_device_readbuf_flip; + logic intr_spi_device_tpm_header_not_empty; + logic intr_spi_device_tpm_rdfifo_cmd_end; + logic intr_spi_device_tpm_rdfifo_drop; + logic intr_i2c0_fmt_threshold; + logic intr_i2c0_rx_threshold; + logic intr_i2c0_acq_threshold; + logic intr_i2c0_rx_overflow; + logic intr_i2c0_controller_halt; + logic intr_i2c0_scl_interference; + logic intr_i2c0_sda_interference; + logic intr_i2c0_stretch_timeout; + logic intr_i2c0_sda_unstable; + logic intr_i2c0_cmd_complete; + logic intr_i2c0_tx_stretch; + logic intr_i2c0_tx_threshold; + logic intr_i2c0_acq_stretch; + logic intr_i2c0_unexp_stop; + logic intr_i2c0_host_timeout; + logic intr_rv_timer_timer_expired_hart0_timer0; + logic intr_otp_ctrl_otp_operation_done; + logic intr_otp_ctrl_otp_error; + logic intr_alert_handler_classa; + logic intr_alert_handler_classb; + logic intr_alert_handler_classc; + logic intr_alert_handler_classd; + logic intr_spi_host0_error; + logic intr_spi_host0_spi_event; + logic intr_pwrmgr_aon_wakeup; + logic intr_aon_timer_aon_wkup_timer_expired; + logic intr_aon_timer_aon_wdog_timer_bark; + logic intr_sensor_ctrl_io_status_change; + logic intr_sensor_ctrl_init_status_change; + logic [31:0] intr_soc_proxy_external; + logic intr_hmac_hmac_done; + logic intr_hmac_fifo_empty; + logic intr_hmac_hmac_err; + logic intr_kmac_kmac_done; + logic intr_kmac_fifo_empty; + logic intr_kmac_kmac_err; + logic intr_otbn_done; + logic intr_keymgr_dpe_op_done; + logic intr_csrng_cs_cmd_req_done; + logic intr_csrng_cs_entropy_req; + logic intr_csrng_cs_hw_inst_exc; + logic intr_csrng_cs_fatal_err; + logic intr_edn0_edn_cmd_req_done; + logic intr_edn0_edn_fatal_err; + logic intr_edn1_edn_cmd_req_done; + logic intr_edn1_edn_fatal_err; + logic intr_dma_dma_done; + logic intr_dma_dma_chunk_done; + logic intr_dma_dma_error; + logic intr_mbx0_mbx_ready; + logic intr_mbx0_mbx_abort; + logic intr_mbx0_mbx_error; + logic intr_mbx1_mbx_ready; + logic intr_mbx1_mbx_abort; + logic intr_mbx1_mbx_error; + logic intr_mbx2_mbx_ready; + logic intr_mbx2_mbx_abort; + logic intr_mbx2_mbx_error; + logic intr_mbx3_mbx_ready; + logic intr_mbx3_mbx_abort; + logic intr_mbx3_mbx_error; + logic intr_mbx4_mbx_ready; + logic intr_mbx4_mbx_abort; + logic intr_mbx4_mbx_error; + logic intr_mbx5_mbx_ready; + logic intr_mbx5_mbx_abort; + logic intr_mbx5_mbx_error; + logic intr_mbx6_mbx_ready; + logic intr_mbx6_mbx_abort; + logic intr_mbx6_mbx_error; + logic intr_mbx_jtag_mbx_ready; + logic intr_mbx_jtag_mbx_abort; + logic intr_mbx_jtag_mbx_error; + logic intr_mbx_pcie0_mbx_ready; + logic intr_mbx_pcie0_mbx_abort; + logic intr_mbx_pcie0_mbx_error; + logic intr_mbx_pcie1_mbx_ready; + logic intr_mbx_pcie1_mbx_abort; + logic intr_mbx_pcie1_mbx_error; + + // Alert list + prim_alert_pkg::alert_tx_t [alert_pkg::NAlerts-1:0] alert_tx; + prim_alert_pkg::alert_rx_t [alert_pkg::NAlerts-1:0] alert_rx; + + + // define inter-module signals + ast_pkg::ast_obs_ctrl_t ast_obs_ctrl; + prim_ram_1p_pkg::ram_1p_cfg_t ast_ram_1p_cfg; + prim_ram_2p_pkg::ram_2p_cfg_t ast_spi_ram_2p_cfg; + prim_rom_pkg::rom_cfg_t ast_rom_cfg; + alert_pkg::alert_crashdump_t alert_handler_crashdump; + prim_esc_pkg::esc_rx_t [3:0] alert_handler_esc_rx; + prim_esc_pkg::esc_tx_t [3:0] alert_handler_esc_tx; + logic aon_timer_aon_nmi_wdog_timer_bark; + csrng_pkg::csrng_req_t [1:0] csrng_csrng_cmd_req; + csrng_pkg::csrng_rsp_t [1:0] csrng_csrng_cmd_rsp; + otp_ctrl_pkg::sram_otp_key_req_t [3:0] otp_ctrl_sram_otp_key_req; + otp_ctrl_pkg::sram_otp_key_rsp_t [3:0] otp_ctrl_sram_otp_key_rsp; + pwrmgr_pkg::pwr_rst_req_t pwrmgr_aon_pwr_rst_req; + pwrmgr_pkg::pwr_rst_rsp_t pwrmgr_aon_pwr_rst_rsp; + pwrmgr_pkg::pwr_clk_req_t pwrmgr_aon_pwr_clk_req; + pwrmgr_pkg::pwr_clk_rsp_t pwrmgr_aon_pwr_clk_rsp; + pwrmgr_pkg::pwr_otp_req_t pwrmgr_aon_pwr_otp_req; + pwrmgr_pkg::pwr_otp_rsp_t pwrmgr_aon_pwr_otp_rsp; + pwrmgr_pkg::pwr_lc_req_t pwrmgr_aon_pwr_lc_req; + pwrmgr_pkg::pwr_lc_rsp_t pwrmgr_aon_pwr_lc_rsp; + logic pwrmgr_aon_strap; + logic pwrmgr_aon_low_power; + lc_ctrl_pkg::lc_tx_t pwrmgr_aon_fetch_en; + rom_ctrl_pkg::pwrmgr_data_t pwrmgr_aon_rom_ctrl; + rom_ctrl_pkg::keymgr_data_t [1:0] keymgr_dpe_rom_digest; + dma_pkg::lsio_trigger_t dma_lsio_trigger; + logic i2c0_lsio_trigger; + logic spi_host0_lsio_trigger; + logic uart0_lsio_trigger; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_flash_rma_req; + lc_ctrl_pkg::lc_tx_t otbn_lc_rma_ack; + edn_pkg::edn_req_t [7:0] edn0_edn_req; + edn_pkg::edn_rsp_t [7:0] edn0_edn_rsp; + edn_pkg::edn_req_t [7:0] edn1_edn_req; + edn_pkg::edn_rsp_t [7:0] edn1_edn_rsp; + otp_ctrl_pkg::otbn_otp_key_req_t otp_ctrl_otbn_otp_key_req; + otp_ctrl_pkg::otbn_otp_key_rsp_t otp_ctrl_otbn_otp_key_rsp; + otp_ctrl_pkg::otp_keymgr_key_t otp_ctrl_otp_keymgr_key; + keymgr_pkg::hw_key_req_t keymgr_dpe_aes_key; + keymgr_pkg::hw_key_req_t keymgr_dpe_kmac_key; + keymgr_pkg::otbn_key_req_t keymgr_dpe_otbn_key; + kmac_pkg::app_req_t [KmacNumAppIntf-1:0] kmac_app_req; + kmac_pkg::app_rsp_t [KmacNumAppIntf-1:0] kmac_app_rsp; + logic kmac_en_masking; + prim_mubi_pkg::mubi4_t [3:0] clkmgr_aon_idle; + otp_ctrl_pkg::otp_lc_data_t otp_ctrl_otp_lc_data; + otp_ctrl_pkg::lc_otp_program_req_t lc_ctrl_lc_otp_program_req; + otp_ctrl_pkg::lc_otp_program_rsp_t lc_ctrl_lc_otp_program_rsp; + otp_ctrl_pkg::lc_otp_vendor_test_req_t lc_ctrl_lc_otp_vendor_test_req; + otp_ctrl_pkg::lc_otp_vendor_test_rsp_t lc_ctrl_lc_otp_vendor_test_rsp; + lc_ctrl_pkg::lc_keymgr_div_t lc_ctrl_lc_keymgr_div; + logic lc_ctrl_strap_en_override; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_dft_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_hw_debug_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_cpu_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_keymgr_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_escalate_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_check_byp_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_clk_byp_req; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_clk_byp_ack; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_creator_seed_sw_rw_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_owner_seed_sw_rw_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_seed_hw_rd_en; + logic rv_plic_msip; + logic rv_plic_irq; + logic rv_dm_debug_req; + rv_core_ibex_pkg::cpu_crash_dump_t rv_core_ibex_crash_dump; + pwrmgr_pkg::pwr_cpu_t rv_core_ibex_pwrmgr; + spi_device_pkg::passthrough_req_t spi_device_passthrough_req; + spi_device_pkg::passthrough_rsp_t spi_device_passthrough_rsp; + logic rv_dm_ndmreset_req; + prim_mubi_pkg::mubi4_t rstmgr_aon_sw_rst_req; + logic [5:0] pwrmgr_aon_wakeups; + logic [1:0] pwrmgr_aon_rstreqs; + tlul_pkg::tl_h2d_t main_tl_rv_core_ibex__corei_req; + tlul_pkg::tl_d2h_t main_tl_rv_core_ibex__corei_rsp; + tlul_pkg::tl_h2d_t main_tl_rv_core_ibex__cored_req; + tlul_pkg::tl_d2h_t main_tl_rv_core_ibex__cored_rsp; + tlul_pkg::tl_h2d_t main_tl_rv_dm__sba_req; + tlul_pkg::tl_d2h_t main_tl_rv_dm__sba_rsp; + tlul_pkg::tl_h2d_t rv_dm_regs_tl_d_req; + tlul_pkg::tl_d2h_t rv_dm_regs_tl_d_rsp; + tlul_pkg::tl_h2d_t rv_dm_mem_tl_d_req; + tlul_pkg::tl_d2h_t rv_dm_mem_tl_d_rsp; + tlul_pkg::tl_h2d_t rom_ctrl0_rom_tl_req; + tlul_pkg::tl_d2h_t rom_ctrl0_rom_tl_rsp; + tlul_pkg::tl_h2d_t rom_ctrl0_regs_tl_req; + tlul_pkg::tl_d2h_t rom_ctrl0_regs_tl_rsp; + tlul_pkg::tl_h2d_t rom_ctrl1_rom_tl_req; + tlul_pkg::tl_d2h_t rom_ctrl1_rom_tl_rsp; + tlul_pkg::tl_h2d_t rom_ctrl1_regs_tl_req; + tlul_pkg::tl_d2h_t rom_ctrl1_regs_tl_rsp; + tlul_pkg::tl_h2d_t main_tl_peri_req; + tlul_pkg::tl_d2h_t main_tl_peri_rsp; + tlul_pkg::tl_h2d_t soc_proxy_core_tl_req; + tlul_pkg::tl_d2h_t soc_proxy_core_tl_rsp; + tlul_pkg::tl_h2d_t soc_proxy_ctn_tl_req; + tlul_pkg::tl_d2h_t soc_proxy_ctn_tl_rsp; + tlul_pkg::tl_h2d_t hmac_tl_req; + tlul_pkg::tl_d2h_t hmac_tl_rsp; + tlul_pkg::tl_h2d_t kmac_tl_req; + tlul_pkg::tl_d2h_t kmac_tl_rsp; + tlul_pkg::tl_h2d_t aes_tl_req; + tlul_pkg::tl_d2h_t aes_tl_rsp; + tlul_pkg::tl_h2d_t csrng_tl_req; + tlul_pkg::tl_d2h_t csrng_tl_rsp; + tlul_pkg::tl_h2d_t edn0_tl_req; + tlul_pkg::tl_d2h_t edn0_tl_rsp; + tlul_pkg::tl_h2d_t edn1_tl_req; + tlul_pkg::tl_d2h_t edn1_tl_rsp; + tlul_pkg::tl_h2d_t rv_plic_tl_req; + tlul_pkg::tl_d2h_t rv_plic_tl_rsp; + tlul_pkg::tl_h2d_t otbn_tl_req; + tlul_pkg::tl_d2h_t otbn_tl_rsp; + tlul_pkg::tl_h2d_t keymgr_dpe_tl_req; + tlul_pkg::tl_d2h_t keymgr_dpe_tl_rsp; + tlul_pkg::tl_h2d_t rv_core_ibex_cfg_tl_d_req; + tlul_pkg::tl_d2h_t rv_core_ibex_cfg_tl_d_rsp; + tlul_pkg::tl_h2d_t sram_ctrl_main_regs_tl_req; + tlul_pkg::tl_d2h_t sram_ctrl_main_regs_tl_rsp; + tlul_pkg::tl_h2d_t sram_ctrl_main_ram_tl_req; + tlul_pkg::tl_d2h_t sram_ctrl_main_ram_tl_rsp; + tlul_pkg::tl_h2d_t sram_ctrl_mbox_regs_tl_req; + tlul_pkg::tl_d2h_t sram_ctrl_mbox_regs_tl_rsp; + tlul_pkg::tl_h2d_t sram_ctrl_mbox_ram_tl_req; + tlul_pkg::tl_d2h_t sram_ctrl_mbox_ram_tl_rsp; + tlul_pkg::tl_h2d_t dma_tl_d_req; + tlul_pkg::tl_d2h_t dma_tl_d_rsp; + tlul_pkg::tl_h2d_t main_tl_dma__host_req; + tlul_pkg::tl_d2h_t main_tl_dma__host_rsp; + tlul_pkg::tl_h2d_t mbx0_core_tl_d_req; + tlul_pkg::tl_d2h_t mbx0_core_tl_d_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx0__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx0__sram_rsp; + tlul_pkg::tl_h2d_t mbx1_core_tl_d_req; + tlul_pkg::tl_d2h_t mbx1_core_tl_d_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx1__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx1__sram_rsp; + tlul_pkg::tl_h2d_t mbx2_core_tl_d_req; + tlul_pkg::tl_d2h_t mbx2_core_tl_d_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx2__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx2__sram_rsp; + tlul_pkg::tl_h2d_t mbx3_core_tl_d_req; + tlul_pkg::tl_d2h_t mbx3_core_tl_d_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx3__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx3__sram_rsp; + tlul_pkg::tl_h2d_t mbx4_core_tl_d_req; + tlul_pkg::tl_d2h_t mbx4_core_tl_d_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx4__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx4__sram_rsp; + tlul_pkg::tl_h2d_t mbx5_core_tl_d_req; + tlul_pkg::tl_d2h_t mbx5_core_tl_d_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx5__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx5__sram_rsp; + tlul_pkg::tl_h2d_t mbx6_core_tl_d_req; + tlul_pkg::tl_d2h_t mbx6_core_tl_d_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx6__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx6__sram_rsp; + tlul_pkg::tl_h2d_t mbx_jtag_core_tl_d_req; + tlul_pkg::tl_d2h_t mbx_jtag_core_tl_d_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx_jtag__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx_jtag__sram_rsp; + tlul_pkg::tl_h2d_t mbx_pcie0_core_tl_d_req; + tlul_pkg::tl_d2h_t mbx_pcie0_core_tl_d_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx_pcie0__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx_pcie0__sram_rsp; + tlul_pkg::tl_h2d_t mbx_pcie1_core_tl_d_req; + tlul_pkg::tl_d2h_t mbx_pcie1_core_tl_d_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx_pcie1__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx_pcie1__sram_rsp; + tlul_pkg::tl_h2d_t uart0_tl_req; + tlul_pkg::tl_d2h_t uart0_tl_rsp; + tlul_pkg::tl_h2d_t i2c0_tl_req; + tlul_pkg::tl_d2h_t i2c0_tl_rsp; + tlul_pkg::tl_h2d_t gpio_tl_req; + tlul_pkg::tl_d2h_t gpio_tl_rsp; + tlul_pkg::tl_h2d_t spi_host0_tl_req; + tlul_pkg::tl_d2h_t spi_host0_tl_rsp; + tlul_pkg::tl_h2d_t spi_device_tl_req; + tlul_pkg::tl_d2h_t spi_device_tl_rsp; + tlul_pkg::tl_h2d_t rv_timer_tl_req; + tlul_pkg::tl_d2h_t rv_timer_tl_rsp; + tlul_pkg::tl_h2d_t pwrmgr_aon_tl_req; + tlul_pkg::tl_d2h_t pwrmgr_aon_tl_rsp; + tlul_pkg::tl_h2d_t rstmgr_aon_tl_req; + tlul_pkg::tl_d2h_t rstmgr_aon_tl_rsp; + tlul_pkg::tl_h2d_t clkmgr_aon_tl_req; + tlul_pkg::tl_d2h_t clkmgr_aon_tl_rsp; + tlul_pkg::tl_h2d_t pinmux_aon_tl_req; + tlul_pkg::tl_d2h_t pinmux_aon_tl_rsp; + tlul_pkg::tl_h2d_t otp_ctrl_core_tl_req; + tlul_pkg::tl_d2h_t otp_ctrl_core_tl_rsp; + tlul_pkg::tl_h2d_t otp_ctrl_prim_tl_req; + tlul_pkg::tl_d2h_t otp_ctrl_prim_tl_rsp; + tlul_pkg::tl_h2d_t lc_ctrl_regs_tl_req; + tlul_pkg::tl_d2h_t lc_ctrl_regs_tl_rsp; + tlul_pkg::tl_h2d_t sensor_ctrl_tl_req; + tlul_pkg::tl_d2h_t sensor_ctrl_tl_rsp; + tlul_pkg::tl_h2d_t alert_handler_tl_req; + tlul_pkg::tl_d2h_t alert_handler_tl_rsp; + tlul_pkg::tl_h2d_t sram_ctrl_ret_aon_regs_tl_req; + tlul_pkg::tl_d2h_t sram_ctrl_ret_aon_regs_tl_rsp; + tlul_pkg::tl_h2d_t sram_ctrl_ret_aon_ram_tl_req; + tlul_pkg::tl_d2h_t sram_ctrl_ret_aon_ram_tl_rsp; + tlul_pkg::tl_h2d_t aon_timer_aon_tl_req; + tlul_pkg::tl_d2h_t aon_timer_aon_tl_rsp; + tlul_pkg::tl_h2d_t mbx0_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx0_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx1_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx1_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx2_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx2_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx3_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx3_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx4_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx4_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx5_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx5_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx6_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx6_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx_pcie0_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx_pcie0_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx_pcie1_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx_pcie1_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t rv_dm_dbg_tl_d_req; + tlul_pkg::tl_d2h_t rv_dm_dbg_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx_jtag_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx_jtag_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t lc_ctrl_dmi_tl_req; + tlul_pkg::tl_d2h_t lc_ctrl_dmi_tl_rsp; + clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks; + clkmgr_pkg::clkmgr_cg_en_t clkmgr_aon_cg_en; + rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets; + rstmgr_pkg::rstmgr_rst_en_t rstmgr_aon_rst_en; + logic rv_core_ibex_irq_timer; + logic [31:0] rv_core_ibex_hart_id; + logic [31:0] rv_core_ibex_boot_addr; + otp_ctrl_part_pkg::otp_broadcast_t otp_ctrl_otp_broadcast; + otp_ctrl_pkg::otp_device_id_t lc_ctrl_otp_device_id; + otp_ctrl_pkg::otp_manuf_state_t lc_ctrl_otp_manuf_state; + otp_ctrl_pkg::otp_device_id_t keymgr_dpe_otp_device_id; + prim_mubi_pkg::mubi8_t sram_ctrl_main_otp_en_sram_ifetch; + + // define mixed connection to port + assign edn0_edn_req[2] = ast_edn_req_i; + assign ast_edn_rsp_o = edn0_edn_rsp[2]; + assign ast_lc_dft_en_o = lc_ctrl_lc_dft_en; + assign ast_lc_hw_debug_en_o = lc_ctrl_lc_hw_debug_en; + assign ast_obs_ctrl = obs_ctrl_i; + assign ast_ram_1p_cfg = ram_1p_cfg_i; + assign ast_spi_ram_2p_cfg = spi_ram_2p_cfg_i; + assign ast_rom_cfg = rom_cfg_i; + + // define partial inter-module tie-off + edn_pkg::edn_rsp_t unused_edn1_edn_rsp1; + edn_pkg::edn_rsp_t unused_edn1_edn_rsp2; + edn_pkg::edn_rsp_t unused_edn1_edn_rsp3; + edn_pkg::edn_rsp_t unused_edn1_edn_rsp4; + edn_pkg::edn_rsp_t unused_edn1_edn_rsp5; + edn_pkg::edn_rsp_t unused_edn1_edn_rsp6; + edn_pkg::edn_rsp_t unused_edn1_edn_rsp7; + + // assign partial inter-module tie-off + assign unused_edn1_edn_rsp1 = edn1_edn_rsp[1]; + assign unused_edn1_edn_rsp2 = edn1_edn_rsp[2]; + assign unused_edn1_edn_rsp3 = edn1_edn_rsp[3]; + assign unused_edn1_edn_rsp4 = edn1_edn_rsp[4]; + assign unused_edn1_edn_rsp5 = edn1_edn_rsp[5]; + assign unused_edn1_edn_rsp6 = edn1_edn_rsp[6]; + assign unused_edn1_edn_rsp7 = edn1_edn_rsp[7]; + assign edn1_edn_req[1] = '0; + assign edn1_edn_req[2] = '0; + assign edn1_edn_req[3] = '0; + assign edn1_edn_req[4] = '0; + assign edn1_edn_req[5] = '0; + assign edn1_edn_req[6] = '0; + assign edn1_edn_req[7] = '0; + + + // OTP HW_CFG Broadcast signals. + // TODO(#6713): The actual struct breakout and mapping currently needs to + // be performed by hand. + assign sram_ctrl_main_otp_en_sram_ifetch = + otp_ctrl_otp_broadcast.hw_cfg1_data.en_sram_ifetch; + assign lc_ctrl_otp_device_id = + otp_ctrl_otp_broadcast.hw_cfg0_data.device_id; + assign lc_ctrl_otp_manuf_state = + otp_ctrl_otp_broadcast.hw_cfg0_data.manuf_state; + assign keymgr_dpe_otp_device_id = + otp_ctrl_otp_broadcast.hw_cfg0_data.device_id; + + logic unused_otp_broadcast_bits; + assign unused_otp_broadcast_bits = ^{ + otp_ctrl_otp_broadcast.valid, + otp_ctrl_otp_broadcast.hw_cfg0_data.hw_cfg0_digest, + otp_ctrl_otp_broadcast.hw_cfg1_data.hw_cfg1_digest, + otp_ctrl_otp_broadcast.hw_cfg1_data.soc_dbg_state, + otp_ctrl_otp_broadcast.hw_cfg1_data.unallocated + }; + + // See #7978 This below is a hack. + // This is because ast is a comportable-like module that sits outside + // of top_darjeeling's boundary. + assign clks_ast_o = clkmgr_aon_clocks; + assign rsts_ast_o = rstmgr_aon_resets; + + // ibex specific assignments + // TODO: This should be further automated in the future. + assign rv_core_ibex_irq_timer = intr_rv_timer_timer_expired_hart0_timer0; + assign rv_core_ibex_hart_id = '0; + + assign rv_core_ibex_boot_addr = ADDR_SPACE_ROM_CTRL0__ROM; + + // Wire up alert handler LPGs + prim_mubi_pkg::mubi4_t [alert_pkg::NLpg-1:0] lpg_cg_en; + prim_mubi_pkg::mubi4_t [alert_pkg::NLpg-1:0] lpg_rst_en; + + + // peri_lc_io_div4_0 + assign lpg_cg_en[0] = clkmgr_aon_cg_en.io_div4_peri; + assign lpg_rst_en[0] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; + // peri_spi_device_0 + assign lpg_cg_en[1] = clkmgr_aon_cg_en.io_div4_peri; + assign lpg_rst_en[1] = rstmgr_aon_rst_en.spi_device[rstmgr_pkg::Domain0Sel]; + // peri_i2c0_0 + assign lpg_cg_en[2] = clkmgr_aon_cg_en.io_div4_peri; + assign lpg_rst_en[2] = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::Domain0Sel]; + // timers_lc_io_div4_0 + assign lpg_cg_en[3] = clkmgr_aon_cg_en.io_div4_timers; + assign lpg_rst_en[3] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; + // secure_lc_io_div4_0 + assign lpg_cg_en[4] = clkmgr_aon_cg_en.io_div4_secure; + assign lpg_rst_en[4] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; + // peri_spi_host0_0 + assign lpg_cg_en[5] = clkmgr_aon_cg_en.io_div4_peri; + assign lpg_rst_en[5] = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::Domain0Sel]; + // powerup_por_io_div4_Aon + assign lpg_cg_en[6] = clkmgr_aon_cg_en.io_div4_powerup; + assign lpg_rst_en[6] = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::DomainAonSel]; + // powerup_lc_io_div4_Aon + assign lpg_cg_en[7] = clkmgr_aon_cg_en.io_div4_powerup; + assign lpg_rst_en[7] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; + // timers_lc_io_div4_Aon + assign lpg_cg_en[8] = clkmgr_aon_cg_en.io_div4_timers; + assign lpg_rst_en[8] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; + // infra_lc_io_div4_0 + assign lpg_cg_en[9] = clkmgr_aon_cg_en.io_div4_infra; + assign lpg_rst_en[9] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; + // secure_lc_io_div4_Aon + assign lpg_cg_en[10] = clkmgr_aon_cg_en.io_div4_secure; + assign lpg_rst_en[10] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; + // infra_lc_0 + assign lpg_cg_en[11] = clkmgr_aon_cg_en.main_infra; + assign lpg_rst_en[11] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + // infra_lc_io_div4_Aon + assign lpg_cg_en[12] = clkmgr_aon_cg_en.io_div4_infra; + assign lpg_rst_en[12] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; + // infra_sys_0 + assign lpg_cg_en[13] = clkmgr_aon_cg_en.main_infra; + assign lpg_rst_en[13] = rstmgr_aon_rst_en.sys[rstmgr_pkg::Domain0Sel]; + // secure_lc_0 + assign lpg_cg_en[14] = clkmgr_aon_cg_en.main_secure; + assign lpg_rst_en[14] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + // aes_trans_lc_0 + assign lpg_cg_en[15] = clkmgr_aon_cg_en.main_aes; + assign lpg_rst_en[15] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + // hmac_trans_lc_0 + assign lpg_cg_en[16] = clkmgr_aon_cg_en.main_hmac; + assign lpg_rst_en[16] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + // kmac_trans_lc_0 + assign lpg_cg_en[17] = clkmgr_aon_cg_en.main_kmac; + assign lpg_rst_en[17] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + // otbn_trans_lc_0 + assign lpg_cg_en[18] = clkmgr_aon_cg_en.main_otbn; + assign lpg_rst_en[18] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + +// tie-off unused connections +//VCS coverage off +// pragma coverage off + prim_mubi_pkg::mubi4_t unused_cg_en_0; + assign unused_cg_en_0 = clkmgr_aon_cg_en.aon_powerup; + prim_mubi_pkg::mubi4_t unused_cg_en_1; + assign unused_cg_en_1 = clkmgr_aon_cg_en.main_powerup; + prim_mubi_pkg::mubi4_t unused_cg_en_2; + assign unused_cg_en_2 = clkmgr_aon_cg_en.io_powerup; + prim_mubi_pkg::mubi4_t unused_cg_en_3; + assign unused_cg_en_3 = clkmgr_aon_cg_en.usb_powerup; + prim_mubi_pkg::mubi4_t unused_cg_en_4; + assign unused_cg_en_4 = clkmgr_aon_cg_en.io_div2_powerup; + prim_mubi_pkg::mubi4_t unused_cg_en_5; + assign unused_cg_en_5 = clkmgr_aon_cg_en.aon_infra; + prim_mubi_pkg::mubi4_t unused_cg_en_6; + assign unused_cg_en_6 = clkmgr_aon_cg_en.aon_secure; + prim_mubi_pkg::mubi4_t unused_cg_en_7; + assign unused_cg_en_7 = clkmgr_aon_cg_en.aon_peri; + prim_mubi_pkg::mubi4_t unused_cg_en_8; + assign unused_cg_en_8 = clkmgr_aon_cg_en.aon_timers; + prim_mubi_pkg::mubi4_t unused_cg_en_9; + assign unused_cg_en_9 = clkmgr_aon_cg_en.usb_infra; + prim_mubi_pkg::mubi4_t unused_cg_en_10; + assign unused_cg_en_10 = clkmgr_aon_cg_en.io_div2_peri; + prim_mubi_pkg::mubi4_t unused_cg_en_11; + assign unused_cg_en_11 = clkmgr_aon_cg_en.usb_peri; + prim_mubi_pkg::mubi4_t unused_rst_en_0; + assign unused_rst_en_0 = rstmgr_aon_rst_en.por_aon[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_1; + assign unused_rst_en_1 = rstmgr_aon_rst_en.por_aon[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_2; + assign unused_rst_en_2 = rstmgr_aon_rst_en.por[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_3; + assign unused_rst_en_3 = rstmgr_aon_rst_en.por[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_4; + assign unused_rst_en_4 = rstmgr_aon_rst_en.por_io[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_5; + assign unused_rst_en_5 = rstmgr_aon_rst_en.por_io[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_6; + assign unused_rst_en_6 = rstmgr_aon_rst_en.por_io_div2[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_7; + assign unused_rst_en_7 = rstmgr_aon_rst_en.por_io_div2[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_8; + assign unused_rst_en_8 = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_9; + assign unused_rst_en_9 = rstmgr_aon_rst_en.por_usb[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_10; + assign unused_rst_en_10 = rstmgr_aon_rst_en.por_usb[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_11; + assign unused_rst_en_11 = rstmgr_aon_rst_en.lc_shadowed[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_12; + assign unused_rst_en_12 = rstmgr_aon_rst_en.lc[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_13; + assign unused_rst_en_13 = rstmgr_aon_rst_en.lc_shadowed[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_14; + assign unused_rst_en_14 = rstmgr_aon_rst_en.lc_aon[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_15; + assign unused_rst_en_15 = rstmgr_aon_rst_en.lc_aon[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_16; + assign unused_rst_en_16 = rstmgr_aon_rst_en.lc_io[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_17; + assign unused_rst_en_17 = rstmgr_aon_rst_en.lc_io[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_18; + assign unused_rst_en_18 = rstmgr_aon_rst_en.lc_io_div2[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_19; + assign unused_rst_en_19 = rstmgr_aon_rst_en.lc_io_div2[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_20; + assign unused_rst_en_20 = rstmgr_aon_rst_en.lc_io_div4_shadowed[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_21; + assign unused_rst_en_21 = rstmgr_aon_rst_en.lc_io_div4_shadowed[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_22; + assign unused_rst_en_22 = rstmgr_aon_rst_en.lc_usb[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_23; + assign unused_rst_en_23 = rstmgr_aon_rst_en.lc_usb[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_24; + assign unused_rst_en_24 = rstmgr_aon_rst_en.sys[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_25; + assign unused_rst_en_25 = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_26; + assign unused_rst_en_26 = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_27; + assign unused_rst_en_27 = rstmgr_aon_rst_en.spi_device[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_28; + assign unused_rst_en_28 = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_29; + assign unused_rst_en_29 = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::DomainAonSel]; +//VCS coverage on +// pragma coverage on + + // Peripheral Instantiation + + + uart #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[0:0]) + ) u_uart0 ( + + // Input + .cio_rx_i (cio_uart0_rx_p2d), + + // Output + .cio_tx_o (cio_uart0_tx_d2p), + .cio_tx_en_o (cio_uart0_tx_en_d2p), + + // Interrupt + .intr_tx_watermark_o (intr_uart0_tx_watermark), + .intr_rx_watermark_o (intr_uart0_rx_watermark), + .intr_tx_done_o (intr_uart0_tx_done), + .intr_rx_overflow_o (intr_uart0_rx_overflow), + .intr_rx_frame_err_o (intr_uart0_rx_frame_err), + .intr_rx_break_err_o (intr_uart0_rx_break_err), + .intr_rx_timeout_o (intr_uart0_rx_timeout), + .intr_rx_parity_err_o (intr_uart0_rx_parity_err), + .intr_tx_empty_o (intr_uart0_tx_empty), + // [0]: fatal_fault + .alert_tx_o ( alert_tx[0:0] ), + .alert_rx_i ( alert_rx[0:0] ), + + // Inter-module signals + .lsio_trigger_o(uart0_lsio_trigger), + .tl_i(uart0_tl_req), + .tl_o(uart0_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + gpio #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[1:1]), + .GpioAsyncOn(GpioGpioAsyncOn), + .GpioAsHwStrapsEn(GpioGpioAsHwStrapsEn) + ) u_gpio ( + + // Input + .cio_gpio_i (cio_gpio_gpio_p2d), + + // Output + .cio_gpio_o (cio_gpio_gpio_d2p), + .cio_gpio_en_o (cio_gpio_gpio_en_d2p), + + // Interrupt + .intr_gpio_o (intr_gpio_gpio), + // [1]: fatal_fault + .alert_tx_o ( alert_tx[1:1] ), + .alert_rx_i ( alert_rx[1:1] ), + + // Inter-module signals + .strap_en_i(pwrmgr_aon_strap), + .sampled_straps_o(), + .tl_i(gpio_tl_req), + .tl_o(gpio_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + spi_device #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[2:2]), + .SramType(SpiDeviceSramType) + ) u_spi_device ( + + // Input + .cio_sck_i (cio_spi_device_sck_p2d), + .cio_csb_i (cio_spi_device_csb_p2d), + .cio_tpm_csb_i (cio_spi_device_tpm_csb_p2d), + .cio_sd_i (cio_spi_device_sd_p2d), + + // Output + .cio_sd_o (cio_spi_device_sd_d2p), + .cio_sd_en_o (cio_spi_device_sd_en_d2p), + + // Interrupt + .intr_upload_cmdfifo_not_empty_o (intr_spi_device_upload_cmdfifo_not_empty), + .intr_upload_payload_not_empty_o (intr_spi_device_upload_payload_not_empty), + .intr_upload_payload_overflow_o (intr_spi_device_upload_payload_overflow), + .intr_readbuf_watermark_o (intr_spi_device_readbuf_watermark), + .intr_readbuf_flip_o (intr_spi_device_readbuf_flip), + .intr_tpm_header_not_empty_o (intr_spi_device_tpm_header_not_empty), + .intr_tpm_rdfifo_cmd_end_o (intr_spi_device_tpm_rdfifo_cmd_end), + .intr_tpm_rdfifo_drop_o (intr_spi_device_tpm_rdfifo_drop), + // [2]: fatal_fault + .alert_tx_o ( alert_tx[2:2] ), + .alert_rx_i ( alert_rx[2:2] ), + + // Inter-module signals + .ram_cfg_i(ast_spi_ram_2p_cfg), + .passthrough_o(spi_device_passthrough_req), + .passthrough_i(spi_device_passthrough_rsp), + .mbist_en_i('0), + .sck_monitor_o(sck_monitor_o), + .tl_i(spi_device_tl_req), + .tl_o(spi_device_tl_rsp), + .scanmode_i, + .scan_rst_ni, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), + .scan_clk_i (clkmgr_aon_clocks.clk_io_div2_peri), + .rst_ni (rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel]) + ); + i2c #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[3:3]), + .InputDelayCycles(I2c0InputDelayCycles) + ) u_i2c0 ( + + // Input + .cio_sda_i (cio_i2c0_sda_p2d), + .cio_scl_i (cio_i2c0_scl_p2d), + + // Output + .cio_sda_o (cio_i2c0_sda_d2p), + .cio_sda_en_o (cio_i2c0_sda_en_d2p), + .cio_scl_o (cio_i2c0_scl_d2p), + .cio_scl_en_o (cio_i2c0_scl_en_d2p), + + // Interrupt + .intr_fmt_threshold_o (intr_i2c0_fmt_threshold), + .intr_rx_threshold_o (intr_i2c0_rx_threshold), + .intr_acq_threshold_o (intr_i2c0_acq_threshold), + .intr_rx_overflow_o (intr_i2c0_rx_overflow), + .intr_controller_halt_o (intr_i2c0_controller_halt), + .intr_scl_interference_o (intr_i2c0_scl_interference), + .intr_sda_interference_o (intr_i2c0_sda_interference), + .intr_stretch_timeout_o (intr_i2c0_stretch_timeout), + .intr_sda_unstable_o (intr_i2c0_sda_unstable), + .intr_cmd_complete_o (intr_i2c0_cmd_complete), + .intr_tx_stretch_o (intr_i2c0_tx_stretch), + .intr_tx_threshold_o (intr_i2c0_tx_threshold), + .intr_acq_stretch_o (intr_i2c0_acq_stretch), + .intr_unexp_stop_o (intr_i2c0_unexp_stop), + .intr_host_timeout_o (intr_i2c0_host_timeout), + // [3]: fatal_fault + .alert_tx_o ( alert_tx[3:3] ), + .alert_rx_i ( alert_rx[3:3] ), + + // Inter-module signals + .ram_cfg_i(prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT), + .lsio_trigger_o(i2c0_lsio_trigger), + .tl_i(i2c0_tl_req), + .tl_o(i2c0_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), + .rst_ni (rstmgr_aon_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel]) + ); + rv_timer #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[4:4]) + ) u_rv_timer ( + + // Interrupt + .intr_timer_expired_hart0_timer0_o (intr_rv_timer_timer_expired_hart0_timer0), + // [4]: fatal_fault + .alert_tx_o ( alert_tx[4:4] ), + .alert_rx_i ( alert_rx[4:4] ), + + // Inter-module signals + .tl_i(rv_timer_tl_req), + .tl_o(rv_timer_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_timers), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + otp_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[9:5]), + .MemInitFile(OtpCtrlMemInitFile), + .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed), + .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm), + .RndCnstScrmblKeyInit(RndCnstOtpCtrlScrmblKeyInit) + ) u_otp_ctrl ( + + // Output + .cio_test_o (cio_otp_ctrl_test_d2p), + .cio_test_en_o (cio_otp_ctrl_test_en_d2p), + + // Interrupt + .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done), + .intr_otp_error_o (intr_otp_ctrl_otp_error), + // [5]: fatal_macro_error + // [6]: fatal_check_error + // [7]: fatal_bus_integ_error + // [8]: fatal_prim_otp_alert + // [9]: recov_prim_otp_alert + .alert_tx_o ( alert_tx[9:5] ), + .alert_rx_i ( alert_rx[9:5] ), + + // Inter-module signals + .otp_ext_voltage_h_io(otp_ext_voltage_h_io), + .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o), + .otp_ast_pwr_seq_h_i(otp_ctrl_otp_ast_pwr_seq_h_i), + .edn_o(edn0_edn_req[1]), + .edn_i(edn0_edn_rsp[1]), + .pwr_otp_i(pwrmgr_aon_pwr_otp_req), + .pwr_otp_o(pwrmgr_aon_pwr_otp_rsp), + .lc_otp_vendor_test_i(lc_ctrl_lc_otp_vendor_test_req), + .lc_otp_vendor_test_o(lc_ctrl_lc_otp_vendor_test_rsp), + .lc_otp_program_i(lc_ctrl_lc_otp_program_req), + .lc_otp_program_o(lc_ctrl_lc_otp_program_rsp), + .otp_lc_data_o(otp_ctrl_otp_lc_data), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en), + .lc_owner_seed_sw_rw_en_i(lc_ctrl_lc_owner_seed_sw_rw_en), + .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en), + .lc_dft_en_i(lc_ctrl_lc_dft_en), + .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en), + .otp_keymgr_key_o(otp_ctrl_otp_keymgr_key), + .flash_otp_key_i('0), + .flash_otp_key_o(), + .sram_otp_key_i(otp_ctrl_sram_otp_key_req), + .sram_otp_key_o(otp_ctrl_sram_otp_key_rsp), + .otbn_otp_key_i(otp_ctrl_otbn_otp_key_req), + .otbn_otp_key_o(otp_ctrl_otbn_otp_key_rsp), + .otp_broadcast_o(otp_ctrl_otp_broadcast), + .obs_ctrl_i(ast_obs_ctrl), + .otp_obs_o(otp_obs_o), + .core_tl_i(otp_ctrl_core_tl_req), + .core_tl_o(otp_ctrl_core_tl_rsp), + .prim_tl_i(otp_ctrl_prim_tl_req), + .prim_tl_o(otp_ctrl_prim_tl_rsp), + .scanmode_i, + .scan_rst_ni, + .scan_en_i, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), + .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + lc_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[12:10]), + .SecVolatileRawUnlockEn(SecLcCtrlVolatileRawUnlockEn), + .UseDmiInterface(LcCtrlUseDmiInterface), + .RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid), + .RndCnstLcKeymgrDivTestUnlocked(RndCnstLcCtrlLcKeymgrDivTestUnlocked), + .RndCnstLcKeymgrDivDev(RndCnstLcCtrlLcKeymgrDivDev), + .RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction), + .RndCnstLcKeymgrDivRma(RndCnstLcCtrlLcKeymgrDivRma), + .RndCnstInvalidTokens(RndCnstLcCtrlInvalidTokens), + .SiliconCreatorId(LcCtrlSiliconCreatorId), + .ProductId(LcCtrlProductId), + .RevisionId(LcCtrlRevisionId), + .IdcodeValue(LcCtrlIdcodeValue) + ) u_lc_ctrl ( + // [10]: fatal_prog_error + // [11]: fatal_state_error + // [12]: fatal_bus_integ_error + .alert_tx_o ( alert_tx[12:10] ), + .alert_rx_i ( alert_rx[12:10] ), + + // Inter-module signals + .jtag_i(jtag_pkg::JTAG_REQ_DEFAULT), + .jtag_o(), + .esc_scrap_state0_tx_i(alert_handler_esc_tx[1]), + .esc_scrap_state0_rx_o(alert_handler_esc_rx[1]), + .esc_scrap_state1_tx_i(alert_handler_esc_tx[2]), + .esc_scrap_state1_rx_o(alert_handler_esc_rx[2]), + .pwr_lc_i(pwrmgr_aon_pwr_lc_req), + .pwr_lc_o(pwrmgr_aon_pwr_lc_rsp), + .lc_otp_vendor_test_o(lc_ctrl_lc_otp_vendor_test_req), + .lc_otp_vendor_test_i(lc_ctrl_lc_otp_vendor_test_rsp), + .otp_lc_data_i(otp_ctrl_otp_lc_data), + .lc_otp_program_o(lc_ctrl_lc_otp_program_req), + .lc_otp_program_i(lc_ctrl_lc_otp_program_rsp), + .kmac_data_o(kmac_app_req[1]), + .kmac_data_i(kmac_app_rsp[1]), + .lc_dft_en_o(lc_ctrl_lc_dft_en), + .lc_nvm_debug_en_o(), + .lc_hw_debug_en_o(lc_ctrl_lc_hw_debug_en), + .lc_cpu_en_o(lc_ctrl_lc_cpu_en), + .lc_keymgr_en_o(lc_ctrl_lc_keymgr_en), + .lc_escalate_en_o(lc_ctrl_lc_escalate_en), + .lc_clk_byp_req_o(lc_ctrl_lc_clk_byp_req), + .lc_clk_byp_ack_i(lc_ctrl_lc_clk_byp_ack), + .lc_flash_rma_req_o(lc_ctrl_lc_flash_rma_req), + .lc_flash_rma_ack_i(otbn_lc_rma_ack), + .lc_flash_rma_seed_o(), + .lc_check_byp_en_o(lc_ctrl_lc_check_byp_en), + .lc_creator_seed_sw_rw_en_o(lc_ctrl_lc_creator_seed_sw_rw_en), + .lc_owner_seed_sw_rw_en_o(lc_ctrl_lc_owner_seed_sw_rw_en), + .lc_iso_part_sw_rd_en_o(), + .lc_iso_part_sw_wr_en_o(), + .lc_seed_hw_rd_en_o(lc_ctrl_lc_seed_hw_rd_en), + .lc_keymgr_div_o(lc_ctrl_lc_keymgr_div), + .otp_device_id_i(lc_ctrl_otp_device_id), + .otp_manuf_state_i(lc_ctrl_otp_manuf_state), + .hw_rev_o(), + .strap_en_override_o(lc_ctrl_strap_en_override), + .regs_tl_i(lc_ctrl_regs_tl_req), + .regs_tl_o(lc_ctrl_regs_tl_rsp), + .dmi_tl_i(lc_ctrl_dmi_tl_req), + .dmi_tl_o(lc_ctrl_dmi_tl_rsp), + .scanmode_i, + .scan_rst_ni, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), + .clk_kmac_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_kmac_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + alert_handler #( + .RndCnstLfsrSeed(RndCnstAlertHandlerLfsrSeed), + .RndCnstLfsrPerm(RndCnstAlertHandlerLfsrPerm) + ) u_alert_handler ( + + // Interrupt + .intr_classa_o (intr_alert_handler_classa), + .intr_classb_o (intr_alert_handler_classb), + .intr_classc_o (intr_alert_handler_classc), + .intr_classd_o (intr_alert_handler_classd), + + // Inter-module signals + .crashdump_o(alert_handler_crashdump), + .edn_o(edn0_edn_req[4]), + .edn_i(edn0_edn_rsp[4]), + .esc_rx_i(alert_handler_esc_rx), + .esc_tx_o(alert_handler_esc_tx), + .tl_i(alert_handler_tl_req), + .tl_o(alert_handler_tl_rsp), + // alert signals + .alert_rx_o ( alert_rx ), + .alert_tx_i ( alert_tx ), + // synchronized clock gated / reset asserted + // indications for each alert + .lpg_cg_en_i ( lpg_cg_en ), + .lpg_rst_en_i ( lpg_rst_en ), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), + .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), + .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_io_div4_shadowed_n[rstmgr_pkg::Domain0Sel]), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + spi_host #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[13:13]) + ) u_spi_host0 ( + + // Input + .cio_sd_i (cio_spi_host0_sd_p2d), + + // Output + .cio_sck_o (cio_spi_host0_sck_d2p), + .cio_sck_en_o (cio_spi_host0_sck_en_d2p), + .cio_csb_o (cio_spi_host0_csb_d2p), + .cio_csb_en_o (cio_spi_host0_csb_en_d2p), + .cio_sd_o (cio_spi_host0_sd_d2p), + .cio_sd_en_o (cio_spi_host0_sd_en_d2p), + + // Interrupt + .intr_error_o (intr_spi_host0_error), + .intr_spi_event_o (intr_spi_host0_spi_event), + // [13]: fatal_fault + .alert_tx_o ( alert_tx[13:13] ), + .alert_rx_i ( alert_rx[13:13] ), + + // Inter-module signals + .passthrough_i(spi_device_passthrough_req), + .passthrough_o(spi_device_passthrough_rsp), + .lsio_trigger_o(spi_host0_lsio_trigger), + .tl_i(spi_host0_tl_req), + .tl_o(spi_host0_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), + .rst_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel]) + ); + pwrmgr #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[14:14]) + ) u_pwrmgr_aon ( + + // Interrupt + .intr_wakeup_o (intr_pwrmgr_aon_wakeup), + // [14]: fatal_fault + .alert_tx_o ( alert_tx[14:14] ), + .alert_rx_i ( alert_rx[14:14] ), + + // Inter-module signals + .boot_status_o(), + .pwr_ast_o(pwrmgr_ast_req_o), + .pwr_ast_i(pwrmgr_ast_rsp_i), + .pwr_rst_o(pwrmgr_aon_pwr_rst_req), + .pwr_rst_i(pwrmgr_aon_pwr_rst_rsp), + .pwr_clk_o(pwrmgr_aon_pwr_clk_req), + .pwr_clk_i(pwrmgr_aon_pwr_clk_rsp), + .pwr_otp_o(pwrmgr_aon_pwr_otp_req), + .pwr_otp_i(pwrmgr_aon_pwr_otp_rsp), + .pwr_lc_o(pwrmgr_aon_pwr_lc_req), + .pwr_lc_i(pwrmgr_aon_pwr_lc_rsp), + .pwr_flash_i(pwrmgr_pkg::PWR_FLASH_DEFAULT), + .esc_rst_tx_i(alert_handler_esc_tx[3]), + .esc_rst_rx_o(alert_handler_esc_rx[3]), + .pwr_cpu_i(rv_core_ibex_pwrmgr), + .wakeups_i(pwrmgr_aon_wakeups), + .rstreqs_i(pwrmgr_aon_rstreqs), + .ndmreset_req_i(rv_dm_ndmreset_req), + .strap_o(pwrmgr_aon_strap), + .low_power_o(pwrmgr_aon_low_power), + .rom_ctrl_i(pwrmgr_aon_rom_ctrl), + .fetch_en_o(pwrmgr_aon_fetch_en), + .lc_dft_en_i(lc_ctrl_lc_dft_en), + .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), + .sw_rst_req_i(rstmgr_aon_sw_rst_req), + .tl_i(pwrmgr_aon_tl_req), + .tl_o(pwrmgr_aon_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .clk_slow_i (clkmgr_aon_clocks.clk_aon_powerup), + .clk_lc_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_secure), + .rst_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_main_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::Domain0Sel]), + .rst_lc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_esc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_slow_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::DomainAonSel]) + ); + rstmgr #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[16:15]), + .SecCheck(SecRstmgrAonCheck), + .SecMaxSyncDelay(SecRstmgrAonMaxSyncDelay) + ) u_rstmgr_aon ( + // [15]: fatal_fault + // [16]: fatal_cnsty_fault + .alert_tx_o ( alert_tx[16:15] ), + .alert_rx_i ( alert_rx[16:15] ), + + // Inter-module signals + .por_n_i(por_n_i), + .pwr_i(pwrmgr_aon_pwr_rst_req), + .pwr_o(pwrmgr_aon_pwr_rst_rsp), + .resets_o(rstmgr_aon_resets), + .rst_en_o(rstmgr_aon_rst_en), + .alert_dump_i(alert_handler_crashdump), + .cpu_dump_i(rv_core_ibex_crash_dump), + .sw_rst_req_o(rstmgr_aon_sw_rst_req), + .tl_i(rstmgr_aon_tl_req), + .tl_o(rstmgr_aon_tl_rsp), + .scanmode_i, + .scan_rst_ni, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .clk_por_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .clk_aon_i (clkmgr_aon_clocks.clk_aon_powerup), + .clk_main_i (clkmgr_aon_clocks.clk_main_powerup), + .clk_io_i (clkmgr_aon_clocks.clk_io_powerup), + .clk_usb_i (clkmgr_aon_clocks.clk_usb_powerup), + .clk_io_div2_i (clkmgr_aon_clocks.clk_io_div2_powerup), + .clk_io_div4_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_por_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]) + ); + clkmgr #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:17]) + ) u_clkmgr_aon ( + // [17]: recov_fault + // [18]: fatal_fault + .alert_tx_o ( alert_tx[18:17] ), + .alert_rx_i ( alert_rx[18:17] ), + + // Inter-module signals + .clocks_o(clkmgr_aon_clocks), + .cg_en_o(clkmgr_aon_cg_en), + .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), + .io_clk_byp_req_o(io_clk_byp_req_o), + .io_clk_byp_ack_i(io_clk_byp_ack_i), + .all_clk_byp_req_o(all_clk_byp_req_o), + .all_clk_byp_ack_i(all_clk_byp_ack_i), + .hi_speed_sel_o(hi_speed_sel_o), + .div_step_down_req_i(div_step_down_req_i), + .lc_clk_byp_req_i(lc_ctrl_lc_clk_byp_req), + .lc_clk_byp_ack_o(lc_ctrl_lc_clk_byp_ack), + .jitter_en_o(clk_main_jitter_en_o), + .pwr_i(pwrmgr_aon_pwr_clk_req), + .pwr_o(pwrmgr_aon_pwr_clk_rsp), + .idle_i(clkmgr_aon_idle), + .calib_rdy_i(calib_rdy_i), + .tl_i(clkmgr_aon_tl_req), + .tl_o(clkmgr_aon_tl_rsp), + .scanmode_i, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .clk_main_i (clk_main_i), + .clk_io_i (clk_io_i), + .clk_usb_i (clk_usb_i), + .clk_aon_i (clk_aon_i), + .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_io_div4_shadowed_n[rstmgr_pkg::DomainAonSel]), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]), + .rst_io_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::DomainAonSel]), + .rst_io_div2_ni (rstmgr_aon_resets.rst_lc_io_div2_n[rstmgr_pkg::DomainAonSel]), + .rst_io_div4_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::DomainAonSel]), + .rst_usb_ni (rstmgr_aon_resets.rst_lc_usb_n[rstmgr_pkg::DomainAonSel]), + .rst_root_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_root_io_ni (rstmgr_aon_resets.rst_por_io_n[rstmgr_pkg::DomainAonSel]), + .rst_root_io_div2_ni (rstmgr_aon_resets.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel]), + .rst_root_io_div4_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_root_main_ni (rstmgr_aon_resets.rst_por_n[rstmgr_pkg::DomainAonSel]), + .rst_root_usb_ni (rstmgr_aon_resets.rst_por_usb_n[rstmgr_pkg::DomainAonSel]) + ); + pinmux #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:19]), + .SecVolatileRawUnlockEn(SecPinmuxAonVolatileRawUnlockEn), + .TargetCfg(PinmuxAonTargetCfg) + ) u_pinmux_aon ( + // [19]: fatal_fault + .alert_tx_o ( alert_tx[19:19] ), + .alert_rx_i ( alert_rx[19:19] ), + + // Inter-module signals + .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), + .lc_dft_en_i(lc_ctrl_lc_dft_en), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en), + .pinmux_hw_debug_en_o(), + .lc_jtag_o(), + .lc_jtag_i(jtag_pkg::JTAG_RSP_DEFAULT), + .rv_jtag_o(), + .rv_jtag_i(jtag_pkg::JTAG_RSP_DEFAULT), + .dft_jtag_o(), + .dft_jtag_i(jtag_pkg::JTAG_RSP_DEFAULT), + .dft_strap_test_o(dft_strap_test_o), + .dft_hold_tap_sel_i(dft_hold_tap_sel_i), + .sleep_en_i(pwrmgr_aon_low_power), + .strap_en_i(pwrmgr_aon_strap), + .strap_en_override_i(lc_ctrl_strap_en_override), + .pin_wkup_req_o(pwrmgr_aon_wakeups[0]), + .usbdev_dppullup_en_i('0), + .usbdev_dnpullup_en_i('0), + .usb_dppullup_en_o(), + .usb_dnpullup_en_o(), + .usb_wkup_req_o(pwrmgr_aon_wakeups[1]), + .usbdev_suspend_req_i('0), + .usbdev_wake_ack_i('0), + .usbdev_bus_not_idle_o(), + .usbdev_bus_reset_o(), + .usbdev_sense_lost_o(), + .usbdev_wake_detect_active_o(), + .tl_i(pinmux_aon_tl_req), + .tl_o(pinmux_aon_tl_rsp), + + .periph_to_mio_i (mio_d2p ), + .periph_to_mio_oe_i (mio_en_d2p ), + .mio_to_periph_o (mio_p2d ), + + .mio_attr_o, + .mio_out_o, + .mio_oe_o, + .mio_in_i, + + .periph_to_dio_i (dio_d2p ), + .periph_to_dio_oe_i (dio_en_d2p ), + .dio_to_periph_o (dio_p2d ), + + .dio_attr_o, + .dio_out_o, + .dio_oe_o, + .dio_in_i, + + .scanmode_i, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .clk_aon_i (clkmgr_aon_clocks.clk_aon_powerup), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]), + .rst_sys_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]) + ); + aon_timer #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:20]) + ) u_aon_timer_aon ( + + // Interrupt + .intr_wkup_timer_expired_o (intr_aon_timer_aon_wkup_timer_expired), + .intr_wdog_timer_bark_o (intr_aon_timer_aon_wdog_timer_bark), + // [20]: fatal_fault + .alert_tx_o ( alert_tx[20:20] ), + .alert_rx_i ( alert_rx[20:20] ), + + // Inter-module signals + .nmi_wdog_timer_bark_o(aon_timer_aon_nmi_wdog_timer_bark), + .wkup_req_o(pwrmgr_aon_wakeups[2]), + .aon_timer_rst_req_o(pwrmgr_aon_rstreqs[0]), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .sleep_mode_i(pwrmgr_aon_low_power), + .tl_i(aon_timer_aon_tl_req), + .tl_o(aon_timer_aon_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_timers), + .clk_aon_i (clkmgr_aon_clocks.clk_aon_timers), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]) + ); + sensor_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:21]) + ) u_sensor_ctrl ( + + // Interrupt + .intr_io_status_change_o (intr_sensor_ctrl_io_status_change), + .intr_init_status_change_o (intr_sensor_ctrl_init_status_change), + // [21]: recov_alert + // [22]: fatal_alert + .alert_tx_o ( alert_tx[22:21] ), + .alert_rx_i ( alert_rx[22:21] ), + + // Inter-module signals + .ast_alert_i(sensor_ctrl_ast_alert_req_i), + .ast_alert_o(sensor_ctrl_ast_alert_rsp_o), + .ast_status_i(sensor_ctrl_ast_status_i), + .ast_init_done_i(ast_init_done_i), + .wkup_req_o(pwrmgr_aon_wakeups[3]), + .tl_i(sensor_ctrl_tl_req), + .tl_o(sensor_ctrl_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), + .clk_aon_i (clkmgr_aon_clocks.clk_aon_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]) + ); + soc_proxy #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[51:23]) + ) u_soc_proxy ( + + // Input + .cio_soc_gpi_i (cio_soc_proxy_soc_gpi_p2d), + + // Output + .cio_soc_gpo_o (cio_soc_proxy_soc_gpo_d2p), + .cio_soc_gpo_en_o (cio_soc_proxy_soc_gpo_en_d2p), + + // Interrupt + .intr_external_o (intr_soc_proxy_external), + // [23]: fatal_alert_intg + // [24]: fatal_alert_external_0 + // [25]: fatal_alert_external_1 + // [26]: fatal_alert_external_2 + // [27]: fatal_alert_external_3 + // [28]: fatal_alert_external_4 + // [29]: fatal_alert_external_5 + // [30]: fatal_alert_external_6 + // [31]: fatal_alert_external_7 + // [32]: fatal_alert_external_8 + // [33]: fatal_alert_external_9 + // [34]: fatal_alert_external_10 + // [35]: fatal_alert_external_11 + // [36]: fatal_alert_external_12 + // [37]: fatal_alert_external_13 + // [38]: fatal_alert_external_14 + // [39]: fatal_alert_external_15 + // [40]: fatal_alert_external_16 + // [41]: fatal_alert_external_17 + // [42]: fatal_alert_external_18 + // [43]: fatal_alert_external_19 + // [44]: fatal_alert_external_20 + // [45]: fatal_alert_external_21 + // [46]: fatal_alert_external_22 + // [47]: fatal_alert_external_23 + // [48]: recov_alert_external_0 + // [49]: recov_alert_external_1 + // [50]: recov_alert_external_2 + // [51]: recov_alert_external_3 + .alert_tx_o ( alert_tx[51:23] ), + .alert_rx_i ( alert_rx[51:23] ), + + // Inter-module signals + .wkup_internal_req_o(pwrmgr_aon_wakeups[4]), + .wkup_external_req_o(pwrmgr_aon_wakeups[5]), + .rst_req_external_o(pwrmgr_aon_rstreqs[1]), + .ctn_tl_h2d_o(ctn_tl_h2d_o), + .ctn_tl_d2h_i(ctn_tl_d2h_i), + .i2c_lsio_trigger_i(i2c0_lsio_trigger), + .spi_host_lsio_trigger_i(spi_host0_lsio_trigger), + .uart_lsio_trigger_i(uart0_lsio_trigger), + .soc_lsio_trigger_i(soc_lsio_trigger_i), + .dma_lsio_trigger_o(dma_lsio_trigger), + .soc_fatal_alert_i(soc_fatal_alert_req_i), + .soc_fatal_alert_o(soc_fatal_alert_rsp_o), + .soc_recov_alert_i(soc_recov_alert_req_i), + .soc_recov_alert_o(soc_recov_alert_rsp_o), + .soc_wkup_async_i(soc_wkup_async_i), + .soc_rst_req_async_i(soc_rst_req_async_i), + .soc_intr_async_i(soc_intr_async_i), + .soc_gpi_async_o(soc_gpi_async_o), + .soc_gpo_async_i(soc_gpo_async_i), + .core_tl_i(soc_proxy_core_tl_req), + .core_tl_o(soc_proxy_core_tl_rsp), + .ctn_tl_i(soc_proxy_ctn_tl_req), + .ctn_tl_o(soc_proxy_ctn_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .clk_aon_i (clkmgr_aon_clocks.clk_aon_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_por_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]) + ); + sram_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:52]), + .RndCnstSramKey(RndCnstSramCtrlRetAonSramKey), + .RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce), + .RndCnstLfsrSeed(RndCnstSramCtrlRetAonLfsrSeed), + .RndCnstLfsrPerm(RndCnstSramCtrlRetAonLfsrPerm), + .MemSizeRam(4096), + .InstrExec(SramCtrlRetAonInstrExec), + .NumPrinceRoundsHalf(SramCtrlRetAonNumPrinceRoundsHalf) + ) u_sram_ctrl_ret_aon ( + // [52]: fatal_error + .alert_tx_o ( alert_tx[52:52] ), + .alert_rx_i ( alert_rx[52:52] ), + + // Inter-module signals + .sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]), + .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[1]), + .cfg_i(ast_ram_1p_cfg), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_hw_debug_en_i(lc_ctrl_pkg::Off), + .otp_en_sram_ifetch_i(prim_mubi_pkg::MuBi8False), + .regs_tl_i(sram_ctrl_ret_aon_regs_tl_req), + .regs_tl_o(sram_ctrl_ret_aon_regs_tl_rsp), + .ram_tl_i(sram_ctrl_ret_aon_ram_tl_req), + .ram_tl_o(sram_ctrl_ret_aon_ram_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_infra), + .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]) + ); + rv_dm #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[53:53]), + .IdcodeValue(RvDmIdcodeValue), + .UseDmiInterface(RvDmUseDmiInterface), + .SecVolatileRawUnlockEn(SecRvDmVolatileRawUnlockEn) + ) u_rv_dm ( + // [53]: fatal_fault + .alert_tx_o ( alert_tx[53:53] ), + .alert_rx_i ( alert_rx[53:53] ), + + // Inter-module signals + .next_dm_addr_i(rv_dm_next_dm_addr_i), + .jtag_i(jtag_pkg::JTAG_REQ_DEFAULT), + .jtag_o(), + .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), + .lc_dft_en_i(lc_ctrl_pkg::Off), + .pinmux_hw_debug_en_i(lc_ctrl_pkg::Off), + .otp_dis_rv_dm_late_debug_i(prim_mubi_pkg::MuBi8False), + .unavailable_i(1'b0), + .ndmreset_req_o(rv_dm_ndmreset_req), + .dmactive_o(), + .debug_req_o(rv_dm_debug_req), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en), + .strap_en_i(pwrmgr_aon_strap), + .strap_en_override_i(lc_ctrl_strap_en_override), + .sba_tl_h_o(main_tl_rv_dm__sba_req), + .sba_tl_h_i(main_tl_rv_dm__sba_rsp), + .regs_tl_d_i(rv_dm_regs_tl_d_req), + .regs_tl_d_o(rv_dm_regs_tl_d_rsp), + .mem_tl_d_i(rv_dm_mem_tl_d_req), + .mem_tl_d_o(rv_dm_mem_tl_d_rsp), + .dbg_tl_d_i(rv_dm_dbg_tl_d_req), + .dbg_tl_d_o(rv_dm_dbg_tl_d_rsp), + .scanmode_i, + .scan_rst_ni, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .clk_lc_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]), + .rst_lc_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + rv_plic #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:54]) + ) u_rv_plic ( + // [54]: fatal_fault + .alert_tx_o ( alert_tx[54:54] ), + .alert_rx_i ( alert_rx[54:54] ), + + // Inter-module signals + .irq_o(rv_plic_irq), + .irq_id_o(), + .msip_o(rv_plic_msip), + .tl_i(rv_plic_tl_req), + .tl_o(rv_plic_tl_rsp), + .intr_src_i (intr_vector), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + aes #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:55]), + .AES192Enable(1'b1), + .SecMasking(SecAesMasking), + .SecSBoxImpl(SecAesSBoxImpl), + .SecStartTriggerDelay(SecAesStartTriggerDelay), + .SecAllowForcingMasks(SecAesAllowForcingMasks), + .SecSkipPRNGReseeding(SecAesSkipPRNGReseeding), + .RndCnstClearingLfsrSeed(RndCnstAesClearingLfsrSeed), + .RndCnstClearingLfsrPerm(RndCnstAesClearingLfsrPerm), + .RndCnstClearingSharePerm(RndCnstAesClearingSharePerm), + .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed), + .RndCnstMaskingLfsrPerm(RndCnstAesMaskingLfsrPerm) + ) u_aes ( + // [55]: recov_ctrl_update_err + // [56]: fatal_fault + .alert_tx_o ( alert_tx[56:55] ), + .alert_rx_i ( alert_rx[56:55] ), + + // Inter-module signals + .idle_o(clkmgr_aon_idle[0]), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .edn_o(edn0_edn_req[5]), + .edn_i(edn0_edn_rsp[5]), + .keymgr_key_i(keymgr_dpe_aes_key), + .tl_i(aes_tl_req), + .tl_o(aes_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_aes), + .clk_edn_i (clkmgr_aon_clocks.clk_main_aes), + .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + hmac #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[57:57]) + ) u_hmac ( + + // Interrupt + .intr_hmac_done_o (intr_hmac_hmac_done), + .intr_fifo_empty_o (intr_hmac_fifo_empty), + .intr_hmac_err_o (intr_hmac_hmac_err), + // [57]: fatal_fault + .alert_tx_o ( alert_tx[57:57] ), + .alert_rx_i ( alert_rx[57:57] ), + + // Inter-module signals + .idle_o(clkmgr_aon_idle[1]), + .tl_i(hmac_tl_req), + .tl_o(hmac_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_hmac), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + kmac #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:58]), + .EnMasking(KmacEnMasking), + .SwKeyMasked(KmacSwKeyMasked), + .SecCmdDelay(SecKmacCmdDelay), + .SecIdleAcceptSwMsg(SecKmacIdleAcceptSwMsg), + .NumAppIntf(KmacNumAppIntf), + .AppCfg(KmacAppCfg), + .RndCnstLfsrSeed(RndCnstKmacLfsrSeed), + .RndCnstLfsrPerm(RndCnstKmacLfsrPerm), + .RndCnstBufferLfsrSeed(RndCnstKmacBufferLfsrSeed), + .RndCnstMsgPerm(RndCnstKmacMsgPerm) + ) u_kmac ( + + // Interrupt + .intr_kmac_done_o (intr_kmac_kmac_done), + .intr_fifo_empty_o (intr_kmac_fifo_empty), + .intr_kmac_err_o (intr_kmac_kmac_err), + // [58]: recov_operation_err + // [59]: fatal_fault_err + .alert_tx_o ( alert_tx[59:58] ), + .alert_rx_i ( alert_rx[59:58] ), + + // Inter-module signals + .keymgr_key_i(keymgr_dpe_kmac_key), + .app_i(kmac_app_req), + .app_o(kmac_app_rsp), + .entropy_o(edn0_edn_req[3]), + .entropy_i(edn0_edn_rsp[3]), + .idle_o(clkmgr_aon_idle[2]), + .en_masking_o(kmac_en_masking), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .tl_i(kmac_tl_req), + .tl_o(kmac_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_kmac), + .clk_edn_i (clkmgr_aon_clocks.clk_main_kmac), + .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + otbn #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[61:60]), + .Stub(OtbnStub), + .RegFile(OtbnRegFile), + .RndCnstUrndPrngSeed(RndCnstOtbnUrndPrngSeed), + .SecMuteUrnd(SecOtbnMuteUrnd), + .SecSkipUrndReseedAtStart(SecOtbnSkipUrndReseedAtStart), + .RndCnstOtbnKey(RndCnstOtbnOtbnKey), + .RndCnstOtbnNonce(RndCnstOtbnOtbnNonce) + ) u_otbn ( + + // Interrupt + .intr_done_o (intr_otbn_done), + // [60]: fatal + // [61]: recov + .alert_tx_o ( alert_tx[61:60] ), + .alert_rx_i ( alert_rx[61:60] ), + + // Inter-module signals + .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req), + .otbn_otp_key_i(otp_ctrl_otbn_otp_key_rsp), + .edn_rnd_o(edn1_edn_req[0]), + .edn_rnd_i(edn1_edn_rsp[0]), + .edn_urnd_o(edn0_edn_req[6]), + .edn_urnd_i(edn0_edn_rsp[6]), + .idle_o(clkmgr_aon_idle[3]), + .ram_cfg_i(ast_ram_1p_cfg), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_rma_req_i(lc_ctrl_lc_flash_rma_req), + .lc_rma_ack_o(otbn_lc_rma_ack), + .keymgr_key_i(keymgr_dpe_otbn_key), + .tl_i(otbn_tl_req), + .tl_o(otbn_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_otbn), + .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), + .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + keymgr_dpe #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[63:62]), + .KmacEnMasking(KeymgrDpeKmacEnMasking), + .RndCnstLfsrSeed(RndCnstKeymgrDpeLfsrSeed), + .RndCnstLfsrPerm(RndCnstKeymgrDpeLfsrPerm), + .RndCnstRandPerm(RndCnstKeymgrDpeRandPerm), + .RndCnstRevisionSeed(RndCnstKeymgrDpeRevisionSeed), + .RndCnstSoftOutputSeed(RndCnstKeymgrDpeSoftOutputSeed), + .RndCnstHardOutputSeed(RndCnstKeymgrDpeHardOutputSeed), + .RndCnstAesSeed(RndCnstKeymgrDpeAesSeed), + .RndCnstKmacSeed(RndCnstKeymgrDpeKmacSeed), + .RndCnstOtbnSeed(RndCnstKeymgrDpeOtbnSeed), + .RndCnstNoneSeed(RndCnstKeymgrDpeNoneSeed) + ) u_keymgr_dpe ( + + // Interrupt + .intr_op_done_o (intr_keymgr_dpe_op_done), + // [62]: recov_operation_err + // [63]: fatal_fault_err + .alert_tx_o ( alert_tx[63:62] ), + .alert_rx_i ( alert_rx[63:62] ), + + // Inter-module signals + .edn_o(edn0_edn_req[0]), + .edn_i(edn0_edn_rsp[0]), + .aes_key_o(keymgr_dpe_aes_key), + .kmac_key_o(keymgr_dpe_kmac_key), + .otbn_key_o(keymgr_dpe_otbn_key), + .kmac_data_o(kmac_app_req[0]), + .kmac_data_i(kmac_app_rsp[0]), + .otp_key_i(otp_ctrl_otp_keymgr_key), + .otp_device_id_i(keymgr_dpe_otp_device_id), + .lc_keymgr_en_i(lc_ctrl_lc_keymgr_en), + .lc_keymgr_div_i(lc_ctrl_lc_keymgr_div), + .rom_digest_i(keymgr_dpe_rom_digest), + .kmac_en_masking_i(kmac_en_masking), + .tl_i(keymgr_dpe_tl_req), + .tl_o(keymgr_dpe_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_secure), + .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), + .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + csrng #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[65:64]), + .RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction), + .RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction), + .SBoxImpl(CsrngSBoxImpl) + ) u_csrng ( + + // Interrupt + .intr_cs_cmd_req_done_o (intr_csrng_cs_cmd_req_done), + .intr_cs_entropy_req_o (intr_csrng_cs_entropy_req), + .intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc), + .intr_cs_fatal_err_o (intr_csrng_cs_fatal_err), + // [64]: recov_alert + // [65]: fatal_alert + .alert_tx_o ( alert_tx[65:64] ), + .alert_rx_i ( alert_rx[65:64] ), + + // Inter-module signals + .csrng_cmd_i(csrng_csrng_cmd_req), + .csrng_cmd_o(csrng_csrng_cmd_rsp), + .entropy_src_hw_if_o(entropy_src_hw_if_req_o), + .entropy_src_hw_if_i(entropy_src_hw_if_rsp_i), + .cs_aes_halt_i(entropy_src_pkg::CS_AES_HALT_REQ_DEFAULT), + .cs_aes_halt_o(), + .otp_en_csrng_sw_app_read_i(prim_mubi_pkg::MuBi8True), + .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), + .tl_i(csrng_tl_req), + .tl_o(csrng_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + edn #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[67:66]) + ) u_edn0 ( + + // Interrupt + .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done), + .intr_edn_fatal_err_o (intr_edn0_edn_fatal_err), + // [66]: recov_alert + // [67]: fatal_alert + .alert_tx_o ( alert_tx[67:66] ), + .alert_rx_i ( alert_rx[67:66] ), + + // Inter-module signals + .csrng_cmd_o(csrng_csrng_cmd_req[0]), + .csrng_cmd_i(csrng_csrng_cmd_rsp[0]), + .edn_i(edn0_edn_req), + .edn_o(edn0_edn_rsp), + .tl_i(edn0_tl_req), + .tl_o(edn0_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + edn #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[69:68]) + ) u_edn1 ( + + // Interrupt + .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done), + .intr_edn_fatal_err_o (intr_edn1_edn_fatal_err), + // [68]: recov_alert + // [69]: fatal_alert + .alert_tx_o ( alert_tx[69:68] ), + .alert_rx_i ( alert_rx[69:68] ), + + // Inter-module signals + .csrng_cmd_o(csrng_csrng_cmd_req[1]), + .csrng_cmd_i(csrng_csrng_cmd_rsp[1]), + .edn_i(edn1_edn_req), + .edn_o(edn1_edn_rsp), + .tl_i(edn1_tl_req), + .tl_o(edn1_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + sram_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[70:70]), + .RndCnstSramKey(RndCnstSramCtrlMainSramKey), + .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce), + .RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed), + .RndCnstLfsrPerm(RndCnstSramCtrlMainLfsrPerm), + .MemSizeRam(65536), + .InstrExec(SramCtrlMainInstrExec), + .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf) + ) u_sram_ctrl_main ( + // [70]: fatal_error + .alert_tx_o ( alert_tx[70:70] ), + .alert_rx_i ( alert_rx[70:70] ), + + // Inter-module signals + .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]), + .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[0]), + .cfg_i(ast_ram_1p_cfg), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), + .otp_en_sram_ifetch_i(sram_ctrl_main_otp_en_sram_ifetch), + .regs_tl_i(sram_ctrl_main_regs_tl_req), + .regs_tl_o(sram_ctrl_main_regs_tl_rsp), + .ram_tl_i(sram_ctrl_main_ram_tl_req), + .ram_tl_o(sram_ctrl_main_ram_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + sram_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[71:71]), + .RndCnstSramKey(RndCnstSramCtrlMboxSramKey), + .RndCnstSramNonce(RndCnstSramCtrlMboxSramNonce), + .RndCnstLfsrSeed(RndCnstSramCtrlMboxLfsrSeed), + .RndCnstLfsrPerm(RndCnstSramCtrlMboxLfsrPerm), + .MemSizeRam(4096), + .InstrExec(SramCtrlMboxInstrExec), + .NumPrinceRoundsHalf(SramCtrlMboxNumPrinceRoundsHalf) + ) u_sram_ctrl_mbox ( + // [71]: fatal_error + .alert_tx_o ( alert_tx[71:71] ), + .alert_rx_i ( alert_rx[71:71] ), + + // Inter-module signals + .sram_otp_key_o(otp_ctrl_sram_otp_key_req[2]), + .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[2]), + .cfg_i(ast_ram_1p_cfg), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_hw_debug_en_i(lc_ctrl_pkg::Off), + .otp_en_sram_ifetch_i(prim_mubi_pkg::MuBi8False), + .regs_tl_i(sram_ctrl_mbox_regs_tl_req), + .regs_tl_o(sram_ctrl_mbox_regs_tl_rsp), + .ram_tl_i(sram_ctrl_mbox_ram_tl_req), + .ram_tl_o(sram_ctrl_mbox_ram_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + rom_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[72:72]), + .BootRomInitFile(RomCtrl0BootRomInitFile), + .RndCnstScrNonce(RndCnstRomCtrl0ScrNonce), + .RndCnstScrKey(RndCnstRomCtrl0ScrKey), + .SecDisableScrambling(SecRomCtrl0DisableScrambling), + .MemSizeRom(32768) + ) u_rom_ctrl0 ( + // [72]: fatal + .alert_tx_o ( alert_tx[72:72] ), + .alert_rx_i ( alert_rx[72:72] ), + + // Inter-module signals + .rom_cfg_i(ast_rom_cfg), + .pwrmgr_data_o(pwrmgr_aon_rom_ctrl), + .keymgr_data_o(keymgr_dpe_rom_digest[0]), + .kmac_data_o(kmac_app_req[2]), + .kmac_data_i(kmac_app_rsp[2]), + .regs_tl_i(rom_ctrl0_regs_tl_req), + .regs_tl_o(rom_ctrl0_regs_tl_rsp), + .rom_tl_i(rom_ctrl0_rom_tl_req), + .rom_tl_o(rom_ctrl0_rom_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + rom_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[73:73]), + .BootRomInitFile(RomCtrl1BootRomInitFile), + .RndCnstScrNonce(RndCnstRomCtrl1ScrNonce), + .RndCnstScrKey(RndCnstRomCtrl1ScrKey), + .SecDisableScrambling(SecRomCtrl1DisableScrambling), + .MemSizeRom(65536) + ) u_rom_ctrl1 ( + // [73]: fatal + .alert_tx_o ( alert_tx[73:73] ), + .alert_rx_i ( alert_rx[73:73] ), + + // Inter-module signals + .rom_cfg_i(ast_rom_cfg), + .pwrmgr_data_o(pwrmgr_aon_rom_ctrl), + .keymgr_data_o(keymgr_dpe_rom_digest[1]), + .kmac_data_o(kmac_app_req[3]), + .kmac_data_i(kmac_app_rsp[3]), + .regs_tl_i(rom_ctrl1_regs_tl_req), + .regs_tl_o(rom_ctrl1_regs_tl_rsp), + .rom_tl_i(rom_ctrl1_rom_tl_req), + .rom_tl_o(rom_ctrl1_rom_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + dma #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[74:74]), + .EnableDataIntgGen(DmaEnableDataIntgGen), + .EnableRspDataIntgCheck(DmaEnableRspDataIntgCheck), + .TlUserRsvd(DmaTlUserRsvd), + .SysRacl(DmaSysRacl), + .OtAgentId(DmaOtAgentId) + ) u_dma ( + + // Interrupt + .intr_dma_done_o (intr_dma_dma_done), + .intr_dma_chunk_done_o (intr_dma_dma_chunk_done), + .intr_dma_error_o (intr_dma_dma_error), + // [74]: fatal_fault + .alert_tx_o ( alert_tx[74:74] ), + .alert_rx_i ( alert_rx[74:74] ), + + // Inter-module signals + .lsio_trigger_i(dma_lsio_trigger), + .sys_o(dma_sys_req_o), + .sys_i(dma_sys_rsp_i), + .ctn_tl_h2d_o(dma_ctn_tl_h2d_o), + .ctn_tl_d2h_i(dma_ctn_tl_d2h_i), + .host_tl_h_o(main_tl_dma__host_req), + .host_tl_h_i(main_tl_dma__host_rsp), + .tl_d_i(dma_tl_d_req), + .tl_d_o(dma_tl_d_rsp), + .scanmode_i, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[76:75]) + ) u_mbx0 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx0_mbx_ready), + .intr_mbx_abort_o (intr_mbx0_mbx_abort), + .intr_mbx_error_o (intr_mbx0_mbx_error), + // [75]: fatal_fault + // [76]: recov_fault + .alert_tx_o ( alert_tx[76:75] ), + .alert_rx_i ( alert_rx[76:75] ), + + // Inter-module signals + .doe_intr_support_o(mbx0_doe_intr_support_o), + .doe_intr_en_o(mbx0_doe_intr_en_o), + .doe_intr_o(mbx0_doe_intr_o), + .doe_async_msg_support_o(mbx0_doe_async_msg_support_o), + .sram_tl_h_o(main_tl_mbx0__sram_req), + .sram_tl_h_i(main_tl_mbx0__sram_rsp), + .core_tl_d_i(mbx0_core_tl_d_req), + .core_tl_d_o(mbx0_core_tl_d_rsp), + .soc_tl_d_i(mbx0_soc_tl_d_req), + .soc_tl_d_o(mbx0_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[78:77]) + ) u_mbx1 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx1_mbx_ready), + .intr_mbx_abort_o (intr_mbx1_mbx_abort), + .intr_mbx_error_o (intr_mbx1_mbx_error), + // [77]: fatal_fault + // [78]: recov_fault + .alert_tx_o ( alert_tx[78:77] ), + .alert_rx_i ( alert_rx[78:77] ), + + // Inter-module signals + .doe_intr_support_o(mbx1_doe_intr_support_o), + .doe_intr_en_o(mbx1_doe_intr_en_o), + .doe_intr_o(mbx1_doe_intr_o), + .doe_async_msg_support_o(mbx1_doe_async_msg_support_o), + .sram_tl_h_o(main_tl_mbx1__sram_req), + .sram_tl_h_i(main_tl_mbx1__sram_rsp), + .core_tl_d_i(mbx1_core_tl_d_req), + .core_tl_d_o(mbx1_core_tl_d_rsp), + .soc_tl_d_i(mbx1_soc_tl_d_req), + .soc_tl_d_o(mbx1_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[80:79]) + ) u_mbx2 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx2_mbx_ready), + .intr_mbx_abort_o (intr_mbx2_mbx_abort), + .intr_mbx_error_o (intr_mbx2_mbx_error), + // [79]: fatal_fault + // [80]: recov_fault + .alert_tx_o ( alert_tx[80:79] ), + .alert_rx_i ( alert_rx[80:79] ), + + // Inter-module signals + .doe_intr_support_o(mbx2_doe_intr_support_o), + .doe_intr_en_o(mbx2_doe_intr_en_o), + .doe_intr_o(mbx2_doe_intr_o), + .doe_async_msg_support_o(mbx2_doe_async_msg_support_o), + .sram_tl_h_o(main_tl_mbx2__sram_req), + .sram_tl_h_i(main_tl_mbx2__sram_rsp), + .core_tl_d_i(mbx2_core_tl_d_req), + .core_tl_d_o(mbx2_core_tl_d_rsp), + .soc_tl_d_i(mbx2_soc_tl_d_req), + .soc_tl_d_o(mbx2_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[82:81]) + ) u_mbx3 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx3_mbx_ready), + .intr_mbx_abort_o (intr_mbx3_mbx_abort), + .intr_mbx_error_o (intr_mbx3_mbx_error), + // [81]: fatal_fault + // [82]: recov_fault + .alert_tx_o ( alert_tx[82:81] ), + .alert_rx_i ( alert_rx[82:81] ), + + // Inter-module signals + .doe_intr_support_o(mbx3_doe_intr_support_o), + .doe_intr_en_o(mbx3_doe_intr_en_o), + .doe_intr_o(mbx3_doe_intr_o), + .doe_async_msg_support_o(mbx3_doe_async_msg_support_o), + .sram_tl_h_o(main_tl_mbx3__sram_req), + .sram_tl_h_i(main_tl_mbx3__sram_rsp), + .core_tl_d_i(mbx3_core_tl_d_req), + .core_tl_d_o(mbx3_core_tl_d_rsp), + .soc_tl_d_i(mbx3_soc_tl_d_req), + .soc_tl_d_o(mbx3_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[84:83]) + ) u_mbx4 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx4_mbx_ready), + .intr_mbx_abort_o (intr_mbx4_mbx_abort), + .intr_mbx_error_o (intr_mbx4_mbx_error), + // [83]: fatal_fault + // [84]: recov_fault + .alert_tx_o ( alert_tx[84:83] ), + .alert_rx_i ( alert_rx[84:83] ), + + // Inter-module signals + .doe_intr_support_o(mbx4_doe_intr_support_o), + .doe_intr_en_o(mbx4_doe_intr_en_o), + .doe_intr_o(mbx4_doe_intr_o), + .doe_async_msg_support_o(mbx4_doe_async_msg_support_o), + .sram_tl_h_o(main_tl_mbx4__sram_req), + .sram_tl_h_i(main_tl_mbx4__sram_rsp), + .core_tl_d_i(mbx4_core_tl_d_req), + .core_tl_d_o(mbx4_core_tl_d_rsp), + .soc_tl_d_i(mbx4_soc_tl_d_req), + .soc_tl_d_o(mbx4_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[86:85]) + ) u_mbx5 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx5_mbx_ready), + .intr_mbx_abort_o (intr_mbx5_mbx_abort), + .intr_mbx_error_o (intr_mbx5_mbx_error), + // [85]: fatal_fault + // [86]: recov_fault + .alert_tx_o ( alert_tx[86:85] ), + .alert_rx_i ( alert_rx[86:85] ), + + // Inter-module signals + .doe_intr_support_o(mbx5_doe_intr_support_o), + .doe_intr_en_o(mbx5_doe_intr_en_o), + .doe_intr_o(mbx5_doe_intr_o), + .doe_async_msg_support_o(mbx5_doe_async_msg_support_o), + .sram_tl_h_o(main_tl_mbx5__sram_req), + .sram_tl_h_i(main_tl_mbx5__sram_rsp), + .core_tl_d_i(mbx5_core_tl_d_req), + .core_tl_d_o(mbx5_core_tl_d_rsp), + .soc_tl_d_i(mbx5_soc_tl_d_req), + .soc_tl_d_o(mbx5_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[88:87]) + ) u_mbx6 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx6_mbx_ready), + .intr_mbx_abort_o (intr_mbx6_mbx_abort), + .intr_mbx_error_o (intr_mbx6_mbx_error), + // [87]: fatal_fault + // [88]: recov_fault + .alert_tx_o ( alert_tx[88:87] ), + .alert_rx_i ( alert_rx[88:87] ), + + // Inter-module signals + .doe_intr_support_o(mbx6_doe_intr_support_o), + .doe_intr_en_o(mbx6_doe_intr_en_o), + .doe_intr_o(mbx6_doe_intr_o), + .doe_async_msg_support_o(mbx6_doe_async_msg_support_o), + .sram_tl_h_o(main_tl_mbx6__sram_req), + .sram_tl_h_i(main_tl_mbx6__sram_rsp), + .core_tl_d_i(mbx6_core_tl_d_req), + .core_tl_d_o(mbx6_core_tl_d_rsp), + .soc_tl_d_i(mbx6_soc_tl_d_req), + .soc_tl_d_o(mbx6_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[90:89]) + ) u_mbx_jtag ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx_jtag_mbx_ready), + .intr_mbx_abort_o (intr_mbx_jtag_mbx_abort), + .intr_mbx_error_o (intr_mbx_jtag_mbx_error), + // [89]: fatal_fault + // [90]: recov_fault + .alert_tx_o ( alert_tx[90:89] ), + .alert_rx_i ( alert_rx[90:89] ), + + // Inter-module signals + .doe_intr_support_o(mbx_jtag_doe_intr_support_o), + .doe_intr_en_o(mbx_jtag_doe_intr_en_o), + .doe_intr_o(mbx_jtag_doe_intr_o), + .doe_async_msg_support_o(mbx_jtag_doe_async_msg_support_o), + .sram_tl_h_o(main_tl_mbx_jtag__sram_req), + .sram_tl_h_i(main_tl_mbx_jtag__sram_rsp), + .core_tl_d_i(mbx_jtag_core_tl_d_req), + .core_tl_d_o(mbx_jtag_core_tl_d_rsp), + .soc_tl_d_i(mbx_jtag_soc_tl_d_req), + .soc_tl_d_o(mbx_jtag_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[92:91]) + ) u_mbx_pcie0 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx_pcie0_mbx_ready), + .intr_mbx_abort_o (intr_mbx_pcie0_mbx_abort), + .intr_mbx_error_o (intr_mbx_pcie0_mbx_error), + // [91]: fatal_fault + // [92]: recov_fault + .alert_tx_o ( alert_tx[92:91] ), + .alert_rx_i ( alert_rx[92:91] ), + + // Inter-module signals + .doe_intr_support_o(mbx_pcie0_doe_intr_support_o), + .doe_intr_en_o(mbx_pcie0_doe_intr_en_o), + .doe_intr_o(mbx_pcie0_doe_intr_o), + .doe_async_msg_support_o(mbx_pcie0_doe_async_msg_support_o), + .sram_tl_h_o(main_tl_mbx_pcie0__sram_req), + .sram_tl_h_i(main_tl_mbx_pcie0__sram_rsp), + .core_tl_d_i(mbx_pcie0_core_tl_d_req), + .core_tl_d_o(mbx_pcie0_core_tl_d_rsp), + .soc_tl_d_i(mbx_pcie0_soc_tl_d_req), + .soc_tl_d_o(mbx_pcie0_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[94:93]) + ) u_mbx_pcie1 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx_pcie1_mbx_ready), + .intr_mbx_abort_o (intr_mbx_pcie1_mbx_abort), + .intr_mbx_error_o (intr_mbx_pcie1_mbx_error), + // [93]: fatal_fault + // [94]: recov_fault + .alert_tx_o ( alert_tx[94:93] ), + .alert_rx_i ( alert_rx[94:93] ), + + // Inter-module signals + .doe_intr_support_o(mbx_pcie1_doe_intr_support_o), + .doe_intr_en_o(mbx_pcie1_doe_intr_en_o), + .doe_intr_o(mbx_pcie1_doe_intr_o), + .doe_async_msg_support_o(mbx_pcie1_doe_async_msg_support_o), + .sram_tl_h_o(main_tl_mbx_pcie1__sram_req), + .sram_tl_h_i(main_tl_mbx_pcie1__sram_rsp), + .core_tl_d_i(mbx_pcie1_core_tl_d_req), + .core_tl_d_o(mbx_pcie1_core_tl_d_rsp), + .soc_tl_d_i(mbx_pcie1_soc_tl_d_req), + .soc_tl_d_o(mbx_pcie1_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + rv_core_ibex #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[98:95]), + .RndCnstLfsrSeed(RndCnstRvCoreIbexLfsrSeed), + .RndCnstLfsrPerm(RndCnstRvCoreIbexLfsrPerm), + .RndCnstIbexKeyDefault(RndCnstRvCoreIbexIbexKeyDefault), + .RndCnstIbexNonceDefault(RndCnstRvCoreIbexIbexNonceDefault), + .PMPEnable(RvCoreIbexPMPEnable), + .PMPGranularity(RvCoreIbexPMPGranularity), + .PMPNumRegions(RvCoreIbexPMPNumRegions), + .MHPMCounterNum(RvCoreIbexMHPMCounterNum), + .MHPMCounterWidth(RvCoreIbexMHPMCounterWidth), + .PMPRstCfg(RvCoreIbexPMPRstCfg), + .PMPRstAddr(RvCoreIbexPMPRstAddr), + .PMPRstMsecCfg(RvCoreIbexPMPRstMsecCfg), + .RV32E(RvCoreIbexRV32E), + .RV32M(RvCoreIbexRV32M), + .RV32B(RvCoreIbexRV32B), + .RegFile(RvCoreIbexRegFile), + .BranchTargetALU(RvCoreIbexBranchTargetALU), + .WritebackStage(RvCoreIbexWritebackStage), + .ICache(RvCoreIbexICache), + .ICacheECC(RvCoreIbexICacheECC), + .ICacheScramble(RvCoreIbexICacheScramble), + .BranchPredictor(RvCoreIbexBranchPredictor), + .DbgTriggerEn(RvCoreIbexDbgTriggerEn), + .DbgHwBreakNum(RvCoreIbexDbgHwBreakNum), + .SecureIbex(RvCoreIbexSecureIbex), + .DmHaltAddr(RvCoreIbexDmHaltAddr), + .DmExceptionAddr(RvCoreIbexDmExceptionAddr), + .PipeLine(RvCoreIbexPipeLine) + ) u_rv_core_ibex ( + // [95]: fatal_sw_err + // [96]: recov_sw_err + // [97]: fatal_hw_err + // [98]: recov_hw_err + .alert_tx_o ( alert_tx[98:95] ), + .alert_rx_i ( alert_rx[98:95] ), + + // Inter-module signals + .rst_cpu_n_o(), + .ram_cfg_i(ast_ram_1p_cfg), + .hart_id_i(rv_core_ibex_hart_id), + .boot_addr_i(rv_core_ibex_boot_addr), + .irq_software_i(rv_plic_msip), + .irq_timer_i(rv_core_ibex_irq_timer), + .irq_external_i(rv_plic_irq), + .esc_tx_i(alert_handler_esc_tx[0]), + .esc_rx_o(alert_handler_esc_rx[0]), + .debug_req_i(rv_dm_debug_req), + .crash_dump_o(rv_core_ibex_crash_dump), + .lc_cpu_en_i(lc_ctrl_lc_cpu_en), + .pwrmgr_cpu_en_i(pwrmgr_aon_fetch_en), + .pwrmgr_o(rv_core_ibex_pwrmgr), + .nmi_wdog_i(aon_timer_aon_nmi_wdog_timer_bark), + .edn_o(edn0_edn_req[7]), + .edn_i(edn0_edn_rsp[7]), + .icache_otp_key_o(otp_ctrl_sram_otp_key_req[3]), + .icache_otp_key_i(otp_ctrl_sram_otp_key_rsp[3]), + .fpga_info_i(fpga_info_i), + .corei_tl_h_o(main_tl_rv_core_ibex__corei_req), + .corei_tl_h_i(main_tl_rv_core_ibex__corei_rsp), + .cored_tl_h_o(main_tl_rv_core_ibex__cored_req), + .cored_tl_h_i(main_tl_rv_core_ibex__cored_rsp), + .cfg_tl_d_i(rv_core_ibex_cfg_tl_d_req), + .cfg_tl_d_o(rv_core_ibex_cfg_tl_d_rsp), + .scanmode_i, + .scan_rst_ni, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .clk_edn_i (clkmgr_aon_clocks.clk_main_infra), + .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_secure), + .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_esc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + // interrupt assignments + assign intr_vector = { + intr_mbx_pcie1_mbx_error, // IDs [159 +: 1] + intr_mbx_pcie1_mbx_abort, // IDs [158 +: 1] + intr_mbx_pcie1_mbx_ready, // IDs [157 +: 1] + intr_mbx_pcie0_mbx_error, // IDs [156 +: 1] + intr_mbx_pcie0_mbx_abort, // IDs [155 +: 1] + intr_mbx_pcie0_mbx_ready, // IDs [154 +: 1] + intr_mbx_jtag_mbx_error, // IDs [153 +: 1] + intr_mbx_jtag_mbx_abort, // IDs [152 +: 1] + intr_mbx_jtag_mbx_ready, // IDs [151 +: 1] + intr_mbx6_mbx_error, // IDs [150 +: 1] + intr_mbx6_mbx_abort, // IDs [149 +: 1] + intr_mbx6_mbx_ready, // IDs [148 +: 1] + intr_mbx5_mbx_error, // IDs [147 +: 1] + intr_mbx5_mbx_abort, // IDs [146 +: 1] + intr_mbx5_mbx_ready, // IDs [145 +: 1] + intr_mbx4_mbx_error, // IDs [144 +: 1] + intr_mbx4_mbx_abort, // IDs [143 +: 1] + intr_mbx4_mbx_ready, // IDs [142 +: 1] + intr_mbx3_mbx_error, // IDs [141 +: 1] + intr_mbx3_mbx_abort, // IDs [140 +: 1] + intr_mbx3_mbx_ready, // IDs [139 +: 1] + intr_mbx2_mbx_error, // IDs [138 +: 1] + intr_mbx2_mbx_abort, // IDs [137 +: 1] + intr_mbx2_mbx_ready, // IDs [136 +: 1] + intr_mbx1_mbx_error, // IDs [135 +: 1] + intr_mbx1_mbx_abort, // IDs [134 +: 1] + intr_mbx1_mbx_ready, // IDs [133 +: 1] + intr_mbx0_mbx_error, // IDs [132 +: 1] + intr_mbx0_mbx_abort, // IDs [131 +: 1] + intr_mbx0_mbx_ready, // IDs [130 +: 1] + intr_dma_dma_error, // IDs [129 +: 1] + intr_dma_dma_chunk_done, // IDs [128 +: 1] + intr_dma_dma_done, // IDs [127 +: 1] + intr_edn1_edn_fatal_err, // IDs [126 +: 1] + intr_edn1_edn_cmd_req_done, // IDs [125 +: 1] + intr_edn0_edn_fatal_err, // IDs [124 +: 1] + intr_edn0_edn_cmd_req_done, // IDs [123 +: 1] + intr_csrng_cs_fatal_err, // IDs [122 +: 1] + intr_csrng_cs_hw_inst_exc, // IDs [121 +: 1] + intr_csrng_cs_entropy_req, // IDs [120 +: 1] + intr_csrng_cs_cmd_req_done, // IDs [119 +: 1] + intr_keymgr_dpe_op_done, // IDs [118 +: 1] + intr_otbn_done, // IDs [117 +: 1] + intr_kmac_kmac_err, // IDs [116 +: 1] + intr_kmac_fifo_empty, // IDs [115 +: 1] + intr_kmac_kmac_done, // IDs [114 +: 1] + intr_hmac_hmac_err, // IDs [113 +: 1] + intr_hmac_fifo_empty, // IDs [112 +: 1] + intr_hmac_hmac_done, // IDs [111 +: 1] + intr_soc_proxy_external, // IDs [79 +: 32] + intr_sensor_ctrl_init_status_change, // IDs [78 +: 1] + intr_sensor_ctrl_io_status_change, // IDs [77 +: 1] + intr_aon_timer_aon_wdog_timer_bark, // IDs [76 +: 1] + intr_aon_timer_aon_wkup_timer_expired, // IDs [75 +: 1] + intr_pwrmgr_aon_wakeup, // IDs [74 +: 1] + intr_spi_host0_spi_event, // IDs [73 +: 1] + intr_spi_host0_error, // IDs [72 +: 1] + intr_alert_handler_classd, // IDs [71 +: 1] + intr_alert_handler_classc, // IDs [70 +: 1] + intr_alert_handler_classb, // IDs [69 +: 1] + intr_alert_handler_classa, // IDs [68 +: 1] + intr_otp_ctrl_otp_error, // IDs [67 +: 1] + intr_otp_ctrl_otp_operation_done, // IDs [66 +: 1] + intr_rv_timer_timer_expired_hart0_timer0, // IDs [65 +: 1] + intr_i2c0_host_timeout, // IDs [64 +: 1] + intr_i2c0_unexp_stop, // IDs [63 +: 1] + intr_i2c0_acq_stretch, // IDs [62 +: 1] + intr_i2c0_tx_threshold, // IDs [61 +: 1] + intr_i2c0_tx_stretch, // IDs [60 +: 1] + intr_i2c0_cmd_complete, // IDs [59 +: 1] + intr_i2c0_sda_unstable, // IDs [58 +: 1] + intr_i2c0_stretch_timeout, // IDs [57 +: 1] + intr_i2c0_sda_interference, // IDs [56 +: 1] + intr_i2c0_scl_interference, // IDs [55 +: 1] + intr_i2c0_controller_halt, // IDs [54 +: 1] + intr_i2c0_rx_overflow, // IDs [53 +: 1] + intr_i2c0_acq_threshold, // IDs [52 +: 1] + intr_i2c0_rx_threshold, // IDs [51 +: 1] + intr_i2c0_fmt_threshold, // IDs [50 +: 1] + intr_spi_device_tpm_rdfifo_drop, // IDs [49 +: 1] + intr_spi_device_tpm_rdfifo_cmd_end, // IDs [48 +: 1] + intr_spi_device_tpm_header_not_empty, // IDs [47 +: 1] + intr_spi_device_readbuf_flip, // IDs [46 +: 1] + intr_spi_device_readbuf_watermark, // IDs [45 +: 1] + intr_spi_device_upload_payload_overflow, // IDs [44 +: 1] + intr_spi_device_upload_payload_not_empty, // IDs [43 +: 1] + intr_spi_device_upload_cmdfifo_not_empty, // IDs [42 +: 1] + intr_gpio_gpio, // IDs [10 +: 32] + intr_uart0_tx_empty, // IDs [9 +: 1] + intr_uart0_rx_parity_err, // IDs [8 +: 1] + intr_uart0_rx_timeout, // IDs [7 +: 1] + intr_uart0_rx_break_err, // IDs [6 +: 1] + intr_uart0_rx_frame_err, // IDs [5 +: 1] + intr_uart0_rx_overflow, // IDs [4 +: 1] + intr_uart0_tx_done, // IDs [3 +: 1] + intr_uart0_rx_watermark, // IDs [2 +: 1] + intr_uart0_tx_watermark, // IDs [1 +: 1] + 1'b 0 // ID [0 +: 1] is a special case and tied to zero. + }; + + // TL-UL Crossbar + xbar_main u_xbar_main ( + .clk_main_i (clkmgr_aon_clocks.clk_main_infra), + .clk_fixed_i (clkmgr_aon_clocks.clk_io_div4_infra), + .clk_usb_i (clkmgr_aon_clocks.clk_usb_infra), + .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_fixed_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_usb_ni (rstmgr_aon_resets.rst_lc_usb_n[rstmgr_pkg::Domain0Sel]), + + // port: tl_rv_core_ibex__corei + .tl_rv_core_ibex__corei_i(main_tl_rv_core_ibex__corei_req), + .tl_rv_core_ibex__corei_o(main_tl_rv_core_ibex__corei_rsp), + + // port: tl_rv_core_ibex__cored + .tl_rv_core_ibex__cored_i(main_tl_rv_core_ibex__cored_req), + .tl_rv_core_ibex__cored_o(main_tl_rv_core_ibex__cored_rsp), + + // port: tl_rv_dm__sba + .tl_rv_dm__sba_i(main_tl_rv_dm__sba_req), + .tl_rv_dm__sba_o(main_tl_rv_dm__sba_rsp), + + // port: tl_dma__host + .tl_dma__host_i(main_tl_dma__host_req), + .tl_dma__host_o(main_tl_dma__host_rsp), + + // port: tl_mbx0__sram + .tl_mbx0__sram_i(main_tl_mbx0__sram_req), + .tl_mbx0__sram_o(main_tl_mbx0__sram_rsp), + + // port: tl_mbx1__sram + .tl_mbx1__sram_i(main_tl_mbx1__sram_req), + .tl_mbx1__sram_o(main_tl_mbx1__sram_rsp), + + // port: tl_mbx2__sram + .tl_mbx2__sram_i(main_tl_mbx2__sram_req), + .tl_mbx2__sram_o(main_tl_mbx2__sram_rsp), + + // port: tl_mbx3__sram + .tl_mbx3__sram_i(main_tl_mbx3__sram_req), + .tl_mbx3__sram_o(main_tl_mbx3__sram_rsp), + + // port: tl_mbx4__sram + .tl_mbx4__sram_i(main_tl_mbx4__sram_req), + .tl_mbx4__sram_o(main_tl_mbx4__sram_rsp), + + // port: tl_mbx5__sram + .tl_mbx5__sram_i(main_tl_mbx5__sram_req), + .tl_mbx5__sram_o(main_tl_mbx5__sram_rsp), + + // port: tl_mbx6__sram + .tl_mbx6__sram_i(main_tl_mbx6__sram_req), + .tl_mbx6__sram_o(main_tl_mbx6__sram_rsp), + + // port: tl_mbx_jtag__sram + .tl_mbx_jtag__sram_i(main_tl_mbx_jtag__sram_req), + .tl_mbx_jtag__sram_o(main_tl_mbx_jtag__sram_rsp), + + // port: tl_mbx_pcie0__sram + .tl_mbx_pcie0__sram_i(main_tl_mbx_pcie0__sram_req), + .tl_mbx_pcie0__sram_o(main_tl_mbx_pcie0__sram_rsp), + + // port: tl_mbx_pcie1__sram + .tl_mbx_pcie1__sram_i(main_tl_mbx_pcie1__sram_req), + .tl_mbx_pcie1__sram_o(main_tl_mbx_pcie1__sram_rsp), + + // port: tl_rv_dm__regs + .tl_rv_dm__regs_o(rv_dm_regs_tl_d_req), + .tl_rv_dm__regs_i(rv_dm_regs_tl_d_rsp), + + // port: tl_rv_dm__mem + .tl_rv_dm__mem_o(rv_dm_mem_tl_d_req), + .tl_rv_dm__mem_i(rv_dm_mem_tl_d_rsp), + + // port: tl_rom_ctrl0__rom + .tl_rom_ctrl0__rom_o(rom_ctrl0_rom_tl_req), + .tl_rom_ctrl0__rom_i(rom_ctrl0_rom_tl_rsp), + + // port: tl_rom_ctrl0__regs + .tl_rom_ctrl0__regs_o(rom_ctrl0_regs_tl_req), + .tl_rom_ctrl0__regs_i(rom_ctrl0_regs_tl_rsp), + + // port: tl_rom_ctrl1__rom + .tl_rom_ctrl1__rom_o(rom_ctrl1_rom_tl_req), + .tl_rom_ctrl1__rom_i(rom_ctrl1_rom_tl_rsp), + + // port: tl_rom_ctrl1__regs + .tl_rom_ctrl1__regs_o(rom_ctrl1_regs_tl_req), + .tl_rom_ctrl1__regs_i(rom_ctrl1_regs_tl_rsp), + + // port: tl_peri + .tl_peri_o(main_tl_peri_req), + .tl_peri_i(main_tl_peri_rsp), + + // port: tl_soc_proxy__core + .tl_soc_proxy__core_o(soc_proxy_core_tl_req), + .tl_soc_proxy__core_i(soc_proxy_core_tl_rsp), + + // port: tl_soc_proxy__ctn + .tl_soc_proxy__ctn_o(soc_proxy_ctn_tl_req), + .tl_soc_proxy__ctn_i(soc_proxy_ctn_tl_rsp), + + // port: tl_hmac + .tl_hmac_o(hmac_tl_req), + .tl_hmac_i(hmac_tl_rsp), + + // port: tl_kmac + .tl_kmac_o(kmac_tl_req), + .tl_kmac_i(kmac_tl_rsp), + + // port: tl_aes + .tl_aes_o(aes_tl_req), + .tl_aes_i(aes_tl_rsp), + + // port: tl_csrng + .tl_csrng_o(csrng_tl_req), + .tl_csrng_i(csrng_tl_rsp), + + // port: tl_edn0 + .tl_edn0_o(edn0_tl_req), + .tl_edn0_i(edn0_tl_rsp), + + // port: tl_edn1 + .tl_edn1_o(edn1_tl_req), + .tl_edn1_i(edn1_tl_rsp), + + // port: tl_rv_plic + .tl_rv_plic_o(rv_plic_tl_req), + .tl_rv_plic_i(rv_plic_tl_rsp), + + // port: tl_otbn + .tl_otbn_o(otbn_tl_req), + .tl_otbn_i(otbn_tl_rsp), + + // port: tl_keymgr_dpe + .tl_keymgr_dpe_o(keymgr_dpe_tl_req), + .tl_keymgr_dpe_i(keymgr_dpe_tl_rsp), + + // port: tl_rv_core_ibex__cfg + .tl_rv_core_ibex__cfg_o(rv_core_ibex_cfg_tl_d_req), + .tl_rv_core_ibex__cfg_i(rv_core_ibex_cfg_tl_d_rsp), + + // port: tl_sram_ctrl_main__regs + .tl_sram_ctrl_main__regs_o(sram_ctrl_main_regs_tl_req), + .tl_sram_ctrl_main__regs_i(sram_ctrl_main_regs_tl_rsp), + + // port: tl_sram_ctrl_main__ram + .tl_sram_ctrl_main__ram_o(sram_ctrl_main_ram_tl_req), + .tl_sram_ctrl_main__ram_i(sram_ctrl_main_ram_tl_rsp), + + // port: tl_sram_ctrl_mbox__regs + .tl_sram_ctrl_mbox__regs_o(sram_ctrl_mbox_regs_tl_req), + .tl_sram_ctrl_mbox__regs_i(sram_ctrl_mbox_regs_tl_rsp), + + // port: tl_sram_ctrl_mbox__ram + .tl_sram_ctrl_mbox__ram_o(sram_ctrl_mbox_ram_tl_req), + .tl_sram_ctrl_mbox__ram_i(sram_ctrl_mbox_ram_tl_rsp), + + // port: tl_dma + .tl_dma_o(dma_tl_d_req), + .tl_dma_i(dma_tl_d_rsp), + + // port: tl_mbx0__core + .tl_mbx0__core_o(mbx0_core_tl_d_req), + .tl_mbx0__core_i(mbx0_core_tl_d_rsp), + + // port: tl_mbx1__core + .tl_mbx1__core_o(mbx1_core_tl_d_req), + .tl_mbx1__core_i(mbx1_core_tl_d_rsp), + + // port: tl_mbx2__core + .tl_mbx2__core_o(mbx2_core_tl_d_req), + .tl_mbx2__core_i(mbx2_core_tl_d_rsp), + + // port: tl_mbx3__core + .tl_mbx3__core_o(mbx3_core_tl_d_req), + .tl_mbx3__core_i(mbx3_core_tl_d_rsp), + + // port: tl_mbx4__core + .tl_mbx4__core_o(mbx4_core_tl_d_req), + .tl_mbx4__core_i(mbx4_core_tl_d_rsp), + + // port: tl_mbx5__core + .tl_mbx5__core_o(mbx5_core_tl_d_req), + .tl_mbx5__core_i(mbx5_core_tl_d_rsp), + + // port: tl_mbx6__core + .tl_mbx6__core_o(mbx6_core_tl_d_req), + .tl_mbx6__core_i(mbx6_core_tl_d_rsp), + + // port: tl_mbx_jtag__core + .tl_mbx_jtag__core_o(mbx_jtag_core_tl_d_req), + .tl_mbx_jtag__core_i(mbx_jtag_core_tl_d_rsp), + + // port: tl_mbx_pcie0__core + .tl_mbx_pcie0__core_o(mbx_pcie0_core_tl_d_req), + .tl_mbx_pcie0__core_i(mbx_pcie0_core_tl_d_rsp), + + // port: tl_mbx_pcie1__core + .tl_mbx_pcie1__core_o(mbx_pcie1_core_tl_d_req), + .tl_mbx_pcie1__core_i(mbx_pcie1_core_tl_d_rsp), + + + .scanmode_i + ); + xbar_peri u_xbar_peri ( + .clk_peri_i (clkmgr_aon_clocks.clk_io_div4_infra), + .rst_peri_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + + // port: tl_main + .tl_main_i(main_tl_peri_req), + .tl_main_o(main_tl_peri_rsp), + + // port: tl_uart0 + .tl_uart0_o(uart0_tl_req), + .tl_uart0_i(uart0_tl_rsp), + + // port: tl_i2c0 + .tl_i2c0_o(i2c0_tl_req), + .tl_i2c0_i(i2c0_tl_rsp), + + // port: tl_gpio + .tl_gpio_o(gpio_tl_req), + .tl_gpio_i(gpio_tl_rsp), + + // port: tl_spi_host0 + .tl_spi_host0_o(spi_host0_tl_req), + .tl_spi_host0_i(spi_host0_tl_rsp), + + // port: tl_spi_device + .tl_spi_device_o(spi_device_tl_req), + .tl_spi_device_i(spi_device_tl_rsp), + + // port: tl_rv_timer + .tl_rv_timer_o(rv_timer_tl_req), + .tl_rv_timer_i(rv_timer_tl_rsp), + + // port: tl_pwrmgr_aon + .tl_pwrmgr_aon_o(pwrmgr_aon_tl_req), + .tl_pwrmgr_aon_i(pwrmgr_aon_tl_rsp), + + // port: tl_rstmgr_aon + .tl_rstmgr_aon_o(rstmgr_aon_tl_req), + .tl_rstmgr_aon_i(rstmgr_aon_tl_rsp), + + // port: tl_clkmgr_aon + .tl_clkmgr_aon_o(clkmgr_aon_tl_req), + .tl_clkmgr_aon_i(clkmgr_aon_tl_rsp), + + // port: tl_pinmux_aon + .tl_pinmux_aon_o(pinmux_aon_tl_req), + .tl_pinmux_aon_i(pinmux_aon_tl_rsp), + + // port: tl_otp_ctrl__core + .tl_otp_ctrl__core_o(otp_ctrl_core_tl_req), + .tl_otp_ctrl__core_i(otp_ctrl_core_tl_rsp), + + // port: tl_otp_ctrl__prim + .tl_otp_ctrl__prim_o(otp_ctrl_prim_tl_req), + .tl_otp_ctrl__prim_i(otp_ctrl_prim_tl_rsp), + + // port: tl_lc_ctrl__regs + .tl_lc_ctrl__regs_o(lc_ctrl_regs_tl_req), + .tl_lc_ctrl__regs_i(lc_ctrl_regs_tl_rsp), + + // port: tl_sensor_ctrl + .tl_sensor_ctrl_o(sensor_ctrl_tl_req), + .tl_sensor_ctrl_i(sensor_ctrl_tl_rsp), + + // port: tl_alert_handler + .tl_alert_handler_o(alert_handler_tl_req), + .tl_alert_handler_i(alert_handler_tl_rsp), + + // port: tl_sram_ctrl_ret_aon__regs + .tl_sram_ctrl_ret_aon__regs_o(sram_ctrl_ret_aon_regs_tl_req), + .tl_sram_ctrl_ret_aon__regs_i(sram_ctrl_ret_aon_regs_tl_rsp), + + // port: tl_sram_ctrl_ret_aon__ram + .tl_sram_ctrl_ret_aon__ram_o(sram_ctrl_ret_aon_ram_tl_req), + .tl_sram_ctrl_ret_aon__ram_i(sram_ctrl_ret_aon_ram_tl_rsp), + + // port: tl_aon_timer_aon + .tl_aon_timer_aon_o(aon_timer_aon_tl_req), + .tl_aon_timer_aon_i(aon_timer_aon_tl_rsp), + + // port: tl_ast + .tl_ast_o(ast_tl_req_o), + .tl_ast_i(ast_tl_rsp_i), + + + .scanmode_i + ); + xbar_mbx u_xbar_mbx ( + .clk_mbx_i (clkmgr_aon_clocks.clk_main_infra), + .rst_mbx_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + + // port: tl_mbx + .tl_mbx_i(mbx_tl_req_i), + .tl_mbx_o(mbx_tl_rsp_o), + + // port: tl_mbx0__soc + .tl_mbx0__soc_o(mbx0_soc_tl_d_req), + .tl_mbx0__soc_i(mbx0_soc_tl_d_rsp), + + // port: tl_mbx1__soc + .tl_mbx1__soc_o(mbx1_soc_tl_d_req), + .tl_mbx1__soc_i(mbx1_soc_tl_d_rsp), + + // port: tl_mbx2__soc + .tl_mbx2__soc_o(mbx2_soc_tl_d_req), + .tl_mbx2__soc_i(mbx2_soc_tl_d_rsp), + + // port: tl_mbx3__soc + .tl_mbx3__soc_o(mbx3_soc_tl_d_req), + .tl_mbx3__soc_i(mbx3_soc_tl_d_rsp), + + // port: tl_mbx4__soc + .tl_mbx4__soc_o(mbx4_soc_tl_d_req), + .tl_mbx4__soc_i(mbx4_soc_tl_d_rsp), + + // port: tl_mbx5__soc + .tl_mbx5__soc_o(mbx5_soc_tl_d_req), + .tl_mbx5__soc_i(mbx5_soc_tl_d_rsp), + + // port: tl_mbx6__soc + .tl_mbx6__soc_o(mbx6_soc_tl_d_req), + .tl_mbx6__soc_i(mbx6_soc_tl_d_rsp), + + // port: tl_mbx_pcie0__soc + .tl_mbx_pcie0__soc_o(mbx_pcie0_soc_tl_d_req), + .tl_mbx_pcie0__soc_i(mbx_pcie0_soc_tl_d_rsp), + + // port: tl_mbx_pcie1__soc + .tl_mbx_pcie1__soc_o(mbx_pcie1_soc_tl_d_req), + .tl_mbx_pcie1__soc_i(mbx_pcie1_soc_tl_d_rsp), + + + .scanmode_i + ); + xbar_dbg u_xbar_dbg ( + .clk_dbg_i (clkmgr_aon_clocks.clk_main_infra), + .clk_peri_i (clkmgr_aon_clocks.clk_io_div4_infra), + .rst_dbg_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_peri_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + + // port: tl_dbg + .tl_dbg_i(dbg_tl_req_i), + .tl_dbg_o(dbg_tl_rsp_o), + + // port: tl_rv_dm__dbg + .tl_rv_dm__dbg_o(rv_dm_dbg_tl_d_req), + .tl_rv_dm__dbg_i(rv_dm_dbg_tl_d_rsp), + + // port: tl_mbx_jtag__soc + .tl_mbx_jtag__soc_o(mbx_jtag_soc_tl_d_req), + .tl_mbx_jtag__soc_i(mbx_jtag_soc_tl_d_rsp), + + // port: tl_lc_ctrl__dmi + .tl_lc_ctrl__dmi_o(lc_ctrl_dmi_tl_req), + .tl_lc_ctrl__dmi_i(lc_ctrl_dmi_tl_rsp), + + + .scanmode_i + ); + + // Pinmux connections + // All muxed inputs + assign cio_soc_proxy_soc_gpi_p2d[12] = mio_p2d[MioInSocProxySocGpi12]; + assign cio_soc_proxy_soc_gpi_p2d[13] = mio_p2d[MioInSocProxySocGpi13]; + assign cio_soc_proxy_soc_gpi_p2d[14] = mio_p2d[MioInSocProxySocGpi14]; + assign cio_soc_proxy_soc_gpi_p2d[15] = mio_p2d[MioInSocProxySocGpi15]; + + // All muxed outputs + assign mio_d2p[MioOutSocProxySocGpo12] = cio_soc_proxy_soc_gpo_d2p[12]; + assign mio_d2p[MioOutSocProxySocGpo13] = cio_soc_proxy_soc_gpo_d2p[13]; + assign mio_d2p[MioOutSocProxySocGpo14] = cio_soc_proxy_soc_gpo_d2p[14]; + assign mio_d2p[MioOutSocProxySocGpo15] = cio_soc_proxy_soc_gpo_d2p[15]; + assign mio_d2p[MioOutOtpCtrlTest0] = cio_otp_ctrl_test_d2p[0]; + + // All muxed output enables + assign mio_en_d2p[MioOutSocProxySocGpo12] = cio_soc_proxy_soc_gpo_en_d2p[12]; + assign mio_en_d2p[MioOutSocProxySocGpo13] = cio_soc_proxy_soc_gpo_en_d2p[13]; + assign mio_en_d2p[MioOutSocProxySocGpo14] = cio_soc_proxy_soc_gpo_en_d2p[14]; + assign mio_en_d2p[MioOutSocProxySocGpo15] = cio_soc_proxy_soc_gpo_en_d2p[15]; + assign mio_en_d2p[MioOutOtpCtrlTest0] = cio_otp_ctrl_test_en_d2p[0]; + + // All dedicated inputs + logic [72:0] unused_dio_p2d; + assign unused_dio_p2d = dio_p2d; + assign cio_spi_host0_sd_p2d[0] = dio_p2d[DioSpiHost0Sd0]; + assign cio_spi_host0_sd_p2d[1] = dio_p2d[DioSpiHost0Sd1]; + assign cio_spi_host0_sd_p2d[2] = dio_p2d[DioSpiHost0Sd2]; + assign cio_spi_host0_sd_p2d[3] = dio_p2d[DioSpiHost0Sd3]; + assign cio_spi_device_sd_p2d[0] = dio_p2d[DioSpiDeviceSd0]; + assign cio_spi_device_sd_p2d[1] = dio_p2d[DioSpiDeviceSd1]; + assign cio_spi_device_sd_p2d[2] = dio_p2d[DioSpiDeviceSd2]; + assign cio_spi_device_sd_p2d[3] = dio_p2d[DioSpiDeviceSd3]; + assign cio_i2c0_scl_p2d = dio_p2d[DioI2c0Scl]; + assign cio_i2c0_sda_p2d = dio_p2d[DioI2c0Sda]; + assign cio_gpio_gpio_p2d[0] = dio_p2d[DioGpioGpio0]; + assign cio_gpio_gpio_p2d[1] = dio_p2d[DioGpioGpio1]; + assign cio_gpio_gpio_p2d[2] = dio_p2d[DioGpioGpio2]; + assign cio_gpio_gpio_p2d[3] = dio_p2d[DioGpioGpio3]; + assign cio_gpio_gpio_p2d[4] = dio_p2d[DioGpioGpio4]; + assign cio_gpio_gpio_p2d[5] = dio_p2d[DioGpioGpio5]; + assign cio_gpio_gpio_p2d[6] = dio_p2d[DioGpioGpio6]; + assign cio_gpio_gpio_p2d[7] = dio_p2d[DioGpioGpio7]; + assign cio_gpio_gpio_p2d[8] = dio_p2d[DioGpioGpio8]; + assign cio_gpio_gpio_p2d[9] = dio_p2d[DioGpioGpio9]; + assign cio_gpio_gpio_p2d[10] = dio_p2d[DioGpioGpio10]; + assign cio_gpio_gpio_p2d[11] = dio_p2d[DioGpioGpio11]; + assign cio_gpio_gpio_p2d[12] = dio_p2d[DioGpioGpio12]; + assign cio_gpio_gpio_p2d[13] = dio_p2d[DioGpioGpio13]; + assign cio_gpio_gpio_p2d[14] = dio_p2d[DioGpioGpio14]; + assign cio_gpio_gpio_p2d[15] = dio_p2d[DioGpioGpio15]; + assign cio_gpio_gpio_p2d[16] = dio_p2d[DioGpioGpio16]; + assign cio_gpio_gpio_p2d[17] = dio_p2d[DioGpioGpio17]; + assign cio_gpio_gpio_p2d[18] = dio_p2d[DioGpioGpio18]; + assign cio_gpio_gpio_p2d[19] = dio_p2d[DioGpioGpio19]; + assign cio_gpio_gpio_p2d[20] = dio_p2d[DioGpioGpio20]; + assign cio_gpio_gpio_p2d[21] = dio_p2d[DioGpioGpio21]; + assign cio_gpio_gpio_p2d[22] = dio_p2d[DioGpioGpio22]; + assign cio_gpio_gpio_p2d[23] = dio_p2d[DioGpioGpio23]; + assign cio_gpio_gpio_p2d[24] = dio_p2d[DioGpioGpio24]; + assign cio_gpio_gpio_p2d[25] = dio_p2d[DioGpioGpio25]; + assign cio_gpio_gpio_p2d[26] = dio_p2d[DioGpioGpio26]; + assign cio_gpio_gpio_p2d[27] = dio_p2d[DioGpioGpio27]; + assign cio_gpio_gpio_p2d[28] = dio_p2d[DioGpioGpio28]; + assign cio_gpio_gpio_p2d[29] = dio_p2d[DioGpioGpio29]; + assign cio_gpio_gpio_p2d[30] = dio_p2d[DioGpioGpio30]; + assign cio_gpio_gpio_p2d[31] = dio_p2d[DioGpioGpio31]; + assign cio_spi_device_sck_p2d = dio_p2d[DioSpiDeviceSck]; + assign cio_spi_device_csb_p2d = dio_p2d[DioSpiDeviceCsb]; + assign cio_spi_device_tpm_csb_p2d = dio_p2d[DioSpiDeviceTpmCsb]; + assign cio_uart0_rx_p2d = dio_p2d[DioUart0Rx]; + assign cio_soc_proxy_soc_gpi_p2d[0] = dio_p2d[DioSocProxySocGpi0]; + assign cio_soc_proxy_soc_gpi_p2d[1] = dio_p2d[DioSocProxySocGpi1]; + assign cio_soc_proxy_soc_gpi_p2d[2] = dio_p2d[DioSocProxySocGpi2]; + assign cio_soc_proxy_soc_gpi_p2d[3] = dio_p2d[DioSocProxySocGpi3]; + assign cio_soc_proxy_soc_gpi_p2d[4] = dio_p2d[DioSocProxySocGpi4]; + assign cio_soc_proxy_soc_gpi_p2d[5] = dio_p2d[DioSocProxySocGpi5]; + assign cio_soc_proxy_soc_gpi_p2d[6] = dio_p2d[DioSocProxySocGpi6]; + assign cio_soc_proxy_soc_gpi_p2d[7] = dio_p2d[DioSocProxySocGpi7]; + assign cio_soc_proxy_soc_gpi_p2d[8] = dio_p2d[DioSocProxySocGpi8]; + assign cio_soc_proxy_soc_gpi_p2d[9] = dio_p2d[DioSocProxySocGpi9]; + assign cio_soc_proxy_soc_gpi_p2d[10] = dio_p2d[DioSocProxySocGpi10]; + assign cio_soc_proxy_soc_gpi_p2d[11] = dio_p2d[DioSocProxySocGpi11]; + + // All dedicated outputs + assign dio_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_d2p[0]; + assign dio_d2p[DioSpiHost0Sd1] = cio_spi_host0_sd_d2p[1]; + assign dio_d2p[DioSpiHost0Sd2] = cio_spi_host0_sd_d2p[2]; + assign dio_d2p[DioSpiHost0Sd3] = cio_spi_host0_sd_d2p[3]; + assign dio_d2p[DioSpiDeviceSd0] = cio_spi_device_sd_d2p[0]; + assign dio_d2p[DioSpiDeviceSd1] = cio_spi_device_sd_d2p[1]; + assign dio_d2p[DioSpiDeviceSd2] = cio_spi_device_sd_d2p[2]; + assign dio_d2p[DioSpiDeviceSd3] = cio_spi_device_sd_d2p[3]; + assign dio_d2p[DioI2c0Scl] = cio_i2c0_scl_d2p; + assign dio_d2p[DioI2c0Sda] = cio_i2c0_sda_d2p; + assign dio_d2p[DioGpioGpio0] = cio_gpio_gpio_d2p[0]; + assign dio_d2p[DioGpioGpio1] = cio_gpio_gpio_d2p[1]; + assign dio_d2p[DioGpioGpio2] = cio_gpio_gpio_d2p[2]; + assign dio_d2p[DioGpioGpio3] = cio_gpio_gpio_d2p[3]; + assign dio_d2p[DioGpioGpio4] = cio_gpio_gpio_d2p[4]; + assign dio_d2p[DioGpioGpio5] = cio_gpio_gpio_d2p[5]; + assign dio_d2p[DioGpioGpio6] = cio_gpio_gpio_d2p[6]; + assign dio_d2p[DioGpioGpio7] = cio_gpio_gpio_d2p[7]; + assign dio_d2p[DioGpioGpio8] = cio_gpio_gpio_d2p[8]; + assign dio_d2p[DioGpioGpio9] = cio_gpio_gpio_d2p[9]; + assign dio_d2p[DioGpioGpio10] = cio_gpio_gpio_d2p[10]; + assign dio_d2p[DioGpioGpio11] = cio_gpio_gpio_d2p[11]; + assign dio_d2p[DioGpioGpio12] = cio_gpio_gpio_d2p[12]; + assign dio_d2p[DioGpioGpio13] = cio_gpio_gpio_d2p[13]; + assign dio_d2p[DioGpioGpio14] = cio_gpio_gpio_d2p[14]; + assign dio_d2p[DioGpioGpio15] = cio_gpio_gpio_d2p[15]; + assign dio_d2p[DioGpioGpio16] = cio_gpio_gpio_d2p[16]; + assign dio_d2p[DioGpioGpio17] = cio_gpio_gpio_d2p[17]; + assign dio_d2p[DioGpioGpio18] = cio_gpio_gpio_d2p[18]; + assign dio_d2p[DioGpioGpio19] = cio_gpio_gpio_d2p[19]; + assign dio_d2p[DioGpioGpio20] = cio_gpio_gpio_d2p[20]; + assign dio_d2p[DioGpioGpio21] = cio_gpio_gpio_d2p[21]; + assign dio_d2p[DioGpioGpio22] = cio_gpio_gpio_d2p[22]; + assign dio_d2p[DioGpioGpio23] = cio_gpio_gpio_d2p[23]; + assign dio_d2p[DioGpioGpio24] = cio_gpio_gpio_d2p[24]; + assign dio_d2p[DioGpioGpio25] = cio_gpio_gpio_d2p[25]; + assign dio_d2p[DioGpioGpio26] = cio_gpio_gpio_d2p[26]; + assign dio_d2p[DioGpioGpio27] = cio_gpio_gpio_d2p[27]; + assign dio_d2p[DioGpioGpio28] = cio_gpio_gpio_d2p[28]; + assign dio_d2p[DioGpioGpio29] = cio_gpio_gpio_d2p[29]; + assign dio_d2p[DioGpioGpio30] = cio_gpio_gpio_d2p[30]; + assign dio_d2p[DioGpioGpio31] = cio_gpio_gpio_d2p[31]; + assign dio_d2p[DioSpiDeviceSck] = 1'b0; + assign dio_d2p[DioSpiDeviceCsb] = 1'b0; + assign dio_d2p[DioSpiDeviceTpmCsb] = 1'b0; + assign dio_d2p[DioUart0Rx] = 1'b0; + assign dio_d2p[DioSocProxySocGpi0] = 1'b0; + assign dio_d2p[DioSocProxySocGpi1] = 1'b0; + assign dio_d2p[DioSocProxySocGpi2] = 1'b0; + assign dio_d2p[DioSocProxySocGpi3] = 1'b0; + assign dio_d2p[DioSocProxySocGpi4] = 1'b0; + assign dio_d2p[DioSocProxySocGpi5] = 1'b0; + assign dio_d2p[DioSocProxySocGpi6] = 1'b0; + assign dio_d2p[DioSocProxySocGpi7] = 1'b0; + assign dio_d2p[DioSocProxySocGpi8] = 1'b0; + assign dio_d2p[DioSocProxySocGpi9] = 1'b0; + assign dio_d2p[DioSocProxySocGpi10] = 1'b0; + assign dio_d2p[DioSocProxySocGpi11] = 1'b0; + assign dio_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_d2p; + assign dio_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_d2p; + assign dio_d2p[DioUart0Tx] = cio_uart0_tx_d2p; + assign dio_d2p[DioSocProxySocGpo0] = cio_soc_proxy_soc_gpo_d2p[0]; + assign dio_d2p[DioSocProxySocGpo1] = cio_soc_proxy_soc_gpo_d2p[1]; + assign dio_d2p[DioSocProxySocGpo2] = cio_soc_proxy_soc_gpo_d2p[2]; + assign dio_d2p[DioSocProxySocGpo3] = cio_soc_proxy_soc_gpo_d2p[3]; + assign dio_d2p[DioSocProxySocGpo4] = cio_soc_proxy_soc_gpo_d2p[4]; + assign dio_d2p[DioSocProxySocGpo5] = cio_soc_proxy_soc_gpo_d2p[5]; + assign dio_d2p[DioSocProxySocGpo6] = cio_soc_proxy_soc_gpo_d2p[6]; + assign dio_d2p[DioSocProxySocGpo7] = cio_soc_proxy_soc_gpo_d2p[7]; + assign dio_d2p[DioSocProxySocGpo8] = cio_soc_proxy_soc_gpo_d2p[8]; + assign dio_d2p[DioSocProxySocGpo9] = cio_soc_proxy_soc_gpo_d2p[9]; + assign dio_d2p[DioSocProxySocGpo10] = cio_soc_proxy_soc_gpo_d2p[10]; + assign dio_d2p[DioSocProxySocGpo11] = cio_soc_proxy_soc_gpo_d2p[11]; + + // All dedicated output enables + assign dio_en_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_en_d2p[0]; + assign dio_en_d2p[DioSpiHost0Sd1] = cio_spi_host0_sd_en_d2p[1]; + assign dio_en_d2p[DioSpiHost0Sd2] = cio_spi_host0_sd_en_d2p[2]; + assign dio_en_d2p[DioSpiHost0Sd3] = cio_spi_host0_sd_en_d2p[3]; + assign dio_en_d2p[DioSpiDeviceSd0] = cio_spi_device_sd_en_d2p[0]; + assign dio_en_d2p[DioSpiDeviceSd1] = cio_spi_device_sd_en_d2p[1]; + assign dio_en_d2p[DioSpiDeviceSd2] = cio_spi_device_sd_en_d2p[2]; + assign dio_en_d2p[DioSpiDeviceSd3] = cio_spi_device_sd_en_d2p[3]; + assign dio_en_d2p[DioI2c0Scl] = cio_i2c0_scl_en_d2p; + assign dio_en_d2p[DioI2c0Sda] = cio_i2c0_sda_en_d2p; + assign dio_en_d2p[DioGpioGpio0] = cio_gpio_gpio_en_d2p[0]; + assign dio_en_d2p[DioGpioGpio1] = cio_gpio_gpio_en_d2p[1]; + assign dio_en_d2p[DioGpioGpio2] = cio_gpio_gpio_en_d2p[2]; + assign dio_en_d2p[DioGpioGpio3] = cio_gpio_gpio_en_d2p[3]; + assign dio_en_d2p[DioGpioGpio4] = cio_gpio_gpio_en_d2p[4]; + assign dio_en_d2p[DioGpioGpio5] = cio_gpio_gpio_en_d2p[5]; + assign dio_en_d2p[DioGpioGpio6] = cio_gpio_gpio_en_d2p[6]; + assign dio_en_d2p[DioGpioGpio7] = cio_gpio_gpio_en_d2p[7]; + assign dio_en_d2p[DioGpioGpio8] = cio_gpio_gpio_en_d2p[8]; + assign dio_en_d2p[DioGpioGpio9] = cio_gpio_gpio_en_d2p[9]; + assign dio_en_d2p[DioGpioGpio10] = cio_gpio_gpio_en_d2p[10]; + assign dio_en_d2p[DioGpioGpio11] = cio_gpio_gpio_en_d2p[11]; + assign dio_en_d2p[DioGpioGpio12] = cio_gpio_gpio_en_d2p[12]; + assign dio_en_d2p[DioGpioGpio13] = cio_gpio_gpio_en_d2p[13]; + assign dio_en_d2p[DioGpioGpio14] = cio_gpio_gpio_en_d2p[14]; + assign dio_en_d2p[DioGpioGpio15] = cio_gpio_gpio_en_d2p[15]; + assign dio_en_d2p[DioGpioGpio16] = cio_gpio_gpio_en_d2p[16]; + assign dio_en_d2p[DioGpioGpio17] = cio_gpio_gpio_en_d2p[17]; + assign dio_en_d2p[DioGpioGpio18] = cio_gpio_gpio_en_d2p[18]; + assign dio_en_d2p[DioGpioGpio19] = cio_gpio_gpio_en_d2p[19]; + assign dio_en_d2p[DioGpioGpio20] = cio_gpio_gpio_en_d2p[20]; + assign dio_en_d2p[DioGpioGpio21] = cio_gpio_gpio_en_d2p[21]; + assign dio_en_d2p[DioGpioGpio22] = cio_gpio_gpio_en_d2p[22]; + assign dio_en_d2p[DioGpioGpio23] = cio_gpio_gpio_en_d2p[23]; + assign dio_en_d2p[DioGpioGpio24] = cio_gpio_gpio_en_d2p[24]; + assign dio_en_d2p[DioGpioGpio25] = cio_gpio_gpio_en_d2p[25]; + assign dio_en_d2p[DioGpioGpio26] = cio_gpio_gpio_en_d2p[26]; + assign dio_en_d2p[DioGpioGpio27] = cio_gpio_gpio_en_d2p[27]; + assign dio_en_d2p[DioGpioGpio28] = cio_gpio_gpio_en_d2p[28]; + assign dio_en_d2p[DioGpioGpio29] = cio_gpio_gpio_en_d2p[29]; + assign dio_en_d2p[DioGpioGpio30] = cio_gpio_gpio_en_d2p[30]; + assign dio_en_d2p[DioGpioGpio31] = cio_gpio_gpio_en_d2p[31]; + assign dio_en_d2p[DioSpiDeviceSck] = 1'b0; + assign dio_en_d2p[DioSpiDeviceCsb] = 1'b0; + assign dio_en_d2p[DioSpiDeviceTpmCsb] = 1'b0; + assign dio_en_d2p[DioUart0Rx] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi0] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi1] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi2] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi3] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi4] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi5] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi6] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi7] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi8] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi9] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi10] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi11] = 1'b0; + assign dio_en_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_en_d2p; + assign dio_en_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_en_d2p; + assign dio_en_d2p[DioUart0Tx] = cio_uart0_tx_en_d2p; + assign dio_en_d2p[DioSocProxySocGpo0] = cio_soc_proxy_soc_gpo_en_d2p[0]; + assign dio_en_d2p[DioSocProxySocGpo1] = cio_soc_proxy_soc_gpo_en_d2p[1]; + assign dio_en_d2p[DioSocProxySocGpo2] = cio_soc_proxy_soc_gpo_en_d2p[2]; + assign dio_en_d2p[DioSocProxySocGpo3] = cio_soc_proxy_soc_gpo_en_d2p[3]; + assign dio_en_d2p[DioSocProxySocGpo4] = cio_soc_proxy_soc_gpo_en_d2p[4]; + assign dio_en_d2p[DioSocProxySocGpo5] = cio_soc_proxy_soc_gpo_en_d2p[5]; + assign dio_en_d2p[DioSocProxySocGpo6] = cio_soc_proxy_soc_gpo_en_d2p[6]; + assign dio_en_d2p[DioSocProxySocGpo7] = cio_soc_proxy_soc_gpo_en_d2p[7]; + assign dio_en_d2p[DioSocProxySocGpo8] = cio_soc_proxy_soc_gpo_en_d2p[8]; + assign dio_en_d2p[DioSocProxySocGpo9] = cio_soc_proxy_soc_gpo_en_d2p[9]; + assign dio_en_d2p[DioSocProxySocGpo10] = cio_soc_proxy_soc_gpo_en_d2p[10]; + assign dio_en_d2p[DioSocProxySocGpo11] = cio_soc_proxy_soc_gpo_en_d2p[11]; + + + // make sure scanmode_i is never X (including during reset) + `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_main_i, 0) + +endmodule diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv new file mode 100644 index 0000000000000..9a889180a9ba7 --- /dev/null +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv @@ -0,0 +1,1019 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \ +// -o hw/top_darjeeling/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + +package top_darjeeling_pkg; + /** + * Peripheral base address for uart0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_UART0_BASE_ADDR = 32'h30010000; + + /** + * Peripheral size in bytes for uart0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_UART0_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for gpio in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_GPIO_BASE_ADDR = 32'h30000000; + + /** + * Peripheral size in bytes for gpio in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_GPIO_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for spi_device in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SPI_DEVICE_BASE_ADDR = 32'h30310000; + + /** + * Peripheral size in bytes for spi_device in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SPI_DEVICE_SIZE_BYTES = 32'h2000; + + /** + * Peripheral base address for i2c0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_I2C0_BASE_ADDR = 32'h30080000; + + /** + * Peripheral size in bytes for i2c0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_I2C0_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for rv_timer in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RV_TIMER_BASE_ADDR = 32'h30100000; + + /** + * Peripheral size in bytes for rv_timer in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RV_TIMER_SIZE_BYTES = 32'h200; + + /** + * Peripheral base address for core device on otp_ctrl in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR = 32'h30130000; + + /** + * Peripheral size in bytes for core device on otp_ctrl in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_OTP_CTRL_CORE_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for prim device on otp_ctrl in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_OTP_CTRL_PRIM_BASE_ADDR = 32'h30138000; + + /** + * Peripheral size in bytes for prim device on otp_ctrl in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_OTP_CTRL_PRIM_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for regs device on lc_ctrl in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR = 32'h30140000; + + /** + * Peripheral size in bytes for regs device on lc_ctrl in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES = 32'h100; + + /** + * Peripheral base address for alert_handler in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR = 32'h30150000; + + /** + * Peripheral size in bytes for alert_handler in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ALERT_HANDLER_SIZE_BYTES = 32'h800; + + /** + * Peripheral base address for spi_host0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SPI_HOST0_BASE_ADDR = 32'h30300000; + + /** + * Peripheral size in bytes for spi_host0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SPI_HOST0_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for pwrmgr_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_PWRMGR_AON_BASE_ADDR = 32'h30400000; + + /** + * Peripheral size in bytes for pwrmgr_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_PWRMGR_AON_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for rstmgr_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RSTMGR_AON_BASE_ADDR = 32'h30410000; + + /** + * Peripheral size in bytes for rstmgr_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RSTMGR_AON_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for clkmgr_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_CLKMGR_AON_BASE_ADDR = 32'h30420000; + + /** + * Peripheral size in bytes for clkmgr_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_CLKMGR_AON_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for pinmux_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_PINMUX_AON_BASE_ADDR = 32'h30460000; + + /** + * Peripheral size in bytes for pinmux_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_PINMUX_AON_SIZE_BYTES = 32'h800; + + /** + * Peripheral base address for aon_timer_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR = 32'h30470000; + + /** + * Peripheral size in bytes for aon_timer_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_AON_TIMER_AON_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for ast in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_AST_BASE_ADDR = 32'h30480000; + + /** + * Peripheral size in bytes for ast in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_AST_SIZE_BYTES = 32'h400; + + /** + * Peripheral base address for sensor_ctrl in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SENSOR_CTRL_BASE_ADDR = 32'h30020000; + + /** + * Peripheral size in bytes for sensor_ctrl in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SENSOR_CTRL_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for core device on soc_proxy in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR = 32'h22030000; + + /** + * Peripheral size in bytes for core device on soc_proxy in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SOC_PROXY_CORE_SIZE_BYTES = 32'h10; + + /** + * Peripheral base address for ctn device on soc_proxy in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR = 32'h40000000; + + /** + * Peripheral size in bytes for ctn device on soc_proxy in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES = 32'h40000000; + + /** + * Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR = 32'h30500000; + + /** + * Peripheral size in bytes for regs device on sram_ctrl_ret_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for ram device on sram_ctrl_ret_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR = 32'h30600000; + + /** + * Peripheral size in bytes for ram device on sram_ctrl_ret_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for regs device on rv_dm in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RV_DM_REGS_BASE_ADDR = 32'h21200000; + + /** + * Peripheral size in bytes for regs device on rv_dm in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RV_DM_REGS_SIZE_BYTES = 32'h10; + + /** + * Peripheral base address for mem device on rv_dm in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RV_DM_MEM_BASE_ADDR = 32'h40000; + + /** + * Peripheral size in bytes for mem device on rv_dm in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for rv_plic in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RV_PLIC_BASE_ADDR = 32'h28000000; + + /** + * Peripheral size in bytes for rv_plic in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RV_PLIC_SIZE_BYTES = 32'h8000000; + + /** + * Peripheral base address for aes in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_AES_BASE_ADDR = 32'h21100000; + + /** + * Peripheral size in bytes for aes in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_AES_SIZE_BYTES = 32'h100; + + /** + * Peripheral base address for hmac in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_HMAC_BASE_ADDR = 32'h21110000; + + /** + * Peripheral size in bytes for hmac in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_HMAC_SIZE_BYTES = 32'h2000; + + /** + * Peripheral base address for kmac in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_KMAC_BASE_ADDR = 32'h21120000; + + /** + * Peripheral size in bytes for kmac in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_KMAC_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for otbn in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_OTBN_BASE_ADDR = 32'h21130000; + + /** + * Peripheral size in bytes for otbn in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_OTBN_SIZE_BYTES = 32'h10000; + + /** + * Peripheral base address for keymgr_dpe in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR = 32'h21140000; + + /** + * Peripheral size in bytes for keymgr_dpe in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES = 32'h100; + + /** + * Peripheral base address for csrng in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_CSRNG_BASE_ADDR = 32'h21150000; + + /** + * Peripheral size in bytes for csrng in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_CSRNG_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for edn0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_EDN0_BASE_ADDR = 32'h21170000; + + /** + * Peripheral size in bytes for edn0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_EDN0_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for edn1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_EDN1_BASE_ADDR = 32'h21180000; + + /** + * Peripheral size in bytes for edn1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_EDN1_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for regs device on sram_ctrl_main in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR = 32'h211C0000; + + /** + * Peripheral size in bytes for regs device on sram_ctrl_main in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for ram device on sram_ctrl_main in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR = 32'h10000000; + + /** + * Peripheral size in bytes for ram device on sram_ctrl_main in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES = 32'h10000; + + /** + * Peripheral base address for regs device on sram_ctrl_mbox in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR = 32'h211D0000; + + /** + * Peripheral size in bytes for regs device on sram_ctrl_mbox in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for ram device on sram_ctrl_mbox in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR = 32'h11000000; + + /** + * Peripheral size in bytes for ram device on sram_ctrl_mbox in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for regs device on rom_ctrl0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR = 32'h211E0000; + + /** + * Peripheral size in bytes for regs device on rom_ctrl0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ROM_CTRL0_REGS_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for rom device on rom_ctrl0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR = 32'h8000; + + /** + * Peripheral size in bytes for rom device on rom_ctrl0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES = 32'h8000; + + /** + * Peripheral base address for regs device on rom_ctrl1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR = 32'h211E1000; + + /** + * Peripheral size in bytes for regs device on rom_ctrl1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ROM_CTRL1_REGS_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for rom device on rom_ctrl1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR = 32'h20000; + + /** + * Peripheral size in bytes for rom device on rom_ctrl1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ROM_CTRL1_ROM_SIZE_BYTES = 32'h10000; + + /** + * Peripheral base address for dma in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_DMA_BASE_ADDR = 32'h22010000; + + /** + * Peripheral size in bytes for dma in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_DMA_SIZE_BYTES = 32'h200; + + /** + * Peripheral base address for core device on mbx0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX0_CORE_BASE_ADDR = 32'h22000000; + + /** + * Peripheral size in bytes for core device on mbx0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX0_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX1_CORE_BASE_ADDR = 32'h22000100; + + /** + * Peripheral size in bytes for core device on mbx1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX1_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx2 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX2_CORE_BASE_ADDR = 32'h22000200; + + /** + * Peripheral size in bytes for core device on mbx2 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX2_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx3 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX3_CORE_BASE_ADDR = 32'h22000300; + + /** + * Peripheral size in bytes for core device on mbx3 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX3_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx4 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX4_CORE_BASE_ADDR = 32'h22000400; + + /** + * Peripheral size in bytes for core device on mbx4 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX4_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx5 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX5_CORE_BASE_ADDR = 32'h22000500; + + /** + * Peripheral size in bytes for core device on mbx5 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX5_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx6 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX6_CORE_BASE_ADDR = 32'h22000600; + + /** + * Peripheral size in bytes for core device on mbx6 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX6_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx_jtag in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR = 32'h22000800; + + /** + * Peripheral size in bytes for core device on mbx_jtag in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx_pcie0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR = 32'h22040000; + + /** + * Peripheral size in bytes for core device on mbx_pcie0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx_pcie1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR = 32'h22040100; + + /** + * Peripheral size in bytes for core device on mbx_pcie1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for cfg device on rv_core_ibex in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR = 32'h211F0000; + + /** + * Peripheral size in bytes for cfg device on rv_core_ibex in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES = 32'h100; + + /** + * Memory base address for ctn in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_CTN_BASE_ADDR = 32'h40000000; + + /** + * Memory size for ctn in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_CTN_SIZE_BYTES = 32'h40000000; + + /** + * Memory base address for ram_ret_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RAM_RET_AON_BASE_ADDR = 32'h30600000; + + /** + * Memory size for ram_ret_aon in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RAM_RET_AON_SIZE_BYTES = 32'h1000; + + /** + * Memory base address for ram_main in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RAM_MAIN_BASE_ADDR = 32'h10000000; + + /** + * Memory size for ram_main in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RAM_MAIN_SIZE_BYTES = 32'h10000; + + /** + * Memory base address for ram_mbox in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RAM_MBOX_BASE_ADDR = 32'h11000000; + + /** + * Memory size for ram_mbox in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_RAM_MBOX_SIZE_BYTES = 32'h1000; + + /** + * Memory base address for rom0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ROM0_BASE_ADDR = 32'h8000; + + /** + * Memory size for rom0 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ROM0_SIZE_BYTES = 32'h8000; + + /** + * Memory base address for rom1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ROM1_BASE_ADDR = 32'h20000; + + /** + * Memory size for rom1 in top darjeeling. + */ + parameter int unsigned TOP_DARJEELING_ROM1_SIZE_BYTES = 32'h10000; + + + // Enumeration of alert modules + typedef enum int unsigned { + TopDarjeelingAlertPeripheralUart0 = 0, + TopDarjeelingAlertPeripheralGpio = 1, + TopDarjeelingAlertPeripheralSpiDevice = 2, + TopDarjeelingAlertPeripheralI2c0 = 3, + TopDarjeelingAlertPeripheralRvTimer = 4, + TopDarjeelingAlertPeripheralOtpCtrl = 5, + TopDarjeelingAlertPeripheralLcCtrl = 6, + TopDarjeelingAlertPeripheralSpiHost0 = 7, + TopDarjeelingAlertPeripheralPwrmgrAon = 8, + TopDarjeelingAlertPeripheralRstmgrAon = 9, + TopDarjeelingAlertPeripheralClkmgrAon = 10, + TopDarjeelingAlertPeripheralPinmuxAon = 11, + TopDarjeelingAlertPeripheralAonTimerAon = 12, + TopDarjeelingAlertPeripheralSensorCtrl = 13, + TopDarjeelingAlertPeripheralSocProxy = 14, + TopDarjeelingAlertPeripheralSramCtrlRetAon = 15, + TopDarjeelingAlertPeripheralRvDm = 16, + TopDarjeelingAlertPeripheralRvPlic = 17, + TopDarjeelingAlertPeripheralAes = 18, + TopDarjeelingAlertPeripheralHmac = 19, + TopDarjeelingAlertPeripheralKmac = 20, + TopDarjeelingAlertPeripheralOtbn = 21, + TopDarjeelingAlertPeripheralKeymgrDpe = 22, + TopDarjeelingAlertPeripheralCsrng = 23, + TopDarjeelingAlertPeripheralEdn0 = 24, + TopDarjeelingAlertPeripheralEdn1 = 25, + TopDarjeelingAlertPeripheralSramCtrlMain = 26, + TopDarjeelingAlertPeripheralSramCtrlMbox = 27, + TopDarjeelingAlertPeripheralRomCtrl0 = 28, + TopDarjeelingAlertPeripheralRomCtrl1 = 29, + TopDarjeelingAlertPeripheralDma = 30, + TopDarjeelingAlertPeripheralMbx0 = 31, + TopDarjeelingAlertPeripheralMbx1 = 32, + TopDarjeelingAlertPeripheralMbx2 = 33, + TopDarjeelingAlertPeripheralMbx3 = 34, + TopDarjeelingAlertPeripheralMbx4 = 35, + TopDarjeelingAlertPeripheralMbx5 = 36, + TopDarjeelingAlertPeripheralMbx6 = 37, + TopDarjeelingAlertPeripheralMbxJtag = 38, + TopDarjeelingAlertPeripheralMbxPcie0 = 39, + TopDarjeelingAlertPeripheralMbxPcie1 = 40, + TopDarjeelingAlertPeripheralRvCoreIbex = 41, + TopDarjeelingAlertPeripheralCount + } alert_peripheral_e; + + // Enumeration of alerts + typedef enum int unsigned { + TopDarjeelingAlertIdUart0FatalFault = 0, + TopDarjeelingAlertIdGpioFatalFault = 1, + TopDarjeelingAlertIdSpiDeviceFatalFault = 2, + TopDarjeelingAlertIdI2c0FatalFault = 3, + TopDarjeelingAlertIdRvTimerFatalFault = 4, + TopDarjeelingAlertIdOtpCtrlFatalMacroError = 5, + TopDarjeelingAlertIdOtpCtrlFatalCheckError = 6, + TopDarjeelingAlertIdOtpCtrlFatalBusIntegError = 7, + TopDarjeelingAlertIdOtpCtrlFatalPrimOtpAlert = 8, + TopDarjeelingAlertIdOtpCtrlRecovPrimOtpAlert = 9, + TopDarjeelingAlertIdLcCtrlFatalProgError = 10, + TopDarjeelingAlertIdLcCtrlFatalStateError = 11, + TopDarjeelingAlertIdLcCtrlFatalBusIntegError = 12, + TopDarjeelingAlertIdSpiHost0FatalFault = 13, + TopDarjeelingAlertIdPwrmgrAonFatalFault = 14, + TopDarjeelingAlertIdRstmgrAonFatalFault = 15, + TopDarjeelingAlertIdRstmgrAonFatalCnstyFault = 16, + TopDarjeelingAlertIdClkmgrAonRecovFault = 17, + TopDarjeelingAlertIdClkmgrAonFatalFault = 18, + TopDarjeelingAlertIdPinmuxAonFatalFault = 19, + TopDarjeelingAlertIdAonTimerAonFatalFault = 20, + TopDarjeelingAlertIdSensorCtrlRecovAlert = 21, + TopDarjeelingAlertIdSensorCtrlFatalAlert = 22, + TopDarjeelingAlertIdSocProxyFatalAlertIntg = 23, + TopDarjeelingAlertIdSocProxyFatalAlertExternal0 = 24, + TopDarjeelingAlertIdSocProxyFatalAlertExternal1 = 25, + TopDarjeelingAlertIdSocProxyFatalAlertExternal2 = 26, + TopDarjeelingAlertIdSocProxyFatalAlertExternal3 = 27, + TopDarjeelingAlertIdSocProxyFatalAlertExternal4 = 28, + TopDarjeelingAlertIdSocProxyFatalAlertExternal5 = 29, + TopDarjeelingAlertIdSocProxyFatalAlertExternal6 = 30, + TopDarjeelingAlertIdSocProxyFatalAlertExternal7 = 31, + TopDarjeelingAlertIdSocProxyFatalAlertExternal8 = 32, + TopDarjeelingAlertIdSocProxyFatalAlertExternal9 = 33, + TopDarjeelingAlertIdSocProxyFatalAlertExternal10 = 34, + TopDarjeelingAlertIdSocProxyFatalAlertExternal11 = 35, + TopDarjeelingAlertIdSocProxyFatalAlertExternal12 = 36, + TopDarjeelingAlertIdSocProxyFatalAlertExternal13 = 37, + TopDarjeelingAlertIdSocProxyFatalAlertExternal14 = 38, + TopDarjeelingAlertIdSocProxyFatalAlertExternal15 = 39, + TopDarjeelingAlertIdSocProxyFatalAlertExternal16 = 40, + TopDarjeelingAlertIdSocProxyFatalAlertExternal17 = 41, + TopDarjeelingAlertIdSocProxyFatalAlertExternal18 = 42, + TopDarjeelingAlertIdSocProxyFatalAlertExternal19 = 43, + TopDarjeelingAlertIdSocProxyFatalAlertExternal20 = 44, + TopDarjeelingAlertIdSocProxyFatalAlertExternal21 = 45, + TopDarjeelingAlertIdSocProxyFatalAlertExternal22 = 46, + TopDarjeelingAlertIdSocProxyFatalAlertExternal23 = 47, + TopDarjeelingAlertIdSocProxyRecovAlertExternal0 = 48, + TopDarjeelingAlertIdSocProxyRecovAlertExternal1 = 49, + TopDarjeelingAlertIdSocProxyRecovAlertExternal2 = 50, + TopDarjeelingAlertIdSocProxyRecovAlertExternal3 = 51, + TopDarjeelingAlertIdSramCtrlRetAonFatalError = 52, + TopDarjeelingAlertIdRvDmFatalFault = 53, + TopDarjeelingAlertIdRvPlicFatalFault = 54, + TopDarjeelingAlertIdAesRecovCtrlUpdateErr = 55, + TopDarjeelingAlertIdAesFatalFault = 56, + TopDarjeelingAlertIdHmacFatalFault = 57, + TopDarjeelingAlertIdKmacRecovOperationErr = 58, + TopDarjeelingAlertIdKmacFatalFaultErr = 59, + TopDarjeelingAlertIdOtbnFatal = 60, + TopDarjeelingAlertIdOtbnRecov = 61, + TopDarjeelingAlertIdKeymgrDpeRecovOperationErr = 62, + TopDarjeelingAlertIdKeymgrDpeFatalFaultErr = 63, + TopDarjeelingAlertIdCsrngRecovAlert = 64, + TopDarjeelingAlertIdCsrngFatalAlert = 65, + TopDarjeelingAlertIdEdn0RecovAlert = 66, + TopDarjeelingAlertIdEdn0FatalAlert = 67, + TopDarjeelingAlertIdEdn1RecovAlert = 68, + TopDarjeelingAlertIdEdn1FatalAlert = 69, + TopDarjeelingAlertIdSramCtrlMainFatalError = 70, + TopDarjeelingAlertIdSramCtrlMboxFatalError = 71, + TopDarjeelingAlertIdRomCtrl0Fatal = 72, + TopDarjeelingAlertIdRomCtrl1Fatal = 73, + TopDarjeelingAlertIdDmaFatalFault = 74, + TopDarjeelingAlertIdMbx0FatalFault = 75, + TopDarjeelingAlertIdMbx0RecovFault = 76, + TopDarjeelingAlertIdMbx1FatalFault = 77, + TopDarjeelingAlertIdMbx1RecovFault = 78, + TopDarjeelingAlertIdMbx2FatalFault = 79, + TopDarjeelingAlertIdMbx2RecovFault = 80, + TopDarjeelingAlertIdMbx3FatalFault = 81, + TopDarjeelingAlertIdMbx3RecovFault = 82, + TopDarjeelingAlertIdMbx4FatalFault = 83, + TopDarjeelingAlertIdMbx4RecovFault = 84, + TopDarjeelingAlertIdMbx5FatalFault = 85, + TopDarjeelingAlertIdMbx5RecovFault = 86, + TopDarjeelingAlertIdMbx6FatalFault = 87, + TopDarjeelingAlertIdMbx6RecovFault = 88, + TopDarjeelingAlertIdMbxJtagFatalFault = 89, + TopDarjeelingAlertIdMbxJtagRecovFault = 90, + TopDarjeelingAlertIdMbxPcie0FatalFault = 91, + TopDarjeelingAlertIdMbxPcie0RecovFault = 92, + TopDarjeelingAlertIdMbxPcie1FatalFault = 93, + TopDarjeelingAlertIdMbxPcie1RecovFault = 94, + TopDarjeelingAlertIdRvCoreIbexFatalSwErr = 95, + TopDarjeelingAlertIdRvCoreIbexRecovSwErr = 96, + TopDarjeelingAlertIdRvCoreIbexFatalHwErr = 97, + TopDarjeelingAlertIdRvCoreIbexRecovHwErr = 98, + TopDarjeelingAlertIdCount + } alert_id_e; + + // Enumeration of IO power domains. + // Only used in ASIC target. + typedef enum logic [0:0] { + IoBankVio = 0, + IoBankCount = 1 + } pwr_dom_e; + + // Enumeration for MIO signals on the top-level. + typedef enum int unsigned { + MioInSocProxySocGpi12 = 0, + MioInSocProxySocGpi13 = 1, + MioInSocProxySocGpi14 = 2, + MioInSocProxySocGpi15 = 3, + MioInCount = 4 + } mio_in_e; + + typedef enum { + MioOutSocProxySocGpo12 = 0, + MioOutSocProxySocGpo13 = 1, + MioOutSocProxySocGpo14 = 2, + MioOutSocProxySocGpo15 = 3, + MioOutOtpCtrlTest0 = 4, + MioOutCount = 5 + } mio_out_e; + + // Enumeration for DIO signals, used on both the top and chip-levels. + typedef enum int unsigned { + DioSpiHost0Sd0 = 0, + DioSpiHost0Sd1 = 1, + DioSpiHost0Sd2 = 2, + DioSpiHost0Sd3 = 3, + DioSpiDeviceSd0 = 4, + DioSpiDeviceSd1 = 5, + DioSpiDeviceSd2 = 6, + DioSpiDeviceSd3 = 7, + DioI2c0Scl = 8, + DioI2c0Sda = 9, + DioGpioGpio0 = 10, + DioGpioGpio1 = 11, + DioGpioGpio2 = 12, + DioGpioGpio3 = 13, + DioGpioGpio4 = 14, + DioGpioGpio5 = 15, + DioGpioGpio6 = 16, + DioGpioGpio7 = 17, + DioGpioGpio8 = 18, + DioGpioGpio9 = 19, + DioGpioGpio10 = 20, + DioGpioGpio11 = 21, + DioGpioGpio12 = 22, + DioGpioGpio13 = 23, + DioGpioGpio14 = 24, + DioGpioGpio15 = 25, + DioGpioGpio16 = 26, + DioGpioGpio17 = 27, + DioGpioGpio18 = 28, + DioGpioGpio19 = 29, + DioGpioGpio20 = 30, + DioGpioGpio21 = 31, + DioGpioGpio22 = 32, + DioGpioGpio23 = 33, + DioGpioGpio24 = 34, + DioGpioGpio25 = 35, + DioGpioGpio26 = 36, + DioGpioGpio27 = 37, + DioGpioGpio28 = 38, + DioGpioGpio29 = 39, + DioGpioGpio30 = 40, + DioGpioGpio31 = 41, + DioSpiDeviceSck = 42, + DioSpiDeviceCsb = 43, + DioSpiDeviceTpmCsb = 44, + DioUart0Rx = 45, + DioSocProxySocGpi0 = 46, + DioSocProxySocGpi1 = 47, + DioSocProxySocGpi2 = 48, + DioSocProxySocGpi3 = 49, + DioSocProxySocGpi4 = 50, + DioSocProxySocGpi5 = 51, + DioSocProxySocGpi6 = 52, + DioSocProxySocGpi7 = 53, + DioSocProxySocGpi8 = 54, + DioSocProxySocGpi9 = 55, + DioSocProxySocGpi10 = 56, + DioSocProxySocGpi11 = 57, + DioSpiHost0Sck = 58, + DioSpiHost0Csb = 59, + DioUart0Tx = 60, + DioSocProxySocGpo0 = 61, + DioSocProxySocGpo1 = 62, + DioSocProxySocGpo2 = 63, + DioSocProxySocGpo3 = 64, + DioSocProxySocGpo4 = 65, + DioSocProxySocGpo5 = 66, + DioSocProxySocGpo6 = 67, + DioSocProxySocGpo7 = 68, + DioSocProxySocGpo8 = 69, + DioSocProxySocGpo9 = 70, + DioSocProxySocGpo10 = 71, + DioSocProxySocGpo11 = 72, + DioCount = 73 + } dio_e; + + // Enumeration for the types of pads. + typedef enum { + MioPad, + DioPad + } pad_type_e; + + // Raw MIO/DIO input array indices on chip-level. + // TODO: Does not account for target specific stubbed/added pads. + // Need to make a target-specific package for those. + typedef enum int unsigned { + MioPadMio0 = 0, + MioPadMio1 = 1, + MioPadMio2 = 2, + MioPadMio3 = 3, + MioPadMio4 = 4, + MioPadMio5 = 5, + MioPadMio6 = 6, + MioPadMio7 = 7, + MioPadMio8 = 8, + MioPadMio9 = 9, + MioPadMio10 = 10, + MioPadMio11 = 11, + MioPadCount + } mio_pad_e; + + typedef enum int unsigned { + DioPadPorN = 0, + DioPadJtagTck = 1, + DioPadJtagTms = 2, + DioPadJtagTdi = 3, + DioPadJtagTdo = 4, + DioPadJtagTrstN = 5, + DioPadOtpExtVolt = 6, + DioPadSpiHostD0 = 7, + DioPadSpiHostD1 = 8, + DioPadSpiHostD2 = 9, + DioPadSpiHostD3 = 10, + DioPadSpiHostClk = 11, + DioPadSpiHostCsL = 12, + DioPadSpiDevD0 = 13, + DioPadSpiDevD1 = 14, + DioPadSpiDevD2 = 15, + DioPadSpiDevD3 = 16, + DioPadSpiDevClk = 17, + DioPadSpiDevCsL = 18, + DioPadSpiDevTpmCsL = 19, + DioPadUartRx = 20, + DioPadUartTx = 21, + DioPadI2cScl = 22, + DioPadI2cSda = 23, + DioPadGpio0 = 24, + DioPadGpio1 = 25, + DioPadGpio2 = 26, + DioPadGpio3 = 27, + DioPadGpio4 = 28, + DioPadGpio5 = 29, + DioPadGpio6 = 30, + DioPadGpio7 = 31, + DioPadGpio8 = 32, + DioPadGpio9 = 33, + DioPadGpio10 = 34, + DioPadGpio11 = 35, + DioPadGpio12 = 36, + DioPadGpio13 = 37, + DioPadGpio14 = 38, + DioPadGpio15 = 39, + DioPadGpio16 = 40, + DioPadGpio17 = 41, + DioPadGpio18 = 42, + DioPadGpio19 = 43, + DioPadGpio20 = 44, + DioPadGpio21 = 45, + DioPadGpio22 = 46, + DioPadGpio23 = 47, + DioPadGpio24 = 48, + DioPadGpio25 = 49, + DioPadGpio26 = 50, + DioPadGpio27 = 51, + DioPadGpio28 = 52, + DioPadGpio29 = 53, + DioPadGpio30 = 54, + DioPadGpio31 = 55, + DioPadSocGpi0 = 56, + DioPadSocGpi1 = 57, + DioPadSocGpi2 = 58, + DioPadSocGpi3 = 59, + DioPadSocGpi4 = 60, + DioPadSocGpi5 = 61, + DioPadSocGpi6 = 62, + DioPadSocGpi7 = 63, + DioPadSocGpi8 = 64, + DioPadSocGpi9 = 65, + DioPadSocGpi10 = 66, + DioPadSocGpi11 = 67, + DioPadSocGpo0 = 68, + DioPadSocGpo1 = 69, + DioPadSocGpo2 = 70, + DioPadSocGpo3 = 71, + DioPadSocGpo4 = 72, + DioPadSocGpo5 = 73, + DioPadSocGpo6 = 74, + DioPadSocGpo7 = 75, + DioPadSocGpo8 = 76, + DioPadSocGpo9 = 77, + DioPadSocGpo10 = 78, + DioPadSocGpo11 = 79, + DioPadCount + } dio_pad_e; + + // List of peripheral instantiated in this chip. + typedef enum { + PeripheralAes, + PeripheralAlertHandler, + PeripheralAonTimerAon, + PeripheralAst, + PeripheralClkmgrAon, + PeripheralCsrng, + PeripheralDma, + PeripheralEdn0, + PeripheralEdn1, + PeripheralGpio, + PeripheralHmac, + PeripheralI2c0, + PeripheralKeymgrDpe, + PeripheralKmac, + PeripheralLcCtrl, + PeripheralMbx0, + PeripheralMbx1, + PeripheralMbx2, + PeripheralMbx3, + PeripheralMbx4, + PeripheralMbx5, + PeripheralMbx6, + PeripheralMbxJtag, + PeripheralMbxPcie0, + PeripheralMbxPcie1, + PeripheralOtbn, + PeripheralOtpCtrl, + PeripheralPinmuxAon, + PeripheralPwrmgrAon, + PeripheralRomCtrl0, + PeripheralRomCtrl1, + PeripheralRstmgrAon, + PeripheralRvCoreIbex, + PeripheralRvDm, + PeripheralRvPlic, + PeripheralRvTimer, + PeripheralSensorCtrl, + PeripheralSocProxy, + PeripheralSpiDevice, + PeripheralSpiHost0, + PeripheralSramCtrlMain, + PeripheralSramCtrlMbox, + PeripheralSramCtrlRetAon, + PeripheralUart0, + PeripheralCount + } peripheral_e; + + // TODO: Enumeration for PLIC Interrupt source peripheral. + // TODO: Enumeration for PLIC Interrupt Ids. + +// MACROs for AST analog simulation support +`ifdef ANALOGSIM + `define INOUT_AI input ast_pkg::awire_t + `define INOUT_AO output ast_pkg::awire_t +`else + `define INOUT_AI inout + `define INOUT_AO inout +`endif + +endpackage diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling_rnd_cnst_pkg.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling_rnd_cnst_pkg.sv new file mode 100644 index 0000000000000..ae0469d61eb80 --- /dev/null +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling_rnd_cnst_pkg.sv @@ -0,0 +1,382 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \ +// -o hw/top_darjeeling/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + + +package top_darjeeling_rnd_cnst_pkg; + + //////////////////////////////////////////// + // otp_ctrl + //////////////////////////////////////////// + // Compile-time random bits for initial LFSR seed + parameter otp_ctrl_pkg::lfsr_seed_t RndCnstOtpCtrlLfsrSeed = { + 40'h50_8E576E43 + }; + + // Compile-time random permutation for LFSR output + parameter otp_ctrl_pkg::lfsr_perm_t RndCnstOtpCtrlLfsrPerm = { + 240'h7DA5_DD443190_81848F24_210E8DE8_A498830A_0015672C_74CD6E11_6559C654 + }; + + // Compile-time random permutation for scrambling key/nonce register reset value + parameter otp_ctrl_pkg::scrmbl_key_init_t RndCnstOtpCtrlScrmblKeyInit = { + 256'h986313D6_12FDCD62_AFD0C3A5_FC772CEB_91C16F5D_6E17DFF0_661BFBA6_F4E0571E + }; + + //////////////////////////////////////////// + // lc_ctrl + //////////////////////////////////////////// + // Diversification value used for all invalid life cycle states. + parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivInvalid = { + 128'hAE0FC6E6_A1A665F0_42709B54_CB121F70 + }; + + // Diversification value used for the TEST_UNLOCKED* life cycle states. + parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivTestUnlocked = { + 128'h02A405EC_DCF1FEB0_FA7A1487_7EC88637 + }; + + // Diversification value used for the DEV life cycle state. + parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivDev = { + 128'h87AF272E_FAA51F0D_E710C891_D47FF720 + }; + + // Diversification value used for the PROD/PROD_END life cycle states. + parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivProduction = { + 128'h9F95D614_848E3836_1CD9B7EB_23D532C0 + }; + + // Diversification value used for the RMA life cycle state. + parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivRma = { + 128'hAB44E1E9_2CCFEBAD_AD9193A3_EE4ECD8C + }; + + // Compile-time random bits used for invalid tokens in the token mux + parameter lc_ctrl_pkg::lc_token_mux_t RndCnstLcCtrlInvalidTokens = { + 256'h032462B3_E18549CB_1E70D5A8_3DE6673D_2C1C0A7B_55176264_E55C329C_8AE4725A, + 256'hEAF67281_50127AC7_55D70063_277642B5_309A1639_90B966CD_494444C3_BCDF8087, + 256'hB7FACD65_E9654CD8_5BC66D10_208C4FB5_1B97BBF4_D12C378C_CFD6A5A5_BF3032DB, + 256'h51FA1EB9_2F6CE10E_90F9C5C0_6F733DC9_11A321DD_4C0AC240_6D467215_DAB3F2B5 + }; + + //////////////////////////////////////////// + // alert_handler + //////////////////////////////////////////// + // Compile-time random bits for initial LFSR seed + parameter alert_pkg::lfsr_seed_t RndCnstAlertHandlerLfsrSeed = { + 32'h4A52E672 + }; + + // Compile-time random permutation for LFSR output + parameter alert_pkg::lfsr_perm_t RndCnstAlertHandlerLfsrPerm = { + 160'h1626CA23_5B3B6C12_4BFE5E54_EBF4A934_783055F0 + }; + + //////////////////////////////////////////// + // sram_ctrl_ret_aon + //////////////////////////////////////////// + // Compile-time random reset value for SRAM scrambling key. + parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlRetAonSramKey = { + 128'h55E0F815_0242862E_B20EEA9A_1F754471 + }; + + // Compile-time random reset value for SRAM scrambling nonce. + parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlRetAonSramNonce = { + 128'h6551512A_112DED67_8CE824A0_8E29C772 + }; + + // Compile-time random bits for initial LFSR seed + parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlRetAonLfsrSeed = { + 32'h795A358E + }; + + // Compile-time random permutation for LFSR output + parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlRetAonLfsrPerm = { + 160'h44CFC8B5_8B712090_29F2B7FA_22DE86DE_7D5D0C38 + }; + + //////////////////////////////////////////// + // aes + //////////////////////////////////////////// + // Default seed of the PRNG used for register clearing. + parameter aes_pkg::clearing_lfsr_seed_t RndCnstAesClearingLfsrSeed = { + 64'hD1095889_FBD8A7B5 + }; + + // Permutation applied to the LFSR of the PRNG used for clearing. + parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingLfsrPerm = { + 128'h392FA90D_E595FF71_3B4289DD_4E117922, + 256'h432F2804_49DB5525_06281AC8_698B62BB_B13CDF02_B73D2A71_B8D7F7AC_191F8B1F + }; + + // Permutation applied to the clearing PRNG output for clearing the second share of registers. + parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingSharePerm = { + 128'h03E5AB51_C865BF6D_4DDC1EB8_653F3233, + 256'h3B7DFCA2_4814FA1F_11D61B09_5A971EC8_101B4C0E_8D14A793_92E689E6_A9C6EEC3 + }; + + // Default seed of the PRNG used for masking. + parameter aes_pkg::masking_lfsr_seed_t RndCnstAesMaskingLfsrSeed = { + 32'h82FA14A8, + 256'hF2B75C26_5C9CB3B2_F1C44A72_87AB4C06_18822E92_A084A048_FFE9FB86_140A79D3 + }; + + // Permutation applied to the output of the PRNG used for masking. + parameter aes_pkg::masking_lfsr_perm_t RndCnstAesMaskingLfsrPerm = { + 256'h70666885_3241427A_1D566559_0D530C47_458C2397_5C21863C_917C5160_37078324, + 256'h8B9A7F93_73627706_5A392F1B_8E7E6F4E_81118A1C_79589D74_042B0817_710F252D, + 256'h48648819_2A2E4900_4610129E_1A319228_8257843F_894C090A_50695440_616A1E96, + 256'h6C362038_144D1595_35346D02_875D9C18_754A268F_0B015B1F_78137629_9827220E, + 256'h9F7B8D90_437D4F6B_3D723A05_63996716_9B30446E_52942C33_5E033E3B_5F4B5580 + }; + + //////////////////////////////////////////// + // kmac + //////////////////////////////////////////// + // Compile-time random data for PRNG default seed + parameter kmac_pkg::lfsr_seed_t RndCnstKmacLfsrSeed = { + 32'hE933D88E, + 256'h2E1CF654_60F23FB7_80499E6F_CCE64CEA_FD282C0E_33FD2C07_986C2A51_1755F072 + }; + + // Compile-time random permutation for PRNG output + parameter kmac_pkg::lfsr_perm_t RndCnstKmacLfsrPerm = { + 64'h99E8E296_3E89488B, + 256'h131D0C87_2324F634_25F3CEDE_85EF7490_761B0EC0_AD251FC8_163069A6_5313C5AD, + 256'hA542E455_D553AEB3_7506368D_F89C1876_C38C3186_C6AA35AC_ED838342_B42D8471, + 256'h88A8C868_5C27895E_B4905481_AF5DE7E8_7210799F_63A6AD13_88D0561B_49C2A1E9, + 256'h9B876359_2CAA899B_B52E072E_92BA9A20_ABD6235D_97AA5183_C30F09CF_F5BCDE2D, + 256'h5B6AE2E1_7B9347DD_7C97164A_698E620C_B22E087C_2318B809_0190182A_A8262847, + 256'hC4F77240_A1453AB1_8BF07857_400BE5BB_0D07C504_FE02279E_C0FC901A_03EC0C33, + 256'h9A18B255_4D68DCB1_9079BEEC_0C1C169B_D569B628_26ACE962_B26FCBB3_E4B11019, + 256'hEBE0A119_B149E27D_A4222AC4_5F423012_3306A30E_E28244BB_52CA91B2_7F56C759, + 256'hB0625D13_1A005F6F_F0956988_6C5932F6_B70D2345_CF83128C_7C9426E6_B049D957, + 256'h5EB1A899_5D16A728_E190ADB5_547B2E66_17E6D750_DA619DA7_216BD1B6_5D6AD934, + 256'h8F1699A5_43925E3B_DD8039A5_180002BE_B529C963_8B000C19_271EE67B_5C65C140, + 256'hB94D65E5_1B602125_9CC0A71E_5476C36E_9ACB0AB9_60504A79_1C6426C9_D1B4A1CE, + 256'h8ADC622B_1D7C0A50_195B377C_6B4D824A_FE9391AC_1B4DD07D_4A621871_8B56151D, + 256'hE7868FC3_8F17C142_9106E97F_1CD398B0_8D0A4BEA_FD13C217_490C355A_09048A6A, + 256'hAFE0A1C8_04DBC939_CC98F102_1CC45DA9_2AF8A3A2_CFE6E670_6C6D4A9E_3C804925, + 256'h40CA1571_911D2252_A83AEA43_44603C11_60A089F3_615C82EE_88B0D370_D2AA5A49, + 256'h161E14E4_802BAEF6_0A8FBE6D_912A6094_4CC0C68A_1F6B44CE_CD074491_79A8516C, + 256'h9825E403_CFBC557B_A75FB314_C25D4526_6910A857_1900C3B8_19D2F19C_8DB0A658, + 256'h0B7E9097_A1993CA4_7860B358_C4885037_0047E2D8_8474DD42_8B1E1D4D_C88E5927, + 256'h1F49D408_8A44BBB0_0D991126_54E72DE2_FB68FD3E_A3A9E50D_B7C35521_29ADA65B, + 256'hA93C118C_7512056F_90A65093_0650B532_F56B93B2_CA4D008A_883EB3B8_8898CA45, + 256'h49966275_7FBC2CA6_D58D1B81_07C83D41_E7C43E94_B6224A61_5A544363_645C4F82, + 256'h660DF8B1_EBBB2F13_69054A44_058FE1FA_AA2B9ED4_9779E94C_15F6DDDD_1D1CE8ED, + 256'hF3B3F08A_7C5AB40C_F08B1BA9_43B06DB8_6897395C_5BB20B89_88429683_C20985A1, + 256'hA89712F4_92914564_637BCEB8_102CC3A7_A7A98F6F_4CD9B92E_7FA55485_547FD3D7, + 256'h06523D1E_31E23323_A1962903_C4A0605D_3208E885_18CE662F_28361554_97245CE5, + 256'h9207353C_F5132691_5AEE9D80_CB90A99A_87725ED1_702304D6_AE4E16D9_C64FAF21, + 256'h30E941A3_5DC47E72_20CB4A5C_04C26D58_DD166101_C14EE740_99F61D13_114436A4, + 256'h70174ABB_5A5B94E9_B1BEF156_0208F6F3_5E091AAD_19596391_851E3827_F00C591F, + 256'h0C1069E0_3E2B03A9_42768D4A_0039B8E7_723D1A87_A85A81C5_B31370BD_2F4B44DB, + 256'h765601CB_D04673AB_16885AA2_55D7E54D_915E8143_6F1CC2D0_EBF15BA0_444C4638 + }; + + // Compile-time random data for PRNG buffer default seed + parameter kmac_pkg::buffer_lfsr_seed_t RndCnstKmacBufferLfsrSeed = { + 32'h46C49F15, + 256'hA16A2A1F_D01F8E09_D92DD13E_0298799D_91C54BFD_2A51F45A_ADF344C2_62BB0ABD, + 256'hE9B240D7_63DA6C42_50BA5A44_A7D4F4D7_F99B4A64_80DA2D53_E7CA1520_1A8F5653, + 256'h0010117F_58C9E994_6C111804_07FEB471_0F404E6E_4FACE59B_972D1FDC_AF711C05 + }; + + // Compile-time random permutation for LFSR Message output + parameter kmac_pkg::msg_perm_t RndCnstKmacMsgPerm = { + 128'h1ABBA9F8_CE16CF92_D4B5C3C2_6435ECD4, + 256'hDDE06154_85C5D6E8_9BB244D3_D7F0ABC0_641D3467_86323688_ABC0EB2F_E541E39A + }; + + //////////////////////////////////////////// + // otbn + //////////////////////////////////////////// + // Default seed of the PRNG used for URND. + parameter otbn_pkg::urnd_prng_seed_t RndCnstOtbnUrndPrngSeed = { + 256'hE24BE7E1_C96737B7_26A4C6F0_4993B3E6_AAE70F22_AAF748B5_7C320264_E157E2C7 + }; + + // Compile-time random reset value for IMem/DMem scrambling key. + parameter otp_ctrl_pkg::otbn_key_t RndCnstOtbnOtbnKey = { + 128'h4A280332_61EE6CEC_10075C55_A820F842 + }; + + // Compile-time random reset value for IMem/DMem scrambling nonce. + parameter otp_ctrl_pkg::otbn_nonce_t RndCnstOtbnOtbnNonce = { + 64'hD43EE1AB_1B3D78F9 + }; + + //////////////////////////////////////////// + // keymgr_dpe + //////////////////////////////////////////// + // Compile-time random bits for initial LFSR seed + parameter keymgr_pkg::lfsr_seed_t RndCnstKeymgrDpeLfsrSeed = { + 64'h92D22346_9898EB2A + }; + + // Compile-time random permutation for LFSR output + parameter keymgr_pkg::lfsr_perm_t RndCnstKeymgrDpeLfsrPerm = { + 128'hBA87C33D_D8319DE0_A103ECEC_EAD96923, + 256'h98EFC95D_9B938350_5FC4B550_B9B459CA_A265A3B0_311F5824_12AB4C5E_C71371BF + }; + + // Compile-time random permutation for entropy used in share overriding + parameter keymgr_pkg::rand_perm_t RndCnstKeymgrDpeRandPerm = { + 160'hBCE26820_3CC807B4_B242F394_F262A5B5_35F3F5AB + }; + + // Compile-time random bits for revision seed + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeRevisionSeed = { + 256'h5E456F3B_26D15F55_84BB9879_BD249785_2C23D0FA_289C3348_CE364ED5_34970E1F + }; + + // Compile-time random bits for software generation seed + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeSoftOutputSeed = { + 256'hD45EC606_BE134FC0_8318BD29_B22B08DF_647BDC30_068E7513_200FA828_BFEE3ECC + }; + + // Compile-time random bits for hardware generation seed + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeHardOutputSeed = { + 256'hF02417FA_68D00453_4267F60B_34A8F072_E77EE485_9B243F92_CEB098BE_6E65C359 + }; + + // Compile-time random bits for generation seed when aes destination selected + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeAesSeed = { + 256'h480858C3_9611E658_C97FB8D3_E9CC0E7F_8FA87252_00C726C8_F90EF5E2_B74BEEE2 + }; + + // Compile-time random bits for generation seed when kmac destination selected + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeKmacSeed = { + 256'h7CFA19EA_576CA8A8_225C8E17_053E44B6_8DD7822A_6859F2CF_52A55FD1_81B082D0 + }; + + // Compile-time random bits for generation seed when otbn destination selected + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeOtbnSeed = { + 256'h3C583756_F11AA5B3_7F9544C4_AA90EB97_E1C0F808_6F627A28_1C5681D6_566641EE + }; + + // Compile-time random bits for generation seed when no destination selected + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeNoneSeed = { + 256'hCCCC8887_6AD113C5_0AD1BE4D_94DCE8FC_A54128A3_860AE1D3_493FBEF6_B9BA5DFE + }; + + //////////////////////////////////////////// + // csrng + //////////////////////////////////////////// + // Compile-time random bits for csrng state group diversification value + parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivNonProduction = { + 128'h4463A461_5EF46762_A794A8C2_597E69FB, + 256'h259B9619_14CD75BB_FD36BA48_E780D27C_D582540C_7A68FF25_4EDFD852_829FECCC + }; + + // Compile-time random bits for csrng state group diversification value + parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivProduction = { + 128'hABD4AF9C_9032DA20_BDAF59FE_2AE209B8, + 256'h325D2C8C_35FC9606_79B106A8_7E59E6AE_B1B5302D_33401070_251696FB_B4BA169A + }; + + //////////////////////////////////////////// + // sram_ctrl_main + //////////////////////////////////////////// + // Compile-time random reset value for SRAM scrambling key. + parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlMainSramKey = { + 128'h6CD82FAD_46A0A5C0_4009BB93_4C7EF7B8 + }; + + // Compile-time random reset value for SRAM scrambling nonce. + parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlMainSramNonce = { + 128'h3B6E4061_0B4309FC_B9DC54D4_276137F9 + }; + + // Compile-time random bits for initial LFSR seed + parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlMainLfsrSeed = { + 32'h901D09A7 + }; + + // Compile-time random permutation for LFSR output + parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlMainLfsrPerm = { + 160'h1036ED2B_E8B646C8_24A692F9_5F1031B9_DF89D3AD + }; + + //////////////////////////////////////////// + // sram_ctrl_mbox + //////////////////////////////////////////// + // Compile-time random reset value for SRAM scrambling key. + parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlMboxSramKey = { + 128'hE927F6D9_E4ABAC39_8D42C745_EEF646C1 + }; + + // Compile-time random reset value for SRAM scrambling nonce. + parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlMboxSramNonce = { + 128'h464DCA86_DAFD7C7C_71E6058D_DFD871C5 + }; + + // Compile-time random bits for initial LFSR seed + parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlMboxLfsrSeed = { + 32'h1CACBAF4 + }; + + // Compile-time random permutation for LFSR output + parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlMboxLfsrPerm = { + 160'h2C32AE93_87FDA299_E9CCF52A_BBC8627B_4D8D8028 + }; + + //////////////////////////////////////////// + // rom_ctrl0 + //////////////////////////////////////////// + // Fixed nonce used for address / data scrambling + parameter bit [63:0] RndCnstRomCtrl0ScrNonce = { + 64'h6FD468A7_7EFDE3DE + }; + + // Randomised constant used as a scrambling key for ROM data + parameter bit [127:0] RndCnstRomCtrl0ScrKey = { + 128'h5B4CAF47_76A247BA_BA4C9908_ED16BC54 + }; + + //////////////////////////////////////////// + // rom_ctrl1 + //////////////////////////////////////////// + // Fixed nonce used for address / data scrambling + parameter bit [63:0] RndCnstRomCtrl1ScrNonce = { + 64'h15EC16D2_8C535513 + }; + + // Randomised constant used as a scrambling key for ROM data + parameter bit [127:0] RndCnstRomCtrl1ScrKey = { + 128'h12FCEDCF_2832A66C_EACF8ED4_D5B61617 + }; + + //////////////////////////////////////////// + // rv_core_ibex + //////////////////////////////////////////// + // Default seed of the PRNG used for random instructions. + parameter ibex_pkg::lfsr_seed_t RndCnstRvCoreIbexLfsrSeed = { + 32'h7DD43B56 + }; + + // Permutation applied to the LFSR of the PRNG used for random instructions. + parameter ibex_pkg::lfsr_perm_t RndCnstRvCoreIbexLfsrPerm = { + 160'h1440B451_B8D70817_96663DFD_BEE6D283_2AA1A5DF + }; + + // Default icache scrambling key + parameter logic [ibex_pkg::SCRAMBLE_KEY_W-1:0] RndCnstRvCoreIbexIbexKeyDefault = { + 128'h74F35C79_F397C4E4_C7E22B75_81848A90 + }; + + // Default icache scrambling nonce + parameter logic [ibex_pkg::SCRAMBLE_NONCE_W-1:0] RndCnstRvCoreIbexIbexNonceDefault = { + 64'hA1254B22_76BEC9FC + }; + +endpackage : top_darjeeling_rnd_cnst_pkg diff --git a/hw/top_darjeeling/sw/autogen/.clang-format b/hw/top_darjeeling/sw/autogen/.clang-format new file mode 100644 index 0000000000000..7cb47a7a72ec7 --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/.clang-format @@ -0,0 +1,4 @@ +# This disables clang-format on all files in the sw/autogen directory. +# This is needed so that git-clang-format and similar scripts work. +DisableFormat: true +SortIncludes: false diff --git a/hw/top_darjeeling/sw/autogen/chip/mod.rs b/hw/top_darjeeling/sw/autogen/chip/mod.rs new file mode 100644 index 0000000000000..f088e61f153dd --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/chip/mod.rs @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +pub mod top_darjeeling; diff --git a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs new file mode 100644 index 0000000000000..ea334bcfb33ee --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs @@ -0,0 +1,2796 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file was generated automatically. +// Please do not modify content of this file directly. +// File generated by using template: "toplevel.rs.tpl" +// To regenerate this file follow OpenTitan topgen documentations. + +#![allow(dead_code)] + +//! This file contains enums and consts for use within the Rust codebase. +//! +//! These definitions are for information that depends on the top-specific chip +//! configuration, which includes: +//! - Device Memory Information (for Peripherals and Memory) +//! - PLIC Interrupt ID Names and Source Mappings +//! - Alert ID Names and Source Mappings +//! - Pinmux Pin/Select Names +//! - Power Manager Wakeups + +use core::convert::TryFrom; + +/// Peripheral base address for uart0 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const UART0_BASE_ADDR: usize = 0x30010000; + +/// Peripheral size for uart0 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #UART0_BASE_ADDR and +/// `UART0_BASE_ADDR + UART0_SIZE_BYTES`. +pub const UART0_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for gpio in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const GPIO_BASE_ADDR: usize = 0x30000000; + +/// Peripheral size for gpio in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #GPIO_BASE_ADDR and +/// `GPIO_BASE_ADDR + GPIO_SIZE_BYTES`. +pub const GPIO_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for spi_device in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SPI_DEVICE_BASE_ADDR: usize = 0x30310000; + +/// Peripheral size for spi_device in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SPI_DEVICE_BASE_ADDR and +/// `SPI_DEVICE_BASE_ADDR + SPI_DEVICE_SIZE_BYTES`. +pub const SPI_DEVICE_SIZE_BYTES: usize = 0x2000; + +/// Peripheral base address for i2c0 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const I2C0_BASE_ADDR: usize = 0x30080000; + +/// Peripheral size for i2c0 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #I2C0_BASE_ADDR and +/// `I2C0_BASE_ADDR + I2C0_SIZE_BYTES`. +pub const I2C0_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for rv_timer in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const RV_TIMER_BASE_ADDR: usize = 0x30100000; + +/// Peripheral size for rv_timer in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #RV_TIMER_BASE_ADDR and +/// `RV_TIMER_BASE_ADDR + RV_TIMER_SIZE_BYTES`. +pub const RV_TIMER_SIZE_BYTES: usize = 0x200; + +/// Peripheral base address for core device on otp_ctrl in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const OTP_CTRL_CORE_BASE_ADDR: usize = 0x30130000; + +/// Peripheral size for core device on otp_ctrl in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #OTP_CTRL_CORE_BASE_ADDR and +/// `OTP_CTRL_CORE_BASE_ADDR + OTP_CTRL_CORE_SIZE_BYTES`. +pub const OTP_CTRL_CORE_SIZE_BYTES: usize = 0x1000; + +/// Peripheral base address for prim device on otp_ctrl in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const OTP_CTRL_PRIM_BASE_ADDR: usize = 0x30138000; + +/// Peripheral size for prim device on otp_ctrl in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #OTP_CTRL_PRIM_BASE_ADDR and +/// `OTP_CTRL_PRIM_BASE_ADDR + OTP_CTRL_PRIM_SIZE_BYTES`. +pub const OTP_CTRL_PRIM_SIZE_BYTES: usize = 0x20; + +/// Peripheral base address for regs device on lc_ctrl in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const LC_CTRL_REGS_BASE_ADDR: usize = 0x30140000; + +/// Peripheral size for regs device on lc_ctrl in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #LC_CTRL_REGS_BASE_ADDR and +/// `LC_CTRL_REGS_BASE_ADDR + LC_CTRL_REGS_SIZE_BYTES`. +pub const LC_CTRL_REGS_SIZE_BYTES: usize = 0x100; + +/// Peripheral base address for alert_handler in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const ALERT_HANDLER_BASE_ADDR: usize = 0x30150000; + +/// Peripheral size for alert_handler in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #ALERT_HANDLER_BASE_ADDR and +/// `ALERT_HANDLER_BASE_ADDR + ALERT_HANDLER_SIZE_BYTES`. +pub const ALERT_HANDLER_SIZE_BYTES: usize = 0x800; + +/// Peripheral base address for spi_host0 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SPI_HOST0_BASE_ADDR: usize = 0x30300000; + +/// Peripheral size for spi_host0 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SPI_HOST0_BASE_ADDR and +/// `SPI_HOST0_BASE_ADDR + SPI_HOST0_SIZE_BYTES`. +pub const SPI_HOST0_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for pwrmgr_aon in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const PWRMGR_AON_BASE_ADDR: usize = 0x30400000; + +/// Peripheral size for pwrmgr_aon in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #PWRMGR_AON_BASE_ADDR and +/// `PWRMGR_AON_BASE_ADDR + PWRMGR_AON_SIZE_BYTES`. +pub const PWRMGR_AON_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for rstmgr_aon in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const RSTMGR_AON_BASE_ADDR: usize = 0x30410000; + +/// Peripheral size for rstmgr_aon in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #RSTMGR_AON_BASE_ADDR and +/// `RSTMGR_AON_BASE_ADDR + RSTMGR_AON_SIZE_BYTES`. +pub const RSTMGR_AON_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for clkmgr_aon in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const CLKMGR_AON_BASE_ADDR: usize = 0x30420000; + +/// Peripheral size for clkmgr_aon in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #CLKMGR_AON_BASE_ADDR and +/// `CLKMGR_AON_BASE_ADDR + CLKMGR_AON_SIZE_BYTES`. +pub const CLKMGR_AON_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for pinmux_aon in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const PINMUX_AON_BASE_ADDR: usize = 0x30460000; + +/// Peripheral size for pinmux_aon in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #PINMUX_AON_BASE_ADDR and +/// `PINMUX_AON_BASE_ADDR + PINMUX_AON_SIZE_BYTES`. +pub const PINMUX_AON_SIZE_BYTES: usize = 0x800; + +/// Peripheral base address for aon_timer_aon in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const AON_TIMER_AON_BASE_ADDR: usize = 0x30470000; + +/// Peripheral size for aon_timer_aon in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #AON_TIMER_AON_BASE_ADDR and +/// `AON_TIMER_AON_BASE_ADDR + AON_TIMER_AON_SIZE_BYTES`. +pub const AON_TIMER_AON_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for ast in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const AST_BASE_ADDR: usize = 0x30480000; + +/// Peripheral size for ast in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #AST_BASE_ADDR and +/// `AST_BASE_ADDR + AST_SIZE_BYTES`. +pub const AST_SIZE_BYTES: usize = 0x400; + +/// Peripheral base address for sensor_ctrl in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SENSOR_CTRL_BASE_ADDR: usize = 0x30020000; + +/// Peripheral size for sensor_ctrl in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SENSOR_CTRL_BASE_ADDR and +/// `SENSOR_CTRL_BASE_ADDR + SENSOR_CTRL_SIZE_BYTES`. +pub const SENSOR_CTRL_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for core device on soc_proxy in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SOC_PROXY_CORE_BASE_ADDR: usize = 0x22030000; + +/// Peripheral size for core device on soc_proxy in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SOC_PROXY_CORE_BASE_ADDR and +/// `SOC_PROXY_CORE_BASE_ADDR + SOC_PROXY_CORE_SIZE_BYTES`. +pub const SOC_PROXY_CORE_SIZE_BYTES: usize = 0x10; + +/// Peripheral base address for ctn device on soc_proxy in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SOC_PROXY_CTN_BASE_ADDR: usize = 0x40000000; + +/// Peripheral size for ctn device on soc_proxy in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SOC_PROXY_CTN_BASE_ADDR and +/// `SOC_PROXY_CTN_BASE_ADDR + SOC_PROXY_CTN_SIZE_BYTES`. +pub const SOC_PROXY_CTN_SIZE_BYTES: usize = 0x40000000; + +/// Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SRAM_CTRL_RET_AON_REGS_BASE_ADDR: usize = 0x30500000; + +/// Peripheral size for regs device on sram_ctrl_ret_aon in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SRAM_CTRL_RET_AON_REGS_BASE_ADDR and +/// `SRAM_CTRL_RET_AON_REGS_BASE_ADDR + SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`. +pub const SRAM_CTRL_RET_AON_REGS_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for ram device on sram_ctrl_ret_aon in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SRAM_CTRL_RET_AON_RAM_BASE_ADDR: usize = 0x30600000; + +/// Peripheral size for ram device on sram_ctrl_ret_aon in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SRAM_CTRL_RET_AON_RAM_BASE_ADDR and +/// `SRAM_CTRL_RET_AON_RAM_BASE_ADDR + SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`. +pub const SRAM_CTRL_RET_AON_RAM_SIZE_BYTES: usize = 0x1000; + +/// Peripheral base address for regs device on rv_dm in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const RV_DM_REGS_BASE_ADDR: usize = 0x21200000; + +/// Peripheral size for regs device on rv_dm in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #RV_DM_REGS_BASE_ADDR and +/// `RV_DM_REGS_BASE_ADDR + RV_DM_REGS_SIZE_BYTES`. +pub const RV_DM_REGS_SIZE_BYTES: usize = 0x10; + +/// Peripheral base address for mem device on rv_dm in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const RV_DM_MEM_BASE_ADDR: usize = 0x40000; + +/// Peripheral size for mem device on rv_dm in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #RV_DM_MEM_BASE_ADDR and +/// `RV_DM_MEM_BASE_ADDR + RV_DM_MEM_SIZE_BYTES`. +pub const RV_DM_MEM_SIZE_BYTES: usize = 0x1000; + +/// Peripheral base address for rv_plic in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const RV_PLIC_BASE_ADDR: usize = 0x28000000; + +/// Peripheral size for rv_plic in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #RV_PLIC_BASE_ADDR and +/// `RV_PLIC_BASE_ADDR + RV_PLIC_SIZE_BYTES`. +pub const RV_PLIC_SIZE_BYTES: usize = 0x8000000; + +/// Peripheral base address for aes in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const AES_BASE_ADDR: usize = 0x21100000; + +/// Peripheral size for aes in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #AES_BASE_ADDR and +/// `AES_BASE_ADDR + AES_SIZE_BYTES`. +pub const AES_SIZE_BYTES: usize = 0x100; + +/// Peripheral base address for hmac in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const HMAC_BASE_ADDR: usize = 0x21110000; + +/// Peripheral size for hmac in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #HMAC_BASE_ADDR and +/// `HMAC_BASE_ADDR + HMAC_SIZE_BYTES`. +pub const HMAC_SIZE_BYTES: usize = 0x2000; + +/// Peripheral base address for kmac in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const KMAC_BASE_ADDR: usize = 0x21120000; + +/// Peripheral size for kmac in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #KMAC_BASE_ADDR and +/// `KMAC_BASE_ADDR + KMAC_SIZE_BYTES`. +pub const KMAC_SIZE_BYTES: usize = 0x1000; + +/// Peripheral base address for otbn in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const OTBN_BASE_ADDR: usize = 0x21130000; + +/// Peripheral size for otbn in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #OTBN_BASE_ADDR and +/// `OTBN_BASE_ADDR + OTBN_SIZE_BYTES`. +pub const OTBN_SIZE_BYTES: usize = 0x10000; + +/// Peripheral base address for keymgr_dpe in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const KEYMGR_DPE_BASE_ADDR: usize = 0x21140000; + +/// Peripheral size for keymgr_dpe in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #KEYMGR_DPE_BASE_ADDR and +/// `KEYMGR_DPE_BASE_ADDR + KEYMGR_DPE_SIZE_BYTES`. +pub const KEYMGR_DPE_SIZE_BYTES: usize = 0x100; + +/// Peripheral base address for csrng in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const CSRNG_BASE_ADDR: usize = 0x21150000; + +/// Peripheral size for csrng in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #CSRNG_BASE_ADDR and +/// `CSRNG_BASE_ADDR + CSRNG_SIZE_BYTES`. +pub const CSRNG_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for edn0 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const EDN0_BASE_ADDR: usize = 0x21170000; + +/// Peripheral size for edn0 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #EDN0_BASE_ADDR and +/// `EDN0_BASE_ADDR + EDN0_SIZE_BYTES`. +pub const EDN0_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for edn1 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const EDN1_BASE_ADDR: usize = 0x21180000; + +/// Peripheral size for edn1 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #EDN1_BASE_ADDR and +/// `EDN1_BASE_ADDR + EDN1_SIZE_BYTES`. +pub const EDN1_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for regs device on sram_ctrl_main in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SRAM_CTRL_MAIN_REGS_BASE_ADDR: usize = 0x211C0000; + +/// Peripheral size for regs device on sram_ctrl_main in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SRAM_CTRL_MAIN_REGS_BASE_ADDR and +/// `SRAM_CTRL_MAIN_REGS_BASE_ADDR + SRAM_CTRL_MAIN_REGS_SIZE_BYTES`. +pub const SRAM_CTRL_MAIN_REGS_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for ram device on sram_ctrl_main in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SRAM_CTRL_MAIN_RAM_BASE_ADDR: usize = 0x10000000; + +/// Peripheral size for ram device on sram_ctrl_main in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SRAM_CTRL_MAIN_RAM_BASE_ADDR and +/// `SRAM_CTRL_MAIN_RAM_BASE_ADDR + SRAM_CTRL_MAIN_RAM_SIZE_BYTES`. +pub const SRAM_CTRL_MAIN_RAM_SIZE_BYTES: usize = 0x10000; + +/// Peripheral base address for regs device on sram_ctrl_mbox in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SRAM_CTRL_MBOX_REGS_BASE_ADDR: usize = 0x211D0000; + +/// Peripheral size for regs device on sram_ctrl_mbox in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SRAM_CTRL_MBOX_REGS_BASE_ADDR and +/// `SRAM_CTRL_MBOX_REGS_BASE_ADDR + SRAM_CTRL_MBOX_REGS_SIZE_BYTES`. +pub const SRAM_CTRL_MBOX_REGS_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for ram device on sram_ctrl_mbox in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SRAM_CTRL_MBOX_RAM_BASE_ADDR: usize = 0x11000000; + +/// Peripheral size for ram device on sram_ctrl_mbox in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SRAM_CTRL_MBOX_RAM_BASE_ADDR and +/// `SRAM_CTRL_MBOX_RAM_BASE_ADDR + SRAM_CTRL_MBOX_RAM_SIZE_BYTES`. +pub const SRAM_CTRL_MBOX_RAM_SIZE_BYTES: usize = 0x1000; + +/// Peripheral base address for regs device on rom_ctrl0 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const ROM_CTRL0_REGS_BASE_ADDR: usize = 0x211E0000; + +/// Peripheral size for regs device on rom_ctrl0 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #ROM_CTRL0_REGS_BASE_ADDR and +/// `ROM_CTRL0_REGS_BASE_ADDR + ROM_CTRL0_REGS_SIZE_BYTES`. +pub const ROM_CTRL0_REGS_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for rom device on rom_ctrl0 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const ROM_CTRL0_ROM_BASE_ADDR: usize = 0x8000; + +/// Peripheral size for rom device on rom_ctrl0 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #ROM_CTRL0_ROM_BASE_ADDR and +/// `ROM_CTRL0_ROM_BASE_ADDR + ROM_CTRL0_ROM_SIZE_BYTES`. +pub const ROM_CTRL0_ROM_SIZE_BYTES: usize = 0x8000; + +/// Peripheral base address for regs device on rom_ctrl1 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const ROM_CTRL1_REGS_BASE_ADDR: usize = 0x211E1000; + +/// Peripheral size for regs device on rom_ctrl1 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #ROM_CTRL1_REGS_BASE_ADDR and +/// `ROM_CTRL1_REGS_BASE_ADDR + ROM_CTRL1_REGS_SIZE_BYTES`. +pub const ROM_CTRL1_REGS_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for rom device on rom_ctrl1 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const ROM_CTRL1_ROM_BASE_ADDR: usize = 0x20000; + +/// Peripheral size for rom device on rom_ctrl1 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #ROM_CTRL1_ROM_BASE_ADDR and +/// `ROM_CTRL1_ROM_BASE_ADDR + ROM_CTRL1_ROM_SIZE_BYTES`. +pub const ROM_CTRL1_ROM_SIZE_BYTES: usize = 0x10000; + +/// Peripheral base address for dma in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const DMA_BASE_ADDR: usize = 0x22010000; + +/// Peripheral size for dma in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #DMA_BASE_ADDR and +/// `DMA_BASE_ADDR + DMA_SIZE_BYTES`. +pub const DMA_SIZE_BYTES: usize = 0x200; + +/// Peripheral base address for core device on mbx0 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX0_CORE_BASE_ADDR: usize = 0x22000000; + +/// Peripheral size for core device on mbx0 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX0_CORE_BASE_ADDR and +/// `MBX0_CORE_BASE_ADDR + MBX0_CORE_SIZE_BYTES`. +pub const MBX0_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx1 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX1_CORE_BASE_ADDR: usize = 0x22000100; + +/// Peripheral size for core device on mbx1 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX1_CORE_BASE_ADDR and +/// `MBX1_CORE_BASE_ADDR + MBX1_CORE_SIZE_BYTES`. +pub const MBX1_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx2 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX2_CORE_BASE_ADDR: usize = 0x22000200; + +/// Peripheral size for core device on mbx2 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX2_CORE_BASE_ADDR and +/// `MBX2_CORE_BASE_ADDR + MBX2_CORE_SIZE_BYTES`. +pub const MBX2_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx3 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX3_CORE_BASE_ADDR: usize = 0x22000300; + +/// Peripheral size for core device on mbx3 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX3_CORE_BASE_ADDR and +/// `MBX3_CORE_BASE_ADDR + MBX3_CORE_SIZE_BYTES`. +pub const MBX3_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx4 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX4_CORE_BASE_ADDR: usize = 0x22000400; + +/// Peripheral size for core device on mbx4 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX4_CORE_BASE_ADDR and +/// `MBX4_CORE_BASE_ADDR + MBX4_CORE_SIZE_BYTES`. +pub const MBX4_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx5 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX5_CORE_BASE_ADDR: usize = 0x22000500; + +/// Peripheral size for core device on mbx5 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX5_CORE_BASE_ADDR and +/// `MBX5_CORE_BASE_ADDR + MBX5_CORE_SIZE_BYTES`. +pub const MBX5_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx6 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX6_CORE_BASE_ADDR: usize = 0x22000600; + +/// Peripheral size for core device on mbx6 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX6_CORE_BASE_ADDR and +/// `MBX6_CORE_BASE_ADDR + MBX6_CORE_SIZE_BYTES`. +pub const MBX6_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx_jtag in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX_JTAG_CORE_BASE_ADDR: usize = 0x22000800; + +/// Peripheral size for core device on mbx_jtag in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX_JTAG_CORE_BASE_ADDR and +/// `MBX_JTAG_CORE_BASE_ADDR + MBX_JTAG_CORE_SIZE_BYTES`. +pub const MBX_JTAG_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx_pcie0 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX_PCIE0_CORE_BASE_ADDR: usize = 0x22040000; + +/// Peripheral size for core device on mbx_pcie0 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX_PCIE0_CORE_BASE_ADDR and +/// `MBX_PCIE0_CORE_BASE_ADDR + MBX_PCIE0_CORE_SIZE_BYTES`. +pub const MBX_PCIE0_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx_pcie1 in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX_PCIE1_CORE_BASE_ADDR: usize = 0x22040100; + +/// Peripheral size for core device on mbx_pcie1 in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX_PCIE1_CORE_BASE_ADDR and +/// `MBX_PCIE1_CORE_BASE_ADDR + MBX_PCIE1_CORE_SIZE_BYTES`. +pub const MBX_PCIE1_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for cfg device on rv_core_ibex in top darjeeling. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const RV_CORE_IBEX_CFG_BASE_ADDR: usize = 0x211F0000; + +/// Peripheral size for cfg device on rv_core_ibex in top darjeeling. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #RV_CORE_IBEX_CFG_BASE_ADDR and +/// `RV_CORE_IBEX_CFG_BASE_ADDR + RV_CORE_IBEX_CFG_SIZE_BYTES`. +pub const RV_CORE_IBEX_CFG_SIZE_BYTES: usize = 0x100; + +/// Memory base address for ctn in top darjeeling. +pub const CTN_BASE_ADDR: usize = 0x40000000; + +/// Memory size for ctn in top darjeeling. +pub const CTN_SIZE_BYTES: usize = 0x40000000; + +/// Memory base address for ram_ret_aon in top darjeeling. +pub const RAM_RET_AON_BASE_ADDR: usize = 0x30600000; + +/// Memory size for ram_ret_aon in top darjeeling. +pub const RAM_RET_AON_SIZE_BYTES: usize = 0x1000; + +/// Memory base address for ram_main in top darjeeling. +pub const RAM_MAIN_BASE_ADDR: usize = 0x10000000; + +/// Memory size for ram_main in top darjeeling. +pub const RAM_MAIN_SIZE_BYTES: usize = 0x10000; + +/// Memory base address for ram_mbox in top darjeeling. +pub const RAM_MBOX_BASE_ADDR: usize = 0x11000000; + +/// Memory size for ram_mbox in top darjeeling. +pub const RAM_MBOX_SIZE_BYTES: usize = 0x1000; + +/// Memory base address for rom0 in top darjeeling. +pub const ROM0_BASE_ADDR: usize = 0x8000; + +/// Memory size for rom0 in top darjeeling. +pub const ROM0_SIZE_BYTES: usize = 0x8000; + +/// Memory base address for rom1 in top darjeeling. +pub const ROM1_BASE_ADDR: usize = 0x20000; + +/// Memory size for rom1 in top darjeeling. +pub const ROM1_SIZE_BYTES: usize = 0x10000; + +/// PLIC Interrupt Source Peripheral. +/// +/// Enumeration used to determine which peripheral asserted the corresponding +/// interrupt. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PlicPeripheral { + /// Unknown Peripheral + Unknown = 0, + /// uart0 + Uart0 = 1, + /// gpio + Gpio = 2, + /// spi_device + SpiDevice = 3, + /// i2c0 + I2c0 = 4, + /// rv_timer + RvTimer = 5, + /// otp_ctrl + OtpCtrl = 6, + /// alert_handler + AlertHandler = 7, + /// spi_host0 + SpiHost0 = 8, + /// pwrmgr_aon + PwrmgrAon = 9, + /// aon_timer_aon + AonTimerAon = 10, + /// sensor_ctrl + SensorCtrl = 11, + /// soc_proxy + SocProxy = 12, + /// hmac + Hmac = 13, + /// kmac + Kmac = 14, + /// otbn + Otbn = 15, + /// keymgr_dpe + KeymgrDpe = 16, + /// csrng + Csrng = 17, + /// edn0 + Edn0 = 18, + /// edn1 + Edn1 = 19, + /// dma + Dma = 20, + /// mbx0 + Mbx0 = 21, + /// mbx1 + Mbx1 = 22, + /// mbx2 + Mbx2 = 23, + /// mbx3 + Mbx3 = 24, + /// mbx4 + Mbx4 = 25, + /// mbx5 + Mbx5 = 26, + /// mbx6 + Mbx6 = 27, + /// mbx_jtag + MbxJtag = 28, + /// mbx_pcie0 + MbxPcie0 = 29, + /// mbx_pcie1 + MbxPcie1 = 30, +} + +impl TryFrom for PlicPeripheral { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::Unknown), + 1 => Ok(Self::Uart0), + 2 => Ok(Self::Gpio), + 3 => Ok(Self::SpiDevice), + 4 => Ok(Self::I2c0), + 5 => Ok(Self::RvTimer), + 6 => Ok(Self::OtpCtrl), + 7 => Ok(Self::AlertHandler), + 8 => Ok(Self::SpiHost0), + 9 => Ok(Self::PwrmgrAon), + 10 => Ok(Self::AonTimerAon), + 11 => Ok(Self::SensorCtrl), + 12 => Ok(Self::SocProxy), + 13 => Ok(Self::Hmac), + 14 => Ok(Self::Kmac), + 15 => Ok(Self::Otbn), + 16 => Ok(Self::KeymgrDpe), + 17 => Ok(Self::Csrng), + 18 => Ok(Self::Edn0), + 19 => Ok(Self::Edn1), + 20 => Ok(Self::Dma), + 21 => Ok(Self::Mbx0), + 22 => Ok(Self::Mbx1), + 23 => Ok(Self::Mbx2), + 24 => Ok(Self::Mbx3), + 25 => Ok(Self::Mbx4), + 26 => Ok(Self::Mbx5), + 27 => Ok(Self::Mbx6), + 28 => Ok(Self::MbxJtag), + 29 => Ok(Self::MbxPcie0), + 30 => Ok(Self::MbxPcie1), + _ => Err(val), + } + } +} + +/// PLIC Interrupt Source. +/// +/// Enumeration of all PLIC interrupt sources. The interrupt sources belonging to +/// the same peripheral are guaranteed to be consecutive. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PlicIrqId { + /// No Interrupt + None = 0, + /// uart0_tx_watermark + Uart0TxWatermark = 1, + /// uart0_rx_watermark + Uart0RxWatermark = 2, + /// uart0_tx_done + Uart0TxDone = 3, + /// uart0_rx_overflow + Uart0RxOverflow = 4, + /// uart0_rx_frame_err + Uart0RxFrameErr = 5, + /// uart0_rx_break_err + Uart0RxBreakErr = 6, + /// uart0_rx_timeout + Uart0RxTimeout = 7, + /// uart0_rx_parity_err + Uart0RxParityErr = 8, + /// uart0_tx_empty + Uart0TxEmpty = 9, + /// gpio_gpio 0 + GpioGpio0 = 10, + /// gpio_gpio 1 + GpioGpio1 = 11, + /// gpio_gpio 2 + GpioGpio2 = 12, + /// gpio_gpio 3 + GpioGpio3 = 13, + /// gpio_gpio 4 + GpioGpio4 = 14, + /// gpio_gpio 5 + GpioGpio5 = 15, + /// gpio_gpio 6 + GpioGpio6 = 16, + /// gpio_gpio 7 + GpioGpio7 = 17, + /// gpio_gpio 8 + GpioGpio8 = 18, + /// gpio_gpio 9 + GpioGpio9 = 19, + /// gpio_gpio 10 + GpioGpio10 = 20, + /// gpio_gpio 11 + GpioGpio11 = 21, + /// gpio_gpio 12 + GpioGpio12 = 22, + /// gpio_gpio 13 + GpioGpio13 = 23, + /// gpio_gpio 14 + GpioGpio14 = 24, + /// gpio_gpio 15 + GpioGpio15 = 25, + /// gpio_gpio 16 + GpioGpio16 = 26, + /// gpio_gpio 17 + GpioGpio17 = 27, + /// gpio_gpio 18 + GpioGpio18 = 28, + /// gpio_gpio 19 + GpioGpio19 = 29, + /// gpio_gpio 20 + GpioGpio20 = 30, + /// gpio_gpio 21 + GpioGpio21 = 31, + /// gpio_gpio 22 + GpioGpio22 = 32, + /// gpio_gpio 23 + GpioGpio23 = 33, + /// gpio_gpio 24 + GpioGpio24 = 34, + /// gpio_gpio 25 + GpioGpio25 = 35, + /// gpio_gpio 26 + GpioGpio26 = 36, + /// gpio_gpio 27 + GpioGpio27 = 37, + /// gpio_gpio 28 + GpioGpio28 = 38, + /// gpio_gpio 29 + GpioGpio29 = 39, + /// gpio_gpio 30 + GpioGpio30 = 40, + /// gpio_gpio 31 + GpioGpio31 = 41, + /// spi_device_upload_cmdfifo_not_empty + SpiDeviceUploadCmdfifoNotEmpty = 42, + /// spi_device_upload_payload_not_empty + SpiDeviceUploadPayloadNotEmpty = 43, + /// spi_device_upload_payload_overflow + SpiDeviceUploadPayloadOverflow = 44, + /// spi_device_readbuf_watermark + SpiDeviceReadbufWatermark = 45, + /// spi_device_readbuf_flip + SpiDeviceReadbufFlip = 46, + /// spi_device_tpm_header_not_empty + SpiDeviceTpmHeaderNotEmpty = 47, + /// spi_device_tpm_rdfifo_cmd_end + SpiDeviceTpmRdfifoCmdEnd = 48, + /// spi_device_tpm_rdfifo_drop + SpiDeviceTpmRdfifoDrop = 49, + /// i2c0_fmt_threshold + I2c0FmtThreshold = 50, + /// i2c0_rx_threshold + I2c0RxThreshold = 51, + /// i2c0_acq_threshold + I2c0AcqThreshold = 52, + /// i2c0_rx_overflow + I2c0RxOverflow = 53, + /// i2c0_controller_halt + I2c0ControllerHalt = 54, + /// i2c0_scl_interference + I2c0SclInterference = 55, + /// i2c0_sda_interference + I2c0SdaInterference = 56, + /// i2c0_stretch_timeout + I2c0StretchTimeout = 57, + /// i2c0_sda_unstable + I2c0SdaUnstable = 58, + /// i2c0_cmd_complete + I2c0CmdComplete = 59, + /// i2c0_tx_stretch + I2c0TxStretch = 60, + /// i2c0_tx_threshold + I2c0TxThreshold = 61, + /// i2c0_acq_stretch + I2c0AcqStretch = 62, + /// i2c0_unexp_stop + I2c0UnexpStop = 63, + /// i2c0_host_timeout + I2c0HostTimeout = 64, + /// rv_timer_timer_expired_hart0_timer0 + RvTimerTimerExpiredHart0Timer0 = 65, + /// otp_ctrl_otp_operation_done + OtpCtrlOtpOperationDone = 66, + /// otp_ctrl_otp_error + OtpCtrlOtpError = 67, + /// alert_handler_classa + AlertHandlerClassa = 68, + /// alert_handler_classb + AlertHandlerClassb = 69, + /// alert_handler_classc + AlertHandlerClassc = 70, + /// alert_handler_classd + AlertHandlerClassd = 71, + /// spi_host0_error + SpiHost0Error = 72, + /// spi_host0_spi_event + SpiHost0SpiEvent = 73, + /// pwrmgr_aon_wakeup + PwrmgrAonWakeup = 74, + /// aon_timer_aon_wkup_timer_expired + AonTimerAonWkupTimerExpired = 75, + /// aon_timer_aon_wdog_timer_bark + AonTimerAonWdogTimerBark = 76, + /// sensor_ctrl_io_status_change + SensorCtrlIoStatusChange = 77, + /// sensor_ctrl_init_status_change + SensorCtrlInitStatusChange = 78, + /// soc_proxy_external 0 + SocProxyExternal0 = 79, + /// soc_proxy_external 1 + SocProxyExternal1 = 80, + /// soc_proxy_external 2 + SocProxyExternal2 = 81, + /// soc_proxy_external 3 + SocProxyExternal3 = 82, + /// soc_proxy_external 4 + SocProxyExternal4 = 83, + /// soc_proxy_external 5 + SocProxyExternal5 = 84, + /// soc_proxy_external 6 + SocProxyExternal6 = 85, + /// soc_proxy_external 7 + SocProxyExternal7 = 86, + /// soc_proxy_external 8 + SocProxyExternal8 = 87, + /// soc_proxy_external 9 + SocProxyExternal9 = 88, + /// soc_proxy_external 10 + SocProxyExternal10 = 89, + /// soc_proxy_external 11 + SocProxyExternal11 = 90, + /// soc_proxy_external 12 + SocProxyExternal12 = 91, + /// soc_proxy_external 13 + SocProxyExternal13 = 92, + /// soc_proxy_external 14 + SocProxyExternal14 = 93, + /// soc_proxy_external 15 + SocProxyExternal15 = 94, + /// soc_proxy_external 16 + SocProxyExternal16 = 95, + /// soc_proxy_external 17 + SocProxyExternal17 = 96, + /// soc_proxy_external 18 + SocProxyExternal18 = 97, + /// soc_proxy_external 19 + SocProxyExternal19 = 98, + /// soc_proxy_external 20 + SocProxyExternal20 = 99, + /// soc_proxy_external 21 + SocProxyExternal21 = 100, + /// soc_proxy_external 22 + SocProxyExternal22 = 101, + /// soc_proxy_external 23 + SocProxyExternal23 = 102, + /// soc_proxy_external 24 + SocProxyExternal24 = 103, + /// soc_proxy_external 25 + SocProxyExternal25 = 104, + /// soc_proxy_external 26 + SocProxyExternal26 = 105, + /// soc_proxy_external 27 + SocProxyExternal27 = 106, + /// soc_proxy_external 28 + SocProxyExternal28 = 107, + /// soc_proxy_external 29 + SocProxyExternal29 = 108, + /// soc_proxy_external 30 + SocProxyExternal30 = 109, + /// soc_proxy_external 31 + SocProxyExternal31 = 110, + /// hmac_hmac_done + HmacHmacDone = 111, + /// hmac_fifo_empty + HmacFifoEmpty = 112, + /// hmac_hmac_err + HmacHmacErr = 113, + /// kmac_kmac_done + KmacKmacDone = 114, + /// kmac_fifo_empty + KmacFifoEmpty = 115, + /// kmac_kmac_err + KmacKmacErr = 116, + /// otbn_done + OtbnDone = 117, + /// keymgr_dpe_op_done + KeymgrDpeOpDone = 118, + /// csrng_cs_cmd_req_done + CsrngCsCmdReqDone = 119, + /// csrng_cs_entropy_req + CsrngCsEntropyReq = 120, + /// csrng_cs_hw_inst_exc + CsrngCsHwInstExc = 121, + /// csrng_cs_fatal_err + CsrngCsFatalErr = 122, + /// edn0_edn_cmd_req_done + Edn0EdnCmdReqDone = 123, + /// edn0_edn_fatal_err + Edn0EdnFatalErr = 124, + /// edn1_edn_cmd_req_done + Edn1EdnCmdReqDone = 125, + /// edn1_edn_fatal_err + Edn1EdnFatalErr = 126, + /// dma_dma_done + DmaDmaDone = 127, + /// dma_dma_chunk_done + DmaDmaChunkDone = 128, + /// dma_dma_error + DmaDmaError = 129, + /// mbx0_mbx_ready + Mbx0MbxReady = 130, + /// mbx0_mbx_abort + Mbx0MbxAbort = 131, + /// mbx0_mbx_error + Mbx0MbxError = 132, + /// mbx1_mbx_ready + Mbx1MbxReady = 133, + /// mbx1_mbx_abort + Mbx1MbxAbort = 134, + /// mbx1_mbx_error + Mbx1MbxError = 135, + /// mbx2_mbx_ready + Mbx2MbxReady = 136, + /// mbx2_mbx_abort + Mbx2MbxAbort = 137, + /// mbx2_mbx_error + Mbx2MbxError = 138, + /// mbx3_mbx_ready + Mbx3MbxReady = 139, + /// mbx3_mbx_abort + Mbx3MbxAbort = 140, + /// mbx3_mbx_error + Mbx3MbxError = 141, + /// mbx4_mbx_ready + Mbx4MbxReady = 142, + /// mbx4_mbx_abort + Mbx4MbxAbort = 143, + /// mbx4_mbx_error + Mbx4MbxError = 144, + /// mbx5_mbx_ready + Mbx5MbxReady = 145, + /// mbx5_mbx_abort + Mbx5MbxAbort = 146, + /// mbx5_mbx_error + Mbx5MbxError = 147, + /// mbx6_mbx_ready + Mbx6MbxReady = 148, + /// mbx6_mbx_abort + Mbx6MbxAbort = 149, + /// mbx6_mbx_error + Mbx6MbxError = 150, + /// mbx_jtag_mbx_ready + MbxJtagMbxReady = 151, + /// mbx_jtag_mbx_abort + MbxJtagMbxAbort = 152, + /// mbx_jtag_mbx_error + MbxJtagMbxError = 153, + /// mbx_pcie0_mbx_ready + MbxPcie0MbxReady = 154, + /// mbx_pcie0_mbx_abort + MbxPcie0MbxAbort = 155, + /// mbx_pcie0_mbx_error + MbxPcie0MbxError = 156, + /// mbx_pcie1_mbx_ready + MbxPcie1MbxReady = 157, + /// mbx_pcie1_mbx_abort + MbxPcie1MbxAbort = 158, + /// mbx_pcie1_mbx_error + MbxPcie1MbxError = 159, +} + +impl TryFrom for PlicIrqId { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::None), + 1 => Ok(Self::Uart0TxWatermark), + 2 => Ok(Self::Uart0RxWatermark), + 3 => Ok(Self::Uart0TxDone), + 4 => Ok(Self::Uart0RxOverflow), + 5 => Ok(Self::Uart0RxFrameErr), + 6 => Ok(Self::Uart0RxBreakErr), + 7 => Ok(Self::Uart0RxTimeout), + 8 => Ok(Self::Uart0RxParityErr), + 9 => Ok(Self::Uart0TxEmpty), + 10 => Ok(Self::GpioGpio0), + 11 => Ok(Self::GpioGpio1), + 12 => Ok(Self::GpioGpio2), + 13 => Ok(Self::GpioGpio3), + 14 => Ok(Self::GpioGpio4), + 15 => Ok(Self::GpioGpio5), + 16 => Ok(Self::GpioGpio6), + 17 => Ok(Self::GpioGpio7), + 18 => Ok(Self::GpioGpio8), + 19 => Ok(Self::GpioGpio9), + 20 => Ok(Self::GpioGpio10), + 21 => Ok(Self::GpioGpio11), + 22 => Ok(Self::GpioGpio12), + 23 => Ok(Self::GpioGpio13), + 24 => Ok(Self::GpioGpio14), + 25 => Ok(Self::GpioGpio15), + 26 => Ok(Self::GpioGpio16), + 27 => Ok(Self::GpioGpio17), + 28 => Ok(Self::GpioGpio18), + 29 => Ok(Self::GpioGpio19), + 30 => Ok(Self::GpioGpio20), + 31 => Ok(Self::GpioGpio21), + 32 => Ok(Self::GpioGpio22), + 33 => Ok(Self::GpioGpio23), + 34 => Ok(Self::GpioGpio24), + 35 => Ok(Self::GpioGpio25), + 36 => Ok(Self::GpioGpio26), + 37 => Ok(Self::GpioGpio27), + 38 => Ok(Self::GpioGpio28), + 39 => Ok(Self::GpioGpio29), + 40 => Ok(Self::GpioGpio30), + 41 => Ok(Self::GpioGpio31), + 42 => Ok(Self::SpiDeviceUploadCmdfifoNotEmpty), + 43 => Ok(Self::SpiDeviceUploadPayloadNotEmpty), + 44 => Ok(Self::SpiDeviceUploadPayloadOverflow), + 45 => Ok(Self::SpiDeviceReadbufWatermark), + 46 => Ok(Self::SpiDeviceReadbufFlip), + 47 => Ok(Self::SpiDeviceTpmHeaderNotEmpty), + 48 => Ok(Self::SpiDeviceTpmRdfifoCmdEnd), + 49 => Ok(Self::SpiDeviceTpmRdfifoDrop), + 50 => Ok(Self::I2c0FmtThreshold), + 51 => Ok(Self::I2c0RxThreshold), + 52 => Ok(Self::I2c0AcqThreshold), + 53 => Ok(Self::I2c0RxOverflow), + 54 => Ok(Self::I2c0ControllerHalt), + 55 => Ok(Self::I2c0SclInterference), + 56 => Ok(Self::I2c0SdaInterference), + 57 => Ok(Self::I2c0StretchTimeout), + 58 => Ok(Self::I2c0SdaUnstable), + 59 => Ok(Self::I2c0CmdComplete), + 60 => Ok(Self::I2c0TxStretch), + 61 => Ok(Self::I2c0TxThreshold), + 62 => Ok(Self::I2c0AcqStretch), + 63 => Ok(Self::I2c0UnexpStop), + 64 => Ok(Self::I2c0HostTimeout), + 65 => Ok(Self::RvTimerTimerExpiredHart0Timer0), + 66 => Ok(Self::OtpCtrlOtpOperationDone), + 67 => Ok(Self::OtpCtrlOtpError), + 68 => Ok(Self::AlertHandlerClassa), + 69 => Ok(Self::AlertHandlerClassb), + 70 => Ok(Self::AlertHandlerClassc), + 71 => Ok(Self::AlertHandlerClassd), + 72 => Ok(Self::SpiHost0Error), + 73 => Ok(Self::SpiHost0SpiEvent), + 74 => Ok(Self::PwrmgrAonWakeup), + 75 => Ok(Self::AonTimerAonWkupTimerExpired), + 76 => Ok(Self::AonTimerAonWdogTimerBark), + 77 => Ok(Self::SensorCtrlIoStatusChange), + 78 => Ok(Self::SensorCtrlInitStatusChange), + 79 => Ok(Self::SocProxyExternal0), + 80 => Ok(Self::SocProxyExternal1), + 81 => Ok(Self::SocProxyExternal2), + 82 => Ok(Self::SocProxyExternal3), + 83 => Ok(Self::SocProxyExternal4), + 84 => Ok(Self::SocProxyExternal5), + 85 => Ok(Self::SocProxyExternal6), + 86 => Ok(Self::SocProxyExternal7), + 87 => Ok(Self::SocProxyExternal8), + 88 => Ok(Self::SocProxyExternal9), + 89 => Ok(Self::SocProxyExternal10), + 90 => Ok(Self::SocProxyExternal11), + 91 => Ok(Self::SocProxyExternal12), + 92 => Ok(Self::SocProxyExternal13), + 93 => Ok(Self::SocProxyExternal14), + 94 => Ok(Self::SocProxyExternal15), + 95 => Ok(Self::SocProxyExternal16), + 96 => Ok(Self::SocProxyExternal17), + 97 => Ok(Self::SocProxyExternal18), + 98 => Ok(Self::SocProxyExternal19), + 99 => Ok(Self::SocProxyExternal20), + 100 => Ok(Self::SocProxyExternal21), + 101 => Ok(Self::SocProxyExternal22), + 102 => Ok(Self::SocProxyExternal23), + 103 => Ok(Self::SocProxyExternal24), + 104 => Ok(Self::SocProxyExternal25), + 105 => Ok(Self::SocProxyExternal26), + 106 => Ok(Self::SocProxyExternal27), + 107 => Ok(Self::SocProxyExternal28), + 108 => Ok(Self::SocProxyExternal29), + 109 => Ok(Self::SocProxyExternal30), + 110 => Ok(Self::SocProxyExternal31), + 111 => Ok(Self::HmacHmacDone), + 112 => Ok(Self::HmacFifoEmpty), + 113 => Ok(Self::HmacHmacErr), + 114 => Ok(Self::KmacKmacDone), + 115 => Ok(Self::KmacFifoEmpty), + 116 => Ok(Self::KmacKmacErr), + 117 => Ok(Self::OtbnDone), + 118 => Ok(Self::KeymgrDpeOpDone), + 119 => Ok(Self::CsrngCsCmdReqDone), + 120 => Ok(Self::CsrngCsEntropyReq), + 121 => Ok(Self::CsrngCsHwInstExc), + 122 => Ok(Self::CsrngCsFatalErr), + 123 => Ok(Self::Edn0EdnCmdReqDone), + 124 => Ok(Self::Edn0EdnFatalErr), + 125 => Ok(Self::Edn1EdnCmdReqDone), + 126 => Ok(Self::Edn1EdnFatalErr), + 127 => Ok(Self::DmaDmaDone), + 128 => Ok(Self::DmaDmaChunkDone), + 129 => Ok(Self::DmaDmaError), + 130 => Ok(Self::Mbx0MbxReady), + 131 => Ok(Self::Mbx0MbxAbort), + 132 => Ok(Self::Mbx0MbxError), + 133 => Ok(Self::Mbx1MbxReady), + 134 => Ok(Self::Mbx1MbxAbort), + 135 => Ok(Self::Mbx1MbxError), + 136 => Ok(Self::Mbx2MbxReady), + 137 => Ok(Self::Mbx2MbxAbort), + 138 => Ok(Self::Mbx2MbxError), + 139 => Ok(Self::Mbx3MbxReady), + 140 => Ok(Self::Mbx3MbxAbort), + 141 => Ok(Self::Mbx3MbxError), + 142 => Ok(Self::Mbx4MbxReady), + 143 => Ok(Self::Mbx4MbxAbort), + 144 => Ok(Self::Mbx4MbxError), + 145 => Ok(Self::Mbx5MbxReady), + 146 => Ok(Self::Mbx5MbxAbort), + 147 => Ok(Self::Mbx5MbxError), + 148 => Ok(Self::Mbx6MbxReady), + 149 => Ok(Self::Mbx6MbxAbort), + 150 => Ok(Self::Mbx6MbxError), + 151 => Ok(Self::MbxJtagMbxReady), + 152 => Ok(Self::MbxJtagMbxAbort), + 153 => Ok(Self::MbxJtagMbxError), + 154 => Ok(Self::MbxPcie0MbxReady), + 155 => Ok(Self::MbxPcie0MbxAbort), + 156 => Ok(Self::MbxPcie0MbxError), + 157 => Ok(Self::MbxPcie1MbxReady), + 158 => Ok(Self::MbxPcie1MbxAbort), + 159 => Ok(Self::MbxPcie1MbxError), + _ => Err(val), + } + } +} + +/// PLIC Interrupt Target. +/// +/// Enumeration used to determine which set of IE, CC, threshold registers to +/// access for a given interrupt target. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PlicTarget { + /// Ibex Core 0 + Ibex0 = 0, +} + +/// Alert Handler Source Peripheral. +/// +/// Enumeration used to determine which peripheral asserted the corresponding +/// alert. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum AlertPeripheral { + /// uart0 + Uart0 = 0, + /// gpio + Gpio = 1, + /// spi_device + SpiDevice = 2, + /// i2c0 + I2c0 = 3, + /// rv_timer + RvTimer = 4, + /// otp_ctrl + OtpCtrl = 5, + /// lc_ctrl + LcCtrl = 6, + /// spi_host0 + SpiHost0 = 7, + /// pwrmgr_aon + PwrmgrAon = 8, + /// rstmgr_aon + RstmgrAon = 9, + /// clkmgr_aon + ClkmgrAon = 10, + /// pinmux_aon + PinmuxAon = 11, + /// aon_timer_aon + AonTimerAon = 12, + /// sensor_ctrl + SensorCtrl = 13, + /// soc_proxy + SocProxy = 14, + /// sram_ctrl_ret_aon + SramCtrlRetAon = 15, + /// rv_dm + RvDm = 16, + /// rv_plic + RvPlic = 17, + /// aes + Aes = 18, + /// hmac + Hmac = 19, + /// kmac + Kmac = 20, + /// otbn + Otbn = 21, + /// keymgr_dpe + KeymgrDpe = 22, + /// csrng + Csrng = 23, + /// edn0 + Edn0 = 24, + /// edn1 + Edn1 = 25, + /// sram_ctrl_main + SramCtrlMain = 26, + /// sram_ctrl_mbox + SramCtrlMbox = 27, + /// rom_ctrl0 + RomCtrl0 = 28, + /// rom_ctrl1 + RomCtrl1 = 29, + /// dma + Dma = 30, + /// mbx0 + Mbx0 = 31, + /// mbx1 + Mbx1 = 32, + /// mbx2 + Mbx2 = 33, + /// mbx3 + Mbx3 = 34, + /// mbx4 + Mbx4 = 35, + /// mbx5 + Mbx5 = 36, + /// mbx6 + Mbx6 = 37, + /// mbx_jtag + MbxJtag = 38, + /// mbx_pcie0 + MbxPcie0 = 39, + /// mbx_pcie1 + MbxPcie1 = 40, + /// rv_core_ibex + RvCoreIbex = 41, +} + +/// Alert Handler Alert Source. +/// +/// Enumeration of all Alert Handler Alert Sources. The alert sources belonging to +/// the same peripheral are guaranteed to be consecutive. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum AlertId { + /// uart0_fatal_fault + Uart0FatalFault = 0, + /// gpio_fatal_fault + GpioFatalFault = 1, + /// spi_device_fatal_fault + SpiDeviceFatalFault = 2, + /// i2c0_fatal_fault + I2c0FatalFault = 3, + /// rv_timer_fatal_fault + RvTimerFatalFault = 4, + /// otp_ctrl_fatal_macro_error + OtpCtrlFatalMacroError = 5, + /// otp_ctrl_fatal_check_error + OtpCtrlFatalCheckError = 6, + /// otp_ctrl_fatal_bus_integ_error + OtpCtrlFatalBusIntegError = 7, + /// otp_ctrl_fatal_prim_otp_alert + OtpCtrlFatalPrimOtpAlert = 8, + /// otp_ctrl_recov_prim_otp_alert + OtpCtrlRecovPrimOtpAlert = 9, + /// lc_ctrl_fatal_prog_error + LcCtrlFatalProgError = 10, + /// lc_ctrl_fatal_state_error + LcCtrlFatalStateError = 11, + /// lc_ctrl_fatal_bus_integ_error + LcCtrlFatalBusIntegError = 12, + /// spi_host0_fatal_fault + SpiHost0FatalFault = 13, + /// pwrmgr_aon_fatal_fault + PwrmgrAonFatalFault = 14, + /// rstmgr_aon_fatal_fault + RstmgrAonFatalFault = 15, + /// rstmgr_aon_fatal_cnsty_fault + RstmgrAonFatalCnstyFault = 16, + /// clkmgr_aon_recov_fault + ClkmgrAonRecovFault = 17, + /// clkmgr_aon_fatal_fault + ClkmgrAonFatalFault = 18, + /// pinmux_aon_fatal_fault + PinmuxAonFatalFault = 19, + /// aon_timer_aon_fatal_fault + AonTimerAonFatalFault = 20, + /// sensor_ctrl_recov_alert + SensorCtrlRecovAlert = 21, + /// sensor_ctrl_fatal_alert + SensorCtrlFatalAlert = 22, + /// soc_proxy_fatal_alert_intg + SocProxyFatalAlertIntg = 23, + /// soc_proxy_fatal_alert_external_0 + SocProxyFatalAlertExternal0 = 24, + /// soc_proxy_fatal_alert_external_1 + SocProxyFatalAlertExternal1 = 25, + /// soc_proxy_fatal_alert_external_2 + SocProxyFatalAlertExternal2 = 26, + /// soc_proxy_fatal_alert_external_3 + SocProxyFatalAlertExternal3 = 27, + /// soc_proxy_fatal_alert_external_4 + SocProxyFatalAlertExternal4 = 28, + /// soc_proxy_fatal_alert_external_5 + SocProxyFatalAlertExternal5 = 29, + /// soc_proxy_fatal_alert_external_6 + SocProxyFatalAlertExternal6 = 30, + /// soc_proxy_fatal_alert_external_7 + SocProxyFatalAlertExternal7 = 31, + /// soc_proxy_fatal_alert_external_8 + SocProxyFatalAlertExternal8 = 32, + /// soc_proxy_fatal_alert_external_9 + SocProxyFatalAlertExternal9 = 33, + /// soc_proxy_fatal_alert_external_10 + SocProxyFatalAlertExternal10 = 34, + /// soc_proxy_fatal_alert_external_11 + SocProxyFatalAlertExternal11 = 35, + /// soc_proxy_fatal_alert_external_12 + SocProxyFatalAlertExternal12 = 36, + /// soc_proxy_fatal_alert_external_13 + SocProxyFatalAlertExternal13 = 37, + /// soc_proxy_fatal_alert_external_14 + SocProxyFatalAlertExternal14 = 38, + /// soc_proxy_fatal_alert_external_15 + SocProxyFatalAlertExternal15 = 39, + /// soc_proxy_fatal_alert_external_16 + SocProxyFatalAlertExternal16 = 40, + /// soc_proxy_fatal_alert_external_17 + SocProxyFatalAlertExternal17 = 41, + /// soc_proxy_fatal_alert_external_18 + SocProxyFatalAlertExternal18 = 42, + /// soc_proxy_fatal_alert_external_19 + SocProxyFatalAlertExternal19 = 43, + /// soc_proxy_fatal_alert_external_20 + SocProxyFatalAlertExternal20 = 44, + /// soc_proxy_fatal_alert_external_21 + SocProxyFatalAlertExternal21 = 45, + /// soc_proxy_fatal_alert_external_22 + SocProxyFatalAlertExternal22 = 46, + /// soc_proxy_fatal_alert_external_23 + SocProxyFatalAlertExternal23 = 47, + /// soc_proxy_recov_alert_external_0 + SocProxyRecovAlertExternal0 = 48, + /// soc_proxy_recov_alert_external_1 + SocProxyRecovAlertExternal1 = 49, + /// soc_proxy_recov_alert_external_2 + SocProxyRecovAlertExternal2 = 50, + /// soc_proxy_recov_alert_external_3 + SocProxyRecovAlertExternal3 = 51, + /// sram_ctrl_ret_aon_fatal_error + SramCtrlRetAonFatalError = 52, + /// rv_dm_fatal_fault + RvDmFatalFault = 53, + /// rv_plic_fatal_fault + RvPlicFatalFault = 54, + /// aes_recov_ctrl_update_err + AesRecovCtrlUpdateErr = 55, + /// aes_fatal_fault + AesFatalFault = 56, + /// hmac_fatal_fault + HmacFatalFault = 57, + /// kmac_recov_operation_err + KmacRecovOperationErr = 58, + /// kmac_fatal_fault_err + KmacFatalFaultErr = 59, + /// otbn_fatal + OtbnFatal = 60, + /// otbn_recov + OtbnRecov = 61, + /// keymgr_dpe_recov_operation_err + KeymgrDpeRecovOperationErr = 62, + /// keymgr_dpe_fatal_fault_err + KeymgrDpeFatalFaultErr = 63, + /// csrng_recov_alert + CsrngRecovAlert = 64, + /// csrng_fatal_alert + CsrngFatalAlert = 65, + /// edn0_recov_alert + Edn0RecovAlert = 66, + /// edn0_fatal_alert + Edn0FatalAlert = 67, + /// edn1_recov_alert + Edn1RecovAlert = 68, + /// edn1_fatal_alert + Edn1FatalAlert = 69, + /// sram_ctrl_main_fatal_error + SramCtrlMainFatalError = 70, + /// sram_ctrl_mbox_fatal_error + SramCtrlMboxFatalError = 71, + /// rom_ctrl0_fatal + RomCtrl0Fatal = 72, + /// rom_ctrl1_fatal + RomCtrl1Fatal = 73, + /// dma_fatal_fault + DmaFatalFault = 74, + /// mbx0_fatal_fault + Mbx0FatalFault = 75, + /// mbx0_recov_fault + Mbx0RecovFault = 76, + /// mbx1_fatal_fault + Mbx1FatalFault = 77, + /// mbx1_recov_fault + Mbx1RecovFault = 78, + /// mbx2_fatal_fault + Mbx2FatalFault = 79, + /// mbx2_recov_fault + Mbx2RecovFault = 80, + /// mbx3_fatal_fault + Mbx3FatalFault = 81, + /// mbx3_recov_fault + Mbx3RecovFault = 82, + /// mbx4_fatal_fault + Mbx4FatalFault = 83, + /// mbx4_recov_fault + Mbx4RecovFault = 84, + /// mbx5_fatal_fault + Mbx5FatalFault = 85, + /// mbx5_recov_fault + Mbx5RecovFault = 86, + /// mbx6_fatal_fault + Mbx6FatalFault = 87, + /// mbx6_recov_fault + Mbx6RecovFault = 88, + /// mbx_jtag_fatal_fault + MbxJtagFatalFault = 89, + /// mbx_jtag_recov_fault + MbxJtagRecovFault = 90, + /// mbx_pcie0_fatal_fault + MbxPcie0FatalFault = 91, + /// mbx_pcie0_recov_fault + MbxPcie0RecovFault = 92, + /// mbx_pcie1_fatal_fault + MbxPcie1FatalFault = 93, + /// mbx_pcie1_recov_fault + MbxPcie1RecovFault = 94, + /// rv_core_ibex_fatal_sw_err + RvCoreIbexFatalSwErr = 95, + /// rv_core_ibex_recov_sw_err + RvCoreIbexRecovSwErr = 96, + /// rv_core_ibex_fatal_hw_err + RvCoreIbexFatalHwErr = 97, + /// rv_core_ibex_recov_hw_err + RvCoreIbexRecovHwErr = 98, +} + +impl TryFrom for AlertId { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::Uart0FatalFault), + 1 => Ok(Self::GpioFatalFault), + 2 => Ok(Self::SpiDeviceFatalFault), + 3 => Ok(Self::I2c0FatalFault), + 4 => Ok(Self::RvTimerFatalFault), + 5 => Ok(Self::OtpCtrlFatalMacroError), + 6 => Ok(Self::OtpCtrlFatalCheckError), + 7 => Ok(Self::OtpCtrlFatalBusIntegError), + 8 => Ok(Self::OtpCtrlFatalPrimOtpAlert), + 9 => Ok(Self::OtpCtrlRecovPrimOtpAlert), + 10 => Ok(Self::LcCtrlFatalProgError), + 11 => Ok(Self::LcCtrlFatalStateError), + 12 => Ok(Self::LcCtrlFatalBusIntegError), + 13 => Ok(Self::SpiHost0FatalFault), + 14 => Ok(Self::PwrmgrAonFatalFault), + 15 => Ok(Self::RstmgrAonFatalFault), + 16 => Ok(Self::RstmgrAonFatalCnstyFault), + 17 => Ok(Self::ClkmgrAonRecovFault), + 18 => Ok(Self::ClkmgrAonFatalFault), + 19 => Ok(Self::PinmuxAonFatalFault), + 20 => Ok(Self::AonTimerAonFatalFault), + 21 => Ok(Self::SensorCtrlRecovAlert), + 22 => Ok(Self::SensorCtrlFatalAlert), + 23 => Ok(Self::SocProxyFatalAlertIntg), + 24 => Ok(Self::SocProxyFatalAlertExternal0), + 25 => Ok(Self::SocProxyFatalAlertExternal1), + 26 => Ok(Self::SocProxyFatalAlertExternal2), + 27 => Ok(Self::SocProxyFatalAlertExternal3), + 28 => Ok(Self::SocProxyFatalAlertExternal4), + 29 => Ok(Self::SocProxyFatalAlertExternal5), + 30 => Ok(Self::SocProxyFatalAlertExternal6), + 31 => Ok(Self::SocProxyFatalAlertExternal7), + 32 => Ok(Self::SocProxyFatalAlertExternal8), + 33 => Ok(Self::SocProxyFatalAlertExternal9), + 34 => Ok(Self::SocProxyFatalAlertExternal10), + 35 => Ok(Self::SocProxyFatalAlertExternal11), + 36 => Ok(Self::SocProxyFatalAlertExternal12), + 37 => Ok(Self::SocProxyFatalAlertExternal13), + 38 => Ok(Self::SocProxyFatalAlertExternal14), + 39 => Ok(Self::SocProxyFatalAlertExternal15), + 40 => Ok(Self::SocProxyFatalAlertExternal16), + 41 => Ok(Self::SocProxyFatalAlertExternal17), + 42 => Ok(Self::SocProxyFatalAlertExternal18), + 43 => Ok(Self::SocProxyFatalAlertExternal19), + 44 => Ok(Self::SocProxyFatalAlertExternal20), + 45 => Ok(Self::SocProxyFatalAlertExternal21), + 46 => Ok(Self::SocProxyFatalAlertExternal22), + 47 => Ok(Self::SocProxyFatalAlertExternal23), + 48 => Ok(Self::SocProxyRecovAlertExternal0), + 49 => Ok(Self::SocProxyRecovAlertExternal1), + 50 => Ok(Self::SocProxyRecovAlertExternal2), + 51 => Ok(Self::SocProxyRecovAlertExternal3), + 52 => Ok(Self::SramCtrlRetAonFatalError), + 53 => Ok(Self::RvDmFatalFault), + 54 => Ok(Self::RvPlicFatalFault), + 55 => Ok(Self::AesRecovCtrlUpdateErr), + 56 => Ok(Self::AesFatalFault), + 57 => Ok(Self::HmacFatalFault), + 58 => Ok(Self::KmacRecovOperationErr), + 59 => Ok(Self::KmacFatalFaultErr), + 60 => Ok(Self::OtbnFatal), + 61 => Ok(Self::OtbnRecov), + 62 => Ok(Self::KeymgrDpeRecovOperationErr), + 63 => Ok(Self::KeymgrDpeFatalFaultErr), + 64 => Ok(Self::CsrngRecovAlert), + 65 => Ok(Self::CsrngFatalAlert), + 66 => Ok(Self::Edn0RecovAlert), + 67 => Ok(Self::Edn0FatalAlert), + 68 => Ok(Self::Edn1RecovAlert), + 69 => Ok(Self::Edn1FatalAlert), + 70 => Ok(Self::SramCtrlMainFatalError), + 71 => Ok(Self::SramCtrlMboxFatalError), + 72 => Ok(Self::RomCtrl0Fatal), + 73 => Ok(Self::RomCtrl1Fatal), + 74 => Ok(Self::DmaFatalFault), + 75 => Ok(Self::Mbx0FatalFault), + 76 => Ok(Self::Mbx0RecovFault), + 77 => Ok(Self::Mbx1FatalFault), + 78 => Ok(Self::Mbx1RecovFault), + 79 => Ok(Self::Mbx2FatalFault), + 80 => Ok(Self::Mbx2RecovFault), + 81 => Ok(Self::Mbx3FatalFault), + 82 => Ok(Self::Mbx3RecovFault), + 83 => Ok(Self::Mbx4FatalFault), + 84 => Ok(Self::Mbx4RecovFault), + 85 => Ok(Self::Mbx5FatalFault), + 86 => Ok(Self::Mbx5RecovFault), + 87 => Ok(Self::Mbx6FatalFault), + 88 => Ok(Self::Mbx6RecovFault), + 89 => Ok(Self::MbxJtagFatalFault), + 90 => Ok(Self::MbxJtagRecovFault), + 91 => Ok(Self::MbxPcie0FatalFault), + 92 => Ok(Self::MbxPcie0RecovFault), + 93 => Ok(Self::MbxPcie1FatalFault), + 94 => Ok(Self::MbxPcie1RecovFault), + 95 => Ok(Self::RvCoreIbexFatalSwErr), + 96 => Ok(Self::RvCoreIbexRecovSwErr), + 97 => Ok(Self::RvCoreIbexFatalHwErr), + 98 => Ok(Self::RvCoreIbexRecovHwErr), + _ => Err(val), + } + } +} + +/// PLIC Interrupt Source to Peripheral Map +/// +/// This array is a mapping from `PlicIrqId` to +/// `PlicPeripheral`. +pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 160] = [ + // None -> PlicPeripheral::Unknown + PlicPeripheral::Unknown, + // Uart0TxWatermark -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0RxWatermark -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0TxDone -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0RxOverflow -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0RxFrameErr -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0RxBreakErr -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0RxTimeout -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0RxParityErr -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0TxEmpty -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // GpioGpio0 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio1 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio2 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio3 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio4 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio5 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio6 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio7 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio8 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio9 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio10 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio11 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio12 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio13 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio14 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio15 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio16 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio17 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio18 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio19 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio20 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio21 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio22 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio23 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio24 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio25 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio26 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio27 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio28 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio29 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio30 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio31 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // SpiDeviceUploadCmdfifoNotEmpty -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceUploadPayloadNotEmpty -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceUploadPayloadOverflow -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceReadbufWatermark -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceReadbufFlip -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceTpmHeaderNotEmpty -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceTpmRdfifoCmdEnd -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceTpmRdfifoDrop -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // I2c0FmtThreshold -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0RxThreshold -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0AcqThreshold -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0RxOverflow -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0ControllerHalt -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0SclInterference -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0SdaInterference -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0StretchTimeout -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0SdaUnstable -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0CmdComplete -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0TxStretch -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0TxThreshold -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0AcqStretch -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0UnexpStop -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0HostTimeout -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // RvTimerTimerExpiredHart0Timer0 -> PlicPeripheral::RvTimer + PlicPeripheral::RvTimer, + // OtpCtrlOtpOperationDone -> PlicPeripheral::OtpCtrl + PlicPeripheral::OtpCtrl, + // OtpCtrlOtpError -> PlicPeripheral::OtpCtrl + PlicPeripheral::OtpCtrl, + // AlertHandlerClassa -> PlicPeripheral::AlertHandler + PlicPeripheral::AlertHandler, + // AlertHandlerClassb -> PlicPeripheral::AlertHandler + PlicPeripheral::AlertHandler, + // AlertHandlerClassc -> PlicPeripheral::AlertHandler + PlicPeripheral::AlertHandler, + // AlertHandlerClassd -> PlicPeripheral::AlertHandler + PlicPeripheral::AlertHandler, + // SpiHost0Error -> PlicPeripheral::SpiHost0 + PlicPeripheral::SpiHost0, + // SpiHost0SpiEvent -> PlicPeripheral::SpiHost0 + PlicPeripheral::SpiHost0, + // PwrmgrAonWakeup -> PlicPeripheral::PwrmgrAon + PlicPeripheral::PwrmgrAon, + // AonTimerAonWkupTimerExpired -> PlicPeripheral::AonTimerAon + PlicPeripheral::AonTimerAon, + // AonTimerAonWdogTimerBark -> PlicPeripheral::AonTimerAon + PlicPeripheral::AonTimerAon, + // SensorCtrlIoStatusChange -> PlicPeripheral::SensorCtrl + PlicPeripheral::SensorCtrl, + // SensorCtrlInitStatusChange -> PlicPeripheral::SensorCtrl + PlicPeripheral::SensorCtrl, + // SocProxyExternal0 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal1 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal2 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal3 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal4 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal5 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal6 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal7 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal8 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal9 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal10 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal11 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal12 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal13 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal14 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal15 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal16 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal17 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal18 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal19 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal20 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal21 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal22 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal23 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal24 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal25 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal26 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal27 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal28 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal29 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal30 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal31 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // HmacHmacDone -> PlicPeripheral::Hmac + PlicPeripheral::Hmac, + // HmacFifoEmpty -> PlicPeripheral::Hmac + PlicPeripheral::Hmac, + // HmacHmacErr -> PlicPeripheral::Hmac + PlicPeripheral::Hmac, + // KmacKmacDone -> PlicPeripheral::Kmac + PlicPeripheral::Kmac, + // KmacFifoEmpty -> PlicPeripheral::Kmac + PlicPeripheral::Kmac, + // KmacKmacErr -> PlicPeripheral::Kmac + PlicPeripheral::Kmac, + // OtbnDone -> PlicPeripheral::Otbn + PlicPeripheral::Otbn, + // KeymgrDpeOpDone -> PlicPeripheral::KeymgrDpe + PlicPeripheral::KeymgrDpe, + // CsrngCsCmdReqDone -> PlicPeripheral::Csrng + PlicPeripheral::Csrng, + // CsrngCsEntropyReq -> PlicPeripheral::Csrng + PlicPeripheral::Csrng, + // CsrngCsHwInstExc -> PlicPeripheral::Csrng + PlicPeripheral::Csrng, + // CsrngCsFatalErr -> PlicPeripheral::Csrng + PlicPeripheral::Csrng, + // Edn0EdnCmdReqDone -> PlicPeripheral::Edn0 + PlicPeripheral::Edn0, + // Edn0EdnFatalErr -> PlicPeripheral::Edn0 + PlicPeripheral::Edn0, + // Edn1EdnCmdReqDone -> PlicPeripheral::Edn1 + PlicPeripheral::Edn1, + // Edn1EdnFatalErr -> PlicPeripheral::Edn1 + PlicPeripheral::Edn1, + // DmaDmaDone -> PlicPeripheral::Dma + PlicPeripheral::Dma, + // DmaDmaChunkDone -> PlicPeripheral::Dma + PlicPeripheral::Dma, + // DmaDmaError -> PlicPeripheral::Dma + PlicPeripheral::Dma, + // Mbx0MbxReady -> PlicPeripheral::Mbx0 + PlicPeripheral::Mbx0, + // Mbx0MbxAbort -> PlicPeripheral::Mbx0 + PlicPeripheral::Mbx0, + // Mbx0MbxError -> PlicPeripheral::Mbx0 + PlicPeripheral::Mbx0, + // Mbx1MbxReady -> PlicPeripheral::Mbx1 + PlicPeripheral::Mbx1, + // Mbx1MbxAbort -> PlicPeripheral::Mbx1 + PlicPeripheral::Mbx1, + // Mbx1MbxError -> PlicPeripheral::Mbx1 + PlicPeripheral::Mbx1, + // Mbx2MbxReady -> PlicPeripheral::Mbx2 + PlicPeripheral::Mbx2, + // Mbx2MbxAbort -> PlicPeripheral::Mbx2 + PlicPeripheral::Mbx2, + // Mbx2MbxError -> PlicPeripheral::Mbx2 + PlicPeripheral::Mbx2, + // Mbx3MbxReady -> PlicPeripheral::Mbx3 + PlicPeripheral::Mbx3, + // Mbx3MbxAbort -> PlicPeripheral::Mbx3 + PlicPeripheral::Mbx3, + // Mbx3MbxError -> PlicPeripheral::Mbx3 + PlicPeripheral::Mbx3, + // Mbx4MbxReady -> PlicPeripheral::Mbx4 + PlicPeripheral::Mbx4, + // Mbx4MbxAbort -> PlicPeripheral::Mbx4 + PlicPeripheral::Mbx4, + // Mbx4MbxError -> PlicPeripheral::Mbx4 + PlicPeripheral::Mbx4, + // Mbx5MbxReady -> PlicPeripheral::Mbx5 + PlicPeripheral::Mbx5, + // Mbx5MbxAbort -> PlicPeripheral::Mbx5 + PlicPeripheral::Mbx5, + // Mbx5MbxError -> PlicPeripheral::Mbx5 + PlicPeripheral::Mbx5, + // Mbx6MbxReady -> PlicPeripheral::Mbx6 + PlicPeripheral::Mbx6, + // Mbx6MbxAbort -> PlicPeripheral::Mbx6 + PlicPeripheral::Mbx6, + // Mbx6MbxError -> PlicPeripheral::Mbx6 + PlicPeripheral::Mbx6, + // MbxJtagMbxReady -> PlicPeripheral::MbxJtag + PlicPeripheral::MbxJtag, + // MbxJtagMbxAbort -> PlicPeripheral::MbxJtag + PlicPeripheral::MbxJtag, + // MbxJtagMbxError -> PlicPeripheral::MbxJtag + PlicPeripheral::MbxJtag, + // MbxPcie0MbxReady -> PlicPeripheral::MbxPcie0 + PlicPeripheral::MbxPcie0, + // MbxPcie0MbxAbort -> PlicPeripheral::MbxPcie0 + PlicPeripheral::MbxPcie0, + // MbxPcie0MbxError -> PlicPeripheral::MbxPcie0 + PlicPeripheral::MbxPcie0, + // MbxPcie1MbxReady -> PlicPeripheral::MbxPcie1 + PlicPeripheral::MbxPcie1, + // MbxPcie1MbxAbort -> PlicPeripheral::MbxPcie1 + PlicPeripheral::MbxPcie1, + // MbxPcie1MbxError -> PlicPeripheral::MbxPcie1 + PlicPeripheral::MbxPcie1, +]; + +/// Alert Handler Alert Source to Peripheral Map +/// +/// This array is a mapping from `AlertId` to +/// `AlertPeripheral`. +pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 99] = [ + // Uart0FatalFault -> AlertPeripheral::Uart0 + AlertPeripheral::Uart0, + // GpioFatalFault -> AlertPeripheral::Gpio + AlertPeripheral::Gpio, + // SpiDeviceFatalFault -> AlertPeripheral::SpiDevice + AlertPeripheral::SpiDevice, + // I2c0FatalFault -> AlertPeripheral::I2c0 + AlertPeripheral::I2c0, + // RvTimerFatalFault -> AlertPeripheral::RvTimer + AlertPeripheral::RvTimer, + // OtpCtrlFatalMacroError -> AlertPeripheral::OtpCtrl + AlertPeripheral::OtpCtrl, + // OtpCtrlFatalCheckError -> AlertPeripheral::OtpCtrl + AlertPeripheral::OtpCtrl, + // OtpCtrlFatalBusIntegError -> AlertPeripheral::OtpCtrl + AlertPeripheral::OtpCtrl, + // OtpCtrlFatalPrimOtpAlert -> AlertPeripheral::OtpCtrl + AlertPeripheral::OtpCtrl, + // OtpCtrlRecovPrimOtpAlert -> AlertPeripheral::OtpCtrl + AlertPeripheral::OtpCtrl, + // LcCtrlFatalProgError -> AlertPeripheral::LcCtrl + AlertPeripheral::LcCtrl, + // LcCtrlFatalStateError -> AlertPeripheral::LcCtrl + AlertPeripheral::LcCtrl, + // LcCtrlFatalBusIntegError -> AlertPeripheral::LcCtrl + AlertPeripheral::LcCtrl, + // SpiHost0FatalFault -> AlertPeripheral::SpiHost0 + AlertPeripheral::SpiHost0, + // PwrmgrAonFatalFault -> AlertPeripheral::PwrmgrAon + AlertPeripheral::PwrmgrAon, + // RstmgrAonFatalFault -> AlertPeripheral::RstmgrAon + AlertPeripheral::RstmgrAon, + // RstmgrAonFatalCnstyFault -> AlertPeripheral::RstmgrAon + AlertPeripheral::RstmgrAon, + // ClkmgrAonRecovFault -> AlertPeripheral::ClkmgrAon + AlertPeripheral::ClkmgrAon, + // ClkmgrAonFatalFault -> AlertPeripheral::ClkmgrAon + AlertPeripheral::ClkmgrAon, + // PinmuxAonFatalFault -> AlertPeripheral::PinmuxAon + AlertPeripheral::PinmuxAon, + // AonTimerAonFatalFault -> AlertPeripheral::AonTimerAon + AlertPeripheral::AonTimerAon, + // SensorCtrlRecovAlert -> AlertPeripheral::SensorCtrl + AlertPeripheral::SensorCtrl, + // SensorCtrlFatalAlert -> AlertPeripheral::SensorCtrl + AlertPeripheral::SensorCtrl, + // SocProxyFatalAlertIntg -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal0 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal1 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal2 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal3 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal4 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal5 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal6 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal7 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal8 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal9 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal10 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal11 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal12 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal13 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal14 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal15 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal16 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal17 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal18 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal19 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal20 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal21 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal22 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal23 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyRecovAlertExternal0 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyRecovAlertExternal1 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyRecovAlertExternal2 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyRecovAlertExternal3 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SramCtrlRetAonFatalError -> AlertPeripheral::SramCtrlRetAon + AlertPeripheral::SramCtrlRetAon, + // RvDmFatalFault -> AlertPeripheral::RvDm + AlertPeripheral::RvDm, + // RvPlicFatalFault -> AlertPeripheral::RvPlic + AlertPeripheral::RvPlic, + // AesRecovCtrlUpdateErr -> AlertPeripheral::Aes + AlertPeripheral::Aes, + // AesFatalFault -> AlertPeripheral::Aes + AlertPeripheral::Aes, + // HmacFatalFault -> AlertPeripheral::Hmac + AlertPeripheral::Hmac, + // KmacRecovOperationErr -> AlertPeripheral::Kmac + AlertPeripheral::Kmac, + // KmacFatalFaultErr -> AlertPeripheral::Kmac + AlertPeripheral::Kmac, + // OtbnFatal -> AlertPeripheral::Otbn + AlertPeripheral::Otbn, + // OtbnRecov -> AlertPeripheral::Otbn + AlertPeripheral::Otbn, + // KeymgrDpeRecovOperationErr -> AlertPeripheral::KeymgrDpe + AlertPeripheral::KeymgrDpe, + // KeymgrDpeFatalFaultErr -> AlertPeripheral::KeymgrDpe + AlertPeripheral::KeymgrDpe, + // CsrngRecovAlert -> AlertPeripheral::Csrng + AlertPeripheral::Csrng, + // CsrngFatalAlert -> AlertPeripheral::Csrng + AlertPeripheral::Csrng, + // Edn0RecovAlert -> AlertPeripheral::Edn0 + AlertPeripheral::Edn0, + // Edn0FatalAlert -> AlertPeripheral::Edn0 + AlertPeripheral::Edn0, + // Edn1RecovAlert -> AlertPeripheral::Edn1 + AlertPeripheral::Edn1, + // Edn1FatalAlert -> AlertPeripheral::Edn1 + AlertPeripheral::Edn1, + // SramCtrlMainFatalError -> AlertPeripheral::SramCtrlMain + AlertPeripheral::SramCtrlMain, + // SramCtrlMboxFatalError -> AlertPeripheral::SramCtrlMbox + AlertPeripheral::SramCtrlMbox, + // RomCtrl0Fatal -> AlertPeripheral::RomCtrl0 + AlertPeripheral::RomCtrl0, + // RomCtrl1Fatal -> AlertPeripheral::RomCtrl1 + AlertPeripheral::RomCtrl1, + // DmaFatalFault -> AlertPeripheral::Dma + AlertPeripheral::Dma, + // Mbx0FatalFault -> AlertPeripheral::Mbx0 + AlertPeripheral::Mbx0, + // Mbx0RecovFault -> AlertPeripheral::Mbx0 + AlertPeripheral::Mbx0, + // Mbx1FatalFault -> AlertPeripheral::Mbx1 + AlertPeripheral::Mbx1, + // Mbx1RecovFault -> AlertPeripheral::Mbx1 + AlertPeripheral::Mbx1, + // Mbx2FatalFault -> AlertPeripheral::Mbx2 + AlertPeripheral::Mbx2, + // Mbx2RecovFault -> AlertPeripheral::Mbx2 + AlertPeripheral::Mbx2, + // Mbx3FatalFault -> AlertPeripheral::Mbx3 + AlertPeripheral::Mbx3, + // Mbx3RecovFault -> AlertPeripheral::Mbx3 + AlertPeripheral::Mbx3, + // Mbx4FatalFault -> AlertPeripheral::Mbx4 + AlertPeripheral::Mbx4, + // Mbx4RecovFault -> AlertPeripheral::Mbx4 + AlertPeripheral::Mbx4, + // Mbx5FatalFault -> AlertPeripheral::Mbx5 + AlertPeripheral::Mbx5, + // Mbx5RecovFault -> AlertPeripheral::Mbx5 + AlertPeripheral::Mbx5, + // Mbx6FatalFault -> AlertPeripheral::Mbx6 + AlertPeripheral::Mbx6, + // Mbx6RecovFault -> AlertPeripheral::Mbx6 + AlertPeripheral::Mbx6, + // MbxJtagFatalFault -> AlertPeripheral::MbxJtag + AlertPeripheral::MbxJtag, + // MbxJtagRecovFault -> AlertPeripheral::MbxJtag + AlertPeripheral::MbxJtag, + // MbxPcie0FatalFault -> AlertPeripheral::MbxPcie0 + AlertPeripheral::MbxPcie0, + // MbxPcie0RecovFault -> AlertPeripheral::MbxPcie0 + AlertPeripheral::MbxPcie0, + // MbxPcie1FatalFault -> AlertPeripheral::MbxPcie1 + AlertPeripheral::MbxPcie1, + // MbxPcie1RecovFault -> AlertPeripheral::MbxPcie1 + AlertPeripheral::MbxPcie1, + // RvCoreIbexFatalSwErr -> AlertPeripheral::RvCoreIbex + AlertPeripheral::RvCoreIbex, + // RvCoreIbexRecovSwErr -> AlertPeripheral::RvCoreIbex + AlertPeripheral::RvCoreIbex, + // RvCoreIbexFatalHwErr -> AlertPeripheral::RvCoreIbex + AlertPeripheral::RvCoreIbex, + // RvCoreIbexRecovHwErr -> AlertPeripheral::RvCoreIbex + AlertPeripheral::RvCoreIbex, +]; + +// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1} +// 0 and 1 are tied to value 0 and 1 +pub const NUM_MIO_PADS: usize = 12; +pub const NUM_DIO_PADS: usize = 73; + +pub const PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET: usize = 2; +pub const PINMUX_PERIPH_OUTSEL_IDX_OFFSET: usize = 3; + +/// Pinmux Peripheral Input. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PinmuxPeripheralIn { + /// Peripheral Input 0 + SocProxySocGpi12 = 0, + /// Peripheral Input 1 + SocProxySocGpi13 = 1, + /// Peripheral Input 2 + SocProxySocGpi14 = 2, + /// Peripheral Input 3 + SocProxySocGpi15 = 3, +} + +impl TryFrom for PinmuxPeripheralIn { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::SocProxySocGpi12), + 1 => Ok(Self::SocProxySocGpi13), + 2 => Ok(Self::SocProxySocGpi14), + 3 => Ok(Self::SocProxySocGpi15), + _ => Err(val), + } + } +} + +/// Pinmux MIO Input Selector. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PinmuxInsel { + /// Tie constantly to zero + ConstantZero = 0, + /// Tie constantly to one + ConstantOne = 1, + /// MIO Pad 0 + Mio0 = 2, + /// MIO Pad 1 + Mio1 = 3, + /// MIO Pad 2 + Mio2 = 4, + /// MIO Pad 3 + Mio3 = 5, + /// MIO Pad 4 + Mio4 = 6, + /// MIO Pad 5 + Mio5 = 7, + /// MIO Pad 6 + Mio6 = 8, + /// MIO Pad 7 + Mio7 = 9, + /// MIO Pad 8 + Mio8 = 10, + /// MIO Pad 9 + Mio9 = 11, + /// MIO Pad 10 + Mio10 = 12, + /// MIO Pad 11 + Mio11 = 13, +} + +impl TryFrom for PinmuxInsel { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::ConstantZero), + 1 => Ok(Self::ConstantOne), + 2 => Ok(Self::Mio0), + 3 => Ok(Self::Mio1), + 4 => Ok(Self::Mio2), + 5 => Ok(Self::Mio3), + 6 => Ok(Self::Mio4), + 7 => Ok(Self::Mio5), + 8 => Ok(Self::Mio6), + 9 => Ok(Self::Mio7), + 10 => Ok(Self::Mio8), + 11 => Ok(Self::Mio9), + 12 => Ok(Self::Mio10), + 13 => Ok(Self::Mio11), + _ => Err(val), + } + } +} + +/// Pinmux MIO Output. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PinmuxMioOut { + /// MIO Pad 0 + Mio0 = 0, + /// MIO Pad 1 + Mio1 = 1, + /// MIO Pad 2 + Mio2 = 2, + /// MIO Pad 3 + Mio3 = 3, + /// MIO Pad 4 + Mio4 = 4, + /// MIO Pad 5 + Mio5 = 5, + /// MIO Pad 6 + Mio6 = 6, + /// MIO Pad 7 + Mio7 = 7, + /// MIO Pad 8 + Mio8 = 8, + /// MIO Pad 9 + Mio9 = 9, + /// MIO Pad 10 + Mio10 = 10, + /// MIO Pad 11 + Mio11 = 11, +} + +impl TryFrom for PinmuxMioOut { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::Mio0), + 1 => Ok(Self::Mio1), + 2 => Ok(Self::Mio2), + 3 => Ok(Self::Mio3), + 4 => Ok(Self::Mio4), + 5 => Ok(Self::Mio5), + 6 => Ok(Self::Mio6), + 7 => Ok(Self::Mio7), + 8 => Ok(Self::Mio8), + 9 => Ok(Self::Mio9), + 10 => Ok(Self::Mio10), + 11 => Ok(Self::Mio11), + _ => Err(val), + } + } +} + +/// Pinmux Peripheral Output Selector. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PinmuxOutsel { + /// Tie constantly to zero + ConstantZero = 0, + /// Tie constantly to one + ConstantOne = 1, + /// Tie constantly to high-Z + ConstantHighZ = 2, + /// Peripheral Output 0 + SocProxySocGpo12 = 3, + /// Peripheral Output 1 + SocProxySocGpo13 = 4, + /// Peripheral Output 2 + SocProxySocGpo14 = 5, + /// Peripheral Output 3 + SocProxySocGpo15 = 6, + /// Peripheral Output 4 + OtpCtrlTest0 = 7, +} + +impl TryFrom for PinmuxOutsel { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::ConstantZero), + 1 => Ok(Self::ConstantOne), + 2 => Ok(Self::ConstantHighZ), + 3 => Ok(Self::SocProxySocGpo12), + 4 => Ok(Self::SocProxySocGpo13), + 5 => Ok(Self::SocProxySocGpo14), + 6 => Ok(Self::SocProxySocGpo15), + 7 => Ok(Self::OtpCtrlTest0), + _ => Err(val), + } + } +} + +/// Dedicated Pad Selects +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum DirectPads { + SpiHost0Sd0 = 0, + SpiHost0Sd1 = 1, + SpiHost0Sd2 = 2, + SpiHost0Sd3 = 3, + SpiDeviceSd0 = 4, + SpiDeviceSd1 = 5, + SpiDeviceSd2 = 6, + SpiDeviceSd3 = 7, + I2c0Scl = 8, + I2c0Sda = 9, + GpioGpio0 = 10, + GpioGpio1 = 11, + GpioGpio2 = 12, + GpioGpio3 = 13, + GpioGpio4 = 14, + GpioGpio5 = 15, + GpioGpio6 = 16, + GpioGpio7 = 17, + GpioGpio8 = 18, + GpioGpio9 = 19, + GpioGpio10 = 20, + GpioGpio11 = 21, + GpioGpio12 = 22, + GpioGpio13 = 23, + GpioGpio14 = 24, + GpioGpio15 = 25, + GpioGpio16 = 26, + GpioGpio17 = 27, + GpioGpio18 = 28, + GpioGpio19 = 29, + GpioGpio20 = 30, + GpioGpio21 = 31, + GpioGpio22 = 32, + GpioGpio23 = 33, + GpioGpio24 = 34, + GpioGpio25 = 35, + GpioGpio26 = 36, + GpioGpio27 = 37, + GpioGpio28 = 38, + GpioGpio29 = 39, + GpioGpio30 = 40, + GpioGpio31 = 41, + SpiDeviceSck = 42, + SpiDeviceCsb = 43, + SpiDeviceTpmCsb = 44, + Uart0Rx = 45, + SocProxySocGpi0 = 46, + SocProxySocGpi1 = 47, + SocProxySocGpi2 = 48, + SocProxySocGpi3 = 49, + SocProxySocGpi4 = 50, + SocProxySocGpi5 = 51, + SocProxySocGpi6 = 52, + SocProxySocGpi7 = 53, + SocProxySocGpi8 = 54, + SocProxySocGpi9 = 55, + SocProxySocGpi10 = 56, + SocProxySocGpi11 = 57, + SpiHost0Sck = 58, + SpiHost0Csb = 59, + Uart0Tx = 60, + SocProxySocGpo0 = 61, + SocProxySocGpo1 = 62, + SocProxySocGpo2 = 63, + SocProxySocGpo3 = 64, + SocProxySocGpo4 = 65, + SocProxySocGpo5 = 66, + SocProxySocGpo6 = 67, + SocProxySocGpo7 = 68, + SocProxySocGpo8 = 69, + SocProxySocGpo9 = 70, + SocProxySocGpo10 = 71, + SocProxySocGpo11 = 72, +} + +impl TryFrom for DirectPads { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::SpiHost0Sd0), + 1 => Ok(Self::SpiHost0Sd1), + 2 => Ok(Self::SpiHost0Sd2), + 3 => Ok(Self::SpiHost0Sd3), + 4 => Ok(Self::SpiDeviceSd0), + 5 => Ok(Self::SpiDeviceSd1), + 6 => Ok(Self::SpiDeviceSd2), + 7 => Ok(Self::SpiDeviceSd3), + 8 => Ok(Self::I2c0Scl), + 9 => Ok(Self::I2c0Sda), + 10 => Ok(Self::GpioGpio0), + 11 => Ok(Self::GpioGpio1), + 12 => Ok(Self::GpioGpio2), + 13 => Ok(Self::GpioGpio3), + 14 => Ok(Self::GpioGpio4), + 15 => Ok(Self::GpioGpio5), + 16 => Ok(Self::GpioGpio6), + 17 => Ok(Self::GpioGpio7), + 18 => Ok(Self::GpioGpio8), + 19 => Ok(Self::GpioGpio9), + 20 => Ok(Self::GpioGpio10), + 21 => Ok(Self::GpioGpio11), + 22 => Ok(Self::GpioGpio12), + 23 => Ok(Self::GpioGpio13), + 24 => Ok(Self::GpioGpio14), + 25 => Ok(Self::GpioGpio15), + 26 => Ok(Self::GpioGpio16), + 27 => Ok(Self::GpioGpio17), + 28 => Ok(Self::GpioGpio18), + 29 => Ok(Self::GpioGpio19), + 30 => Ok(Self::GpioGpio20), + 31 => Ok(Self::GpioGpio21), + 32 => Ok(Self::GpioGpio22), + 33 => Ok(Self::GpioGpio23), + 34 => Ok(Self::GpioGpio24), + 35 => Ok(Self::GpioGpio25), + 36 => Ok(Self::GpioGpio26), + 37 => Ok(Self::GpioGpio27), + 38 => Ok(Self::GpioGpio28), + 39 => Ok(Self::GpioGpio29), + 40 => Ok(Self::GpioGpio30), + 41 => Ok(Self::GpioGpio31), + 42 => Ok(Self::SpiDeviceSck), + 43 => Ok(Self::SpiDeviceCsb), + 44 => Ok(Self::SpiDeviceTpmCsb), + 45 => Ok(Self::Uart0Rx), + 46 => Ok(Self::SocProxySocGpi0), + 47 => Ok(Self::SocProxySocGpi1), + 48 => Ok(Self::SocProxySocGpi2), + 49 => Ok(Self::SocProxySocGpi3), + 50 => Ok(Self::SocProxySocGpi4), + 51 => Ok(Self::SocProxySocGpi5), + 52 => Ok(Self::SocProxySocGpi6), + 53 => Ok(Self::SocProxySocGpi7), + 54 => Ok(Self::SocProxySocGpi8), + 55 => Ok(Self::SocProxySocGpi9), + 56 => Ok(Self::SocProxySocGpi10), + 57 => Ok(Self::SocProxySocGpi11), + 58 => Ok(Self::SpiHost0Sck), + 59 => Ok(Self::SpiHost0Csb), + 60 => Ok(Self::Uart0Tx), + 61 => Ok(Self::SocProxySocGpo0), + 62 => Ok(Self::SocProxySocGpo1), + 63 => Ok(Self::SocProxySocGpo2), + 64 => Ok(Self::SocProxySocGpo3), + 65 => Ok(Self::SocProxySocGpo4), + 66 => Ok(Self::SocProxySocGpo5), + 67 => Ok(Self::SocProxySocGpo6), + 68 => Ok(Self::SocProxySocGpo7), + 69 => Ok(Self::SocProxySocGpo8), + 70 => Ok(Self::SocProxySocGpo9), + 71 => Ok(Self::SocProxySocGpo10), + 72 => Ok(Self::SocProxySocGpo11), + _ => Err(val), + } + } +} + +/// Muxed Pad Selects +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum MuxedPads { + Mio0 = 0, + Mio1 = 1, + Mio2 = 2, + Mio3 = 3, + Mio4 = 4, + Mio5 = 5, + Mio6 = 6, + Mio7 = 7, + Mio8 = 8, + Mio9 = 9, + Mio10 = 10, + Mio11 = 11, +} + +impl TryFrom for MuxedPads { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::Mio0), + 1 => Ok(Self::Mio1), + 2 => Ok(Self::Mio2), + 3 => Ok(Self::Mio3), + 4 => Ok(Self::Mio4), + 5 => Ok(Self::Mio5), + 6 => Ok(Self::Mio6), + 7 => Ok(Self::Mio7), + 8 => Ok(Self::Mio8), + 9 => Ok(Self::Mio9), + 10 => Ok(Self::Mio10), + 11 => Ok(Self::Mio11), + _ => Err(val), + } + } +} + +/// Power Manager Wakeup Signals +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PowerManagerWakeUps { + PinmuxAonPinWkupReq = 0, + PinmuxAonUsbWkupReq = 1, + AonTimerAonWkupReq = 2, + SensorCtrlWkupReq = 3, + SocProxyWkupInternalReq = 4, + SocProxyWkupExternalReq = 5, +} + +/// Reset Manager Software Controlled Resets +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum ResetManagerSwResets { + SpiDevice = 0, + SpiHost0 = 1, + I2c0 = 2, +} + +/// Power Manager Reset Request Signals +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PowerManagerResetRequests { + AonTimerAonAonTimerRstReq = 0, + SocProxyRstReqExternal = 1, +} + +/// Clock Manager Software-Controlled ("Gated") Clocks. +/// +/// The Software has full control over these clocks. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum GateableClocks { + /// Clock clk_io_div4_peri in group peri + IoDiv4Peri = 0, + /// Clock clk_io_div2_peri in group peri + IoDiv2Peri = 1, + /// Clock clk_usb_peri in group peri + UsbPeri = 2, +} + +/// Clock Manager Software-Hinted Clocks. +/// +/// The Software has partial control over these clocks. It can ask them to stop, +/// but the clock manager is in control of whether the clock actually is stopped. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum HintableClocks { + /// Clock clk_main_aes in group trans + MainAes = 0, + /// Clock clk_main_hmac in group trans + MainHmac = 1, + /// Clock clk_main_kmac in group trans + MainKmac = 2, + /// Clock clk_main_otbn in group trans + MainOtbn = 3, +} + +/// MMIO Region +/// +/// MMIO region excludes any memory that is separate from the module +/// configuration space, i.e. ROM, main SRAM, and mbx SRAM are excluded but +/// retention SRAM or spi_device are included. +pub const TOP_DARJEELING_MMIO_BASE_ADDR: usize = 0x21100000; +pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0xF501000; diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling.c b/hw/top_darjeeling/sw/autogen/top_darjeeling.c new file mode 100644 index 0000000000000..03e6933a26845 --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling.c @@ -0,0 +1,285 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include "hw/top_darjeeling/sw/autogen/top_darjeeling.h" + +/** + * PLIC Interrupt Source to Peripheral Map + * + * This array is a mapping from `top_darjeeling_plic_irq_id_t` to + * `top_darjeeling_plic_peripheral_t`. + */ +const top_darjeeling_plic_peripheral_t + top_darjeeling_plic_interrupt_for_peripheral[160] = { + [kTopDarjeelingPlicIrqIdNone] = kTopDarjeelingPlicPeripheralUnknown, + [kTopDarjeelingPlicIrqIdUart0TxWatermark] = kTopDarjeelingPlicPeripheralUart0, + [kTopDarjeelingPlicIrqIdUart0RxWatermark] = kTopDarjeelingPlicPeripheralUart0, + [kTopDarjeelingPlicIrqIdUart0TxDone] = kTopDarjeelingPlicPeripheralUart0, + [kTopDarjeelingPlicIrqIdUart0RxOverflow] = kTopDarjeelingPlicPeripheralUart0, + [kTopDarjeelingPlicIrqIdUart0RxFrameErr] = kTopDarjeelingPlicPeripheralUart0, + [kTopDarjeelingPlicIrqIdUart0RxBreakErr] = kTopDarjeelingPlicPeripheralUart0, + [kTopDarjeelingPlicIrqIdUart0RxTimeout] = kTopDarjeelingPlicPeripheralUart0, + [kTopDarjeelingPlicIrqIdUart0RxParityErr] = kTopDarjeelingPlicPeripheralUart0, + [kTopDarjeelingPlicIrqIdUart0TxEmpty] = kTopDarjeelingPlicPeripheralUart0, + [kTopDarjeelingPlicIrqIdGpioGpio0] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio1] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio2] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio3] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio4] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio5] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio6] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio7] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio8] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio9] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio10] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio11] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio12] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio13] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio14] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio15] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio16] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio17] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio18] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio19] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio20] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio21] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio22] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio23] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio24] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio25] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio26] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio27] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio28] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio29] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio30] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdGpioGpio31] = kTopDarjeelingPlicPeripheralGpio, + [kTopDarjeelingPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty] = kTopDarjeelingPlicPeripheralSpiDevice, + [kTopDarjeelingPlicIrqIdSpiDeviceUploadPayloadNotEmpty] = kTopDarjeelingPlicPeripheralSpiDevice, + [kTopDarjeelingPlicIrqIdSpiDeviceUploadPayloadOverflow] = kTopDarjeelingPlicPeripheralSpiDevice, + [kTopDarjeelingPlicIrqIdSpiDeviceReadbufWatermark] = kTopDarjeelingPlicPeripheralSpiDevice, + [kTopDarjeelingPlicIrqIdSpiDeviceReadbufFlip] = kTopDarjeelingPlicPeripheralSpiDevice, + [kTopDarjeelingPlicIrqIdSpiDeviceTpmHeaderNotEmpty] = kTopDarjeelingPlicPeripheralSpiDevice, + [kTopDarjeelingPlicIrqIdSpiDeviceTpmRdfifoCmdEnd] = kTopDarjeelingPlicPeripheralSpiDevice, + [kTopDarjeelingPlicIrqIdSpiDeviceTpmRdfifoDrop] = kTopDarjeelingPlicPeripheralSpiDevice, + [kTopDarjeelingPlicIrqIdI2c0FmtThreshold] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0RxThreshold] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0AcqThreshold] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0RxOverflow] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0ControllerHalt] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0SclInterference] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0SdaInterference] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0StretchTimeout] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0SdaUnstable] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0CmdComplete] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0TxStretch] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0TxThreshold] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0AcqStretch] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0UnexpStop] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdI2c0HostTimeout] = kTopDarjeelingPlicPeripheralI2c0, + [kTopDarjeelingPlicIrqIdRvTimerTimerExpiredHart0Timer0] = kTopDarjeelingPlicPeripheralRvTimer, + [kTopDarjeelingPlicIrqIdOtpCtrlOtpOperationDone] = kTopDarjeelingPlicPeripheralOtpCtrl, + [kTopDarjeelingPlicIrqIdOtpCtrlOtpError] = kTopDarjeelingPlicPeripheralOtpCtrl, + [kTopDarjeelingPlicIrqIdAlertHandlerClassa] = kTopDarjeelingPlicPeripheralAlertHandler, + [kTopDarjeelingPlicIrqIdAlertHandlerClassb] = kTopDarjeelingPlicPeripheralAlertHandler, + [kTopDarjeelingPlicIrqIdAlertHandlerClassc] = kTopDarjeelingPlicPeripheralAlertHandler, + [kTopDarjeelingPlicIrqIdAlertHandlerClassd] = kTopDarjeelingPlicPeripheralAlertHandler, + [kTopDarjeelingPlicIrqIdSpiHost0Error] = kTopDarjeelingPlicPeripheralSpiHost0, + [kTopDarjeelingPlicIrqIdSpiHost0SpiEvent] = kTopDarjeelingPlicPeripheralSpiHost0, + [kTopDarjeelingPlicIrqIdPwrmgrAonWakeup] = kTopDarjeelingPlicPeripheralPwrmgrAon, + [kTopDarjeelingPlicIrqIdAonTimerAonWkupTimerExpired] = kTopDarjeelingPlicPeripheralAonTimerAon, + [kTopDarjeelingPlicIrqIdAonTimerAonWdogTimerBark] = kTopDarjeelingPlicPeripheralAonTimerAon, + [kTopDarjeelingPlicIrqIdSensorCtrlIoStatusChange] = kTopDarjeelingPlicPeripheralSensorCtrl, + [kTopDarjeelingPlicIrqIdSensorCtrlInitStatusChange] = kTopDarjeelingPlicPeripheralSensorCtrl, + [kTopDarjeelingPlicIrqIdSocProxyExternal0] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal1] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal2] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal3] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal4] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal5] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal6] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal7] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal8] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal9] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal10] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal11] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal12] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal13] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal14] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal15] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal16] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal17] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal18] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal19] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal20] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal21] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal22] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal23] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal24] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal25] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal26] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal27] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal28] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal29] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal30] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdSocProxyExternal31] = kTopDarjeelingPlicPeripheralSocProxy, + [kTopDarjeelingPlicIrqIdHmacHmacDone] = kTopDarjeelingPlicPeripheralHmac, + [kTopDarjeelingPlicIrqIdHmacFifoEmpty] = kTopDarjeelingPlicPeripheralHmac, + [kTopDarjeelingPlicIrqIdHmacHmacErr] = kTopDarjeelingPlicPeripheralHmac, + [kTopDarjeelingPlicIrqIdKmacKmacDone] = kTopDarjeelingPlicPeripheralKmac, + [kTopDarjeelingPlicIrqIdKmacFifoEmpty] = kTopDarjeelingPlicPeripheralKmac, + [kTopDarjeelingPlicIrqIdKmacKmacErr] = kTopDarjeelingPlicPeripheralKmac, + [kTopDarjeelingPlicIrqIdOtbnDone] = kTopDarjeelingPlicPeripheralOtbn, + [kTopDarjeelingPlicIrqIdKeymgrDpeOpDone] = kTopDarjeelingPlicPeripheralKeymgrDpe, + [kTopDarjeelingPlicIrqIdCsrngCsCmdReqDone] = kTopDarjeelingPlicPeripheralCsrng, + [kTopDarjeelingPlicIrqIdCsrngCsEntropyReq] = kTopDarjeelingPlicPeripheralCsrng, + [kTopDarjeelingPlicIrqIdCsrngCsHwInstExc] = kTopDarjeelingPlicPeripheralCsrng, + [kTopDarjeelingPlicIrqIdCsrngCsFatalErr] = kTopDarjeelingPlicPeripheralCsrng, + [kTopDarjeelingPlicIrqIdEdn0EdnCmdReqDone] = kTopDarjeelingPlicPeripheralEdn0, + [kTopDarjeelingPlicIrqIdEdn0EdnFatalErr] = kTopDarjeelingPlicPeripheralEdn0, + [kTopDarjeelingPlicIrqIdEdn1EdnCmdReqDone] = kTopDarjeelingPlicPeripheralEdn1, + [kTopDarjeelingPlicIrqIdEdn1EdnFatalErr] = kTopDarjeelingPlicPeripheralEdn1, + [kTopDarjeelingPlicIrqIdDmaDmaDone] = kTopDarjeelingPlicPeripheralDma, + [kTopDarjeelingPlicIrqIdDmaDmaChunkDone] = kTopDarjeelingPlicPeripheralDma, + [kTopDarjeelingPlicIrqIdDmaDmaError] = kTopDarjeelingPlicPeripheralDma, + [kTopDarjeelingPlicIrqIdMbx0MbxReady] = kTopDarjeelingPlicPeripheralMbx0, + [kTopDarjeelingPlicIrqIdMbx0MbxAbort] = kTopDarjeelingPlicPeripheralMbx0, + [kTopDarjeelingPlicIrqIdMbx0MbxError] = kTopDarjeelingPlicPeripheralMbx0, + [kTopDarjeelingPlicIrqIdMbx1MbxReady] = kTopDarjeelingPlicPeripheralMbx1, + [kTopDarjeelingPlicIrqIdMbx1MbxAbort] = kTopDarjeelingPlicPeripheralMbx1, + [kTopDarjeelingPlicIrqIdMbx1MbxError] = kTopDarjeelingPlicPeripheralMbx1, + [kTopDarjeelingPlicIrqIdMbx2MbxReady] = kTopDarjeelingPlicPeripheralMbx2, + [kTopDarjeelingPlicIrqIdMbx2MbxAbort] = kTopDarjeelingPlicPeripheralMbx2, + [kTopDarjeelingPlicIrqIdMbx2MbxError] = kTopDarjeelingPlicPeripheralMbx2, + [kTopDarjeelingPlicIrqIdMbx3MbxReady] = kTopDarjeelingPlicPeripheralMbx3, + [kTopDarjeelingPlicIrqIdMbx3MbxAbort] = kTopDarjeelingPlicPeripheralMbx3, + [kTopDarjeelingPlicIrqIdMbx3MbxError] = kTopDarjeelingPlicPeripheralMbx3, + [kTopDarjeelingPlicIrqIdMbx4MbxReady] = kTopDarjeelingPlicPeripheralMbx4, + [kTopDarjeelingPlicIrqIdMbx4MbxAbort] = kTopDarjeelingPlicPeripheralMbx4, + [kTopDarjeelingPlicIrqIdMbx4MbxError] = kTopDarjeelingPlicPeripheralMbx4, + [kTopDarjeelingPlicIrqIdMbx5MbxReady] = kTopDarjeelingPlicPeripheralMbx5, + [kTopDarjeelingPlicIrqIdMbx5MbxAbort] = kTopDarjeelingPlicPeripheralMbx5, + [kTopDarjeelingPlicIrqIdMbx5MbxError] = kTopDarjeelingPlicPeripheralMbx5, + [kTopDarjeelingPlicIrqIdMbx6MbxReady] = kTopDarjeelingPlicPeripheralMbx6, + [kTopDarjeelingPlicIrqIdMbx6MbxAbort] = kTopDarjeelingPlicPeripheralMbx6, + [kTopDarjeelingPlicIrqIdMbx6MbxError] = kTopDarjeelingPlicPeripheralMbx6, + [kTopDarjeelingPlicIrqIdMbxJtagMbxReady] = kTopDarjeelingPlicPeripheralMbxJtag, + [kTopDarjeelingPlicIrqIdMbxJtagMbxAbort] = kTopDarjeelingPlicPeripheralMbxJtag, + [kTopDarjeelingPlicIrqIdMbxJtagMbxError] = kTopDarjeelingPlicPeripheralMbxJtag, + [kTopDarjeelingPlicIrqIdMbxPcie0MbxReady] = kTopDarjeelingPlicPeripheralMbxPcie0, + [kTopDarjeelingPlicIrqIdMbxPcie0MbxAbort] = kTopDarjeelingPlicPeripheralMbxPcie0, + [kTopDarjeelingPlicIrqIdMbxPcie0MbxError] = kTopDarjeelingPlicPeripheralMbxPcie0, + [kTopDarjeelingPlicIrqIdMbxPcie1MbxReady] = kTopDarjeelingPlicPeripheralMbxPcie1, + [kTopDarjeelingPlicIrqIdMbxPcie1MbxAbort] = kTopDarjeelingPlicPeripheralMbxPcie1, + [kTopDarjeelingPlicIrqIdMbxPcie1MbxError] = kTopDarjeelingPlicPeripheralMbxPcie1, +}; + + +/** + * Alert Handler Alert Source to Peripheral Map + * + * This array is a mapping from `top_darjeeling_alert_id_t` to + * `top_darjeeling_alert_peripheral_t`. + */ +const top_darjeeling_alert_peripheral_t + top_darjeeling_alert_for_peripheral[99] = { + [kTopDarjeelingAlertIdUart0FatalFault] = kTopDarjeelingAlertPeripheralUart0, + [kTopDarjeelingAlertIdGpioFatalFault] = kTopDarjeelingAlertPeripheralGpio, + [kTopDarjeelingAlertIdSpiDeviceFatalFault] = kTopDarjeelingAlertPeripheralSpiDevice, + [kTopDarjeelingAlertIdI2c0FatalFault] = kTopDarjeelingAlertPeripheralI2c0, + [kTopDarjeelingAlertIdRvTimerFatalFault] = kTopDarjeelingAlertPeripheralRvTimer, + [kTopDarjeelingAlertIdOtpCtrlFatalMacroError] = kTopDarjeelingAlertPeripheralOtpCtrl, + [kTopDarjeelingAlertIdOtpCtrlFatalCheckError] = kTopDarjeelingAlertPeripheralOtpCtrl, + [kTopDarjeelingAlertIdOtpCtrlFatalBusIntegError] = kTopDarjeelingAlertPeripheralOtpCtrl, + [kTopDarjeelingAlertIdOtpCtrlFatalPrimOtpAlert] = kTopDarjeelingAlertPeripheralOtpCtrl, + [kTopDarjeelingAlertIdOtpCtrlRecovPrimOtpAlert] = kTopDarjeelingAlertPeripheralOtpCtrl, + [kTopDarjeelingAlertIdLcCtrlFatalProgError] = kTopDarjeelingAlertPeripheralLcCtrl, + [kTopDarjeelingAlertIdLcCtrlFatalStateError] = kTopDarjeelingAlertPeripheralLcCtrl, + [kTopDarjeelingAlertIdLcCtrlFatalBusIntegError] = kTopDarjeelingAlertPeripheralLcCtrl, + [kTopDarjeelingAlertIdSpiHost0FatalFault] = kTopDarjeelingAlertPeripheralSpiHost0, + [kTopDarjeelingAlertIdPwrmgrAonFatalFault] = kTopDarjeelingAlertPeripheralPwrmgrAon, + [kTopDarjeelingAlertIdRstmgrAonFatalFault] = kTopDarjeelingAlertPeripheralRstmgrAon, + [kTopDarjeelingAlertIdRstmgrAonFatalCnstyFault] = kTopDarjeelingAlertPeripheralRstmgrAon, + [kTopDarjeelingAlertIdClkmgrAonRecovFault] = kTopDarjeelingAlertPeripheralClkmgrAon, + [kTopDarjeelingAlertIdClkmgrAonFatalFault] = kTopDarjeelingAlertPeripheralClkmgrAon, + [kTopDarjeelingAlertIdPinmuxAonFatalFault] = kTopDarjeelingAlertPeripheralPinmuxAon, + [kTopDarjeelingAlertIdAonTimerAonFatalFault] = kTopDarjeelingAlertPeripheralAonTimerAon, + [kTopDarjeelingAlertIdSensorCtrlRecovAlert] = kTopDarjeelingAlertPeripheralSensorCtrl, + [kTopDarjeelingAlertIdSensorCtrlFatalAlert] = kTopDarjeelingAlertPeripheralSensorCtrl, + [kTopDarjeelingAlertIdSocProxyFatalAlertIntg] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal0] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal1] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal2] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal3] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal4] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal5] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal6] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal7] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal8] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal9] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal10] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal11] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal12] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal13] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal14] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal15] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal16] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal17] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal18] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal19] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal20] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal21] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal22] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyFatalAlertExternal23] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyRecovAlertExternal0] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyRecovAlertExternal1] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyRecovAlertExternal2] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSocProxyRecovAlertExternal3] = kTopDarjeelingAlertPeripheralSocProxy, + [kTopDarjeelingAlertIdSramCtrlRetAonFatalError] = kTopDarjeelingAlertPeripheralSramCtrlRetAon, + [kTopDarjeelingAlertIdRvDmFatalFault] = kTopDarjeelingAlertPeripheralRvDm, + [kTopDarjeelingAlertIdRvPlicFatalFault] = kTopDarjeelingAlertPeripheralRvPlic, + [kTopDarjeelingAlertIdAesRecovCtrlUpdateErr] = kTopDarjeelingAlertPeripheralAes, + [kTopDarjeelingAlertIdAesFatalFault] = kTopDarjeelingAlertPeripheralAes, + [kTopDarjeelingAlertIdHmacFatalFault] = kTopDarjeelingAlertPeripheralHmac, + [kTopDarjeelingAlertIdKmacRecovOperationErr] = kTopDarjeelingAlertPeripheralKmac, + [kTopDarjeelingAlertIdKmacFatalFaultErr] = kTopDarjeelingAlertPeripheralKmac, + [kTopDarjeelingAlertIdOtbnFatal] = kTopDarjeelingAlertPeripheralOtbn, + [kTopDarjeelingAlertIdOtbnRecov] = kTopDarjeelingAlertPeripheralOtbn, + [kTopDarjeelingAlertIdKeymgrDpeRecovOperationErr] = kTopDarjeelingAlertPeripheralKeymgrDpe, + [kTopDarjeelingAlertIdKeymgrDpeFatalFaultErr] = kTopDarjeelingAlertPeripheralKeymgrDpe, + [kTopDarjeelingAlertIdCsrngRecovAlert] = kTopDarjeelingAlertPeripheralCsrng, + [kTopDarjeelingAlertIdCsrngFatalAlert] = kTopDarjeelingAlertPeripheralCsrng, + [kTopDarjeelingAlertIdEdn0RecovAlert] = kTopDarjeelingAlertPeripheralEdn0, + [kTopDarjeelingAlertIdEdn0FatalAlert] = kTopDarjeelingAlertPeripheralEdn0, + [kTopDarjeelingAlertIdEdn1RecovAlert] = kTopDarjeelingAlertPeripheralEdn1, + [kTopDarjeelingAlertIdEdn1FatalAlert] = kTopDarjeelingAlertPeripheralEdn1, + [kTopDarjeelingAlertIdSramCtrlMainFatalError] = kTopDarjeelingAlertPeripheralSramCtrlMain, + [kTopDarjeelingAlertIdSramCtrlMboxFatalError] = kTopDarjeelingAlertPeripheralSramCtrlMbox, + [kTopDarjeelingAlertIdRomCtrl0Fatal] = kTopDarjeelingAlertPeripheralRomCtrl0, + [kTopDarjeelingAlertIdRomCtrl1Fatal] = kTopDarjeelingAlertPeripheralRomCtrl1, + [kTopDarjeelingAlertIdDmaFatalFault] = kTopDarjeelingAlertPeripheralDma, + [kTopDarjeelingAlertIdMbx0FatalFault] = kTopDarjeelingAlertPeripheralMbx0, + [kTopDarjeelingAlertIdMbx0RecovFault] = kTopDarjeelingAlertPeripheralMbx0, + [kTopDarjeelingAlertIdMbx1FatalFault] = kTopDarjeelingAlertPeripheralMbx1, + [kTopDarjeelingAlertIdMbx1RecovFault] = kTopDarjeelingAlertPeripheralMbx1, + [kTopDarjeelingAlertIdMbx2FatalFault] = kTopDarjeelingAlertPeripheralMbx2, + [kTopDarjeelingAlertIdMbx2RecovFault] = kTopDarjeelingAlertPeripheralMbx2, + [kTopDarjeelingAlertIdMbx3FatalFault] = kTopDarjeelingAlertPeripheralMbx3, + [kTopDarjeelingAlertIdMbx3RecovFault] = kTopDarjeelingAlertPeripheralMbx3, + [kTopDarjeelingAlertIdMbx4FatalFault] = kTopDarjeelingAlertPeripheralMbx4, + [kTopDarjeelingAlertIdMbx4RecovFault] = kTopDarjeelingAlertPeripheralMbx4, + [kTopDarjeelingAlertIdMbx5FatalFault] = kTopDarjeelingAlertPeripheralMbx5, + [kTopDarjeelingAlertIdMbx5RecovFault] = kTopDarjeelingAlertPeripheralMbx5, + [kTopDarjeelingAlertIdMbx6FatalFault] = kTopDarjeelingAlertPeripheralMbx6, + [kTopDarjeelingAlertIdMbx6RecovFault] = kTopDarjeelingAlertPeripheralMbx6, + [kTopDarjeelingAlertIdMbxJtagFatalFault] = kTopDarjeelingAlertPeripheralMbxJtag, + [kTopDarjeelingAlertIdMbxJtagRecovFault] = kTopDarjeelingAlertPeripheralMbxJtag, + [kTopDarjeelingAlertIdMbxPcie0FatalFault] = kTopDarjeelingAlertPeripheralMbxPcie0, + [kTopDarjeelingAlertIdMbxPcie0RecovFault] = kTopDarjeelingAlertPeripheralMbxPcie0, + [kTopDarjeelingAlertIdMbxPcie1FatalFault] = kTopDarjeelingAlertPeripheralMbxPcie1, + [kTopDarjeelingAlertIdMbxPcie1RecovFault] = kTopDarjeelingAlertPeripheralMbxPcie1, + [kTopDarjeelingAlertIdRvCoreIbexFatalSwErr] = kTopDarjeelingAlertPeripheralRvCoreIbex, + [kTopDarjeelingAlertIdRvCoreIbexRecovSwErr] = kTopDarjeelingAlertPeripheralRvCoreIbex, + [kTopDarjeelingAlertIdRvCoreIbexFatalHwErr] = kTopDarjeelingAlertPeripheralRvCoreIbex, + [kTopDarjeelingAlertIdRvCoreIbexRecovHwErr] = kTopDarjeelingAlertPeripheralRvCoreIbex, +}; diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling.h b/hw/top_darjeeling/sw/autogen/top_darjeeling.h new file mode 100644 index 0000000000000..4057d586337be --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling.h @@ -0,0 +1,1674 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_H_ +#define OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_H_ + +/** + * @file + * @brief Top-specific Definitions + * + * This file contains preprocessor and type definitions for use within the + * device C/C++ codebase. + * + * These definitions are for information that depends on the top-specific chip + * configuration, which includes: + * - Device Memory Information (for Peripherals and Memory) + * - PLIC Interrupt ID Names and Source Mappings + * - Alert ID Names and Source Mappings + * - Pinmux Pin/Select Names + * - Power Manager Wakeups + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Peripheral base address for uart0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_UART0_BASE_ADDR 0x30010000u + +/** + * Peripheral size for uart0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_UART0_BASE_ADDR and + * `TOP_DARJEELING_UART0_BASE_ADDR + TOP_DARJEELING_UART0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_UART0_SIZE_BYTES 0x40u + +/** + * Peripheral base address for gpio in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_GPIO_BASE_ADDR 0x30000000u + +/** + * Peripheral size for gpio in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_GPIO_BASE_ADDR and + * `TOP_DARJEELING_GPIO_BASE_ADDR + TOP_DARJEELING_GPIO_SIZE_BYTES`. + */ +#define TOP_DARJEELING_GPIO_SIZE_BYTES 0x80u + +/** + * Peripheral base address for spi_device in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SPI_DEVICE_BASE_ADDR 0x30310000u + +/** + * Peripheral size for spi_device in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SPI_DEVICE_BASE_ADDR and + * `TOP_DARJEELING_SPI_DEVICE_BASE_ADDR + TOP_DARJEELING_SPI_DEVICE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SPI_DEVICE_SIZE_BYTES 0x2000u + +/** + * Peripheral base address for i2c0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_I2C0_BASE_ADDR 0x30080000u + +/** + * Peripheral size for i2c0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_I2C0_BASE_ADDR and + * `TOP_DARJEELING_I2C0_BASE_ADDR + TOP_DARJEELING_I2C0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_I2C0_SIZE_BYTES 0x80u + +/** + * Peripheral base address for rv_timer in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RV_TIMER_BASE_ADDR 0x30100000u + +/** + * Peripheral size for rv_timer in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RV_TIMER_BASE_ADDR and + * `TOP_DARJEELING_RV_TIMER_BASE_ADDR + TOP_DARJEELING_RV_TIMER_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RV_TIMER_SIZE_BYTES 0x200u + +/** + * Peripheral base address for core device on otp_ctrl in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR 0x30130000u + +/** + * Peripheral size for core device on otp_ctrl in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR and + * `TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR + TOP_DARJEELING_OTP_CTRL_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_OTP_CTRL_CORE_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for prim device on otp_ctrl in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_OTP_CTRL_PRIM_BASE_ADDR 0x30138000u + +/** + * Peripheral size for prim device on otp_ctrl in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_OTP_CTRL_PRIM_BASE_ADDR and + * `TOP_DARJEELING_OTP_CTRL_PRIM_BASE_ADDR + TOP_DARJEELING_OTP_CTRL_PRIM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_OTP_CTRL_PRIM_SIZE_BYTES 0x20u + +/** + * Peripheral base address for regs device on lc_ctrl in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR 0x30140000u + +/** + * Peripheral size for regs device on lc_ctrl in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR and + * `TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR + TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES 0x100u + +/** + * Peripheral base address for alert_handler in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR 0x30150000u + +/** + * Peripheral size for alert_handler in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR and + * `TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR + TOP_DARJEELING_ALERT_HANDLER_SIZE_BYTES`. + */ +#define TOP_DARJEELING_ALERT_HANDLER_SIZE_BYTES 0x800u + +/** + * Peripheral base address for spi_host0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SPI_HOST0_BASE_ADDR 0x30300000u + +/** + * Peripheral size for spi_host0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SPI_HOST0_BASE_ADDR and + * `TOP_DARJEELING_SPI_HOST0_BASE_ADDR + TOP_DARJEELING_SPI_HOST0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SPI_HOST0_SIZE_BYTES 0x40u + +/** + * Peripheral base address for pwrmgr_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_PWRMGR_AON_BASE_ADDR 0x30400000u + +/** + * Peripheral size for pwrmgr_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_PWRMGR_AON_BASE_ADDR and + * `TOP_DARJEELING_PWRMGR_AON_BASE_ADDR + TOP_DARJEELING_PWRMGR_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_PWRMGR_AON_SIZE_BYTES 0x80u + +/** + * Peripheral base address for rstmgr_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RSTMGR_AON_BASE_ADDR 0x30410000u + +/** + * Peripheral size for rstmgr_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RSTMGR_AON_BASE_ADDR and + * `TOP_DARJEELING_RSTMGR_AON_BASE_ADDR + TOP_DARJEELING_RSTMGR_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RSTMGR_AON_SIZE_BYTES 0x80u + +/** + * Peripheral base address for clkmgr_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_CLKMGR_AON_BASE_ADDR 0x30420000u + +/** + * Peripheral size for clkmgr_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_CLKMGR_AON_BASE_ADDR and + * `TOP_DARJEELING_CLKMGR_AON_BASE_ADDR + TOP_DARJEELING_CLKMGR_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_CLKMGR_AON_SIZE_BYTES 0x80u + +/** + * Peripheral base address for pinmux_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_PINMUX_AON_BASE_ADDR 0x30460000u + +/** + * Peripheral size for pinmux_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_PINMUX_AON_BASE_ADDR and + * `TOP_DARJEELING_PINMUX_AON_BASE_ADDR + TOP_DARJEELING_PINMUX_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_PINMUX_AON_SIZE_BYTES 0x800u + +/** + * Peripheral base address for aon_timer_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR 0x30470000u + +/** + * Peripheral size for aon_timer_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR and + * `TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR + TOP_DARJEELING_AON_TIMER_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_AON_TIMER_AON_SIZE_BYTES 0x40u + +/** + * Peripheral base address for ast in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_AST_BASE_ADDR 0x30480000u + +/** + * Peripheral size for ast in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_AST_BASE_ADDR and + * `TOP_DARJEELING_AST_BASE_ADDR + TOP_DARJEELING_AST_SIZE_BYTES`. + */ +#define TOP_DARJEELING_AST_SIZE_BYTES 0x400u + +/** + * Peripheral base address for sensor_ctrl in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SENSOR_CTRL_BASE_ADDR 0x30020000u + +/** + * Peripheral size for sensor_ctrl in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SENSOR_CTRL_BASE_ADDR and + * `TOP_DARJEELING_SENSOR_CTRL_BASE_ADDR + TOP_DARJEELING_SENSOR_CTRL_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SENSOR_CTRL_SIZE_BYTES 0x40u + +/** + * Peripheral base address for core device on soc_proxy in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR 0x22030000u + +/** + * Peripheral size for core device on soc_proxy in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR and + * `TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR + TOP_DARJEELING_SOC_PROXY_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SOC_PROXY_CORE_SIZE_BYTES 0x10u + +/** + * Peripheral base address for ctn device on soc_proxy in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR 0x40000000u + +/** + * Peripheral size for ctn device on soc_proxy in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR and + * `TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR + TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x40000000u + +/** + * Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x30500000u + +/** + * Peripheral size for regs device on sram_ctrl_ret_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and + * `TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40u + +/** + * Peripheral base address for ram device on sram_ctrl_ret_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x30600000u + +/** + * Peripheral size for ram device on sram_ctrl_ret_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and + * `TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for regs device on rv_dm in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RV_DM_REGS_BASE_ADDR 0x21200000u + +/** + * Peripheral size for regs device on rv_dm in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RV_DM_REGS_BASE_ADDR and + * `TOP_DARJEELING_RV_DM_REGS_BASE_ADDR + TOP_DARJEELING_RV_DM_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RV_DM_REGS_SIZE_BYTES 0x10u + +/** + * Peripheral base address for mem device on rv_dm in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RV_DM_MEM_BASE_ADDR 0x40000u + +/** + * Peripheral size for mem device on rv_dm in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RV_DM_MEM_BASE_ADDR and + * `TOP_DARJEELING_RV_DM_MEM_BASE_ADDR + TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for rv_plic in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RV_PLIC_BASE_ADDR 0x28000000u + +/** + * Peripheral size for rv_plic in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RV_PLIC_BASE_ADDR and + * `TOP_DARJEELING_RV_PLIC_BASE_ADDR + TOP_DARJEELING_RV_PLIC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RV_PLIC_SIZE_BYTES 0x8000000u + +/** + * Peripheral base address for aes in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_AES_BASE_ADDR 0x21100000u + +/** + * Peripheral size for aes in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_AES_BASE_ADDR and + * `TOP_DARJEELING_AES_BASE_ADDR + TOP_DARJEELING_AES_SIZE_BYTES`. + */ +#define TOP_DARJEELING_AES_SIZE_BYTES 0x100u + +/** + * Peripheral base address for hmac in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_HMAC_BASE_ADDR 0x21110000u + +/** + * Peripheral size for hmac in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_HMAC_BASE_ADDR and + * `TOP_DARJEELING_HMAC_BASE_ADDR + TOP_DARJEELING_HMAC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_HMAC_SIZE_BYTES 0x2000u + +/** + * Peripheral base address for kmac in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_KMAC_BASE_ADDR 0x21120000u + +/** + * Peripheral size for kmac in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_KMAC_BASE_ADDR and + * `TOP_DARJEELING_KMAC_BASE_ADDR + TOP_DARJEELING_KMAC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_KMAC_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for otbn in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_OTBN_BASE_ADDR 0x21130000u + +/** + * Peripheral size for otbn in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_OTBN_BASE_ADDR and + * `TOP_DARJEELING_OTBN_BASE_ADDR + TOP_DARJEELING_OTBN_SIZE_BYTES`. + */ +#define TOP_DARJEELING_OTBN_SIZE_BYTES 0x10000u + +/** + * Peripheral base address for keymgr_dpe in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR 0x21140000u + +/** + * Peripheral size for keymgr_dpe in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR and + * `TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR + TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES 0x100u + +/** + * Peripheral base address for csrng in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_CSRNG_BASE_ADDR 0x21150000u + +/** + * Peripheral size for csrng in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_CSRNG_BASE_ADDR and + * `TOP_DARJEELING_CSRNG_BASE_ADDR + TOP_DARJEELING_CSRNG_SIZE_BYTES`. + */ +#define TOP_DARJEELING_CSRNG_SIZE_BYTES 0x80u + +/** + * Peripheral base address for edn0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_EDN0_BASE_ADDR 0x21170000u + +/** + * Peripheral size for edn0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_EDN0_BASE_ADDR and + * `TOP_DARJEELING_EDN0_BASE_ADDR + TOP_DARJEELING_EDN0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_EDN0_SIZE_BYTES 0x80u + +/** + * Peripheral base address for edn1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_EDN1_BASE_ADDR 0x21180000u + +/** + * Peripheral size for edn1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_EDN1_BASE_ADDR and + * `TOP_DARJEELING_EDN1_BASE_ADDR + TOP_DARJEELING_EDN1_SIZE_BYTES`. + */ +#define TOP_DARJEELING_EDN1_SIZE_BYTES 0x80u + +/** + * Peripheral base address for regs device on sram_ctrl_main in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x211C0000u + +/** + * Peripheral size for regs device on sram_ctrl_main in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR and + * `TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u + +/** + * Peripheral base address for ram device on sram_ctrl_main in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u + +/** + * Peripheral size for ram device on sram_ctrl_main in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR and + * `TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x10000u + +/** + * Peripheral base address for regs device on sram_ctrl_mbox in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR 0x211D0000u + +/** + * Peripheral size for regs device on sram_ctrl_mbox in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR and + * `TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_SIZE_BYTES 0x40u + +/** + * Peripheral base address for ram device on sram_ctrl_mbox in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR 0x11000000u + +/** + * Peripheral size for ram device on sram_ctrl_mbox in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR and + * `TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for regs device on rom_ctrl0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR 0x211E0000u + +/** + * Peripheral size for regs device on rom_ctrl0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR and + * `TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR + TOP_DARJEELING_ROM_CTRL0_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_ROM_CTRL0_REGS_SIZE_BYTES 0x80u + +/** + * Peripheral base address for rom device on rom_ctrl0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR 0x8000u + +/** + * Peripheral size for rom device on rom_ctrl0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR and + * `TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR + TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES 0x8000u + +/** + * Peripheral base address for regs device on rom_ctrl1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR 0x211E1000u + +/** + * Peripheral size for regs device on rom_ctrl1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR and + * `TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR + TOP_DARJEELING_ROM_CTRL1_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_ROM_CTRL1_REGS_SIZE_BYTES 0x80u + +/** + * Peripheral base address for rom device on rom_ctrl1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR 0x20000u + +/** + * Peripheral size for rom device on rom_ctrl1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR and + * `TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR + TOP_DARJEELING_ROM_CTRL1_ROM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_ROM_CTRL1_ROM_SIZE_BYTES 0x10000u + +/** + * Peripheral base address for dma in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_DMA_BASE_ADDR 0x22010000u + +/** + * Peripheral size for dma in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_DMA_BASE_ADDR and + * `TOP_DARJEELING_DMA_BASE_ADDR + TOP_DARJEELING_DMA_SIZE_BYTES`. + */ +#define TOP_DARJEELING_DMA_SIZE_BYTES 0x200u + +/** + * Peripheral base address for core device on mbx0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX0_CORE_BASE_ADDR 0x22000000u + +/** + * Peripheral size for core device on mbx0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX0_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX0_CORE_BASE_ADDR + TOP_DARJEELING_MBX0_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX0_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX1_CORE_BASE_ADDR 0x22000100u + +/** + * Peripheral size for core device on mbx1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX1_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX1_CORE_BASE_ADDR + TOP_DARJEELING_MBX1_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX1_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx2 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX2_CORE_BASE_ADDR 0x22000200u + +/** + * Peripheral size for core device on mbx2 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX2_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX2_CORE_BASE_ADDR + TOP_DARJEELING_MBX2_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX2_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx3 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX3_CORE_BASE_ADDR 0x22000300u + +/** + * Peripheral size for core device on mbx3 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX3_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX3_CORE_BASE_ADDR + TOP_DARJEELING_MBX3_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX3_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx4 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX4_CORE_BASE_ADDR 0x22000400u + +/** + * Peripheral size for core device on mbx4 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX4_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX4_CORE_BASE_ADDR + TOP_DARJEELING_MBX4_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX4_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx5 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX5_CORE_BASE_ADDR 0x22000500u + +/** + * Peripheral size for core device on mbx5 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX5_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX5_CORE_BASE_ADDR + TOP_DARJEELING_MBX5_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX5_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx6 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX6_CORE_BASE_ADDR 0x22000600u + +/** + * Peripheral size for core device on mbx6 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX6_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX6_CORE_BASE_ADDR + TOP_DARJEELING_MBX6_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX6_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx_jtag in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR 0x22000800u + +/** + * Peripheral size for core device on mbx_jtag in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx_pcie0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR 0x22040000u + +/** + * Peripheral size for core device on mbx_pcie0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx_pcie1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR 0x22040100u + +/** + * Peripheral size for core device on mbx_pcie1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for cfg device on rv_core_ibex in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR 0x211F0000u + +/** + * Peripheral size for cfg device on rv_core_ibex in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR and + * `TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100u + + +/** + * Memory base address for ctn in top darjeeling. + */ +#define TOP_DARJEELING_CTN_BASE_ADDR 0x40000000u + +/** + * Memory size for ctn in top darjeeling. + */ +#define TOP_DARJEELING_CTN_SIZE_BYTES 0x40000000u + +/** + * Memory base address for ram_ret_aon in top darjeeling. + */ +#define TOP_DARJEELING_RAM_RET_AON_BASE_ADDR 0x30600000u + +/** + * Memory size for ram_ret_aon in top darjeeling. + */ +#define TOP_DARJEELING_RAM_RET_AON_SIZE_BYTES 0x1000u + +/** + * Memory base address for ram_main in top darjeeling. + */ +#define TOP_DARJEELING_RAM_MAIN_BASE_ADDR 0x10000000u + +/** + * Memory size for ram_main in top darjeeling. + */ +#define TOP_DARJEELING_RAM_MAIN_SIZE_BYTES 0x10000u + +/** + * Memory base address for ram_mbox in top darjeeling. + */ +#define TOP_DARJEELING_RAM_MBOX_BASE_ADDR 0x11000000u + +/** + * Memory size for ram_mbox in top darjeeling. + */ +#define TOP_DARJEELING_RAM_MBOX_SIZE_BYTES 0x1000u + +/** + * Memory base address for rom0 in top darjeeling. + */ +#define TOP_DARJEELING_ROM0_BASE_ADDR 0x8000u + +/** + * Memory size for rom0 in top darjeeling. + */ +#define TOP_DARJEELING_ROM0_SIZE_BYTES 0x8000u + +/** + * Memory base address for rom1 in top darjeeling. + */ +#define TOP_DARJEELING_ROM1_BASE_ADDR 0x20000u + +/** + * Memory size for rom1 in top darjeeling. + */ +#define TOP_DARJEELING_ROM1_SIZE_BYTES 0x10000u + + +/** + * PLIC Interrupt Source Peripheral. + * + * Enumeration used to determine which peripheral asserted the corresponding + * interrupt. + */ +typedef enum top_darjeeling_plic_peripheral { + kTopDarjeelingPlicPeripheralUnknown = 0, /**< Unknown Peripheral */ + kTopDarjeelingPlicPeripheralUart0 = 1, /**< uart0 */ + kTopDarjeelingPlicPeripheralGpio = 2, /**< gpio */ + kTopDarjeelingPlicPeripheralSpiDevice = 3, /**< spi_device */ + kTopDarjeelingPlicPeripheralI2c0 = 4, /**< i2c0 */ + kTopDarjeelingPlicPeripheralRvTimer = 5, /**< rv_timer */ + kTopDarjeelingPlicPeripheralOtpCtrl = 6, /**< otp_ctrl */ + kTopDarjeelingPlicPeripheralAlertHandler = 7, /**< alert_handler */ + kTopDarjeelingPlicPeripheralSpiHost0 = 8, /**< spi_host0 */ + kTopDarjeelingPlicPeripheralPwrmgrAon = 9, /**< pwrmgr_aon */ + kTopDarjeelingPlicPeripheralAonTimerAon = 10, /**< aon_timer_aon */ + kTopDarjeelingPlicPeripheralSensorCtrl = 11, /**< sensor_ctrl */ + kTopDarjeelingPlicPeripheralSocProxy = 12, /**< soc_proxy */ + kTopDarjeelingPlicPeripheralHmac = 13, /**< hmac */ + kTopDarjeelingPlicPeripheralKmac = 14, /**< kmac */ + kTopDarjeelingPlicPeripheralOtbn = 15, /**< otbn */ + kTopDarjeelingPlicPeripheralKeymgrDpe = 16, /**< keymgr_dpe */ + kTopDarjeelingPlicPeripheralCsrng = 17, /**< csrng */ + kTopDarjeelingPlicPeripheralEdn0 = 18, /**< edn0 */ + kTopDarjeelingPlicPeripheralEdn1 = 19, /**< edn1 */ + kTopDarjeelingPlicPeripheralDma = 20, /**< dma */ + kTopDarjeelingPlicPeripheralMbx0 = 21, /**< mbx0 */ + kTopDarjeelingPlicPeripheralMbx1 = 22, /**< mbx1 */ + kTopDarjeelingPlicPeripheralMbx2 = 23, /**< mbx2 */ + kTopDarjeelingPlicPeripheralMbx3 = 24, /**< mbx3 */ + kTopDarjeelingPlicPeripheralMbx4 = 25, /**< mbx4 */ + kTopDarjeelingPlicPeripheralMbx5 = 26, /**< mbx5 */ + kTopDarjeelingPlicPeripheralMbx6 = 27, /**< mbx6 */ + kTopDarjeelingPlicPeripheralMbxJtag = 28, /**< mbx_jtag */ + kTopDarjeelingPlicPeripheralMbxPcie0 = 29, /**< mbx_pcie0 */ + kTopDarjeelingPlicPeripheralMbxPcie1 = 30, /**< mbx_pcie1 */ + kTopDarjeelingPlicPeripheralLast = 30, /**< \internal Final PLIC peripheral */ +} top_darjeeling_plic_peripheral_t; + +/** + * PLIC Interrupt Source. + * + * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to + * the same peripheral are guaranteed to be consecutive. + */ +typedef enum top_darjeeling_plic_irq_id { + kTopDarjeelingPlicIrqIdNone = 0, /**< No Interrupt */ + kTopDarjeelingPlicIrqIdUart0TxWatermark = 1, /**< uart0_tx_watermark */ + kTopDarjeelingPlicIrqIdUart0RxWatermark = 2, /**< uart0_rx_watermark */ + kTopDarjeelingPlicIrqIdUart0TxDone = 3, /**< uart0_tx_done */ + kTopDarjeelingPlicIrqIdUart0RxOverflow = 4, /**< uart0_rx_overflow */ + kTopDarjeelingPlicIrqIdUart0RxFrameErr = 5, /**< uart0_rx_frame_err */ + kTopDarjeelingPlicIrqIdUart0RxBreakErr = 6, /**< uart0_rx_break_err */ + kTopDarjeelingPlicIrqIdUart0RxTimeout = 7, /**< uart0_rx_timeout */ + kTopDarjeelingPlicIrqIdUart0RxParityErr = 8, /**< uart0_rx_parity_err */ + kTopDarjeelingPlicIrqIdUart0TxEmpty = 9, /**< uart0_tx_empty */ + kTopDarjeelingPlicIrqIdGpioGpio0 = 10, /**< gpio_gpio 0 */ + kTopDarjeelingPlicIrqIdGpioGpio1 = 11, /**< gpio_gpio 1 */ + kTopDarjeelingPlicIrqIdGpioGpio2 = 12, /**< gpio_gpio 2 */ + kTopDarjeelingPlicIrqIdGpioGpio3 = 13, /**< gpio_gpio 3 */ + kTopDarjeelingPlicIrqIdGpioGpio4 = 14, /**< gpio_gpio 4 */ + kTopDarjeelingPlicIrqIdGpioGpio5 = 15, /**< gpio_gpio 5 */ + kTopDarjeelingPlicIrqIdGpioGpio6 = 16, /**< gpio_gpio 6 */ + kTopDarjeelingPlicIrqIdGpioGpio7 = 17, /**< gpio_gpio 7 */ + kTopDarjeelingPlicIrqIdGpioGpio8 = 18, /**< gpio_gpio 8 */ + kTopDarjeelingPlicIrqIdGpioGpio9 = 19, /**< gpio_gpio 9 */ + kTopDarjeelingPlicIrqIdGpioGpio10 = 20, /**< gpio_gpio 10 */ + kTopDarjeelingPlicIrqIdGpioGpio11 = 21, /**< gpio_gpio 11 */ + kTopDarjeelingPlicIrqIdGpioGpio12 = 22, /**< gpio_gpio 12 */ + kTopDarjeelingPlicIrqIdGpioGpio13 = 23, /**< gpio_gpio 13 */ + kTopDarjeelingPlicIrqIdGpioGpio14 = 24, /**< gpio_gpio 14 */ + kTopDarjeelingPlicIrqIdGpioGpio15 = 25, /**< gpio_gpio 15 */ + kTopDarjeelingPlicIrqIdGpioGpio16 = 26, /**< gpio_gpio 16 */ + kTopDarjeelingPlicIrqIdGpioGpio17 = 27, /**< gpio_gpio 17 */ + kTopDarjeelingPlicIrqIdGpioGpio18 = 28, /**< gpio_gpio 18 */ + kTopDarjeelingPlicIrqIdGpioGpio19 = 29, /**< gpio_gpio 19 */ + kTopDarjeelingPlicIrqIdGpioGpio20 = 30, /**< gpio_gpio 20 */ + kTopDarjeelingPlicIrqIdGpioGpio21 = 31, /**< gpio_gpio 21 */ + kTopDarjeelingPlicIrqIdGpioGpio22 = 32, /**< gpio_gpio 22 */ + kTopDarjeelingPlicIrqIdGpioGpio23 = 33, /**< gpio_gpio 23 */ + kTopDarjeelingPlicIrqIdGpioGpio24 = 34, /**< gpio_gpio 24 */ + kTopDarjeelingPlicIrqIdGpioGpio25 = 35, /**< gpio_gpio 25 */ + kTopDarjeelingPlicIrqIdGpioGpio26 = 36, /**< gpio_gpio 26 */ + kTopDarjeelingPlicIrqIdGpioGpio27 = 37, /**< gpio_gpio 27 */ + kTopDarjeelingPlicIrqIdGpioGpio28 = 38, /**< gpio_gpio 28 */ + kTopDarjeelingPlicIrqIdGpioGpio29 = 39, /**< gpio_gpio 29 */ + kTopDarjeelingPlicIrqIdGpioGpio30 = 40, /**< gpio_gpio 30 */ + kTopDarjeelingPlicIrqIdGpioGpio31 = 41, /**< gpio_gpio 31 */ + kTopDarjeelingPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 42, /**< spi_device_upload_cmdfifo_not_empty */ + kTopDarjeelingPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 43, /**< spi_device_upload_payload_not_empty */ + kTopDarjeelingPlicIrqIdSpiDeviceUploadPayloadOverflow = 44, /**< spi_device_upload_payload_overflow */ + kTopDarjeelingPlicIrqIdSpiDeviceReadbufWatermark = 45, /**< spi_device_readbuf_watermark */ + kTopDarjeelingPlicIrqIdSpiDeviceReadbufFlip = 46, /**< spi_device_readbuf_flip */ + kTopDarjeelingPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 47, /**< spi_device_tpm_header_not_empty */ + kTopDarjeelingPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 48, /**< spi_device_tpm_rdfifo_cmd_end */ + kTopDarjeelingPlicIrqIdSpiDeviceTpmRdfifoDrop = 49, /**< spi_device_tpm_rdfifo_drop */ + kTopDarjeelingPlicIrqIdI2c0FmtThreshold = 50, /**< i2c0_fmt_threshold */ + kTopDarjeelingPlicIrqIdI2c0RxThreshold = 51, /**< i2c0_rx_threshold */ + kTopDarjeelingPlicIrqIdI2c0AcqThreshold = 52, /**< i2c0_acq_threshold */ + kTopDarjeelingPlicIrqIdI2c0RxOverflow = 53, /**< i2c0_rx_overflow */ + kTopDarjeelingPlicIrqIdI2c0ControllerHalt = 54, /**< i2c0_controller_halt */ + kTopDarjeelingPlicIrqIdI2c0SclInterference = 55, /**< i2c0_scl_interference */ + kTopDarjeelingPlicIrqIdI2c0SdaInterference = 56, /**< i2c0_sda_interference */ + kTopDarjeelingPlicIrqIdI2c0StretchTimeout = 57, /**< i2c0_stretch_timeout */ + kTopDarjeelingPlicIrqIdI2c0SdaUnstable = 58, /**< i2c0_sda_unstable */ + kTopDarjeelingPlicIrqIdI2c0CmdComplete = 59, /**< i2c0_cmd_complete */ + kTopDarjeelingPlicIrqIdI2c0TxStretch = 60, /**< i2c0_tx_stretch */ + kTopDarjeelingPlicIrqIdI2c0TxThreshold = 61, /**< i2c0_tx_threshold */ + kTopDarjeelingPlicIrqIdI2c0AcqStretch = 62, /**< i2c0_acq_stretch */ + kTopDarjeelingPlicIrqIdI2c0UnexpStop = 63, /**< i2c0_unexp_stop */ + kTopDarjeelingPlicIrqIdI2c0HostTimeout = 64, /**< i2c0_host_timeout */ + kTopDarjeelingPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 65, /**< rv_timer_timer_expired_hart0_timer0 */ + kTopDarjeelingPlicIrqIdOtpCtrlOtpOperationDone = 66, /**< otp_ctrl_otp_operation_done */ + kTopDarjeelingPlicIrqIdOtpCtrlOtpError = 67, /**< otp_ctrl_otp_error */ + kTopDarjeelingPlicIrqIdAlertHandlerClassa = 68, /**< alert_handler_classa */ + kTopDarjeelingPlicIrqIdAlertHandlerClassb = 69, /**< alert_handler_classb */ + kTopDarjeelingPlicIrqIdAlertHandlerClassc = 70, /**< alert_handler_classc */ + kTopDarjeelingPlicIrqIdAlertHandlerClassd = 71, /**< alert_handler_classd */ + kTopDarjeelingPlicIrqIdSpiHost0Error = 72, /**< spi_host0_error */ + kTopDarjeelingPlicIrqIdSpiHost0SpiEvent = 73, /**< spi_host0_spi_event */ + kTopDarjeelingPlicIrqIdPwrmgrAonWakeup = 74, /**< pwrmgr_aon_wakeup */ + kTopDarjeelingPlicIrqIdAonTimerAonWkupTimerExpired = 75, /**< aon_timer_aon_wkup_timer_expired */ + kTopDarjeelingPlicIrqIdAonTimerAonWdogTimerBark = 76, /**< aon_timer_aon_wdog_timer_bark */ + kTopDarjeelingPlicIrqIdSensorCtrlIoStatusChange = 77, /**< sensor_ctrl_io_status_change */ + kTopDarjeelingPlicIrqIdSensorCtrlInitStatusChange = 78, /**< sensor_ctrl_init_status_change */ + kTopDarjeelingPlicIrqIdSocProxyExternal0 = 79, /**< soc_proxy_external 0 */ + kTopDarjeelingPlicIrqIdSocProxyExternal1 = 80, /**< soc_proxy_external 1 */ + kTopDarjeelingPlicIrqIdSocProxyExternal2 = 81, /**< soc_proxy_external 2 */ + kTopDarjeelingPlicIrqIdSocProxyExternal3 = 82, /**< soc_proxy_external 3 */ + kTopDarjeelingPlicIrqIdSocProxyExternal4 = 83, /**< soc_proxy_external 4 */ + kTopDarjeelingPlicIrqIdSocProxyExternal5 = 84, /**< soc_proxy_external 5 */ + kTopDarjeelingPlicIrqIdSocProxyExternal6 = 85, /**< soc_proxy_external 6 */ + kTopDarjeelingPlicIrqIdSocProxyExternal7 = 86, /**< soc_proxy_external 7 */ + kTopDarjeelingPlicIrqIdSocProxyExternal8 = 87, /**< soc_proxy_external 8 */ + kTopDarjeelingPlicIrqIdSocProxyExternal9 = 88, /**< soc_proxy_external 9 */ + kTopDarjeelingPlicIrqIdSocProxyExternal10 = 89, /**< soc_proxy_external 10 */ + kTopDarjeelingPlicIrqIdSocProxyExternal11 = 90, /**< soc_proxy_external 11 */ + kTopDarjeelingPlicIrqIdSocProxyExternal12 = 91, /**< soc_proxy_external 12 */ + kTopDarjeelingPlicIrqIdSocProxyExternal13 = 92, /**< soc_proxy_external 13 */ + kTopDarjeelingPlicIrqIdSocProxyExternal14 = 93, /**< soc_proxy_external 14 */ + kTopDarjeelingPlicIrqIdSocProxyExternal15 = 94, /**< soc_proxy_external 15 */ + kTopDarjeelingPlicIrqIdSocProxyExternal16 = 95, /**< soc_proxy_external 16 */ + kTopDarjeelingPlicIrqIdSocProxyExternal17 = 96, /**< soc_proxy_external 17 */ + kTopDarjeelingPlicIrqIdSocProxyExternal18 = 97, /**< soc_proxy_external 18 */ + kTopDarjeelingPlicIrqIdSocProxyExternal19 = 98, /**< soc_proxy_external 19 */ + kTopDarjeelingPlicIrqIdSocProxyExternal20 = 99, /**< soc_proxy_external 20 */ + kTopDarjeelingPlicIrqIdSocProxyExternal21 = 100, /**< soc_proxy_external 21 */ + kTopDarjeelingPlicIrqIdSocProxyExternal22 = 101, /**< soc_proxy_external 22 */ + kTopDarjeelingPlicIrqIdSocProxyExternal23 = 102, /**< soc_proxy_external 23 */ + kTopDarjeelingPlicIrqIdSocProxyExternal24 = 103, /**< soc_proxy_external 24 */ + kTopDarjeelingPlicIrqIdSocProxyExternal25 = 104, /**< soc_proxy_external 25 */ + kTopDarjeelingPlicIrqIdSocProxyExternal26 = 105, /**< soc_proxy_external 26 */ + kTopDarjeelingPlicIrqIdSocProxyExternal27 = 106, /**< soc_proxy_external 27 */ + kTopDarjeelingPlicIrqIdSocProxyExternal28 = 107, /**< soc_proxy_external 28 */ + kTopDarjeelingPlicIrqIdSocProxyExternal29 = 108, /**< soc_proxy_external 29 */ + kTopDarjeelingPlicIrqIdSocProxyExternal30 = 109, /**< soc_proxy_external 30 */ + kTopDarjeelingPlicIrqIdSocProxyExternal31 = 110, /**< soc_proxy_external 31 */ + kTopDarjeelingPlicIrqIdHmacHmacDone = 111, /**< hmac_hmac_done */ + kTopDarjeelingPlicIrqIdHmacFifoEmpty = 112, /**< hmac_fifo_empty */ + kTopDarjeelingPlicIrqIdHmacHmacErr = 113, /**< hmac_hmac_err */ + kTopDarjeelingPlicIrqIdKmacKmacDone = 114, /**< kmac_kmac_done */ + kTopDarjeelingPlicIrqIdKmacFifoEmpty = 115, /**< kmac_fifo_empty */ + kTopDarjeelingPlicIrqIdKmacKmacErr = 116, /**< kmac_kmac_err */ + kTopDarjeelingPlicIrqIdOtbnDone = 117, /**< otbn_done */ + kTopDarjeelingPlicIrqIdKeymgrDpeOpDone = 118, /**< keymgr_dpe_op_done */ + kTopDarjeelingPlicIrqIdCsrngCsCmdReqDone = 119, /**< csrng_cs_cmd_req_done */ + kTopDarjeelingPlicIrqIdCsrngCsEntropyReq = 120, /**< csrng_cs_entropy_req */ + kTopDarjeelingPlicIrqIdCsrngCsHwInstExc = 121, /**< csrng_cs_hw_inst_exc */ + kTopDarjeelingPlicIrqIdCsrngCsFatalErr = 122, /**< csrng_cs_fatal_err */ + kTopDarjeelingPlicIrqIdEdn0EdnCmdReqDone = 123, /**< edn0_edn_cmd_req_done */ + kTopDarjeelingPlicIrqIdEdn0EdnFatalErr = 124, /**< edn0_edn_fatal_err */ + kTopDarjeelingPlicIrqIdEdn1EdnCmdReqDone = 125, /**< edn1_edn_cmd_req_done */ + kTopDarjeelingPlicIrqIdEdn1EdnFatalErr = 126, /**< edn1_edn_fatal_err */ + kTopDarjeelingPlicIrqIdDmaDmaDone = 127, /**< dma_dma_done */ + kTopDarjeelingPlicIrqIdDmaDmaChunkDone = 128, /**< dma_dma_chunk_done */ + kTopDarjeelingPlicIrqIdDmaDmaError = 129, /**< dma_dma_error */ + kTopDarjeelingPlicIrqIdMbx0MbxReady = 130, /**< mbx0_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx0MbxAbort = 131, /**< mbx0_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx0MbxError = 132, /**< mbx0_mbx_error */ + kTopDarjeelingPlicIrqIdMbx1MbxReady = 133, /**< mbx1_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx1MbxAbort = 134, /**< mbx1_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx1MbxError = 135, /**< mbx1_mbx_error */ + kTopDarjeelingPlicIrqIdMbx2MbxReady = 136, /**< mbx2_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx2MbxAbort = 137, /**< mbx2_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx2MbxError = 138, /**< mbx2_mbx_error */ + kTopDarjeelingPlicIrqIdMbx3MbxReady = 139, /**< mbx3_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx3MbxAbort = 140, /**< mbx3_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx3MbxError = 141, /**< mbx3_mbx_error */ + kTopDarjeelingPlicIrqIdMbx4MbxReady = 142, /**< mbx4_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx4MbxAbort = 143, /**< mbx4_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx4MbxError = 144, /**< mbx4_mbx_error */ + kTopDarjeelingPlicIrqIdMbx5MbxReady = 145, /**< mbx5_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx5MbxAbort = 146, /**< mbx5_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx5MbxError = 147, /**< mbx5_mbx_error */ + kTopDarjeelingPlicIrqIdMbx6MbxReady = 148, /**< mbx6_mbx_ready */ + kTopDarjeelingPlicIrqIdMbx6MbxAbort = 149, /**< mbx6_mbx_abort */ + kTopDarjeelingPlicIrqIdMbx6MbxError = 150, /**< mbx6_mbx_error */ + kTopDarjeelingPlicIrqIdMbxJtagMbxReady = 151, /**< mbx_jtag_mbx_ready */ + kTopDarjeelingPlicIrqIdMbxJtagMbxAbort = 152, /**< mbx_jtag_mbx_abort */ + kTopDarjeelingPlicIrqIdMbxJtagMbxError = 153, /**< mbx_jtag_mbx_error */ + kTopDarjeelingPlicIrqIdMbxPcie0MbxReady = 154, /**< mbx_pcie0_mbx_ready */ + kTopDarjeelingPlicIrqIdMbxPcie0MbxAbort = 155, /**< mbx_pcie0_mbx_abort */ + kTopDarjeelingPlicIrqIdMbxPcie0MbxError = 156, /**< mbx_pcie0_mbx_error */ + kTopDarjeelingPlicIrqIdMbxPcie1MbxReady = 157, /**< mbx_pcie1_mbx_ready */ + kTopDarjeelingPlicIrqIdMbxPcie1MbxAbort = 158, /**< mbx_pcie1_mbx_abort */ + kTopDarjeelingPlicIrqIdMbxPcie1MbxError = 159, /**< mbx_pcie1_mbx_error */ + kTopDarjeelingPlicIrqIdLast = 159, /**< \internal The Last Valid Interrupt ID. */ +} top_darjeeling_plic_irq_id_t; + +/** + * PLIC Interrupt Source to Peripheral Map + * + * This array is a mapping from `top_darjeeling_plic_irq_id_t` to + * `top_darjeeling_plic_peripheral_t`. + */ +extern const top_darjeeling_plic_peripheral_t + top_darjeeling_plic_interrupt_for_peripheral[160]; + +/** + * PLIC Interrupt Target. + * + * Enumeration used to determine which set of IE, CC, threshold registers to + * access for a given interrupt target. + */ +typedef enum top_darjeeling_plic_target { + kTopDarjeelingPlicTargetIbex0 = 0, /**< Ibex Core 0 */ + kTopDarjeelingPlicTargetLast = 0, /**< \internal Final PLIC target */ +} top_darjeeling_plic_target_t; + +/** + * Alert Handler Source Peripheral. + * + * Enumeration used to determine which peripheral asserted the corresponding + * alert. + */ +typedef enum top_darjeeling_alert_peripheral { + kTopDarjeelingAlertPeripheralUart0 = 0, /**< uart0 */ + kTopDarjeelingAlertPeripheralGpio = 1, /**< gpio */ + kTopDarjeelingAlertPeripheralSpiDevice = 2, /**< spi_device */ + kTopDarjeelingAlertPeripheralI2c0 = 3, /**< i2c0 */ + kTopDarjeelingAlertPeripheralRvTimer = 4, /**< rv_timer */ + kTopDarjeelingAlertPeripheralOtpCtrl = 5, /**< otp_ctrl */ + kTopDarjeelingAlertPeripheralLcCtrl = 6, /**< lc_ctrl */ + kTopDarjeelingAlertPeripheralSpiHost0 = 7, /**< spi_host0 */ + kTopDarjeelingAlertPeripheralPwrmgrAon = 8, /**< pwrmgr_aon */ + kTopDarjeelingAlertPeripheralRstmgrAon = 9, /**< rstmgr_aon */ + kTopDarjeelingAlertPeripheralClkmgrAon = 10, /**< clkmgr_aon */ + kTopDarjeelingAlertPeripheralPinmuxAon = 11, /**< pinmux_aon */ + kTopDarjeelingAlertPeripheralAonTimerAon = 12, /**< aon_timer_aon */ + kTopDarjeelingAlertPeripheralSensorCtrl = 13, /**< sensor_ctrl */ + kTopDarjeelingAlertPeripheralSocProxy = 14, /**< soc_proxy */ + kTopDarjeelingAlertPeripheralSramCtrlRetAon = 15, /**< sram_ctrl_ret_aon */ + kTopDarjeelingAlertPeripheralRvDm = 16, /**< rv_dm */ + kTopDarjeelingAlertPeripheralRvPlic = 17, /**< rv_plic */ + kTopDarjeelingAlertPeripheralAes = 18, /**< aes */ + kTopDarjeelingAlertPeripheralHmac = 19, /**< hmac */ + kTopDarjeelingAlertPeripheralKmac = 20, /**< kmac */ + kTopDarjeelingAlertPeripheralOtbn = 21, /**< otbn */ + kTopDarjeelingAlertPeripheralKeymgrDpe = 22, /**< keymgr_dpe */ + kTopDarjeelingAlertPeripheralCsrng = 23, /**< csrng */ + kTopDarjeelingAlertPeripheralEdn0 = 24, /**< edn0 */ + kTopDarjeelingAlertPeripheralEdn1 = 25, /**< edn1 */ + kTopDarjeelingAlertPeripheralSramCtrlMain = 26, /**< sram_ctrl_main */ + kTopDarjeelingAlertPeripheralSramCtrlMbox = 27, /**< sram_ctrl_mbox */ + kTopDarjeelingAlertPeripheralRomCtrl0 = 28, /**< rom_ctrl0 */ + kTopDarjeelingAlertPeripheralRomCtrl1 = 29, /**< rom_ctrl1 */ + kTopDarjeelingAlertPeripheralDma = 30, /**< dma */ + kTopDarjeelingAlertPeripheralMbx0 = 31, /**< mbx0 */ + kTopDarjeelingAlertPeripheralMbx1 = 32, /**< mbx1 */ + kTopDarjeelingAlertPeripheralMbx2 = 33, /**< mbx2 */ + kTopDarjeelingAlertPeripheralMbx3 = 34, /**< mbx3 */ + kTopDarjeelingAlertPeripheralMbx4 = 35, /**< mbx4 */ + kTopDarjeelingAlertPeripheralMbx5 = 36, /**< mbx5 */ + kTopDarjeelingAlertPeripheralMbx6 = 37, /**< mbx6 */ + kTopDarjeelingAlertPeripheralMbxJtag = 38, /**< mbx_jtag */ + kTopDarjeelingAlertPeripheralMbxPcie0 = 39, /**< mbx_pcie0 */ + kTopDarjeelingAlertPeripheralMbxPcie1 = 40, /**< mbx_pcie1 */ + kTopDarjeelingAlertPeripheralRvCoreIbex = 41, /**< rv_core_ibex */ + kTopDarjeelingAlertPeripheralLast = 41, /**< \internal Final Alert peripheral */ +} top_darjeeling_alert_peripheral_t; + +/** + * Alert Handler Alert Source. + * + * Enumeration of all Alert Handler Alert Sources. The alert sources belonging to + * the same peripheral are guaranteed to be consecutive. + */ +typedef enum top_darjeeling_alert_id { + kTopDarjeelingAlertIdUart0FatalFault = 0, /**< uart0_fatal_fault */ + kTopDarjeelingAlertIdGpioFatalFault = 1, /**< gpio_fatal_fault */ + kTopDarjeelingAlertIdSpiDeviceFatalFault = 2, /**< spi_device_fatal_fault */ + kTopDarjeelingAlertIdI2c0FatalFault = 3, /**< i2c0_fatal_fault */ + kTopDarjeelingAlertIdRvTimerFatalFault = 4, /**< rv_timer_fatal_fault */ + kTopDarjeelingAlertIdOtpCtrlFatalMacroError = 5, /**< otp_ctrl_fatal_macro_error */ + kTopDarjeelingAlertIdOtpCtrlFatalCheckError = 6, /**< otp_ctrl_fatal_check_error */ + kTopDarjeelingAlertIdOtpCtrlFatalBusIntegError = 7, /**< otp_ctrl_fatal_bus_integ_error */ + kTopDarjeelingAlertIdOtpCtrlFatalPrimOtpAlert = 8, /**< otp_ctrl_fatal_prim_otp_alert */ + kTopDarjeelingAlertIdOtpCtrlRecovPrimOtpAlert = 9, /**< otp_ctrl_recov_prim_otp_alert */ + kTopDarjeelingAlertIdLcCtrlFatalProgError = 10, /**< lc_ctrl_fatal_prog_error */ + kTopDarjeelingAlertIdLcCtrlFatalStateError = 11, /**< lc_ctrl_fatal_state_error */ + kTopDarjeelingAlertIdLcCtrlFatalBusIntegError = 12, /**< lc_ctrl_fatal_bus_integ_error */ + kTopDarjeelingAlertIdSpiHost0FatalFault = 13, /**< spi_host0_fatal_fault */ + kTopDarjeelingAlertIdPwrmgrAonFatalFault = 14, /**< pwrmgr_aon_fatal_fault */ + kTopDarjeelingAlertIdRstmgrAonFatalFault = 15, /**< rstmgr_aon_fatal_fault */ + kTopDarjeelingAlertIdRstmgrAonFatalCnstyFault = 16, /**< rstmgr_aon_fatal_cnsty_fault */ + kTopDarjeelingAlertIdClkmgrAonRecovFault = 17, /**< clkmgr_aon_recov_fault */ + kTopDarjeelingAlertIdClkmgrAonFatalFault = 18, /**< clkmgr_aon_fatal_fault */ + kTopDarjeelingAlertIdPinmuxAonFatalFault = 19, /**< pinmux_aon_fatal_fault */ + kTopDarjeelingAlertIdAonTimerAonFatalFault = 20, /**< aon_timer_aon_fatal_fault */ + kTopDarjeelingAlertIdSensorCtrlRecovAlert = 21, /**< sensor_ctrl_recov_alert */ + kTopDarjeelingAlertIdSensorCtrlFatalAlert = 22, /**< sensor_ctrl_fatal_alert */ + kTopDarjeelingAlertIdSocProxyFatalAlertIntg = 23, /**< soc_proxy_fatal_alert_intg */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal0 = 24, /**< soc_proxy_fatal_alert_external_0 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal1 = 25, /**< soc_proxy_fatal_alert_external_1 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal2 = 26, /**< soc_proxy_fatal_alert_external_2 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal3 = 27, /**< soc_proxy_fatal_alert_external_3 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal4 = 28, /**< soc_proxy_fatal_alert_external_4 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal5 = 29, /**< soc_proxy_fatal_alert_external_5 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal6 = 30, /**< soc_proxy_fatal_alert_external_6 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal7 = 31, /**< soc_proxy_fatal_alert_external_7 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal8 = 32, /**< soc_proxy_fatal_alert_external_8 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal9 = 33, /**< soc_proxy_fatal_alert_external_9 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal10 = 34, /**< soc_proxy_fatal_alert_external_10 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal11 = 35, /**< soc_proxy_fatal_alert_external_11 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal12 = 36, /**< soc_proxy_fatal_alert_external_12 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal13 = 37, /**< soc_proxy_fatal_alert_external_13 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal14 = 38, /**< soc_proxy_fatal_alert_external_14 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal15 = 39, /**< soc_proxy_fatal_alert_external_15 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal16 = 40, /**< soc_proxy_fatal_alert_external_16 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal17 = 41, /**< soc_proxy_fatal_alert_external_17 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal18 = 42, /**< soc_proxy_fatal_alert_external_18 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal19 = 43, /**< soc_proxy_fatal_alert_external_19 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal20 = 44, /**< soc_proxy_fatal_alert_external_20 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal21 = 45, /**< soc_proxy_fatal_alert_external_21 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal22 = 46, /**< soc_proxy_fatal_alert_external_22 */ + kTopDarjeelingAlertIdSocProxyFatalAlertExternal23 = 47, /**< soc_proxy_fatal_alert_external_23 */ + kTopDarjeelingAlertIdSocProxyRecovAlertExternal0 = 48, /**< soc_proxy_recov_alert_external_0 */ + kTopDarjeelingAlertIdSocProxyRecovAlertExternal1 = 49, /**< soc_proxy_recov_alert_external_1 */ + kTopDarjeelingAlertIdSocProxyRecovAlertExternal2 = 50, /**< soc_proxy_recov_alert_external_2 */ + kTopDarjeelingAlertIdSocProxyRecovAlertExternal3 = 51, /**< soc_proxy_recov_alert_external_3 */ + kTopDarjeelingAlertIdSramCtrlRetAonFatalError = 52, /**< sram_ctrl_ret_aon_fatal_error */ + kTopDarjeelingAlertIdRvDmFatalFault = 53, /**< rv_dm_fatal_fault */ + kTopDarjeelingAlertIdRvPlicFatalFault = 54, /**< rv_plic_fatal_fault */ + kTopDarjeelingAlertIdAesRecovCtrlUpdateErr = 55, /**< aes_recov_ctrl_update_err */ + kTopDarjeelingAlertIdAesFatalFault = 56, /**< aes_fatal_fault */ + kTopDarjeelingAlertIdHmacFatalFault = 57, /**< hmac_fatal_fault */ + kTopDarjeelingAlertIdKmacRecovOperationErr = 58, /**< kmac_recov_operation_err */ + kTopDarjeelingAlertIdKmacFatalFaultErr = 59, /**< kmac_fatal_fault_err */ + kTopDarjeelingAlertIdOtbnFatal = 60, /**< otbn_fatal */ + kTopDarjeelingAlertIdOtbnRecov = 61, /**< otbn_recov */ + kTopDarjeelingAlertIdKeymgrDpeRecovOperationErr = 62, /**< keymgr_dpe_recov_operation_err */ + kTopDarjeelingAlertIdKeymgrDpeFatalFaultErr = 63, /**< keymgr_dpe_fatal_fault_err */ + kTopDarjeelingAlertIdCsrngRecovAlert = 64, /**< csrng_recov_alert */ + kTopDarjeelingAlertIdCsrngFatalAlert = 65, /**< csrng_fatal_alert */ + kTopDarjeelingAlertIdEdn0RecovAlert = 66, /**< edn0_recov_alert */ + kTopDarjeelingAlertIdEdn0FatalAlert = 67, /**< edn0_fatal_alert */ + kTopDarjeelingAlertIdEdn1RecovAlert = 68, /**< edn1_recov_alert */ + kTopDarjeelingAlertIdEdn1FatalAlert = 69, /**< edn1_fatal_alert */ + kTopDarjeelingAlertIdSramCtrlMainFatalError = 70, /**< sram_ctrl_main_fatal_error */ + kTopDarjeelingAlertIdSramCtrlMboxFatalError = 71, /**< sram_ctrl_mbox_fatal_error */ + kTopDarjeelingAlertIdRomCtrl0Fatal = 72, /**< rom_ctrl0_fatal */ + kTopDarjeelingAlertIdRomCtrl1Fatal = 73, /**< rom_ctrl1_fatal */ + kTopDarjeelingAlertIdDmaFatalFault = 74, /**< dma_fatal_fault */ + kTopDarjeelingAlertIdMbx0FatalFault = 75, /**< mbx0_fatal_fault */ + kTopDarjeelingAlertIdMbx0RecovFault = 76, /**< mbx0_recov_fault */ + kTopDarjeelingAlertIdMbx1FatalFault = 77, /**< mbx1_fatal_fault */ + kTopDarjeelingAlertIdMbx1RecovFault = 78, /**< mbx1_recov_fault */ + kTopDarjeelingAlertIdMbx2FatalFault = 79, /**< mbx2_fatal_fault */ + kTopDarjeelingAlertIdMbx2RecovFault = 80, /**< mbx2_recov_fault */ + kTopDarjeelingAlertIdMbx3FatalFault = 81, /**< mbx3_fatal_fault */ + kTopDarjeelingAlertIdMbx3RecovFault = 82, /**< mbx3_recov_fault */ + kTopDarjeelingAlertIdMbx4FatalFault = 83, /**< mbx4_fatal_fault */ + kTopDarjeelingAlertIdMbx4RecovFault = 84, /**< mbx4_recov_fault */ + kTopDarjeelingAlertIdMbx5FatalFault = 85, /**< mbx5_fatal_fault */ + kTopDarjeelingAlertIdMbx5RecovFault = 86, /**< mbx5_recov_fault */ + kTopDarjeelingAlertIdMbx6FatalFault = 87, /**< mbx6_fatal_fault */ + kTopDarjeelingAlertIdMbx6RecovFault = 88, /**< mbx6_recov_fault */ + kTopDarjeelingAlertIdMbxJtagFatalFault = 89, /**< mbx_jtag_fatal_fault */ + kTopDarjeelingAlertIdMbxJtagRecovFault = 90, /**< mbx_jtag_recov_fault */ + kTopDarjeelingAlertIdMbxPcie0FatalFault = 91, /**< mbx_pcie0_fatal_fault */ + kTopDarjeelingAlertIdMbxPcie0RecovFault = 92, /**< mbx_pcie0_recov_fault */ + kTopDarjeelingAlertIdMbxPcie1FatalFault = 93, /**< mbx_pcie1_fatal_fault */ + kTopDarjeelingAlertIdMbxPcie1RecovFault = 94, /**< mbx_pcie1_recov_fault */ + kTopDarjeelingAlertIdRvCoreIbexFatalSwErr = 95, /**< rv_core_ibex_fatal_sw_err */ + kTopDarjeelingAlertIdRvCoreIbexRecovSwErr = 96, /**< rv_core_ibex_recov_sw_err */ + kTopDarjeelingAlertIdRvCoreIbexFatalHwErr = 97, /**< rv_core_ibex_fatal_hw_err */ + kTopDarjeelingAlertIdRvCoreIbexRecovHwErr = 98, /**< rv_core_ibex_recov_hw_err */ + kTopDarjeelingAlertIdLast = 98, /**< \internal The Last Valid Alert ID. */ +} top_darjeeling_alert_id_t; + +/** + * Alert Handler Alert Source to Peripheral Map + * + * This array is a mapping from `top_darjeeling_alert_id_t` to + * `top_darjeeling_alert_peripheral_t`. + */ +extern const top_darjeeling_alert_peripheral_t + top_darjeeling_alert_for_peripheral[99]; + +#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2 + +// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1} +// 0 and 1 are tied to value 0 and 1 +#define NUM_MIO_PADS 12 +#define NUM_DIO_PADS 73 + +#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3 + +/** + * Pinmux Peripheral Input. + */ +typedef enum top_darjeeling_pinmux_peripheral_in { + kTopDarjeelingPinmuxPeripheralInSocProxySocGpi12 = 0, /**< Peripheral Input 0 */ + kTopDarjeelingPinmuxPeripheralInSocProxySocGpi13 = 1, /**< Peripheral Input 1 */ + kTopDarjeelingPinmuxPeripheralInSocProxySocGpi14 = 2, /**< Peripheral Input 2 */ + kTopDarjeelingPinmuxPeripheralInSocProxySocGpi15 = 3, /**< Peripheral Input 3 */ + kTopDarjeelingPinmuxPeripheralInLast = 3, /**< \internal Last valid peripheral input */ +} top_darjeeling_pinmux_peripheral_in_t; + +/** + * Pinmux MIO Input Selector. + */ +typedef enum top_darjeeling_pinmux_insel { + kTopDarjeelingPinmuxInselConstantZero = 0, /**< Tie constantly to zero */ + kTopDarjeelingPinmuxInselConstantOne = 1, /**< Tie constantly to one */ + kTopDarjeelingPinmuxInselMio0 = 2, /**< MIO Pad 0 */ + kTopDarjeelingPinmuxInselMio1 = 3, /**< MIO Pad 1 */ + kTopDarjeelingPinmuxInselMio2 = 4, /**< MIO Pad 2 */ + kTopDarjeelingPinmuxInselMio3 = 5, /**< MIO Pad 3 */ + kTopDarjeelingPinmuxInselMio4 = 6, /**< MIO Pad 4 */ + kTopDarjeelingPinmuxInselMio5 = 7, /**< MIO Pad 5 */ + kTopDarjeelingPinmuxInselMio6 = 8, /**< MIO Pad 6 */ + kTopDarjeelingPinmuxInselMio7 = 9, /**< MIO Pad 7 */ + kTopDarjeelingPinmuxInselMio8 = 10, /**< MIO Pad 8 */ + kTopDarjeelingPinmuxInselMio9 = 11, /**< MIO Pad 9 */ + kTopDarjeelingPinmuxInselMio10 = 12, /**< MIO Pad 10 */ + kTopDarjeelingPinmuxInselMio11 = 13, /**< MIO Pad 11 */ + kTopDarjeelingPinmuxInselLast = 13, /**< \internal Last valid insel value */ +} top_darjeeling_pinmux_insel_t; + +/** + * Pinmux MIO Output. + */ +typedef enum top_darjeeling_pinmux_mio_out { + kTopDarjeelingPinmuxMioOutMio0 = 0, /**< MIO Pad 0 */ + kTopDarjeelingPinmuxMioOutMio1 = 1, /**< MIO Pad 1 */ + kTopDarjeelingPinmuxMioOutMio2 = 2, /**< MIO Pad 2 */ + kTopDarjeelingPinmuxMioOutMio3 = 3, /**< MIO Pad 3 */ + kTopDarjeelingPinmuxMioOutMio4 = 4, /**< MIO Pad 4 */ + kTopDarjeelingPinmuxMioOutMio5 = 5, /**< MIO Pad 5 */ + kTopDarjeelingPinmuxMioOutMio6 = 6, /**< MIO Pad 6 */ + kTopDarjeelingPinmuxMioOutMio7 = 7, /**< MIO Pad 7 */ + kTopDarjeelingPinmuxMioOutMio8 = 8, /**< MIO Pad 8 */ + kTopDarjeelingPinmuxMioOutMio9 = 9, /**< MIO Pad 9 */ + kTopDarjeelingPinmuxMioOutMio10 = 10, /**< MIO Pad 10 */ + kTopDarjeelingPinmuxMioOutMio11 = 11, /**< MIO Pad 11 */ + kTopDarjeelingPinmuxMioOutLast = 11, /**< \internal Last valid mio output */ +} top_darjeeling_pinmux_mio_out_t; + +/** + * Pinmux Peripheral Output Selector. + */ +typedef enum top_darjeeling_pinmux_outsel { + kTopDarjeelingPinmuxOutselConstantZero = 0, /**< Tie constantly to zero */ + kTopDarjeelingPinmuxOutselConstantOne = 1, /**< Tie constantly to one */ + kTopDarjeelingPinmuxOutselConstantHighZ = 2, /**< Tie constantly to high-Z */ + kTopDarjeelingPinmuxOutselSocProxySocGpo12 = 3, /**< Peripheral Output 0 */ + kTopDarjeelingPinmuxOutselSocProxySocGpo13 = 4, /**< Peripheral Output 1 */ + kTopDarjeelingPinmuxOutselSocProxySocGpo14 = 5, /**< Peripheral Output 2 */ + kTopDarjeelingPinmuxOutselSocProxySocGpo15 = 6, /**< Peripheral Output 3 */ + kTopDarjeelingPinmuxOutselOtpCtrlTest0 = 7, /**< Peripheral Output 4 */ + kTopDarjeelingPinmuxOutselLast = 7, /**< \internal Last valid outsel value */ +} top_darjeeling_pinmux_outsel_t; + +/** + * Dedicated Pad Selects + */ +typedef enum top_darjeeling_direct_pads { + kTopDarjeelingDirectPadsSpiHost0Sd0 = 0, /**< */ + kTopDarjeelingDirectPadsSpiHost0Sd1 = 1, /**< */ + kTopDarjeelingDirectPadsSpiHost0Sd2 = 2, /**< */ + kTopDarjeelingDirectPadsSpiHost0Sd3 = 3, /**< */ + kTopDarjeelingDirectPadsSpiDeviceSd0 = 4, /**< */ + kTopDarjeelingDirectPadsSpiDeviceSd1 = 5, /**< */ + kTopDarjeelingDirectPadsSpiDeviceSd2 = 6, /**< */ + kTopDarjeelingDirectPadsSpiDeviceSd3 = 7, /**< */ + kTopDarjeelingDirectPadsI2c0Scl = 8, /**< */ + kTopDarjeelingDirectPadsI2c0Sda = 9, /**< */ + kTopDarjeelingDirectPadsGpioGpio0 = 10, /**< */ + kTopDarjeelingDirectPadsGpioGpio1 = 11, /**< */ + kTopDarjeelingDirectPadsGpioGpio2 = 12, /**< */ + kTopDarjeelingDirectPadsGpioGpio3 = 13, /**< */ + kTopDarjeelingDirectPadsGpioGpio4 = 14, /**< */ + kTopDarjeelingDirectPadsGpioGpio5 = 15, /**< */ + kTopDarjeelingDirectPadsGpioGpio6 = 16, /**< */ + kTopDarjeelingDirectPadsGpioGpio7 = 17, /**< */ + kTopDarjeelingDirectPadsGpioGpio8 = 18, /**< */ + kTopDarjeelingDirectPadsGpioGpio9 = 19, /**< */ + kTopDarjeelingDirectPadsGpioGpio10 = 20, /**< */ + kTopDarjeelingDirectPadsGpioGpio11 = 21, /**< */ + kTopDarjeelingDirectPadsGpioGpio12 = 22, /**< */ + kTopDarjeelingDirectPadsGpioGpio13 = 23, /**< */ + kTopDarjeelingDirectPadsGpioGpio14 = 24, /**< */ + kTopDarjeelingDirectPadsGpioGpio15 = 25, /**< */ + kTopDarjeelingDirectPadsGpioGpio16 = 26, /**< */ + kTopDarjeelingDirectPadsGpioGpio17 = 27, /**< */ + kTopDarjeelingDirectPadsGpioGpio18 = 28, /**< */ + kTopDarjeelingDirectPadsGpioGpio19 = 29, /**< */ + kTopDarjeelingDirectPadsGpioGpio20 = 30, /**< */ + kTopDarjeelingDirectPadsGpioGpio21 = 31, /**< */ + kTopDarjeelingDirectPadsGpioGpio22 = 32, /**< */ + kTopDarjeelingDirectPadsGpioGpio23 = 33, /**< */ + kTopDarjeelingDirectPadsGpioGpio24 = 34, /**< */ + kTopDarjeelingDirectPadsGpioGpio25 = 35, /**< */ + kTopDarjeelingDirectPadsGpioGpio26 = 36, /**< */ + kTopDarjeelingDirectPadsGpioGpio27 = 37, /**< */ + kTopDarjeelingDirectPadsGpioGpio28 = 38, /**< */ + kTopDarjeelingDirectPadsGpioGpio29 = 39, /**< */ + kTopDarjeelingDirectPadsGpioGpio30 = 40, /**< */ + kTopDarjeelingDirectPadsGpioGpio31 = 41, /**< */ + kTopDarjeelingDirectPadsSpiDeviceSck = 42, /**< */ + kTopDarjeelingDirectPadsSpiDeviceCsb = 43, /**< */ + kTopDarjeelingDirectPadsSpiDeviceTpmCsb = 44, /**< */ + kTopDarjeelingDirectPadsUart0Rx = 45, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpi0 = 46, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpi1 = 47, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpi2 = 48, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpi3 = 49, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpi4 = 50, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpi5 = 51, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpi6 = 52, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpi7 = 53, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpi8 = 54, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpi9 = 55, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpi10 = 56, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpi11 = 57, /**< */ + kTopDarjeelingDirectPadsSpiHost0Sck = 58, /**< */ + kTopDarjeelingDirectPadsSpiHost0Csb = 59, /**< */ + kTopDarjeelingDirectPadsUart0Tx = 60, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpo0 = 61, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpo1 = 62, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpo2 = 63, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpo3 = 64, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpo4 = 65, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpo5 = 66, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpo6 = 67, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpo7 = 68, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpo8 = 69, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpo9 = 70, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpo10 = 71, /**< */ + kTopDarjeelingDirectPadsSocProxySocGpo11 = 72, /**< */ + kTopDarjeelingDirectPadsLast = 72, /**< \internal Last valid direct pad */ +} top_darjeeling_direct_pads_t; + +/** + * Muxed Pad Selects + */ +typedef enum top_darjeeling_muxed_pads { + kTopDarjeelingMuxedPadsMio0 = 0, /**< */ + kTopDarjeelingMuxedPadsMio1 = 1, /**< */ + kTopDarjeelingMuxedPadsMio2 = 2, /**< */ + kTopDarjeelingMuxedPadsMio3 = 3, /**< */ + kTopDarjeelingMuxedPadsMio4 = 4, /**< */ + kTopDarjeelingMuxedPadsMio5 = 5, /**< */ + kTopDarjeelingMuxedPadsMio6 = 6, /**< */ + kTopDarjeelingMuxedPadsMio7 = 7, /**< */ + kTopDarjeelingMuxedPadsMio8 = 8, /**< */ + kTopDarjeelingMuxedPadsMio9 = 9, /**< */ + kTopDarjeelingMuxedPadsMio10 = 10, /**< */ + kTopDarjeelingMuxedPadsMio11 = 11, /**< */ + kTopDarjeelingMuxedPadsLast = 11, /**< \internal Last valid muxed pad */ +} top_darjeeling_muxed_pads_t; + +/** + * Power Manager Wakeup Signals + */ +typedef enum top_darjeeling_power_manager_wake_ups { + kTopDarjeelingPowerManagerWakeUpsPinmuxAonPinWkupReq = 0, /**< */ + kTopDarjeelingPowerManagerWakeUpsPinmuxAonUsbWkupReq = 1, /**< */ + kTopDarjeelingPowerManagerWakeUpsAonTimerAonWkupReq = 2, /**< */ + kTopDarjeelingPowerManagerWakeUpsSensorCtrlWkupReq = 3, /**< */ + kTopDarjeelingPowerManagerWakeUpsSocProxyWkupInternalReq = 4, /**< */ + kTopDarjeelingPowerManagerWakeUpsSocProxyWkupExternalReq = 5, /**< */ + kTopDarjeelingPowerManagerWakeUpsLast = 5, /**< \internal Last valid pwrmgr wakeup signal */ +} top_darjeeling_power_manager_wake_ups_t; + +/** + * Reset Manager Software Controlled Resets + */ +typedef enum top_darjeeling_reset_manager_sw_resets { + kTopDarjeelingResetManagerSwResetsSpiDevice = 0, /**< */ + kTopDarjeelingResetManagerSwResetsSpiHost0 = 1, /**< */ + kTopDarjeelingResetManagerSwResetsI2c0 = 2, /**< */ + kTopDarjeelingResetManagerSwResetsLast = 2, /**< \internal Last valid rstmgr software reset request */ +} top_darjeeling_reset_manager_sw_resets_t; + +/** + * Power Manager Reset Request Signals + */ +typedef enum top_darjeeling_power_manager_reset_requests { + kTopDarjeelingPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 0, /**< */ + kTopDarjeelingPowerManagerResetRequestsSocProxyRstReqExternal = 1, /**< */ + kTopDarjeelingPowerManagerResetRequestsLast = 1, /**< \internal Last valid pwrmgr reset_request signal */ +} top_darjeeling_power_manager_reset_requests_t; + +/** + * Clock Manager Software-Controlled ("Gated") Clocks. + * + * The Software has full control over these clocks. + */ +typedef enum top_darjeeling_gateable_clocks { + kTopDarjeelingGateableClocksIoDiv4Peri = 0, /**< Clock clk_io_div4_peri in group peri */ + kTopDarjeelingGateableClocksIoDiv2Peri = 1, /**< Clock clk_io_div2_peri in group peri */ + kTopDarjeelingGateableClocksUsbPeri = 2, /**< Clock clk_usb_peri in group peri */ + kTopDarjeelingGateableClocksLast = 2, /**< \internal Last Valid Gateable Clock */ +} top_darjeeling_gateable_clocks_t; + +/** + * Clock Manager Software-Hinted Clocks. + * + * The Software has partial control over these clocks. It can ask them to stop, + * but the clock manager is in control of whether the clock actually is stopped. + */ +typedef enum top_darjeeling_hintable_clocks { + kTopDarjeelingHintableClocksMainAes = 0, /**< Clock clk_main_aes in group trans */ + kTopDarjeelingHintableClocksMainHmac = 1, /**< Clock clk_main_hmac in group trans */ + kTopDarjeelingHintableClocksMainKmac = 2, /**< Clock clk_main_kmac in group trans */ + kTopDarjeelingHintableClocksMainOtbn = 3, /**< Clock clk_main_otbn in group trans */ + kTopDarjeelingHintableClocksLast = 3, /**< \internal Last Valid Hintable Clock */ +} top_darjeeling_hintable_clocks_t; + +/** + * MMIO Region + * + * MMIO region excludes any memory that is separate from the module + * configuration space, i.e. ROM, main SRAM, and mbx SRAM are excluded but + * retention SRAM or spi_device are included. + */ +#define TOP_DARJEELING_MMIO_BASE_ADDR 0x21100000u +#define TOP_DARJEELING_MMIO_SIZE_BYTES 0xF501000u + +// Header Extern Guard +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_H_ diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h b/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h new file mode 100644 index 0000000000000..668e3aa237a42 --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h @@ -0,0 +1,983 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_MEMORY_H_ +#define OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_MEMORY_H_ + +/** + * @file + * @brief Assembler-only Top-Specific Definitions. + * + * This file contains preprocessor definitions for use within assembly code. + * + * These are not shared with C/C++ code because these are only allowed to be + * preprocessor definitions, no data or type declarations are allowed. The + * assembler is also stricter about literals (not allowing suffixes for + * signed/unsigned which are sensible to use for unsigned values in C/C++). + */ + +// Include guard for assembler +#ifdef __ASSEMBLER__ + + +/** + * Memory base for soc_proxy_ctn in top darjeeling. + */ +#define TOP_DARJEELING_CTN_BASE_ADDR 0x40000000 + +/** + * Memory size for soc_proxy_ctn in top darjeeling. + */ +#define TOP_DARJEELING_CTN_SIZE_BYTES 0x40000000 + +/** + * Memory base for sram_ctrl_ret_aon_ram_ret_aon in top darjeeling. + */ +#define TOP_DARJEELING_RAM_RET_AON_BASE_ADDR 0x30600000 + +/** + * Memory size for sram_ctrl_ret_aon_ram_ret_aon in top darjeeling. + */ +#define TOP_DARJEELING_RAM_RET_AON_SIZE_BYTES 0x1000 + +/** + * Memory base for sram_ctrl_main_ram_main in top darjeeling. + */ +#define TOP_DARJEELING_RAM_MAIN_BASE_ADDR 0x10000000 + +/** + * Memory size for sram_ctrl_main_ram_main in top darjeeling. + */ +#define TOP_DARJEELING_RAM_MAIN_SIZE_BYTES 0x10000 + +/** + * Memory base for sram_ctrl_mbox_ram_mbox in top darjeeling. + */ +#define TOP_DARJEELING_RAM_MBOX_BASE_ADDR 0x11000000 + +/** + * Memory size for sram_ctrl_mbox_ram_mbox in top darjeeling. + */ +#define TOP_DARJEELING_RAM_MBOX_SIZE_BYTES 0x1000 + +/** + * Memory base for rom_ctrl0_rom0 in top darjeeling. + */ +#define TOP_DARJEELING_ROM0_BASE_ADDR 0x00008000 + +/** + * Memory size for rom_ctrl0_rom0 in top darjeeling. + */ +#define TOP_DARJEELING_ROM0_SIZE_BYTES 0x8000 + +/** + * Memory base for rom_ctrl1_rom1 in top darjeeling. + */ +#define TOP_DARJEELING_ROM1_BASE_ADDR 0x00020000 + +/** + * Memory size for rom_ctrl1_rom1 in top darjeeling. + */ +#define TOP_DARJEELING_ROM1_SIZE_BYTES 0x10000 + + + +/** + * Peripheral base address for uart0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_UART0_BASE_ADDR 0x30010000 + +/** + * Peripheral size for uart0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_UART0_BASE_ADDR and + * `TOP_DARJEELING_UART0_BASE_ADDR + TOP_DARJEELING_UART0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_UART0_SIZE_BYTES 0x40 +/** + * Peripheral base address for gpio in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_GPIO_BASE_ADDR 0x30000000 + +/** + * Peripheral size for gpio in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_GPIO_BASE_ADDR and + * `TOP_DARJEELING_GPIO_BASE_ADDR + TOP_DARJEELING_GPIO_SIZE_BYTES`. + */ +#define TOP_DARJEELING_GPIO_SIZE_BYTES 0x80 +/** + * Peripheral base address for spi_device in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SPI_DEVICE_BASE_ADDR 0x30310000 + +/** + * Peripheral size for spi_device in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SPI_DEVICE_BASE_ADDR and + * `TOP_DARJEELING_SPI_DEVICE_BASE_ADDR + TOP_DARJEELING_SPI_DEVICE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SPI_DEVICE_SIZE_BYTES 0x2000 +/** + * Peripheral base address for i2c0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_I2C0_BASE_ADDR 0x30080000 + +/** + * Peripheral size for i2c0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_I2C0_BASE_ADDR and + * `TOP_DARJEELING_I2C0_BASE_ADDR + TOP_DARJEELING_I2C0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_I2C0_SIZE_BYTES 0x80 +/** + * Peripheral base address for rv_timer in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RV_TIMER_BASE_ADDR 0x30100000 + +/** + * Peripheral size for rv_timer in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RV_TIMER_BASE_ADDR and + * `TOP_DARJEELING_RV_TIMER_BASE_ADDR + TOP_DARJEELING_RV_TIMER_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RV_TIMER_SIZE_BYTES 0x200 +/** + * Peripheral base address for core device on otp_ctrl in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR 0x30130000 + +/** + * Peripheral size for core device on otp_ctrl in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR and + * `TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR + TOP_DARJEELING_OTP_CTRL_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_OTP_CTRL_CORE_SIZE_BYTES 0x1000 +/** + * Peripheral base address for prim device on otp_ctrl in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_OTP_CTRL_PRIM_BASE_ADDR 0x30138000 + +/** + * Peripheral size for prim device on otp_ctrl in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_OTP_CTRL_PRIM_BASE_ADDR and + * `TOP_DARJEELING_OTP_CTRL_PRIM_BASE_ADDR + TOP_DARJEELING_OTP_CTRL_PRIM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_OTP_CTRL_PRIM_SIZE_BYTES 0x20 +/** + * Peripheral base address for regs device on lc_ctrl in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR 0x30140000 + +/** + * Peripheral size for regs device on lc_ctrl in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR and + * `TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR + TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES 0x100 +/** + * Peripheral base address for alert_handler in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR 0x30150000 + +/** + * Peripheral size for alert_handler in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR and + * `TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR + TOP_DARJEELING_ALERT_HANDLER_SIZE_BYTES`. + */ +#define TOP_DARJEELING_ALERT_HANDLER_SIZE_BYTES 0x800 +/** + * Peripheral base address for spi_host0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SPI_HOST0_BASE_ADDR 0x30300000 + +/** + * Peripheral size for spi_host0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SPI_HOST0_BASE_ADDR and + * `TOP_DARJEELING_SPI_HOST0_BASE_ADDR + TOP_DARJEELING_SPI_HOST0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SPI_HOST0_SIZE_BYTES 0x40 +/** + * Peripheral base address for pwrmgr_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_PWRMGR_AON_BASE_ADDR 0x30400000 + +/** + * Peripheral size for pwrmgr_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_PWRMGR_AON_BASE_ADDR and + * `TOP_DARJEELING_PWRMGR_AON_BASE_ADDR + TOP_DARJEELING_PWRMGR_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_PWRMGR_AON_SIZE_BYTES 0x80 +/** + * Peripheral base address for rstmgr_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RSTMGR_AON_BASE_ADDR 0x30410000 + +/** + * Peripheral size for rstmgr_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RSTMGR_AON_BASE_ADDR and + * `TOP_DARJEELING_RSTMGR_AON_BASE_ADDR + TOP_DARJEELING_RSTMGR_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RSTMGR_AON_SIZE_BYTES 0x80 +/** + * Peripheral base address for clkmgr_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_CLKMGR_AON_BASE_ADDR 0x30420000 + +/** + * Peripheral size for clkmgr_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_CLKMGR_AON_BASE_ADDR and + * `TOP_DARJEELING_CLKMGR_AON_BASE_ADDR + TOP_DARJEELING_CLKMGR_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_CLKMGR_AON_SIZE_BYTES 0x80 +/** + * Peripheral base address for pinmux_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_PINMUX_AON_BASE_ADDR 0x30460000 + +/** + * Peripheral size for pinmux_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_PINMUX_AON_BASE_ADDR and + * `TOP_DARJEELING_PINMUX_AON_BASE_ADDR + TOP_DARJEELING_PINMUX_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_PINMUX_AON_SIZE_BYTES 0x800 +/** + * Peripheral base address for aon_timer_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR 0x30470000 + +/** + * Peripheral size for aon_timer_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR and + * `TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR + TOP_DARJEELING_AON_TIMER_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_AON_TIMER_AON_SIZE_BYTES 0x40 +/** + * Peripheral base address for ast in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_AST_BASE_ADDR 0x30480000 + +/** + * Peripheral size for ast in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_AST_BASE_ADDR and + * `TOP_DARJEELING_AST_BASE_ADDR + TOP_DARJEELING_AST_SIZE_BYTES`. + */ +#define TOP_DARJEELING_AST_SIZE_BYTES 0x400 +/** + * Peripheral base address for sensor_ctrl in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SENSOR_CTRL_BASE_ADDR 0x30020000 + +/** + * Peripheral size for sensor_ctrl in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SENSOR_CTRL_BASE_ADDR and + * `TOP_DARJEELING_SENSOR_CTRL_BASE_ADDR + TOP_DARJEELING_SENSOR_CTRL_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SENSOR_CTRL_SIZE_BYTES 0x40 +/** + * Peripheral base address for core device on soc_proxy in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR 0x22030000 + +/** + * Peripheral size for core device on soc_proxy in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR and + * `TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR + TOP_DARJEELING_SOC_PROXY_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SOC_PROXY_CORE_SIZE_BYTES 0x10 +/** + * Peripheral base address for ctn device on soc_proxy in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR 0x40000000 + +/** + * Peripheral size for ctn device on soc_proxy in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR and + * `TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR + TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x40000000 +/** + * Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x30500000 + +/** + * Peripheral size for regs device on sram_ctrl_ret_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and + * `TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40 +/** + * Peripheral base address for ram device on sram_ctrl_ret_aon in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x30600000 + +/** + * Peripheral size for ram device on sram_ctrl_ret_aon in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and + * `TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000 +/** + * Peripheral base address for regs device on rv_dm in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RV_DM_REGS_BASE_ADDR 0x21200000 + +/** + * Peripheral size for regs device on rv_dm in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RV_DM_REGS_BASE_ADDR and + * `TOP_DARJEELING_RV_DM_REGS_BASE_ADDR + TOP_DARJEELING_RV_DM_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RV_DM_REGS_SIZE_BYTES 0x10 +/** + * Peripheral base address for mem device on rv_dm in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RV_DM_MEM_BASE_ADDR 0x40000 + +/** + * Peripheral size for mem device on rv_dm in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RV_DM_MEM_BASE_ADDR and + * `TOP_DARJEELING_RV_DM_MEM_BASE_ADDR + TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES 0x1000 +/** + * Peripheral base address for rv_plic in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RV_PLIC_BASE_ADDR 0x28000000 + +/** + * Peripheral size for rv_plic in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RV_PLIC_BASE_ADDR and + * `TOP_DARJEELING_RV_PLIC_BASE_ADDR + TOP_DARJEELING_RV_PLIC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RV_PLIC_SIZE_BYTES 0x8000000 +/** + * Peripheral base address for aes in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_AES_BASE_ADDR 0x21100000 + +/** + * Peripheral size for aes in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_AES_BASE_ADDR and + * `TOP_DARJEELING_AES_BASE_ADDR + TOP_DARJEELING_AES_SIZE_BYTES`. + */ +#define TOP_DARJEELING_AES_SIZE_BYTES 0x100 +/** + * Peripheral base address for hmac in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_HMAC_BASE_ADDR 0x21110000 + +/** + * Peripheral size for hmac in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_HMAC_BASE_ADDR and + * `TOP_DARJEELING_HMAC_BASE_ADDR + TOP_DARJEELING_HMAC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_HMAC_SIZE_BYTES 0x2000 +/** + * Peripheral base address for kmac in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_KMAC_BASE_ADDR 0x21120000 + +/** + * Peripheral size for kmac in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_KMAC_BASE_ADDR and + * `TOP_DARJEELING_KMAC_BASE_ADDR + TOP_DARJEELING_KMAC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_KMAC_SIZE_BYTES 0x1000 +/** + * Peripheral base address for otbn in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_OTBN_BASE_ADDR 0x21130000 + +/** + * Peripheral size for otbn in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_OTBN_BASE_ADDR and + * `TOP_DARJEELING_OTBN_BASE_ADDR + TOP_DARJEELING_OTBN_SIZE_BYTES`. + */ +#define TOP_DARJEELING_OTBN_SIZE_BYTES 0x10000 +/** + * Peripheral base address for keymgr_dpe in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR 0x21140000 + +/** + * Peripheral size for keymgr_dpe in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR and + * `TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR + TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES 0x100 +/** + * Peripheral base address for csrng in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_CSRNG_BASE_ADDR 0x21150000 + +/** + * Peripheral size for csrng in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_CSRNG_BASE_ADDR and + * `TOP_DARJEELING_CSRNG_BASE_ADDR + TOP_DARJEELING_CSRNG_SIZE_BYTES`. + */ +#define TOP_DARJEELING_CSRNG_SIZE_BYTES 0x80 +/** + * Peripheral base address for edn0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_EDN0_BASE_ADDR 0x21170000 + +/** + * Peripheral size for edn0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_EDN0_BASE_ADDR and + * `TOP_DARJEELING_EDN0_BASE_ADDR + TOP_DARJEELING_EDN0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_EDN0_SIZE_BYTES 0x80 +/** + * Peripheral base address for edn1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_EDN1_BASE_ADDR 0x21180000 + +/** + * Peripheral size for edn1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_EDN1_BASE_ADDR and + * `TOP_DARJEELING_EDN1_BASE_ADDR + TOP_DARJEELING_EDN1_SIZE_BYTES`. + */ +#define TOP_DARJEELING_EDN1_SIZE_BYTES 0x80 +/** + * Peripheral base address for regs device on sram_ctrl_main in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x211C0000 + +/** + * Peripheral size for regs device on sram_ctrl_main in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR and + * `TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40 +/** + * Peripheral base address for ram device on sram_ctrl_main in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000 + +/** + * Peripheral size for ram device on sram_ctrl_main in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR and + * `TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x10000 +/** + * Peripheral base address for regs device on sram_ctrl_mbox in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR 0x211D0000 + +/** + * Peripheral size for regs device on sram_ctrl_mbox in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR and + * `TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_SIZE_BYTES 0x40 +/** + * Peripheral base address for ram device on sram_ctrl_mbox in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR 0x11000000 + +/** + * Peripheral size for ram device on sram_ctrl_mbox in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR and + * `TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR + TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_SIZE_BYTES 0x1000 +/** + * Peripheral base address for regs device on rom_ctrl0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR 0x211E0000 + +/** + * Peripheral size for regs device on rom_ctrl0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR and + * `TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR + TOP_DARJEELING_ROM_CTRL0_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_ROM_CTRL0_REGS_SIZE_BYTES 0x80 +/** + * Peripheral base address for rom device on rom_ctrl0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR 0x8000 + +/** + * Peripheral size for rom device on rom_ctrl0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR and + * `TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR + TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES 0x8000 +/** + * Peripheral base address for regs device on rom_ctrl1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR 0x211E1000 + +/** + * Peripheral size for regs device on rom_ctrl1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR and + * `TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR + TOP_DARJEELING_ROM_CTRL1_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_ROM_CTRL1_REGS_SIZE_BYTES 0x80 +/** + * Peripheral base address for rom device on rom_ctrl1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR 0x20000 + +/** + * Peripheral size for rom device on rom_ctrl1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR and + * `TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR + TOP_DARJEELING_ROM_CTRL1_ROM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_ROM_CTRL1_ROM_SIZE_BYTES 0x10000 +/** + * Peripheral base address for dma in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_DMA_BASE_ADDR 0x22010000 + +/** + * Peripheral size for dma in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_DMA_BASE_ADDR and + * `TOP_DARJEELING_DMA_BASE_ADDR + TOP_DARJEELING_DMA_SIZE_BYTES`. + */ +#define TOP_DARJEELING_DMA_SIZE_BYTES 0x200 +/** + * Peripheral base address for core device on mbx0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX0_CORE_BASE_ADDR 0x22000000 + +/** + * Peripheral size for core device on mbx0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX0_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX0_CORE_BASE_ADDR + TOP_DARJEELING_MBX0_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX0_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX1_CORE_BASE_ADDR 0x22000100 + +/** + * Peripheral size for core device on mbx1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX1_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX1_CORE_BASE_ADDR + TOP_DARJEELING_MBX1_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX1_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx2 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX2_CORE_BASE_ADDR 0x22000200 + +/** + * Peripheral size for core device on mbx2 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX2_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX2_CORE_BASE_ADDR + TOP_DARJEELING_MBX2_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX2_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx3 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX3_CORE_BASE_ADDR 0x22000300 + +/** + * Peripheral size for core device on mbx3 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX3_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX3_CORE_BASE_ADDR + TOP_DARJEELING_MBX3_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX3_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx4 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX4_CORE_BASE_ADDR 0x22000400 + +/** + * Peripheral size for core device on mbx4 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX4_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX4_CORE_BASE_ADDR + TOP_DARJEELING_MBX4_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX4_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx5 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX5_CORE_BASE_ADDR 0x22000500 + +/** + * Peripheral size for core device on mbx5 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX5_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX5_CORE_BASE_ADDR + TOP_DARJEELING_MBX5_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX5_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx6 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX6_CORE_BASE_ADDR 0x22000600 + +/** + * Peripheral size for core device on mbx6 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX6_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX6_CORE_BASE_ADDR + TOP_DARJEELING_MBX6_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX6_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx_jtag in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR 0x22000800 + +/** + * Peripheral size for core device on mbx_jtag in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx_pcie0 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR 0x22040000 + +/** + * Peripheral size for core device on mbx_pcie0 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx_pcie1 in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR 0x22040100 + +/** + * Peripheral size for core device on mbx_pcie1 in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR and + * `TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR + TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for cfg device on rv_core_ibex in top darjeeling. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR 0x211F0000 + +/** + * Peripheral size for cfg device on rv_core_ibex in top darjeeling. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR and + * `TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES`. + */ +#define TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100 + +/** + * MMIO Region + * + * MMIO region excludes any memory that is separate from the module + * configuration space, i.e. ROM, main SRAM, and mbx SRAM are excluded but + * retention SRAM or spi_device are included. + */ +#define TOP_DARJEELING_MMIO_BASE_ADDR 0x21100000 +#define TOP_DARJEELING_MMIO_SIZE_BYTES 0xF501000 + +#endif // __ASSEMBLER__ + +#endif // OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_MEMORY_H_ diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld b/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld new file mode 100644 index 0000000000000..731c6ad3ab18c --- /dev/null +++ b/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld @@ -0,0 +1,58 @@ +/* Copyright lowRISC contributors (OpenTitan project). */ +/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ +/* SPDX-License-Identifier: Apache-2.0 */ + +/** + * Partial linker script for chip memory configuration. + * rom_ext_virtual and owner_virtual are address windows that provide a fixed translation + * address for whichever half of the flash contains the corresponding boot stage. + */ +MEMORY { + ctn(rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000 + ram_ret_aon(rwx) : ORIGIN = 0x30600000, LENGTH = 0x1000 + ram_main(rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000 + ram_mbox(rwx) : ORIGIN = 0x11000000, LENGTH = 0x1000 + rom0(rx) : ORIGIN = 0x00008000, LENGTH = 0x8000 + rom1(rx) : ORIGIN = 0x00020000, LENGTH = 0x10000 + rom_ext_virtual(rx) : ORIGIN = 0x90000000, LENGTH = None + owner_virtual(rx) : ORIGIN = 0xa0000000, LENGTH = None +} + +/** + * Exception frame at the top of main SRAM + */ +_exception_frame_size = 128; +_exception_frame_end = ORIGIN(ram_main) + LENGTH(ram_main); +_exception_frame_start = _exception_frame_end - _exception_frame_size; + + +/** + * Stack just below the exception frame. + */ +_stack_size = 16384 - _exception_frame_size; +_stack_end = _exception_frame_start; +_stack_start = _stack_end - _stack_size; + +/** + * Size of the `.static_critical` section at the bottom of the main SRAM (in + * bytes). + */ +_static_critical_size = 8168; + +/** + * `.chip_info` at the top of each ROM. + */ +_chip_info_size = 128; +_rom0_chip_info_end = ORIGIN(rom0) + LENGTH(rom0); +_rom0_chip_info_start = _rom0_chip_info_end - _chip_info_size; +_rom1_chip_info_end = ORIGIN(rom1) + LENGTH(rom1); +_rom1_chip_info_start = _rom1_chip_info_end - _chip_info_size; + +/** + * Size of the initial ePMP RX region at reset (in bytes). This region must be + * large enough to cover the .crt section. + * + * NOTE: This value must match the size of the RX region in + * hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh. + */ +_epmp_reset_rx_size = 2048; diff --git a/sw/host/opentitanlib/src/chip/autogen/darjeeling.rs b/sw/host/opentitanlib/src/chip/autogen/darjeeling.rs new file mode 100644 index 0000000000000..1154531e553b9 --- /dev/null +++ b/sw/host/opentitanlib/src/chip/autogen/darjeeling.rs @@ -0,0 +1,172 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file was generated automatically. +// Please do not modify content of this file directly. +// File generated by using template: "host_toplevel.rs.tpl" +// To regenerate this file follow OpenTitan topgen documentations. + +#![allow(dead_code)] + +use crate::with_unknown; + +with_unknown! { + pub enum PinmuxPeripheralIn: u32 [default = Self::End] { + SocProxySocGpi12 = 0, + SocProxySocGpi13 = 1, + SocProxySocGpi14 = 2, + SocProxySocGpi15 = 3, + End = 4, + } + + pub enum PinmuxInsel: u32 [default = Self::End] { + ConstantZero = 0, + ConstantOne = 1, + Mio0 = 2, + Mio1 = 3, + Mio2 = 4, + Mio3 = 5, + Mio4 = 6, + Mio5 = 7, + Mio6 = 8, + Mio7 = 9, + Mio8 = 10, + Mio9 = 11, + Mio10 = 12, + Mio11 = 13, + End = 14, + } + + pub enum PinmuxMioOut: u32 [default = Self::End] { + Mio0 = 0, + Mio1 = 1, + Mio2 = 2, + Mio3 = 3, + Mio4 = 4, + Mio5 = 5, + Mio6 = 6, + Mio7 = 7, + Mio8 = 8, + Mio9 = 9, + Mio10 = 10, + Mio11 = 11, + End = 12, + } + + pub enum PinmuxOutsel: u32 [default = Self::End] { + ConstantZero = 0, + ConstantOne = 1, + ConstantHighZ = 2, + SocProxySocGpo12 = 3, + SocProxySocGpo13 = 4, + SocProxySocGpo14 = 5, + SocProxySocGpo15 = 6, + OtpCtrlTest0 = 7, + End = 8, + } + + pub enum DirectPads: u32 [default = Self::End] { + SpiHost0Sd0 = 0, + SpiHost0Sd1 = 1, + SpiHost0Sd2 = 2, + SpiHost0Sd3 = 3, + SpiDeviceSd0 = 4, + SpiDeviceSd1 = 5, + SpiDeviceSd2 = 6, + SpiDeviceSd3 = 7, + I2c0Scl = 8, + I2c0Sda = 9, + GpioGpio0 = 10, + GpioGpio1 = 11, + GpioGpio2 = 12, + GpioGpio3 = 13, + GpioGpio4 = 14, + GpioGpio5 = 15, + GpioGpio6 = 16, + GpioGpio7 = 17, + GpioGpio8 = 18, + GpioGpio9 = 19, + GpioGpio10 = 20, + GpioGpio11 = 21, + GpioGpio12 = 22, + GpioGpio13 = 23, + GpioGpio14 = 24, + GpioGpio15 = 25, + GpioGpio16 = 26, + GpioGpio17 = 27, + GpioGpio18 = 28, + GpioGpio19 = 29, + GpioGpio20 = 30, + GpioGpio21 = 31, + GpioGpio22 = 32, + GpioGpio23 = 33, + GpioGpio24 = 34, + GpioGpio25 = 35, + GpioGpio26 = 36, + GpioGpio27 = 37, + GpioGpio28 = 38, + GpioGpio29 = 39, + GpioGpio30 = 40, + GpioGpio31 = 41, + SpiDeviceSck = 42, + SpiDeviceCsb = 43, + SpiDeviceTpmCsb = 44, + Uart0Rx = 45, + SocProxySocGpi0 = 46, + SocProxySocGpi1 = 47, + SocProxySocGpi2 = 48, + SocProxySocGpi3 = 49, + SocProxySocGpi4 = 50, + SocProxySocGpi5 = 51, + SocProxySocGpi6 = 52, + SocProxySocGpi7 = 53, + SocProxySocGpi8 = 54, + SocProxySocGpi9 = 55, + SocProxySocGpi10 = 56, + SocProxySocGpi11 = 57, + SpiHost0Sck = 58, + SpiHost0Csb = 59, + Uart0Tx = 60, + SocProxySocGpo0 = 61, + SocProxySocGpo1 = 62, + SocProxySocGpo2 = 63, + SocProxySocGpo3 = 64, + SocProxySocGpo4 = 65, + SocProxySocGpo5 = 66, + SocProxySocGpo6 = 67, + SocProxySocGpo7 = 68, + SocProxySocGpo8 = 69, + SocProxySocGpo9 = 70, + SocProxySocGpo10 = 71, + SocProxySocGpo11 = 72, + End = 73, + } + + pub enum MuxedPads: u32 [default = Self::End] { + Mio0 = 0, + Mio1 = 1, + Mio2 = 2, + Mio3 = 3, + Mio4 = 4, + Mio5 = 5, + Mio6 = 6, + Mio7 = 7, + Mio8 = 8, + Mio9 = 9, + Mio10 = 10, + Mio11 = 11, + End = 12, + } +} + +#[allow(non_camel_case_types)] +pub mod ujson_alias { + use super::*; + // Create aliases for the C names of these types so that the ujson + // created structs can access these structures by their C names. + pub type pinmux_peripheral_in_t = PinmuxPeripheralIn; + pub type pinmux_insel_t = PinmuxInsel; + pub type pinmux_mio_out_t = PinmuxMioOut; + pub type pinmux_outsel_t = PinmuxOutsel; +} From e3e619d9c43cdf6b6ec17e985b7ff9d8d0cc827c Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Fri, 15 Nov 2024 06:56:56 -0800 Subject: [PATCH 4/8] [hw,keymgr,rtl] Add keymgr_common package for sharing with keymgr_dpe Signed-off-by: Robert Schilling --- hw/ip/keymgr/keymgr_common.core | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 hw/ip/keymgr/keymgr_common.core diff --git a/hw/ip/keymgr/keymgr_common.core b/hw/ip/keymgr/keymgr_common.core new file mode 100644 index 0000000000000..8111812d75a96 --- /dev/null +++ b/hw/ip/keymgr/keymgr_common.core @@ -0,0 +1,28 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:ip:keymgr_common:0.1" +description: "Keymgr modules that are also used in Keymgr_DPE" + +filesets: + files_rtl: + depend: + - lowrisc:prim:edn_req + - lowrisc:ip:keymgr_pkg + - lowrisc:ip:kmac_pkg + files: + - rtl/keymgr_cfg_en.sv + - rtl/keymgr_reseed_ctrl.sv + - rtl/keymgr_sideload_key.sv + - rtl/keymgr_sideload_key_ctrl.sv + - rtl/keymgr_data_en_state.sv + - rtl/keymgr_kmac_if.sv + - rtl/keymgr_input_checks.sv + - rtl/keymgr_err.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl From 1f2e53cc8f8aefe78715bc27e01999478e7e4d0c Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Fri, 15 Nov 2024 07:14:08 -0800 Subject: [PATCH 5/8] [darjeeling] Add core and linter files for Darjeeling Signed-off-by: Robert Schilling --- hw/top_darjeeling/chip_darjeeling_asic.core | 84 +++++++++++ .../lint/chip_darjeeling_asic.waiver | 5 + hw/top_darjeeling/lint/top_darjeeling.vlt | 5 + hw/top_darjeeling/lint/top_darjeeling.waiver | 5 + hw/top_darjeeling/top_darjeeling.core | 138 ++++++++++++++++++ hw/top_darjeeling/top_darjeeling_pkg.core | 16 ++ 6 files changed, 253 insertions(+) create mode 100644 hw/top_darjeeling/chip_darjeeling_asic.core create mode 100644 hw/top_darjeeling/lint/chip_darjeeling_asic.waiver create mode 100644 hw/top_darjeeling/lint/top_darjeeling.vlt create mode 100644 hw/top_darjeeling/lint/top_darjeeling.waiver create mode 100644 hw/top_darjeeling/top_darjeeling.core create mode 100644 hw/top_darjeeling/top_darjeeling_pkg.core diff --git a/hw/top_darjeeling/chip_darjeeling_asic.core b/hw/top_darjeeling/chip_darjeeling_asic.core new file mode 100644 index 0000000000000..7fe019634f501 --- /dev/null +++ b/hw/top_darjeeling/chip_darjeeling_asic.core @@ -0,0 +1,84 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:systems:chip_darjeeling_asic:0.1" +description: "Earl Grey chip level" +filesets: + files_rtl: + depend: + - lowrisc:systems:top_darjeeling:0.1 + - lowrisc:systems:top_darjeeling_pkg + - lowrisc:systems:padring + - "fileset_partner ? (partner:systems:ast)" + - "fileset_partner ? (partner:systems:scan_role_pkg)" + - "!fileset_partner ? (lowrisc:systems:ast)" + - "!fileset_partner ? (lowrisc:systems:scan_role_pkg)" + files: + - rtl/autogen/chip_darjeeling_asic.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/chip_darjeeling_asic.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + IBEX_CUSTOM_PMP_RESET_VALUES: + datatype: bool + default: true + paramtype: vlogdefine + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: chip_darjeeling_asic + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" + + syn: + <<: *default_target + # TODO: set default to DC once + # this option is available + # olofk/edalize#89 + default_tool: icarus + parameters: + - SYNTHESIS=true + toplevel: chip_darjeeling_asic + + formal: + <<: *default_target + toplevel: chip_darjeeling_asic diff --git a/hw/top_darjeeling/lint/chip_darjeeling_asic.waiver b/hw/top_darjeeling/lint/chip_darjeeling_asic.waiver new file mode 100644 index 0000000000000..17387b12aa775 --- /dev/null +++ b/hw/top_darjeeling/lint/chip_darjeeling_asic.waiver @@ -0,0 +1,5 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for chip_darjeeling_asic diff --git a/hw/top_darjeeling/lint/top_darjeeling.vlt b/hw/top_darjeeling/lint/top_darjeeling.vlt new file mode 100644 index 0000000000000..45812a2536084 --- /dev/null +++ b/hw/top_darjeeling/lint/top_darjeeling.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for top_darjeeling diff --git a/hw/top_darjeeling/lint/top_darjeeling.waiver b/hw/top_darjeeling/lint/top_darjeeling.waiver new file mode 100644 index 0000000000000..4d0d397c4e6f3 --- /dev/null +++ b/hw/top_darjeeling/lint/top_darjeeling.waiver @@ -0,0 +1,5 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for top_darjeeling diff --git a/hw/top_darjeeling/top_darjeeling.core b/hw/top_darjeeling/top_darjeeling.core new file mode 100644 index 0000000000000..00d0bfd5d99d3 --- /dev/null +++ b/hw/top_darjeeling/top_darjeeling.core @@ -0,0 +1,138 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:systems:top_darjeeling:0.1" +description: "Technology-independent Darjeeling toplevel" +filesets: + files_rtl_generic: + depend: + # Place the autogen packages first to avoid conflicts + - lowrisc:opentitan:top_darjeeling_alert_handler_reg + - lowrisc:opentitan:top_darjeeling_pwrmgr_pkg + - lowrisc:ip:uart:0.1 + - lowrisc:ip:gpio + - lowrisc:ip:rv_core_ibex + - lowrisc:ip:rv_dm + - lowrisc:ip:rv_timer + - lowrisc:ip:tlul + - lowrisc:ip:spi_device + - lowrisc:ip:spi_host + - lowrisc:ip:i2c + - lowrisc:ip:pattgen + - lowrisc:ip:aes + - lowrisc:ip:entropy_src_pkg + - lowrisc:ip:csrng + - lowrisc:ip:edn + - lowrisc:ip:dma + - lowrisc:ip:hmac + - lowrisc:ip:kmac + - lowrisc:ip:otbn + - lowrisc:prim:ram_1p_scr + - lowrisc:ip:sram_ctrl + - lowrisc:ip:keymgr_dpe + - lowrisc:constants:top_pkg + - lowrisc:constants:jtag_id_pkg + - lowrisc:constants:ibex_pmp_reset_pkg + - lowrisc:ip:otp_ctrl + - lowrisc:ip:lc_ctrl + - lowrisc:ip:mbx + - lowrisc:top_darjeeling:xbar_dbg + - lowrisc:top_darjeeling:xbar_main + - lowrisc:top_darjeeling:xbar_mbx + - lowrisc:top_darjeeling:xbar_peri + - lowrisc:opentitan:top_darjeeling_alert_handler + - lowrisc:opentitan:top_darjeeling_clkmgr + - lowrisc:opentitan:top_darjeeling_rstmgr + - lowrisc:opentitan:top_darjeeling_rv_plic + - lowrisc:opentitan:top_darjeeling_pinmux + - lowrisc:opentitan:top_darjeeling_pwrmgr + - lowrisc:ip:aon_timer + - lowrisc:ip:adc_ctrl + - lowrisc:ip:sysrst_ctrl + - lowrisc:ip:rom_ctrl + - lowrisc:systems:sensor_ctrl + - lowrisc:systems:soc_proxy + - lowrisc:tlul:headers + - lowrisc:prim:all + - lowrisc:prim:mubi + - lowrisc:systems:top_darjeeling_pkg + - "fileset_partner ? (partner:systems:ast_pkg)" + - "!fileset_partner ? (lowrisc:systems:ast_pkg)" + files: + - rtl/autogen/top_darjeeling_rnd_cnst_pkg.sv + - rtl/autogen/top_darjeeling.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/top_darjeeling.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/top_darjeeling.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/top_darjeeling.vbw + file_type: veribleLintWaiver + + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl_generic + toplevel: top_darjeeling + + sim: + default_tool: icarus + filesets: + - files_rtl_generic + toplevel: top_darjeeling + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" + + syn: + <<: *default_target + # TODO: set default to DC once + # this option is available + # olofk/edalize#89 + default_tool: icarus + parameters: + - SYNTHESIS=true + toplevel: top_darjeeling + + formal: + <<: *default_target + toplevel: top_darjeeling diff --git a/hw/top_darjeeling/top_darjeeling_pkg.core b/hw/top_darjeeling/top_darjeeling_pkg.core new file mode 100644 index 0000000000000..33561d544dd14 --- /dev/null +++ b/hw/top_darjeeling/top_darjeeling_pkg.core @@ -0,0 +1,16 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:systems:top_darjeeling_pkg:0.1" +description: "Autogenerated top_darjeeling_pkg used in RTL and DV." +filesets: + files_rtl: + files: + - rtl/autogen/top_darjeeling_pkg.sv + file_type: systemVerilogSource + +targets: + default: &default_target + filesets: + - files_rtl From d0f0cd3f685081e181c5306d96aaf91e26a32e99 Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Fri, 15 Nov 2024 12:54:39 +0100 Subject: [PATCH 6/8] [darjeeling,lint] Re-enable uncommented linting rules Signed-off-by: Robert Schilling --- hw/top_darjeeling/FUSESOC_IGNORE | 1 - .../lint/top_darjeeling_lint_cfgs.hjson | 240 +++++++++--------- 2 files changed, 120 insertions(+), 121 deletions(-) delete mode 100644 hw/top_darjeeling/FUSESOC_IGNORE diff --git a/hw/top_darjeeling/FUSESOC_IGNORE b/hw/top_darjeeling/FUSESOC_IGNORE deleted file mode 100644 index 8b137891791fe..0000000000000 --- a/hw/top_darjeeling/FUSESOC_IGNORE +++ /dev/null @@ -1 +0,0 @@ - diff --git a/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson b/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson index d68b1e28bdb46..a801fe2aeb1f2 100644 --- a/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson +++ b/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson @@ -36,44 +36,44 @@ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/ip/aes/lint/{tool}" }, - // { name: alert_handler - // fusesoc_core: lowrisc:opentitan:top_darjeeling_alert_handler - // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] - // rel_path: "hw/top_darjeeling/ip_autogen/alert_handler/lint/{tool}" - // overrides: [ - // { - // name: design_level - // value: "top" - // } - // ] - // }, + { name: alert_handler + fusesoc_core: lowrisc:opentitan:top_darjeeling_alert_handler + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + rel_path: "hw/top_darjeeling/ip_autogen/alert_handler/lint/{tool}" + overrides: [ + { + name: design_level + value: "top" + } + ] + }, { name: aon_timer fusesoc_core: lowrisc:ip:aon_timer import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/ip/aon_timer/lint/{tool}" }, - // { name: ast - // fusesoc_core: lowrisc:systems:ast - // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] - // rel_path: "hw/top_darjeeling/ip/ast/lint/{tool}" - // overrides: [ - // { - // name: design_level - // value: "top" - // } - // ] - // }, - // { name: clkmgr - // fusesoc_core: lowrisc:opentitan:top_darjeeling_clkmgr - // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], - // rel_path: "hw/top_darjeeling/ip_autogen/clkmgr/lint/{tool}", - // overrides: [ - // { - // name: design_level - // value: "top" - // } - // ] - // }, + { name: ast + fusesoc_core: lowrisc:systems:ast + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + rel_path: "hw/top_darjeeling/ip/ast/lint/{tool}" + overrides: [ + { + name: design_level + value: "top" + } + ] + }, + { name: clkmgr + fusesoc_core: lowrisc:opentitan:top_darjeeling_clkmgr + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], + rel_path: "hw/top_darjeeling/ip_autogen/clkmgr/lint/{tool}", + overrides: [ + { + name: design_level + value: "top" + } + ] + }, { name: csrng fusesoc_core: lowrisc:ip:csrng import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] @@ -84,17 +84,17 @@ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/ip/edn/lint/{tool}" }, - // { name: flash_ctrl - // fusesoc_core: lowrisc:opentitan:top_darjeeling_flash_ctrl - // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] - // rel_path: "hw/top_darjeeling/ip_autogen/flash_ctrl/lint/{tool}" - // overrides: [ - // { - // name: design_level - // value: "top" - // } - // ] - // }, + { name: flash_ctrl + fusesoc_core: lowrisc:opentitan:top_darjeeling_flash_ctrl + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + rel_path: "hw/top_darjeeling/ip_autogen/flash_ctrl/lint/{tool}" + overrides: [ + { + name: design_level + value: "top" + } + ] + }, { name: gpio fusesoc_core: lowrisc:ip:gpio import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] @@ -115,17 +115,17 @@ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/ip/i2c/lint/{tool}" }, - // { name: lc_ctrl - // fusesoc_core: lowrisc:ip:lc_ctrl - // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] - // rel_path: "hw/ip/lc_ctrl/lint/{tool}" - // overrides: [ - // { - // name: design_level - // value: "top" - // } - // ] - // }, + { name: lc_ctrl + fusesoc_core: lowrisc:ip:lc_ctrl + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + rel_path: "hw/ip/lc_ctrl/lint/{tool}" + overrides: [ + { + name: design_level + value: "top" + } + ] + }, { name: keymgr fusesoc_core: lowrisc:ip:keymgr import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] @@ -141,28 +141,28 @@ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/ip/otbn/lint/{tool}" }, - // { name: otp_ctrl - // fusesoc_core: lowrisc:ip:otp_ctrl - // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] - // rel_path: "hw/ip/otp_ctrl/lint/{tool}" - // overrides: [ - // { - // name: design_level - // value: "top" - // } - // ] - // }, - // { name: pinmux - // fusesoc_core: lowrisc:ip:pinmux - // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] - // rel_path: "hw/ip/pinmux/lint/{tool}" - // overrides: [ - // { - // name: design_level - // value: "top" - // } - // ] - // }, + { name: otp_ctrl + fusesoc_core: lowrisc:ip:otp_ctrl + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + rel_path: "hw/ip/otp_ctrl/lint/{tool}" + overrides: [ + { + name: design_level + value: "top" + } + ] + }, + { name: pinmux + fusesoc_core: lowrisc:ip:pinmux + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + rel_path: "hw/ip/pinmux/lint/{tool}" + overrides: [ + { + name: design_level + value: "top" + } + ] + }, { name: pwm fusesoc_core: lowrisc:ip:pwm import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] @@ -174,33 +174,33 @@ } ] }, - // { name: pwrmgr - // fusesoc_core: lowrisc:opentitan:top_darjeeling_pwrmgr - // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], - // rel_path: "hw/top_darjeeling/ip_autogen/pwrmgr/lint/{tool}", - // overrides: [ - // { - // name: design_level - // value: "top" - // } - // ] - // }, + { name: pwrmgr + fusesoc_core: lowrisc:opentitan:top_darjeeling_pwrmgr + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], + rel_path: "hw/top_darjeeling/ip_autogen/pwrmgr/lint/{tool}", + overrides: [ + { + name: design_level + value: "top" + } + ] + }, { name: rom_ctrl fusesoc_core: lowrisc:ip:rom_ctrl import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/ip/rom_ctrl/lint/{tool}" }, - // { name: rstmgr - // fusesoc_core: lowrisc:opentitan:top_darjeeling_rstmgr - // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], - // rel_path: "hw/top_darjeeling/ip_autogen/rstmgr/lint/{tool}", - // overrides: [ - // { - // name: design_level - // value: "top" - // } - // ] - // }, + { name: rstmgr + fusesoc_core: lowrisc:opentitan:top_darjeeling_rstmgr + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], + rel_path: "hw/top_darjeeling/ip_autogen/rstmgr/lint/{tool}", + overrides: [ + { + name: design_level + value: "top" + } + ] + }, { name: rv_core_ibex fusesoc_core: lowrisc:ip:rv_core_ibex import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] @@ -211,11 +211,11 @@ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/ip/rv_dm/lint/{tool}" }, - // { name: top_darjeeling_rv_plic - // fusesoc_core: lowrisc:opentitan:top_darjeeling_rv_plic - // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] - // rel_path: "hw/top_darjeeling/ip_autogen/rv_plic/lint/{tool}" - // }, + { name: top_darjeeling_rv_plic + fusesoc_core: lowrisc:opentitan:top_darjeeling_rv_plic + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + rel_path: "hw/top_darjeeling/ip_autogen/rv_plic/lint/{tool}" + }, { name: rv_timer fusesoc_core: lowrisc:ip:rv_timer import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] @@ -282,27 +282,27 @@ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/ip/tlul/adapter_sram/lint/{tool}" }, - // { name: sensor_ctrl - // fusesoc_core: lowrisc:systems:sensor_ctrl - // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] - // rel_path: "hw/top_darjeeling/ip/sensor_ctrl/lint/{tool}" - // }, + { name: sensor_ctrl + fusesoc_core: lowrisc:systems:sensor_ctrl + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + rel_path: "hw/top_darjeeling/ip/sensor_ctrl/lint/{tool}" + }, { name: sram2tlul fusesoc_core: lowrisc:tlul:sram2tlul import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/ip/tlul/sram2tlul/lint/{tool}" }, - // { name: chip_darjeeling_asic - // fusesoc_core: lowrisc:systems:chip_darjeeling_asic - // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] - // rel_path: "hw/top_darjeeling/lint/{tool}" - // overrides: [ - // { - // name: design_level - // value: "top" - // } - // ] - // }, + { name: chip_darjeeling_asic + fusesoc_core: lowrisc:systems:chip_darjeeling_asic + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + rel_path: "hw/top_darjeeling/lint/{tool}" + overrides: [ + { + name: design_level + value: "top" + } + ] + }, ] } From fe8fbe23a0d172d5ceda7d871e5fe7e5af222e7c Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Fri, 15 Nov 2024 17:40:12 +0100 Subject: [PATCH 7/8] [darjeeling] Add top-dependend RTL files Add jtag_id_pkg.sv, padring.sv, scan_role_pkg, ibex_pmp_reset_pkg.sv Signed-off-by: Robert Schilling --- hw/top_darjeeling/chip_darjeeling_asic.core | 6 +- hw/top_darjeeling/lint/padring.waiver | 30 +++++ hw/top_darjeeling/rtl/ibex_pmp_reset_pkg.sv | 58 +++++++++ hw/top_darjeeling/rtl/jtag_id_pkg copy.sv | 30 +++++ hw/top_darjeeling/rtl/jtag_id_pkg.sv | 37 ++++++ hw/top_darjeeling/rtl/padring.sv | 110 ++++++++++++++++++ hw/top_darjeeling/rtl/scan_role_pkg.sv | 105 +++++++++++++++++ hw/top_darjeeling/top_darjeeling.core | 4 +- .../top_darjeeling_ibex_pmp_reset_pkg.core | 22 ++++ .../top_darjeeling_jtag_id_pkg.core | 19 +++ hw/top_darjeeling/top_darjeeling_padring.core | 47 ++++++++ .../top_darjeeling_scan_role_pkg.core | 42 +++++++ 12 files changed, 505 insertions(+), 5 deletions(-) create mode 100644 hw/top_darjeeling/lint/padring.waiver create mode 100644 hw/top_darjeeling/rtl/ibex_pmp_reset_pkg.sv create mode 100644 hw/top_darjeeling/rtl/jtag_id_pkg copy.sv create mode 100644 hw/top_darjeeling/rtl/jtag_id_pkg.sv create mode 100644 hw/top_darjeeling/rtl/padring.sv create mode 100644 hw/top_darjeeling/rtl/scan_role_pkg.sv create mode 100644 hw/top_darjeeling/top_darjeeling_ibex_pmp_reset_pkg.core create mode 100644 hw/top_darjeeling/top_darjeeling_jtag_id_pkg.core create mode 100644 hw/top_darjeeling/top_darjeeling_padring.core create mode 100644 hw/top_darjeeling/top_darjeeling_scan_role_pkg.core diff --git a/hw/top_darjeeling/chip_darjeeling_asic.core b/hw/top_darjeeling/chip_darjeeling_asic.core index 7fe019634f501..b436ac378b93c 100644 --- a/hw/top_darjeeling/chip_darjeeling_asic.core +++ b/hw/top_darjeeling/chip_darjeeling_asic.core @@ -9,11 +9,11 @@ filesets: depend: - lowrisc:systems:top_darjeeling:0.1 - lowrisc:systems:top_darjeeling_pkg - - lowrisc:systems:padring + - lowrisc:systems:top_darjeeling_padring - "fileset_partner ? (partner:systems:ast)" - - "fileset_partner ? (partner:systems:scan_role_pkg)" + - "fileset_partner ? (partner:systems:top_darjeeling_scan_role_pkg)" - "!fileset_partner ? (lowrisc:systems:ast)" - - "!fileset_partner ? (lowrisc:systems:scan_role_pkg)" + - "!fileset_partner ? (lowrisc:systems:top_darjeeling_scan_role_pkg)" files: - rtl/autogen/chip_darjeeling_asic.sv file_type: systemVerilogSource diff --git a/hw/top_darjeeling/lint/padring.waiver b/hw/top_darjeeling/lint/padring.waiver new file mode 100644 index 0000000000000..64c85d7f32b15 --- /dev/null +++ b/hw/top_darjeeling/lint/padring.waiver @@ -0,0 +1,30 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for padring + +waive -rules {HIER_BRANCH_NOT_READ HIER_NET_NOT_READ} \ + -location {padring.sv} \ + -regexp {Net 'pok_i.*' in module 'padring'.*is not read from} \ + -comment "SNS and RTO cells are not read from in the converted LIB/DB model, resulting in these warnings." + +waive -rules {HIER_BRANCH_NOT_READ HIER_NET_NOT_READ} \ + -location {padring.sv} \ + -regexp {Connected net '(SNS|RTO)'.*is not read from in module.*} \ + -comment "Some ports are not read from in the converted LIB/DB model, resulting in these warnings." + +waive -rules {HIER_BRANCH_NOT_READ} \ + -location {padring.sv} \ + -regexp {Net 'clk_scan_i' in module 'padring'.*} \ + -comment "This net is not read from if no scan role is defined for the pads (which is the case in the opensource view)." + +waive -rules {CLOCK_DRIVER} \ + -location {padring.sv} \ + -regexp {'gen_mio_pads\[38\].mio_in' is driven by instance 'gen_mio_pads\[38\]\^u_mio_pad' of module 'prim_pad_wrapper', and used as a clock 'tck_i' at dmi_jtag_tap.sv} \ + -comment "The 'mio_in[TckPadIdx]' input signal driven by a prim_pad_wrapper eventually feeds in to the JTAG Selection Mux." + +waive -rules {CLOCK_DRIVER} \ + -location {padring.sv} \ + -regexp {'gen_mio_pads\[28\].mio_in_raw' is driven by instance 'gen_mio_pads\[28\]\^u_mio_pad' of module 'prim_pad_wrapper', and used as a clock} \ + -comment "'MioPadIoc6' at index 28 may also serve as an external clock input." diff --git a/hw/top_darjeeling/rtl/ibex_pmp_reset_pkg.sv b/hw/top_darjeeling/rtl/ibex_pmp_reset_pkg.sv new file mode 100644 index 0000000000000..450e25d320ec4 --- /dev/null +++ b/hw/top_darjeeling/rtl/ibex_pmp_reset_pkg.sv @@ -0,0 +1,58 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package ibex_pmp_reset_pkg; + import ibex_pkg::*; + + // Default reset values for PMP CSRs. Where the number of regions + // (PMPNumRegions) is less than 16 the reset values for the higher numbered + // regions are ignored. + + localparam pmp_cfg_t PmpCfgRst[16] = '{ + // Region info + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 0 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 1 + '{lock: 1'b1, mode: PMP_MODE_NAPOT, exec: 1'b1, write: 1'b0, read: 1'b1}, // 2 [ROM: LRX] + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 3 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 4 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 5 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 6 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 7 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 8 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 9 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 10 + '{lock: 1'b1, mode: PMP_MODE_TOR, exec: 1'b0, write: 1'b1, read: 1'b1}, // 11 [MMIO: LRW] + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 12 + '{lock: 1'b1, mode: PMP_MODE_NAPOT, exec: 1'b1, write: 1'b1, read: 1'b1}, // 13 [DV_ROM: LRWX] + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // 14 + '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0} // 15 + }; + + // Addresses are given in byte granularity for readibility. A minimum of two + // bits will be stripped off the bottom (PMPGranularity == 0) with more stripped + // off at coarser granularities. + // + // Note: The size of region 2 below must match `_epmp_reset_rx_size` in + // `sw/device/silicon_creator/rom/rom.ld` + localparam logic [33:0] PmpAddrRst[16] = '{ + 34'h00000000, // rgn 0 + 34'h00000000, // rgn 1 + 34'h000083fc, // rgn 2 [ROM: base=0x0000_8000 size=0x800 (2KiB)] + 34'h00000000, // rgn 3 + 34'h00000000, // rgn 4 + 34'h00000000, // rgn 5 + 34'h00000000, // rgn 6 + 34'h00000000, // rgn 7 + 34'h00000000, // rgn 8 + 34'h00000000, // rgn 9 + 34'h40000000, // rgn 10 [MMIO: lo=0x4000_0000] + 34'h42010000, // rgn 11 [MMIO: hi=0x4201_0000] + 34'h00000000, // rgn 12 + 34'h000107fc, // rgn 13 [DV_ROM: base=0x0001_0000 size=0x1000 (4KiB)] + 34'h00000000, // rgn 14 + 34'h00000000 // rgn 15 + }; + + localparam pmp_mseccfg_t PmpMseccfgRst = '{rlb : 1'b1, mmwp: 1'b1, mml: 1'b0}; +endpackage diff --git a/hw/top_darjeeling/rtl/jtag_id_pkg copy.sv b/hw/top_darjeeling/rtl/jtag_id_pkg copy.sv new file mode 100644 index 0000000000000..fe13284241b43 --- /dev/null +++ b/hw/top_darjeeling/rtl/jtag_id_pkg copy.sv @@ -0,0 +1,30 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +package jtag_id_pkg; + + // lowRISC JEDEC Manufacturer ID, bank 13 0xEF + localparam logic [10:0] JEDEC_MANUFACTURER_ID = {4'd12, 7'b110_1111}; + localparam logic [3:0] JTAG_VERSION = 4'h1; + + // These are the open source facing JTAG values that silicon creators may wish to replace We have + // two TAPs, one for rv_dm and the other for lc_ctrl, they each have their own JTAG_IDCODE. They + // only differ in part number. + + localparam logic [31:0] RV_DM_JTAG_IDCODE = { + JTAG_VERSION, // Version + 16'h1, // Part Number + JEDEC_MANUFACTURER_ID, // Manufacturer ID + 1'b1 // (fixed) + }; + + localparam logic [31:0] LC_CTRL_JTAG_IDCODE = { + JTAG_VERSION, // Version + 16'h2, // Part Number + JEDEC_MANUFACTURER_ID, // Manufacturer ID + 1'b1 // (fixed) + }; + +endpackage : jtag_id_pkg diff --git a/hw/top_darjeeling/rtl/jtag_id_pkg.sv b/hw/top_darjeeling/rtl/jtag_id_pkg.sv new file mode 100644 index 0000000000000..67d5a5b18f1d9 --- /dev/null +++ b/hw/top_darjeeling/rtl/jtag_id_pkg.sv @@ -0,0 +1,37 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +package jtag_id_pkg; + + // lowRISC JEDEC Manufacturer ID, bank 13 0xEF + localparam logic [10:0] JEDEC_MANUFACTURER_ID = {4'd12, 7'b110_1111}; + localparam logic [3:0] JTAG_VERSION = 4'h1; + + // These are the open source facing JTAG values that silicon creators may wish to replace We have + // two TAPs, one for rv_dm and the other for lc_ctrl, they each have their own JTAG_IDCODE. They + // only differ in part number. + + localparam logic [31:0] RV_DM_JTAG_IDCODE = { + JTAG_VERSION, // Version + 16'h1, // Part Number + JEDEC_MANUFACTURER_ID, // Manufacturer ID + 1'b1 // (fixed) + }; + + localparam logic [31:0] LC_CTRL_JTAG_IDCODE = { + JTAG_VERSION, // Version + 16'h2, // Part Number + JEDEC_MANUFACTURER_ID, // Manufacturer ID + 1'b1 // (fixed) + }; + + localparam logic [31:0] LC_DM_COMBINED_JTAG_IDCODE = { + JTAG_VERSION, // Version + 16'h3, // Part Number + JEDEC_MANUFACTURER_ID, // Manufacturer ID + 1'b1 // (fixed) + }; + +endpackage : jtag_id_pkg \ No newline at end of file diff --git a/hw/top_darjeeling/rtl/padring.sv b/hw/top_darjeeling/rtl/padring.sv new file mode 100644 index 0000000000000..8cd9cf6ec859b --- /dev/null +++ b/hw/top_darjeeling/rtl/padring.sv @@ -0,0 +1,110 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This is the pinmux portion that has to be instantiated on the chip level. +// The module instantiates the technology dependent pads, and connects them +// to the MIOs/DIOs and pad attributes coming from the pinmux block. +// + +`include "prim_assert.sv" + +module padring + import prim_pad_wrapper_pkg::*; +#( + parameter int NDioPads = 1, + parameter int NMioPads = 1, + parameter pad_type_e [NDioPads-1:0] DioPadType = {NDioPads{BidirStd}}, + parameter pad_type_e [NMioPads-1:0] MioPadType = {NMioPads{BidirStd}}, + // Only used for ASIC target + parameter bit PhysicalPads = 0, + parameter int NIoBanks = 4, + parameter logic [NDioPads-1:0][$clog2(NIoBanks):0] DioPadBank = '0, + parameter logic [NMioPads-1:0][$clog2(NIoBanks):0] MioPadBank = '0, + parameter scan_role_e [NDioPads-1:0] DioScanRole = {NDioPads{NoScan}}, + parameter scan_role_e [NMioPads-1:0] MioScanRole = {NMioPads{NoScan}} +) ( + // This is only used for scan + input clk_scan_i, + prim_mubi_pkg::mubi4_t scanmode_i, + // RAW outputs used for DFT and infrastructure + // purposes (e.g. external muxed clock) + output logic [NDioPads-1:0] dio_in_raw_o, + output logic [NMioPads-1:0] mio_in_raw_o, + // Pad wires + inout wire [NDioPads-1:0] dio_pad_io, + inout wire [NMioPads-1:0] mio_pad_io, + // Dedicated IO signals coming from peripherals + output logic [NDioPads-1:0] dio_in_o, + input [NDioPads-1:0] dio_out_i, + input [NDioPads-1:0] dio_oe_i, + // Muxed IO signals coming from pinmux + output logic [NMioPads-1:0] mio_in_o, + input [NMioPads-1:0] mio_out_i, + input [NMioPads-1:0] mio_oe_i, + // Pad attributes from top level instance + input pad_attr_t [NDioPads-1:0] dio_attr_i, + input pad_attr_t [NMioPads-1:0] mio_attr_i +); + + pad_pok_t [NIoBanks-1:0] pad_pok; + + logic scanmode; + prim_mubi4_dec u_prim_mubi4_dec ( + .mubi_i ( scanmode_i ), + .mubi_dec_o ( scanmode ) + ); + + for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_pads + prim_pad_wrapper #( + .PadType ( DioPadType[k] ), + .ScanRole ( DioScanRole[k] ) + ) u_dio_pad ( + .clk_scan_i, + .scanmode_i ( scanmode ), + .pok_i ( pad_pok[DioPadBank[k]] ), + .inout_io ( dio_pad_io[k] ), + .in_o ( dio_in_o[k] ), + .in_raw_o ( dio_in_raw_o[k] ), + // This is currently not dynamically controlled. + // However, this may change in the future if the + // need arises (e.g. as part of to power sequencing). + .ie_i ( 1'b1 ), + .out_i ( dio_out_i[k] ), + .oe_i ( dio_oe_i[k] ), + .attr_i ( dio_attr_i[k] ) + ); + end + + for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_pads + prim_pad_wrapper #( + .PadType ( MioPadType[k] ), + .ScanRole ( MioScanRole[k] ) + ) u_mio_pad ( + .clk_scan_i, + .scanmode_i ( scanmode ), + .pok_i ( pad_pok[MioPadBank[k]] ), + .inout_io ( mio_pad_io[k] ), + .in_o ( mio_in_o[k] ), + .in_raw_o ( mio_in_raw_o[k] ), + // This is currently not dynamically controlled. + // However, this may change in the future if the + // need arises (e.g. as part of to power sequencing). + .ie_i ( 1'b1 ), + .out_i ( mio_out_i[k] ), + .oe_i ( mio_oe_i[k] ), + .attr_i ( mio_attr_i[k] ) + ); + end + + if (PhysicalPads) begin : gen_physical_pads + physical_pads #( + .NIoBanks(NIoBanks) + ) u_physical_pads ( + .pad_pok_o(pad_pok) + ); + end else begin : gen_no_physical_pads + assign pad_pok = '0; + end + +endmodule : padring diff --git a/hw/top_darjeeling/rtl/scan_role_pkg.sv b/hw/top_darjeeling/rtl/scan_role_pkg.sv new file mode 100644 index 0000000000000..10690fa541254 --- /dev/null +++ b/hw/top_darjeeling/rtl/scan_role_pkg.sv @@ -0,0 +1,105 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Open-source scan role definitions for pads. +// This is only relevant for the ASIC target. + +package scan_role_pkg; + + import prim_pad_wrapper_pkg::*; + + parameter scan_role_e DioPadPorNScanRole = NoScan; + parameter scan_role_e DioPadOtpExtVoltScanRole = NoScan; + parameter scan_role_e DioPadJtagTckScanRole = NoScan; + parameter scan_role_e DioPadJtagTmsScanRole = NoScan; + parameter scan_role_e DioPadJtagTdiScanRole = NoScan; + parameter scan_role_e DioPadJtagTdoScanRole = NoScan; + parameter scan_role_e DioPadJtagTrstNScanRole = NoScan; + parameter scan_role_e DioPadSpiHostD0ScanRole = NoScan; + parameter scan_role_e DioPadSpiHostD1ScanRole = NoScan; + parameter scan_role_e DioPadSpiHostD2ScanRole = NoScan; + parameter scan_role_e DioPadSpiHostD3ScanRole = NoScan; + parameter scan_role_e DioPadSpiHostClkScanRole = NoScan; + parameter scan_role_e DioPadSpiHostCsLScanRole = NoScan; + parameter scan_role_e DioPadSpiDevD0ScanRole = NoScan; + parameter scan_role_e DioPadSpiDevD1ScanRole = NoScan; + parameter scan_role_e DioPadSpiDevD2ScanRole = NoScan; + parameter scan_role_e DioPadSpiDevD3ScanRole = NoScan; + parameter scan_role_e DioPadSpiDevClkScanRole = NoScan; + parameter scan_role_e DioPadSpiDevCsLScanRole = NoScan; + parameter scan_role_e DioPadSpiDevTpmCsLScanRole = NoScan; + parameter scan_role_e DioPadUartRxScanRole = NoScan; + parameter scan_role_e DioPadUartTxScanRole = NoScan; + parameter scan_role_e DioPadI2cSclScanRole = NoScan; + parameter scan_role_e DioPadI2cSdaScanRole = NoScan; + parameter scan_role_e DioPadGpio0ScanRole = NoScan; + parameter scan_role_e DioPadGpio1ScanRole = NoScan; + parameter scan_role_e DioPadGpio2ScanRole = NoScan; + parameter scan_role_e DioPadGpio3ScanRole = NoScan; + parameter scan_role_e DioPadGpio4ScanRole = NoScan; + parameter scan_role_e DioPadGpio5ScanRole = NoScan; + parameter scan_role_e DioPadGpio6ScanRole = NoScan; + parameter scan_role_e DioPadGpio7ScanRole = NoScan; + parameter scan_role_e DioPadGpio8ScanRole = NoScan; + parameter scan_role_e DioPadGpio9ScanRole = NoScan; + parameter scan_role_e DioPadGpio10ScanRole = NoScan; + parameter scan_role_e DioPadGpio11ScanRole = NoScan; + parameter scan_role_e DioPadGpio12ScanRole = NoScan; + parameter scan_role_e DioPadGpio13ScanRole = NoScan; + parameter scan_role_e DioPadGpio14ScanRole = NoScan; + parameter scan_role_e DioPadGpio15ScanRole = NoScan; + parameter scan_role_e DioPadGpio16ScanRole = NoScan; + parameter scan_role_e DioPadGpio17ScanRole = NoScan; + parameter scan_role_e DioPadGpio18ScanRole = NoScan; + parameter scan_role_e DioPadGpio19ScanRole = NoScan; + parameter scan_role_e DioPadGpio20ScanRole = NoScan; + parameter scan_role_e DioPadGpio21ScanRole = NoScan; + parameter scan_role_e DioPadGpio22ScanRole = NoScan; + parameter scan_role_e DioPadGpio23ScanRole = NoScan; + parameter scan_role_e DioPadGpio24ScanRole = NoScan; + parameter scan_role_e DioPadGpio25ScanRole = NoScan; + parameter scan_role_e DioPadGpio26ScanRole = NoScan; + parameter scan_role_e DioPadGpio27ScanRole = NoScan; + parameter scan_role_e DioPadGpio28ScanRole = NoScan; + parameter scan_role_e DioPadGpio29ScanRole = NoScan; + parameter scan_role_e DioPadGpio30ScanRole = NoScan; + parameter scan_role_e DioPadGpio31ScanRole = NoScan; + parameter scan_role_e DioPadSocGpi0ScanRole = NoScan; + parameter scan_role_e DioPadSocGpi1ScanRole = NoScan; + parameter scan_role_e DioPadSocGpi2ScanRole = NoScan; + parameter scan_role_e DioPadSocGpi3ScanRole = NoScan; + parameter scan_role_e DioPadSocGpi4ScanRole = NoScan; + parameter scan_role_e DioPadSocGpi5ScanRole = NoScan; + parameter scan_role_e DioPadSocGpi6ScanRole = NoScan; + parameter scan_role_e DioPadSocGpi7ScanRole = NoScan; + parameter scan_role_e DioPadSocGpi8ScanRole = NoScan; + parameter scan_role_e DioPadSocGpi9ScanRole = NoScan; + parameter scan_role_e DioPadSocGpi10ScanRole = NoScan; + parameter scan_role_e DioPadSocGpi11ScanRole = NoScan; + parameter scan_role_e DioPadSocGpo0ScanRole = NoScan; + parameter scan_role_e DioPadSocGpo1ScanRole = NoScan; + parameter scan_role_e DioPadSocGpo2ScanRole = NoScan; + parameter scan_role_e DioPadSocGpo3ScanRole = NoScan; + parameter scan_role_e DioPadSocGpo4ScanRole = NoScan; + parameter scan_role_e DioPadSocGpo5ScanRole = NoScan; + parameter scan_role_e DioPadSocGpo6ScanRole = NoScan; + parameter scan_role_e DioPadSocGpo7ScanRole = NoScan; + parameter scan_role_e DioPadSocGpo8ScanRole = NoScan; + parameter scan_role_e DioPadSocGpo9ScanRole = NoScan; + parameter scan_role_e DioPadSocGpo10ScanRole = NoScan; + parameter scan_role_e DioPadSocGpo11ScanRole = NoScan; + parameter scan_role_e MioPadMio0ScanRole = NoScan; + parameter scan_role_e MioPadMio1ScanRole = NoScan; + parameter scan_role_e MioPadMio2ScanRole = NoScan; + parameter scan_role_e MioPadMio3ScanRole = NoScan; + parameter scan_role_e MioPadMio4ScanRole = NoScan; + parameter scan_role_e MioPadMio5ScanRole = NoScan; + parameter scan_role_e MioPadMio6ScanRole = NoScan; + parameter scan_role_e MioPadMio7ScanRole = NoScan; + parameter scan_role_e MioPadMio8ScanRole = NoScan; + parameter scan_role_e MioPadMio9ScanRole = NoScan; + parameter scan_role_e MioPadMio10ScanRole = NoScan; + parameter scan_role_e MioPadMio11ScanRole = NoScan; + +endpackage : scan_role_pkg diff --git a/hw/top_darjeeling/top_darjeeling.core b/hw/top_darjeeling/top_darjeeling.core index 00d0bfd5d99d3..c261b98b25a3e 100644 --- a/hw/top_darjeeling/top_darjeeling.core +++ b/hw/top_darjeeling/top_darjeeling.core @@ -32,8 +32,8 @@ filesets: - lowrisc:ip:sram_ctrl - lowrisc:ip:keymgr_dpe - lowrisc:constants:top_pkg - - lowrisc:constants:jtag_id_pkg - - lowrisc:constants:ibex_pmp_reset_pkg + - lowrisc:constants:top_darjeeling_jtag_id_pkg + - lowrisc:constants:top_darjeeling_ibex_pmp_reset_pkg - lowrisc:ip:otp_ctrl - lowrisc:ip:lc_ctrl - lowrisc:ip:mbx diff --git a/hw/top_darjeeling/top_darjeeling_ibex_pmp_reset_pkg.core b/hw/top_darjeeling/top_darjeeling_ibex_pmp_reset_pkg.core new file mode 100644 index 0000000000000..17977985fa09a --- /dev/null +++ b/hw/top_darjeeling/top_darjeeling_ibex_pmp_reset_pkg.core @@ -0,0 +1,22 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# XXX: This name is currently required as global identifier until we have +# support for "interfaces" or a similar concept. +# Tracked in https://github.com/olofk/fusesoc/issues/235 +name: "lowrisc:constants:top_darjeeling_ibex_pmp_reset_pkg" +description: "Top-level specific PMP reset settings for Darjeeling" +filesets: + files_rtl: + depend: + - lowrisc:ip:rv_core_ibex_pkg + files: + - rtl/ibex_pmp_reset_pkg.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_darjeeling/top_darjeeling_jtag_id_pkg.core b/hw/top_darjeeling/top_darjeeling_jtag_id_pkg.core new file mode 100644 index 0000000000000..7de640bb979a5 --- /dev/null +++ b/hw/top_darjeeling/top_darjeeling_jtag_id_pkg.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: "lowrisc:constants:top_darjeeling_jtag_id_pkg" +description: "jtag id for top_darjeeling" +filesets: + files_rtl: + depend: + - "fileset_partner ? (partner:constants:top_darjeeling_jtag_id_pkg)" + files: + - "!fileset_partner ? (rtl/jtag_id_pkg.sv)" + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_darjeeling/top_darjeeling_padring.core b/hw/top_darjeeling/top_darjeeling_padring.core new file mode 100644 index 0000000000000..2b38e17ec0630 --- /dev/null +++ b/hw/top_darjeeling/top_darjeeling_padring.core @@ -0,0 +1,47 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:systems:top_darjeeling_padring:0.1" +description: "Chip-level padring instance for Darjeeling" + +filesets: + files_rtl: + depend: + - lowrisc:prim:mubi + - lowrisc:prim:pad_wrapper_pkg + - lowrisc:systems:top_darjeeling_pkg + - "!fileset_partner ? (lowrisc:systems:physical_pads)" + - "fileset_partner ? (partner:systems:physical_pads)" + files: + - rtl/padring.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/padring.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl diff --git a/hw/top_darjeeling/top_darjeeling_scan_role_pkg.core b/hw/top_darjeeling/top_darjeeling_scan_role_pkg.core new file mode 100644 index 0000000000000..526f71c3bdf73 --- /dev/null +++ b/hw/top_darjeeling/top_darjeeling_scan_role_pkg.core @@ -0,0 +1,42 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:systems:top_darjeeling_scan_role_pkg:0.1" +description: "Open-source place-holder for scanrole parameters for Darjeeling" + +filesets: + files_rtl: + depend: + - lowrisc:prim:pad_wrapper_pkg + files: + - rtl/scan_role_pkg.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl From 7eb4a0e5095a9d6dfe6585634a1c405f37e27a6c Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Fri, 15 Nov 2024 11:31:42 -0800 Subject: [PATCH 8/8] [hw,pinmux,rtl] Move signal definition outside of param block The mi/dio signals are used in both cases, hardware strap sampling enabled an not. Signed-off-by: Robert Schilling --- hw/ip_templates/pinmux/rtl/pinmux.sv.tpl | 8 ++++---- hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux.sv | 4 ++++ hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux.sv | 8 ++++---- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/hw/ip_templates/pinmux/rtl/pinmux.sv.tpl b/hw/ip_templates/pinmux/rtl/pinmux.sv.tpl index 28594c5e6a3e8..e9ba725094fdb 100644 --- a/hw/ip_templates/pinmux/rtl/pinmux.sv.tpl +++ b/hw/ip_templates/pinmux/rtl/pinmux.sv.tpl @@ -298,6 +298,10 @@ module pinmux assign hw2reg.mio_pad_attr[k].invert.d = mio_attr[k].invert; end + // Local versions of the input signals + logic [NMioPads-1:0] mio_out, mio_oe, mio_in; + logic [NDioPads-1:0] dio_out, dio_oe, dio_in; + % if enable_strap_sampling: ////////////////////////// @@ -338,10 +342,6 @@ module pinmux assign strap_en = strap_en_i; end - // Local versions of the input signals - logic [NMioPads-1:0] mio_out, mio_oe, mio_in; - logic [NDioPads-1:0] dio_out, dio_oe, dio_in; - // This module contains the strap sampling and JTAG mux. // Affected inputs are intercepted/tapped before they go to the pinmux // matrix. Likewise, affected outputs are intercepted/tapped after the diff --git a/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux.sv b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux.sv index 6826bc46ab1f5..bfad811ca4db5 100644 --- a/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux.sv +++ b/hw/top_darjeeling/ip_autogen/pinmux/rtl/pinmux.sv @@ -245,6 +245,10 @@ module pinmux assign hw2reg.mio_pad_attr[k].invert.d = mio_attr[k].invert; end + // Local versions of the input signals + logic [NMioPads-1:0] mio_out, mio_oe, mio_in; + logic [NDioPads-1:0] dio_out, dio_oe, dio_in; + // Just pass through these signals. assign { dio_out_o, mio_out_o } = { dio_out, mio_out }; assign { dio_oe_o , mio_oe_o } = { dio_oe, mio_oe }; diff --git a/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux.sv b/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux.sv index b24c590e6dce4..bd3d9212f3247 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux.sv +++ b/hw/top_earlgrey/ip_autogen/pinmux/rtl/pinmux.sv @@ -292,6 +292,10 @@ module pinmux assign hw2reg.mio_pad_attr[k].invert.d = mio_attr[k].invert; end + // Local versions of the input signals + logic [NMioPads-1:0] mio_out, mio_oe, mio_in; + logic [NDioPads-1:0] dio_out, dio_oe, dio_in; + ////////////////////////// // Strap Sampling Logic // @@ -331,10 +335,6 @@ module pinmux assign strap_en = strap_en_i; end - // Local versions of the input signals - logic [NMioPads-1:0] mio_out, mio_oe, mio_in; - logic [NDioPads-1:0] dio_out, dio_oe, dio_in; - // This module contains the strap sampling and JTAG mux. // Affected inputs are intercepted/tapped before they go to the pinmux // matrix. Likewise, affected outputs are intercepted/tapped after the